drivers/net/sunbmac.c

   1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
   2  * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
   3  *
   4  * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #include <linux/module.h>
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/fcntl.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/ioport.h>
  14 #include <linux/in.h>
  15 #include <linux/slab.h>
  16 #include <linux/string.h>
  17 #include <linux/delay.h>
  18 #include <linux/init.h>
  19 #include <linux/crc32.h>
  20 #include <linux/errno.h>
  21 #include <linux/ethtool.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/bitops.h>
  26
  27 #include <asm/auxio.h>
  28 #include <asm/byteorder.h>
  29 #include <asm/dma.h>
  30 #include <asm/idprom.h>
  31 #include <asm/io.h>
  32 #include <asm/openprom.h>
  33 #include <asm/oplib.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/sbus.h>
  36 #include <asm/system.h>
  37
  38 #include "sunbmac.h"
  39
  40 #define DRV_NAME        "sunbmac"
  41 #define DRV_VERSION     "2.0"
  42 #define DRV_RELDATE     "11/24/03"
  43 #define DRV_AUTHOR      "David S. Miller (davem@redhat.com)"
  44
  45 static char version[] __initdata =
  46         DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
  47
  48 MODULE_VERSION(DRV_VERSION);
  49 MODULE_AUTHOR(DRV_AUTHOR);
  50 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
  51 MODULE_LICENSE("GPL");
  52
  53 #undef DEBUG_PROBE
  54 #undef DEBUG_TX
  55 #undef DEBUG_IRQ
  56
  57 #ifdef DEBUG_PROBE
  58 #define DP(x)  printk x
  59 #else
  60 #define DP(x)
  61 #endif
  62
  63 #ifdef DEBUG_TX
  64 #define DTX(x)  printk x
  65 #else
  66 #define DTX(x)
  67 #endif
  68
  69 #ifdef DEBUG_IRQ
  70 #define DIRQ(x)  printk x
  71 #else
  72 #define DIRQ(x)
  73 #endif
  74
  75 #define DEFAULT_JAMSIZE    4 /* Toe jam */
  76
  77 #define QEC_RESET_TRIES 200
  78
  79 static int qec_global_reset(void __iomem *gregs)
  80 {
  81         int tries = QEC_RESET_TRIES;
  82
  83         sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
  84         while (--tries) {
  85                 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
  86                         udelay(20);
  87                         continue;
  88                 }
  89                 break;
  90         }
  91         if (tries)
  92                 return 0;
  93         printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
  94         return -1;
  95 }
  96
  97 static void qec_init(struct bigmac *bp)
  98 {
  99         void __iomem *gregs = bp->gregs;
 100         struct sbus_dev *qec_sdev = bp->qec_sdev;
 101         u8 bsizes = bp->bigmac_bursts;
 102         u32 regval;
 103
 104         /* 64byte bursts do not work at the moment, do
 105          * not even try to enable them.  -DaveM
 106          */
 107         if (bsizes & DMA_BURST32)
 108                 regval = GLOB_CTRL_B32;
 109         else
 110                 regval = GLOB_CTRL_B16;
 111         sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
 112         sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
 113
 114         /* All of memsize is given to bigmac. */
 115         sbus_writel(qec_sdev->reg_addrs[1].reg_size,
 116                     gregs + GLOB_MSIZE);
 117
 118         /* Half to the transmitter, half to the receiver. */
 119         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
 120                     gregs + GLOB_TSIZE);
 121         sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
 122                     gregs + GLOB_RSIZE);
 123 }
 124
 125 #define TX_RESET_TRIES     32
 126 #define RX_RESET_TRIES     32
 127
 128 static void bigmac_tx_reset(void __iomem *bregs)
 129 {
 130         int tries = TX_RESET_TRIES;
 131
 132         sbus_writel(0, bregs + BMAC_TXCFG);
 133
 134         /* The fifo threshold bit is read-only and does
 135          * not clear.  -DaveM
 136          */
 137         while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
 138                --tries != 0)
 139                 udelay(20);
 140
 141         if (!tries) {
 142                 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
 143                 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
 144                        sbus_readl(bregs + BMAC_TXCFG));
 145         }
 146 }
 147
 148 static void bigmac_rx_reset(void __iomem *bregs)
 149 {
 150         int tries = RX_RESET_TRIES;
 151
 152         sbus_writel(0, bregs + BMAC_RXCFG);
 153         while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
 154                 udelay(20);
 155
 156         if (!tries) {
 157                 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
 158                 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
 159                        sbus_readl(bregs + BMAC_RXCFG));
 160         }
 161 }
 162
 163 /* Reset the transmitter and receiver. */
 164 static void bigmac_stop(struct bigmac *bp)
 165 {
 166         bigmac_tx_reset(bp->bregs);
 167         bigmac_rx_reset(bp->bregs);
 168 }
 169
 170 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
 171 {
 172         struct net_device_stats *stats = &bp->enet_stats;
 173
 174         stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
 175         sbus_writel(0, bregs + BMAC_RCRCECTR);
 176
 177         stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
 178         sbus_writel(0, bregs + BMAC_UNALECTR);
 179
 180         stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
 181         sbus_writel(0, bregs + BMAC_GLECTR);
 182
 183         stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
 184
 185         stats->collisions +=
 186                 (sbus_readl(bregs + BMAC_EXCTR) +
 187                  sbus_readl(bregs + BMAC_LTCTR));
 188         sbus_writel(0, bregs + BMAC_EXCTR);
 189         sbus_writel(0, bregs + BMAC_LTCTR);
 190 }
 191
 192 static void bigmac_clean_rings(struct bigmac *bp)
 193 {
 194         int i;
 195
 196         for (i = 0; i < RX_RING_SIZE; i++) {
 197                 if (bp->rx_skbs[i] != NULL) {
 198                         dev_kfree_skb_any(bp->rx_skbs[i]);
 199                         bp->rx_skbs[i] = NULL;
 200                 }
 201         }
 202
 203         for (i = 0; i < TX_RING_SIZE; i++) {
 204                 if (bp->tx_skbs[i] != NULL) {
 205                         dev_kfree_skb_any(bp->tx_skbs[i]);
 206                         bp->tx_skbs[i] = NULL;
 207                 }
 208         }
 209 }
 210
 211 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
 212 {
 213         struct bmac_init_block *bb = bp->bmac_block;
 214         struct net_device *dev = bp->dev;
 215         int i;
 216         gfp_t gfp_flags = GFP_KERNEL;
 217
 218         if (from_irq || in_interrupt())
 219                 gfp_flags = GFP_ATOMIC;
 220
 221         bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
 222
 223         /* Free any skippy bufs left around in the rings. */
 224         bigmac_clean_rings(bp);
 225
 226         /* Now get new skbufs for the receive ring. */
 227         for (i = 0; i < RX_RING_SIZE; i++) {
 228                 struct sk_buff *skb;
 229
 230                 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
 231                 if (!skb)
 232                         continue;
 233
 234                 bp->rx_skbs[i] = skb;
 235                 skb->dev = dev;
 236
 237                 /* Because we reserve afterwards. */
 238                 skb_put(skb, ETH_FRAME_LEN);
 239                 skb_reserve(skb, 34);
 240
 241                 bb->be_rxd[i].rx_addr =
 242                         sbus_map_single(bp->bigmac_sdev, skb->data,
 243                                         RX_BUF_ALLOC_SIZE - 34,
 244                                         SBUS_DMA_FROMDEVICE);
 245                 bb->be_rxd[i].rx_flags =
 246                         (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
 247         }
 248
 249         for (i = 0; i < TX_RING_SIZE; i++)
 250                 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
 251 }
 252
 253 #define MGMT_CLKON  (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
 254 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
 255
 256 static void idle_transceiver(void __iomem *tregs)
 257 {
 258         int i = 20;
 259
 260         while (i--) {
 261                 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
 262                 sbus_readl(tregs + TCVR_MPAL);
 263                 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
 264                 sbus_readl(tregs + TCVR_MPAL);
 265         }
 266 }
 267
 268 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
 269 {
 270         if (bp->tcvr_type == internal) {
 271                 bit = (bit & 1) << 3;
 272                 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
 273                             tregs + TCVR_MPAL);
 274                 sbus_readl(tregs + TCVR_MPAL);
 275                 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
 276                             tregs + TCVR_MPAL);
 277                 sbus_readl(tregs + TCVR_MPAL);
 278         } else if (bp->tcvr_type == external) {
 279                 bit = (bit & 1) << 2;
 280                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
 281                             tregs + TCVR_MPAL);
 282                 sbus_readl(tregs + TCVR_MPAL);
 283                 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
 284                             tregs + TCVR_MPAL);
 285                 sbus_readl(tregs + TCVR_MPAL);
 286         } else {
 287                 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
 288         }
 289 }
 290
 291 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
 292 {
 293         int retval = 0;
 294
 295         if (bp->tcvr_type == internal) {
 296                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
 297                 sbus_readl(tregs + TCVR_MPAL);
 298                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
 299                             tregs + TCVR_MPAL);
 300                 sbus_readl(tregs + TCVR_MPAL);
 301                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
 302         } else if (bp->tcvr_type == external) {
 303                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
 304                 sbus_readl(tregs + TCVR_MPAL);
 305                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
 306                 sbus_readl(tregs + TCVR_MPAL);
 307                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
 308         } else {
 309                 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
 310         }
 311         return retval;
 312 }
 313
 314 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
 315 {
 316         int retval = 0;
 317
 318         if (bp->tcvr_type == internal) {
 319                 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
 320                 sbus_readl(tregs + TCVR_MPAL);
 321                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
 322                 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
 323                 sbus_readl(tregs + TCVR_MPAL);
 324         } else if (bp->tcvr_type == external) {
 325                 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
 326                 sbus_readl(tregs + TCVR_MPAL);
 327                 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
 328                 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
 329                 sbus_readl(tregs + TCVR_MPAL);
 330         } else {
 331                 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
 332         }
 333         return retval;
 334 }
 335
 336 static void put_tcvr_byte(struct bigmac *bp,
 337                           void __iomem *tregs,
 338                           unsigned int byte)
 339 {
 340         int shift = 4;
 341
 342         do {
 343                 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
 344                 shift -= 1;
 345         } while (shift >= 0);
 346 }
 347
 348 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
 349                               int reg, unsigned short val)
 350 {
 351         int shift;
 352
 353         reg &= 0xff;
 354         val &= 0xffff;
 355         switch(bp->tcvr_type) {
 356         case internal:
 357         case external:
 358                 break;
 359
 360         default:
 361                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
 362                 return;
 363         };
 364
 365         idle_transceiver(tregs);
 366         write_tcvr_bit(bp, tregs, 0);
 367         write_tcvr_bit(bp, tregs, 1);
 368         write_tcvr_bit(bp, tregs, 0);
 369         write_tcvr_bit(bp, tregs, 1);
 370
 371         put_tcvr_byte(bp, tregs,
 372                       ((bp->tcvr_type == internal) ?
 373                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
 374
 375         put_tcvr_byte(bp, tregs, reg);
 376
 377         write_tcvr_bit(bp, tregs, 1);
 378         write_tcvr_bit(bp, tregs, 0);
 379
 380         shift = 15;
 381         do {
 382                 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
 383                 shift -= 1;
 384         } while (shift >= 0);
 385 }
 386
 387 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
 388                                        void __iomem *tregs,
 389                                        int reg)
 390 {
 391         unsigned short retval = 0;
 392
 393         reg &= 0xff;
 394         switch(bp->tcvr_type) {
 395         case internal:
 396         case external:
 397                 break;
 398
 399         default:
 400                 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
 401                 return 0xffff;
 402         };
 403
 404         idle_transceiver(tregs);
 405         write_tcvr_bit(bp, tregs, 0);
 406         write_tcvr_bit(bp, tregs, 1);
 407         write_tcvr_bit(bp, tregs, 1);
 408         write_tcvr_bit(bp, tregs, 0);
 409
 410         put_tcvr_byte(bp, tregs,
 411                       ((bp->tcvr_type == internal) ?
 412                        BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
 413
 414         put_tcvr_byte(bp, tregs, reg);
 415
 416         if (bp->tcvr_type == external) {
 417                 int shift = 15;
 418
 419                 (void) read_tcvr_bit2(bp, tregs);
 420                 (void) read_tcvr_bit2(bp, tregs);
 421
 422                 do {
 423                         int tmp;
 424
 425                         tmp = read_tcvr_bit2(bp, tregs);
 426                         retval |= ((tmp & 1) << shift);
 427                         shift -= 1;
 428                 } while (shift >= 0);
 429
 430                 (void) read_tcvr_bit2(bp, tregs);
 431                 (void) read_tcvr_bit2(bp, tregs);
 432                 (void) read_tcvr_bit2(bp, tregs);
 433         } else {
 434                 int shift = 15;
 435
 436                 (void) read_tcvr_bit(bp, tregs);
 437                 (void) read_tcvr_bit(bp, tregs);
 438
 439                 do {
 440                         int tmp;
 441
 442                         tmp = read_tcvr_bit(bp, tregs);
 443                         retval |= ((tmp & 1) << shift);
 444                         shift -= 1;
 445                 } while (shift >= 0);
 446
 447                 (void) read_tcvr_bit(bp, tregs);
 448                 (void) read_tcvr_bit(bp, tregs);
 449                 (void) read_tcvr_bit(bp, tregs);
 450         }
 451         return retval;
 452 }
 453
 454 static void bigmac_tcvr_init(struct bigmac *bp)
 455 {
 456         void __iomem *tregs = bp->tregs;
 457         u32 mpal;
 458
 459         idle_transceiver(tregs);
 460         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
 461                     tregs + TCVR_MPAL);
 462         sbus_readl(tregs + TCVR_MPAL);
 463
 464         /* Only the bit for the present transceiver (internal or
 465          * external) will stick, set them both and see what stays.
 466          */
 467         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
 468         sbus_readl(tregs + TCVR_MPAL);
 469         udelay(20);
 470
 471         mpal = sbus_readl(tregs + TCVR_MPAL);
 472         if (mpal & MGMT_PAL_EXT_MDIO) {
 473                 bp->tcvr_type = external;
 474                 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
 475                             tregs + TCVR_TPAL);
 476                 sbus_readl(tregs + TCVR_TPAL);
 477         } else if (mpal & MGMT_PAL_INT_MDIO) {
 478                 bp->tcvr_type = internal;
 479                 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
 480                               TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
 481                             tregs + TCVR_TPAL);
 482                 sbus_readl(tregs + TCVR_TPAL);
 483         } else {
 484                 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
 485                        "external MDIO available!\n");
 486                 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
 487                        sbus_readl(tregs + TCVR_MPAL),
 488                        sbus_readl(tregs + TCVR_TPAL));
 489         }
 490 }
 491
 492 static int bigmac_init_hw(struct bigmac *, int);
 493
 494 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
 495 {
 496         if (bp->sw_bmcr & BMCR_SPEED100) {
 497                 int timeout;
 498
 499                 /* Reset the PHY. */
 500                 bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
 501                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 502                 bp->sw_bmcr     = (BMCR_RESET);
 503                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 504
 505                 timeout = 64;
 506                 while (--timeout) {
 507                         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 508                         if ((bp->sw_bmcr & BMCR_RESET) == 0)
 509                                 break;
 510                         udelay(20);
 511                 }
 512                 if (timeout == 0)
 513                         printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
 514
 515                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 516
 517                 /* Now we try 10baseT. */
 518                 bp->sw_bmcr &= ~(BMCR_SPEED100);
 519                 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 520                 return 0;
 521         }
 522
 523         /* We've tried them all. */
 524         return -1;
 525 }
 526
 527 static void bigmac_timer(unsigned long data)
 528 {
 529         struct bigmac *bp = (struct bigmac *) data;
 530         void __iomem *tregs = bp->tregs;
 531         int restart_timer = 0;
 532
 533         bp->timer_ticks++;
 534         if (bp->timer_state == ltrywait) {
 535                 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
 536                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 537                 if (bp->sw_bmsr & BMSR_LSTATUS) {
 538                         printk(KERN_INFO "%s: Link is now up at %s.\n",
 539                                bp->dev->name,
 540                                (bp->sw_bmcr & BMCR_SPEED100) ?
 541                                "100baseT" : "10baseT");
 542                         bp->timer_state = asleep;
 543                         restart_timer = 0;
 544                 } else {
 545                         if (bp->timer_ticks >= 4) {
 546                                 int ret;
 547
 548                                 ret = try_next_permutation(bp, tregs);
 549                                 if (ret == -1) {
 550                                         printk(KERN_ERR "%s: Link down, cable problem?\n",
 551                                                bp->dev->name);
 552                                         ret = bigmac_init_hw(bp, 0);
 553                                         if (ret) {
 554                                                 printk(KERN_ERR "%s: Error, cannot re-init the "
 555                                                        "BigMAC.\n", bp->dev->name);
 556                                         }
 557                                         return;
 558                                 }
 559                                 bp->timer_ticks = 0;
 560                                 restart_timer = 1;
 561                         } else {
 562                                 restart_timer = 1;
 563                         }
 564                 }
 565         } else {
 566                 /* Can't happens.... */
 567                 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
 568                        bp->dev->name);
 569                 restart_timer = 0;
 570                 bp->timer_ticks = 0;
 571                 bp->timer_state = asleep; /* foo on you */
 572         }
 573
 574         if (restart_timer != 0) {
 575                 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
 576                 add_timer(&bp->bigmac_timer);
 577         }
 578 }
 579
 580 /* Well, really we just force the chip into 100baseT then
 581  * 10baseT, each time checking for a link status.
 582  */
 583 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
 584 {
 585         void __iomem *tregs = bp->tregs;
 586         int timeout;
 587
 588         /* Grab new software copies of PHY registers. */
 589         bp->sw_bmsr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
 590         bp->sw_bmcr     = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 591
 592         /* Reset the PHY. */
 593         bp->sw_bmcr     = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
 594         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 595         bp->sw_bmcr     = (BMCR_RESET);
 596         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 597
 598         timeout = 64;
 599         while (--timeout) {
 600                 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 601                 if ((bp->sw_bmcr & BMCR_RESET) == 0)
 602                         break;
 603                 udelay(20);
 604         }
 605         if (timeout == 0)
 606                 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
 607
 608         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
 609
 610         /* First we try 100baseT. */
 611         bp->sw_bmcr |= BMCR_SPEED100;
 612         bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
 613
 614         bp->timer_state = ltrywait;
 615         bp->timer_ticks = 0;
 616         bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
 617         bp->bigmac_timer.data = (unsigned long) bp;
 618         bp->bigmac_timer.function = &bigmac_timer;
 619         add_timer(&bp->bigmac_timer);
 620 }
 621
 622 static int bigmac_init_hw(struct bigmac *bp, int from_irq)
 623 {
 624         void __iomem *gregs        = bp->gregs;
 625         void __iomem *cregs        = bp->creg;
 626         void __iomem *bregs        = bp->bregs;
 627         unsigned char *e = &bp->dev->dev_addr[0];
 628
 629         /* Latch current counters into statistics. */
 630         bigmac_get_counters(bp, bregs);
 631
 632         /* Reset QEC. */
 633         qec_global_reset(gregs);
 634
 635         /* Init QEC. */
 636         qec_init(bp);
 637
 638         /* Alloc and reset the tx/rx descriptor chains. */
 639         bigmac_init_rings(bp, from_irq);
 640
 641         /* Initialize the PHY. */
 642         bigmac_tcvr_init(bp);
 643
 644         /* Stop transmitter and receiver. */
 645         bigmac_stop(bp);
 646
 647         /* Set hardware ethernet address. */
 648         sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
 649         sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
 650         sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
 651
 652         /* Clear the hash table until mc upload occurs. */
 653         sbus_writel(0, bregs + BMAC_HTABLE3);
 654         sbus_writel(0, bregs + BMAC_HTABLE2);
 655         sbus_writel(0, bregs + BMAC_HTABLE1);
 656         sbus_writel(0, bregs + BMAC_HTABLE0);
 657
 658         /* Enable Big Mac hash table filter. */
 659         sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
 660                     bregs + BMAC_RXCFG);
 661         udelay(20);
 662
 663         /* Ok, configure the Big Mac transmitter. */
 664         sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
 665
 666         /* The HME docs recommend to use the 10LSB of our MAC here. */
 667         sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
 668                     bregs + BMAC_RSEED);
 669
 670         /* Enable the output drivers no matter what. */
 671         sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
 672                     bregs + BMAC_XIFCFG);
 673
 674         /* Tell the QEC where the ring descriptors are. */
 675         sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
 676                     cregs + CREG_RXDS);
 677         sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
 678                     cregs + CREG_TXDS);
 679
 680         /* Setup the FIFO pointers into QEC local memory. */
 681         sbus_writel(0, cregs + CREG_RXRBUFPTR);
 682         sbus_writel(0, cregs + CREG_RXWBUFPTR);
 683         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
 684                     cregs + CREG_TXRBUFPTR);
 685         sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
 686                     cregs + CREG_TXWBUFPTR);
 687
 688         /* Tell bigmac what interrupts we don't want to hear about. */
 689         sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
 690                     bregs + BMAC_IMASK);
 691
 692         /* Enable the various other irq's. */
 693         sbus_writel(0, cregs + CREG_RIMASK);
 694         sbus_writel(0, cregs + CREG_TIMASK);
 695         sbus_writel(0, cregs + CREG_QMASK);
 696         sbus_writel(0, cregs + CREG_BMASK);
 697
 698         /* Set jam size to a reasonable default. */
 699         sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
 700
 701         /* Clear collision counter. */
 702         sbus_writel(0, cregs + CREG_CCNT);
 703
 704         /* Enable transmitter and receiver. */
 705         sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
 706                     bregs + BMAC_TXCFG);
 707         sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
 708                     bregs + BMAC_RXCFG);
 709
 710         /* Ok, start detecting link speed/duplex. */
 711         bigmac_begin_auto_negotiation(bp);
 712
 713         /* Success. */
 714         return 0;
 715 }
 716
 717 /* Error interrupts get sent here. */
 718 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
 719 {
 720         printk(KERN_ERR "bigmac_is_medium_rare: ");
 721         if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
 722                 if (qec_status & GLOB_STAT_ER)
 723                         printk("QEC_ERROR, ");
 724                 if (qec_status & GLOB_STAT_BM)
 725                         printk("QEC_BMAC_ERROR, ");
 726         }
 727         if (bmac_status & CREG_STAT_ERRORS) {
 728                 if (bmac_status & CREG_STAT_BERROR)
 729                         printk("BMAC_ERROR, ");
 730                 if (bmac_status & CREG_STAT_TXDERROR)
 731                         printk("TXD_ERROR, ");
 732                 if (bmac_status & CREG_STAT_TXLERR)
 733                         printk("TX_LATE_ERROR, ");
 734                 if (bmac_status & CREG_STAT_TXPERR)
 735                         printk("TX_PARITY_ERROR, ");
 736                 if (bmac_status & CREG_STAT_TXSERR)
 737                         printk("TX_SBUS_ERROR, ");
 738
 739                 if (bmac_status & CREG_STAT_RXDROP)
 740                         printk("RX_DROP_ERROR, ");
 741
 742                 if (bmac_status & CREG_STAT_RXSMALL)
 743                         printk("RX_SMALL_ERROR, ");
 744                 if (bmac_status & CREG_STAT_RXLERR)
 745                         printk("RX_LATE_ERROR, ");
 746                 if (bmac_status & CREG_STAT_RXPERR)
 747                         printk("RX_PARITY_ERROR, ");
 748                 if (bmac_status & CREG_STAT_RXSERR)
 749                         printk("RX_SBUS_ERROR, ");
 750         }
 751
 752         printk(" RESET\n");
 753         bigmac_init_hw(bp, 1);
 754 }
 755
 756 /* BigMAC transmit complete service routines. */
 757 static void bigmac_tx(struct bigmac *bp)
 758 {
 759         struct be_txd *txbase = &bp->bmac_block->be_txd[0];
 760         struct net_device *dev = bp->dev;
 761         int elem;
 762
 763         spin_lock(&bp->lock);
 764
 765         elem = bp->tx_old;
 766         DTX(("bigmac_tx: tx_old[%d] ", elem));
 767         while (elem != bp->tx_new) {
 768                 struct sk_buff *skb;
 769                 struct be_txd *this = &txbase[elem];
 770
 771                 DTX(("this(%p) [flags(%08x)addr(%08x)]",
 772                      this, this->tx_flags, this->tx_addr));
 773
 774                 if (this->tx_flags & TXD_OWN)
 775                         break;
 776                 skb = bp->tx_skbs[elem];
 777                 bp->enet_stats.tx_packets++;
 778                 bp->enet_stats.tx_bytes += skb->len;
 779                 sbus_unmap_single(bp->bigmac_sdev,
 780                                   this->tx_addr, skb->len,
 781                                   SBUS_DMA_TODEVICE);
 782
 783                 DTX(("skb(%p) ", skb));
 784                 bp->tx_skbs[elem] = NULL;
 785                 dev_kfree_skb_irq(skb);
 786
 787                 elem = NEXT_TX(elem);
 788         }
 789         DTX((" DONE, tx_old=%d\n", elem));
 790         bp->tx_old = elem;
 791
 792         if (netif_queue_stopped(dev) &&
 793             TX_BUFFS_AVAIL(bp) > 0)
 794                 netif_wake_queue(bp->dev);
 795
 796         spin_unlock(&bp->lock);
 797 }
 798
 799 /* BigMAC receive complete service routines. */
 800 static void bigmac_rx(struct bigmac *bp)
 801 {
 802         struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
 803         struct be_rxd *this;
 804         int elem = bp->rx_new, drops = 0;
 805         u32 flags;
 806
 807         this = &rxbase[elem];
 808         while (!((flags = this->rx_flags) & RXD_OWN)) {
 809                 struct sk_buff *skb;
 810                 int len = (flags & RXD_LENGTH); /* FCS not included */
 811
 812                 /* Check for errors. */
 813                 if (len < ETH_ZLEN) {
 814                         bp->enet_stats.rx_errors++;
 815                         bp->enet_stats.rx_length_errors++;
 816
 817         drop_it:
 818                         /* Return it to the BigMAC. */
 819                         bp->enet_stats.rx_dropped++;
 820                         this->rx_flags =
 821                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
 822                         goto next;
 823                 }
 824                 skb = bp->rx_skbs[elem];
 825                 if (len > RX_COPY_THRESHOLD) {
 826                         struct sk_buff *new_skb;
 827
 828                         /* Now refill the entry, if we can. */
 829                         new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
 830                         if (new_skb == NULL) {
 831                                 drops++;
 832                                 goto drop_it;
 833                         }
 834                         sbus_unmap_single(bp->bigmac_sdev,
 835                                           this->rx_addr,
 836                                           RX_BUF_ALLOC_SIZE - 34,
 837                                           SBUS_DMA_FROMDEVICE);
 838                         bp->rx_skbs[elem] = new_skb;
 839                         new_skb->dev = bp->dev;
 840                         skb_put(new_skb, ETH_FRAME_LEN);
 841                         skb_reserve(new_skb, 34);
 842                         this->rx_addr = sbus_map_single(bp->bigmac_sdev,
 843                                                         new_skb->data,
 844                                                         RX_BUF_ALLOC_SIZE - 34,
 845                                                         SBUS_DMA_FROMDEVICE);
 846                         this->rx_flags =
 847                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
 848
 849                         /* Trim the original skb for the netif. */
 850                         skb_trim(skb, len);
 851                 } else {
 852                         struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
 853
 854                         if (copy_skb == NULL) {
 855                                 drops++;
 856                                 goto drop_it;
 857                         }
 858                         copy_skb->dev = bp->dev;
 859                         skb_reserve(copy_skb, 2);
 860                         skb_put(copy_skb, len);
 861                         sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
 862                                                      this->rx_addr, len,
 863                                                      SBUS_DMA_FROMDEVICE);
 864                         eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
 865                         sbus_dma_sync_single_for_device(bp->bigmac_sdev,
 866                                                         this->rx_addr, len,
 867                                                         SBUS_DMA_FROMDEVICE);
 868
 869                         /* Reuse original ring buffer. */
 870                         this->rx_flags =
 871                                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
 872
 873                         skb = copy_skb;
 874                 }
 875
 876                 /* No checksums done by the BigMAC ;-( */
 877                 skb->protocol = eth_type_trans(skb, bp->dev);
 878                 netif_rx(skb);
 879                 bp->dev->last_rx = jiffies;
 880                 bp->enet_stats.rx_packets++;
 881                 bp->enet_stats.rx_bytes += len;
 882         next:
 883                 elem = NEXT_RX(elem);
 884                 this = &rxbase[elem];
 885         }
 886         bp->rx_new = elem;
 887         if (drops)
 888                 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
 889 }
 890
 891 static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 892 {
 893         struct bigmac *bp = (struct bigmac *) dev_id;
 894         u32 qec_status, bmac_status;
 895
 896         DIRQ(("bigmac_interrupt: "));
 897
 898         /* Latch status registers now. */
 899         bmac_status = sbus_readl(bp->creg + CREG_STAT);
 900         qec_status = sbus_readl(bp->gregs + GLOB_STAT);
 901
 902         DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
 903         if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
 904            (bmac_status & CREG_STAT_ERRORS))
 905                 bigmac_is_medium_rare(bp, qec_status, bmac_status);
 906
 907         if (bmac_status & CREG_STAT_TXIRQ)
 908                 bigmac_tx(bp);
 909
 910         if (bmac_status & CREG_STAT_RXIRQ)
 911                 bigmac_rx(bp);
 912
 913         return IRQ_HANDLED;
 914 }
 915
 916 static int bigmac_open(struct net_device *dev)
 917 {
 918         struct bigmac *bp = (struct bigmac *) dev->priv;
 919         int ret;
 920
 921         ret = request_irq(dev->irq, &bigmac_interrupt, IRQF_SHARED, dev->name, bp);
 922         if (ret) {
 923                 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
 924                 return ret;
 925         }
 926         init_timer(&bp->bigmac_timer);
 927         ret = bigmac_init_hw(bp, 0);
 928         if (ret)
 929                 free_irq(dev->irq, bp);
 930         return ret;
 931 }
 932
 933 static int bigmac_close(struct net_device *dev)
 934 {
 935         struct bigmac *bp = (struct bigmac *) dev->priv;
 936
 937         del_timer(&bp->bigmac_timer);
 938         bp->timer_state = asleep;
 939         bp->timer_ticks = 0;
 940
 941         bigmac_stop(bp);
 942         bigmac_clean_rings(bp);
 943         free_irq(dev->irq, bp);
 944         return 0;
 945 }
 946
 947 static void bigmac_tx_timeout(struct net_device *dev)
 948 {
 949         struct bigmac *bp = (struct bigmac *) dev->priv;
 950
 951         bigmac_init_hw(bp, 0);
 952         netif_wake_queue(dev);
 953 }
 954
 955 /* Put a packet on the wire. */
 956 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 957 {
 958         struct bigmac *bp = (struct bigmac *) dev->priv;
 959         int len, entry;
 960         u32 mapping;
 961
 962         len = skb->len;
 963         mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
 964
 965         /* Avoid a race... */
 966         spin_lock_irq(&bp->lock);
 967         entry = bp->tx_new;
 968         DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
 969         bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
 970         bp->tx_skbs[entry] = skb;
 971         bp->bmac_block->be_txd[entry].tx_addr = mapping;
 972         bp->bmac_block->be_txd[entry].tx_flags =
 973                 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
 974         bp->tx_new = NEXT_TX(entry);
 975         if (TX_BUFFS_AVAIL(bp) <= 0)
 976                 netif_stop_queue(dev);
 977         spin_unlock_irq(&bp->lock);
 978
 979         /* Get it going. */
 980         sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
 981
 982
 983         dev->trans_start = jiffies;
 984
 985         return 0;
 986 }
 987
 988 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
 989 {
 990         struct bigmac *bp = (struct bigmac *) dev->priv;
 991
 992         bigmac_get_counters(bp, bp->bregs);
 993         return &bp->enet_stats;
 994 }
 995
 996 static void bigmac_set_multicast(struct net_device *dev)
 997 {
 998         struct bigmac *bp = (struct bigmac *) dev->priv;
 999         void __iomem *bregs = bp->bregs;
1000         struct dev_mc_list *dmi = dev->mc_list;
1001         char *addrs;
1002         int i;
1003         u32 tmp, crc;
1004
1005         /* Disable the receiver.  The bit self-clears when
1006          * the operation is complete.
1007          */
1008         tmp = sbus_readl(bregs + BMAC_RXCFG);
1009         tmp &= ~(BIGMAC_RXCFG_ENABLE);
1010         sbus_writel(tmp, bregs + BMAC_RXCFG);
1011         while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1012                 udelay(20);
1013
1014         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1015                 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1016                 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1017                 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1018                 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1019         } else if (dev->flags & IFF_PROMISC) {
1020                 tmp = sbus_readl(bregs + BMAC_RXCFG);
1021                 tmp |= BIGMAC_RXCFG_PMISC;
1022                 sbus_writel(tmp, bregs + BMAC_RXCFG);
1023         } else {
1024                 u16 hash_table[4];
1025
1026                 for (i = 0; i < 4; i++)
1027                         hash_table[i] = 0;
1028
1029                 for (i = 0; i < dev->mc_count; i++) {
1030                         addrs = dmi->dmi_addr;
1031                         dmi = dmi->next;
1032
1033                         if (!(*addrs & 1))
1034                                 continue;
1035
1036                         crc = ether_crc_le(6, addrs);
1037                         crc >>= 26;
1038                         hash_table[crc >> 4] |= 1 << (crc & 0xf);
1039                 }
1040                 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1041                 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1042                 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1043                 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1044         }
1045
1046         /* Re-enable the receiver. */
1047         tmp = sbus_readl(bregs + BMAC_RXCFG);
1048         tmp |= BIGMAC_RXCFG_ENABLE;
1049         sbus_writel(tmp, bregs + BMAC_RXCFG);
1050 }
1051
1052 /* Ethtool support... */
1053 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1054 {
1055         struct bigmac *bp = dev->priv;
1056
1057         strcpy(info->driver, "sunbmac");
1058         strcpy(info->version, "2.0");
1059         sprintf(info->bus_info, "SBUS:%d",
1060                 bp->qec_sdev->slot);
1061 }
1062
1063 static u32 bigmac_get_link(struct net_device *dev)
1064 {
1065         struct bigmac *bp = dev->priv;
1066
1067         spin_lock_irq(&bp->lock);
1068         bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
1069         spin_unlock_irq(&bp->lock);
1070
1071         return (bp->sw_bmsr & BMSR_LSTATUS);
1072 }
1073
1074 static const struct ethtool_ops bigmac_ethtool_ops = {
1075         .get_drvinfo            = bigmac_get_drvinfo,
1076         .get_link               = bigmac_get_link,
1077 };
1078
1079 static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
1080 {
1081         struct net_device *dev;
1082         static int version_printed;
1083         struct bigmac *bp;
1084         u8 bsizes, bsizes_more;
1085         int i;
1086
1087         /* Get a new device struct for this interface. */
1088         dev = alloc_etherdev(sizeof(struct bigmac));
1089         if (!dev)
1090                 return -ENOMEM;
1091         SET_MODULE_OWNER(dev);
1092
1093         if (version_printed++ == 0)
1094                 printk(KERN_INFO "%s", version);
1095
1096         dev->base_addr = (long) qec_sdev;
1097         for (i = 0; i < 6; i++)
1098                 dev->dev_addr[i] = idprom->id_ethaddr[i];
1099
1100         /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1101         bp = dev->priv;
1102         bp->qec_sdev = qec_sdev;
1103         bp->bigmac_sdev = qec_sdev->child;
1104
1105         SET_NETDEV_DEV(dev, &bp->bigmac_sdev->ofdev.dev);
1106
1107         spin_lock_init(&bp->lock);
1108
1109         /* Verify the registers we expect, are actually there. */
1110         if ((bp->bigmac_sdev->num_registers != 3) ||
1111            (bp->qec_sdev->num_registers != 2)) {
1112                 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1113                        bp->qec_sdev->num_registers,
1114                        bp->bigmac_sdev->num_registers);
1115                 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1116                 goto fail_and_cleanup;
1117         }
1118
1119         /* Map in QEC global control registers. */
1120         bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1121                                  GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1122         if (!bp->gregs) {
1123                 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1124                 goto fail_and_cleanup;
1125         }
1126
1127         /* Make sure QEC is in BigMAC mode. */
1128         if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1129                 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1130                 goto fail_and_cleanup;
1131         }
1132
1133         /* Reset the QEC. */
1134         if (qec_global_reset(bp->gregs))
1135                 goto fail_and_cleanup;
1136
1137         /* Get supported SBUS burst sizes. */
1138         bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1139                                     "burst-sizes",
1140                                     0xff);
1141
1142         bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1143                                          "burst-sizes",
1144                                          0xff);
1145
1146         bsizes &= 0xff;
1147         if (bsizes_more != 0xff)
1148                 bsizes &= bsizes_more;
1149         if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1150             (bsizes & DMA_BURST32) == 0)
1151                 bsizes = (DMA_BURST32 - 1);
1152         bp->bigmac_bursts = bsizes;
1153
1154         /* Perform QEC initialization. */
1155         qec_init(bp);
1156
1157         /* Map in the BigMAC channel registers. */
1158         bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1159                                 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1160         if (!bp->creg) {
1161                 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1162                 goto fail_and_cleanup;
1163         }
1164
1165         /* Map in the BigMAC control registers. */
1166         bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1167                                  BMAC_REG_SIZE, "BigMAC Primary Regs");
1168         if (!bp->bregs) {
1169                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1170                 goto fail_and_cleanup;
1171         }
1172
1173         /* Map in the BigMAC transceiver registers, this is how you poke at
1174          * the BigMAC's PHY.
1175          */
1176         bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1177                                  TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1178         if (!bp->tregs) {
1179                 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1180                 goto fail_and_cleanup;
1181         }
1182
1183         /* Stop the BigMAC. */
1184         bigmac_stop(bp);
1185
1186         /* Allocate transmit/receive descriptor DVMA block. */
1187         bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1188                                                PAGE_SIZE,
1189                                                &bp->bblock_dvma);
1190         if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1191                 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1192                 goto fail_and_cleanup;
1193         }
1194
1195         /* Get the board revision of this BigMAC. */
1196         bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1197                                            "board-version", 1);
1198
1199         /* Init auto-negotiation timer state. */
1200         init_timer(&bp->bigmac_timer);
1201         bp->timer_state = asleep;
1202         bp->timer_ticks = 0;
1203
1204         /* Backlink to generic net device struct. */
1205         bp->dev = dev;
1206
1207         /* Set links to our BigMAC open and close routines. */
1208         dev->open = &bigmac_open;
1209         dev->stop = &bigmac_close;
1210         dev->hard_start_xmit = &bigmac_start_xmit;
1211         dev->ethtool_ops = &bigmac_ethtool_ops;
1212
1213         /* Set links to BigMAC statistic and multi-cast loading code. */
1214         dev->get_stats = &bigmac_get_stats;
1215         dev->set_multicast_list = &bigmac_set_multicast;
1216
1217         dev->tx_timeout = &bigmac_tx_timeout;
1218         dev->watchdog_timeo = 5*HZ;
1219
1220         /* Finish net device registration. */
1221         dev->irq = bp->bigmac_sdev->irqs[0];
1222         dev->dma = 0;
1223
1224         if (register_netdev(dev)) {
1225                 printk(KERN_ERR "BIGMAC: Cannot register device.\n");
1226                 goto fail_and_cleanup;
1227         }
1228
1229         dev_set_drvdata(&bp->bigmac_sdev->ofdev.dev, bp);
1230
1231         printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1232         for (i = 0; i < 6; i++)
1233                 printk("%2.2x%c", dev->dev_addr[i],
1234                        i == 5 ? ' ' : ':');
1235         printk("\n");
1236
1237         return 0;
1238
1239 fail_and_cleanup:
1240         /* Something went wrong, undo whatever we did so far. */
1241         /* Free register mappings if any. */
1242         if (bp->gregs)
1243                 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1244         if (bp->creg)
1245                 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1246         if (bp->bregs)
1247                 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1248         if (bp->tregs)
1249                 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1250
1251         if (bp->bmac_block)
1252                 sbus_free_consistent(bp->bigmac_sdev,
1253                                      PAGE_SIZE,
1254                                      bp->bmac_block,
1255                                      bp->bblock_dvma);
1256
1257         /* This also frees the co-located 'dev->priv' */
1258         free_netdev(dev);
1259         return -ENODEV;
1260 }
1261
1262 /* QEC can be the parent of either QuadEthernet or
1263  * a BigMAC.  We want the latter.
1264  */
1265 static int __devinit bigmac_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1266 {
1267         struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1268         struct device_node *dp = dev->node;
1269
1270         if (!strcmp(dp->name, "be"))
1271                 sdev = sdev->parent;
1272
1273         return bigmac_ether_init(sdev);
1274 }
1275
1276 static int __devexit bigmac_sbus_remove(struct of_device *dev)
1277 {
1278         struct bigmac *bp = dev_get_drvdata(&dev->dev);
1279         struct net_device *net_dev = bp->dev;
1280
1281         unregister_netdevice(net_dev);
1282
1283         sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1284         sbus_iounmap(bp->creg, CREG_REG_SIZE);
1285         sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1286         sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1287         sbus_free_consistent(bp->bigmac_sdev,
1288                              PAGE_SIZE,
1289                              bp->bmac_block,
1290                              bp->bblock_dvma);
1291
1292         free_netdev(net_dev);
1293
1294         dev_set_drvdata(&dev->dev, NULL);
1295
1296         return 0;
1297 }
1298
1299 static struct of_device_id bigmac_sbus_match[] = {
1300         {
1301                 .name = "qec",
1302         },
1303         {
1304                 .name = "be",
1305         },
1306         {},
1307 };
1308
1309 MODULE_DEVICE_TABLE(of, bigmac_sbus_match);
1310
1311 static struct of_platform_driver bigmac_sbus_driver = {
1312         .name           = "sunbmac",
1313         .match_table    = bigmac_sbus_match,
1314         .probe          = bigmac_sbus_probe,
1315         .remove         = __devexit_p(bigmac_sbus_remove),
1316 };
1317
1318 static int __init bigmac_init(void)
1319 {
1320         return of_register_driver(&bigmac_sbus_driver, &sbus_bus_type);
1321 }
1322
1323 static void __exit bigmac_exit(void)
1324 {
1325         of_unregister_driver(&bigmac_sbus_driver);
1326 }
1327
1328 module_init(bigmac_init);
1329 module_exit(bigmac_exit);