1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/crc32.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/if_vlan.h>
46 #include <linux/firmware.h>
47 #include <asm/processor.h> /* Processor type for cache alignment. */
48 #include <asm/uaccess.h>
52 * The current frame processor firmware fails to checksum a fragment
53 * of length 1. If and when this is fixed, the #define below can be removed.
55 #define HAS_BROKEN_FIRMWARE
58 * If using the broken firmware, data must be padded to the next 32-bit boundary.
60 #ifdef HAS_BROKEN_FIRMWARE
61 #define PADDING_MASK 3
65 * Define this if using the driver with the zero-copy patch
69 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
73 /* The user-configurable values.
74 These may be modified when a driver module is loaded.*/
76 /* Used for tuning interrupt latency vs. overhead. */
77 static int intr_latency;
78 static int small_frames;
80 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
81 static int max_interrupt_work = 20;
83 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
84 The Starfire has a 512 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 512;
86 /* Whether to do TCP/UDP checksums in hardware */
87 static int enable_hw_cksum = 1;
89 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
91 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
92 * Setting to > 1518 effectively disables this feature.
95 * The ia64 doesn't allow for unaligned loads even of integers being
96 * misaligned on a 2 byte boundary. Thus always force copying of
97 * packets as the starfire doesn't allow for misaligned DMAs ;-(
100 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
101 * at least, having unaligned frames leads to a rather serious performance
104 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
105 static int rx_copybreak = PKT_BUF_SZ;
107 static int rx_copybreak /* = 0 */;
110 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
112 #define DMA_BURST_SIZE 64
114 #define DMA_BURST_SIZE 128
117 /* Used to pass the media type, etc.
118 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
119 The media type is usually passed in 'options[]'.
120 These variables are deprecated, use ethtool instead. -Ion
122 #define MAX_UNITS 8 /* More are supported, limit only on options */
123 static int options[MAX_UNITS] = {0, };
124 static int full_duplex[MAX_UNITS] = {0, };
126 /* Operational parameters that are set at compile time. */
128 /* The "native" ring sizes are either 256 or 2048.
129 However in some modes a descriptor may be marked to wrap the ring earlier.
131 #define RX_RING_SIZE 256
132 #define TX_RING_SIZE 32
133 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
134 #define DONE_Q_SIZE 1024
135 /* All queues must be aligned on a 256-byte boundary */
136 #define QUEUE_ALIGN 256
138 #if RX_RING_SIZE > 256
139 #define RX_Q_ENTRIES Rx2048QEntries
141 #define RX_Q_ENTRIES Rx256QEntries
144 /* Operational parameters that usually are not changed. */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (2 * HZ)
148 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
149 /* 64-bit dma_addr_t */
150 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
151 #define netdrv_addr_t __le64
152 #define cpu_to_dma(x) cpu_to_le64(x)
153 #define dma_to_cpu(x) le64_to_cpu(x)
154 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
155 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
156 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
157 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
158 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
159 #else /* 32-bit dma_addr_t */
160 #define netdrv_addr_t __le32
161 #define cpu_to_dma(x) cpu_to_le32(x)
162 #define dma_to_cpu(x) le32_to_cpu(x)
163 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
164 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
165 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
166 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
167 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
170 #define skb_first_frag_len(skb) skb_headlen(skb)
171 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
174 #define FIRMWARE_RX "adaptec/starfire_rx.bin"
175 #define FIRMWARE_TX "adaptec/starfire_tx.bin"
177 /* These identify the driver base version and may not be removed. */
178 static const char version[] __devinitconst =
179 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
180 " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
182 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
183 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_RX);
187 MODULE_FIRMWARE(FIRMWARE_TX);
189 module_param(max_interrupt_work, int, 0);
190 module_param(mtu, int, 0);
191 module_param(debug, int, 0);
192 module_param(rx_copybreak, int, 0);
193 module_param(intr_latency, int, 0);
194 module_param(small_frames, int, 0);
195 module_param_array(options, int, NULL, 0);
196 module_param_array(full_duplex, int, NULL, 0);
197 module_param(enable_hw_cksum, int, 0);
198 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
199 MODULE_PARM_DESC(mtu, "MTU (all boards)");
200 MODULE_PARM_DESC(debug, "Debug level (0-6)");
201 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
202 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
203 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
204 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
205 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
206 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
211 I. Board Compatibility
213 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
215 II. Board-specific settings
217 III. Driver operation
221 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
222 ring sizes are set fixed by the hardware, but may optionally be wrapped
223 earlier by the END bit in the descriptor.
224 This driver uses that hardware queue size for the Rx ring, where a large
225 number of entries has no ill effect beyond increases the potential backlog.
226 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
227 disables the queue layer priority ordering and we have no mechanism to
228 utilize the hardware two-level priority queue. When modifying the
229 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
232 IIIb/c. Transmit/Receive Structure
234 See the Adaptec manual for the many possible structures, and options for
235 each structure. There are far too many to document all of them here.
237 For transmit this driver uses type 0/1 transmit descriptors (depending
238 on the 32/64 bitness of the architecture), and relies on automatic
239 minimum-length padding. It does not use the completion queue
240 consumer index, but instead checks for non-zero status entries.
242 For receive this driver uses type 2/3 receive descriptors. The driver
243 allocates full frame size skbuffs for the Rx ring buffers, so all frames
244 should fit in a single descriptor. The driver does not use the completion
245 queue consumer index, but instead checks for non-zero status entries.
247 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
248 is allocated and the frame is copied to the new skbuff. When the incoming
249 frame is larger, the skbuff is passed directly up the protocol stack.
250 Buffers consumed this way are replaced by newly allocated skbuffs in a later
253 A notable aspect of operation is that unaligned buffers are not permitted by
254 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
255 isn't longword aligned, which may cause problems on some machine
256 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
257 the frame into a new skbuff unconditionally. Copied frames are put into the
258 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
260 IIId. Synchronization
262 The driver runs as two independent, single-threaded flows of control. One
263 is the send-packet routine, which enforces single-threaded use by the
264 dev->tbusy flag. The other thread is the interrupt handler, which is single
265 threaded by the hardware and interrupt handling software.
267 The send packet thread has partial control over the Tx ring and the netif_queue
268 status. If the number of free Tx slots in the ring falls below a certain number
269 (currently hardcoded to 4), it signals the upper layer to stop the queue.
271 The interrupt handler has exclusive control over the Rx ring and records stats
272 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
273 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
274 number of free Tx slow is above the threshold, it signals the upper layer to
281 The Adaptec Starfire manuals, available only from Adaptec.
282 http://www.scyld.com/expert/100mbps.html
283 http://www.scyld.com/expert/NWay.html
287 - StopOnPerr is broken, don't enable
288 - Hardware ethernet padding exposes random data, perform software padding
289 instead (unverified -- works correctly for all the hardware I have)
295 enum chip_capability_flags {CanHaveMII=1, };
301 static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
302 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
305 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
307 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
308 static const struct chip_info {
311 } netdrv_tbl[] __devinitdata = {
312 { "Adaptec Starfire 6915", CanHaveMII },
316 /* Offsets to the device registers.
317 Unlike software-only systems, device drivers interact with complex hardware.
318 It's not useful to define symbolic names for every register bit in the
319 device. The name can only partially document the semantics and make
320 the driver longer and more difficult to read.
321 In general, only the important configuration values or bits changed
322 multiple times should be defined symbolically.
324 enum register_offsets {
325 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
326 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
327 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
328 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
329 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
330 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
331 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
333 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
334 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
335 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
336 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
337 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
338 TxMode=0x55000, VlanType=0x55064,
339 PerfFilterTable=0x56000, HashTable=0x56100,
340 TxGfpMem=0x58000, RxGfpMem=0x5a000,
344 * Bits in the interrupt status/mask registers.
345 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
346 * enables all the interrupt sources that are or'ed into those status bits.
348 enum intr_status_bits {
349 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
350 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
351 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
352 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
353 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
354 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
355 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
356 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
357 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
358 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
359 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
360 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
361 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
362 IntrTxGfp=0x02, IntrPCIPad=0x01,
364 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
365 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
366 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
369 /* Bits in the RxFilterMode register. */
371 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
372 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
373 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
377 /* Bits in the TxMode register */
379 MiiSoftReset=0x8000, MIILoopback=0x4000,
380 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
381 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
384 /* Bits in the TxDescCtrl register. */
386 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
387 TxDescSpace128=0x30, TxDescSpace256=0x40,
388 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
389 TxDescType3=0x03, TxDescType4=0x04,
390 TxNoDMACompletion=0x08,
391 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
392 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
393 TxDMABurstSizeShift=8,
396 /* Bits in the RxDescQCtrl register. */
398 RxBufferLenShift=16, RxMinDescrThreshShift=0,
399 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
400 Rx2048QEntries=0x4000, Rx256QEntries=0,
401 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
402 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
403 RxDescSpace4=0x000, RxDescSpace8=0x100,
404 RxDescSpace16=0x200, RxDescSpace32=0x300,
405 RxDescSpace64=0x400, RxDescSpace128=0x500,
409 /* Bits in the RxDMACtrl register. */
410 enum rx_dmactrl_bits {
411 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
412 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
413 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
414 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
415 RxChecksumRejectTCPOnly=0x01000000,
416 RxCompletionQ2Enable=0x800000,
417 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
418 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
419 RxDMAQ2NonIP=0x400000,
420 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
421 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
425 /* Bits in the RxCompletionAddr register */
427 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
428 RxComplProducerWrEn=0x40,
429 RxComplType0=0x00, RxComplType1=0x10,
430 RxComplType2=0x20, RxComplType3=0x30,
431 RxComplThreshShift=0,
434 /* Bits in the TxCompletionAddr register */
436 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
437 TxComplProducerWrEn=0x40,
438 TxComplIntrStatus=0x20,
439 CommonQueueMode=0x10,
440 TxComplThreshShift=0,
443 /* Bits in the GenCtrl register */
445 RxEnable=0x05, TxEnable=0x0a,
446 RxGFPEnable=0x10, TxGFPEnable=0x20,
449 /* Bits in the IntrTimerCtrl register */
450 enum intr_ctrl_bits {
451 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
452 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
453 IntrLatencyMask=0x1f,
456 /* The Rx and Tx buffer descriptors. */
457 struct starfire_rx_desc {
458 netdrv_addr_t rxaddr;
461 RxDescValid=1, RxDescEndRing=2,
464 /* Completion queue entry. */
465 struct short_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
468 struct basic_rx_done_desc {
469 __le32 status; /* Low 16 bits is length. */
473 struct csum_rx_done_desc {
474 __le32 status; /* Low 16 bits is length. */
475 __le16 csum; /* Partial checksum */
478 struct full_rx_done_desc {
479 __le32 status; /* Low 16 bits is length. */
483 __le16 csum; /* partial checksum */
486 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
488 typedef struct full_rx_done_desc rx_done_desc;
489 #define RxComplType RxComplType3
490 #else /* not VLAN_SUPPORT */
491 typedef struct csum_rx_done_desc rx_done_desc;
492 #define RxComplType RxComplType2
493 #endif /* not VLAN_SUPPORT */
496 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
499 /* Type 1 Tx descriptor. */
500 struct starfire_tx_desc_1 {
501 __le32 status; /* Upper bits are status, lower 16 length. */
505 /* Type 2 Tx descriptor. */
506 struct starfire_tx_desc_2 {
507 __le32 status; /* Upper bits are status, lower 16 length. */
513 typedef struct starfire_tx_desc_2 starfire_tx_desc;
514 #define TX_DESC_TYPE TxDescType2
515 #else /* not ADDR_64BITS */
516 typedef struct starfire_tx_desc_1 starfire_tx_desc;
517 #define TX_DESC_TYPE TxDescType1
518 #endif /* not ADDR_64BITS */
519 #define TX_DESC_SPACING TxDescSpaceUnlim
523 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
524 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
526 struct tx_done_desc {
527 __le32 status; /* timestamp, index. */
529 __le32 intrstatus; /* interrupt status */
533 struct rx_ring_info {
537 struct tx_ring_info {
540 unsigned int used_slots;
544 struct netdev_private {
545 /* Descriptor rings first for alignment. */
546 struct starfire_rx_desc *rx_ring;
547 starfire_tx_desc *tx_ring;
548 dma_addr_t rx_ring_dma;
549 dma_addr_t tx_ring_dma;
550 /* The addresses of rx/tx-in-place skbuffs. */
551 struct rx_ring_info rx_info[RX_RING_SIZE];
552 struct tx_ring_info tx_info[TX_RING_SIZE];
553 /* Pointers to completion queues (full pages). */
554 rx_done_desc *rx_done_q;
555 dma_addr_t rx_done_q_dma;
556 unsigned int rx_done;
557 struct tx_done_desc *tx_done_q;
558 dma_addr_t tx_done_q_dma;
559 unsigned int tx_done;
560 struct napi_struct napi;
561 struct net_device *dev;
562 struct pci_dev *pci_dev;
564 struct vlan_group *vlgrp;
567 dma_addr_t queue_mem_dma;
568 size_t queue_mem_size;
570 /* Frequently used values: keep some adjacent for cache effect. */
572 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
573 unsigned int cur_tx, dirty_tx, reap_tx;
574 unsigned int rx_buf_sz; /* Based on MTU+slack. */
575 /* These values keep track of the transceiver/media in use. */
576 int speed100; /* Set if speed == 100MBit. */
580 /* MII transceiver section. */
581 struct mii_if_info mii_if; /* MII lib hooks/info */
582 int phy_cnt; /* MII device addresses. */
583 unsigned char phys[PHY_CNT]; /* MII device addresses. */
588 static int mdio_read(struct net_device *dev, int phy_id, int location);
589 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
590 static int netdev_open(struct net_device *dev);
591 static void check_duplex(struct net_device *dev);
592 static void tx_timeout(struct net_device *dev);
593 static void init_ring(struct net_device *dev);
594 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
595 static irqreturn_t intr_handler(int irq, void *dev_instance);
596 static void netdev_error(struct net_device *dev, int intr_status);
597 static int __netdev_rx(struct net_device *dev, int *quota);
598 static int netdev_poll(struct napi_struct *napi, int budget);
599 static void refill_rx_ring(struct net_device *dev);
600 static void netdev_error(struct net_device *dev, int intr_status);
601 static void set_rx_mode(struct net_device *dev);
602 static struct net_device_stats *get_stats(struct net_device *dev);
603 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
604 static int netdev_close(struct net_device *dev);
605 static void netdev_media_change(struct net_device *dev);
606 static const struct ethtool_ops ethtool_ops;
610 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
612 struct netdev_private *np = netdev_priv(dev);
614 spin_lock(&np->lock);
616 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
619 spin_unlock(&np->lock);
622 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
624 struct netdev_private *np = netdev_priv(dev);
626 spin_lock(&np->lock);
628 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
630 spin_unlock(&np->lock);
633 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
635 struct netdev_private *np = netdev_priv(dev);
637 spin_lock(&np->lock);
639 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
640 vlan_group_set_device(np->vlgrp, vid, NULL);
642 spin_unlock(&np->lock);
644 #endif /* VLAN_SUPPORT */
647 static const struct net_device_ops netdev_ops = {
648 .ndo_open = netdev_open,
649 .ndo_stop = netdev_close,
650 .ndo_start_xmit = start_tx,
651 .ndo_tx_timeout = tx_timeout,
652 .ndo_get_stats = get_stats,
653 .ndo_set_multicast_list = &set_rx_mode,
654 .ndo_do_ioctl = netdev_ioctl,
655 .ndo_change_mtu = eth_change_mtu,
656 .ndo_set_mac_address = eth_mac_addr,
657 .ndo_validate_addr = eth_validate_addr,
659 .ndo_vlan_rx_register = netdev_vlan_rx_register,
660 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
661 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
665 static int __devinit starfire_init_one(struct pci_dev *pdev,
666 const struct pci_device_id *ent)
668 struct netdev_private *np;
669 int i, irq, option, chip_idx = ent->driver_data;
670 struct net_device *dev;
671 static int card_idx = -1;
674 int drv_flags, io_size;
677 /* when built into the kernel, we only print version if device is found */
679 static int printed_version;
680 if (!printed_version++)
686 if (pci_enable_device (pdev))
689 ioaddr = pci_resource_start(pdev, 0);
690 io_size = pci_resource_len(pdev, 0);
691 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
692 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
696 dev = alloc_etherdev(sizeof(*np));
698 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
701 SET_NETDEV_DEV(dev, &pdev->dev);
705 if (pci_request_regions (pdev, DRV_NAME)) {
706 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
707 goto err_out_free_netdev;
710 base = ioremap(ioaddr, io_size);
712 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
713 card_idx, io_size, ioaddr);
714 goto err_out_free_res;
717 pci_set_master(pdev);
719 /* enable MWI -- it vastly improves Rx performance on sparc64 */
720 pci_try_set_mwi(pdev);
723 /* Starfire can do TCP/UDP checksumming */
725 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
726 #endif /* ZEROCOPY */
729 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
730 #endif /* VLAN_RX_KILL_VID */
732 dev->features |= NETIF_F_HIGHDMA;
733 #endif /* ADDR_64BITS */
735 /* Serial EEPROM reads are hidden by the hardware. */
736 for (i = 0; i < 6; i++)
737 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
739 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
741 for (i = 0; i < 0x20; i++)
743 (unsigned int)readb(base + EEPROMCtrl + i),
744 i % 16 != 15 ? " " : "\n");
747 /* Issue soft reset */
748 writel(MiiSoftReset, base + TxMode);
750 writel(0, base + TxMode);
752 /* Reset the chip to erase previous misconfiguration. */
753 writel(1, base + PCIDeviceConfig);
755 while (--boguscnt > 0) {
757 if ((readl(base + PCIDeviceConfig) & 1) == 0)
761 printk("%s: chipset reset never completed!\n", dev->name);
762 /* wait a little longer */
765 dev->base_addr = (unsigned long)base;
768 np = netdev_priv(dev);
771 spin_lock_init(&np->lock);
772 pci_set_drvdata(pdev, dev);
776 np->mii_if.dev = dev;
777 np->mii_if.mdio_read = mdio_read;
778 np->mii_if.mdio_write = mdio_write;
779 np->mii_if.phy_id_mask = 0x1f;
780 np->mii_if.reg_num_mask = 0x1f;
782 drv_flags = netdrv_tbl[chip_idx].drv_flags;
784 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
786 option = dev->mem_start;
788 /* The lower four bits are the media type. */
790 np->mii_if.full_duplex = 1;
792 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
793 np->mii_if.full_duplex = 1;
795 if (np->mii_if.full_duplex)
796 np->mii_if.force_media = 1;
798 np->mii_if.force_media = 0;
801 /* timer resolution is 128 * 0.8us */
802 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
803 Timer10X | EnableIntrMasking;
805 if (small_frames > 0) {
806 np->intr_timer_ctrl |= SmallFrameBypass;
807 switch (small_frames) {
809 np->intr_timer_ctrl |= SmallFrame64;
812 np->intr_timer_ctrl |= SmallFrame128;
815 np->intr_timer_ctrl |= SmallFrame256;
818 np->intr_timer_ctrl |= SmallFrame512;
819 if (small_frames > 512)
820 printk("Adjusting small_frames down to 512\n");
825 dev->netdev_ops = &netdev_ops;
826 dev->watchdog_timeo = TX_TIMEOUT;
827 SET_ETHTOOL_OPS(dev, ðtool_ops);
829 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
834 if (register_netdev(dev))
835 goto err_out_cleardev;
837 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
838 dev->name, netdrv_tbl[chip_idx].name, base,
841 if (drv_flags & CanHaveMII) {
842 int phy, phy_idx = 0;
844 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
845 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
848 while (--boguscnt > 0)
849 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
852 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
855 mii_status = mdio_read(dev, phy, MII_BMSR);
856 if (mii_status != 0) {
857 np->phys[phy_idx++] = phy;
858 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
859 printk(KERN_INFO "%s: MII PHY found at address %d, status "
860 "%#4.4x advertising %#4.4x.\n",
861 dev->name, phy, mii_status, np->mii_if.advertising);
862 /* there can be only one PHY on-board */
866 np->phy_cnt = phy_idx;
868 np->mii_if.phy_id = np->phys[0];
870 memset(&np->mii_if, 0, sizeof(np->mii_if));
873 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
874 dev->name, enable_hw_cksum ? "enabled" : "disabled");
878 pci_set_drvdata(pdev, NULL);
881 pci_release_regions (pdev);
888 /* Read the MII Management Data I/O (MDIO) interfaces. */
889 static int mdio_read(struct net_device *dev, int phy_id, int location)
891 struct netdev_private *np = netdev_priv(dev);
892 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
893 int result, boguscnt=1000;
894 /* ??? Should we add a busy-wait here? */
896 result = readl(mdio_addr);
897 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
900 if ((result & 0xffff) == 0xffff)
902 return result & 0xffff;
906 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
908 struct netdev_private *np = netdev_priv(dev);
909 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
910 writel(value, mdio_addr);
911 /* The busy-wait will occur before a read. */
915 static int netdev_open(struct net_device *dev)
917 const struct firmware *fw_rx, *fw_tx;
918 const __be32 *fw_rx_data, *fw_tx_data;
919 struct netdev_private *np = netdev_priv(dev);
920 void __iomem *ioaddr = np->base;
922 size_t tx_size, rx_size;
923 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
925 /* Do we ever need to reset the chip??? */
927 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
931 /* Disable the Rx and Tx, and reset the chip. */
932 writel(0, ioaddr + GenCtrl);
933 writel(1, ioaddr + PCIDeviceConfig);
935 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
936 dev->name, dev->irq);
938 /* Allocate the various queues. */
939 if (!np->queue_mem) {
940 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
941 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
942 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
943 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
944 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
945 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
946 if (np->queue_mem == NULL) {
947 free_irq(dev->irq, dev);
951 np->tx_done_q = np->queue_mem;
952 np->tx_done_q_dma = np->queue_mem_dma;
953 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
954 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
955 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
956 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
957 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
958 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
961 /* Start with no carrier, it gets adjusted later */
962 netif_carrier_off(dev);
964 /* Set the size of the Rx buffers. */
965 writel((np->rx_buf_sz << RxBufferLenShift) |
966 (0 << RxMinDescrThreshShift) |
967 RxPrefetchMode | RxVariableQ |
969 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
971 ioaddr + RxDescQCtrl);
973 /* Set up the Rx DMA controller. */
974 writel(RxChecksumIgnore |
975 (0 << RxEarlyIntThreshShift) |
976 (6 << RxHighPrioThreshShift) |
977 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
980 /* Set Tx descriptor */
981 writel((2 << TxHiPriFIFOThreshShift) |
982 (0 << TxPadLenShift) |
983 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
984 TX_DESC_Q_ADDR_SIZE |
985 TX_DESC_SPACING | TX_DESC_TYPE,
986 ioaddr + TxDescCtrl);
988 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
989 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
990 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
991 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
992 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
994 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
995 writel(np->rx_done_q_dma |
997 (0 << RxComplThreshShift),
998 ioaddr + RxCompletionAddr);
1001 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1003 /* Fill both the Tx SA register and the Rx perfect filter. */
1004 for (i = 0; i < 6; i++)
1005 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1006 /* The first entry is special because it bypasses the VLAN filter.
1008 writew(0, ioaddr + PerfFilterTable);
1009 writew(0, ioaddr + PerfFilterTable + 4);
1010 writew(0, ioaddr + PerfFilterTable + 8);
1011 for (i = 1; i < 16; i++) {
1012 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1013 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1014 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1015 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1016 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1019 /* Initialize other registers. */
1020 /* Configure the PCI bus bursts and FIFO thresholds. */
1021 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1022 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1024 writel(np->tx_mode, ioaddr + TxMode);
1025 np->tx_threshold = 4;
1026 writel(np->tx_threshold, ioaddr + TxThreshold);
1028 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1030 napi_enable(&np->napi);
1032 netif_start_queue(dev);
1035 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1038 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1041 /* Enable GPIO interrupts on link change */
1042 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1044 /* Set the interrupt mask */
1045 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1046 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1047 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1048 ioaddr + IntrEnable);
1049 /* Enable PCI interrupts. */
1050 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1051 ioaddr + PCIDeviceConfig);
1054 /* Set VLAN type to 802.1q */
1055 writel(ETH_P_8021Q, ioaddr + VlanType);
1056 #endif /* VLAN_SUPPORT */
1058 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1060 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1064 if (fw_rx->size % 4) {
1065 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1066 fw_rx->size, FIRMWARE_RX);
1070 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1072 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1076 if (fw_tx->size % 4) {
1077 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1078 fw_tx->size, FIRMWARE_TX);
1082 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1083 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1084 rx_size = fw_rx->size / 4;
1085 tx_size = fw_tx->size / 4;
1087 /* Load Rx/Tx firmware into the frame processors */
1088 for (i = 0; i < rx_size; i++)
1089 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1090 for (i = 0; i < tx_size; i++)
1091 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1092 if (enable_hw_cksum)
1093 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1094 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1096 /* Enable the Rx and Tx units only. */
1097 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1100 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1104 release_firmware(fw_tx);
1106 release_firmware(fw_rx);
1114 static void check_duplex(struct net_device *dev)
1116 struct netdev_private *np = netdev_priv(dev);
1118 int silly_count = 1000;
1120 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1121 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1123 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1126 printk("%s: MII reset failed!\n", dev->name);
1130 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1132 if (!np->mii_if.force_media) {
1133 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1135 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1137 reg0 |= BMCR_SPEED100;
1138 if (np->mii_if.full_duplex)
1139 reg0 |= BMCR_FULLDPLX;
1140 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1142 np->speed100 ? "100" : "10",
1143 np->mii_if.full_duplex ? "full" : "half");
1145 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1149 static void tx_timeout(struct net_device *dev)
1151 struct netdev_private *np = netdev_priv(dev);
1152 void __iomem *ioaddr = np->base;
1155 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1156 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1158 /* Perhaps we should reinitialize the hardware here. */
1161 * Stop and restart the interface.
1162 * Cheat and increase the debug level temporarily.
1170 /* Trigger an immediate transmit demand. */
1172 dev->trans_start = jiffies; /* prevent tx timeout */
1173 dev->stats.tx_errors++;
1174 netif_wake_queue(dev);
1178 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1179 static void init_ring(struct net_device *dev)
1181 struct netdev_private *np = netdev_priv(dev);
1184 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1185 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1187 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1189 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1191 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1192 np->rx_info[i].skb = skb;
1195 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1196 skb->dev = dev; /* Mark as being used by this device. */
1197 /* Grrr, we cannot offset to correctly align the IP header. */
1198 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1200 writew(i - 1, np->base + RxDescQIdx);
1201 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1203 /* Clear the remainder of the Rx buffer ring. */
1204 for ( ; i < RX_RING_SIZE; i++) {
1205 np->rx_ring[i].rxaddr = 0;
1206 np->rx_info[i].skb = NULL;
1207 np->rx_info[i].mapping = 0;
1209 /* Mark the last entry as wrapping the ring. */
1210 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1212 /* Clear the completion rings. */
1213 for (i = 0; i < DONE_Q_SIZE; i++) {
1214 np->rx_done_q[i].status = 0;
1215 np->tx_done_q[i].status = 0;
1218 for (i = 0; i < TX_RING_SIZE; i++)
1219 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1223 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1225 struct netdev_private *np = netdev_priv(dev);
1231 * be cautious here, wrapping the queue has weird semantics
1232 * and we may not have enough slots even when it seems we do.
1234 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1235 netif_stop_queue(dev);
1236 return NETDEV_TX_BUSY;
1239 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1240 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1241 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1242 return NETDEV_TX_OK;
1244 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1246 entry = np->cur_tx % TX_RING_SIZE;
1247 for (i = 0; i < skb_num_frags(skb); i++) {
1252 np->tx_info[entry].skb = skb;
1254 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1255 status |= TxRingWrap;
1259 status |= TxDescIntr;
1262 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1264 dev->stats.tx_compressed++;
1266 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1268 np->tx_info[entry].mapping =
1269 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1271 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1272 status |= this_frag->size;
1273 np->tx_info[entry].mapping =
1274 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1277 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1278 np->tx_ring[entry].status = cpu_to_le32(status);
1280 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1281 dev->name, np->cur_tx, np->dirty_tx,
1284 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1285 np->cur_tx += np->tx_info[entry].used_slots;
1288 np->tx_info[entry].used_slots = 1;
1289 np->cur_tx += np->tx_info[entry].used_slots;
1292 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1293 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1297 /* Non-x86: explicitly flush descriptor cache lines here. */
1298 /* Ensure all descriptors are written back before the transmit is
1302 /* Update the producer index. */
1303 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1305 /* 4 is arbitrary, but should be ok */
1306 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1307 netif_stop_queue(dev);
1309 return NETDEV_TX_OK;
1313 /* The interrupt handler does all of the Rx thread work and cleans up
1314 after the Tx thread. */
1315 static irqreturn_t intr_handler(int irq, void *dev_instance)
1317 struct net_device *dev = dev_instance;
1318 struct netdev_private *np = netdev_priv(dev);
1319 void __iomem *ioaddr = np->base;
1320 int boguscnt = max_interrupt_work;
1326 u32 intr_status = readl(ioaddr + IntrClear);
1329 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1330 dev->name, intr_status);
1332 if (intr_status == 0 || intr_status == (u32) -1)
1337 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1340 if (likely(napi_schedule_prep(&np->napi))) {
1341 __napi_schedule(&np->napi);
1342 enable = readl(ioaddr + IntrEnable);
1343 enable &= ~(IntrRxDone | IntrRxEmpty);
1344 writel(enable, ioaddr + IntrEnable);
1345 /* flush PCI posting buffers */
1346 readl(ioaddr + IntrEnable);
1348 /* Paranoia check */
1349 enable = readl(ioaddr + IntrEnable);
1350 if (enable & (IntrRxDone | IntrRxEmpty)) {
1352 "%s: interrupt while in poll!\n",
1354 enable &= ~(IntrRxDone | IntrRxEmpty);
1355 writel(enable, ioaddr + IntrEnable);
1360 /* Scavenge the skbuff list based on the Tx-done queue.
1361 There are redundant checks here that may be cleaned up
1362 after the driver has proven to be reliable. */
1363 consumer = readl(ioaddr + TxConsumerIdx);
1365 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1366 dev->name, consumer);
1368 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1370 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1371 dev->name, np->dirty_tx, np->tx_done, tx_status);
1372 if ((tx_status & 0xe0000000) == 0xa0000000) {
1373 dev->stats.tx_packets++;
1374 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1375 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1376 struct sk_buff *skb = np->tx_info[entry].skb;
1377 np->tx_info[entry].skb = NULL;
1378 pci_unmap_single(np->pci_dev,
1379 np->tx_info[entry].mapping,
1380 skb_first_frag_len(skb),
1382 np->tx_info[entry].mapping = 0;
1383 np->dirty_tx += np->tx_info[entry].used_slots;
1384 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1388 pci_unmap_single(np->pci_dev,
1389 np->tx_info[entry].mapping,
1390 skb_shinfo(skb)->frags[i].size,
1397 dev_kfree_skb_irq(skb);
1399 np->tx_done_q[np->tx_done].status = 0;
1400 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1402 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1404 if (netif_queue_stopped(dev) &&
1405 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1406 /* The ring is no longer full, wake the queue. */
1407 netif_wake_queue(dev);
1410 /* Stats overflow */
1411 if (intr_status & IntrStatsMax)
1414 /* Media change interrupt. */
1415 if (intr_status & IntrLinkChange)
1416 netdev_media_change(dev);
1418 /* Abnormal error summary/uncommon events handlers. */
1419 if (intr_status & IntrAbnormalSummary)
1420 netdev_error(dev, intr_status);
1422 if (--boguscnt < 0) {
1424 printk(KERN_WARNING "%s: Too much work at interrupt, "
1426 dev->name, intr_status);
1432 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1433 dev->name, (int) readl(ioaddr + IntrStatus));
1434 return IRQ_RETVAL(handled);
1439 * This routine is logically part of the interrupt/poll handler, but separated
1440 * for clarity and better register allocation.
1442 static int __netdev_rx(struct net_device *dev, int *quota)
1444 struct netdev_private *np = netdev_priv(dev);
1448 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1449 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1450 struct sk_buff *skb;
1453 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1456 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1457 if (!(desc_status & RxOK)) {
1458 /* There was an error. */
1460 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1461 dev->stats.rx_errors++;
1462 if (desc_status & RxFIFOErr)
1463 dev->stats.rx_fifo_errors++;
1467 if (*quota <= 0) { /* out of rx quota */
1473 pkt_len = desc_status; /* Implicitly Truncate */
1474 entry = (desc_status >> 16) & 0x7ff;
1477 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1478 /* Check if the packet is long enough to accept without copying
1479 to a minimally-sized skbuff. */
1480 if (pkt_len < rx_copybreak &&
1481 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1482 skb_reserve(skb, 2); /* 16 byte align the IP header */
1483 pci_dma_sync_single_for_cpu(np->pci_dev,
1484 np->rx_info[entry].mapping,
1485 pkt_len, PCI_DMA_FROMDEVICE);
1486 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1487 pci_dma_sync_single_for_device(np->pci_dev,
1488 np->rx_info[entry].mapping,
1489 pkt_len, PCI_DMA_FROMDEVICE);
1490 skb_put(skb, pkt_len);
1492 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1493 skb = np->rx_info[entry].skb;
1494 skb_put(skb, pkt_len);
1495 np->rx_info[entry].skb = NULL;
1496 np->rx_info[entry].mapping = 0;
1498 #ifndef final_version /* Remove after testing. */
1499 /* You will want this info for the initial debug. */
1501 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1502 skb->data, skb->data + 6,
1503 skb->data[12], skb->data[13]);
1507 skb->protocol = eth_type_trans(skb, dev);
1510 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1512 if (le16_to_cpu(desc->status2) & 0x0100) {
1513 skb->ip_summed = CHECKSUM_UNNECESSARY;
1514 dev->stats.rx_compressed++;
1517 * This feature doesn't seem to be working, at least
1518 * with the two firmware versions I have. If the GFP sees
1519 * an IP fragment, it either ignores it completely, or reports
1520 * "bad checksum" on it.
1522 * Maybe I missed something -- corrections are welcome.
1523 * Until then, the printk stays. :-) -Ion
1525 else if (le16_to_cpu(desc->status2) & 0x0040) {
1526 skb->ip_summed = CHECKSUM_COMPLETE;
1527 skb->csum = le16_to_cpu(desc->csum);
1528 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1531 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1532 u16 vlid = le16_to_cpu(desc->vlanid);
1535 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1539 * vlan_hwaccel_rx expects a packet with the VLAN tag
1542 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1544 #endif /* VLAN_SUPPORT */
1545 netif_receive_skb(skb);
1546 dev->stats.rx_packets++;
1551 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1554 if (*quota == 0) { /* out of rx quota */
1558 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1561 refill_rx_ring(dev);
1563 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1564 retcode, np->rx_done, desc_status);
1568 static int netdev_poll(struct napi_struct *napi, int budget)
1570 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1571 struct net_device *dev = np->dev;
1573 void __iomem *ioaddr = np->base;
1577 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1579 if (__netdev_rx(dev, "a))
1582 intr_status = readl(ioaddr + IntrStatus);
1583 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1585 napi_complete(napi);
1586 intr_status = readl(ioaddr + IntrEnable);
1587 intr_status |= IntrRxDone | IntrRxEmpty;
1588 writel(intr_status, ioaddr + IntrEnable);
1592 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1595 /* Restart Rx engine if stopped. */
1596 return budget - quota;
1599 static void refill_rx_ring(struct net_device *dev)
1601 struct netdev_private *np = netdev_priv(dev);
1602 struct sk_buff *skb;
1605 /* Refill the Rx ring buffers. */
1606 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1607 entry = np->dirty_rx % RX_RING_SIZE;
1608 if (np->rx_info[entry].skb == NULL) {
1609 skb = dev_alloc_skb(np->rx_buf_sz);
1610 np->rx_info[entry].skb = skb;
1612 break; /* Better luck next round. */
1613 np->rx_info[entry].mapping =
1614 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1615 skb->dev = dev; /* Mark as being used by this device. */
1616 np->rx_ring[entry].rxaddr =
1617 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1619 if (entry == RX_RING_SIZE - 1)
1620 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1623 writew(entry, np->base + RxDescQIdx);
1627 static void netdev_media_change(struct net_device *dev)
1629 struct netdev_private *np = netdev_priv(dev);
1630 void __iomem *ioaddr = np->base;
1631 u16 reg0, reg1, reg4, reg5;
1633 u32 new_intr_timer_ctrl;
1635 /* reset status first */
1636 mdio_read(dev, np->phys[0], MII_BMCR);
1637 mdio_read(dev, np->phys[0], MII_BMSR);
1639 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1640 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1642 if (reg1 & BMSR_LSTATUS) {
1644 if (reg0 & BMCR_ANENABLE) {
1645 /* autonegotiation is enabled */
1646 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1647 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1648 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1650 np->mii_if.full_duplex = 1;
1651 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1653 np->mii_if.full_duplex = 0;
1654 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1656 np->mii_if.full_duplex = 1;
1659 np->mii_if.full_duplex = 0;
1662 /* autonegotiation is disabled */
1663 if (reg0 & BMCR_SPEED100)
1667 if (reg0 & BMCR_FULLDPLX)
1668 np->mii_if.full_duplex = 1;
1670 np->mii_if.full_duplex = 0;
1672 netif_carrier_on(dev);
1673 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1675 np->speed100 ? "100" : "10",
1676 np->mii_if.full_duplex ? "full" : "half");
1678 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1679 if (np->mii_if.full_duplex)
1680 new_tx_mode |= FullDuplex;
1681 if (np->tx_mode != new_tx_mode) {
1682 np->tx_mode = new_tx_mode;
1683 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1685 writel(np->tx_mode, ioaddr + TxMode);
1688 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1690 new_intr_timer_ctrl |= Timer10X;
1691 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1692 np->intr_timer_ctrl = new_intr_timer_ctrl;
1693 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1696 netif_carrier_off(dev);
1697 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1702 static void netdev_error(struct net_device *dev, int intr_status)
1704 struct netdev_private *np = netdev_priv(dev);
1706 /* Came close to underrunning the Tx FIFO, increase threshold. */
1707 if (intr_status & IntrTxDataLow) {
1708 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1709 writel(++np->tx_threshold, np->base + TxThreshold);
1710 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1711 dev->name, np->tx_threshold * 16);
1713 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1715 if (intr_status & IntrRxGFPDead) {
1716 dev->stats.rx_fifo_errors++;
1717 dev->stats.rx_errors++;
1719 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1720 dev->stats.tx_fifo_errors++;
1721 dev->stats.tx_errors++;
1723 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1724 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1725 dev->name, intr_status);
1729 static struct net_device_stats *get_stats(struct net_device *dev)
1731 struct netdev_private *np = netdev_priv(dev);
1732 void __iomem *ioaddr = np->base;
1734 /* This adapter architecture needs no SMP locks. */
1735 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1736 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1737 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1738 dev->stats.tx_aborted_errors =
1739 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1740 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1741 dev->stats.collisions =
1742 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1744 /* The chip only need report frame silently dropped. */
1745 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1746 writew(0, ioaddr + RxDMAStatus);
1747 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1748 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1749 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1750 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1756 static void set_rx_mode(struct net_device *dev)
1758 struct netdev_private *np = netdev_priv(dev);
1759 void __iomem *ioaddr = np->base;
1760 u32 rx_mode = MinVLANPrio;
1761 struct netdev_hw_addr *ha;
1765 rx_mode |= VlanMode;
1768 void __iomem *filter_addr = ioaddr + HashTable + 8;
1769 for (i = 0; i < VLAN_VID_MASK; i++) {
1770 if (vlan_group_get_device(np->vlgrp, i)) {
1771 if (vlan_count >= 32)
1773 writew(i, filter_addr);
1778 if (i == VLAN_VID_MASK) {
1779 rx_mode |= PerfectFilterVlan;
1780 while (vlan_count < 32) {
1781 writew(0, filter_addr);
1787 #endif /* VLAN_SUPPORT */
1789 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1790 rx_mode |= AcceptAll;
1791 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1792 (dev->flags & IFF_ALLMULTI)) {
1793 /* Too many to match, or accept all multicasts. */
1794 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1795 } else if (netdev_mc_count(dev) <= 14) {
1796 /* Use the 16 element perfect filter, skip first two entries. */
1797 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1799 netdev_for_each_mc_addr(ha, dev) {
1800 eaddrs = (__be16 *) ha->addr;
1801 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1802 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1803 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1805 eaddrs = (__be16 *)dev->dev_addr;
1806 i = netdev_mc_count(dev) + 2;
1808 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1809 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1810 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1812 rx_mode |= AcceptBroadcast|PerfectFilter;
1814 /* Must use a multicast hash table. */
1815 void __iomem *filter_addr;
1817 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1819 memset(mc_filter, 0, sizeof(mc_filter));
1820 netdev_for_each_mc_addr(ha, dev) {
1821 /* The chip uses the upper 9 CRC bits
1822 as index into the hash table */
1823 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1824 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1826 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1828 /* Clear the perfect filter list, skip first two entries. */
1829 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1830 eaddrs = (__be16 *)dev->dev_addr;
1831 for (i = 2; i < 16; i++) {
1832 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1833 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1834 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1836 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1837 writew(mc_filter[i], filter_addr);
1838 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1840 writel(rx_mode, ioaddr + RxFilterMode);
1843 static int check_if_running(struct net_device *dev)
1845 if (!netif_running(dev))
1850 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1852 struct netdev_private *np = netdev_priv(dev);
1853 strcpy(info->driver, DRV_NAME);
1854 strcpy(info->version, DRV_VERSION);
1855 strcpy(info->bus_info, pci_name(np->pci_dev));
1858 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1860 struct netdev_private *np = netdev_priv(dev);
1861 spin_lock_irq(&np->lock);
1862 mii_ethtool_gset(&np->mii_if, ecmd);
1863 spin_unlock_irq(&np->lock);
1867 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1869 struct netdev_private *np = netdev_priv(dev);
1871 spin_lock_irq(&np->lock);
1872 res = mii_ethtool_sset(&np->mii_if, ecmd);
1873 spin_unlock_irq(&np->lock);
1878 static int nway_reset(struct net_device *dev)
1880 struct netdev_private *np = netdev_priv(dev);
1881 return mii_nway_restart(&np->mii_if);
1884 static u32 get_link(struct net_device *dev)
1886 struct netdev_private *np = netdev_priv(dev);
1887 return mii_link_ok(&np->mii_if);
1890 static u32 get_msglevel(struct net_device *dev)
1895 static void set_msglevel(struct net_device *dev, u32 val)
1900 static const struct ethtool_ops ethtool_ops = {
1901 .begin = check_if_running,
1902 .get_drvinfo = get_drvinfo,
1903 .get_settings = get_settings,
1904 .set_settings = set_settings,
1905 .nway_reset = nway_reset,
1906 .get_link = get_link,
1907 .get_msglevel = get_msglevel,
1908 .set_msglevel = set_msglevel,
1911 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1913 struct netdev_private *np = netdev_priv(dev);
1914 struct mii_ioctl_data *data = if_mii(rq);
1917 if (!netif_running(dev))
1920 spin_lock_irq(&np->lock);
1921 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1922 spin_unlock_irq(&np->lock);
1924 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1930 static int netdev_close(struct net_device *dev)
1932 struct netdev_private *np = netdev_priv(dev);
1933 void __iomem *ioaddr = np->base;
1936 netif_stop_queue(dev);
1938 napi_disable(&np->napi);
1941 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1942 dev->name, (int) readl(ioaddr + IntrStatus));
1943 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1944 dev->name, np->cur_tx, np->dirty_tx,
1945 np->cur_rx, np->dirty_rx);
1948 /* Disable interrupts by clearing the interrupt mask. */
1949 writel(0, ioaddr + IntrEnable);
1951 /* Stop the chip's Tx and Rx processes. */
1952 writel(0, ioaddr + GenCtrl);
1953 readl(ioaddr + GenCtrl);
1956 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1957 (long long) np->tx_ring_dma);
1958 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1959 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1960 i, le32_to_cpu(np->tx_ring[i].status),
1961 (long long) dma_to_cpu(np->tx_ring[i].addr),
1962 le32_to_cpu(np->tx_done_q[i].status));
1963 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1964 (long long) np->rx_ring_dma, np->rx_done_q);
1966 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1967 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1968 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1972 free_irq(dev->irq, dev);
1974 /* Free all the skbuffs in the Rx queue. */
1975 for (i = 0; i < RX_RING_SIZE; i++) {
1976 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1977 if (np->rx_info[i].skb != NULL) {
1978 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1979 dev_kfree_skb(np->rx_info[i].skb);
1981 np->rx_info[i].skb = NULL;
1982 np->rx_info[i].mapping = 0;
1984 for (i = 0; i < TX_RING_SIZE; i++) {
1985 struct sk_buff *skb = np->tx_info[i].skb;
1988 pci_unmap_single(np->pci_dev,
1989 np->tx_info[i].mapping,
1990 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1991 np->tx_info[i].mapping = 0;
1993 np->tx_info[i].skb = NULL;
2000 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
2002 struct net_device *dev = pci_get_drvdata(pdev);
2004 if (netif_running(dev)) {
2005 netif_device_detach(dev);
2009 pci_save_state(pdev);
2010 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2015 static int starfire_resume(struct pci_dev *pdev)
2017 struct net_device *dev = pci_get_drvdata(pdev);
2019 pci_set_power_state(pdev, PCI_D0);
2020 pci_restore_state(pdev);
2022 if (netif_running(dev)) {
2024 netif_device_attach(dev);
2029 #endif /* CONFIG_PM */
2032 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2034 struct net_device *dev = pci_get_drvdata(pdev);
2035 struct netdev_private *np = netdev_priv(dev);
2039 unregister_netdev(dev);
2042 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2045 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2046 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2047 pci_disable_device(pdev);
2050 pci_release_regions(pdev);
2052 pci_set_drvdata(pdev, NULL);
2053 free_netdev(dev); /* Will also free np!! */
2057 static struct pci_driver starfire_driver = {
2059 .probe = starfire_init_one,
2060 .remove = __devexit_p(starfire_remove_one),
2062 .suspend = starfire_suspend,
2063 .resume = starfire_resume,
2064 #endif /* CONFIG_PM */
2065 .id_table = starfire_pci_tbl,
2069 static int __init starfire_init (void)
2071 /* when a module, this is printed whether or not devices are found in probe */
2075 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2078 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2080 return pci_register_driver(&starfire_driver);
2084 static void __exit starfire_cleanup (void)
2086 pci_unregister_driver (&starfire_driver);
2090 module_init(starfire_init);
2091 module_exit(starfire_cleanup);