2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/config.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.3"
48 #define PFX DRV_NAME " "
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
88 MODULE_DEVICE_TABLE(pci, skge_id_table);
90 static int skge_up(struct net_device *dev);
91 static int skge_down(struct net_device *dev);
92 static void skge_phy_reset(struct skge_port *skge);
93 static void skge_tx_clean(struct skge_port *skge);
94 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static void genesis_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_init(struct skge_hw *hw, int port);
99 static void genesis_mac_init(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static int skge_get_regs_len(struct net_device *dev)
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
118 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 const struct skge_port *skge = netdev_priv(dev);
122 const void __iomem *io = skge->hw->regs;
125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
132 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
133 static int wol_supported(const struct skge_hw *hw)
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
139 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 struct skge_port *skge = netdev_priv(dev);
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 skge->wol = wol->wolopts == WAKE_MAGIC;
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
172 /* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 static u32 skge_supported_modes(const struct skge_hw *hw)
180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
203 static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
209 ecmd->transceiver = XCVR_INTERNAL;
210 ecmd->supported = skge_supported_modes(hw);
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
216 ecmd->port = PORT_FIBRE;
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
225 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
229 u32 supported = skge_supported_modes(hw);
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
232 ecmd->advertising = supported;
238 switch (ecmd->speed) {
240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
268 if ((setting & supported) == 0)
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
275 skge->autoneg = ecmd->autoneg;
276 skge->advertising = ecmd->advertising;
278 if (netif_running(dev))
279 skge_phy_reset(skge);
284 static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
287 struct skge_port *skge = netdev_priv(dev);
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295 static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326 static int skge_get_stats_count(struct net_device *dev)
328 return ARRAY_SIZE(skge_stats);
331 static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
334 struct skge_port *skge = netdev_priv(dev);
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
339 yukon_get_stats(skge, data);
342 /* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
346 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
354 yukon_get_stats(skge, data);
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
364 return &skge->net_stats;
367 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
380 static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
383 struct skge_port *skge = netdev_priv(dev);
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
396 static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
399 struct skge_port *skge = netdev_priv(dev);
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
409 if (netif_running(dev)) {
419 static u32 skge_get_msglevel(struct net_device *netdev)
421 struct skge_port *skge = netdev_priv(netdev);
422 return skge->msg_enable;
425 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 struct skge_port *skge = netdev_priv(netdev);
428 skge->msg_enable = value;
431 static int skge_nway_reset(struct net_device *dev)
433 struct skge_port *skge = netdev_priv(dev);
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 skge_phy_reset(skge);
442 static int skge_set_sg(struct net_device *dev, u32 data)
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
447 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return ethtool_op_set_sg(dev, data);
452 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 struct skge_port *skge = netdev_priv(dev);
455 struct skge_hw *hw = skge->hw;
457 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return ethtool_op_set_tx_csum(dev, data);
463 static u32 skge_get_rx_csum(struct net_device *dev)
465 struct skge_port *skge = netdev_priv(dev);
467 return skge->rx_csum;
470 /* Only Yukon supports checksum offload. */
471 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 struct skge_port *skge = netdev_priv(dev);
475 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 skge->rx_csum = data;
482 static void skge_get_pauseparam(struct net_device *dev,
483 struct ethtool_pauseparam *ecmd)
485 struct skge_port *skge = netdev_priv(dev);
487 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
488 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492 ecmd->autoneg = skge->autoneg;
495 static int skge_set_pauseparam(struct net_device *dev,
496 struct ethtool_pauseparam *ecmd)
498 struct skge_port *skge = netdev_priv(dev);
500 skge->autoneg = ecmd->autoneg;
501 if (ecmd->rx_pause && ecmd->tx_pause)
502 skge->flow_control = FLOW_MODE_SYMMETRIC;
503 else if (ecmd->rx_pause && !ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_REM_SEND;
505 else if (!ecmd->rx_pause && ecmd->tx_pause)
506 skge->flow_control = FLOW_MODE_LOC_SEND;
508 skge->flow_control = FLOW_MODE_NONE;
510 if (netif_running(dev))
511 skge_phy_reset(skge);
515 /* Chip internal frequency for clock calculations */
516 static inline u32 hwkhz(const struct skge_hw *hw)
518 if (hw->chip_id == CHIP_ID_GENESIS)
519 return 53215; /* or: 53.125 MHz */
521 return 78215; /* or: 78.125 MHz */
524 /* Chip HZ to microseconds */
525 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 return (ticks * 1000) / hwkhz(hw);
530 /* Microseconds to chip HZ */
531 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 return hwkhz(hw) * usec / 1000;
536 static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
559 /* Note: interrupt timer is per board, but can turn on/off per port */
560 static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
589 skge_write32(hw, B2_IRQM_MSK, msk);
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
599 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
605 spin_lock_bh(&hw->phy_lock);
606 if (hw->chip_id == CHIP_ID_GENESIS) {
609 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
610 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
611 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
612 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
616 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
620 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
637 PHY_M_LED_MO_DUP(MO_LED_OFF) |
638 PHY_M_LED_MO_10(MO_LED_OFF) |
639 PHY_M_LED_MO_100(MO_LED_OFF) |
640 PHY_M_LED_MO_1000(MO_LED_OFF) |
641 PHY_M_LED_MO_RX(MO_LED_OFF));
644 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
645 PHY_M_LED_PULS_DUR(PULS_170MS) |
646 PHY_M_LED_BLINK_RT(BLINK_84MS) |
650 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
651 PHY_M_LED_MO_RX(MO_LED_OFF) |
652 (skge->speed == SPEED_100 ?
653 PHY_M_LED_MO_100(MO_LED_ON) : 0));
656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
657 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
658 PHY_M_LED_MO_DUP(MO_LED_ON) |
659 PHY_M_LED_MO_10(MO_LED_ON) |
660 PHY_M_LED_MO_100(MO_LED_ON) |
661 PHY_M_LED_MO_1000(MO_LED_ON) |
662 PHY_M_LED_MO_RX(MO_LED_ON));
665 spin_unlock_bh(&hw->phy_lock);
668 /* blink LED's for finding board */
669 static int skge_phys_id(struct net_device *dev, u32 data)
671 struct skge_port *skge = netdev_priv(dev);
673 enum led_mode mode = LED_MODE_TST;
675 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
676 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
681 skge_led(skge, mode);
682 mode ^= LED_MODE_TST;
684 if (msleep_interruptible(BLINK_MS))
689 /* back to regular LED state */
690 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
695 static struct ethtool_ops skge_ethtool_ops = {
696 .get_settings = skge_get_settings,
697 .set_settings = skge_set_settings,
698 .get_drvinfo = skge_get_drvinfo,
699 .get_regs_len = skge_get_regs_len,
700 .get_regs = skge_get_regs,
701 .get_wol = skge_get_wol,
702 .set_wol = skge_set_wol,
703 .get_msglevel = skge_get_msglevel,
704 .set_msglevel = skge_set_msglevel,
705 .nway_reset = skge_nway_reset,
706 .get_link = ethtool_op_get_link,
707 .get_ringparam = skge_get_ring_param,
708 .set_ringparam = skge_set_ring_param,
709 .get_pauseparam = skge_get_pauseparam,
710 .set_pauseparam = skge_set_pauseparam,
711 .get_coalesce = skge_get_coalesce,
712 .set_coalesce = skge_set_coalesce,
713 .get_sg = ethtool_op_get_sg,
714 .set_sg = skge_set_sg,
715 .get_tx_csum = ethtool_op_get_tx_csum,
716 .set_tx_csum = skge_set_tx_csum,
717 .get_rx_csum = skge_get_rx_csum,
718 .set_rx_csum = skge_set_rx_csum,
719 .get_strings = skge_get_strings,
720 .phys_id = skge_phys_id,
721 .get_stats_count = skge_get_stats_count,
722 .get_ethtool_stats = skge_get_ethtool_stats,
723 .get_perm_addr = ethtool_op_get_perm_addr,
727 * Allocate ring elements and chain them together
728 * One-to-one association of board descriptors with ring elements
730 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
732 struct skge_tx_desc *d;
733 struct skge_element *e;
736 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
740 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
743 if (i == ring->count - 1) {
744 e->next = ring->start;
745 d->next_offset = base;
748 d->next_offset = base + (i+1) * sizeof(*d);
751 ring->to_use = ring->to_clean = ring->start;
756 /* Allocate and setup a new buffer for receiving */
757 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
758 struct sk_buff *skb, unsigned int bufsize)
760 struct skge_rx_desc *rd = e->desc;
763 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
767 rd->dma_hi = map >> 32;
769 rd->csum1_start = ETH_HLEN;
770 rd->csum2_start = ETH_HLEN;
776 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
777 pci_unmap_addr_set(e, mapaddr, map);
778 pci_unmap_len_set(e, maplen, bufsize);
781 /* Resume receiving using existing skb,
782 * Note: DMA address is not changed by chip.
783 * MTU not changed while receiver active.
785 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 struct skge_rx_desc *rd = e->desc;
790 rd->csum2_start = ETH_HLEN;
794 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
798 /* Free all buffers in receive ring, assumes receiver stopped */
799 static void skge_rx_clean(struct skge_port *skge)
801 struct skge_hw *hw = skge->hw;
802 struct skge_ring *ring = &skge->rx_ring;
803 struct skge_element *e;
807 struct skge_rx_desc *rd = e->desc;
810 pci_unmap_single(hw->pdev,
811 pci_unmap_addr(e, mapaddr),
812 pci_unmap_len(e, maplen),
814 dev_kfree_skb(e->skb);
817 } while ((e = e->next) != ring->start);
821 /* Allocate buffers for receive ring
822 * For receive: to_clean is next received frame.
824 static int skge_rx_fill(struct skge_port *skge)
826 struct skge_ring *ring = &skge->rx_ring;
827 struct skge_element *e;
833 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
837 skb_reserve(skb, NET_IP_ALIGN);
838 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
839 } while ( (e = e->next) != ring->start);
841 ring->to_clean = ring->start;
845 static void skge_link_up(struct skge_port *skge)
847 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
848 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850 netif_carrier_on(skge->netdev);
851 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
852 netif_wake_queue(skge->netdev);
854 if (netif_msg_link(skge))
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
866 static void skge_link_down(struct skge_port *skge)
868 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
869 netif_carrier_off(skge->netdev);
870 netif_stop_queue(skge->netdev);
872 if (netif_msg_link(skge))
873 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
876 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
881 *val = xm_read16(hw, port, XM_PHY_DATA);
883 for (i = 0; i < PHY_RETRIES; i++) {
884 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
891 *val = xm_read16(hw, port, XM_PHY_DATA);
896 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
899 if (__xm_phy_read(hw, port, reg, &v))
900 printk(KERN_WARNING PFX "%s: phy read timed out\n",
901 hw->dev[port]->name);
905 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
910 for (i = 0; i < PHY_RETRIES; i++) {
911 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
918 xm_write16(hw, port, XM_PHY_DATA, val);
919 for (i = 0; i < PHY_RETRIES; i++) {
920 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
927 static void genesis_init(struct skge_hw *hw)
929 /* set blink source counter */
930 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
931 skge_write8(hw, B2_BSC_CTRL, BSC_START);
933 /* configure mac arbiter */
934 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
936 /* configure mac arbiter timeout values */
937 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
942 skge_write8(hw, B3_MA_RCINI_RX1, 0);
943 skge_write8(hw, B3_MA_RCINI_RX2, 0);
944 skge_write8(hw, B3_MA_RCINI_TX1, 0);
945 skge_write8(hw, B3_MA_RCINI_TX2, 0);
947 /* configure packet arbiter timeout */
948 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
949 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
955 static void genesis_reset(struct skge_hw *hw, int port)
957 const u8 zero[8] = { 0 };
959 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
961 /* reset the statistics module */
962 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
963 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
964 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
965 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
966 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
968 /* disable Broadcom PHY IRQ */
969 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
971 xm_outhash(hw, port, XM_HSM, zero);
975 /* Convert mode to MII values */
976 static const u16 phy_pause_map[] = {
977 [FLOW_MODE_NONE] = 0,
978 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
979 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
980 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
984 /* Check status of Broadcom phy link */
985 static void bcom_check_link(struct skge_hw *hw, int port)
987 struct net_device *dev = hw->dev[port];
988 struct skge_port *skge = netdev_priv(dev);
991 /* read twice because of latch */
992 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
993 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
995 if ((status & PHY_ST_LSYNC) == 0) {
996 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
997 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
998 xm_write16(hw, port, XM_MMU_CMD, cmd);
999 /* dummy read to ensure writing */
1000 (void) xm_read16(hw, port, XM_MMU_CMD);
1002 if (netif_carrier_ok(dev))
1003 skge_link_down(skge);
1005 if (skge->autoneg == AUTONEG_ENABLE &&
1006 (status & PHY_ST_AN_OVER)) {
1007 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1008 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1010 if (lpa & PHY_B_AN_RF) {
1011 printk(KERN_NOTICE PFX "%s: remote fault\n",
1016 /* Check Duplex mismatch */
1017 switch (aux & PHY_B_AS_AN_RES_MSK) {
1018 case PHY_B_RES_1000FD:
1019 skge->duplex = DUPLEX_FULL;
1021 case PHY_B_RES_1000HD:
1022 skge->duplex = DUPLEX_HALF;
1025 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1031 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1032 switch (aux & PHY_B_AS_PAUSE_MSK) {
1033 case PHY_B_AS_PAUSE_MSK:
1034 skge->flow_control = FLOW_MODE_SYMMETRIC;
1037 skge->flow_control = FLOW_MODE_REM_SEND;
1040 skge->flow_control = FLOW_MODE_LOC_SEND;
1043 skge->flow_control = FLOW_MODE_NONE;
1046 skge->speed = SPEED_1000;
1049 if (!netif_carrier_ok(dev))
1050 genesis_link_up(skge);
1054 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1055 * Phy on for 100 or 10Mbit operation
1057 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1059 struct skge_hw *hw = skge->hw;
1060 int port = skge->port;
1062 u16 id1, r, ext, ctl;
1064 /* magic workaround patterns for Broadcom */
1065 static const struct {
1069 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1070 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1071 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1072 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1074 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1075 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1078 /* read Id from external PHY (all have the same address) */
1079 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1081 /* Optimize MDIO transfer by suppressing preamble. */
1082 r = xm_read16(hw, port, XM_MMU_CMD);
1084 xm_write16(hw, port, XM_MMU_CMD,r);
1087 case PHY_BCOM_ID1_C0:
1089 * Workaround BCOM Errata for the C0 type.
1090 * Write magic patterns to reserved registers.
1092 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1093 xm_phy_write(hw, port,
1094 C0hack[i].reg, C0hack[i].val);
1097 case PHY_BCOM_ID1_A1:
1099 * Workaround BCOM Errata for the A1 type.
1100 * Write magic patterns to reserved registers.
1102 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1103 xm_phy_write(hw, port,
1104 A1hack[i].reg, A1hack[i].val);
1109 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1110 * Disable Power Management after reset.
1112 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1113 r |= PHY_B_AC_DIS_PM;
1114 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1117 xm_read16(hw, port, XM_ISRC);
1119 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1120 ctl = PHY_CT_SP1000; /* always 1000mbit */
1122 if (skge->autoneg == AUTONEG_ENABLE) {
1124 * Workaround BCOM Errata #1 for the C5 type.
1125 * 1000Base-T Link Acquisition Failure in Slave Mode
1126 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1128 u16 adv = PHY_B_1000C_RD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Half)
1130 adv |= PHY_B_1000C_AHD;
1131 if (skge->advertising & ADVERTISED_1000baseT_Full)
1132 adv |= PHY_B_1000C_AFD;
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1135 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1137 if (skge->duplex == DUPLEX_FULL)
1138 ctl |= PHY_CT_DUP_MD;
1139 /* Force to slave */
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1143 /* Set autonegotiation pause parameters */
1144 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1147 /* Handle Jumbo frames */
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1152 ext |= PHY_B_PEC_HIGH_LA;
1156 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1157 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1159 /* Use link status change interrupt */
1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1162 bcom_check_link(hw, port);
1165 static void genesis_mac_init(struct skge_hw *hw, int port)
1167 struct net_device *dev = hw->dev[port];
1168 struct skge_port *skge = netdev_priv(dev);
1169 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1172 const u8 zero[6] = { 0 };
1174 for (i = 0; i < 10; i++) {
1175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1177 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1182 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1185 /* Unreset the XMAC. */
1186 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1189 * Perform additional initialization for external PHYs,
1190 * namely for the 1000baseTX cards that use the XMAC's
1193 /* Take external Phy out of reset */
1194 r = skge_read32(hw, B2_GP_IO);
1196 r |= GP_DIR_0|GP_IO_0;
1198 r |= GP_DIR_2|GP_IO_2;
1200 skge_write32(hw, B2_GP_IO, r);
1203 /* Enable GMII interface */
1204 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1206 bcom_phy_init(skge, jumbo);
1208 /* Set Station Address */
1209 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1211 /* We don't use match addresses so clear */
1212 for (i = 1; i < 16; i++)
1213 xm_outaddr(hw, port, XM_EXM(i), zero);
1215 /* Clear MIB counters */
1216 xm_write16(hw, port, XM_STAT_CMD,
1217 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1218 /* Clear two times according to Errata #3 */
1219 xm_write16(hw, port, XM_STAT_CMD,
1220 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1222 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1223 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1225 /* We don't need the FCS appended to the packet. */
1226 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1228 r |= XM_RX_BIG_PK_OK;
1230 if (skge->duplex == DUPLEX_HALF) {
1232 * If in manual half duplex mode the other side might be in
1233 * full duplex mode, so ignore if a carrier extension is not seen
1234 * on frames received
1236 r |= XM_RX_DIS_CEXT;
1238 xm_write16(hw, port, XM_RX_CMD, r);
1241 /* We want short frames padded to 60 bytes. */
1242 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1245 * Bump up the transmit threshold. This helps hold off transmit
1246 * underruns when we're blasting traffic from both ports at once.
1248 xm_write16(hw, port, XM_TX_THR, 512);
1251 * Enable the reception of all error frames. This is is
1252 * a necessary evil due to the design of the XMAC. The
1253 * XMAC's receive FIFO is only 8K in size, however jumbo
1254 * frames can be up to 9000 bytes in length. When bad
1255 * frame filtering is enabled, the XMAC's RX FIFO operates
1256 * in 'store and forward' mode. For this to work, the
1257 * entire frame has to fit into the FIFO, but that means
1258 * that jumbo frames larger than 8192 bytes will be
1259 * truncated. Disabling all bad frame filtering causes
1260 * the RX FIFO to operate in streaming mode, in which
1261 * case the XMAC will start transferring frames out of the
1262 * RX FIFO as soon as the FIFO threshold is reached.
1264 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1268 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1269 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1270 * and 'Octets Rx OK Hi Cnt Ov'.
1272 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1275 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1276 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1277 * and 'Octets Tx OK Hi Cnt Ov'.
1279 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1281 /* Configure MAC arbiter */
1282 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1284 /* configure timeout values */
1285 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1290 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1295 /* Configure Rx MAC FIFO */
1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1297 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1298 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1300 /* Configure Tx MAC FIFO */
1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1302 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1303 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1306 /* Enable frame flushing if jumbo frames used */
1307 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1309 /* enable timeout timers if normal frames */
1310 skge_write16(hw, B3_PA_CTRL,
1311 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1315 static void genesis_stop(struct skge_port *skge)
1317 struct skge_hw *hw = skge->hw;
1318 int port = skge->port;
1321 genesis_reset(hw, port);
1323 /* Clear Tx packet arbiter timeout IRQ */
1324 skge_write16(hw, B3_PA_CTRL,
1325 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1328 * If the transfer sticks at the MAC the STOP command will not
1329 * terminate if we don't flush the XMAC's transmit FIFO !
1331 xm_write32(hw, port, XM_MODE,
1332 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1336 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1338 /* For external PHYs there must be special handling */
1339 reg = skge_read32(hw, B2_GP_IO);
1347 skge_write32(hw, B2_GP_IO, reg);
1348 skge_read32(hw, B2_GP_IO);
1350 xm_write16(hw, port, XM_MMU_CMD,
1351 xm_read16(hw, port, XM_MMU_CMD)
1352 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1354 xm_read16(hw, port, XM_MMU_CMD);
1358 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1360 struct skge_hw *hw = skge->hw;
1361 int port = skge->port;
1363 unsigned long timeout = jiffies + HZ;
1365 xm_write16(hw, port,
1366 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1368 /* wait for update to complete */
1369 while (xm_read16(hw, port, XM_STAT_CMD)
1370 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1371 if (time_after(jiffies, timeout))
1376 /* special case for 64 bit octet counter */
1377 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_TXO_OK_LO);
1379 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1380 | xm_read32(hw, port, XM_RXO_OK_LO);
1382 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1383 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1386 static void genesis_mac_intr(struct skge_hw *hw, int port)
1388 struct skge_port *skge = netdev_priv(hw->dev[port]);
1389 u16 status = xm_read16(hw, port, XM_ISRC);
1391 if (netif_msg_intr(skge))
1392 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1393 skge->netdev->name, status);
1395 if (status & XM_IS_TXF_UR) {
1396 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1397 ++skge->net_stats.tx_fifo_errors;
1399 if (status & XM_IS_RXF_OV) {
1400 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1401 ++skge->net_stats.rx_fifo_errors;
1405 static void genesis_link_up(struct skge_port *skge)
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1412 cmd = xm_read16(hw, port, XM_MMU_CMD);
1415 * enabling pause frame reception is required for 1000BT
1416 * because the XMAC is not reset if the link is going down
1418 if (skge->flow_control == FLOW_MODE_NONE ||
1419 skge->flow_control == FLOW_MODE_LOC_SEND)
1420 /* Disable Pause Frame Reception */
1421 cmd |= XM_MMU_IGN_PF;
1423 /* Enable Pause Frame Reception */
1424 cmd &= ~XM_MMU_IGN_PF;
1426 xm_write16(hw, port, XM_MMU_CMD, cmd);
1428 mode = xm_read32(hw, port, XM_MODE);
1429 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1430 skge->flow_control == FLOW_MODE_LOC_SEND) {
1432 * Configure Pause Frame Generation
1433 * Use internal and external Pause Frame Generation.
1434 * Sending pause frames is edge triggered.
1435 * Send a Pause frame with the maximum pause time if
1436 * internal oder external FIFO full condition occurs.
1437 * Send a zero pause time frame to re-start transmission.
1439 /* XM_PAUSE_DA = '010000C28001' (default) */
1440 /* XM_MAC_PTIME = 0xffff (maximum) */
1441 /* remember this value is defined in big endian (!) */
1442 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1444 mode |= XM_PAUSE_MODE;
1445 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1448 * disable pause frame generation is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1451 /* Disable Pause Mode in Mode Register */
1452 mode &= ~XM_PAUSE_MODE;
1454 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1457 xm_write32(hw, port, XM_MODE, mode);
1460 /* disable GP0 interrupt bit for external Phy */
1461 msk |= XM_IS_INP_ASS;
1463 xm_write16(hw, port, XM_IMSK, msk);
1464 xm_read16(hw, port, XM_ISRC);
1466 /* get MMU Command Reg. */
1467 cmd = xm_read16(hw, port, XM_MMU_CMD);
1468 if (skge->duplex == DUPLEX_FULL)
1469 cmd |= XM_MMU_GMII_FD;
1472 * Workaround BCOM Errata (#10523) for all BCom Phys
1473 * Enable Power Management after link up
1475 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1476 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1477 & ~PHY_B_AC_DIS_PM);
1478 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1481 xm_write16(hw, port, XM_MMU_CMD,
1482 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1487 static inline void bcom_phy_intr(struct skge_port *skge)
1489 struct skge_hw *hw = skge->hw;
1490 int port = skge->port;
1493 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1494 if (netif_msg_intr(skge))
1495 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1496 skge->netdev->name, isrc);
1498 if (isrc & PHY_B_IS_PSE)
1499 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1500 hw->dev[port]->name);
1502 /* Workaround BCom Errata:
1503 * enable and disable loopback mode if "NO HCD" occurs.
1505 if (isrc & PHY_B_IS_NO_HDCL) {
1506 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1507 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1508 ctrl | PHY_CT_LOOP);
1509 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1510 ctrl & ~PHY_CT_LOOP);
1513 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1514 bcom_check_link(hw, port);
1518 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1522 gma_write16(hw, port, GM_SMI_DATA, val);
1523 gma_write16(hw, port, GM_SMI_CTRL,
1524 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1525 for (i = 0; i < PHY_RETRIES; i++) {
1528 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1532 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1533 hw->dev[port]->name);
1537 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1541 gma_write16(hw, port, GM_SMI_CTRL,
1542 GM_SMI_CT_PHY_AD(hw->phy_addr)
1543 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1545 for (i = 0; i < PHY_RETRIES; i++) {
1547 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1553 *val = gma_read16(hw, port, GM_SMI_DATA);
1557 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1560 if (__gm_phy_read(hw, port, reg, &v))
1561 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1562 hw->dev[port]->name);
1566 /* Marvell Phy Initialization */
1567 static void yukon_init(struct skge_hw *hw, int port)
1569 struct skge_port *skge = netdev_priv(hw->dev[port]);
1570 u16 ctrl, ct1000, adv;
1572 if (skge->autoneg == AUTONEG_ENABLE) {
1573 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1575 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1576 PHY_M_EC_MAC_S_MSK);
1577 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1579 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1581 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1584 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1585 if (skge->autoneg == AUTONEG_DISABLE)
1586 ctrl &= ~PHY_CT_ANE;
1588 ctrl |= PHY_CT_RESET;
1589 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1595 if (skge->autoneg == AUTONEG_ENABLE) {
1597 if (skge->advertising & ADVERTISED_1000baseT_Full)
1598 ct1000 |= PHY_M_1000C_AFD;
1599 if (skge->advertising & ADVERTISED_1000baseT_Half)
1600 ct1000 |= PHY_M_1000C_AHD;
1601 if (skge->advertising & ADVERTISED_100baseT_Full)
1602 adv |= PHY_M_AN_100_FD;
1603 if (skge->advertising & ADVERTISED_100baseT_Half)
1604 adv |= PHY_M_AN_100_HD;
1605 if (skge->advertising & ADVERTISED_10baseT_Full)
1606 adv |= PHY_M_AN_10_FD;
1607 if (skge->advertising & ADVERTISED_10baseT_Half)
1608 adv |= PHY_M_AN_10_HD;
1609 } else /* special defines for FIBER (88E1011S only) */
1610 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1612 /* Set Flow-control capabilities */
1613 adv |= phy_pause_map[skge->flow_control];
1615 /* Restart Auto-negotiation */
1616 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1618 /* forced speed/duplex settings */
1619 ct1000 = PHY_M_1000C_MSE;
1621 if (skge->duplex == DUPLEX_FULL)
1622 ctrl |= PHY_CT_DUP_MD;
1624 switch (skge->speed) {
1626 ctrl |= PHY_CT_SP1000;
1629 ctrl |= PHY_CT_SP100;
1633 ctrl |= PHY_CT_RESET;
1636 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1638 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1639 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1641 /* Enable phy interrupt on autonegotiation complete (or link up) */
1642 if (skge->autoneg == AUTONEG_ENABLE)
1643 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1645 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1648 static void yukon_reset(struct skge_hw *hw, int port)
1650 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1651 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1652 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1656 gma_write16(hw, port, GM_RX_CTRL,
1657 gma_read16(hw, port, GM_RX_CTRL)
1658 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1661 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1662 static int is_yukon_lite_a0(struct skge_hw *hw)
1667 if (hw->chip_id != CHIP_ID_YUKON)
1670 reg = skge_read32(hw, B2_FAR);
1671 skge_write8(hw, B2_FAR + 3, 0xff);
1672 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1673 skge_write32(hw, B2_FAR, reg);
1677 static void yukon_mac_init(struct skge_hw *hw, int port)
1679 struct skge_port *skge = netdev_priv(hw->dev[port]);
1682 const u8 *addr = hw->dev[port]->dev_addr;
1684 /* WA code for COMA mode -- set PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1687 reg = skge_read32(hw, B2_GP_IO);
1688 reg |= GP_DIR_9 | GP_IO_9;
1689 skge_write32(hw, B2_GP_IO, reg);
1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1694 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1696 /* WA code for COMA mode -- clear PHY reset */
1697 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1698 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1699 reg = skge_read32(hw, B2_GP_IO);
1702 skge_write32(hw, B2_GP_IO, reg);
1705 /* Set hardware config mode */
1706 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1707 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1708 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1710 /* Clear GMC reset */
1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1713 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1715 if (skge->autoneg == AUTONEG_DISABLE) {
1716 reg = GM_GPCR_AU_ALL_DIS;
1717 gma_write16(hw, port, GM_GP_CTRL,
1718 gma_read16(hw, port, GM_GP_CTRL) | reg);
1720 switch (skge->speed) {
1722 reg &= ~GM_GPCR_SPEED_100;
1723 reg |= GM_GPCR_SPEED_1000;
1726 reg &= ~GM_GPCR_SPEED_1000;
1727 reg |= GM_GPCR_SPEED_100;
1730 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1734 if (skge->duplex == DUPLEX_FULL)
1735 reg |= GM_GPCR_DUP_FULL;
1737 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1739 switch (skge->flow_control) {
1740 case FLOW_MODE_NONE:
1741 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1742 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1744 case FLOW_MODE_LOC_SEND:
1745 /* disable Rx flow-control */
1746 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1749 gma_write16(hw, port, GM_GP_CTRL, reg);
1750 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1752 yukon_init(hw, port);
1755 reg = gma_read16(hw, port, GM_PHY_ADDR);
1756 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1758 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1759 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1760 gma_write16(hw, port, GM_PHY_ADDR, reg);
1762 /* transmit control */
1763 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1765 /* receive control reg: unicast + multicast + no FCS */
1766 gma_write16(hw, port, GM_RX_CTRL,
1767 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1769 /* transmit flow control */
1770 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1772 /* transmit parameter */
1773 gma_write16(hw, port, GM_TX_PARAM,
1774 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1775 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1776 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1778 /* serial mode register */
1779 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1780 if (hw->dev[port]->mtu > 1500)
1781 reg |= GM_SMOD_JUMBO_ENA;
1783 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1785 /* physical address: used for pause frames */
1786 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1787 /* virtual address for data */
1788 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1790 /* enable interrupt mask for counter overflows */
1791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1795 /* Initialize Mac Fifo */
1797 /* Configure Rx MAC FIFO */
1798 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1799 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1801 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1802 if (is_yukon_lite_a0(hw))
1803 reg &= ~GMF_RX_F_FL_ON;
1805 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1806 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1808 * because Pause Packet Truncation in GMAC is not working
1809 * we have to increase the Flush Threshold to 64 bytes
1810 * in order to flush pause packets in Rx FIFO on Yukon-1
1812 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1814 /* Configure Tx MAC FIFO */
1815 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1816 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1819 /* Go into power down mode */
1820 static void yukon_suspend(struct skge_hw *hw, int port)
1824 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1825 ctrl |= PHY_M_PC_POL_R_DIS;
1826 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1828 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1829 ctrl |= PHY_CT_RESET;
1830 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1832 /* switch IEEE compatible power down mode on */
1833 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1834 ctrl |= PHY_CT_PDOWN;
1835 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1838 static void yukon_stop(struct skge_port *skge)
1840 struct skge_hw *hw = skge->hw;
1841 int port = skge->port;
1843 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1844 yukon_reset(hw, port);
1846 gma_write16(hw, port, GM_GP_CTRL,
1847 gma_read16(hw, port, GM_GP_CTRL)
1848 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1849 gma_read16(hw, port, GM_GP_CTRL);
1851 yukon_suspend(hw, port);
1853 /* set GPHY Control reset */
1854 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1855 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1858 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
1864 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1865 | gma_read32(hw, port, GM_TXO_OK_LO);
1866 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1867 | gma_read32(hw, port, GM_RXO_OK_LO);
1869 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1870 data[i] = gma_read32(hw, port,
1871 skge_stats[i].gma_offset);
1874 static void yukon_mac_intr(struct skge_hw *hw, int port)
1876 struct net_device *dev = hw->dev[port];
1877 struct skge_port *skge = netdev_priv(dev);
1878 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1880 if (netif_msg_intr(skge))
1881 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1884 if (status & GM_IS_RX_FF_OR) {
1885 ++skge->net_stats.rx_fifo_errors;
1886 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1889 if (status & GM_IS_TX_FF_UR) {
1890 ++skge->net_stats.tx_fifo_errors;
1891 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1896 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1898 switch (aux & PHY_M_PS_SPEED_MSK) {
1899 case PHY_M_PS_SPEED_1000:
1901 case PHY_M_PS_SPEED_100:
1908 static void yukon_link_up(struct skge_port *skge)
1910 struct skge_hw *hw = skge->hw;
1911 int port = skge->port;
1914 /* Enable Transmit FIFO Underrun */
1915 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1917 reg = gma_read16(hw, port, GM_GP_CTRL);
1918 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1919 reg |= GM_GPCR_DUP_FULL;
1922 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1923 gma_write16(hw, port, GM_GP_CTRL, reg);
1925 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1929 static void yukon_link_down(struct skge_port *skge)
1931 struct skge_hw *hw = skge->hw;
1932 int port = skge->port;
1935 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1937 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1938 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1939 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1941 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1942 /* restore Asymmetric Pause bit */
1943 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1944 gm_phy_read(hw, port,
1950 yukon_reset(hw, port);
1951 skge_link_down(skge);
1953 yukon_init(hw, port);
1956 static void yukon_phy_intr(struct skge_port *skge)
1958 struct skge_hw *hw = skge->hw;
1959 int port = skge->port;
1960 const char *reason = NULL;
1961 u16 istatus, phystat;
1963 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1964 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1966 if (netif_msg_intr(skge))
1967 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1968 skge->netdev->name, istatus, phystat);
1970 if (istatus & PHY_M_IS_AN_COMPL) {
1971 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1973 reason = "remote fault";
1977 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1978 reason = "master/slave fault";
1982 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1983 reason = "speed/duplex";
1987 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1988 ? DUPLEX_FULL : DUPLEX_HALF;
1989 skge->speed = yukon_speed(hw, phystat);
1991 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1992 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1993 case PHY_M_PS_PAUSE_MSK:
1994 skge->flow_control = FLOW_MODE_SYMMETRIC;
1996 case PHY_M_PS_RX_P_EN:
1997 skge->flow_control = FLOW_MODE_REM_SEND;
1999 case PHY_M_PS_TX_P_EN:
2000 skge->flow_control = FLOW_MODE_LOC_SEND;
2003 skge->flow_control = FLOW_MODE_NONE;
2006 if (skge->flow_control == FLOW_MODE_NONE ||
2007 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2008 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2010 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2011 yukon_link_up(skge);
2015 if (istatus & PHY_M_IS_LSP_CHANGE)
2016 skge->speed = yukon_speed(hw, phystat);
2018 if (istatus & PHY_M_IS_DUP_CHANGE)
2019 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2020 if (istatus & PHY_M_IS_LST_CHANGE) {
2021 if (phystat & PHY_M_PS_LINK_UP)
2022 yukon_link_up(skge);
2024 yukon_link_down(skge);
2028 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2029 skge->netdev->name, reason);
2031 /* XXX restart autonegotiation? */
2034 static void skge_phy_reset(struct skge_port *skge)
2036 struct skge_hw *hw = skge->hw;
2037 int port = skge->port;
2039 netif_stop_queue(skge->netdev);
2040 netif_carrier_off(skge->netdev);
2042 spin_lock_bh(&hw->phy_lock);
2043 if (hw->chip_id == CHIP_ID_GENESIS) {
2044 genesis_reset(hw, port);
2045 genesis_mac_init(hw, port);
2047 yukon_reset(hw, port);
2048 yukon_init(hw, port);
2050 spin_unlock_bh(&hw->phy_lock);
2053 /* Basic MII support */
2054 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056 struct mii_ioctl_data *data = if_mii(ifr);
2057 struct skge_port *skge = netdev_priv(dev);
2058 struct skge_hw *hw = skge->hw;
2059 int err = -EOPNOTSUPP;
2061 if (!netif_running(dev))
2062 return -ENODEV; /* Phy still in reset */
2066 data->phy_id = hw->phy_addr;
2071 spin_lock_bh(&hw->phy_lock);
2072 if (hw->chip_id == CHIP_ID_GENESIS)
2073 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2076 spin_unlock_bh(&hw->phy_lock);
2077 data->val_out = val;
2082 if (!capable(CAP_NET_ADMIN))
2085 spin_lock_bh(&hw->phy_lock);
2086 if (hw->chip_id == CHIP_ID_GENESIS)
2087 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2090 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2092 spin_unlock_bh(&hw->phy_lock);
2098 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2104 end = start + len - 1;
2106 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2107 skge_write32(hw, RB_ADDR(q, RB_START), start);
2108 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_END), end);
2112 if (q == Q_R1 || q == Q_R2) {
2113 /* Set thresholds on receive queue's */
2114 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2116 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2119 /* Enable store & forward on Tx queue's because
2120 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2122 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2125 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2128 /* Setup Bus Memory Interface */
2129 static void skge_qset(struct skge_port *skge, u16 q,
2130 const struct skge_element *e)
2132 struct skge_hw *hw = skge->hw;
2133 u32 watermark = 0x600;
2134 u64 base = skge->dma + (e->desc - skge->mem);
2136 /* optimization to reduce window on 32bit/33mhz */
2137 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2140 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2141 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2142 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2143 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2146 static int skge_up(struct net_device *dev)
2148 struct skge_port *skge = netdev_priv(dev);
2149 struct skge_hw *hw = skge->hw;
2150 int port = skge->port;
2151 u32 chunk, ram_addr;
2152 size_t rx_size, tx_size;
2155 if (netif_msg_ifup(skge))
2156 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2158 if (dev->mtu > RX_BUF_SIZE)
2159 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2161 skge->rx_buf_size = RX_BUF_SIZE;
2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size;
2167 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2171 BUG_ON(skge->dma & 7);
2173 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2174 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2179 memset(skge->mem, 0, skge->mem_size);
2181 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2184 err = skge_rx_fill(skge);
2188 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2189 skge->dma + rx_size)))
2192 skge->tx_avail = skge->tx_ring.count - 1;
2194 /* Initialize MAC */
2195 spin_lock_bh(&hw->phy_lock);
2196 if (hw->chip_id == CHIP_ID_GENESIS)
2197 genesis_mac_init(hw, port);
2199 yukon_mac_init(hw, port);
2200 spin_unlock_bh(&hw->phy_lock);
2202 /* Configure RAMbuffers */
2203 chunk = hw->ram_size / ((hw->ports + 1)*2);
2204 ram_addr = hw->ram_offset + 2 * chunk * port;
2206 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2207 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2209 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2210 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2211 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2213 /* Start receiver BMU */
2215 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2216 skge_led(skge, LED_MODE_ON);
2221 skge_rx_clean(skge);
2222 kfree(skge->rx_ring.start);
2224 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2230 static int skge_down(struct net_device *dev)
2232 struct skge_port *skge = netdev_priv(dev);
2233 struct skge_hw *hw = skge->hw;
2234 int port = skge->port;
2236 if (skge->mem == NULL)
2239 if (netif_msg_ifdown(skge))
2240 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2242 netif_stop_queue(dev);
2244 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2245 if (hw->chip_id == CHIP_ID_GENESIS)
2250 /* Stop transmitter */
2251 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2252 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2253 RB_RST_SET|RB_DIS_OP_MD);
2256 /* Disable Force Sync bit and Enable Alloc bit */
2257 skge_write8(hw, SK_REG(port, TXA_CTRL),
2258 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2260 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2261 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2262 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2264 /* Reset PCI FIFO */
2265 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2266 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2268 /* Reset the RAM Buffer async Tx queue */
2269 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2271 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2272 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2273 RB_RST_SET|RB_DIS_OP_MD);
2274 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2276 if (hw->chip_id == CHIP_ID_GENESIS) {
2277 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2278 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2281 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2284 skge_led(skge, LED_MODE_OFF);
2286 skge_tx_clean(skge);
2287 skge_rx_clean(skge);
2289 kfree(skge->rx_ring.start);
2290 kfree(skge->tx_ring.start);
2291 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2296 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2298 struct skge_port *skge = netdev_priv(dev);
2299 struct skge_hw *hw = skge->hw;
2300 struct skge_ring *ring = &skge->tx_ring;
2301 struct skge_element *e;
2302 struct skge_tx_desc *td;
2307 skb = skb_padto(skb, ETH_ZLEN);
2309 return NETDEV_TX_OK;
2311 if (!spin_trylock(&skge->tx_lock)) {
2312 /* Collision - tell upper layer to requeue */
2313 return NETDEV_TX_LOCKED;
2316 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2317 if (!netif_queue_stopped(dev)) {
2318 netif_stop_queue(dev);
2320 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2323 spin_unlock(&skge->tx_lock);
2324 return NETDEV_TX_BUSY;
2330 len = skb_headlen(skb);
2331 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2332 pci_unmap_addr_set(e, mapaddr, map);
2333 pci_unmap_len_set(e, maplen, len);
2336 td->dma_hi = map >> 32;
2338 if (skb->ip_summed == CHECKSUM_HW) {
2339 int offset = skb->h.raw - skb->data;
2341 /* This seems backwards, but it is what the sk98lin
2342 * does. Looks like hardware is wrong?
2344 if (skb->h.ipiph->protocol == IPPROTO_UDP
2345 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2346 control = BMU_TCP_CHECK;
2348 control = BMU_UDP_CHECK;
2351 td->csum_start = offset;
2352 td->csum_write = offset + skb->csum;
2354 control = BMU_CHECK;
2356 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2357 control |= BMU_EOF| BMU_IRQ_EOF;
2359 struct skge_tx_desc *tf = td;
2361 control |= BMU_STFWD;
2362 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2363 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2365 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2366 frag->size, PCI_DMA_TODEVICE);
2372 tf->dma_hi = (u64) map >> 32;
2373 pci_unmap_addr_set(e, mapaddr, map);
2374 pci_unmap_len_set(e, maplen, frag->size);
2376 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2378 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2380 /* Make sure all the descriptors written */
2382 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2385 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2387 if (netif_msg_tx_queued(skge))
2388 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2389 dev->name, e - ring->start, skb->len);
2391 ring->to_use = e->next;
2392 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2393 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2394 pr_debug("%s: transmit queue full\n", dev->name);
2395 netif_stop_queue(dev);
2398 dev->trans_start = jiffies;
2399 spin_unlock(&skge->tx_lock);
2401 return NETDEV_TX_OK;
2404 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2406 /* This ring element can be skb or fragment */
2408 pci_unmap_single(hw->pdev,
2409 pci_unmap_addr(e, mapaddr),
2410 pci_unmap_len(e, maplen),
2412 dev_kfree_skb(e->skb);
2415 pci_unmap_page(hw->pdev,
2416 pci_unmap_addr(e, mapaddr),
2417 pci_unmap_len(e, maplen),
2422 static void skge_tx_clean(struct skge_port *skge)
2424 struct skge_ring *ring = &skge->tx_ring;
2425 struct skge_element *e;
2427 spin_lock_bh(&skge->tx_lock);
2428 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2430 skge_tx_free(skge->hw, e);
2433 spin_unlock_bh(&skge->tx_lock);
2436 static void skge_tx_timeout(struct net_device *dev)
2438 struct skge_port *skge = netdev_priv(dev);
2440 if (netif_msg_timer(skge))
2441 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2443 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2444 skge_tx_clean(skge);
2447 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2451 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2454 if (!netif_running(dev)) {
2470 static void genesis_set_multicast(struct net_device *dev)
2472 struct skge_port *skge = netdev_priv(dev);
2473 struct skge_hw *hw = skge->hw;
2474 int port = skge->port;
2475 int i, count = dev->mc_count;
2476 struct dev_mc_list *list = dev->mc_list;
2480 mode = xm_read32(hw, port, XM_MODE);
2481 mode |= XM_MD_ENA_HASH;
2482 if (dev->flags & IFF_PROMISC)
2483 mode |= XM_MD_ENA_PROM;
2485 mode &= ~XM_MD_ENA_PROM;
2487 if (dev->flags & IFF_ALLMULTI)
2488 memset(filter, 0xff, sizeof(filter));
2490 memset(filter, 0, sizeof(filter));
2491 for (i = 0; list && i < count; i++, list = list->next) {
2493 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2495 filter[bit/8] |= 1 << (bit%8);
2499 xm_write32(hw, port, XM_MODE, mode);
2500 xm_outhash(hw, port, XM_HSM, filter);
2503 static void yukon_set_multicast(struct net_device *dev)
2505 struct skge_port *skge = netdev_priv(dev);
2506 struct skge_hw *hw = skge->hw;
2507 int port = skge->port;
2508 struct dev_mc_list *list = dev->mc_list;
2512 memset(filter, 0, sizeof(filter));
2514 reg = gma_read16(hw, port, GM_RX_CTRL);
2515 reg |= GM_RXCR_UCF_ENA;
2517 if (dev->flags & IFF_PROMISC) /* promiscuous */
2518 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2519 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2520 memset(filter, 0xff, sizeof(filter));
2521 else if (dev->mc_count == 0) /* no multicast */
2522 reg &= ~GM_RXCR_MCF_ENA;
2525 reg |= GM_RXCR_MCF_ENA;
2527 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2528 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2529 filter[bit/8] |= 1 << (bit%8);
2534 gma_write16(hw, port, GM_MC_ADDR_H1,
2535 (u16)filter[0] | ((u16)filter[1] << 8));
2536 gma_write16(hw, port, GM_MC_ADDR_H2,
2537 (u16)filter[2] | ((u16)filter[3] << 8));
2538 gma_write16(hw, port, GM_MC_ADDR_H3,
2539 (u16)filter[4] | ((u16)filter[5] << 8));
2540 gma_write16(hw, port, GM_MC_ADDR_H4,
2541 (u16)filter[6] | ((u16)filter[7] << 8));
2543 gma_write16(hw, port, GM_RX_CTRL, reg);
2546 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2548 if (hw->chip_id == CHIP_ID_GENESIS)
2549 return status >> XMR_FS_LEN_SHIFT;
2551 return status >> GMR_FS_LEN_SHIFT;
2554 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2556 if (hw->chip_id == CHIP_ID_GENESIS)
2557 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2559 return (status & GMR_FS_ANY_ERR) ||
2560 (status & GMR_FS_RX_OK) == 0;
2564 /* Get receive buffer from descriptor.
2565 * Handles copy of small buffers and reallocation failures
2567 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2568 struct skge_element *e,
2569 u32 control, u32 status, u16 csum)
2571 struct sk_buff *skb;
2572 u16 len = control & BMU_BBC;
2574 if (unlikely(netif_msg_rx_status(skge)))
2575 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2576 skge->netdev->name, e - skge->rx_ring.start,
2579 if (len > skge->rx_buf_size)
2582 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2585 if (bad_phy_status(skge->hw, status))
2588 if (phy_length(skge->hw, status) != len)
2591 if (len < RX_COPY_THRESHOLD) {
2592 skb = dev_alloc_skb(len + 2);
2596 skb_reserve(skb, 2);
2597 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2598 pci_unmap_addr(e, mapaddr),
2599 len, PCI_DMA_FROMDEVICE);
2600 memcpy(skb->data, e->skb->data, len);
2601 pci_dma_sync_single_for_device(skge->hw->pdev,
2602 pci_unmap_addr(e, mapaddr),
2603 len, PCI_DMA_FROMDEVICE);
2604 skge_rx_reuse(e, skge->rx_buf_size);
2606 struct sk_buff *nskb;
2607 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2611 pci_unmap_single(skge->hw->pdev,
2612 pci_unmap_addr(e, mapaddr),
2613 pci_unmap_len(e, maplen),
2614 PCI_DMA_FROMDEVICE);
2616 prefetch(skb->data);
2617 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2621 skb->dev = skge->netdev;
2622 if (skge->rx_csum) {
2624 skb->ip_summed = CHECKSUM_HW;
2627 skb->protocol = eth_type_trans(skb, skge->netdev);
2632 if (netif_msg_rx_err(skge))
2633 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2634 skge->netdev->name, e - skge->rx_ring.start,
2637 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2638 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2639 skge->net_stats.rx_length_errors++;
2640 if (status & XMR_FS_FRA_ERR)
2641 skge->net_stats.rx_frame_errors++;
2642 if (status & XMR_FS_FCS_ERR)
2643 skge->net_stats.rx_crc_errors++;
2645 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2646 skge->net_stats.rx_length_errors++;
2647 if (status & GMR_FS_FRAGMENT)
2648 skge->net_stats.rx_frame_errors++;
2649 if (status & GMR_FS_CRC_ERR)
2650 skge->net_stats.rx_crc_errors++;
2654 skge_rx_reuse(e, skge->rx_buf_size);
2658 static void skge_tx_done(struct skge_port *skge)
2660 struct skge_ring *ring = &skge->tx_ring;
2661 struct skge_element *e;
2663 spin_lock(&skge->tx_lock);
2664 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2665 struct skge_tx_desc *td = e->desc;
2669 control = td->control;
2670 if (control & BMU_OWN)
2673 if (unlikely(netif_msg_tx_done(skge)))
2674 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2675 skge->netdev->name, e - ring->start, td->status);
2677 skge_tx_free(skge->hw, e);
2682 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2684 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2685 netif_wake_queue(skge->netdev);
2687 spin_unlock(&skge->tx_lock);
2690 static int skge_poll(struct net_device *dev, int *budget)
2692 struct skge_port *skge = netdev_priv(dev);
2693 struct skge_hw *hw = skge->hw;
2694 struct skge_ring *ring = &skge->rx_ring;
2695 struct skge_element *e;
2696 int to_do = min(dev->quota, *budget);
2701 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2702 struct skge_rx_desc *rd = e->desc;
2703 struct sk_buff *skb;
2707 control = rd->control;
2708 if (control & BMU_OWN)
2711 skb = skge_rx_get(skge, e, control, rd->status,
2712 le16_to_cpu(rd->csum2));
2714 dev->last_rx = jiffies;
2715 netif_receive_skb(skb);
2719 skge_rx_reuse(e, skge->rx_buf_size);
2723 /* restart receiver */
2725 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2727 *budget -= work_done;
2728 dev->quota -= work_done;
2730 if (work_done >= to_do)
2731 return 1; /* not done */
2733 netif_rx_complete(dev);
2734 hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
2735 skge_write32(hw, B0_IMSK, hw->intr_mask);
2740 /* Parity errors seem to happen when Genesis is connected to a switch
2741 * with no other ports present. Heartbeat error??
2743 static void skge_mac_parity(struct skge_hw *hw, int port)
2745 struct net_device *dev = hw->dev[port];
2748 struct skge_port *skge = netdev_priv(dev);
2749 ++skge->net_stats.tx_heartbeat_errors;
2752 if (hw->chip_id == CHIP_ID_GENESIS)
2753 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2756 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2757 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2758 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2759 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2762 static void skge_pci_clear(struct skge_hw *hw)
2766 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2767 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2768 pci_write_config_word(hw->pdev, PCI_STATUS,
2769 status | PCI_STATUS_ERROR_BITS);
2770 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2773 static void skge_mac_intr(struct skge_hw *hw, int port)
2775 if (hw->chip_id == CHIP_ID_GENESIS)
2776 genesis_mac_intr(hw, port);
2778 yukon_mac_intr(hw, port);
2781 /* Handle device specific framing and timeout interrupts */
2782 static void skge_error_irq(struct skge_hw *hw)
2784 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2786 if (hw->chip_id == CHIP_ID_GENESIS) {
2787 /* clear xmac errors */
2788 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2789 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2790 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2791 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2793 /* Timestamp (unused) overflow */
2794 if (hwstatus & IS_IRQ_TIST_OV)
2795 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2798 if (hwstatus & IS_RAM_RD_PAR) {
2799 printk(KERN_ERR PFX "Ram read data parity error\n");
2800 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2803 if (hwstatus & IS_RAM_WR_PAR) {
2804 printk(KERN_ERR PFX "Ram write data parity error\n");
2805 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2808 if (hwstatus & IS_M1_PAR_ERR)
2809 skge_mac_parity(hw, 0);
2811 if (hwstatus & IS_M2_PAR_ERR)
2812 skge_mac_parity(hw, 1);
2814 if (hwstatus & IS_R1_PAR_ERR)
2815 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2817 if (hwstatus & IS_R2_PAR_ERR)
2818 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2820 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2821 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2826 /* if error still set then just ignore it */
2827 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2828 if (hwstatus & IS_IRQ_STAT) {
2829 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2831 hw->intr_mask &= ~IS_HW_ERR;
2837 * Interrupt from PHY are handled in tasklet (soft irq)
2838 * because accessing phy registers requires spin wait which might
2839 * cause excess interrupt latency.
2841 static void skge_extirq(unsigned long data)
2843 struct skge_hw *hw = (struct skge_hw *) data;
2846 spin_lock(&hw->phy_lock);
2847 for (port = 0; port < hw->ports; port++) {
2848 struct net_device *dev = hw->dev[port];
2849 struct skge_port *skge = netdev_priv(dev);
2851 if (netif_running(dev)) {
2852 if (hw->chip_id != CHIP_ID_GENESIS)
2853 yukon_phy_intr(skge);
2855 bcom_phy_intr(skge);
2858 spin_unlock(&hw->phy_lock);
2860 hw->intr_mask |= IS_EXT_REG;
2861 skge_write32(hw, B0_IMSK, hw->intr_mask);
2864 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2866 struct skge_hw *hw = dev_id;
2869 /* Reading this register masks IRQ */
2870 status = skge_read32(hw, B0_SP_ISRC);
2874 if (status & IS_EXT_REG) {
2875 hw->intr_mask &= ~IS_EXT_REG;
2876 tasklet_schedule(&hw->ext_tasklet);
2879 if (status & (IS_R1_F|IS_XA1_F)) {
2880 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2881 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
2882 netif_rx_schedule(hw->dev[0]);
2885 if (status & (IS_R2_F|IS_XA2_F)) {
2886 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2887 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
2888 netif_rx_schedule(hw->dev[1]);
2891 if (likely((status & hw->intr_mask) == 0))
2894 if (status & IS_PA_TO_RX1) {
2895 struct skge_port *skge = netdev_priv(hw->dev[0]);
2896 ++skge->net_stats.rx_over_errors;
2897 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2900 if (status & IS_PA_TO_RX2) {
2901 struct skge_port *skge = netdev_priv(hw->dev[1]);
2902 ++skge->net_stats.rx_over_errors;
2903 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2906 if (status & IS_PA_TO_TX1)
2907 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2909 if (status & IS_PA_TO_TX2)
2910 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2912 if (status & IS_MAC1)
2913 skge_mac_intr(hw, 0);
2915 if (status & IS_MAC2)
2916 skge_mac_intr(hw, 1);
2918 if (status & IS_HW_ERR)
2921 skge_write32(hw, B0_IMSK, hw->intr_mask);
2926 #ifdef CONFIG_NET_POLL_CONTROLLER
2927 static void skge_netpoll(struct net_device *dev)
2929 struct skge_port *skge = netdev_priv(dev);
2931 disable_irq(dev->irq);
2932 skge_intr(dev->irq, skge->hw, NULL);
2933 enable_irq(dev->irq);
2937 static int skge_set_mac_address(struct net_device *dev, void *p)
2939 struct skge_port *skge = netdev_priv(dev);
2940 struct skge_hw *hw = skge->hw;
2941 unsigned port = skge->port;
2942 const struct sockaddr *addr = p;
2944 if (!is_valid_ether_addr(addr->sa_data))
2945 return -EADDRNOTAVAIL;
2947 spin_lock_bh(&hw->phy_lock);
2948 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2949 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2950 dev->dev_addr, ETH_ALEN);
2951 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2952 dev->dev_addr, ETH_ALEN);
2954 if (hw->chip_id == CHIP_ID_GENESIS)
2955 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2957 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2958 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2960 spin_unlock_bh(&hw->phy_lock);
2965 static const struct {
2969 { CHIP_ID_GENESIS, "Genesis" },
2970 { CHIP_ID_YUKON, "Yukon" },
2971 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2972 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2975 static const char *skge_board_name(const struct skge_hw *hw)
2978 static char buf[16];
2980 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2981 if (skge_chips[i].id == hw->chip_id)
2982 return skge_chips[i].name;
2984 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2990 * Setup the board data structure, but don't bring up
2993 static int skge_reset(struct skge_hw *hw)
2997 u8 t8, mac_cfg, pmd_type, phy_type;
3000 ctst = skge_read16(hw, B0_CTST);
3003 skge_write8(hw, B0_CTST, CS_RST_SET);
3004 skge_write8(hw, B0_CTST, CS_RST_CLR);
3006 /* clear PCI errors, if any */
3009 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3011 /* restore CLK_RUN bits (for Yukon-Lite) */
3012 skge_write16(hw, B0_CTST,
3013 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3015 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3016 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3017 pmd_type = skge_read8(hw, B2_PMD_TYP);
3018 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3020 switch (hw->chip_id) {
3021 case CHIP_ID_GENESIS:
3024 hw->phy_addr = PHY_ADDR_BCOM;
3027 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3028 pci_name(hw->pdev), phy_type);
3034 case CHIP_ID_YUKON_LITE:
3035 case CHIP_ID_YUKON_LP:
3036 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3039 hw->phy_addr = PHY_ADDR_MARV;
3043 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3044 pci_name(hw->pdev), hw->chip_id);
3048 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3049 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3050 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3052 /* read the adapters RAM size */
3053 t8 = skge_read8(hw, B2_E_0);
3054 if (hw->chip_id == CHIP_ID_GENESIS) {
3056 /* special case: 4 x 64k x 36, offset = 0x80000 */
3057 hw->ram_size = 0x100000;
3058 hw->ram_offset = 0x80000;
3060 hw->ram_size = t8 * 512;
3063 hw->ram_size = 0x20000;
3065 hw->ram_size = t8 * 4096;
3067 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3069 hw->intr_mask |= IS_PORT_2;
3071 if (hw->chip_id == CHIP_ID_GENESIS)
3074 /* switch power to VCC (WA for VAUX problem) */
3075 skge_write8(hw, B0_POWER_CTRL,
3076 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3078 /* avoid boards with stuck Hardware error bits */
3079 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3080 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3081 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3082 hw->intr_mask &= ~IS_HW_ERR;
3085 /* Clear PHY COMA */
3086 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3087 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3088 reg &= ~PCI_PHY_COMA;
3089 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3090 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3093 for (i = 0; i < hw->ports; i++) {
3094 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3095 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3099 /* turn off hardware timer (unused) */
3100 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3101 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3102 skge_write8(hw, B0_LED, LED_STAT_ON);
3104 /* enable the Tx Arbiters */
3105 for (i = 0; i < hw->ports; i++)
3106 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3108 /* Initialize ram interface */
3109 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3111 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3112 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3113 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3114 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3115 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3116 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3117 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3118 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3119 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3120 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3121 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3122 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3124 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3126 /* Set interrupt moderation for Transmit only
3127 * Receive interrupts avoided by NAPI
3129 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3130 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3131 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3133 skge_write32(hw, B0_IMSK, hw->intr_mask);
3135 spin_lock_bh(&hw->phy_lock);
3136 for (i = 0; i < hw->ports; i++) {
3137 if (hw->chip_id == CHIP_ID_GENESIS)
3138 genesis_reset(hw, i);
3142 spin_unlock_bh(&hw->phy_lock);
3147 /* Initialize network device */
3148 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3151 struct skge_port *skge;
3152 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3155 printk(KERN_ERR "skge etherdev alloc failed");
3159 SET_MODULE_OWNER(dev);
3160 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3161 dev->open = skge_up;
3162 dev->stop = skge_down;
3163 dev->do_ioctl = skge_ioctl;
3164 dev->hard_start_xmit = skge_xmit_frame;
3165 dev->get_stats = skge_get_stats;
3166 if (hw->chip_id == CHIP_ID_GENESIS)
3167 dev->set_multicast_list = genesis_set_multicast;
3169 dev->set_multicast_list = yukon_set_multicast;
3171 dev->set_mac_address = skge_set_mac_address;
3172 dev->change_mtu = skge_change_mtu;
3173 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3174 dev->tx_timeout = skge_tx_timeout;
3175 dev->watchdog_timeo = TX_WATCHDOG;
3176 dev->poll = skge_poll;
3177 dev->weight = NAPI_WEIGHT;
3178 #ifdef CONFIG_NET_POLL_CONTROLLER
3179 dev->poll_controller = skge_netpoll;
3181 dev->irq = hw->pdev->irq;
3182 dev->features = NETIF_F_LLTX;
3184 dev->features |= NETIF_F_HIGHDMA;
3186 skge = netdev_priv(dev);
3189 skge->msg_enable = netif_msg_init(debug, default_msg);
3190 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3191 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3193 /* Auto speed and flow control */
3194 skge->autoneg = AUTONEG_ENABLE;
3195 skge->flow_control = FLOW_MODE_SYMMETRIC;
3198 skge->advertising = skge_supported_modes(hw);
3200 hw->dev[port] = dev;
3204 spin_lock_init(&skge->tx_lock);
3206 if (hw->chip_id != CHIP_ID_GENESIS) {
3207 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3211 /* read the mac address */
3212 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3213 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3215 /* device is off until link detection */
3216 netif_carrier_off(dev);
3217 netif_stop_queue(dev);
3222 static void __devinit skge_show_addr(struct net_device *dev)
3224 const struct skge_port *skge = netdev_priv(dev);
3226 if (netif_msg_probe(skge))
3227 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3229 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3230 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3233 static int __devinit skge_probe(struct pci_dev *pdev,
3234 const struct pci_device_id *ent)
3236 struct net_device *dev, *dev1;
3238 int err, using_dac = 0;
3240 if ((err = pci_enable_device(pdev))) {
3241 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3246 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3247 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3249 goto err_out_disable_pdev;
3252 pci_set_master(pdev);
3254 if (sizeof(dma_addr_t) > sizeof(u32) &&
3255 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3257 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3259 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3260 "for consistent allocations\n", pci_name(pdev));
3261 goto err_out_free_regions;
3264 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3266 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3268 goto err_out_free_regions;
3273 /* byte swap descriptors in hardware */
3277 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3278 reg |= PCI_REV_DESC;
3279 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3284 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3286 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3288 goto err_out_free_regions;
3292 spin_lock_init(&hw->phy_lock);
3293 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3295 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3297 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3299 goto err_out_free_hw;
3302 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3303 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3304 pci_name(pdev), pdev->irq);
3305 goto err_out_iounmap;
3307 pci_set_drvdata(pdev, hw);
3309 err = skge_reset(hw);
3311 goto err_out_free_irq;
3313 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3314 pci_resource_start(pdev, 0), pdev->irq,
3315 skge_board_name(hw), hw->chip_rev);
3317 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3318 goto err_out_led_off;
3320 if ((err = register_netdev(dev))) {
3321 printk(KERN_ERR PFX "%s: cannot register net device\n",
3323 goto err_out_free_netdev;
3326 skge_show_addr(dev);
3328 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3329 if (register_netdev(dev1) == 0)
3330 skge_show_addr(dev1);
3332 /* Failure to register second port need not be fatal */
3333 printk(KERN_WARNING PFX "register of second port failed\n");
3341 err_out_free_netdev:
3344 skge_write16(hw, B0_LED, LED_STAT_OFF);
3346 free_irq(pdev->irq, hw);
3351 err_out_free_regions:
3352 pci_release_regions(pdev);
3353 err_out_disable_pdev:
3354 pci_disable_device(pdev);
3355 pci_set_drvdata(pdev, NULL);
3360 static void __devexit skge_remove(struct pci_dev *pdev)
3362 struct skge_hw *hw = pci_get_drvdata(pdev);
3363 struct net_device *dev0, *dev1;
3368 if ((dev1 = hw->dev[1]))
3369 unregister_netdev(dev1);
3371 unregister_netdev(dev0);
3373 skge_write32(hw, B0_IMSK, 0);
3374 skge_write16(hw, B0_LED, LED_STAT_OFF);
3376 skge_write8(hw, B0_CTST, CS_RST_SET);
3378 tasklet_kill(&hw->ext_tasklet);
3380 free_irq(pdev->irq, hw);
3381 pci_release_regions(pdev);
3382 pci_disable_device(pdev);
3389 pci_set_drvdata(pdev, NULL);
3393 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3395 struct skge_hw *hw = pci_get_drvdata(pdev);
3398 for (i = 0; i < 2; i++) {
3399 struct net_device *dev = hw->dev[i];
3402 struct skge_port *skge = netdev_priv(dev);
3403 if (netif_running(dev)) {
3404 netif_carrier_off(dev);
3406 netif_stop_queue(dev);
3410 netif_device_detach(dev);
3415 pci_save_state(pdev);
3416 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3417 pci_disable_device(pdev);
3418 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3423 static int skge_resume(struct pci_dev *pdev)
3425 struct skge_hw *hw = pci_get_drvdata(pdev);
3428 pci_set_power_state(pdev, PCI_D0);
3429 pci_restore_state(pdev);
3430 pci_enable_wake(pdev, PCI_D0, 0);
3434 for (i = 0; i < 2; i++) {
3435 struct net_device *dev = hw->dev[i];
3437 netif_device_attach(dev);
3438 if (netif_running(dev) && skge_up(dev))
3446 static struct pci_driver skge_driver = {
3448 .id_table = skge_id_table,
3449 .probe = skge_probe,
3450 .remove = __devexit_p(skge_remove),
3452 .suspend = skge_suspend,
3453 .resume = skge_resume,
3457 static int __init skge_init_module(void)
3459 return pci_module_init(&skge_driver);
3462 static void __exit skge_cleanup_module(void)
3464 pci_unregister_driver(&skge_driver);
3467 module_init(skge_init_module);
3468 module_exit(skge_cleanup_module);