drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  * rx_ring_num : This can be used to program the number of receive rings used
  30  * in the driver.
  31  * rx_ring_sz: This defines the number of descriptors each ring can have. This
  32  * is also an array of size 8.
  33  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34  *              values are 1, 2 and 3.
  35  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37  * Tx descriptors that can be associated with each corresponding FIFO.
  38  ************************************************************************/
  39
  40 #include <linux/config.h>
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/errno.h>
  44 #include <linux/ioport.h>
  45 #include <linux/pci.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/kernel.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/init.h>
  52 #include <linux/delay.h>
  53 #include <linux/stddef.h>
  54 #include <linux/ioctl.h>
  55 #include <linux/timex.h>
  56 #include <linux/sched.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/workqueue.h>
  59 #include <linux/if_vlan.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/uaccess.h>
  63 #include <asm/io.h>
  64
  65 /* local include */
  66 #include "s2io.h"
  67 #include "s2io-regs.h"
  68
  69 #define DRV_VERSION "Version 2.0.9.4"
  70
  71 /* S2io Driver name & version. */
  72 static char s2io_driver_name[] = "Neterion";
  73 static char s2io_driver_version[] = DRV_VERSION;
  74
  75 int rxd_size[4] = {32,48,48,64};
  76 int rxd_count[4] = {127,85,85,63};
  77
  78 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  79 {
  80         int ret;
  81
  82         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  83                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  84
  85         return ret;
  86 }
  87
  88 /*
  89  * Cards with following subsystem_id have a link state indication
  90  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  91  * macro below identifies these cards given the subsystem_id.
  92  */
  93 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  94         (dev_type == XFRAME_I_DEVICE) ?                 \
  95                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  96                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  97
  98 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
  99                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 100 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 101 #define PANIC   1
 102 #define LOW     2
 103 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 104 {
 105         int level = 0;
 106         mac_info_t *mac_control;
 107
 108         mac_control = &sp->mac_control;
 109         if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
 110                 level = LOW;
 111                 if (rxb_size <= rxd_count[sp->rxd_mode]) {
 112                         level = PANIC;
 113                 }
 114         }
 115
 116         return level;
 117 }
 118
 119 /* Ethtool related variables and Macros. */
 120 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 121         "Register test\t(offline)",
 122         "Eeprom test\t(offline)",
 123         "Link test\t(online)",
 124         "RLDRAM test\t(offline)",
 125         "BIST Test\t(offline)"
 126 };
 127
 128 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 129         {"tmac_frms"},
 130         {"tmac_data_octets"},
 131         {"tmac_drop_frms"},
 132         {"tmac_mcst_frms"},
 133         {"tmac_bcst_frms"},
 134         {"tmac_pause_ctrl_frms"},
 135         {"tmac_any_err_frms"},
 136         {"tmac_vld_ip_octets"},
 137         {"tmac_vld_ip"},
 138         {"tmac_drop_ip"},
 139         {"tmac_icmp"},
 140         {"tmac_rst_tcp"},
 141         {"tmac_tcp"},
 142         {"tmac_udp"},
 143         {"rmac_vld_frms"},
 144         {"rmac_data_octets"},
 145         {"rmac_fcs_err_frms"},
 146         {"rmac_drop_frms"},
 147         {"rmac_vld_mcst_frms"},
 148         {"rmac_vld_bcst_frms"},
 149         {"rmac_in_rng_len_err_frms"},
 150         {"rmac_long_frms"},
 151         {"rmac_pause_ctrl_frms"},
 152         {"rmac_discarded_frms"},
 153         {"rmac_usized_frms"},
 154         {"rmac_osized_frms"},
 155         {"rmac_frag_frms"},
 156         {"rmac_jabber_frms"},
 157         {"rmac_ip"},
 158         {"rmac_ip_octets"},
 159         {"rmac_hdr_err_ip"},
 160         {"rmac_drop_ip"},
 161         {"rmac_icmp"},
 162         {"rmac_tcp"},
 163         {"rmac_udp"},
 164         {"rmac_err_drp_udp"},
 165         {"rmac_pause_cnt"},
 166         {"rmac_accepted_ip"},
 167         {"rmac_err_tcp"},
 168         {"\n DRIVER STATISTICS"},
 169         {"single_bit_ecc_errs"},
 170         {"double_bit_ecc_errs"},
 171 };
 172
 173 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 174 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 175
 176 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 177 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 178
 179 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 180                         init_timer(&timer);                     \
 181                         timer.function = handle;                \
 182                         timer.data = (unsigned long) arg;       \
 183                         mod_timer(&timer, (jiffies + exp))      \
 184
 185 /* Add the vlan */
 186 static void s2io_vlan_rx_register(struct net_device *dev,
 187                                         struct vlan_group *grp)
 188 {
 189         nic_t *nic = dev->priv;
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&nic->tx_lock, flags);
 193         nic->vlgrp = grp;
 194         spin_unlock_irqrestore(&nic->tx_lock, flags);
 195 }
 196
 197 /* Unregister the vlan */
 198 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 199 {
 200         nic_t *nic = dev->priv;
 201         unsigned long flags;
 202
 203         spin_lock_irqsave(&nic->tx_lock, flags);
 204         if (nic->vlgrp)
 205                 nic->vlgrp->vlan_devices[vid] = NULL;
 206         spin_unlock_irqrestore(&nic->tx_lock, flags);
 207 }
 208
 209 /*
 210  * Constants to be programmed into the Xena's registers, to configure
 211  * the XAUI.
 212  */
 213
 214 #define SWITCH_SIGN     0xA5A5A5A5A5A5A5A5ULL
 215 #define END_SIGN        0x0
 216
 217 static u64 herc_act_dtx_cfg[] = {
 218         /* Set address */
 219         0x8000051536750000ULL, 0x80000515367500E0ULL,
 220         /* Write data */
 221         0x8000051536750004ULL, 0x80000515367500E4ULL,
 222         /* Set address */
 223         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 224         /* Write data */
 225         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 226         /* Set address */
 227         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 228         /* Write data */
 229         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 230         /* Set address */
 231         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 232         /* Write data */
 233         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 234         /* Done */
 235         END_SIGN
 236 };
 237
 238 static u64 xena_mdio_cfg[] = {
 239         /* Reset PMA PLL */
 240         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 241         0xC0010100008000E4ULL,
 242         /* Remove Reset from PMA PLL */
 243         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 244         0xC0010100000000E4ULL,
 245         END_SIGN
 246 };
 247
 248 static u64 xena_dtx_cfg[] = {
 249         0x8000051500000000ULL, 0x80000515000000E0ULL,
 250         0x80000515D93500E4ULL, 0x8001051500000000ULL,
 251         0x80010515000000E0ULL, 0x80010515001E00E4ULL,
 252         0x8002051500000000ULL, 0x80020515000000E0ULL,
 253         0x80020515F21000E4ULL,
 254         /* Set PADLOOPBACKN */
 255         0x8002051500000000ULL, 0x80020515000000E0ULL,
 256         0x80020515B20000E4ULL, 0x8003051500000000ULL,
 257         0x80030515000000E0ULL, 0x80030515B20000E4ULL,
 258         0x8004051500000000ULL, 0x80040515000000E0ULL,
 259         0x80040515B20000E4ULL, 0x8005051500000000ULL,
 260         0x80050515000000E0ULL, 0x80050515B20000E4ULL,
 261         SWITCH_SIGN,
 262         /* Remove PADLOOPBACKN */
 263         0x8002051500000000ULL, 0x80020515000000E0ULL,
 264         0x80020515F20000E4ULL, 0x8003051500000000ULL,
 265         0x80030515000000E0ULL, 0x80030515F20000E4ULL,
 266         0x8004051500000000ULL, 0x80040515000000E0ULL,
 267         0x80040515F20000E4ULL, 0x8005051500000000ULL,
 268         0x80050515000000E0ULL, 0x80050515F20000E4ULL,
 269         END_SIGN
 270 };
 271
 272 /*
 273  * Constants for Fixing the MacAddress problem seen mostly on
 274  * Alpha machines.
 275  */
 276 static u64 fix_mac[] = {
 277         0x0060000000000000ULL, 0x0060600000000000ULL,
 278         0x0040600000000000ULL, 0x0000600000000000ULL,
 279         0x0020600000000000ULL, 0x0060600000000000ULL,
 280         0x0020600000000000ULL, 0x0060600000000000ULL,
 281         0x0020600000000000ULL, 0x0060600000000000ULL,
 282         0x0020600000000000ULL, 0x0060600000000000ULL,
 283         0x0020600000000000ULL, 0x0060600000000000ULL,
 284         0x0020600000000000ULL, 0x0060600000000000ULL,
 285         0x0020600000000000ULL, 0x0060600000000000ULL,
 286         0x0020600000000000ULL, 0x0060600000000000ULL,
 287         0x0020600000000000ULL, 0x0060600000000000ULL,
 288         0x0020600000000000ULL, 0x0060600000000000ULL,
 289         0x0020600000000000ULL, 0x0000600000000000ULL,
 290         0x0040600000000000ULL, 0x0060600000000000ULL,
 291         END_SIGN
 292 };
 293
 294 /* Module Loadable parameters. */
 295 static unsigned int tx_fifo_num = 1;
 296 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 297     {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
 298 static unsigned int rx_ring_num = 1;
 299 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 300     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 301 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 302     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 303 static unsigned int rx_ring_mode = 1;
 304 static unsigned int use_continuous_tx_intrs = 1;
 305 static unsigned int rmac_pause_time = 65535;
 306 static unsigned int mc_pause_threshold_q0q3 = 187;
 307 static unsigned int mc_pause_threshold_q4q7 = 187;
 308 static unsigned int shared_splits;
 309 static unsigned int tmac_util_period = 5;
 310 static unsigned int rmac_util_period = 5;
 311 static unsigned int bimodal = 0;
 312 static unsigned int l3l4hdr_size = 128;
 313 #ifndef CONFIG_S2IO_NAPI
 314 static unsigned int indicate_max_pkts;
 315 #endif
 316 /* Frequency of Rx desc syncs expressed as power of 2 */
 317 static unsigned int rxsync_frequency = 3;
 318 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 319 static unsigned int intr_type = 0;
 320
 321 /*
 322  * S2IO device table.
 323  * This table lists all the devices that this driver supports.
 324  */
 325 static struct pci_device_id s2io_tbl[] __devinitdata = {
 326         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 327          PCI_ANY_ID, PCI_ANY_ID},
 328         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 329          PCI_ANY_ID, PCI_ANY_ID},
 330         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 331          PCI_ANY_ID, PCI_ANY_ID},
 332         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 333          PCI_ANY_ID, PCI_ANY_ID},
 334         {0,}
 335 };
 336
 337 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 338
 339 static struct pci_driver s2io_driver = {
 340       .name = "S2IO",
 341       .id_table = s2io_tbl,
 342       .probe = s2io_init_nic,
 343       .remove = __devexit_p(s2io_rem_nic),
 344 };
 345
 346 /* A simplifier macro used both by init and free shared_mem Fns(). */
 347 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 348
 349 /**
 350  * init_shared_mem - Allocation and Initialization of Memory
 351  * @nic: Device private variable.
 352  * Description: The function allocates all the memory areas shared
 353  * between the NIC and the driver. This includes Tx descriptors,
 354  * Rx descriptors and the statistics block.
 355  */
 356
 357 static int init_shared_mem(struct s2io_nic *nic)
 358 {
 359         u32 size;
 360         void *tmp_v_addr, *tmp_v_addr_next;
 361         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 362         RxD_block_t *pre_rxd_blk = NULL;
 363         int i, j, blk_cnt, rx_sz, tx_sz;
 364         int lst_size, lst_per_page;
 365         struct net_device *dev = nic->dev;
 366         unsigned long tmp;
 367         buffAdd_t *ba;
 368
 369         mac_info_t *mac_control;
 370         struct config_param *config;
 371
 372         mac_control = &nic->mac_control;
 373         config = &nic->config;
 374
 375
 376         /* Allocation and initialization of TXDLs in FIOFs */
 377         size = 0;
 378         for (i = 0; i < config->tx_fifo_num; i++) {
 379                 size += config->tx_cfg[i].fifo_len;
 380         }
 381         if (size > MAX_AVAILABLE_TXDS) {
 382                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 383                           __FUNCTION__);
 384                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 385                 return FAILURE;
 386         }
 387
 388         lst_size = (sizeof(TxD_t) * config->max_txds);
 389         tx_sz = lst_size * size;
 390         lst_per_page = PAGE_SIZE / lst_size;
 391
 392         for (i = 0; i < config->tx_fifo_num; i++) {
 393                 int fifo_len = config->tx_cfg[i].fifo_len;
 394                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 395                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 396                                                           GFP_KERNEL);
 397                 if (!mac_control->fifos[i].list_info) {
 398                         DBG_PRINT(ERR_DBG,
 399                                   "Malloc failed for list_info\n");
 400                         return -ENOMEM;
 401                 }
 402                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 403         }
 404         for (i = 0; i < config->tx_fifo_num; i++) {
 405                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 406                                                 lst_per_page);
 407                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 408                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 409                     config->tx_cfg[i].fifo_len - 1;
 410                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 411                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 412                     config->tx_cfg[i].fifo_len - 1;
 413                 mac_control->fifos[i].fifo_no = i;
 414                 mac_control->fifos[i].nic = nic;
 415                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 416
 417                 for (j = 0; j < page_num; j++) {
 418                         int k = 0;
 419                         dma_addr_t tmp_p;
 420                         void *tmp_v;
 421                         tmp_v = pci_alloc_consistent(nic->pdev,
 422                                                      PAGE_SIZE, &tmp_p);
 423                         if (!tmp_v) {
 424                                 DBG_PRINT(ERR_DBG,
 425                                           "pci_alloc_consistent ");
 426                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 427                                 return -ENOMEM;
 428                         }
 429                         /* If we got a zero DMA address(can happen on
 430                          * certain platforms like PPC), reallocate.
 431                          * Store virtual address of page we don't want,
 432                          * to be freed later.
 433                          */
 434                         if (!tmp_p) {
 435                                 mac_control->zerodma_virt_addr = tmp_v;
 436                                 DBG_PRINT(INIT_DBG,
 437                                 "%s: Zero DMA address for TxDL. ", dev->name);
 438                                 DBG_PRINT(INIT_DBG,
 439                                 "Virtual address %p\n", tmp_v);
 440                                 tmp_v = pci_alloc_consistent(nic->pdev,
 441                                                      PAGE_SIZE, &tmp_p);
 442                                 if (!tmp_v) {
 443                                         DBG_PRINT(ERR_DBG,
 444                                           "pci_alloc_consistent ");
 445                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 446                                         return -ENOMEM;
 447                                 }
 448                         }
 449                         while (k < lst_per_page) {
 450                                 int l = (j * lst_per_page) + k;
 451                                 if (l == config->tx_cfg[i].fifo_len)
 452                                         break;
 453                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 454                                     tmp_v + (k * lst_size);
 455                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 456                                     tmp_p + (k * lst_size);
 457                                 k++;
 458                         }
 459                 }
 460         }
 461
 462         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 463         if (!nic->ufo_in_band_v)
 464                 return -ENOMEM;
 465
 466         /* Allocation and initialization of RXDs in Rings */
 467         size = 0;
 468         for (i = 0; i < config->rx_ring_num; i++) {
 469                 if (config->rx_cfg[i].num_rxd %
 470                     (rxd_count[nic->rxd_mode] + 1)) {
 471                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 472                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 473                                   i);
 474                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 475                         return FAILURE;
 476                 }
 477                 size += config->rx_cfg[i].num_rxd;
 478                 mac_control->rings[i].block_count =
 479                         config->rx_cfg[i].num_rxd /
 480                         (rxd_count[nic->rxd_mode] + 1 );
 481                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 482                         mac_control->rings[i].block_count;
 483         }
 484         if (nic->rxd_mode == RXD_MODE_1)
 485                 size = (size * (sizeof(RxD1_t)));
 486         else
 487                 size = (size * (sizeof(RxD3_t)));
 488         rx_sz = size;
 489
 490         for (i = 0; i < config->rx_ring_num; i++) {
 491                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 492                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 493                 mac_control->rings[i].rx_curr_get_info.ring_len =
 494                     config->rx_cfg[i].num_rxd - 1;
 495                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 496                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 497                 mac_control->rings[i].rx_curr_put_info.ring_len =
 498                     config->rx_cfg[i].num_rxd - 1;
 499                 mac_control->rings[i].nic = nic;
 500                 mac_control->rings[i].ring_no = i;
 501
 502                 blk_cnt = config->rx_cfg[i].num_rxd /
 503                                 (rxd_count[nic->rxd_mode] + 1);
 504                 /*  Allocating all the Rx blocks */
 505                 for (j = 0; j < blk_cnt; j++) {
 506                         rx_block_info_t *rx_blocks;
 507                         int l;
 508
 509                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 510                         size = SIZE_OF_BLOCK; //size is always page size
 511                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 512                                                           &tmp_p_addr);
 513                         if (tmp_v_addr == NULL) {
 514                                 /*
 515                                  * In case of failure, free_shared_mem()
 516                                  * is called, which should free any
 517                                  * memory that was alloced till the
 518                                  * failure happened.
 519                                  */
 520                                 rx_blocks->block_virt_addr = tmp_v_addr;
 521                                 return -ENOMEM;
 522                         }
 523                         memset(tmp_v_addr, 0, size);
 524                         rx_blocks->block_virt_addr = tmp_v_addr;
 525                         rx_blocks->block_dma_addr = tmp_p_addr;
 526                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 527                                                   rxd_count[nic->rxd_mode],
 528                                                   GFP_KERNEL);
 529                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 530                                 rx_blocks->rxds[l].virt_addr =
 531                                         rx_blocks->block_virt_addr +
 532                                         (rxd_size[nic->rxd_mode] * l);
 533                                 rx_blocks->rxds[l].dma_addr =
 534                                         rx_blocks->block_dma_addr +
 535                                         (rxd_size[nic->rxd_mode] * l);
 536                         }
 537
 538                         mac_control->rings[i].rx_blocks[j].block_virt_addr =
 539                                 tmp_v_addr;
 540                         mac_control->rings[i].rx_blocks[j].block_dma_addr =
 541                                 tmp_p_addr;
 542                 }
 543                 /* Interlinking all Rx Blocks */
 544                 for (j = 0; j < blk_cnt; j++) {
 545                         tmp_v_addr =
 546                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 547                         tmp_v_addr_next =
 548                                 mac_control->rings[i].rx_blocks[(j + 1) %
 549                                               blk_cnt].block_virt_addr;
 550                         tmp_p_addr =
 551                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 552                         tmp_p_addr_next =
 553                                 mac_control->rings[i].rx_blocks[(j + 1) %
 554                                               blk_cnt].block_dma_addr;
 555
 556                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 557                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 558                             (unsigned long) tmp_v_addr_next;
 559                         pre_rxd_blk->pNext_RxD_Blk_physical =
 560                             (u64) tmp_p_addr_next;
 561                 }
 562         }
 563         if (nic->rxd_mode >= RXD_MODE_3A) {
 564                 /*
 565                  * Allocation of Storages for buffer addresses in 2BUFF mode
 566                  * and the buffers as well.
 567                  */
 568                 for (i = 0; i < config->rx_ring_num; i++) {
 569                         blk_cnt = config->rx_cfg[i].num_rxd /
 570                            (rxd_count[nic->rxd_mode]+ 1);
 571                         mac_control->rings[i].ba =
 572                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 573                                      GFP_KERNEL);
 574                         if (!mac_control->rings[i].ba)
 575                                 return -ENOMEM;
 576                         for (j = 0; j < blk_cnt; j++) {
 577                                 int k = 0;
 578                                 mac_control->rings[i].ba[j] =
 579                                         kmalloc((sizeof(buffAdd_t) *
 580                                                 (rxd_count[nic->rxd_mode] + 1)),
 581                                                 GFP_KERNEL);
 582                                 if (!mac_control->rings[i].ba[j])
 583                                         return -ENOMEM;
 584                                 while (k != rxd_count[nic->rxd_mode]) {
 585                                         ba = &mac_control->rings[i].ba[j][k];
 586
 587                                         ba->ba_0_org = (void *) kmalloc
 588                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 589                                         if (!ba->ba_0_org)
 590                                                 return -ENOMEM;
 591                                         tmp = (unsigned long)ba->ba_0_org;
 592                                         tmp += ALIGN_SIZE;
 593                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 594                                         ba->ba_0 = (void *) tmp;
 595
 596                                         ba->ba_1_org = (void *) kmalloc
 597                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 598                                         if (!ba->ba_1_org)
 599                                                 return -ENOMEM;
 600                                         tmp = (unsigned long) ba->ba_1_org;
 601                                         tmp += ALIGN_SIZE;
 602                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 603                                         ba->ba_1 = (void *) tmp;
 604                                         k++;
 605                                 }
 606                         }
 607                 }
 608         }
 609
 610         /* Allocation and initialization of Statistics block */
 611         size = sizeof(StatInfo_t);
 612         mac_control->stats_mem = pci_alloc_consistent
 613             (nic->pdev, size, &mac_control->stats_mem_phy);
 614
 615         if (!mac_control->stats_mem) {
 616                 /*
 617                  * In case of failure, free_shared_mem() is called, which
 618                  * should free any memory that was alloced till the
 619                  * failure happened.
 620                  */
 621                 return -ENOMEM;
 622         }
 623         mac_control->stats_mem_sz = size;
 624
 625         tmp_v_addr = mac_control->stats_mem;
 626         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 627         memset(tmp_v_addr, 0, size);
 628         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 629                   (unsigned long long) tmp_p_addr);
 630
 631         return SUCCESS;
 632 }
 633
 634 /**
 635  * free_shared_mem - Free the allocated Memory
 636  * @nic:  Device private variable.
 637  * Description: This function is to free all memory locations allocated by
 638  * the init_shared_mem() function and return it to the kernel.
 639  */
 640
 641 static void free_shared_mem(struct s2io_nic *nic)
 642 {
 643         int i, j, blk_cnt, size;
 644         void *tmp_v_addr;
 645         dma_addr_t tmp_p_addr;
 646         mac_info_t *mac_control;
 647         struct config_param *config;
 648         int lst_size, lst_per_page;
 649         struct net_device *dev = nic->dev;
 650
 651         if (!nic)
 652                 return;
 653
 654         mac_control = &nic->mac_control;
 655         config = &nic->config;
 656
 657         lst_size = (sizeof(TxD_t) * config->max_txds);
 658         lst_per_page = PAGE_SIZE / lst_size;
 659
 660         for (i = 0; i < config->tx_fifo_num; i++) {
 661                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 662                                                 lst_per_page);
 663                 for (j = 0; j < page_num; j++) {
 664                         int mem_blks = (j * lst_per_page);
 665                         if (!mac_control->fifos[i].list_info)
 666                                 return;
 667                         if (!mac_control->fifos[i].list_info[mem_blks].
 668                                  list_virt_addr)
 669                                 break;
 670                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 671                                             mac_control->fifos[i].
 672                                             list_info[mem_blks].
 673                                             list_virt_addr,
 674                                             mac_control->fifos[i].
 675                                             list_info[mem_blks].
 676                                             list_phy_addr);
 677                 }
 678                 /* If we got a zero DMA address during allocation,
 679                  * free the page now
 680                  */
 681                 if (mac_control->zerodma_virt_addr) {
 682                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 683                                             mac_control->zerodma_virt_addr,
 684                                             (dma_addr_t)0);
 685                         DBG_PRINT(INIT_DBG,
 686                                 "%s: Freeing TxDL with zero DMA addr. ",
 687                                 dev->name);
 688                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 689                                 mac_control->zerodma_virt_addr);
 690                 }
 691                 kfree(mac_control->fifos[i].list_info);
 692         }
 693
 694         size = SIZE_OF_BLOCK;
 695         for (i = 0; i < config->rx_ring_num; i++) {
 696                 blk_cnt = mac_control->rings[i].block_count;
 697                 for (j = 0; j < blk_cnt; j++) {
 698                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 699                                 block_virt_addr;
 700                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 701                                 block_dma_addr;
 702                         if (tmp_v_addr == NULL)
 703                                 break;
 704                         pci_free_consistent(nic->pdev, size,
 705                                             tmp_v_addr, tmp_p_addr);
 706                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 707                 }
 708         }
 709
 710         if (nic->rxd_mode >= RXD_MODE_3A) {
 711                 /* Freeing buffer storage addresses in 2BUFF mode. */
 712                 for (i = 0; i < config->rx_ring_num; i++) {
 713                         blk_cnt = config->rx_cfg[i].num_rxd /
 714                             (rxd_count[nic->rxd_mode] + 1);
 715                         for (j = 0; j < blk_cnt; j++) {
 716                                 int k = 0;
 717                                 if (!mac_control->rings[i].ba[j])
 718                                         continue;
 719                                 while (k != rxd_count[nic->rxd_mode]) {
 720                                         buffAdd_t *ba =
 721                                                 &mac_control->rings[i].ba[j][k];
 722                                         kfree(ba->ba_0_org);
 723                                         kfree(ba->ba_1_org);
 724                                         k++;
 725                                 }
 726                                 kfree(mac_control->rings[i].ba[j]);
 727                         }
 728                         kfree(mac_control->rings[i].ba);
 729                 }
 730         }
 731
 732         if (mac_control->stats_mem) {
 733                 pci_free_consistent(nic->pdev,
 734                                     mac_control->stats_mem_sz,
 735                                     mac_control->stats_mem,
 736                                     mac_control->stats_mem_phy);
 737         }
 738         if (nic->ufo_in_band_v)
 739                 kfree(nic->ufo_in_band_v);
 740 }
 741
 742 /**
 743  * s2io_verify_pci_mode -
 744  */
 745
 746 static int s2io_verify_pci_mode(nic_t *nic)
 747 {
 748         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 749         register u64 val64 = 0;
 750         int     mode;
 751
 752         val64 = readq(&bar0->pci_mode);
 753         mode = (u8)GET_PCI_MODE(val64);
 754
 755         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 756                 return -1;      /* Unknown PCI mode */
 757         return mode;
 758 }
 759
 760
 761 /**
 762  * s2io_print_pci_mode -
 763  */
 764 static int s2io_print_pci_mode(nic_t *nic)
 765 {
 766         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 767         register u64 val64 = 0;
 768         int     mode;
 769         struct config_param *config = &nic->config;
 770
 771         val64 = readq(&bar0->pci_mode);
 772         mode = (u8)GET_PCI_MODE(val64);
 773
 774         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 775                 return -1;      /* Unknown PCI mode */
 776
 777         if (val64 & PCI_MODE_32_BITS) {
 778                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 779         } else {
 780                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 781         }
 782
 783         switch(mode) {
 784                 case PCI_MODE_PCI_33:
 785                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 786                         config->bus_speed = 33;
 787                         break;
 788                 case PCI_MODE_PCI_66:
 789                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 790                         config->bus_speed = 133;
 791                         break;
 792                 case PCI_MODE_PCIX_M1_66:
 793                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 794                         config->bus_speed = 133; /* Herc doubles the clock rate */
 795                         break;
 796                 case PCI_MODE_PCIX_M1_100:
 797                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 798                         config->bus_speed = 200;
 799                         break;
 800                 case PCI_MODE_PCIX_M1_133:
 801                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 802                         config->bus_speed = 266;
 803                         break;
 804                 case PCI_MODE_PCIX_M2_66:
 805                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 806                         config->bus_speed = 133;
 807                         break;
 808                 case PCI_MODE_PCIX_M2_100:
 809                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 810                         config->bus_speed = 200;
 811                         break;
 812                 case PCI_MODE_PCIX_M2_133:
 813                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 814                         config->bus_speed = 266;
 815                         break;
 816                 default:
 817                         return -1;      /* Unsupported bus speed */
 818         }
 819
 820         return mode;
 821 }
 822
 823 /**
 824  *  init_nic - Initialization of hardware
 825  *  @nic: device peivate variable
 826  *  Description: The function sequentially configures every block
 827  *  of the H/W from their reset values.
 828  *  Return Value:  SUCCESS on success and
 829  *  '-1' on failure (endian settings incorrect).
 830  */
 831
 832 static int init_nic(struct s2io_nic *nic)
 833 {
 834         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 835         struct net_device *dev = nic->dev;
 836         register u64 val64 = 0;
 837         void __iomem *add;
 838         u32 time;
 839         int i, j;
 840         mac_info_t *mac_control;
 841         struct config_param *config;
 842         int mdio_cnt = 0, dtx_cnt = 0;
 843         unsigned long long mem_share;
 844         int mem_size;
 845
 846         mac_control = &nic->mac_control;
 847         config = &nic->config;
 848
 849         /* to set the swapper controle on the card */
 850         if(s2io_set_swapper(nic)) {
 851                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 852                 return -1;
 853         }
 854
 855         /*
 856          * Herc requires EOI to be removed from reset before XGXS, so..
 857          */
 858         if (nic->device_type & XFRAME_II_DEVICE) {
 859                 val64 = 0xA500000000ULL;
 860                 writeq(val64, &bar0->sw_reset);
 861                 msleep(500);
 862                 val64 = readq(&bar0->sw_reset);
 863         }
 864
 865         /* Remove XGXS from reset state */
 866         val64 = 0;
 867         writeq(val64, &bar0->sw_reset);
 868         msleep(500);
 869         val64 = readq(&bar0->sw_reset);
 870
 871         /*  Enable Receiving broadcasts */
 872         add = &bar0->mac_cfg;
 873         val64 = readq(&bar0->mac_cfg);
 874         val64 |= MAC_RMAC_BCAST_ENABLE;
 875         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 876         writel((u32) val64, add);
 877         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 878         writel((u32) (val64 >> 32), (add + 4));
 879
 880         /* Read registers in all blocks */
 881         val64 = readq(&bar0->mac_int_mask);
 882         val64 = readq(&bar0->mc_int_mask);
 883         val64 = readq(&bar0->xgxs_int_mask);
 884
 885         /*  Set MTU */
 886         val64 = dev->mtu;
 887         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 888
 889         /*
 890          * Configuring the XAUI Interface of Xena.
 891          * ***************************************
 892          * To Configure the Xena's XAUI, one has to write a series
 893          * of 64 bit values into two registers in a particular
 894          * sequence. Hence a macro 'SWITCH_SIGN' has been defined
 895          * which will be defined in the array of configuration values
 896          * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
 897          * to switch writing from one regsiter to another. We continue
 898          * writing these values until we encounter the 'END_SIGN' macro.
 899          * For example, After making a series of 21 writes into
 900          * dtx_control register the 'SWITCH_SIGN' appears and hence we
 901          * start writing into mdio_control until we encounter END_SIGN.
 902          */
 903         if (nic->device_type & XFRAME_II_DEVICE) {
 904                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 905                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 906                                           &bar0->dtx_control, UF);
 907                         if (dtx_cnt & 0x1)
 908                                 msleep(1); /* Necessary!! */
 909                         dtx_cnt++;
 910                 }
 911         } else {
 912                 while (1) {
 913                       dtx_cfg:
 914                         while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 915                                 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
 916                                         dtx_cnt++;
 917                                         goto mdio_cfg;
 918                                 }
 919                                 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 920                                                   &bar0->dtx_control, UF);
 921                                 val64 = readq(&bar0->dtx_control);
 922                                 dtx_cnt++;
 923                         }
 924                       mdio_cfg:
 925                         while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
 926                                 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
 927                                         mdio_cnt++;
 928                                         goto dtx_cfg;
 929                                 }
 930                                 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
 931                                                   &bar0->mdio_control, UF);
 932                                 val64 = readq(&bar0->mdio_control);
 933                                 mdio_cnt++;
 934                         }
 935                         if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
 936                             (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
 937                                 break;
 938                         } else {
 939                                 goto dtx_cfg;
 940                         }
 941                 }
 942         }
 943
 944         /*  Tx DMA Initialization */
 945         val64 = 0;
 946         writeq(val64, &bar0->tx_fifo_partition_0);
 947         writeq(val64, &bar0->tx_fifo_partition_1);
 948         writeq(val64, &bar0->tx_fifo_partition_2);
 949         writeq(val64, &bar0->tx_fifo_partition_3);
 950
 951
 952         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
 953                 val64 |=
 954                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
 955                          13) | vBIT(config->tx_cfg[i].fifo_priority,
 956                                     ((i * 32) + 5), 3);
 957
 958                 if (i == (config->tx_fifo_num - 1)) {
 959                         if (i % 2 == 0)
 960                                 i++;
 961                 }
 962
 963                 switch (i) {
 964                 case 1:
 965                         writeq(val64, &bar0->tx_fifo_partition_0);
 966                         val64 = 0;
 967                         break;
 968                 case 3:
 969                         writeq(val64, &bar0->tx_fifo_partition_1);
 970                         val64 = 0;
 971                         break;
 972                 case 5:
 973                         writeq(val64, &bar0->tx_fifo_partition_2);
 974                         val64 = 0;
 975                         break;
 976                 case 7:
 977                         writeq(val64, &bar0->tx_fifo_partition_3);
 978                         break;
 979                 }
 980         }
 981
 982         /* Enable Tx FIFO partition 0. */
 983         val64 = readq(&bar0->tx_fifo_partition_0);
 984         val64 |= BIT(0);        /* To enable the FIFO partition. */
 985         writeq(val64, &bar0->tx_fifo_partition_0);
 986
 987         /*
 988          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
 989          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
 990          */
 991         if ((nic->device_type == XFRAME_I_DEVICE) &&
 992                 (get_xena_rev_id(nic->pdev) < 4))
 993                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
 994
 995         val64 = readq(&bar0->tx_fifo_partition_0);
 996         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
 997                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
 998
 999         /*
1000          * Initialization of Tx_PA_CONFIG register to ignore packet
1001          * integrity checking.
1002          */
1003         val64 = readq(&bar0->tx_pa_cfg);
1004         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1005             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1006         writeq(val64, &bar0->tx_pa_cfg);
1007
1008         /* Rx DMA intialization. */
1009         val64 = 0;
1010         for (i = 0; i < config->rx_ring_num; i++) {
1011                 val64 |=
1012                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1013                          3);
1014         }
1015         writeq(val64, &bar0->rx_queue_priority);
1016
1017         /*
1018          * Allocating equal share of memory to all the
1019          * configured Rings.
1020          */
1021         val64 = 0;
1022         if (nic->device_type & XFRAME_II_DEVICE)
1023                 mem_size = 32;
1024         else
1025                 mem_size = 64;
1026
1027         for (i = 0; i < config->rx_ring_num; i++) {
1028                 switch (i) {
1029                 case 0:
1030                         mem_share = (mem_size / config->rx_ring_num +
1031                                      mem_size % config->rx_ring_num);
1032                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1033                         continue;
1034                 case 1:
1035                         mem_share = (mem_size / config->rx_ring_num);
1036                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1037                         continue;
1038                 case 2:
1039                         mem_share = (mem_size / config->rx_ring_num);
1040                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1041                         continue;
1042                 case 3:
1043                         mem_share = (mem_size / config->rx_ring_num);
1044                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1045                         continue;
1046                 case 4:
1047                         mem_share = (mem_size / config->rx_ring_num);
1048                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1049                         continue;
1050                 case 5:
1051                         mem_share = (mem_size / config->rx_ring_num);
1052                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1053                         continue;
1054                 case 6:
1055                         mem_share = (mem_size / config->rx_ring_num);
1056                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1057                         continue;
1058                 case 7:
1059                         mem_share = (mem_size / config->rx_ring_num);
1060                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1061                         continue;
1062                 }
1063         }
1064         writeq(val64, &bar0->rx_queue_cfg);
1065
1066         /*
1067          * Filling Tx round robin registers
1068          * as per the number of FIFOs
1069          */
1070         switch (config->tx_fifo_num) {
1071         case 1:
1072                 val64 = 0x0000000000000000ULL;
1073                 writeq(val64, &bar0->tx_w_round_robin_0);
1074                 writeq(val64, &bar0->tx_w_round_robin_1);
1075                 writeq(val64, &bar0->tx_w_round_robin_2);
1076                 writeq(val64, &bar0->tx_w_round_robin_3);
1077                 writeq(val64, &bar0->tx_w_round_robin_4);
1078                 break;
1079         case 2:
1080                 val64 = 0x0000010000010000ULL;
1081                 writeq(val64, &bar0->tx_w_round_robin_0);
1082                 val64 = 0x0100000100000100ULL;
1083                 writeq(val64, &bar0->tx_w_round_robin_1);
1084                 val64 = 0x0001000001000001ULL;
1085                 writeq(val64, &bar0->tx_w_round_robin_2);
1086                 val64 = 0x0000010000010000ULL;
1087                 writeq(val64, &bar0->tx_w_round_robin_3);
1088                 val64 = 0x0100000000000000ULL;
1089                 writeq(val64, &bar0->tx_w_round_robin_4);
1090                 break;
1091         case 3:
1092                 val64 = 0x0001000102000001ULL;
1093                 writeq(val64, &bar0->tx_w_round_robin_0);
1094                 val64 = 0x0001020000010001ULL;
1095                 writeq(val64, &bar0->tx_w_round_robin_1);
1096                 val64 = 0x0200000100010200ULL;
1097                 writeq(val64, &bar0->tx_w_round_robin_2);
1098                 val64 = 0x0001000102000001ULL;
1099                 writeq(val64, &bar0->tx_w_round_robin_3);
1100                 val64 = 0x0001020000000000ULL;
1101                 writeq(val64, &bar0->tx_w_round_robin_4);
1102                 break;
1103         case 4:
1104                 val64 = 0x0001020300010200ULL;
1105                 writeq(val64, &bar0->tx_w_round_robin_0);
1106                 val64 = 0x0100000102030001ULL;
1107                 writeq(val64, &bar0->tx_w_round_robin_1);
1108                 val64 = 0x0200010000010203ULL;
1109                 writeq(val64, &bar0->tx_w_round_robin_2);
1110                 val64 = 0x0001020001000001ULL;
1111                 writeq(val64, &bar0->tx_w_round_robin_3);
1112                 val64 = 0x0203000100000000ULL;
1113                 writeq(val64, &bar0->tx_w_round_robin_4);
1114                 break;
1115         case 5:
1116                 val64 = 0x0001000203000102ULL;
1117                 writeq(val64, &bar0->tx_w_round_robin_0);
1118                 val64 = 0x0001020001030004ULL;
1119                 writeq(val64, &bar0->tx_w_round_robin_1);
1120                 val64 = 0x0001000203000102ULL;
1121                 writeq(val64, &bar0->tx_w_round_robin_2);
1122                 val64 = 0x0001020001030004ULL;
1123                 writeq(val64, &bar0->tx_w_round_robin_3);
1124                 val64 = 0x0001000000000000ULL;
1125                 writeq(val64, &bar0->tx_w_round_robin_4);
1126                 break;
1127         case 6:
1128                 val64 = 0x0001020304000102ULL;
1129                 writeq(val64, &bar0->tx_w_round_robin_0);
1130                 val64 = 0x0304050001020001ULL;
1131                 writeq(val64, &bar0->tx_w_round_robin_1);
1132                 val64 = 0x0203000100000102ULL;
1133                 writeq(val64, &bar0->tx_w_round_robin_2);
1134                 val64 = 0x0304000102030405ULL;
1135                 writeq(val64, &bar0->tx_w_round_robin_3);
1136                 val64 = 0x0001000200000000ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_4);
1138                 break;
1139         case 7:
1140                 val64 = 0x0001020001020300ULL;
1141                 writeq(val64, &bar0->tx_w_round_robin_0);
1142                 val64 = 0x0102030400010203ULL;
1143                 writeq(val64, &bar0->tx_w_round_robin_1);
1144                 val64 = 0x0405060001020001ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_2);
1146                 val64 = 0x0304050000010200ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_3);
1148                 val64 = 0x0102030000000000ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_4);
1150                 break;
1151         case 8:
1152                 val64 = 0x0001020300040105ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_0);
1154                 val64 = 0x0200030106000204ULL;
1155                 writeq(val64, &bar0->tx_w_round_robin_1);
1156                 val64 = 0x0103000502010007ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_2);
1158                 val64 = 0x0304010002060500ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_3);
1160                 val64 = 0x0103020400000000ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_4);
1162                 break;
1163         }
1164
1165         /* Filling the Rx round robin registers as per the
1166          * number of Rings and steering based on QoS.
1167          */
1168         switch (config->rx_ring_num) {
1169         case 1:
1170                 val64 = 0x8080808080808080ULL;
1171                 writeq(val64, &bar0->rts_qos_steering);
1172                 break;
1173         case 2:
1174                 val64 = 0x0000010000010000ULL;
1175                 writeq(val64, &bar0->rx_w_round_robin_0);
1176                 val64 = 0x0100000100000100ULL;
1177                 writeq(val64, &bar0->rx_w_round_robin_1);
1178                 val64 = 0x0001000001000001ULL;
1179                 writeq(val64, &bar0->rx_w_round_robin_2);
1180                 val64 = 0x0000010000010000ULL;
1181                 writeq(val64, &bar0->rx_w_round_robin_3);
1182                 val64 = 0x0100000000000000ULL;
1183                 writeq(val64, &bar0->rx_w_round_robin_4);
1184
1185                 val64 = 0x8080808040404040ULL;
1186                 writeq(val64, &bar0->rts_qos_steering);
1187                 break;
1188         case 3:
1189                 val64 = 0x0001000102000001ULL;
1190                 writeq(val64, &bar0->rx_w_round_robin_0);
1191                 val64 = 0x0001020000010001ULL;
1192                 writeq(val64, &bar0->rx_w_round_robin_1);
1193                 val64 = 0x0200000100010200ULL;
1194                 writeq(val64, &bar0->rx_w_round_robin_2);
1195                 val64 = 0x0001000102000001ULL;
1196                 writeq(val64, &bar0->rx_w_round_robin_3);
1197                 val64 = 0x0001020000000000ULL;
1198                 writeq(val64, &bar0->rx_w_round_robin_4);
1199
1200                 val64 = 0x8080804040402020ULL;
1201                 writeq(val64, &bar0->rts_qos_steering);
1202                 break;
1203         case 4:
1204                 val64 = 0x0001020300010200ULL;
1205                 writeq(val64, &bar0->rx_w_round_robin_0);
1206                 val64 = 0x0100000102030001ULL;
1207                 writeq(val64, &bar0->rx_w_round_robin_1);
1208                 val64 = 0x0200010000010203ULL;
1209                 writeq(val64, &bar0->rx_w_round_robin_2);
1210                 val64 = 0x0001020001000001ULL;
1211                 writeq(val64, &bar0->rx_w_round_robin_3);
1212                 val64 = 0x0203000100000000ULL;
1213                 writeq(val64, &bar0->rx_w_round_robin_4);
1214
1215                 val64 = 0x8080404020201010ULL;
1216                 writeq(val64, &bar0->rts_qos_steering);
1217                 break;
1218         case 5:
1219                 val64 = 0x0001000203000102ULL;
1220                 writeq(val64, &bar0->rx_w_round_robin_0);
1221                 val64 = 0x0001020001030004ULL;
1222                 writeq(val64, &bar0->rx_w_round_robin_1);
1223                 val64 = 0x0001000203000102ULL;
1224                 writeq(val64, &bar0->rx_w_round_robin_2);
1225                 val64 = 0x0001020001030004ULL;
1226                 writeq(val64, &bar0->rx_w_round_robin_3);
1227                 val64 = 0x0001000000000000ULL;
1228                 writeq(val64, &bar0->rx_w_round_robin_4);
1229
1230                 val64 = 0x8080404020201008ULL;
1231                 writeq(val64, &bar0->rts_qos_steering);
1232                 break;
1233         case 6:
1234                 val64 = 0x0001020304000102ULL;
1235                 writeq(val64, &bar0->rx_w_round_robin_0);
1236                 val64 = 0x0304050001020001ULL;
1237                 writeq(val64, &bar0->rx_w_round_robin_1);
1238                 val64 = 0x0203000100000102ULL;
1239                 writeq(val64, &bar0->rx_w_round_robin_2);
1240                 val64 = 0x0304000102030405ULL;
1241                 writeq(val64, &bar0->rx_w_round_robin_3);
1242                 val64 = 0x0001000200000000ULL;
1243                 writeq(val64, &bar0->rx_w_round_robin_4);
1244
1245                 val64 = 0x8080404020100804ULL;
1246                 writeq(val64, &bar0->rts_qos_steering);
1247                 break;
1248         case 7:
1249                 val64 = 0x0001020001020300ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_0);
1251                 val64 = 0x0102030400010203ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_1);
1253                 val64 = 0x0405060001020001ULL;
1254                 writeq(val64, &bar0->rx_w_round_robin_2);
1255                 val64 = 0x0304050000010200ULL;
1256                 writeq(val64, &bar0->rx_w_round_robin_3);
1257                 val64 = 0x0102030000000000ULL;
1258                 writeq(val64, &bar0->rx_w_round_robin_4);
1259
1260                 val64 = 0x8080402010080402ULL;
1261                 writeq(val64, &bar0->rts_qos_steering);
1262                 break;
1263         case 8:
1264                 val64 = 0x0001020300040105ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_0);
1266                 val64 = 0x0200030106000204ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_1);
1268                 val64 = 0x0103000502010007ULL;
1269                 writeq(val64, &bar0->rx_w_round_robin_2);
1270                 val64 = 0x0304010002060500ULL;
1271                 writeq(val64, &bar0->rx_w_round_robin_3);
1272                 val64 = 0x0103020400000000ULL;
1273                 writeq(val64, &bar0->rx_w_round_robin_4);
1274
1275                 val64 = 0x8040201008040201ULL;
1276                 writeq(val64, &bar0->rts_qos_steering);
1277                 break;
1278         }
1279
1280         /* UDP Fix */
1281         val64 = 0;
1282         for (i = 0; i < 8; i++)
1283                 writeq(val64, &bar0->rts_frm_len_n[i]);
1284
1285         /* Set the default rts frame length for the rings configured */
1286         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1287         for (i = 0 ; i < config->rx_ring_num ; i++)
1288                 writeq(val64, &bar0->rts_frm_len_n[i]);
1289
1290         /* Set the frame length for the configured rings
1291          * desired by the user
1292          */
1293         for (i = 0; i < config->rx_ring_num; i++) {
1294                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1295                  * specified frame length steering.
1296                  * If the user provides the frame length then program
1297                  * the rts_frm_len register for those values or else
1298                  * leave it as it is.
1299                  */
1300                 if (rts_frm_len[i] != 0) {
1301                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1302                                 &bar0->rts_frm_len_n[i]);
1303                 }
1304         }
1305
1306         /* Program statistics memory */
1307         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1308
1309         if (nic->device_type == XFRAME_II_DEVICE) {
1310                 val64 = STAT_BC(0x320);
1311                 writeq(val64, &bar0->stat_byte_cnt);
1312         }
1313
1314         /*
1315          * Initializing the sampling rate for the device to calculate the
1316          * bandwidth utilization.
1317          */
1318         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1319             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1320         writeq(val64, &bar0->mac_link_util);
1321
1322
1323         /*
1324          * Initializing the Transmit and Receive Traffic Interrupt
1325          * Scheme.
1326          */
1327         /*
1328          * TTI Initialization. Default Tx timer gets us about
1329          * 250 interrupts per sec. Continuous interrupts are enabled
1330          * by default.
1331          */
1332         if (nic->device_type == XFRAME_II_DEVICE) {
1333                 int count = (nic->config.bus_speed * 125)/2;
1334                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1335         } else {
1336
1337                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1338         }
1339         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1340             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1341             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1342                 if (use_continuous_tx_intrs)
1343                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1344         writeq(val64, &bar0->tti_data1_mem);
1345
1346         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1347             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1348             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1349         writeq(val64, &bar0->tti_data2_mem);
1350
1351         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1352         writeq(val64, &bar0->tti_command_mem);
1353
1354         /*
1355          * Once the operation completes, the Strobe bit of the command
1356          * register will be reset. We poll for this particular condition
1357          * We wait for a maximum of 500ms for the operation to complete,
1358          * if it's not complete by then we return error.
1359          */
1360         time = 0;
1361         while (TRUE) {
1362                 val64 = readq(&bar0->tti_command_mem);
1363                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1364                         break;
1365                 }
1366                 if (time > 10) {
1367                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1368                                   dev->name);
1369                         return -1;
1370                 }
1371                 msleep(50);
1372                 time++;
1373         }
1374
1375         if (nic->config.bimodal) {
1376                 int k = 0;
1377                 for (k = 0; k < config->rx_ring_num; k++) {
1378                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1379                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1380                         writeq(val64, &bar0->tti_command_mem);
1381
1382                 /*
1383                  * Once the operation completes, the Strobe bit of the command
1384                  * register will be reset. We poll for this particular condition
1385                  * We wait for a maximum of 500ms for the operation to complete,
1386                  * if it's not complete by then we return error.
1387                 */
1388                         time = 0;
1389                         while (TRUE) {
1390                                 val64 = readq(&bar0->tti_command_mem);
1391                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1392                                         break;
1393                                 }
1394                                 if (time > 10) {
1395                                         DBG_PRINT(ERR_DBG,
1396                                                 "%s: TTI init Failed\n",
1397                                         dev->name);
1398                                         return -1;
1399                                 }
1400                                 time++;
1401                                 msleep(50);
1402                         }
1403                 }
1404         } else {
1405
1406                 /* RTI Initialization */
1407                 if (nic->device_type == XFRAME_II_DEVICE) {
1408                         /*
1409                          * Programmed to generate Apprx 500 Intrs per
1410                          * second
1411                          */
1412                         int count = (nic->config.bus_speed * 125)/4;
1413                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1414                 } else {
1415                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1416                 }
1417                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1418                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1419                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1420
1421                 writeq(val64, &bar0->rti_data1_mem);
1422
1423                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1424                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1425                 if (nic->intr_type == MSI_X)
1426                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1427                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1428                 else
1429                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1430                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1431                 writeq(val64, &bar0->rti_data2_mem);
1432
1433                 for (i = 0; i < config->rx_ring_num; i++) {
1434                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1435                                         | RTI_CMD_MEM_OFFSET(i);
1436                         writeq(val64, &bar0->rti_command_mem);
1437
1438                         /*
1439                          * Once the operation completes, the Strobe bit of the
1440                          * command register will be reset. We poll for this
1441                          * particular condition. We wait for a maximum of 500ms
1442                          * for the operation to complete, if it's not complete
1443                          * by then we return error.
1444                          */
1445                         time = 0;
1446                         while (TRUE) {
1447                                 val64 = readq(&bar0->rti_command_mem);
1448                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1449                                         break;
1450                                 }
1451                                 if (time > 10) {
1452                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1453                                                   dev->name);
1454                                         return -1;
1455                                 }
1456                                 time++;
1457                                 msleep(50);
1458                         }
1459                 }
1460         }
1461
1462         /*
1463          * Initializing proper values as Pause threshold into all
1464          * the 8 Queues on Rx side.
1465          */
1466         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1467         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1468
1469         /* Disable RMAC PAD STRIPPING */
1470         add = &bar0->mac_cfg;
1471         val64 = readq(&bar0->mac_cfg);
1472         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1473         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1474         writel((u32) (val64), add);
1475         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1476         writel((u32) (val64 >> 32), (add + 4));
1477         val64 = readq(&bar0->mac_cfg);
1478
1479         /*
1480          * Set the time value to be inserted in the pause frame
1481          * generated by xena.
1482          */
1483         val64 = readq(&bar0->rmac_pause_cfg);
1484         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1485         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1486         writeq(val64, &bar0->rmac_pause_cfg);
1487
1488         /*
1489          * Set the Threshold Limit for Generating the pause frame
1490          * If the amount of data in any Queue exceeds ratio of
1491          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1492          * pause frame is generated
1493          */
1494         val64 = 0;
1495         for (i = 0; i < 4; i++) {
1496                 val64 |=
1497                     (((u64) 0xFF00 | nic->mac_control.
1498                       mc_pause_threshold_q0q3)
1499                      << (i * 2 * 8));
1500         }
1501         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1502
1503         val64 = 0;
1504         for (i = 0; i < 4; i++) {
1505                 val64 |=
1506                     (((u64) 0xFF00 | nic->mac_control.
1507                       mc_pause_threshold_q4q7)
1508                      << (i * 2 * 8));
1509         }
1510         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1511
1512         /*
1513          * TxDMA will stop Read request if the number of read split has
1514          * exceeded the limit pointed by shared_splits
1515          */
1516         val64 = readq(&bar0->pic_control);
1517         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1518         writeq(val64, &bar0->pic_control);
1519
1520         /*
1521          * Programming the Herc to split every write transaction
1522          * that does not start on an ADB to reduce disconnects.
1523          */
1524         if (nic->device_type == XFRAME_II_DEVICE) {
1525                 val64 = WREQ_SPLIT_MASK_SET_MASK(255);
1526                 writeq(val64, &bar0->wreq_split_mask);
1527         }
1528
1529         /* Setting Link stability period to 64 ms */
1530         if (nic->device_type == XFRAME_II_DEVICE) {
1531                 val64 = MISC_LINK_STABILITY_PRD(3);
1532                 writeq(val64, &bar0->misc_control);
1533         }
1534
1535         return SUCCESS;
1536 }
1537 #define LINK_UP_DOWN_INTERRUPT          1
1538 #define MAC_RMAC_ERR_TIMER              2
1539
1540 static int s2io_link_fault_indication(nic_t *nic)
1541 {
1542         if (nic->intr_type != INTA)
1543                 return MAC_RMAC_ERR_TIMER;
1544         if (nic->device_type == XFRAME_II_DEVICE)
1545                 return LINK_UP_DOWN_INTERRUPT;
1546         else
1547                 return MAC_RMAC_ERR_TIMER;
1548 }
1549
1550 /**
1551  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1552  *  @nic: device private variable,
1553  *  @mask: A mask indicating which Intr block must be modified and,
1554  *  @flag: A flag indicating whether to enable or disable the Intrs.
1555  *  Description: This function will either disable or enable the interrupts
1556  *  depending on the flag argument. The mask argument can be used to
1557  *  enable/disable any Intr block.
1558  *  Return Value: NONE.
1559  */
1560
1561 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1562 {
1563         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1564         register u64 val64 = 0, temp64 = 0;
1565
1566         /*  Top level interrupt classification */
1567         /*  PIC Interrupts */
1568         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1569                 /*  Enable PIC Intrs in the general intr mask register */
1570                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1571                 if (flag == ENABLE_INTRS) {
1572                         temp64 = readq(&bar0->general_int_mask);
1573                         temp64 &= ~((u64) val64);
1574                         writeq(temp64, &bar0->general_int_mask);
1575                         /*
1576                          * If Hercules adapter enable GPIO otherwise
1577                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1578                          * interrupts for now.
1579                          * TODO
1580                          */
1581                         if (s2io_link_fault_indication(nic) ==
1582                                         LINK_UP_DOWN_INTERRUPT ) {
1583                                 temp64 = readq(&bar0->pic_int_mask);
1584                                 temp64 &= ~((u64) PIC_INT_GPIO);
1585                                 writeq(temp64, &bar0->pic_int_mask);
1586                                 temp64 = readq(&bar0->gpio_int_mask);
1587                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1588                                 writeq(temp64, &bar0->gpio_int_mask);
1589                         } else {
1590                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1591                         }
1592                         /*
1593                          * No MSI Support is available presently, so TTI and
1594                          * RTI interrupts are also disabled.
1595                          */
1596                 } else if (flag == DISABLE_INTRS) {
1597                         /*
1598                          * Disable PIC Intrs in the general
1599                          * intr mask register
1600                          */
1601                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1602                         temp64 = readq(&bar0->general_int_mask);
1603                         val64 |= temp64;
1604                         writeq(val64, &bar0->general_int_mask);
1605                 }
1606         }
1607
1608         /*  DMA Interrupts */
1609         /*  Enabling/Disabling Tx DMA interrupts */
1610         if (mask & TX_DMA_INTR) {
1611                 /* Enable TxDMA Intrs in the general intr mask register */
1612                 val64 = TXDMA_INT_M;
1613                 if (flag == ENABLE_INTRS) {
1614                         temp64 = readq(&bar0->general_int_mask);
1615                         temp64 &= ~((u64) val64);
1616                         writeq(temp64, &bar0->general_int_mask);
1617                         /*
1618                          * Keep all interrupts other than PFC interrupt
1619                          * and PCC interrupt disabled in DMA level.
1620                          */
1621                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1622                                                       TXDMA_PCC_INT_M);
1623                         writeq(val64, &bar0->txdma_int_mask);
1624                         /*
1625                          * Enable only the MISC error 1 interrupt in PFC block
1626                          */
1627                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1628                         writeq(val64, &bar0->pfc_err_mask);
1629                         /*
1630                          * Enable only the FB_ECC error interrupt in PCC block
1631                          */
1632                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1633                         writeq(val64, &bar0->pcc_err_mask);
1634                 } else if (flag == DISABLE_INTRS) {
1635                         /*
1636                          * Disable TxDMA Intrs in the general intr mask
1637                          * register
1638                          */
1639                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1640                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1641                         temp64 = readq(&bar0->general_int_mask);
1642                         val64 |= temp64;
1643                         writeq(val64, &bar0->general_int_mask);
1644                 }
1645         }
1646
1647         /*  Enabling/Disabling Rx DMA interrupts */
1648         if (mask & RX_DMA_INTR) {
1649                 /*  Enable RxDMA Intrs in the general intr mask register */
1650                 val64 = RXDMA_INT_M;
1651                 if (flag == ENABLE_INTRS) {
1652                         temp64 = readq(&bar0->general_int_mask);
1653                         temp64 &= ~((u64) val64);
1654                         writeq(temp64, &bar0->general_int_mask);
1655                         /*
1656                          * All RxDMA block interrupts are disabled for now
1657                          * TODO
1658                          */
1659                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1660                 } else if (flag == DISABLE_INTRS) {
1661                         /*
1662                          * Disable RxDMA Intrs in the general intr mask
1663                          * register
1664                          */
1665                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1666                         temp64 = readq(&bar0->general_int_mask);
1667                         val64 |= temp64;
1668                         writeq(val64, &bar0->general_int_mask);
1669                 }
1670         }
1671
1672         /*  MAC Interrupts */
1673         /*  Enabling/Disabling MAC interrupts */
1674         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1675                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1676                 if (flag == ENABLE_INTRS) {
1677                         temp64 = readq(&bar0->general_int_mask);
1678                         temp64 &= ~((u64) val64);
1679                         writeq(temp64, &bar0->general_int_mask);
1680                         /*
1681                          * All MAC block error interrupts are disabled for now
1682                          * TODO
1683                          */
1684                 } else if (flag == DISABLE_INTRS) {
1685                         /*
1686                          * Disable MAC Intrs in the general intr mask register
1687                          */
1688                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1689                         writeq(DISABLE_ALL_INTRS,
1690                                &bar0->mac_rmac_err_mask);
1691
1692                         temp64 = readq(&bar0->general_int_mask);
1693                         val64 |= temp64;
1694                         writeq(val64, &bar0->general_int_mask);
1695                 }
1696         }
1697
1698         /*  XGXS Interrupts */
1699         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1700                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1701                 if (flag == ENABLE_INTRS) {
1702                         temp64 = readq(&bar0->general_int_mask);
1703                         temp64 &= ~((u64) val64);
1704                         writeq(temp64, &bar0->general_int_mask);
1705                         /*
1706                          * All XGXS block error interrupts are disabled for now
1707                          * TODO
1708                          */
1709                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1710                 } else if (flag == DISABLE_INTRS) {
1711                         /*
1712                          * Disable MC Intrs in the general intr mask register
1713                          */
1714                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1715                         temp64 = readq(&bar0->general_int_mask);
1716                         val64 |= temp64;
1717                         writeq(val64, &bar0->general_int_mask);
1718                 }
1719         }
1720
1721         /*  Memory Controller(MC) interrupts */
1722         if (mask & MC_INTR) {
1723                 val64 = MC_INT_M;
1724                 if (flag == ENABLE_INTRS) {
1725                         temp64 = readq(&bar0->general_int_mask);
1726                         temp64 &= ~((u64) val64);
1727                         writeq(temp64, &bar0->general_int_mask);
1728                         /*
1729                          * Enable all MC Intrs.
1730                          */
1731                         writeq(0x0, &bar0->mc_int_mask);
1732                         writeq(0x0, &bar0->mc_err_mask);
1733                 } else if (flag == DISABLE_INTRS) {
1734                         /*
1735                          * Disable MC Intrs in the general intr mask register
1736                          */
1737                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1738                         temp64 = readq(&bar0->general_int_mask);
1739                         val64 |= temp64;
1740                         writeq(val64, &bar0->general_int_mask);
1741                 }
1742         }
1743
1744
1745         /*  Tx traffic interrupts */
1746         if (mask & TX_TRAFFIC_INTR) {
1747                 val64 = TXTRAFFIC_INT_M;
1748                 if (flag == ENABLE_INTRS) {
1749                         temp64 = readq(&bar0->general_int_mask);
1750                         temp64 &= ~((u64) val64);
1751                         writeq(temp64, &bar0->general_int_mask);
1752                         /*
1753                          * Enable all the Tx side interrupts
1754                          * writing 0 Enables all 64 TX interrupt levels
1755                          */
1756                         writeq(0x0, &bar0->tx_traffic_mask);
1757                 } else if (flag == DISABLE_INTRS) {
1758                         /*
1759                          * Disable Tx Traffic Intrs in the general intr mask
1760                          * register.
1761                          */
1762                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1763                         temp64 = readq(&bar0->general_int_mask);
1764                         val64 |= temp64;
1765                         writeq(val64, &bar0->general_int_mask);
1766                 }
1767         }
1768
1769         /*  Rx traffic interrupts */
1770         if (mask & RX_TRAFFIC_INTR) {
1771                 val64 = RXTRAFFIC_INT_M;
1772                 if (flag == ENABLE_INTRS) {
1773                         temp64 = readq(&bar0->general_int_mask);
1774                         temp64 &= ~((u64) val64);
1775                         writeq(temp64, &bar0->general_int_mask);
1776                         /* writing 0 Enables all 8 RX interrupt levels */
1777                         writeq(0x0, &bar0->rx_traffic_mask);
1778                 } else if (flag == DISABLE_INTRS) {
1779                         /*
1780                          * Disable Rx Traffic Intrs in the general intr mask
1781                          * register.
1782                          */
1783                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1784                         temp64 = readq(&bar0->general_int_mask);
1785                         val64 |= temp64;
1786                         writeq(val64, &bar0->general_int_mask);
1787                 }
1788         }
1789 }
1790
1791 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1792 {
1793         int ret = 0;
1794
1795         if (flag == FALSE) {
1796                 if ((!herc && (rev_id >= 4)) || herc) {
1797                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1798                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1799                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1800                                 ret = 1;
1801                         }
1802                 }else {
1803                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1804                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1805                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1806                                 ret = 1;
1807                         }
1808                 }
1809         } else {
1810                 if ((!herc && (rev_id >= 4)) || herc) {
1811                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1812                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1813                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1814                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1815                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1816                                 ret = 1;
1817                         }
1818                 } else {
1819                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1820                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1821                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1822                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1823                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1824                                 ret = 1;
1825                         }
1826                 }
1827         }
1828
1829         return ret;
1830 }
1831 /**
1832  *  verify_xena_quiescence - Checks whether the H/W is ready
1833  *  @val64 :  Value read from adapter status register.
1834  *  @flag : indicates if the adapter enable bit was ever written once
1835  *  before.
1836  *  Description: Returns whether the H/W is ready to go or not. Depending
1837  *  on whether adapter enable bit was written or not the comparison
1838  *  differs and the calling function passes the input argument flag to
1839  *  indicate this.
1840  *  Return: 1 If xena is quiescence
1841  *          0 If Xena is not quiescence
1842  */
1843
1844 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1845 {
1846         int ret = 0, herc;
1847         u64 tmp64 = ~((u64) val64);
1848         int rev_id = get_xena_rev_id(sp->pdev);
1849
1850         herc = (sp->device_type == XFRAME_II_DEVICE);
1851         if (!
1852             (tmp64 &
1853              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1854               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1855               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1856               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1857               ADAPTER_STATUS_P_PLL_LOCK))) {
1858                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1859         }
1860
1861         return ret;
1862 }
1863
1864 /**
1865  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1866  * @sp: Pointer to device specifc structure
1867  * Description :
1868  * New procedure to clear mac address reading  problems on Alpha platforms
1869  *
1870  */
1871
1872 static void fix_mac_address(nic_t * sp)
1873 {
1874         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1875         u64 val64;
1876         int i = 0;
1877
1878         while (fix_mac[i] != END_SIGN) {
1879                 writeq(fix_mac[i++], &bar0->gpio_control);
1880                 udelay(10);
1881                 val64 = readq(&bar0->gpio_control);
1882         }
1883 }
1884
1885 /**
1886  *  start_nic - Turns the device on
1887  *  @nic : device private variable.
1888  *  Description:
1889  *  This function actually turns the device on. Before this  function is
1890  *  called,all Registers are configured from their reset states
1891  *  and shared memory is allocated but the NIC is still quiescent. On
1892  *  calling this function, the device interrupts are cleared and the NIC is
1893  *  literally switched on by writing into the adapter control register.
1894  *  Return Value:
1895  *  SUCCESS on success and -1 on failure.
1896  */
1897
1898 static int start_nic(struct s2io_nic *nic)
1899 {
1900         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1901         struct net_device *dev = nic->dev;
1902         register u64 val64 = 0;
1903         u16 interruptible;
1904         u16 subid, i;
1905         mac_info_t *mac_control;
1906         struct config_param *config;
1907
1908         mac_control = &nic->mac_control;
1909         config = &nic->config;
1910
1911         /*  PRC Initialization and configuration */
1912         for (i = 0; i < config->rx_ring_num; i++) {
1913                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1914                        &bar0->prc_rxd0_n[i]);
1915
1916                 val64 = readq(&bar0->prc_ctrl_n[i]);
1917                 if (nic->config.bimodal)
1918                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1919                 if (nic->rxd_mode == RXD_MODE_1)
1920                         val64 |= PRC_CTRL_RC_ENABLED;
1921                 else
1922                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1923                 writeq(val64, &bar0->prc_ctrl_n[i]);
1924         }
1925
1926         if (nic->rxd_mode == RXD_MODE_3B) {
1927                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1928                 val64 = readq(&bar0->rx_pa_cfg);
1929                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1930                 writeq(val64, &bar0->rx_pa_cfg);
1931         }
1932
1933         /*
1934          * Enabling MC-RLDRAM. After enabling the device, we timeout
1935          * for around 100ms, which is approximately the time required
1936          * for the device to be ready for operation.
1937          */
1938         val64 = readq(&bar0->mc_rldram_mrs);
1939         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1940         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1941         val64 = readq(&bar0->mc_rldram_mrs);
1942
1943         msleep(100);    /* Delay by around 100 ms. */
1944
1945         /* Enabling ECC Protection. */
1946         val64 = readq(&bar0->adapter_control);
1947         val64 &= ~ADAPTER_ECC_EN;
1948         writeq(val64, &bar0->adapter_control);
1949
1950         /*
1951          * Clearing any possible Link state change interrupts that
1952          * could have popped up just before Enabling the card.
1953          */
1954         val64 = readq(&bar0->mac_rmac_err_reg);
1955         if (val64)
1956                 writeq(val64, &bar0->mac_rmac_err_reg);
1957
1958         /*
1959          * Verify if the device is ready to be enabled, if so enable
1960          * it.
1961          */
1962         val64 = readq(&bar0->adapter_status);
1963         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1964                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1965                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1966                           (unsigned long long) val64);
1967                 return FAILURE;
1968         }
1969
1970         /*  Enable select interrupts */
1971         if (nic->intr_type != INTA)
1972                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
1973         else {
1974                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1975                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1976                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1977                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1978         }
1979
1980         /*
1981          * With some switches, link might be already up at this point.
1982          * Because of this weird behavior, when we enable laser,
1983          * we may not get link. We need to handle this. We cannot
1984          * figure out which switch is misbehaving. So we are forced to
1985          * make a global change.
1986          */
1987
1988         /* Enabling Laser. */
1989         val64 = readq(&bar0->adapter_control);
1990         val64 |= ADAPTER_EOI_TX_ON;
1991         writeq(val64, &bar0->adapter_control);
1992
1993         /* SXE-002: Initialize link and activity LED */
1994         subid = nic->pdev->subsystem_device;
1995         if (((subid & 0xFF) >= 0x07) &&
1996             (nic->device_type == XFRAME_I_DEVICE)) {
1997                 val64 = readq(&bar0->gpio_control);
1998                 val64 |= 0x0000800000000000ULL;
1999                 writeq(val64, &bar0->gpio_control);
2000                 val64 = 0x0411040400000000ULL;
2001                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2002         }
2003
2004         /*
2005          * Don't see link state interrupts on certain switches, so
2006          * directly scheduling a link state task from here.
2007          */
2008         schedule_work(&nic->set_link_task);
2009
2010         return SUCCESS;
2011 }
2012 /**
2013  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2014  */
2015 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2016 {
2017         nic_t *nic = fifo_data->nic;
2018         struct sk_buff *skb;
2019         TxD_t *txds;
2020         u16 j, frg_cnt;
2021
2022         txds = txdlp;
2023         if (txds->Host_Control == (u64) nic->ufo_in_band_v) {
2024                 pci_unmap_single(nic->pdev, (dma_addr_t)
2025                         txds->Buffer_Pointer, sizeof(u64),
2026                         PCI_DMA_TODEVICE);
2027                 txds++;
2028         }
2029
2030         skb = (struct sk_buff *) ((unsigned long)
2031                         txds->Host_Control);
2032         if (!skb) {
2033                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2034                 return NULL;
2035         }
2036         pci_unmap_single(nic->pdev, (dma_addr_t)
2037                          txds->Buffer_Pointer,
2038                          skb->len - skb->data_len,
2039                          PCI_DMA_TODEVICE);
2040         frg_cnt = skb_shinfo(skb)->nr_frags;
2041         if (frg_cnt) {
2042                 txds++;
2043                 for (j = 0; j < frg_cnt; j++, txds++) {
2044                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2045                         if (!txds->Buffer_Pointer)
2046                                 break;
2047                         pci_unmap_page(nic->pdev, (dma_addr_t)
2048                                         txds->Buffer_Pointer,
2049                                        frag->size, PCI_DMA_TODEVICE);
2050                 }
2051         }
2052         txdlp->Host_Control = 0;
2053         return(skb);
2054 }
2055
2056 /**
2057  *  free_tx_buffers - Free all queued Tx buffers
2058  *  @nic : device private variable.
2059  *  Description:
2060  *  Free all queued Tx buffers.
2061  *  Return Value: void
2062 */
2063
2064 static void free_tx_buffers(struct s2io_nic *nic)
2065 {
2066         struct net_device *dev = nic->dev;
2067         struct sk_buff *skb;
2068         TxD_t *txdp;
2069         int i, j;
2070         mac_info_t *mac_control;
2071         struct config_param *config;
2072         int cnt = 0;
2073
2074         mac_control = &nic->mac_control;
2075         config = &nic->config;
2076
2077         for (i = 0; i < config->tx_fifo_num; i++) {
2078                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2079                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2080                             list_virt_addr;
2081                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2082                         if (skb) {
2083                                 dev_kfree_skb(skb);
2084                                 cnt++;
2085                         }
2086                 }
2087                 DBG_PRINT(INTR_DBG,
2088                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2089                           dev->name, cnt, i);
2090                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2091                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2092         }
2093 }
2094
2095 /**
2096  *   stop_nic -  To stop the nic
2097  *   @nic ; device private variable.
2098  *   Description:
2099  *   This function does exactly the opposite of what the start_nic()
2100  *   function does. This function is called to stop the device.
2101  *   Return Value:
2102  *   void.
2103  */
2104
2105 static void stop_nic(struct s2io_nic *nic)
2106 {
2107         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2108         register u64 val64 = 0;
2109         u16 interruptible, i;
2110         mac_info_t *mac_control;
2111         struct config_param *config;
2112
2113         mac_control = &nic->mac_control;
2114         config = &nic->config;
2115
2116         /*  Disable all interrupts */
2117         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2118         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2119         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2120         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2121
2122         /*  Disable PRCs */
2123         for (i = 0; i < config->rx_ring_num; i++) {
2124                 val64 = readq(&bar0->prc_ctrl_n[i]);
2125                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2126                 writeq(val64, &bar0->prc_ctrl_n[i]);
2127         }
2128 }
2129
2130 int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2131 {
2132         struct net_device *dev = nic->dev;
2133         struct sk_buff *frag_list;
2134         void *tmp;
2135
2136         /* Buffer-1 receives L3/L4 headers */
2137         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2138                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2139                         PCI_DMA_FROMDEVICE);
2140
2141         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2142         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2143         if (skb_shinfo(skb)->frag_list == NULL) {
2144                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2145                 return -ENOMEM ;
2146         }
2147         frag_list = skb_shinfo(skb)->frag_list;
2148         frag_list->next = NULL;
2149         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2150         frag_list->data = tmp;
2151         frag_list->tail = tmp;
2152
2153         /* Buffer-2 receives L4 data payload */
2154         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2155                                 frag_list->data, dev->mtu,
2156                                 PCI_DMA_FROMDEVICE);
2157         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2158         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2159
2160         return SUCCESS;
2161 }
2162
2163 /**
2164  *  fill_rx_buffers - Allocates the Rx side skbs
2165  *  @nic:  device private variable
2166  *  @ring_no: ring number
2167  *  Description:
2168  *  The function allocates Rx side skbs and puts the physical
2169  *  address of these buffers into the RxD buffer pointers, so that the NIC
2170  *  can DMA the received frame into these locations.
2171  *  The NIC supports 3 receive modes, viz
2172  *  1. single buffer,
2173  *  2. three buffer and
2174  *  3. Five buffer modes.
2175  *  Each mode defines how many fragments the received frame will be split
2176  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2177  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2178  *  is split into 3 fragments. As of now only single buffer mode is
2179  *  supported.
2180  *   Return Value:
2181  *  SUCCESS on success or an appropriate -ve value on failure.
2182  */
2183
2184 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2185 {
2186         struct net_device *dev = nic->dev;
2187         struct sk_buff *skb;
2188         RxD_t *rxdp;
2189         int off, off1, size, block_no, block_no1;
2190         u32 alloc_tab = 0;
2191         u32 alloc_cnt;
2192         mac_info_t *mac_control;
2193         struct config_param *config;
2194         u64 tmp;
2195         buffAdd_t *ba;
2196 #ifndef CONFIG_S2IO_NAPI
2197         unsigned long flags;
2198 #endif
2199         RxD_t *first_rxdp = NULL;
2200
2201         mac_control = &nic->mac_control;
2202         config = &nic->config;
2203         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2204             atomic_read(&nic->rx_bufs_left[ring_no]);
2205
2206         while (alloc_tab < alloc_cnt) {
2207                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2208                     block_index;
2209                 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
2210                     block_index;
2211                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2212                 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2213
2214                 rxdp = mac_control->rings[ring_no].
2215                                 rx_blocks[block_no].rxds[off].virt_addr;
2216
2217                 if ((block_no == block_no1) && (off == off1) &&
2218                                         (rxdp->Host_Control)) {
2219                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2220                                   dev->name);
2221                         DBG_PRINT(INTR_DBG, " info equated\n");
2222                         goto end;
2223                 }
2224                 if (off && (off == rxd_count[nic->rxd_mode])) {
2225                         mac_control->rings[ring_no].rx_curr_put_info.
2226                             block_index++;
2227                         if (mac_control->rings[ring_no].rx_curr_put_info.
2228                             block_index == mac_control->rings[ring_no].
2229                                         block_count)
2230                                 mac_control->rings[ring_no].rx_curr_put_info.
2231                                         block_index = 0;
2232                         block_no = mac_control->rings[ring_no].
2233                                         rx_curr_put_info.block_index;
2234                         if (off == rxd_count[nic->rxd_mode])
2235                                 off = 0;
2236                         mac_control->rings[ring_no].rx_curr_put_info.
2237                                 offset = off;
2238                         rxdp = mac_control->rings[ring_no].
2239                                 rx_blocks[block_no].block_virt_addr;
2240                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2241                                   dev->name, rxdp);
2242                 }
2243 #ifndef CONFIG_S2IO_NAPI
2244                 spin_lock_irqsave(&nic->put_lock, flags);
2245                 mac_control->rings[ring_no].put_pos =
2246                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2247                 spin_unlock_irqrestore(&nic->put_lock, flags);
2248 #endif
2249                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2250                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2251                                 (rxdp->Control_2 & BIT(0)))) {
2252                         mac_control->rings[ring_no].rx_curr_put_info.
2253                                         offset = off;
2254                         goto end;
2255                 }
2256                 /* calculate size of skb based on ring mode */
2257                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2258                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2259                 if (nic->rxd_mode == RXD_MODE_1)
2260                         size += NET_IP_ALIGN;
2261                 else if (nic->rxd_mode == RXD_MODE_3B)
2262                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2263                 else
2264                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2265
2266                 /* allocate skb */
2267                 skb = dev_alloc_skb(size);
2268                 if(!skb) {
2269                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2270                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2271                         if (first_rxdp) {
2272                                 wmb();
2273                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2274                         }
2275                         return -ENOMEM ;
2276                 }
2277                 if (nic->rxd_mode == RXD_MODE_1) {
2278                         /* 1 buffer mode - normal operation mode */
2279                         memset(rxdp, 0, sizeof(RxD1_t));
2280                         skb_reserve(skb, NET_IP_ALIGN);
2281                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2282                             (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
2283                         rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_1);
2284                         rxdp->Control_2 |= SET_BUFFER0_SIZE_1(size);
2285
2286                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2287                         /*
2288                          * 2 or 3 buffer mode -
2289                          * Both 2 buffer mode and 3 buffer mode provides 128
2290                          * byte aligned receive buffers.
2291                          *
2292                          * 3 buffer mode provides header separation where in
2293                          * skb->data will have L3/L4 headers where as
2294                          * skb_shinfo(skb)->frag_list will have the L4 data
2295                          * payload
2296                          */
2297
2298                         memset(rxdp, 0, sizeof(RxD3_t));
2299                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2300                         skb_reserve(skb, BUF0_LEN);
2301                         tmp = (u64)(unsigned long) skb->data;
2302                         tmp += ALIGN_SIZE;
2303                         tmp &= ~ALIGN_SIZE;
2304                         skb->data = (void *) (unsigned long)tmp;
2305                         skb->tail = (void *) (unsigned long)tmp;
2306
2307                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2308                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2309                                            PCI_DMA_FROMDEVICE);
2310                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2311                         if (nic->rxd_mode == RXD_MODE_3B) {
2312                                 /* Two buffer mode */
2313
2314                                 /*
2315                                  * Buffer2 will have L3/L4 header plus
2316                                  * L4 payload
2317                                  */
2318                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2319                                 (nic->pdev, skb->data, dev->mtu + 4,
2320                                                 PCI_DMA_FROMDEVICE);
2321
2322                                 /* Buffer-1 will be dummy buffer not used */
2323                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2324                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2325                                         PCI_DMA_FROMDEVICE);
2326                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2327                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2328                                                                 (dev->mtu + 4);
2329                         } else {
2330                                 /* 3 buffer mode */
2331                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2332                                         dev_kfree_skb_irq(skb);
2333                                         if (first_rxdp) {
2334                                                 wmb();
2335                                                 first_rxdp->Control_1 |=
2336                                                         RXD_OWN_XENA;
2337                                         }
2338                                         return -ENOMEM ;
2339                                 }
2340                         }
2341                         rxdp->Control_2 |= BIT(0);
2342                 }
2343                 rxdp->Host_Control = (unsigned long) (skb);
2344                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2345                         rxdp->Control_1 |= RXD_OWN_XENA;
2346                 off++;
2347                 if (off == (rxd_count[nic->rxd_mode] + 1))
2348                         off = 0;
2349                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2350
2351                 rxdp->Control_2 |= SET_RXD_MARKER;
2352                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2353                         if (first_rxdp) {
2354                                 wmb();
2355                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2356                         }
2357                         first_rxdp = rxdp;
2358                 }
2359                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2360                 alloc_tab++;
2361         }
2362
2363       end:
2364         /* Transfer ownership of first descriptor to adapter just before
2365          * exiting. Before that, use memory barrier so that ownership
2366          * and other fields are seen by adapter correctly.
2367          */
2368         if (first_rxdp) {
2369                 wmb();
2370                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2371         }
2372
2373         return SUCCESS;
2374 }
2375
2376 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2377 {
2378         struct net_device *dev = sp->dev;
2379         int j;
2380         struct sk_buff *skb;
2381         RxD_t *rxdp;
2382         mac_info_t *mac_control;
2383         buffAdd_t *ba;
2384
2385         mac_control = &sp->mac_control;
2386         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2387                 rxdp = mac_control->rings[ring_no].
2388                                 rx_blocks[blk].rxds[j].virt_addr;
2389                 skb = (struct sk_buff *)
2390                         ((unsigned long) rxdp->Host_Control);
2391                 if (!skb) {
2392                         continue;
2393                 }
2394                 if (sp->rxd_mode == RXD_MODE_1) {
2395                         pci_unmap_single(sp->pdev, (dma_addr_t)
2396                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2397                                  dev->mtu +
2398                                  HEADER_ETHERNET_II_802_3_SIZE
2399                                  + HEADER_802_2_SIZE +
2400                                  HEADER_SNAP_SIZE,
2401                                  PCI_DMA_FROMDEVICE);
2402                         memset(rxdp, 0, sizeof(RxD1_t));
2403                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2404                         ba = &mac_control->rings[ring_no].
2405                                 ba[blk][j];
2406                         pci_unmap_single(sp->pdev, (dma_addr_t)
2407                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2408                                  BUF0_LEN,
2409                                  PCI_DMA_FROMDEVICE);
2410                         pci_unmap_single(sp->pdev, (dma_addr_t)
2411                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2412                                  BUF1_LEN,
2413                                  PCI_DMA_FROMDEVICE);
2414                         pci_unmap_single(sp->pdev, (dma_addr_t)
2415                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2416                                  dev->mtu + 4,
2417                                  PCI_DMA_FROMDEVICE);
2418                         memset(rxdp, 0, sizeof(RxD3_t));
2419                 } else {
2420                         pci_unmap_single(sp->pdev, (dma_addr_t)
2421                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2422                                 PCI_DMA_FROMDEVICE);
2423                         pci_unmap_single(sp->pdev, (dma_addr_t)
2424                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2425                                 l3l4hdr_size + 4,
2426                                 PCI_DMA_FROMDEVICE);
2427                         pci_unmap_single(sp->pdev, (dma_addr_t)
2428                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2429                                 PCI_DMA_FROMDEVICE);
2430                         memset(rxdp, 0, sizeof(RxD3_t));
2431                 }
2432                 dev_kfree_skb(skb);
2433                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2434         }
2435 }
2436
2437 /**
2438  *  free_rx_buffers - Frees all Rx buffers
2439  *  @sp: device private variable.
2440  *  Description:
2441  *  This function will free all Rx buffers allocated by host.
2442  *  Return Value:
2443  *  NONE.
2444  */
2445
2446 static void free_rx_buffers(struct s2io_nic *sp)
2447 {
2448         struct net_device *dev = sp->dev;
2449         int i, blk = 0, buf_cnt = 0;
2450         mac_info_t *mac_control;
2451         struct config_param *config;
2452
2453         mac_control = &sp->mac_control;
2454         config = &sp->config;
2455
2456         for (i = 0; i < config->rx_ring_num; i++) {
2457                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2458                         free_rxd_blk(sp,i,blk);
2459
2460                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2461                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2462                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2463                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2464                 atomic_set(&sp->rx_bufs_left[i], 0);
2465                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2466                           dev->name, buf_cnt, i);
2467         }
2468 }
2469
2470 /**
2471  * s2io_poll - Rx interrupt handler for NAPI support
2472  * @dev : pointer to the device structure.
2473  * @budget : The number of packets that were budgeted to be processed
2474  * during  one pass through the 'Poll" function.
2475  * Description:
2476  * Comes into picture only if NAPI support has been incorporated. It does
2477  * the same thing that rx_intr_handler does, but not in a interrupt context
2478  * also It will process only a given number of packets.
2479  * Return value:
2480  * 0 on success and 1 if there are No Rx packets to be processed.
2481  */
2482
2483 #if defined(CONFIG_S2IO_NAPI)
2484 static int s2io_poll(struct net_device *dev, int *budget)
2485 {
2486         nic_t *nic = dev->priv;
2487         int pkt_cnt = 0, org_pkts_to_process;
2488         mac_info_t *mac_control;
2489         struct config_param *config;
2490         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2491         u64 val64;
2492         int i;
2493
2494         atomic_inc(&nic->isr_cnt);
2495         mac_control = &nic->mac_control;
2496         config = &nic->config;
2497
2498         nic->pkts_to_process = *budget;
2499         if (nic->pkts_to_process > dev->quota)
2500                 nic->pkts_to_process = dev->quota;
2501         org_pkts_to_process = nic->pkts_to_process;
2502
2503         val64 = readq(&bar0->rx_traffic_int);
2504         writeq(val64, &bar0->rx_traffic_int);
2505
2506         for (i = 0; i < config->rx_ring_num; i++) {
2507                 rx_intr_handler(&mac_control->rings[i]);
2508                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2509                 if (!nic->pkts_to_process) {
2510                         /* Quota for the current iteration has been met */
2511                         goto no_rx;
2512                 }
2513         }
2514         if (!pkt_cnt)
2515                 pkt_cnt = 1;
2516
2517         dev->quota -= pkt_cnt;
2518         *budget -= pkt_cnt;
2519         netif_rx_complete(dev);
2520
2521         for (i = 0; i < config->rx_ring_num; i++) {
2522                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2523                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2524                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2525                         break;
2526                 }
2527         }
2528         /* Re enable the Rx interrupts. */
2529         en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2530         atomic_dec(&nic->isr_cnt);
2531         return 0;
2532
2533 no_rx:
2534         dev->quota -= pkt_cnt;
2535         *budget -= pkt_cnt;
2536
2537         for (i = 0; i < config->rx_ring_num; i++) {
2538                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2539                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2540                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2541                         break;
2542                 }
2543         }
2544         atomic_dec(&nic->isr_cnt);
2545         return 1;
2546 }
2547 #endif
2548
2549 /**
2550  *  rx_intr_handler - Rx interrupt handler
2551  *  @nic: device private variable.
2552  *  Description:
2553  *  If the interrupt is because of a received frame or if the
2554  *  receive ring contains fresh as yet un-processed frames,this function is
2555  *  called. It picks out the RxD at which place the last Rx processing had
2556  *  stopped and sends the skb to the OSM's Rx handler and then increments
2557  *  the offset.
2558  *  Return Value:
2559  *  NONE.
2560  */
2561 static void rx_intr_handler(ring_info_t *ring_data)
2562 {
2563         nic_t *nic = ring_data->nic;
2564         struct net_device *dev = (struct net_device *) nic->dev;
2565         int get_block, put_block, put_offset;
2566         rx_curr_get_info_t get_info, put_info;
2567         RxD_t *rxdp;
2568         struct sk_buff *skb;
2569 #ifndef CONFIG_S2IO_NAPI
2570         int pkt_cnt = 0;
2571 #endif
2572         spin_lock(&nic->rx_lock);
2573         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2574                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2575                           __FUNCTION__, dev->name);
2576                 spin_unlock(&nic->rx_lock);
2577                 return;
2578         }
2579
2580         get_info = ring_data->rx_curr_get_info;
2581         get_block = get_info.block_index;
2582         put_info = ring_data->rx_curr_put_info;
2583         put_block = put_info.block_index;
2584         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2585 #ifndef CONFIG_S2IO_NAPI
2586         spin_lock(&nic->put_lock);
2587         put_offset = ring_data->put_pos;
2588         spin_unlock(&nic->put_lock);
2589 #else
2590         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2591                 put_info.offset;
2592 #endif
2593         while (RXD_IS_UP2DT(rxdp)) {
2594                 /* If your are next to put index then it's FIFO full condition */
2595                 if ((get_block == put_block) &&
2596                     (get_info.offset + 1) == put_info.offset) {
2597                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2598                         break;
2599                 }
2600                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2601                 if (skb == NULL) {
2602                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2603                                   dev->name);
2604                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2605                         spin_unlock(&nic->rx_lock);
2606                         return;
2607                 }
2608                 if (nic->rxd_mode == RXD_MODE_1) {
2609                         pci_unmap_single(nic->pdev, (dma_addr_t)
2610                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2611                                  dev->mtu +
2612                                  HEADER_ETHERNET_II_802_3_SIZE +
2613                                  HEADER_802_2_SIZE +
2614                                  HEADER_SNAP_SIZE,
2615                                  PCI_DMA_FROMDEVICE);
2616                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2617                         pci_unmap_single(nic->pdev, (dma_addr_t)
2618                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2619                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2620                         pci_unmap_single(nic->pdev, (dma_addr_t)
2621                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2622                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2623                         pci_unmap_single(nic->pdev, (dma_addr_t)
2624                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2625                                  dev->mtu + 4,
2626                                  PCI_DMA_FROMDEVICE);
2627                 } else {
2628                         pci_unmap_single(nic->pdev, (dma_addr_t)
2629                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2630                                          PCI_DMA_FROMDEVICE);
2631                         pci_unmap_single(nic->pdev, (dma_addr_t)
2632                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2633                                          l3l4hdr_size + 4,
2634                                          PCI_DMA_FROMDEVICE);
2635                         pci_unmap_single(nic->pdev, (dma_addr_t)
2636                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2637                                          dev->mtu, PCI_DMA_FROMDEVICE);
2638                 }
2639                 rx_osm_handler(ring_data, rxdp);
2640                 get_info.offset++;
2641                 ring_data->rx_curr_get_info.offset = get_info.offset;
2642                 rxdp = ring_data->rx_blocks[get_block].
2643                                 rxds[get_info.offset].virt_addr;
2644                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2645                         get_info.offset = 0;
2646                         ring_data->rx_curr_get_info.offset = get_info.offset;
2647                         get_block++;
2648                         if (get_block == ring_data->block_count)
2649                                 get_block = 0;
2650                         ring_data->rx_curr_get_info.block_index = get_block;
2651                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2652                 }
2653
2654 #ifdef CONFIG_S2IO_NAPI
2655                 nic->pkts_to_process -= 1;
2656                 if (!nic->pkts_to_process)
2657                         break;
2658 #else
2659                 pkt_cnt++;
2660                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2661                         break;
2662 #endif
2663         }
2664         spin_unlock(&nic->rx_lock);
2665 }
2666
2667 /**
2668  *  tx_intr_handler - Transmit interrupt handler
2669  *  @nic : device private variable
2670  *  Description:
2671  *  If an interrupt was raised to indicate DMA complete of the
2672  *  Tx packet, this function is called. It identifies the last TxD
2673  *  whose buffer was freed and frees all skbs whose data have already
2674  *  DMA'ed into the NICs internal memory.
2675  *  Return Value:
2676  *  NONE
2677  */
2678
2679 static void tx_intr_handler(fifo_info_t *fifo_data)
2680 {
2681         nic_t *nic = fifo_data->nic;
2682         struct net_device *dev = (struct net_device *) nic->dev;
2683         tx_curr_get_info_t get_info, put_info;
2684         struct sk_buff *skb;
2685         TxD_t *txdlp;
2686
2687         get_info = fifo_data->tx_curr_get_info;
2688         put_info = fifo_data->tx_curr_put_info;
2689         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2690             list_virt_addr;
2691         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2692                (get_info.offset != put_info.offset) &&
2693                (txdlp->Host_Control)) {
2694                 /* Check for TxD errors */
2695                 if (txdlp->Control_1 & TXD_T_CODE) {
2696                         unsigned long long err;
2697                         err = txdlp->Control_1 & TXD_T_CODE;
2698                         if ((err >> 48) == 0xA) {
2699                                 DBG_PRINT(TX_DBG, "TxD returned due \
2700 to loss of link\n");
2701                         }
2702                         else {
2703                                 DBG_PRINT(ERR_DBG, "***TxD error \
2704 %llx\n", err);
2705                         }
2706                 }
2707
2708                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2709                 if (skb == NULL) {
2710                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2711                         __FUNCTION__);
2712                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2713                         return;
2714                 }
2715
2716                 /* Updating the statistics block */
2717                 nic->stats.tx_bytes += skb->len;
2718                 dev_kfree_skb_irq(skb);
2719
2720                 get_info.offset++;
2721                 get_info.offset %= get_info.fifo_len + 1;
2722                 txdlp = (TxD_t *) fifo_data->list_info
2723                     [get_info.offset].list_virt_addr;
2724                 fifo_data->tx_curr_get_info.offset =
2725                     get_info.offset;
2726         }
2727
2728         spin_lock(&nic->tx_lock);
2729         if (netif_queue_stopped(dev))
2730                 netif_wake_queue(dev);
2731         spin_unlock(&nic->tx_lock);
2732 }
2733
2734 /**
2735  *  alarm_intr_handler - Alarm Interrrupt handler
2736  *  @nic: device private variable
2737  *  Description: If the interrupt was neither because of Rx packet or Tx
2738  *  complete, this function is called. If the interrupt was to indicate
2739  *  a loss of link, the OSM link status handler is invoked for any other
2740  *  alarm interrupt the block that raised the interrupt is displayed
2741  *  and a H/W reset is issued.
2742  *  Return Value:
2743  *  NONE
2744 */
2745
2746 static void alarm_intr_handler(struct s2io_nic *nic)
2747 {
2748         struct net_device *dev = (struct net_device *) nic->dev;
2749         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2750         register u64 val64 = 0, err_reg = 0;
2751
2752         /* Handling link status change error Intr */
2753         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2754                 err_reg = readq(&bar0->mac_rmac_err_reg);
2755                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2756                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2757                         schedule_work(&nic->set_link_task);
2758                 }
2759         }
2760
2761         /* Handling Ecc errors */
2762         val64 = readq(&bar0->mc_err_reg);
2763         writeq(val64, &bar0->mc_err_reg);
2764         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2765                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2766                         nic->mac_control.stats_info->sw_stat.
2767                                 double_ecc_errs++;
2768                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2769                                   dev->name);
2770                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2771                         if (nic->device_type != XFRAME_II_DEVICE) {
2772                                 /* Reset XframeI only if critical error */
2773                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2774                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2775                                         netif_stop_queue(dev);
2776                                         schedule_work(&nic->rst_timer_task);
2777                                 }
2778                         }
2779                 } else {
2780                         nic->mac_control.stats_info->sw_stat.
2781                                 single_ecc_errs++;
2782                 }
2783         }
2784
2785         /* In case of a serious error, the device will be Reset. */
2786         val64 = readq(&bar0->serr_source);
2787         if (val64 & SERR_SOURCE_ANY) {
2788                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2789                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
2790                           (unsigned long long)val64);
2791                 netif_stop_queue(dev);
2792                 schedule_work(&nic->rst_timer_task);
2793         }
2794
2795         /*
2796          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2797          * Error occurs, the adapter will be recycled by disabling the
2798          * adapter enable bit and enabling it again after the device
2799          * becomes Quiescent.
2800          */
2801         val64 = readq(&bar0->pcc_err_reg);
2802         writeq(val64, &bar0->pcc_err_reg);
2803         if (val64 & PCC_FB_ECC_DB_ERR) {
2804                 u64 ac = readq(&bar0->adapter_control);
2805                 ac &= ~(ADAPTER_CNTL_EN);
2806                 writeq(ac, &bar0->adapter_control);
2807                 ac = readq(&bar0->adapter_control);
2808                 schedule_work(&nic->set_link_task);
2809         }
2810
2811         /* Other type of interrupts are not being handled now,  TODO */
2812 }
2813
2814 /**
2815  *  wait_for_cmd_complete - waits for a command to complete.
2816  *  @sp : private member of the device structure, which is a pointer to the
2817  *  s2io_nic structure.
2818  *  Description: Function that waits for a command to Write into RMAC
2819  *  ADDR DATA registers to be completed and returns either success or
2820  *  error depending on whether the command was complete or not.
2821  *  Return value:
2822  *   SUCCESS on success and FAILURE on failure.
2823  */
2824
2825 static int wait_for_cmd_complete(nic_t * sp)
2826 {
2827         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2828         int ret = FAILURE, cnt = 0;
2829         u64 val64;
2830
2831         while (TRUE) {
2832                 val64 = readq(&bar0->rmac_addr_cmd_mem);
2833                 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2834                         ret = SUCCESS;
2835                         break;
2836                 }
2837                 msleep(50);
2838                 if (cnt++ > 10)
2839                         break;
2840         }
2841
2842         return ret;
2843 }
2844
2845 /**
2846  *  s2io_reset - Resets the card.
2847  *  @sp : private member of the device structure.
2848  *  Description: Function to Reset the card. This function then also
2849  *  restores the previously saved PCI configuration space registers as
2850  *  the card reset also resets the configuration space.
2851  *  Return value:
2852  *  void.
2853  */
2854
2855 void s2io_reset(nic_t * sp)
2856 {
2857         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2858         u64 val64;
2859         u16 subid, pci_cmd;
2860
2861         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2862         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2863
2864         val64 = SW_RESET_ALL;
2865         writeq(val64, &bar0->sw_reset);
2866
2867         /*
2868          * At this stage, if the PCI write is indeed completed, the
2869          * card is reset and so is the PCI Config space of the device.
2870          * So a read cannot be issued at this stage on any of the
2871          * registers to ensure the write into "sw_reset" register
2872          * has gone through.
2873          * Question: Is there any system call that will explicitly force
2874          * all the write commands still pending on the bus to be pushed
2875          * through?
2876          * As of now I'am just giving a 250ms delay and hoping that the
2877          * PCI write to sw_reset register is done by this time.
2878          */
2879         msleep(250);
2880
2881         /* Restore the PCI state saved during initialization. */
2882         pci_restore_state(sp->pdev);
2883         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2884                                      pci_cmd);
2885         s2io_init_pci(sp);
2886
2887         msleep(250);
2888
2889         /* Set swapper to enable I/O register access */
2890         s2io_set_swapper(sp);
2891
2892         /* Restore the MSIX table entries from local variables */
2893         restore_xmsi_data(sp);
2894
2895         /* Clear certain PCI/PCI-X fields after reset */
2896         if (sp->device_type == XFRAME_II_DEVICE) {
2897                 /* Clear parity err detect bit */
2898                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2899
2900                 /* Clearing PCIX Ecc status register */
2901                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2902
2903                 /* Clearing PCI_STATUS error reflected here */
2904                 writeq(BIT(62), &bar0->txpic_int_reg);
2905         }
2906
2907         /* Reset device statistics maintained by OS */
2908         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2909
2910         /* SXE-002: Configure link and activity LED to turn it off */
2911         subid = sp->pdev->subsystem_device;
2912         if (((subid & 0xFF) >= 0x07) &&
2913             (sp->device_type == XFRAME_I_DEVICE)) {
2914                 val64 = readq(&bar0->gpio_control);
2915                 val64 |= 0x0000800000000000ULL;
2916                 writeq(val64, &bar0->gpio_control);
2917                 val64 = 0x0411040400000000ULL;
2918                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2919         }
2920
2921         /*
2922          * Clear spurious ECC interrupts that would have occured on
2923          * XFRAME II cards after reset.
2924          */
2925         if (sp->device_type == XFRAME_II_DEVICE) {
2926                 val64 = readq(&bar0->pcc_err_reg);
2927                 writeq(val64, &bar0->pcc_err_reg);
2928         }
2929
2930         sp->device_enabled_once = FALSE;
2931 }
2932
2933 /**
2934  *  s2io_set_swapper - to set the swapper controle on the card
2935  *  @sp : private member of the device structure,
2936  *  pointer to the s2io_nic structure.
2937  *  Description: Function to set the swapper control on the card
2938  *  correctly depending on the 'endianness' of the system.
2939  *  Return value:
2940  *  SUCCESS on success and FAILURE on failure.
2941  */
2942
2943 int s2io_set_swapper(nic_t * sp)
2944 {
2945         struct net_device *dev = sp->dev;
2946         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2947         u64 val64, valt, valr;
2948
2949         /*
2950          * Set proper endian settings and verify the same by reading
2951          * the PIF Feed-back register.
2952          */
2953
2954         val64 = readq(&bar0->pif_rd_swapper_fb);
2955         if (val64 != 0x0123456789ABCDEFULL) {
2956                 int i = 0;
2957                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
2958                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
2959                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
2960                                 0};                     /* FE=0, SE=0 */
2961
2962                 while(i<4) {
2963                         writeq(value[i], &bar0->swapper_ctrl);
2964                         val64 = readq(&bar0->pif_rd_swapper_fb);
2965                         if (val64 == 0x0123456789ABCDEFULL)
2966                                 break;
2967                         i++;
2968                 }
2969                 if (i == 4) {
2970                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2971                                 dev->name);
2972                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2973                                 (unsigned long long) val64);
2974                         return FAILURE;
2975                 }
2976                 valr = value[i];
2977         } else {
2978                 valr = readq(&bar0->swapper_ctrl);
2979         }
2980
2981         valt = 0x0123456789ABCDEFULL;
2982         writeq(valt, &bar0->xmsi_address);
2983         val64 = readq(&bar0->xmsi_address);
2984
2985         if(val64 != valt) {
2986                 int i = 0;
2987                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
2988                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
2989                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
2990                                 0};                     /* FE=0, SE=0 */
2991
2992                 while(i<4) {
2993                         writeq((value[i] | valr), &bar0->swapper_ctrl);
2994                         writeq(valt, &bar0->xmsi_address);
2995                         val64 = readq(&bar0->xmsi_address);
2996                         if(val64 == valt)
2997                                 break;
2998                         i++;
2999                 }
3000                 if(i == 4) {
3001                         unsigned long long x = val64;
3002                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3003                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3004                         return FAILURE;
3005                 }
3006         }
3007         val64 = readq(&bar0->swapper_ctrl);
3008         val64 &= 0xFFFF000000000000ULL;
3009
3010 #ifdef  __BIG_ENDIAN
3011         /*
3012          * The device by default set to a big endian format, so a
3013          * big endian driver need not set anything.
3014          */
3015         val64 |= (SWAPPER_CTRL_TXP_FE |
3016                  SWAPPER_CTRL_TXP_SE |
3017                  SWAPPER_CTRL_TXD_R_FE |
3018                  SWAPPER_CTRL_TXD_W_FE |
3019                  SWAPPER_CTRL_TXF_R_FE |
3020                  SWAPPER_CTRL_RXD_R_FE |
3021                  SWAPPER_CTRL_RXD_W_FE |
3022                  SWAPPER_CTRL_RXF_W_FE |
3023                  SWAPPER_CTRL_XMSI_FE |
3024                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3025         if (sp->intr_type == INTA)
3026                 val64 |= SWAPPER_CTRL_XMSI_SE;
3027         writeq(val64, &bar0->swapper_ctrl);
3028 #else
3029         /*
3030          * Initially we enable all bits to make it accessible by the
3031          * driver, then we selectively enable only those bits that
3032          * we want to set.
3033          */
3034         val64 |= (SWAPPER_CTRL_TXP_FE |
3035                  SWAPPER_CTRL_TXP_SE |
3036                  SWAPPER_CTRL_TXD_R_FE |
3037                  SWAPPER_CTRL_TXD_R_SE |
3038                  SWAPPER_CTRL_TXD_W_FE |
3039                  SWAPPER_CTRL_TXD_W_SE |
3040                  SWAPPER_CTRL_TXF_R_FE |
3041                  SWAPPER_CTRL_RXD_R_FE |
3042                  SWAPPER_CTRL_RXD_R_SE |
3043                  SWAPPER_CTRL_RXD_W_FE |
3044                  SWAPPER_CTRL_RXD_W_SE |
3045                  SWAPPER_CTRL_RXF_W_FE |
3046                  SWAPPER_CTRL_XMSI_FE |
3047                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3048         if (sp->intr_type == INTA)
3049                 val64 |= SWAPPER_CTRL_XMSI_SE;
3050         writeq(val64, &bar0->swapper_ctrl);
3051 #endif
3052         val64 = readq(&bar0->swapper_ctrl);
3053
3054         /*
3055          * Verifying if endian settings are accurate by reading a
3056          * feedback register.
3057          */
3058         val64 = readq(&bar0->pif_rd_swapper_fb);
3059         if (val64 != 0x0123456789ABCDEFULL) {
3060                 /* Endian settings are incorrect, calls for another dekko. */
3061                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3062                           dev->name);
3063                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3064                           (unsigned long long) val64);
3065                 return FAILURE;
3066         }
3067
3068         return SUCCESS;
3069 }
3070
3071 static int wait_for_msix_trans(nic_t *nic, int i)
3072 {
3073         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3074         u64 val64;
3075         int ret = 0, cnt = 0;
3076
3077         do {
3078                 val64 = readq(&bar0->xmsi_access);
3079                 if (!(val64 & BIT(15)))
3080                         break;
3081                 mdelay(1);
3082                 cnt++;
3083         } while(cnt < 5);
3084         if (cnt == 5) {
3085                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3086                 ret = 1;
3087         }
3088
3089         return ret;
3090 }
3091
3092 void restore_xmsi_data(nic_t *nic)
3093 {
3094         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3095         u64 val64;
3096         int i;
3097
3098         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3099                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3100                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3101                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3102                 writeq(val64, &bar0->xmsi_access);
3103                 if (wait_for_msix_trans(nic, i)) {
3104                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3105                         continue;
3106                 }
3107         }
3108 }
3109
3110 static void store_xmsi_data(nic_t *nic)
3111 {
3112         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3113         u64 val64, addr, data;
3114         int i;
3115
3116         /* Store and display */
3117         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3118                 val64 = (BIT(15) | vBIT(i, 26, 6));
3119                 writeq(val64, &bar0->xmsi_access);
3120                 if (wait_for_msix_trans(nic, i)) {
3121                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3122                         continue;
3123                 }
3124                 addr = readq(&bar0->xmsi_address);
3125                 data = readq(&bar0->xmsi_data);
3126                 if (addr && data) {
3127                         nic->msix_info[i].addr = addr;
3128                         nic->msix_info[i].data = data;
3129                 }
3130         }
3131 }
3132
3133 int s2io_enable_msi(nic_t *nic)
3134 {
3135         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3136         u16 msi_ctrl, msg_val;
3137         struct config_param *config = &nic->config;
3138         struct net_device *dev = nic->dev;
3139         u64 val64, tx_mat, rx_mat;
3140         int i, err;
3141
3142         val64 = readq(&bar0->pic_control);
3143         val64 &= ~BIT(1);
3144         writeq(val64, &bar0->pic_control);
3145
3146         err = pci_enable_msi(nic->pdev);
3147         if (err) {
3148                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3149                           nic->dev->name);
3150                 return err;
3151         }
3152
3153         /*
3154          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3155          * for interrupt handling.
3156          */
3157         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3158         msg_val ^= 0x1;
3159         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3160         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3161
3162         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3163         msi_ctrl |= 0x10;
3164         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3165
3166         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3167         tx_mat = readq(&bar0->tx_mat0_n[0]);
3168         for (i=0; i<config->tx_fifo_num; i++) {
3169                 tx_mat |= TX_MAT_SET(i, 1);
3170         }
3171         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3172
3173         rx_mat = readq(&bar0->rx_mat);
3174         for (i=0; i<config->rx_ring_num; i++) {
3175                 rx_mat |= RX_MAT_SET(i, 1);
3176         }
3177         writeq(rx_mat, &bar0->rx_mat);
3178
3179         dev->irq = nic->pdev->irq;
3180         return 0;
3181 }
3182
3183 int s2io_enable_msi_x(nic_t *nic)
3184 {
3185         XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
3186         u64 tx_mat, rx_mat;
3187         u16 msi_control; /* Temp variable */
3188         int ret, i, j, msix_indx = 1;
3189
3190         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3191                                GFP_KERNEL);
3192         if (nic->entries == NULL) {
3193                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3194                 return -ENOMEM;
3195         }
3196         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3197
3198         nic->s2io_entries =
3199                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3200                                    GFP_KERNEL);
3201         if (nic->s2io_entries == NULL) {
3202                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3203                 kfree(nic->entries);
3204                 return -ENOMEM;
3205         }
3206         memset(nic->s2io_entries, 0,
3207                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3208
3209         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3210                 nic->entries[i].entry = i;
3211                 nic->s2io_entries[i].entry = i;
3212                 nic->s2io_entries[i].arg = NULL;
3213                 nic->s2io_entries[i].in_use = 0;
3214         }
3215
3216         tx_mat = readq(&bar0->tx_mat0_n[0]);
3217         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3218                 tx_mat |= TX_MAT_SET(i, msix_indx);
3219                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3220                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3221                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3222         }
3223         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3224
3225         if (!nic->config.bimodal) {
3226                 rx_mat = readq(&bar0->rx_mat);
3227                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3228                         rx_mat |= RX_MAT_SET(j, msix_indx);
3229                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3230                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3231                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3232                 }
3233                 writeq(rx_mat, &bar0->rx_mat);
3234         } else {
3235                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3236                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3237                         tx_mat |= TX_MAT_SET(i, msix_indx);
3238                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3239                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3240                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3241                 }
3242                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3243         }
3244
3245         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3246         if (ret) {
3247                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3248                 kfree(nic->entries);
3249                 kfree(nic->s2io_entries);
3250                 nic->entries = NULL;
3251                 nic->s2io_entries = NULL;
3252                 return -ENOMEM;
3253         }
3254
3255         /*
3256          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3257          * in the herc NIC. (Temp change, needs to be removed later)
3258          */
3259         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3260         msi_control |= 0x1; /* Enable MSI */
3261         pci_write_config_word(nic->pdev, 0x42, msi_control);
3262
3263         return 0;
3264 }
3265
3266 /* ********************************************************* *
3267  * Functions defined below concern the OS part of the driver *
3268  * ********************************************************* */
3269
3270 /**
3271  *  s2io_open - open entry point of the driver
3272  *  @dev : pointer to the device structure.
3273  *  Description:
3274  *  This function is the open entry point of the driver. It mainly calls a
3275  *  function to allocate Rx buffers and inserts them into the buffer
3276  *  descriptors and then enables the Rx part of the NIC.
3277  *  Return value:
3278  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3279  *   file on failure.
3280  */
3281
3282 static int s2io_open(struct net_device *dev)
3283 {
3284         nic_t *sp = dev->priv;
3285         int err = 0;
3286         int i;
3287         u16 msi_control; /* Temp variable */
3288
3289         /*
3290          * Make sure you have link off by default every time
3291          * Nic is initialized
3292          */
3293         netif_carrier_off(dev);
3294         sp->last_link_state = 0;
3295
3296         /* Initialize H/W and enable interrupts */
3297         if (s2io_card_up(sp)) {
3298                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3299                           dev->name);
3300                 err = -ENODEV;
3301                 goto hw_init_failed;
3302         }
3303
3304         /* Store the values of the MSIX table in the nic_t structure */
3305         store_xmsi_data(sp);
3306
3307         /* After proper initialization of H/W, register ISR */
3308         if (sp->intr_type == MSI) {
3309                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3310                         SA_SHIRQ, sp->name, dev);
3311                 if (err) {
3312                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3313 failed\n", dev->name);
3314                         goto isr_registration_failed;
3315                 }
3316         }
3317         if (sp->intr_type == MSI_X) {
3318                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3319                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3320                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3321                                         dev->name, i);
3322                                 err = request_irq(sp->entries[i].vector,
3323                                           s2io_msix_fifo_handle, 0, sp->desc1,
3324                                           sp->s2io_entries[i].arg);
3325                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3326                                                         sp->msix_info[i].addr);
3327                         } else {
3328                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3329                                         dev->name, i);
3330                                 err = request_irq(sp->entries[i].vector,
3331                                           s2io_msix_ring_handle, 0, sp->desc2,
3332                                           sp->s2io_entries[i].arg);
3333                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3334                                                         sp->msix_info[i].addr);
3335                         }
3336                         if (err) {
3337                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3338 failed\n", dev->name, i);
3339                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3340                                 goto isr_registration_failed;
3341                         }
3342                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3343                 }
3344         }
3345         if (sp->intr_type == INTA) {
3346                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3347                                 sp->name, dev);
3348                 if (err) {
3349                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3350                                   dev->name);
3351                         goto isr_registration_failed;
3352                 }
3353         }
3354
3355         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3356                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3357                 err = -ENODEV;
3358                 goto setting_mac_address_failed;
3359         }
3360
3361         netif_start_queue(dev);
3362         return 0;
3363
3364 setting_mac_address_failed:
3365         if (sp->intr_type != MSI_X)
3366                 free_irq(sp->pdev->irq, dev);
3367 isr_registration_failed:
3368         del_timer_sync(&sp->alarm_timer);
3369         if (sp->intr_type == MSI_X) {
3370                 if (sp->device_type == XFRAME_II_DEVICE) {
3371                         for (i=1; (sp->s2io_entries[i].in_use ==
3372                                 MSIX_REGISTERED_SUCCESS); i++) {
3373                                 int vector = sp->entries[i].vector;
3374                                 void *arg = sp->s2io_entries[i].arg;
3375
3376                                 free_irq(vector, arg);
3377                         }
3378                         pci_disable_msix(sp->pdev);
3379
3380                         /* Temp */
3381                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3382                         msi_control &= 0xFFFE; /* Disable MSI */
3383                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3384                 }
3385         }
3386         else if (sp->intr_type == MSI)
3387                 pci_disable_msi(sp->pdev);
3388         s2io_reset(sp);
3389 hw_init_failed:
3390         if (sp->intr_type == MSI_X) {
3391                 if (sp->entries)
3392                         kfree(sp->entries);
3393                 if (sp->s2io_entries)
3394                         kfree(sp->s2io_entries);
3395         }
3396         return err;
3397 }
3398
3399 /**
3400  *  s2io_close -close entry point of the driver
3401  *  @dev : device pointer.
3402  *  Description:
3403  *  This is the stop entry point of the driver. It needs to undo exactly
3404  *  whatever was done by the open entry point,thus it's usually referred to
3405  *  as the close function.Among other things this function mainly stops the
3406  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3407  *  Return value:
3408  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3409  *  file on failure.
3410  */
3411
3412 static int s2io_close(struct net_device *dev)
3413 {
3414         nic_t *sp = dev->priv;
3415         int i;
3416         u16 msi_control;
3417
3418         flush_scheduled_work();
3419         netif_stop_queue(dev);
3420         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3421         s2io_card_down(sp);
3422
3423         if (sp->intr_type == MSI_X) {
3424                 if (sp->device_type == XFRAME_II_DEVICE) {
3425                         for (i=1; (sp->s2io_entries[i].in_use ==
3426                                         MSIX_REGISTERED_SUCCESS); i++) {
3427                                 int vector = sp->entries[i].vector;
3428                                 void *arg = sp->s2io_entries[i].arg;
3429
3430                                 free_irq(vector, arg);
3431                         }
3432                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3433                         msi_control &= 0xFFFE; /* Disable MSI */
3434                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3435
3436                         pci_disable_msix(sp->pdev);
3437                 }
3438         }
3439         else {
3440                 free_irq(sp->pdev->irq, dev);
3441                 if (sp->intr_type == MSI)
3442                         pci_disable_msi(sp->pdev);
3443         }
3444         sp->device_close_flag = TRUE;   /* Device is shut down. */
3445         return 0;
3446 }
3447
3448 /**
3449  *  s2io_xmit - Tx entry point of te driver
3450  *  @skb : the socket buffer containing the Tx data.
3451  *  @dev : device pointer.
3452  *  Description :
3453  *  This function is the Tx entry point of the driver. S2IO NIC supports
3454  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3455  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3456  *  not be upadted.
3457  *  Return value:
3458  *  0 on success & 1 on failure.
3459  */
3460
3461 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3462 {
3463         nic_t *sp = dev->priv;
3464         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3465         register u64 val64;
3466         TxD_t *txdp;
3467         TxFIFO_element_t __iomem *tx_fifo;
3468         unsigned long flags;
3469 #ifdef NETIF_F_TSO
3470         int mss;
3471 #endif
3472         u16 vlan_tag = 0;
3473         int vlan_priority = 0;
3474         mac_info_t *mac_control;
3475         struct config_param *config;
3476
3477         mac_control = &sp->mac_control;
3478         config = &sp->config;
3479
3480         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3481         spin_lock_irqsave(&sp->tx_lock, flags);
3482         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3483                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3484                           dev->name);
3485                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3486                 dev_kfree_skb(skb);
3487                 return 0;
3488         }
3489
3490         queue = 0;
3491
3492         /* Get Fifo number to Transmit based on vlan priority */
3493         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3494                 vlan_tag = vlan_tx_tag_get(skb);
3495                 vlan_priority = vlan_tag >> 13;
3496                 queue = config->fifo_mapping[vlan_priority];
3497         }
3498
3499         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3500         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3501         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3502                 list_virt_addr;
3503
3504         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3505         /* Avoid "put" pointer going beyond "get" pointer */
3506         if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
3507                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3508                 netif_stop_queue(dev);
3509                 dev_kfree_skb(skb);
3510                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3511                 return 0;
3512         }
3513
3514         /* A buffer with no data will be dropped */
3515         if (!skb->len) {
3516                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3517                 dev_kfree_skb(skb);
3518                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3519                 return 0;
3520         }
3521
3522         txdp->Control_1 = 0;
3523         txdp->Control_2 = 0;
3524 #ifdef NETIF_F_TSO
3525         mss = skb_shinfo(skb)->tso_size;
3526         if (mss) {
3527                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3528                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3529         }
3530 #endif
3531         if (skb->ip_summed == CHECKSUM_HW) {
3532                 txdp->Control_2 |=
3533                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3534                      TXD_TX_CKO_UDP_EN);
3535         }
3536         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3537         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3538         txdp->Control_2 |= config->tx_intr_type;
3539
3540         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3541                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3542                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3543         }
3544
3545         frg_len = skb->len - skb->data_len;
3546         if (skb_shinfo(skb)->ufo_size) {
3547                 int ufo_size;
3548
3549                 ufo_size = skb_shinfo(skb)->ufo_size;
3550                 ufo_size &= ~7;
3551                 txdp->Control_1 |= TXD_UFO_EN;
3552                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3553                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3554 #ifdef __BIG_ENDIAN
3555                 sp->ufo_in_band_v[put_off] =
3556                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3557 #else
3558                 sp->ufo_in_band_v[put_off] =
3559                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3560 #endif
3561                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3562                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3563                                         sp->ufo_in_band_v,
3564                                         sizeof(u64), PCI_DMA_TODEVICE);
3565                 txdp++;
3566                 txdp->Control_1 = 0;
3567                 txdp->Control_2 = 0;
3568         }
3569
3570         txdp->Buffer_Pointer = pci_map_single
3571             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3572         txdp->Host_Control = (unsigned long) skb;
3573         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3574
3575         if (skb_shinfo(skb)->ufo_size)
3576                 txdp->Control_1 |= TXD_UFO_EN;
3577
3578         frg_cnt = skb_shinfo(skb)->nr_frags;
3579         /* For fragmented SKB. */
3580         for (i = 0; i < frg_cnt; i++) {
3581                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3582                 /* A '0' length fragment will be ignored */
3583                 if (!frag->size)
3584                         continue;
3585                 txdp++;
3586                 txdp->Buffer_Pointer = (u64) pci_map_page
3587                     (sp->pdev, frag->page, frag->page_offset,
3588                      frag->size, PCI_DMA_TODEVICE);
3589                 txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
3590                 if (skb_shinfo(skb)->ufo_size)
3591                         txdp->Control_1 |= TXD_UFO_EN;
3592         }
3593         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3594
3595         if (skb_shinfo(skb)->ufo_size)
3596                 frg_cnt++; /* as Txd0 was used for inband header */
3597
3598         tx_fifo = mac_control->tx_FIFO_start[queue];
3599         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3600         writeq(val64, &tx_fifo->TxDL_Pointer);
3601
3602         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3603                  TX_FIFO_LAST_LIST);
3604
3605 #ifdef NETIF_F_TSO
3606         if (mss)
3607                 val64 |= TX_FIFO_SPECIAL_FUNC;
3608 #endif
3609         if (skb_shinfo(skb)->ufo_size)
3610                 val64 |= TX_FIFO_SPECIAL_FUNC;
3611         writeq(val64, &tx_fifo->List_Control);
3612
3613         mmiowb();
3614
3615         put_off++;
3616         put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3617         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3618
3619         /* Avoid "put" pointer going beyond "get" pointer */
3620         if (((put_off + 1) % queue_len) == get_off) {
3621                 DBG_PRINT(TX_DBG,
3622                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3623                           put_off, get_off);
3624                 netif_stop_queue(dev);
3625         }
3626
3627         dev->trans_start = jiffies;
3628         spin_unlock_irqrestore(&sp->tx_lock, flags);
3629
3630         return 0;
3631 }
3632
3633 static void
3634 s2io_alarm_handle(unsigned long data)
3635 {
3636         nic_t *sp = (nic_t *)data;
3637
3638         alarm_intr_handler(sp);
3639         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3640 }
3641
3642 static irqreturn_t
3643 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3644 {
3645         struct net_device *dev = (struct net_device *) dev_id;
3646         nic_t *sp = dev->priv;
3647         int i;
3648         int ret;
3649         mac_info_t *mac_control;
3650         struct config_param *config;
3651
3652         atomic_inc(&sp->isr_cnt);
3653         mac_control = &sp->mac_control;
3654         config = &sp->config;
3655         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3656
3657         /* If Intr is because of Rx Traffic */
3658         for (i = 0; i < config->rx_ring_num; i++)
3659                 rx_intr_handler(&mac_control->rings[i]);
3660
3661         /* If Intr is because of Tx Traffic */
3662         for (i = 0; i < config->tx_fifo_num; i++)
3663                 tx_intr_handler(&mac_control->fifos[i]);
3664
3665         /*
3666          * If the Rx buffer count is below the panic threshold then
3667          * reallocate the buffers from the interrupt handler itself,
3668          * else schedule a tasklet to reallocate the buffers.
3669          */
3670         for (i = 0; i < config->rx_ring_num; i++) {
3671                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3672                 int level = rx_buffer_level(sp, rxb_size, i);
3673
3674                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3675                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3676                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3677                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3678                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3679                                           dev->name);
3680                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3681                                 clear_bit(0, (&sp->tasklet_status));
3682                                 atomic_dec(&sp->isr_cnt);
3683                                 return IRQ_HANDLED;
3684                         }
3685                         clear_bit(0, (&sp->tasklet_status));
3686                 } else if (level == LOW) {
3687                         tasklet_schedule(&sp->task);
3688                 }
3689         }
3690
3691         atomic_dec(&sp->isr_cnt);
3692         return IRQ_HANDLED;
3693 }
3694
3695 static irqreturn_t
3696 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3697 {
3698         ring_info_t *ring = (ring_info_t *)dev_id;
3699         nic_t *sp = ring->nic;
3700         int rxb_size, level, rng_n;
3701
3702         atomic_inc(&sp->isr_cnt);
3703         rx_intr_handler(ring);
3704
3705         rng_n = ring->ring_no;
3706         rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3707         level = rx_buffer_level(sp, rxb_size, rng_n);
3708
3709         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3710                 int ret;
3711                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3712                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3713                 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3714                         DBG_PRINT(ERR_DBG, "Out of memory in %s",
3715                                   __FUNCTION__);
3716                         clear_bit(0, (&sp->tasklet_status));
3717                         return IRQ_HANDLED;
3718                 }
3719                 clear_bit(0, (&sp->tasklet_status));
3720         } else if (level == LOW) {
3721                 tasklet_schedule(&sp->task);
3722         }
3723         atomic_dec(&sp->isr_cnt);
3724
3725         return IRQ_HANDLED;
3726 }
3727
3728 static irqreturn_t
3729 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3730 {
3731         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3732         nic_t *sp = fifo->nic;
3733
3734         atomic_inc(&sp->isr_cnt);
3735         tx_intr_handler(fifo);
3736         atomic_dec(&sp->isr_cnt);
3737         return IRQ_HANDLED;
3738 }
3739
3740 static void s2io_txpic_intr_handle(nic_t *sp)
3741 {
3742         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3743         u64 val64;
3744
3745         val64 = readq(&bar0->pic_int_status);
3746         if (val64 & PIC_INT_GPIO) {
3747                 val64 = readq(&bar0->gpio_int_reg);
3748                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3749                     (val64 & GPIO_INT_REG_LINK_UP)) {
3750                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3751                         val64 |= GPIO_INT_REG_LINK_UP;
3752                         writeq(val64, &bar0->gpio_int_reg);
3753                         goto masking;
3754                 }
3755
3756                 if (((sp->last_link_state == LINK_UP) &&
3757                         (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3758                 ((sp->last_link_state == LINK_DOWN) &&
3759                 (val64 & GPIO_INT_REG_LINK_UP))) {
3760                         val64 = readq(&bar0->gpio_int_mask);
3761                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3762                         val64 |= GPIO_INT_MASK_LINK_UP;
3763                         writeq(val64, &bar0->gpio_int_mask);
3764                         s2io_set_link((unsigned long)sp);
3765                 }
3766 masking:
3767                 if (sp->last_link_state == LINK_UP) {
3768                         /*enable down interrupt */
3769                         val64 = readq(&bar0->gpio_int_mask);
3770                         /* unmasks link down intr */
3771                         val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
3772                         /* masks link up intr */
3773                         val64 |= GPIO_INT_MASK_LINK_UP;
3774                         writeq(val64, &bar0->gpio_int_mask);
3775                 } else {
3776                         /*enable UP Interrupt */
3777                         val64 = readq(&bar0->gpio_int_mask);
3778                         /* unmasks link up interrupt */
3779                         val64 &= ~GPIO_INT_MASK_LINK_UP;
3780                         /* masks link down interrupt */
3781                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3782                         writeq(val64, &bar0->gpio_int_mask);
3783                 }
3784         }
3785 }
3786
3787 /**
3788  *  s2io_isr - ISR handler of the device .
3789  *  @irq: the irq of the device.
3790  *  @dev_id: a void pointer to the dev structure of the NIC.
3791  *  @pt_regs: pointer to the registers pushed on the stack.
3792  *  Description:  This function is the ISR handler of the device. It
3793  *  identifies the reason for the interrupt and calls the relevant
3794  *  service routines. As a contongency measure, this ISR allocates the
3795  *  recv buffers, if their numbers are below the panic value which is
3796  *  presently set to 25% of the original number of rcv buffers allocated.
3797  *  Return value:
3798  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3799  *   IRQ_NONE: will be returned if interrupt is not from our device
3800  */
3801 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3802 {
3803         struct net_device *dev = (struct net_device *) dev_id;
3804         nic_t *sp = dev->priv;
3805         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3806         int i;
3807         u64 reason = 0, val64;
3808         mac_info_t *mac_control;
3809         struct config_param *config;
3810
3811         atomic_inc(&sp->isr_cnt);
3812         mac_control = &sp->mac_control;
3813         config = &sp->config;
3814
3815         /*
3816          * Identify the cause for interrupt and call the appropriate
3817          * interrupt handler. Causes for the interrupt could be;
3818          * 1. Rx of packet.
3819          * 2. Tx complete.
3820          * 3. Link down.
3821          * 4. Error in any functional blocks of the NIC.
3822          */
3823         reason = readq(&bar0->general_int_status);
3824
3825         if (!reason) {
3826                 /* The interrupt was not raised by Xena. */
3827                 atomic_dec(&sp->isr_cnt);
3828                 return IRQ_NONE;
3829         }
3830
3831 #ifdef CONFIG_S2IO_NAPI
3832         if (reason & GEN_INTR_RXTRAFFIC) {
3833                 if (netif_rx_schedule_prep(dev)) {
3834                         en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
3835                                               DISABLE_INTRS);
3836                         __netif_rx_schedule(dev);
3837                 }
3838         }
3839 #else
3840         /* If Intr is because of Rx Traffic */
3841         if (reason & GEN_INTR_RXTRAFFIC) {
3842                 /*
3843                  * rx_traffic_int reg is an R1 register, writing all 1's
3844                  * will ensure that the actual interrupt causing bit get's
3845                  * cleared and hence a read can be avoided.
3846                  */
3847                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3848                 writeq(val64, &bar0->rx_traffic_int);
3849                 for (i = 0; i < config->rx_ring_num; i++) {
3850                         rx_intr_handler(&mac_control->rings[i]);
3851                 }
3852         }
3853 #endif
3854
3855         /* If Intr is because of Tx Traffic */
3856         if (reason & GEN_INTR_TXTRAFFIC) {
3857                 /*
3858                  * tx_traffic_int reg is an R1 register, writing all 1's
3859                  * will ensure that the actual interrupt causing bit get's
3860                  * cleared and hence a read can be avoided.
3861                  */
3862                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3863                 writeq(val64, &bar0->tx_traffic_int);
3864
3865                 for (i = 0; i < config->tx_fifo_num; i++)
3866                         tx_intr_handler(&mac_control->fifos[i]);
3867         }
3868
3869         if (reason & GEN_INTR_TXPIC)
3870                 s2io_txpic_intr_handle(sp);
3871         /*
3872          * If the Rx buffer count is below the panic threshold then
3873          * reallocate the buffers from the interrupt handler itself,
3874          * else schedule a tasklet to reallocate the buffers.
3875          */
3876 #ifndef CONFIG_S2IO_NAPI
3877         for (i = 0; i < config->rx_ring_num; i++) {
3878                 int ret;
3879                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3880                 int level = rx_buffer_level(sp, rxb_size, i);
3881
3882                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3883                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3884                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3885                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3886                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3887                                           dev->name);
3888                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3889                                 clear_bit(0, (&sp->tasklet_status));
3890                                 atomic_dec(&sp->isr_cnt);
3891                                 return IRQ_HANDLED;
3892                         }
3893                         clear_bit(0, (&sp->tasklet_status));
3894                 } else if (level == LOW) {
3895                         tasklet_schedule(&sp->task);
3896                 }
3897         }
3898 #endif
3899
3900         atomic_dec(&sp->isr_cnt);
3901         return IRQ_HANDLED;
3902 }
3903
3904 /**
3905  * s2io_updt_stats -
3906  */
3907 static void s2io_updt_stats(nic_t *sp)
3908 {
3909         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3910         u64 val64;
3911         int cnt = 0;
3912
3913         if (atomic_read(&sp->card_state) == CARD_UP) {
3914                 /* Apprx 30us on a 133 MHz bus */
3915                 val64 = SET_UPDT_CLICKS(10) |
3916                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3917                 writeq(val64, &bar0->stat_cfg);
3918                 do {
3919                         udelay(100);
3920                         val64 = readq(&bar0->stat_cfg);
3921                         if (!(val64 & BIT(0)))
3922                                 break;
3923                         cnt++;
3924                         if (cnt == 5)
3925                                 break; /* Updt failed */
3926                 } while(1);
3927         }
3928 }
3929
3930 /**
3931  *  s2io_get_stats - Updates the device statistics structure.
3932  *  @dev : pointer to the device structure.
3933  *  Description:
3934  *  This function updates the device statistics structure in the s2io_nic
3935  *  structure and returns a pointer to the same.
3936  *  Return value:
3937  *  pointer to the updated net_device_stats structure.
3938  */
3939
3940 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
3941 {
3942         nic_t *sp = dev->priv;
3943         mac_info_t *mac_control;
3944         struct config_param *config;
3945
3946
3947         mac_control = &sp->mac_control;
3948         config = &sp->config;
3949
3950         /* Configure Stats for immediate updt */
3951         s2io_updt_stats(sp);
3952
3953         sp->stats.tx_packets =
3954                 le32_to_cpu(mac_control->stats_info->tmac_frms);
3955         sp->stats.tx_errors =
3956                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
3957         sp->stats.rx_errors =
3958                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
3959         sp->stats.multicast =
3960                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
3961         sp->stats.rx_length_errors =
3962                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
3963
3964         return (&sp->stats);
3965 }
3966
3967 /**
3968  *  s2io_set_multicast - entry point for multicast address enable/disable.
3969  *  @dev : pointer to the device structure
3970  *  Description:
3971  *  This function is a driver entry point which gets called by the kernel
3972  *  whenever multicast addresses must be enabled/disabled. This also gets
3973  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
3974  *  determine, if multicast address must be enabled or if promiscuous mode
3975  *  is to be disabled etc.
3976  *  Return value:
3977  *  void.
3978  */
3979
3980 static void s2io_set_multicast(struct net_device *dev)
3981 {
3982         int i, j, prev_cnt;
3983         struct dev_mc_list *mclist;
3984         nic_t *sp = dev->priv;
3985         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3986         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
3987             0xfeffffffffffULL;
3988         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
3989         void __iomem *add;
3990
3991         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
3992                 /*  Enable all Multicast addresses */
3993                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
3994                        &bar0->rmac_addr_data0_mem);
3995                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
3996                        &bar0->rmac_addr_data1_mem);
3997                 val64 = RMAC_ADDR_CMD_MEM_WE |
3998                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3999                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4000                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4001                 /* Wait till command completes */
4002                 wait_for_cmd_complete(sp);
4003
4004                 sp->m_cast_flg = 1;
4005                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4006         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4007                 /*  Disable all Multicast addresses */
4008                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4009                        &bar0->rmac_addr_data0_mem);
4010                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4011                        &bar0->rmac_addr_data1_mem);
4012                 val64 = RMAC_ADDR_CMD_MEM_WE |
4013                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4014                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4015                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4016                 /* Wait till command completes */
4017                 wait_for_cmd_complete(sp);
4018
4019                 sp->m_cast_flg = 0;
4020                 sp->all_multi_pos = 0;
4021         }
4022
4023         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4024                 /*  Put the NIC into promiscuous mode */
4025                 add = &bar0->mac_cfg;
4026                 val64 = readq(&bar0->mac_cfg);
4027                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4028
4029                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4030                 writel((u32) val64, add);
4031                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4032                 writel((u32) (val64 >> 32), (add + 4));
4033
4034                 val64 = readq(&bar0->mac_cfg);
4035                 sp->promisc_flg = 1;
4036                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4037                           dev->name);
4038         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4039                 /*  Remove the NIC from promiscuous mode */
4040                 add = &bar0->mac_cfg;
4041                 val64 = readq(&bar0->mac_cfg);
4042                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4043
4044                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4045                 writel((u32) val64, add);
4046                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4047                 writel((u32) (val64 >> 32), (add + 4));
4048
4049                 val64 = readq(&bar0->mac_cfg);
4050                 sp->promisc_flg = 0;
4051                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4052                           dev->name);
4053         }
4054
4055         /*  Update individual M_CAST address list */
4056         if ((!sp->m_cast_flg) && dev->mc_count) {
4057                 if (dev->mc_count >
4058                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4059                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4060                                   dev->name);
4061                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4062                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4063                         return;
4064                 }
4065
4066                 prev_cnt = sp->mc_addr_count;
4067                 sp->mc_addr_count = dev->mc_count;
4068
4069                 /* Clear out the previous list of Mc in the H/W. */
4070                 for (i = 0; i < prev_cnt; i++) {
4071                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4072                                &bar0->rmac_addr_data0_mem);
4073                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4074                                 &bar0->rmac_addr_data1_mem);
4075                         val64 = RMAC_ADDR_CMD_MEM_WE |
4076                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4077                             RMAC_ADDR_CMD_MEM_OFFSET
4078                             (MAC_MC_ADDR_START_OFFSET + i);
4079                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4080
4081                         /* Wait for command completes */
4082                         if (wait_for_cmd_complete(sp)) {
4083                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4084                                           dev->name);
4085                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4086                                 return;
4087                         }
4088                 }
4089
4090                 /* Create the new Rx filter list and update the same in H/W. */
4091                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4092                      i++, mclist = mclist->next) {
4093                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4094                                ETH_ALEN);
4095                         for (j = 0; j < ETH_ALEN; j++) {
4096                                 mac_addr |= mclist->dmi_addr[j];
4097                                 mac_addr <<= 8;
4098                         }
4099                         mac_addr >>= 8;
4100                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4101                                &bar0->rmac_addr_data0_mem);
4102                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4103                                 &bar0->rmac_addr_data1_mem);
4104                         val64 = RMAC_ADDR_CMD_MEM_WE |
4105                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4106                             RMAC_ADDR_CMD_MEM_OFFSET
4107                             (i + MAC_MC_ADDR_START_OFFSET);
4108                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4109
4110                         /* Wait for command completes */
4111                         if (wait_for_cmd_complete(sp)) {
4112                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4113                                           dev->name);
4114                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4115                                 return;
4116                         }
4117                 }
4118         }
4119 }
4120
4121 /**
4122  *  s2io_set_mac_addr - Programs the Xframe mac address
4123  *  @dev : pointer to the device structure.
4124  *  @addr: a uchar pointer to the new mac address which is to be set.
4125  *  Description : This procedure will program the Xframe to receive
4126  *  frames with new Mac Address
4127  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4128  *  as defined in errno.h file on failure.
4129  */
4130
4131 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4132 {
4133         nic_t *sp = dev->priv;
4134         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4135         register u64 val64, mac_addr = 0;
4136         int i;
4137
4138         /*
4139          * Set the new MAC address as the new unicast filter and reflect this
4140          * change on the device address registered with the OS. It will be
4141          * at offset 0.
4142          */
4143         for (i = 0; i < ETH_ALEN; i++) {
4144                 mac_addr <<= 8;
4145                 mac_addr |= addr[i];
4146         }
4147
4148         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4149                &bar0->rmac_addr_data0_mem);
4150
4151         val64 =
4152             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4153             RMAC_ADDR_CMD_MEM_OFFSET(0);
4154         writeq(val64, &bar0->rmac_addr_cmd_mem);
4155         /* Wait till command completes */
4156         if (wait_for_cmd_complete(sp)) {
4157                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4158                 return FAILURE;
4159         }
4160
4161         return SUCCESS;
4162 }
4163
4164 /**
4165  * s2io_ethtool_sset - Sets different link parameters.
4166  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4167  * @info: pointer to the structure with parameters given by ethtool to set
4168  * link information.
4169  * Description:
4170  * The function sets different link parameters provided by the user onto
4171  * the NIC.
4172  * Return value:
4173  * 0 on success.
4174 */
4175
4176 static int s2io_ethtool_sset(struct net_device *dev,
4177                              struct ethtool_cmd *info)
4178 {
4179         nic_t *sp = dev->priv;
4180         if ((info->autoneg == AUTONEG_ENABLE) ||
4181             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4182                 return -EINVAL;
4183         else {
4184                 s2io_close(sp->dev);
4185                 s2io_open(sp->dev);
4186         }
4187
4188         return 0;
4189 }
4190
4191 /**
4192  * s2io_ethtol_gset - Return link specific information.
4193  * @sp : private member of the device structure, pointer to the
4194  *      s2io_nic structure.
4195  * @info : pointer to the structure with parameters given by ethtool
4196  * to return link information.
4197  * Description:
4198  * Returns link specific information like speed, duplex etc.. to ethtool.
4199  * Return value :
4200  * return 0 on success.
4201  */
4202
4203 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4204 {
4205         nic_t *sp = dev->priv;
4206         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4207         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4208         info->port = PORT_FIBRE;
4209         /* info->transceiver?? TODO */
4210
4211         if (netif_carrier_ok(sp->dev)) {
4212                 info->speed = 10000;
4213                 info->duplex = DUPLEX_FULL;
4214         } else {
4215                 info->speed = -1;
4216                 info->duplex = -1;
4217         }
4218
4219         info->autoneg = AUTONEG_DISABLE;
4220         return 0;
4221 }
4222
4223 /**
4224  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4225  * @sp : private member of the device structure, which is a pointer to the
4226  * s2io_nic structure.
4227  * @info : pointer to the structure with parameters given by ethtool to
4228  * return driver information.
4229  * Description:
4230  * Returns driver specefic information like name, version etc.. to ethtool.
4231  * Return value:
4232  *  void
4233  */
4234
4235 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4236                                   struct ethtool_drvinfo *info)
4237 {
4238         nic_t *sp = dev->priv;
4239
4240         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4241         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4242         strncpy(info->fw_version, "", sizeof(info->fw_version));
4243         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4244         info->regdump_len = XENA_REG_SPACE;
4245         info->eedump_len = XENA_EEPROM_SPACE;
4246         info->testinfo_len = S2IO_TEST_LEN;
4247         info->n_stats = S2IO_STAT_LEN;
4248 }
4249
4250 /**
4251  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4252  *  @sp: private member of the device structure, which is a pointer to the
4253  *  s2io_nic structure.
4254  *  @regs : pointer to the structure with parameters given by ethtool for
4255  *  dumping the registers.
4256  *  @reg_space: The input argumnet into which all the registers are dumped.
4257  *  Description:
4258  *  Dumps the entire register space of xFrame NIC into the user given
4259  *  buffer area.
4260  * Return value :
4261  * void .
4262 */
4263
4264 static void s2io_ethtool_gregs(struct net_device *dev,
4265                                struct ethtool_regs *regs, void *space)
4266 {
4267         int i;
4268         u64 reg;
4269         u8 *reg_space = (u8 *) space;
4270         nic_t *sp = dev->priv;
4271
4272         regs->len = XENA_REG_SPACE;
4273         regs->version = sp->pdev->subsystem_device;
4274
4275         for (i = 0; i < regs->len; i += 8) {
4276                 reg = readq(sp->bar0 + i);
4277                 memcpy((reg_space + i), &reg, 8);
4278         }
4279 }
4280
4281 /**
4282  *  s2io_phy_id  - timer function that alternates adapter LED.
4283  *  @data : address of the private member of the device structure, which
4284  *  is a pointer to the s2io_nic structure, provided as an u32.
4285  * Description: This is actually the timer function that alternates the
4286  * adapter LED bit of the adapter control bit to set/reset every time on
4287  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4288  *  once every second.
4289 */
4290 static void s2io_phy_id(unsigned long data)
4291 {
4292         nic_t *sp = (nic_t *) data;
4293         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4294         u64 val64 = 0;
4295         u16 subid;
4296
4297         subid = sp->pdev->subsystem_device;
4298         if ((sp->device_type == XFRAME_II_DEVICE) ||
4299                    ((subid & 0xFF) >= 0x07)) {
4300                 val64 = readq(&bar0->gpio_control);
4301                 val64 ^= GPIO_CTRL_GPIO_0;
4302                 writeq(val64, &bar0->gpio_control);
4303         } else {
4304                 val64 = readq(&bar0->adapter_control);
4305                 val64 ^= ADAPTER_LED_ON;
4306                 writeq(val64, &bar0->adapter_control);
4307         }
4308
4309         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4310 }
4311
4312 /**
4313  * s2io_ethtool_idnic - To physically identify the nic on the system.
4314  * @sp : private member of the device structure, which is a pointer to the
4315  * s2io_nic structure.
4316  * @id : pointer to the structure with identification parameters given by
4317  * ethtool.
4318  * Description: Used to physically identify the NIC on the system.
4319  * The Link LED will blink for a time specified by the user for
4320  * identification.
4321  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4322  * identification is possible only if it's link is up.
4323  * Return value:
4324  * int , returns 0 on success
4325  */
4326
4327 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4328 {
4329         u64 val64 = 0, last_gpio_ctrl_val;
4330         nic_t *sp = dev->priv;
4331         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4332         u16 subid;
4333
4334         subid = sp->pdev->subsystem_device;
4335         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4336         if ((sp->device_type == XFRAME_I_DEVICE) &&
4337                 ((subid & 0xFF) < 0x07)) {
4338                 val64 = readq(&bar0->adapter_control);
4339                 if (!(val64 & ADAPTER_CNTL_EN)) {
4340                         printk(KERN_ERR
4341                                "Adapter Link down, cannot blink LED\n");
4342                         return -EFAULT;
4343                 }
4344         }
4345         if (sp->id_timer.function == NULL) {
4346                 init_timer(&sp->id_timer);
4347                 sp->id_timer.function = s2io_phy_id;
4348                 sp->id_timer.data = (unsigned long) sp;
4349         }
4350         mod_timer(&sp->id_timer, jiffies);
4351         if (data)
4352                 msleep_interruptible(data * HZ);
4353         else
4354                 msleep_interruptible(MAX_FLICKER_TIME);
4355         del_timer_sync(&sp->id_timer);
4356
4357         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4358                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4359                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4360         }
4361
4362         return 0;
4363 }
4364
4365 /**
4366  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4367  * @sp : private member of the device structure, which is a pointer to the
4368  *      s2io_nic structure.
4369  * @ep : pointer to the structure with pause parameters given by ethtool.
4370  * Description:
4371  * Returns the Pause frame generation and reception capability of the NIC.
4372  * Return value:
4373  *  void
4374  */
4375 static void s2io_ethtool_getpause_data(struct net_device *dev,
4376                                        struct ethtool_pauseparam *ep)
4377 {
4378         u64 val64;
4379         nic_t *sp = dev->priv;
4380         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4381
4382         val64 = readq(&bar0->rmac_pause_cfg);
4383         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4384                 ep->tx_pause = TRUE;
4385         if (val64 & RMAC_PAUSE_RX_ENABLE)
4386                 ep->rx_pause = TRUE;
4387         ep->autoneg = FALSE;
4388 }
4389
4390 /**
4391  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4392  * @sp : private member of the device structure, which is a pointer to the
4393  *      s2io_nic structure.
4394  * @ep : pointer to the structure with pause parameters given by ethtool.
4395  * Description:
4396  * It can be used to set or reset Pause frame generation or reception
4397  * support of the NIC.
4398  * Return value:
4399  * int, returns 0 on Success
4400  */
4401
4402 static int s2io_ethtool_setpause_data(struct net_device *dev,
4403                                struct ethtool_pauseparam *ep)
4404 {
4405         u64 val64;
4406         nic_t *sp = dev->priv;
4407         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4408
4409         val64 = readq(&bar0->rmac_pause_cfg);
4410         if (ep->tx_pause)
4411                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4412         else
4413                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4414         if (ep->rx_pause)
4415                 val64 |= RMAC_PAUSE_RX_ENABLE;
4416         else
4417                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4418         writeq(val64, &bar0->rmac_pause_cfg);
4419         return 0;
4420 }
4421
4422 /**
4423  * read_eeprom - reads 4 bytes of data from user given offset.
4424  * @sp : private member of the device structure, which is a pointer to the
4425  *      s2io_nic structure.
4426  * @off : offset at which the data must be written
4427  * @data : Its an output parameter where the data read at the given
4428  *      offset is stored.
4429  * Description:
4430  * Will read 4 bytes of data from the user given offset and return the
4431  * read data.
4432  * NOTE: Will allow to read only part of the EEPROM visible through the
4433  *   I2C bus.
4434  * Return value:
4435  *  -1 on failure and 0 on success.
4436  */
4437
4438 #define S2IO_DEV_ID             5
4439 static int read_eeprom(nic_t * sp, int off, u64 * data)
4440 {
4441         int ret = -1;
4442         u32 exit_cnt = 0;
4443         u64 val64;
4444         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4445
4446         if (sp->device_type == XFRAME_I_DEVICE) {
4447                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4448                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4449                     I2C_CONTROL_CNTL_START;
4450                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4451
4452                 while (exit_cnt < 5) {
4453                         val64 = readq(&bar0->i2c_control);
4454                         if (I2C_CONTROL_CNTL_END(val64)) {
4455                                 *data = I2C_CONTROL_GET_DATA(val64);
4456                                 ret = 0;
4457                                 break;
4458                         }
4459                         msleep(50);
4460                         exit_cnt++;
4461                 }
4462         }
4463
4464         if (sp->device_type == XFRAME_II_DEVICE) {
4465                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4466                         SPI_CONTROL_BYTECNT(0x3) |
4467                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4468                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4469                 val64 |= SPI_CONTROL_REQ;
4470                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4471                 while (exit_cnt < 5) {
4472                         val64 = readq(&bar0->spi_control);
4473                         if (val64 & SPI_CONTROL_NACK) {
4474                                 ret = 1;
4475                                 break;
4476                         } else if (val64 & SPI_CONTROL_DONE) {
4477                                 *data = readq(&bar0->spi_data);
4478                                 *data &= 0xffffff;
4479                                 ret = 0;
4480                                 break;
4481                         }
4482                         msleep(50);
4483                         exit_cnt++;
4484                 }
4485         }
4486         return ret;
4487 }
4488
4489 /**
4490  *  write_eeprom - actually writes the relevant part of the data value.
4491  *  @sp : private member of the device structure, which is a pointer to the
4492  *       s2io_nic structure.
4493  *  @off : offset at which the data must be written
4494  *  @data : The data that is to be written
4495  *  @cnt : Number of bytes of the data that are actually to be written into
4496  *  the Eeprom. (max of 3)
4497  * Description:
4498  *  Actually writes the relevant part of the data value into the Eeprom
4499  *  through the I2C bus.
4500  * Return value:
4501  *  0 on success, -1 on failure.
4502  */
4503
4504 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4505 {
4506         int exit_cnt = 0, ret = -1;
4507         u64 val64;
4508         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4509
4510         if (sp->device_type == XFRAME_I_DEVICE) {
4511                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4512                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4513                     I2C_CONTROL_CNTL_START;
4514                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4515
4516                 while (exit_cnt < 5) {
4517                         val64 = readq(&bar0->i2c_control);
4518                         if (I2C_CONTROL_CNTL_END(val64)) {
4519                                 if (!(val64 & I2C_CONTROL_NACK))
4520                                         ret = 0;
4521                                 break;
4522                         }
4523                         msleep(50);
4524                         exit_cnt++;
4525                 }
4526         }
4527
4528         if (sp->device_type == XFRAME_II_DEVICE) {
4529                 int write_cnt = (cnt == 8) ? 0 : cnt;
4530                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4531
4532                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4533                         SPI_CONTROL_BYTECNT(write_cnt) |
4534                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4535                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4536                 val64 |= SPI_CONTROL_REQ;
4537                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4538                 while (exit_cnt < 5) {
4539                         val64 = readq(&bar0->spi_control);
4540                         if (val64 & SPI_CONTROL_NACK) {
4541                                 ret = 1;
4542                                 break;
4543                         } else if (val64 & SPI_CONTROL_DONE) {
4544                                 ret = 0;
4545                                 break;
4546                         }
4547                         msleep(50);
4548                         exit_cnt++;
4549                 }
4550         }
4551         return ret;
4552 }
4553
4554 /**
4555  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4556  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4557  *  @eeprom : pointer to the user level structure provided by ethtool,
4558  *  containing all relevant information.
4559  *  @data_buf : user defined value to be written into Eeprom.
4560  *  Description: Reads the values stored in the Eeprom at given offset
4561  *  for a given length. Stores these values int the input argument data
4562  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4563  *  Return value:
4564  *  int  0 on success
4565  */
4566
4567 static int s2io_ethtool_geeprom(struct net_device *dev,
4568                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4569 {
4570         u32 i, valid;
4571         u64 data;
4572         nic_t *sp = dev->priv;
4573
4574         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4575
4576         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4577                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4578
4579         for (i = 0; i < eeprom->len; i += 4) {
4580                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4581                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4582                         return -EFAULT;
4583                 }
4584                 valid = INV(data);
4585                 memcpy((data_buf + i), &valid, 4);
4586         }
4587         return 0;
4588 }
4589
4590 /**
4591  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4592  *  @sp : private member of the device structure, which is a pointer to the
4593  *  s2io_nic structure.
4594  *  @eeprom : pointer to the user level structure provided by ethtool,
4595  *  containing all relevant information.
4596  *  @data_buf ; user defined value to be written into Eeprom.
4597  *  Description:
4598  *  Tries to write the user provided value in the Eeprom, at the offset
4599  *  given by the user.
4600  *  Return value:
4601  *  0 on success, -EFAULT on failure.
4602  */
4603
4604 static int s2io_ethtool_seeprom(struct net_device *dev,
4605                                 struct ethtool_eeprom *eeprom,
4606                                 u8 * data_buf)
4607 {
4608         int len = eeprom->len, cnt = 0;
4609         u64 valid = 0, data;
4610         nic_t *sp = dev->priv;
4611
4612         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4613                 DBG_PRINT(ERR_DBG,
4614                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4615                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4616                           eeprom->magic);
4617                 return -EFAULT;
4618         }
4619
4620         while (len) {
4621                 data = (u32) data_buf[cnt] & 0x000000FF;
4622                 if (data) {
4623                         valid = (u32) (data << 24);
4624                 } else
4625                         valid = data;
4626
4627                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4628                         DBG_PRINT(ERR_DBG,
4629                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4630                         DBG_PRINT(ERR_DBG,
4631                                   "write into the specified offset\n");
4632                         return -EFAULT;
4633                 }
4634                 cnt++;
4635                 len--;
4636         }
4637
4638         return 0;
4639 }
4640
4641 /**
4642  * s2io_register_test - reads and writes into all clock domains.
4643  * @sp : private member of the device structure, which is a pointer to the
4644  * s2io_nic structure.
4645  * @data : variable that returns the result of each of the test conducted b
4646  * by the driver.
4647  * Description:
4648  * Read and write into all clock domains. The NIC has 3 clock domains,
4649  * see that registers in all the three regions are accessible.
4650  * Return value:
4651  * 0 on success.
4652  */
4653
4654 static int s2io_register_test(nic_t * sp, uint64_t * data)
4655 {
4656         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4657         u64 val64 = 0, exp_val;
4658         int fail = 0;
4659
4660         val64 = readq(&bar0->pif_rd_swapper_fb);
4661         if (val64 != 0x123456789abcdefULL) {
4662                 fail = 1;
4663                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4664         }
4665
4666         val64 = readq(&bar0->rmac_pause_cfg);
4667         if (val64 != 0xc000ffff00000000ULL) {
4668                 fail = 1;
4669                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4670         }
4671
4672         val64 = readq(&bar0->rx_queue_cfg);
4673         if (sp->device_type == XFRAME_II_DEVICE)
4674                 exp_val = 0x0404040404040404ULL;
4675         else
4676                 exp_val = 0x0808080808080808ULL;
4677         if (val64 != exp_val) {
4678                 fail = 1;
4679                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4680         }
4681
4682         val64 = readq(&bar0->xgxs_efifo_cfg);
4683         if (val64 != 0x000000001923141EULL) {
4684                 fail = 1;
4685                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4686         }
4687
4688         val64 = 0x5A5A5A5A5A5A5A5AULL;
4689         writeq(val64, &bar0->xmsi_data);
4690         val64 = readq(&bar0->xmsi_data);
4691         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4692                 fail = 1;
4693                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4694         }
4695
4696         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4697         writeq(val64, &bar0->xmsi_data);
4698         val64 = readq(&bar0->xmsi_data);
4699         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4700                 fail = 1;
4701                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4702         }
4703
4704         *data = fail;
4705         return fail;
4706 }
4707
4708 /**
4709  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4710  * @sp : private member of the device structure, which is a pointer to the
4711  * s2io_nic structure.
4712  * @data:variable that returns the result of each of the test conducted by
4713  * the driver.
4714  * Description:
4715  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4716  * register.
4717  * Return value:
4718  * 0 on success.
4719  */
4720
4721 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4722 {
4723         int fail = 0;
4724         u64 ret_data, org_4F0, org_7F0;
4725         u8 saved_4F0 = 0, saved_7F0 = 0;
4726         struct net_device *dev = sp->dev;
4727
4728         /* Test Write Error at offset 0 */
4729         /* Note that SPI interface allows write access to all areas
4730          * of EEPROM. Hence doing all negative testing only for Xframe I.
4731          */
4732         if (sp->device_type == XFRAME_I_DEVICE)
4733                 if (!write_eeprom(sp, 0, 0, 3))
4734                         fail = 1;
4735
4736         /* Save current values at offsets 0x4F0 and 0x7F0 */
4737         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4738                 saved_4F0 = 1;
4739         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4740                 saved_7F0 = 1;
4741
4742         /* Test Write at offset 4f0 */
4743         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4744                 fail = 1;
4745         if (read_eeprom(sp, 0x4F0, &ret_data))
4746                 fail = 1;
4747
4748         if (ret_data != 0x012345) {
4749                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4750                 fail = 1;
4751         }
4752
4753         /* Reset the EEPROM data go FFFF */
4754         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4755
4756         /* Test Write Request Error at offset 0x7c */
4757         if (sp->device_type == XFRAME_I_DEVICE)
4758                 if (!write_eeprom(sp, 0x07C, 0, 3))
4759                         fail = 1;
4760
4761         /* Test Write Request at offset 0x7f0 */
4762         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4763                 fail = 1;
4764         if (read_eeprom(sp, 0x7F0, &ret_data))
4765                 fail = 1;
4766
4767         if (ret_data != 0x012345) {
4768                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data);
4769                 fail = 1;
4770         }
4771
4772         /* Reset the EEPROM data go FFFF */
4773         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4774
4775         if (sp->device_type == XFRAME_I_DEVICE) {
4776                 /* Test Write Error at offset 0x80 */
4777                 if (!write_eeprom(sp, 0x080, 0, 3))
4778                         fail = 1;
4779
4780                 /* Test Write Error at offset 0xfc */
4781                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4782                         fail = 1;
4783
4784                 /* Test Write Error at offset 0x100 */
4785                 if (!write_eeprom(sp, 0x100, 0, 3))
4786                         fail = 1;
4787
4788                 /* Test Write Error at offset 4ec */
4789                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4790                         fail = 1;
4791         }
4792
4793         /* Restore values at offsets 0x4F0 and 0x7F0 */
4794         if (saved_4F0)
4795                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4796         if (saved_7F0)
4797                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4798
4799         *data = fail;
4800         return fail;
4801 }
4802
4803 /**
4804  * s2io_bist_test - invokes the MemBist test of the card .
4805  * @sp : private member of the device structure, which is a pointer to the
4806  * s2io_nic structure.
4807  * @data:variable that returns the result of each of the test conducted by
4808  * the driver.
4809  * Description:
4810  * This invokes the MemBist test of the card. We give around
4811  * 2 secs time for the Test to complete. If it's still not complete
4812  * within this peiod, we consider that the test failed.
4813  * Return value:
4814  * 0 on success and -1 on failure.
4815  */
4816
4817 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4818 {
4819         u8 bist = 0;
4820         int cnt = 0, ret = -1;
4821
4822         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4823         bist |= PCI_BIST_START;
4824         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4825
4826         while (cnt < 20) {
4827                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4828                 if (!(bist & PCI_BIST_START)) {
4829                         *data = (bist & PCI_BIST_CODE_MASK);
4830                         ret = 0;
4831                         break;
4832                 }
4833                 msleep(100);
4834                 cnt++;
4835         }
4836
4837         return ret;
4838 }
4839
4840 /**
4841  * s2io-link_test - verifies the link state of the nic
4842  * @sp ; private member of the device structure, which is a pointer to the
4843  * s2io_nic structure.
4844  * @data: variable that returns the result of each of the test conducted by
4845  * the driver.
4846  * Description:
4847  * The function verifies the link state of the NIC and updates the input
4848  * argument 'data' appropriately.
4849  * Return value:
4850  * 0 on success.
4851  */
4852
4853 static int s2io_link_test(nic_t * sp, uint64_t * data)
4854 {
4855         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4856         u64 val64;
4857
4858         val64 = readq(&bar0->adapter_status);
4859         if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
4860                 *data = 1;
4861
4862         return 0;
4863 }
4864
4865 /**
4866  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4867  * @sp - private member of the device structure, which is a pointer to the
4868  * s2io_nic structure.
4869  * @data - variable that returns the result of each of the test
4870  * conducted by the driver.
4871  * Description:
4872  *  This is one of the offline test that tests the read and write
4873  *  access to the RldRam chip on the NIC.
4874  * Return value:
4875  *  0 on success.
4876  */
4877
4878 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4879 {
4880         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4881         u64 val64;
4882         int cnt, iteration = 0, test_fail = 0;
4883
4884         val64 = readq(&bar0->adapter_control);
4885         val64 &= ~ADAPTER_ECC_EN;
4886         writeq(val64, &bar0->adapter_control);
4887
4888         val64 = readq(&bar0->mc_rldram_test_ctrl);
4889         val64 |= MC_RLDRAM_TEST_MODE;
4890         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4891
4892         val64 = readq(&bar0->mc_rldram_mrs);
4893         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4894         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4895
4896         val64 |= MC_RLDRAM_MRS_ENABLE;
4897         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4898
4899         while (iteration < 2) {
4900                 val64 = 0x55555555aaaa0000ULL;
4901                 if (iteration == 1) {
4902                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4903                 }
4904                 writeq(val64, &bar0->mc_rldram_test_d0);
4905
4906                 val64 = 0xaaaa5a5555550000ULL;
4907                 if (iteration == 1) {
4908                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4909                 }
4910                 writeq(val64, &bar0->mc_rldram_test_d1);
4911
4912                 val64 = 0x55aaaaaaaa5a0000ULL;
4913                 if (iteration == 1) {
4914                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4915                 }
4916                 writeq(val64, &bar0->mc_rldram_test_d2);
4917
4918                 val64 = (u64) (0x0000003ffffe0100ULL);
4919                 writeq(val64, &bar0->mc_rldram_test_add);
4920
4921                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4922                         MC_RLDRAM_TEST_GO;
4923                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4924
4925                 for (cnt = 0; cnt < 5; cnt++) {
4926                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4927                         if (val64 & MC_RLDRAM_TEST_DONE)
4928                                 break;
4929                         msleep(200);
4930                 }
4931
4932                 if (cnt == 5)
4933                         break;
4934
4935                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4936                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4937
4938                 for (cnt = 0; cnt < 5; cnt++) {
4939                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4940                         if (val64 & MC_RLDRAM_TEST_DONE)
4941                                 break;
4942                         msleep(500);
4943                 }
4944
4945                 if (cnt == 5)
4946                         break;
4947
4948                 val64 = readq(&bar0->mc_rldram_test_ctrl);
4949                 if (!(val64 & MC_RLDRAM_TEST_PASS))
4950                         test_fail = 1;
4951
4952                 iteration++;
4953         }
4954
4955         *data = test_fail;
4956
4957         /* Bring the adapter out of test mode */
4958         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
4959
4960         return test_fail;
4961 }
4962
4963 /**
4964  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
4965  *  @sp : private member of the device structure, which is a pointer to the
4966  *  s2io_nic structure.
4967  *  @ethtest : pointer to a ethtool command specific structure that will be
4968  *  returned to the user.
4969  *  @data : variable that returns the result of each of the test
4970  * conducted by the driver.
4971  * Description:
4972  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
4973  *  the health of the card.
4974  * Return value:
4975  *  void
4976  */
4977
4978 static void s2io_ethtool_test(struct net_device *dev,
4979                               struct ethtool_test *ethtest,
4980                               uint64_t * data)
4981 {
4982         nic_t *sp = dev->priv;
4983         int orig_state = netif_running(sp->dev);
4984
4985         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
4986                 /* Offline Tests. */
4987                 if (orig_state)
4988                         s2io_close(sp->dev);
4989
4990                 if (s2io_register_test(sp, &data[0]))
4991                         ethtest->flags |= ETH_TEST_FL_FAILED;
4992
4993                 s2io_reset(sp);
4994
4995                 if (s2io_rldram_test(sp, &data[3]))
4996                         ethtest->flags |= ETH_TEST_FL_FAILED;
4997
4998                 s2io_reset(sp);
4999
5000                 if (s2io_eeprom_test(sp, &data[1]))
5001                         ethtest->flags |= ETH_TEST_FL_FAILED;
5002
5003                 if (s2io_bist_test(sp, &data[4]))
5004                         ethtest->flags |= ETH_TEST_FL_FAILED;
5005
5006                 if (orig_state)
5007                         s2io_open(sp->dev);
5008
5009                 data[2] = 0;
5010         } else {
5011                 /* Online Tests. */
5012                 if (!orig_state) {
5013                         DBG_PRINT(ERR_DBG,
5014                                   "%s: is not up, cannot run test\n",
5015                                   dev->name);
5016                         data[0] = -1;
5017                         data[1] = -1;
5018                         data[2] = -1;
5019                         data[3] = -1;
5020                         data[4] = -1;
5021                 }
5022
5023                 if (s2io_link_test(sp, &data[2]))
5024                         ethtest->flags |= ETH_TEST_FL_FAILED;
5025
5026                 data[0] = 0;
5027                 data[1] = 0;
5028                 data[3] = 0;
5029                 data[4] = 0;
5030         }
5031 }
5032
5033 static void s2io_get_ethtool_stats(struct net_device *dev,
5034                                    struct ethtool_stats *estats,
5035                                    u64 * tmp_stats)
5036 {
5037         int i = 0;
5038         nic_t *sp = dev->priv;
5039         StatInfo_t *stat_info = sp->mac_control.stats_info;
5040
5041         s2io_updt_stats(sp);
5042         tmp_stats[i++] =
5043                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5044                 le32_to_cpu(stat_info->tmac_frms);
5045         tmp_stats[i++] =
5046                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5047                 le32_to_cpu(stat_info->tmac_data_octets);
5048         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5049         tmp_stats[i++] =
5050                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5051                 le32_to_cpu(stat_info->tmac_mcst_frms);
5052         tmp_stats[i++] =
5053                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5054                 le32_to_cpu(stat_info->tmac_bcst_frms);
5055         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5056         tmp_stats[i++] =
5057                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5058                 le32_to_cpu(stat_info->tmac_any_err_frms);
5059         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5060         tmp_stats[i++] =
5061                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5062                 le32_to_cpu(stat_info->tmac_vld_ip);
5063         tmp_stats[i++] =
5064                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5065                 le32_to_cpu(stat_info->tmac_drop_ip);
5066         tmp_stats[i++] =
5067                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5068                 le32_to_cpu(stat_info->tmac_icmp);
5069         tmp_stats[i++] =
5070                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5071                 le32_to_cpu(stat_info->tmac_rst_tcp);
5072         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5073         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5074                 le32_to_cpu(stat_info->tmac_udp);
5075         tmp_stats[i++] =
5076                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5077                 le32_to_cpu(stat_info->rmac_vld_frms);
5078         tmp_stats[i++] =
5079                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5080                 le32_to_cpu(stat_info->rmac_data_octets);
5081         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5082         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5083         tmp_stats[i++] =
5084                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5085                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5086         tmp_stats[i++] =
5087                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5088                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5089         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5090         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5091         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5092         tmp_stats[i++] =
5093                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5094                 le32_to_cpu(stat_info->rmac_discarded_frms);
5095         tmp_stats[i++] =
5096                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5097                 le32_to_cpu(stat_info->rmac_usized_frms);
5098         tmp_stats[i++] =
5099                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5100                 le32_to_cpu(stat_info->rmac_osized_frms);
5101         tmp_stats[i++] =
5102                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5103                 le32_to_cpu(stat_info->rmac_frag_frms);
5104         tmp_stats[i++] =
5105                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5106                 le32_to_cpu(stat_info->rmac_jabber_frms);
5107         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5108                 le32_to_cpu(stat_info->rmac_ip);
5109         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5110         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5111         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5112                 le32_to_cpu(stat_info->rmac_drop_ip);
5113         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5114                 le32_to_cpu(stat_info->rmac_icmp);
5115         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5116         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5117                 le32_to_cpu(stat_info->rmac_udp);
5118         tmp_stats[i++] =
5119                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5120                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5121         tmp_stats[i++] =
5122                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5123                 le32_to_cpu(stat_info->rmac_pause_cnt);
5124         tmp_stats[i++] =
5125                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5126                 le32_to_cpu(stat_info->rmac_accepted_ip);
5127         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5128         tmp_stats[i++] = 0;
5129         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5130         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5131 }
5132
5133 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5134 {
5135         return (XENA_REG_SPACE);
5136 }
5137
5138
5139 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5140 {
5141         nic_t *sp = dev->priv;
5142
5143         return (sp->rx_csum);
5144 }
5145
5146 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5147 {
5148         nic_t *sp = dev->priv;
5149
5150         if (data)
5151                 sp->rx_csum = 1;
5152         else
5153                 sp->rx_csum = 0;
5154
5155         return 0;
5156 }
5157
5158 static int s2io_get_eeprom_len(struct net_device *dev)
5159 {
5160         return (XENA_EEPROM_SPACE);
5161 }
5162
5163 static int s2io_ethtool_self_test_count(struct net_device *dev)
5164 {
5165         return (S2IO_TEST_LEN);
5166 }
5167
5168 static void s2io_ethtool_get_strings(struct net_device *dev,
5169                                      u32 stringset, u8 * data)
5170 {
5171         switch (stringset) {
5172         case ETH_SS_TEST:
5173                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5174                 break;
5175         case ETH_SS_STATS:
5176                 memcpy(data, &ethtool_stats_keys,
5177                        sizeof(ethtool_stats_keys));
5178         }
5179 }
5180 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5181 {
5182         return (S2IO_STAT_LEN);
5183 }
5184
5185 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5186 {
5187         if (data)
5188                 dev->features |= NETIF_F_IP_CSUM;
5189         else
5190                 dev->features &= ~NETIF_F_IP_CSUM;
5191
5192         return 0;
5193 }
5194
5195
5196 static struct ethtool_ops netdev_ethtool_ops = {
5197         .get_settings = s2io_ethtool_gset,
5198         .set_settings = s2io_ethtool_sset,
5199         .get_drvinfo = s2io_ethtool_gdrvinfo,
5200         .get_regs_len = s2io_ethtool_get_regs_len,
5201         .get_regs = s2io_ethtool_gregs,
5202         .get_link = ethtool_op_get_link,
5203         .get_eeprom_len = s2io_get_eeprom_len,
5204         .get_eeprom = s2io_ethtool_geeprom,
5205         .set_eeprom = s2io_ethtool_seeprom,
5206         .get_pauseparam = s2io_ethtool_getpause_data,
5207         .set_pauseparam = s2io_ethtool_setpause_data,
5208         .get_rx_csum = s2io_ethtool_get_rx_csum,
5209         .set_rx_csum = s2io_ethtool_set_rx_csum,
5210         .get_tx_csum = ethtool_op_get_tx_csum,
5211         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5212         .get_sg = ethtool_op_get_sg,
5213         .set_sg = ethtool_op_set_sg,
5214 #ifdef NETIF_F_TSO
5215         .get_tso = ethtool_op_get_tso,
5216         .set_tso = ethtool_op_set_tso,
5217 #endif
5218         .get_ufo = ethtool_op_get_ufo,
5219         .set_ufo = ethtool_op_set_ufo,
5220         .self_test_count = s2io_ethtool_self_test_count,
5221         .self_test = s2io_ethtool_test,
5222         .get_strings = s2io_ethtool_get_strings,
5223         .phys_id = s2io_ethtool_idnic,
5224         .get_stats_count = s2io_ethtool_get_stats_count,
5225         .get_ethtool_stats = s2io_get_ethtool_stats
5226 };
5227
5228 /**
5229  *  s2io_ioctl - Entry point for the Ioctl
5230  *  @dev :  Device pointer.
5231  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5232  *  a proprietary structure used to pass information to the driver.
5233  *  @cmd :  This is used to distinguish between the different commands that
5234  *  can be passed to the IOCTL functions.
5235  *  Description:
5236  *  Currently there are no special functionality supported in IOCTL, hence
5237  *  function always return EOPNOTSUPPORTED
5238  */
5239
5240 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5241 {
5242         return -EOPNOTSUPP;
5243 }
5244
5245 /**
5246  *  s2io_change_mtu - entry point to change MTU size for the device.
5247  *   @dev : device pointer.
5248  *   @new_mtu : the new MTU size for the device.
5249  *   Description: A driver entry point to change MTU size for the device.
5250  *   Before changing the MTU the device must be stopped.
5251  *  Return value:
5252  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5253  *   file on failure.
5254  */
5255
5256 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5257 {
5258         nic_t *sp = dev->priv;
5259
5260         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5261                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5262                           dev->name);
5263                 return -EPERM;
5264         }
5265
5266         dev->mtu = new_mtu;
5267         if (netif_running(dev)) {
5268                 s2io_card_down(sp);
5269                 netif_stop_queue(dev);
5270                 if (s2io_card_up(sp)) {
5271                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5272                                   __FUNCTION__);
5273                 }
5274                 if (netif_queue_stopped(dev))
5275                         netif_wake_queue(dev);
5276         } else { /* Device is down */
5277                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5278                 u64 val64 = new_mtu;
5279
5280                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5281         }
5282
5283         return 0;
5284 }
5285
5286 /**
5287  *  s2io_tasklet - Bottom half of the ISR.
5288  *  @dev_adr : address of the device structure in dma_addr_t format.
5289  *  Description:
5290  *  This is the tasklet or the bottom half of the ISR. This is
5291  *  an extension of the ISR which is scheduled by the scheduler to be run
5292  *  when the load on the CPU is low. All low priority tasks of the ISR can
5293  *  be pushed into the tasklet. For now the tasklet is used only to
5294  *  replenish the Rx buffers in the Rx buffer descriptors.
5295  *  Return value:
5296  *  void.
5297  */
5298
5299 static void s2io_tasklet(unsigned long dev_addr)
5300 {
5301         struct net_device *dev = (struct net_device *) dev_addr;
5302         nic_t *sp = dev->priv;
5303         int i, ret;
5304         mac_info_t *mac_control;
5305         struct config_param *config;
5306
5307         mac_control = &sp->mac_control;
5308         config = &sp->config;
5309
5310         if (!TASKLET_IN_USE) {
5311                 for (i = 0; i < config->rx_ring_num; i++) {
5312                         ret = fill_rx_buffers(sp, i);
5313                         if (ret == -ENOMEM) {
5314                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5315                                           dev->name);
5316                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5317                                 break;
5318                         } else if (ret == -EFILL) {
5319                                 DBG_PRINT(ERR_DBG,
5320                                           "%s: Rx Ring %d is full\n",
5321                                           dev->name, i);
5322                                 break;
5323                         }
5324                 }
5325                 clear_bit(0, (&sp->tasklet_status));
5326         }
5327 }
5328
5329 /**
5330  * s2io_set_link - Set the LInk status
5331  * @data: long pointer to device private structue
5332  * Description: Sets the link status for the adapter
5333  */
5334
5335 static void s2io_set_link(unsigned long data)
5336 {
5337         nic_t *nic = (nic_t *) data;
5338         struct net_device *dev = nic->dev;
5339         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5340         register u64 val64;
5341         u16 subid;
5342
5343         if (test_and_set_bit(0, &(nic->link_state))) {
5344                 /* The card is being reset, no point doing anything */
5345                 return;
5346         }
5347
5348         subid = nic->pdev->subsystem_device;
5349         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5350                 /*
5351                  * Allow a small delay for the NICs self initiated
5352                  * cleanup to complete.
5353                  */
5354                 msleep(100);
5355         }
5356
5357         val64 = readq(&bar0->adapter_status);
5358         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5359                 if (LINK_IS_UP(val64)) {
5360                         val64 = readq(&bar0->adapter_control);
5361                         val64 |= ADAPTER_CNTL_EN;
5362                         writeq(val64, &bar0->adapter_control);
5363                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5364                                                              subid)) {
5365                                 val64 = readq(&bar0->gpio_control);
5366                                 val64 |= GPIO_CTRL_GPIO_0;
5367                                 writeq(val64, &bar0->gpio_control);
5368                                 val64 = readq(&bar0->gpio_control);
5369                         } else {
5370                                 val64 |= ADAPTER_LED_ON;
5371                                 writeq(val64, &bar0->adapter_control);
5372                         }
5373                         if (s2io_link_fault_indication(nic) ==
5374                                                 MAC_RMAC_ERR_TIMER) {
5375                                 val64 = readq(&bar0->adapter_status);
5376                                 if (!LINK_IS_UP(val64)) {
5377                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5378                                         DBG_PRINT(ERR_DBG, " Link down");
5379                                         DBG_PRINT(ERR_DBG, "after ");
5380                                         DBG_PRINT(ERR_DBG, "enabling ");
5381                                         DBG_PRINT(ERR_DBG, "device \n");
5382                                 }
5383                         }
5384                         if (nic->device_enabled_once == FALSE) {
5385                                 nic->device_enabled_once = TRUE;
5386                         }
5387                         s2io_link(nic, LINK_UP);
5388                 } else {
5389                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5390                                                               subid)) {
5391                                 val64 = readq(&bar0->gpio_control);
5392                                 val64 &= ~GPIO_CTRL_GPIO_0;
5393                                 writeq(val64, &bar0->gpio_control);
5394                                 val64 = readq(&bar0->gpio_control);
5395                         }
5396                         s2io_link(nic, LINK_DOWN);
5397                 }
5398         } else {                /* NIC is not Quiescent. */
5399                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5400                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5401                 netif_stop_queue(dev);
5402         }
5403         clear_bit(0, &(nic->link_state));
5404 }
5405
5406 static void s2io_card_down(nic_t * sp)
5407 {
5408         int cnt = 0;
5409         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5410         unsigned long flags;
5411         register u64 val64 = 0;
5412
5413         del_timer_sync(&sp->alarm_timer);
5414         /* If s2io_set_link task is executing, wait till it completes. */
5415         while (test_and_set_bit(0, &(sp->link_state))) {
5416                 msleep(50);
5417         }
5418         atomic_set(&sp->card_state, CARD_DOWN);
5419
5420         /* disable Tx and Rx traffic on the NIC */
5421         stop_nic(sp);
5422
5423         /* Kill tasklet. */
5424         tasklet_kill(&sp->task);
5425
5426         /* Check if the device is Quiescent and then Reset the NIC */
5427         do {
5428                 val64 = readq(&bar0->adapter_status);
5429                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5430                         break;
5431                 }
5432
5433                 msleep(50);
5434                 cnt++;
5435                 if (cnt == 10) {
5436                         DBG_PRINT(ERR_DBG,
5437                                   "s2io_close:Device not Quiescent ");
5438                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5439                                   (unsigned long long) val64);
5440                         break;
5441                 }
5442         } while (1);
5443         s2io_reset(sp);
5444
5445         /* Waiting till all Interrupt handlers are complete */
5446         cnt = 0;
5447         do {
5448                 msleep(10);
5449                 if (!atomic_read(&sp->isr_cnt))
5450                         break;
5451                 cnt++;
5452         } while(cnt < 5);
5453
5454         spin_lock_irqsave(&sp->tx_lock, flags);
5455         /* Free all Tx buffers */
5456         free_tx_buffers(sp);
5457         spin_unlock_irqrestore(&sp->tx_lock, flags);
5458
5459         /* Free all Rx buffers */
5460         spin_lock_irqsave(&sp->rx_lock, flags);
5461         free_rx_buffers(sp);
5462         spin_unlock_irqrestore(&sp->rx_lock, flags);
5463
5464         clear_bit(0, &(sp->link_state));
5465 }
5466
5467 static int s2io_card_up(nic_t * sp)
5468 {
5469         int i, ret = 0;
5470         mac_info_t *mac_control;
5471         struct config_param *config;
5472         struct net_device *dev = (struct net_device *) sp->dev;
5473
5474         /* Initialize the H/W I/O registers */
5475         if (init_nic(sp) != 0) {
5476                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5477                           dev->name);
5478                 return -ENODEV;
5479         }
5480
5481         if (sp->intr_type == MSI)
5482                 ret = s2io_enable_msi(sp);
5483         else if (sp->intr_type == MSI_X)
5484                 ret = s2io_enable_msi_x(sp);
5485         if (ret) {
5486                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5487                 sp->intr_type = INTA;
5488         }
5489
5490         /*
5491          * Initializing the Rx buffers. For now we are considering only 1
5492          * Rx ring and initializing buffers into 30 Rx blocks
5493          */
5494         mac_control = &sp->mac_control;
5495         config = &sp->config;
5496
5497         for (i = 0; i < config->rx_ring_num; i++) {
5498                 if ((ret = fill_rx_buffers(sp, i))) {
5499                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5500                                   dev->name);
5501                         s2io_reset(sp);
5502                         free_rx_buffers(sp);
5503                         return -ENOMEM;
5504                 }
5505                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5506                           atomic_read(&sp->rx_bufs_left[i]));
5507         }
5508
5509         /* Setting its receive mode */
5510         s2io_set_multicast(dev);
5511
5512         /* Enable tasklet for the device */
5513         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5514
5515         /* Enable Rx Traffic and interrupts on the NIC */
5516         if (start_nic(sp)) {
5517                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5518                 tasklet_kill(&sp->task);
5519                 s2io_reset(sp);
5520                 free_irq(dev->irq, dev);
5521                 free_rx_buffers(sp);
5522                 return -ENODEV;
5523         }
5524
5525         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5526
5527         atomic_set(&sp->card_state, CARD_UP);
5528         return 0;
5529 }
5530
5531 /**
5532  * s2io_restart_nic - Resets the NIC.
5533  * @data : long pointer to the device private structure
5534  * Description:
5535  * This function is scheduled to be run by the s2io_tx_watchdog
5536  * function after 0.5 secs to reset the NIC. The idea is to reduce
5537  * the run time of the watch dog routine which is run holding a
5538  * spin lock.
5539  */
5540
5541 static void s2io_restart_nic(unsigned long data)
5542 {
5543         struct net_device *dev = (struct net_device *) data;
5544         nic_t *sp = dev->priv;
5545
5546         s2io_card_down(sp);
5547         if (s2io_card_up(sp)) {
5548                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5549                           dev->name);
5550         }
5551         netif_wake_queue(dev);
5552         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5553                   dev->name);
5554
5555 }
5556
5557 /**
5558  *  s2io_tx_watchdog - Watchdog for transmit side.
5559  *  @dev : Pointer to net device structure
5560  *  Description:
5561  *  This function is triggered if the Tx Queue is stopped
5562  *  for a pre-defined amount of time when the Interface is still up.
5563  *  If the Interface is jammed in such a situation, the hardware is
5564  *  reset (by s2io_close) and restarted again (by s2io_open) to
5565  *  overcome any problem that might have been caused in the hardware.
5566  *  Return value:
5567  *  void
5568  */
5569
5570 static void s2io_tx_watchdog(struct net_device *dev)
5571 {
5572         nic_t *sp = dev->priv;
5573
5574         if (netif_carrier_ok(dev)) {
5575                 schedule_work(&sp->rst_timer_task);
5576         }
5577 }
5578
5579 /**
5580  *   rx_osm_handler - To perform some OS related operations on SKB.
5581  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5582  *   @skb : the socket buffer pointer.
5583  *   @len : length of the packet
5584  *   @cksum : FCS checksum of the frame.
5585  *   @ring_no : the ring from which this RxD was extracted.
5586  *   Description:
5587  *   This function is called by the Tx interrupt serivce routine to perform
5588  *   some OS related operations on the SKB before passing it to the upper
5589  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5590  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5591  *   to the upper layer. If the checksum is wrong, it increments the Rx
5592  *   packet error count, frees the SKB and returns error.
5593  *   Return value:
5594  *   SUCCESS on success and -1 on failure.
5595  */
5596 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5597 {
5598         nic_t *sp = ring_data->nic;
5599         struct net_device *dev = (struct net_device *) sp->dev;
5600         struct sk_buff *skb = (struct sk_buff *)
5601                 ((unsigned long) rxdp->Host_Control);
5602         int ring_no = ring_data->ring_no;
5603         u16 l3_csum, l4_csum;
5604
5605         skb->dev = dev;
5606         if (rxdp->Control_1 & RXD_T_CODE) {
5607                 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5608                 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5609                           dev->name, err);
5610                 dev_kfree_skb(skb);
5611                 sp->stats.rx_crc_errors++;
5612                 atomic_dec(&sp->rx_bufs_left[ring_no]);
5613                 rxdp->Host_Control = 0;
5614                 return 0;
5615         }
5616
5617         /* Updating statistics */
5618         rxdp->Host_Control = 0;
5619         sp->rx_pkt_count++;
5620         sp->stats.rx_packets++;
5621         if (sp->rxd_mode == RXD_MODE_1) {
5622                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
5623
5624                 sp->stats.rx_bytes += len;
5625                 skb_put(skb, len);
5626
5627         } else if (sp->rxd_mode >= RXD_MODE_3A) {
5628                 int get_block = ring_data->rx_curr_get_info.block_index;
5629                 int get_off = ring_data->rx_curr_get_info.offset;
5630                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
5631                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
5632                 unsigned char *buff = skb_push(skb, buf0_len);
5633
5634                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5635                 sp->stats.rx_bytes += buf0_len + buf2_len;
5636                 memcpy(buff, ba->ba_0, buf0_len);
5637
5638                 if (sp->rxd_mode == RXD_MODE_3A) {
5639                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
5640
5641                         skb_put(skb, buf1_len);
5642                         skb->len += buf2_len;
5643                         skb->data_len += buf2_len;
5644                         skb->truesize += buf2_len;
5645                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
5646                         sp->stats.rx_bytes += buf1_len;
5647
5648                 } else
5649                         skb_put(skb, buf2_len);
5650         }
5651
5652         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
5653             (sp->rx_csum)) {
5654                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5655                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5656                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5657                         /*
5658                          * NIC verifies if the Checksum of the received
5659                          * frame is Ok or not and accordingly returns
5660                          * a flag in the RxD.
5661                          */
5662                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5663                 } else {
5664                         /*
5665                          * Packet with erroneous checksum, let the
5666                          * upper layers deal with it.
5667                          */
5668                         skb->ip_summed = CHECKSUM_NONE;
5669                 }
5670         } else {
5671                 skb->ip_summed = CHECKSUM_NONE;
5672         }
5673
5674         skb->protocol = eth_type_trans(skb, dev);
5675 #ifdef CONFIG_S2IO_NAPI
5676         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5677                 /* Queueing the vlan frame to the upper layer */
5678                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5679                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5680         } else {
5681                 netif_receive_skb(skb);
5682         }
5683 #else
5684         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5685                 /* Queueing the vlan frame to the upper layer */
5686                 vlan_hwaccel_rx(skb, sp->vlgrp,
5687                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5688         } else {
5689                 netif_rx(skb);
5690         }
5691 #endif
5692         dev->last_rx = jiffies;
5693         atomic_dec(&sp->rx_bufs_left[ring_no]);
5694         return SUCCESS;
5695 }
5696
5697 /**
5698  *  s2io_link - stops/starts the Tx queue.
5699  *  @sp : private member of the device structure, which is a pointer to the
5700  *  s2io_nic structure.
5701  *  @link : inidicates whether link is UP/DOWN.
5702  *  Description:
5703  *  This function stops/starts the Tx queue depending on whether the link
5704  *  status of the NIC is is down or up. This is called by the Alarm
5705  *  interrupt handler whenever a link change interrupt comes up.
5706  *  Return value:
5707  *  void.
5708  */
5709
5710 void s2io_link(nic_t * sp, int link)
5711 {
5712         struct net_device *dev = (struct net_device *) sp->dev;
5713
5714         if (link != sp->last_link_state) {
5715                 if (link == LINK_DOWN) {
5716                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
5717                         netif_carrier_off(dev);
5718                 } else {
5719                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
5720                         netif_carrier_on(dev);
5721                 }
5722         }
5723         sp->last_link_state = link;
5724 }
5725
5726 /**
5727  *  get_xena_rev_id - to identify revision ID of xena.
5728  *  @pdev : PCI Dev structure
5729  *  Description:
5730  *  Function to identify the Revision ID of xena.
5731  *  Return value:
5732  *  returns the revision ID of the device.
5733  */
5734
5735 int get_xena_rev_id(struct pci_dev *pdev)
5736 {
5737         u8 id = 0;
5738         int ret;
5739         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5740         return id;
5741 }
5742
5743 /**
5744  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5745  *  @sp : private member of the device structure, which is a pointer to the
5746  *  s2io_nic structure.
5747  *  Description:
5748  *  This function initializes a few of the PCI and PCI-X configuration registers
5749  *  with recommended values.
5750  *  Return value:
5751  *  void
5752  */
5753
5754 static void s2io_init_pci(nic_t * sp)
5755 {
5756         u16 pci_cmd = 0, pcix_cmd = 0;
5757
5758         /* Enable Data Parity Error Recovery in PCI-X command register. */
5759         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5760                              &(pcix_cmd));
5761         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5762                               (pcix_cmd | 1));
5763         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5764                              &(pcix_cmd));
5765
5766         /* Set the PErr Response bit in PCI command register. */
5767         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5768         pci_write_config_word(sp->pdev, PCI_COMMAND,
5769                               (pci_cmd | PCI_COMMAND_PARITY));
5770         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5771
5772         /* Forcibly disabling relaxed ordering capability of the card. */
5773         pcix_cmd &= 0xfffd;
5774         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5775                               pcix_cmd);
5776         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5777                              &(pcix_cmd));
5778 }
5779
5780 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5781 MODULE_LICENSE("GPL");
5782 MODULE_VERSION(DRV_VERSION);
5783
5784 module_param(tx_fifo_num, int, 0);
5785 module_param(rx_ring_num, int, 0);
5786 module_param(rx_ring_mode, int, 0);
5787 module_param_array(tx_fifo_len, uint, NULL, 0);
5788 module_param_array(rx_ring_sz, uint, NULL, 0);
5789 module_param_array(rts_frm_len, uint, NULL, 0);
5790 module_param(use_continuous_tx_intrs, int, 1);
5791 module_param(rmac_pause_time, int, 0);
5792 module_param(mc_pause_threshold_q0q3, int, 0);
5793 module_param(mc_pause_threshold_q4q7, int, 0);
5794 module_param(shared_splits, int, 0);
5795 module_param(tmac_util_period, int, 0);
5796 module_param(rmac_util_period, int, 0);
5797 module_param(bimodal, bool, 0);
5798 module_param(l3l4hdr_size, int , 0);
5799 #ifndef CONFIG_S2IO_NAPI
5800 module_param(indicate_max_pkts, int, 0);
5801 #endif
5802 module_param(rxsync_frequency, int, 0);
5803 module_param(intr_type, int, 0);
5804
5805 /**
5806  *  s2io_init_nic - Initialization of the adapter .
5807  *  @pdev : structure containing the PCI related information of the device.
5808  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
5809  *  Description:
5810  *  The function initializes an adapter identified by the pci_dec structure.
5811  *  All OS related initialization including memory and device structure and
5812  *  initlaization of the device private variable is done. Also the swapper
5813  *  control register is initialized to enable read and write into the I/O
5814  *  registers of the device.
5815  *  Return value:
5816  *  returns 0 on success and negative on failure.
5817  */
5818
5819 static int __devinit
5820 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
5821 {
5822         nic_t *sp;
5823         struct net_device *dev;
5824         int i, j, ret;
5825         int dma_flag = FALSE;
5826         u32 mac_up, mac_down;
5827         u64 val64 = 0, tmp64 = 0;
5828         XENA_dev_config_t __iomem *bar0 = NULL;
5829         u16 subid;
5830         mac_info_t *mac_control;
5831         struct config_param *config;
5832         int mode;
5833         u8 dev_intr_type = intr_type;
5834
5835 #ifdef CONFIG_S2IO_NAPI
5836         if (dev_intr_type != INTA) {
5837                 DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
5838 is enabled. Defaulting to INTA\n");
5839                 dev_intr_type = INTA;
5840         }
5841         else
5842                 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
5843 #endif
5844
5845         if ((ret = pci_enable_device(pdev))) {
5846                 DBG_PRINT(ERR_DBG,
5847                           "s2io_init_nic: pci_enable_device failed\n");
5848                 return ret;
5849         }
5850
5851         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5852                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
5853                 dma_flag = TRUE;
5854                 if (pci_set_consistent_dma_mask
5855                     (pdev, DMA_64BIT_MASK)) {
5856                         DBG_PRINT(ERR_DBG,
5857                                   "Unable to obtain 64bit DMA for \
5858                                         consistent allocations\n");
5859                         pci_disable_device(pdev);
5860                         return -ENOMEM;
5861                 }
5862         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
5863                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
5864         } else {
5865                 pci_disable_device(pdev);
5866                 return -ENOMEM;
5867         }
5868
5869         if ((dev_intr_type == MSI_X) &&
5870                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
5871                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
5872                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
5873 Defaulting to INTA\n");
5874                 dev_intr_type = INTA;
5875         }
5876         if (dev_intr_type != MSI_X) {
5877                 if (pci_request_regions(pdev, s2io_driver_name)) {
5878                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
5879                             pci_disable_device(pdev);
5880                         return -ENODEV;
5881                 }
5882         }
5883         else {
5884                 if (!(request_mem_region(pci_resource_start(pdev, 0),
5885                          pci_resource_len(pdev, 0), s2io_driver_name))) {
5886                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
5887                         pci_disable_device(pdev);
5888                         return -ENODEV;
5889                 }
5890                 if (!(request_mem_region(pci_resource_start(pdev, 2),
5891                          pci_resource_len(pdev, 2), s2io_driver_name))) {
5892                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
5893                         release_mem_region(pci_resource_start(pdev, 0),
5894                                    pci_resource_len(pdev, 0));
5895                         pci_disable_device(pdev);
5896                         return -ENODEV;
5897                 }
5898         }
5899
5900         dev = alloc_etherdev(sizeof(nic_t));
5901         if (dev == NULL) {
5902                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
5903                 pci_disable_device(pdev);
5904                 pci_release_regions(pdev);
5905                 return -ENODEV;
5906         }
5907
5908         pci_set_master(pdev);
5909         pci_set_drvdata(pdev, dev);
5910         SET_MODULE_OWNER(dev);
5911         SET_NETDEV_DEV(dev, &pdev->dev);
5912
5913         /*  Private member variable initialized to s2io NIC structure */
5914         sp = dev->priv;
5915         memset(sp, 0, sizeof(nic_t));
5916         sp->dev = dev;
5917         sp->pdev = pdev;
5918         sp->high_dma_flag = dma_flag;
5919         sp->device_enabled_once = FALSE;
5920         if (rx_ring_mode == 1)
5921                 sp->rxd_mode = RXD_MODE_1;
5922         if (rx_ring_mode == 2)
5923                 sp->rxd_mode = RXD_MODE_3B;
5924         if (rx_ring_mode == 3)
5925                 sp->rxd_mode = RXD_MODE_3A;
5926
5927         sp->intr_type = dev_intr_type;
5928
5929         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
5930                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
5931                 sp->device_type = XFRAME_II_DEVICE;
5932         else
5933                 sp->device_type = XFRAME_I_DEVICE;
5934
5935
5936         /* Initialize some PCI/PCI-X fields of the NIC. */
5937         s2io_init_pci(sp);
5938
5939         /*
5940          * Setting the device configuration parameters.
5941          * Most of these parameters can be specified by the user during
5942          * module insertion as they are module loadable parameters. If
5943          * these parameters are not not specified during load time, they
5944          * are initialized with default values.
5945          */
5946         mac_control = &sp->mac_control;
5947         config = &sp->config;
5948
5949         /* Tx side parameters. */
5950         if (tx_fifo_len[0] == 0)
5951                 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
5952         config->tx_fifo_num = tx_fifo_num;
5953         for (i = 0; i < MAX_TX_FIFOS; i++) {
5954                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
5955                 config->tx_cfg[i].fifo_priority = i;
5956         }
5957
5958         /* mapping the QoS priority to the configured fifos */
5959         for (i = 0; i < MAX_TX_FIFOS; i++)
5960                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
5961
5962         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
5963         for (i = 0; i < config->tx_fifo_num; i++) {
5964                 config->tx_cfg[i].f_no_snoop =
5965                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
5966                 if (config->tx_cfg[i].fifo_len < 65) {
5967                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
5968                         break;
5969                 }
5970         }
5971         /* + 2 because one Txd for skb->data and one Txd for UFO */
5972         config->max_txds = MAX_SKB_FRAGS + 2;
5973
5974         /* Rx side parameters. */
5975         if (rx_ring_sz[0] == 0)
5976                 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
5977         config->rx_ring_num = rx_ring_num;
5978         for (i = 0; i < MAX_RX_RINGS; i++) {
5979                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
5980                     (rxd_count[sp->rxd_mode] + 1);
5981                 config->rx_cfg[i].ring_priority = i;
5982         }
5983
5984         for (i = 0; i < rx_ring_num; i++) {
5985                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
5986                 config->rx_cfg[i].f_no_snoop =
5987                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
5988         }
5989
5990         /*  Setting Mac Control parameters */
5991         mac_control->rmac_pause_time = rmac_pause_time;
5992         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
5993         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
5994
5995
5996         /* Initialize Ring buffer parameters. */
5997         for (i = 0; i < config->rx_ring_num; i++)
5998                 atomic_set(&sp->rx_bufs_left[i], 0);
5999
6000         /* Initialize the number of ISRs currently running */
6001         atomic_set(&sp->isr_cnt, 0);
6002
6003         /*  initialize the shared memory used by the NIC and the host */
6004         if (init_shared_mem(sp)) {
6005                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6006                           __FUNCTION__);
6007                 ret = -ENOMEM;
6008                 goto mem_alloc_failed;
6009         }
6010
6011         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6012                                      pci_resource_len(pdev, 0));
6013         if (!sp->bar0) {
6014                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6015                           dev->name);
6016                 ret = -ENOMEM;
6017                 goto bar0_remap_failed;
6018         }
6019
6020         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6021                                      pci_resource_len(pdev, 2));
6022         if (!sp->bar1) {
6023                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6024                           dev->name);
6025                 ret = -ENOMEM;
6026                 goto bar1_remap_failed;
6027         }
6028
6029         dev->irq = pdev->irq;
6030         dev->base_addr = (unsigned long) sp->bar0;
6031
6032         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6033         for (j = 0; j < MAX_TX_FIFOS; j++) {
6034                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6035                     (sp->bar1 + (j * 0x00020000));
6036         }
6037
6038         /*  Driver entry points */
6039         dev->open = &s2io_open;
6040         dev->stop = &s2io_close;
6041         dev->hard_start_xmit = &s2io_xmit;
6042         dev->get_stats = &s2io_get_stats;
6043         dev->set_multicast_list = &s2io_set_multicast;
6044         dev->do_ioctl = &s2io_ioctl;
6045         dev->change_mtu = &s2io_change_mtu;
6046         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6047         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6048         dev->vlan_rx_register = s2io_vlan_rx_register;
6049         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6050
6051         /*
6052          * will use eth_mac_addr() for  dev->set_mac_address
6053          * mac address will be set every time dev->open() is called
6054          */
6055 #if defined(CONFIG_S2IO_NAPI)
6056         dev->poll = s2io_poll;
6057         dev->weight = 32;
6058 #endif
6059
6060         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6061         if (sp->high_dma_flag == TRUE)
6062                 dev->features |= NETIF_F_HIGHDMA;
6063 #ifdef NETIF_F_TSO
6064         dev->features |= NETIF_F_TSO;
6065 #endif
6066         if (sp->device_type & XFRAME_II_DEVICE) {
6067                 dev->features |= NETIF_F_UFO;
6068                 dev->features |= NETIF_F_HW_CSUM;
6069         }
6070
6071         dev->tx_timeout = &s2io_tx_watchdog;
6072         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6073         INIT_WORK(&sp->rst_timer_task,
6074                   (void (*)(void *)) s2io_restart_nic, dev);
6075         INIT_WORK(&sp->set_link_task,
6076                   (void (*)(void *)) s2io_set_link, sp);
6077
6078         pci_save_state(sp->pdev);
6079
6080         /* Setting swapper control on the NIC, for proper reset operation */
6081         if (s2io_set_swapper(sp)) {
6082                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6083                           dev->name);
6084                 ret = -EAGAIN;
6085                 goto set_swap_failed;
6086         }
6087
6088         /* Verify if the Herc works on the slot its placed into */
6089         if (sp->device_type & XFRAME_II_DEVICE) {
6090                 mode = s2io_verify_pci_mode(sp);
6091                 if (mode < 0) {
6092                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6093                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6094                         ret = -EBADSLT;
6095                         goto set_swap_failed;
6096                 }
6097         }
6098
6099         /* Not needed for Herc */
6100         if (sp->device_type & XFRAME_I_DEVICE) {
6101                 /*
6102                  * Fix for all "FFs" MAC address problems observed on
6103                  * Alpha platforms
6104                  */
6105                 fix_mac_address(sp);
6106                 s2io_reset(sp);
6107         }
6108
6109         /*
6110          * MAC address initialization.
6111          * For now only one mac address will be read and used.
6112          */
6113         bar0 = sp->bar0;
6114         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6115             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6116         writeq(val64, &bar0->rmac_addr_cmd_mem);
6117         wait_for_cmd_complete(sp);
6118
6119         tmp64 = readq(&bar0->rmac_addr_data0_mem);
6120         mac_down = (u32) tmp64;
6121         mac_up = (u32) (tmp64 >> 32);
6122
6123         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
6124
6125         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
6126         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
6127         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
6128         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
6129         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
6130         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
6131
6132         /*  Set the factory defined MAC address initially   */
6133         dev->addr_len = ETH_ALEN;
6134         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
6135
6136         /*
6137          * Initialize the tasklet status and link state flags
6138          * and the card state parameter
6139          */
6140         atomic_set(&(sp->card_state), 0);
6141         sp->tasklet_status = 0;
6142         sp->link_state = 0;
6143
6144         /* Initialize spinlocks */
6145         spin_lock_init(&sp->tx_lock);
6146 #ifndef CONFIG_S2IO_NAPI
6147         spin_lock_init(&sp->put_lock);
6148 #endif
6149         spin_lock_init(&sp->rx_lock);
6150
6151         /*
6152          * SXE-002: Configure link and activity LED to init state
6153          * on driver load.
6154          */
6155         subid = sp->pdev->subsystem_device;
6156         if ((subid & 0xFF) >= 0x07) {
6157                 val64 = readq(&bar0->gpio_control);
6158                 val64 |= 0x0000800000000000ULL;
6159                 writeq(val64, &bar0->gpio_control);
6160                 val64 = 0x0411040400000000ULL;
6161                 writeq(val64, (void __iomem *) bar0 + 0x2700);
6162                 val64 = readq(&bar0->gpio_control);
6163         }
6164
6165         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
6166
6167         if (register_netdev(dev)) {
6168                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
6169                 ret = -ENODEV;
6170                 goto register_failed;
6171         }
6172
6173         if (sp->device_type & XFRAME_II_DEVICE) {
6174                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
6175                           dev->name);
6176                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6177                                 get_xena_rev_id(sp->pdev),
6178                                 s2io_driver_version);
6179                 switch(sp->intr_type) {
6180                         case INTA:
6181                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6182                                 break;
6183                         case MSI:
6184                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6185                                 break;
6186                         case MSI_X:
6187                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6188                                 break;
6189                 }
6190
6191                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6192                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6193                           sp->def_mac_addr[0].mac_addr[0],
6194                           sp->def_mac_addr[0].mac_addr[1],
6195                           sp->def_mac_addr[0].mac_addr[2],
6196                           sp->def_mac_addr[0].mac_addr[3],
6197                           sp->def_mac_addr[0].mac_addr[4],
6198                           sp->def_mac_addr[0].mac_addr[5]);
6199                 mode = s2io_print_pci_mode(sp);
6200                 if (mode < 0) {
6201                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
6202                         ret = -EBADSLT;
6203                         goto set_swap_failed;
6204                 }
6205         } else {
6206                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
6207                           dev->name);
6208                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6209                                         get_xena_rev_id(sp->pdev),
6210                                         s2io_driver_version);
6211                 switch(sp->intr_type) {
6212                         case INTA:
6213                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6214                                 break;
6215                         case MSI:
6216                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6217                                 break;
6218                         case MSI_X:
6219                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6220                                 break;
6221                 }
6222                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6223                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6224                           sp->def_mac_addr[0].mac_addr[0],
6225                           sp->def_mac_addr[0].mac_addr[1],
6226                           sp->def_mac_addr[0].mac_addr[2],
6227                           sp->def_mac_addr[0].mac_addr[3],
6228                           sp->def_mac_addr[0].mac_addr[4],
6229                           sp->def_mac_addr[0].mac_addr[5]);
6230         }
6231         if (sp->rxd_mode == RXD_MODE_3B)
6232                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer mode support has been "
6233                           "enabled\n",dev->name);
6234         if (sp->rxd_mode == RXD_MODE_3A)
6235                 DBG_PRINT(ERR_DBG, "%s: 3-Buffer mode support has been "
6236                           "enabled\n",dev->name);
6237
6238         /* Initialize device name */
6239         strcpy(sp->name, dev->name);
6240         if (sp->device_type & XFRAME_II_DEVICE)
6241                 strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
6242         else
6243                 strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
6244
6245         /* Initialize bimodal Interrupts */
6246         sp->config.bimodal = bimodal;
6247         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
6248                 sp->config.bimodal = 0;
6249                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
6250                         dev->name);
6251         }
6252
6253         /*
6254          * Make Link state as off at this point, when the Link change
6255          * interrupt comes the state will be automatically changed to
6256          * the right state.
6257          */
6258         netif_carrier_off(dev);
6259
6260         return 0;
6261
6262       register_failed:
6263       set_swap_failed:
6264         iounmap(sp->bar1);
6265       bar1_remap_failed:
6266         iounmap(sp->bar0);
6267       bar0_remap_failed:
6268       mem_alloc_failed:
6269         free_shared_mem(sp);
6270         pci_disable_device(pdev);
6271         if (dev_intr_type != MSI_X)
6272                 pci_release_regions(pdev);
6273         else {
6274                 release_mem_region(pci_resource_start(pdev, 0),
6275                         pci_resource_len(pdev, 0));
6276                 release_mem_region(pci_resource_start(pdev, 2),
6277                         pci_resource_len(pdev, 2));
6278         }
6279         pci_set_drvdata(pdev, NULL);
6280         free_netdev(dev);
6281
6282         return ret;
6283 }
6284
6285 /**
6286  * s2io_rem_nic - Free the PCI device
6287  * @pdev: structure containing the PCI related information of the device.
6288  * Description: This function is called by the Pci subsystem to release a
6289  * PCI device and free up all resource held up by the device. This could
6290  * be in response to a Hot plug event or when the driver is to be removed
6291  * from memory.
6292  */
6293
6294 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
6295 {
6296         struct net_device *dev =
6297             (struct net_device *) pci_get_drvdata(pdev);
6298         nic_t *sp;
6299
6300         if (dev == NULL) {
6301                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
6302                 return;
6303         }
6304
6305         sp = dev->priv;
6306         unregister_netdev(dev);
6307
6308         free_shared_mem(sp);
6309         iounmap(sp->bar0);
6310         iounmap(sp->bar1);
6311         pci_disable_device(pdev);
6312         if (sp->intr_type != MSI_X)
6313                 pci_release_regions(pdev);
6314         else {
6315                 release_mem_region(pci_resource_start(pdev, 0),
6316                         pci_resource_len(pdev, 0));
6317                 release_mem_region(pci_resource_start(pdev, 2),
6318                         pci_resource_len(pdev, 2));
6319         }
6320         pci_set_drvdata(pdev, NULL);
6321         free_netdev(dev);
6322 }
6323
6324 /**
6325  * s2io_starter - Entry point for the driver
6326  * Description: This function is the entry point for the driver. It verifies
6327  * the module loadable parameters and initializes PCI configuration space.
6328  */
6329
6330 int __init s2io_starter(void)
6331 {
6332         return pci_module_init(&s2io_driver);
6333 }
6334
6335 /**
6336  * s2io_closer - Cleanup routine for the driver
6337  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6338  */
6339
6340 void s2io_closer(void)
6341 {
6342         pci_unregister_driver(&s2io_driver);
6343         DBG_PRINT(INIT_DBG, "cleanup done\n");
6344 }
6345
6346 module_init(s2io_starter);
6347 module_exit(s2io_closer);