drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  ************************************************************************/
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/errno.h>
  50 #include <linux/ioport.h>
  51 #include <linux/pci.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/kernel.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/stddef.h>
  60 #include <linux/ioctl.h>
  61 #include <linux/timex.h>
  62 #include <linux/sched.h>
  63 #include <linux/ethtool.h>
  64 #include <linux/workqueue.h>
  65 #include <linux/if_vlan.h>
  66 #include <linux/ip.h>
  67 #include <linux/tcp.h>
  68 #include <net/tcp.h>
  69
  70 #include <asm/system.h>
  71 #include <asm/uaccess.h>
  72 #include <asm/io.h>
  73 #include <asm/div64.h>
  74
  75 /* local include */
  76 #include "s2io.h"
  77 #include "s2io-regs.h"
  78
  79 #define DRV_VERSION "2.0.14.2"
  80
  81 /* S2io Driver name & version. */
  82 static char s2io_driver_name[] = "Neterion";
  83 static char s2io_driver_version[] = DRV_VERSION;
  84
  85 static int rxd_size[4] = {32,48,48,64};
  86 static int rxd_count[4] = {127,85,85,63};
  87
  88 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  89 {
  90         int ret;
  91
  92         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  93                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  94
  95         return ret;
  96 }
  97
  98 /*
  99  * Cards with following subsystem_id have a link state indication
 100  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 101  * macro below identifies these cards given the subsystem_id.
 102  */
 103 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 104         (dev_type == XFRAME_I_DEVICE) ?                 \
 105                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 106                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 107
 108 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 109                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 110 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 111 #define PANIC   1
 112 #define LOW     2
 113 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 114 {
 115         mac_info_t *mac_control;
 116
 117         mac_control = &sp->mac_control;
 118         if (rxb_size <= rxd_count[sp->rxd_mode])
 119                 return PANIC;
 120         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 121                 return  LOW;
 122         return 0;
 123 }
 124
 125 /* Ethtool related variables and Macros. */
 126 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 127         "Register test\t(offline)",
 128         "Eeprom test\t(offline)",
 129         "Link test\t(online)",
 130         "RLDRAM test\t(offline)",
 131         "BIST Test\t(offline)"
 132 };
 133
 134 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 135         {"tmac_frms"},
 136         {"tmac_data_octets"},
 137         {"tmac_drop_frms"},
 138         {"tmac_mcst_frms"},
 139         {"tmac_bcst_frms"},
 140         {"tmac_pause_ctrl_frms"},
 141         {"tmac_ttl_octets"},
 142         {"tmac_ucst_frms"},
 143         {"tmac_nucst_frms"},
 144         {"tmac_any_err_frms"},
 145         {"tmac_ttl_less_fb_octets"},
 146         {"tmac_vld_ip_octets"},
 147         {"tmac_vld_ip"},
 148         {"tmac_drop_ip"},
 149         {"tmac_icmp"},
 150         {"tmac_rst_tcp"},
 151         {"tmac_tcp"},
 152         {"tmac_udp"},
 153         {"rmac_vld_frms"},
 154         {"rmac_data_octets"},
 155         {"rmac_fcs_err_frms"},
 156         {"rmac_drop_frms"},
 157         {"rmac_vld_mcst_frms"},
 158         {"rmac_vld_bcst_frms"},
 159         {"rmac_in_rng_len_err_frms"},
 160         {"rmac_out_rng_len_err_frms"},
 161         {"rmac_long_frms"},
 162         {"rmac_pause_ctrl_frms"},
 163         {"rmac_unsup_ctrl_frms"},
 164         {"rmac_ttl_octets"},
 165         {"rmac_accepted_ucst_frms"},
 166         {"rmac_accepted_nucst_frms"},
 167         {"rmac_discarded_frms"},
 168         {"rmac_drop_events"},
 169         {"rmac_ttl_less_fb_octets"},
 170         {"rmac_ttl_frms"},
 171         {"rmac_usized_frms"},
 172         {"rmac_osized_frms"},
 173         {"rmac_frag_frms"},
 174         {"rmac_jabber_frms"},
 175         {"rmac_ttl_64_frms"},
 176         {"rmac_ttl_65_127_frms"},
 177         {"rmac_ttl_128_255_frms"},
 178         {"rmac_ttl_256_511_frms"},
 179         {"rmac_ttl_512_1023_frms"},
 180         {"rmac_ttl_1024_1518_frms"},
 181         {"rmac_ip"},
 182         {"rmac_ip_octets"},
 183         {"rmac_hdr_err_ip"},
 184         {"rmac_drop_ip"},
 185         {"rmac_icmp"},
 186         {"rmac_tcp"},
 187         {"rmac_udp"},
 188         {"rmac_err_drp_udp"},
 189         {"rmac_xgmii_err_sym"},
 190         {"rmac_frms_q0"},
 191         {"rmac_frms_q1"},
 192         {"rmac_frms_q2"},
 193         {"rmac_frms_q3"},
 194         {"rmac_frms_q4"},
 195         {"rmac_frms_q5"},
 196         {"rmac_frms_q6"},
 197         {"rmac_frms_q7"},
 198         {"rmac_full_q0"},
 199         {"rmac_full_q1"},
 200         {"rmac_full_q2"},
 201         {"rmac_full_q3"},
 202         {"rmac_full_q4"},
 203         {"rmac_full_q5"},
 204         {"rmac_full_q6"},
 205         {"rmac_full_q7"},
 206         {"rmac_pause_cnt"},
 207         {"rmac_xgmii_data_err_cnt"},
 208         {"rmac_xgmii_ctrl_err_cnt"},
 209         {"rmac_accepted_ip"},
 210         {"rmac_err_tcp"},
 211         {"rd_req_cnt"},
 212         {"new_rd_req_cnt"},
 213         {"new_rd_req_rtry_cnt"},
 214         {"rd_rtry_cnt"},
 215         {"wr_rtry_rd_ack_cnt"},
 216         {"wr_req_cnt"},
 217         {"new_wr_req_cnt"},
 218         {"new_wr_req_rtry_cnt"},
 219         {"wr_rtry_cnt"},
 220         {"wr_disc_cnt"},
 221         {"rd_rtry_wr_ack_cnt"},
 222         {"txp_wr_cnt"},
 223         {"txd_rd_cnt"},
 224         {"txd_wr_cnt"},
 225         {"rxd_rd_cnt"},
 226         {"rxd_wr_cnt"},
 227         {"txf_rd_cnt"},
 228         {"rxf_wr_cnt"},
 229         {"rmac_ttl_1519_4095_frms"},
 230         {"rmac_ttl_4096_8191_frms"},
 231         {"rmac_ttl_8192_max_frms"},
 232         {"rmac_ttl_gt_max_frms"},
 233         {"rmac_osized_alt_frms"},
 234         {"rmac_jabber_alt_frms"},
 235         {"rmac_gt_max_alt_frms"},
 236         {"rmac_vlan_frms"},
 237         {"rmac_len_discard"},
 238         {"rmac_fcs_discard"},
 239         {"rmac_pf_discard"},
 240         {"rmac_da_discard"},
 241         {"rmac_red_discard"},
 242         {"rmac_rts_discard"},
 243         {"rmac_ingm_full_discard"},
 244         {"link_fault_cnt"},
 245         {"\n DRIVER STATISTICS"},
 246         {"single_bit_ecc_errs"},
 247         {"double_bit_ecc_errs"},
 248         {"parity_err_cnt"},
 249         {"serious_err_cnt"},
 250         {"soft_reset_cnt"},
 251         {"fifo_full_cnt"},
 252         {"ring_full_cnt"},
 253         ("alarm_transceiver_temp_high"),
 254         ("alarm_transceiver_temp_low"),
 255         ("alarm_laser_bias_current_high"),
 256         ("alarm_laser_bias_current_low"),
 257         ("alarm_laser_output_power_high"),
 258         ("alarm_laser_output_power_low"),
 259         ("warn_transceiver_temp_high"),
 260         ("warn_transceiver_temp_low"),
 261         ("warn_laser_bias_current_high"),
 262         ("warn_laser_bias_current_low"),
 263         ("warn_laser_output_power_high"),
 264         ("warn_laser_output_power_low"),
 265         ("lro_aggregated_pkts"),
 266         ("lro_flush_both_count"),
 267         ("lro_out_of_sequence_pkts"),
 268         ("lro_flush_due_to_max_pkts"),
 269         ("lro_avg_aggr_pkts"),
 270 };
 271
 272 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 273 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 274
 275 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 276 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 277
 278 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 279                         init_timer(&timer);                     \
 280                         timer.function = handle;                \
 281                         timer.data = (unsigned long) arg;       \
 282                         mod_timer(&timer, (jiffies + exp))      \
 283
 284 /* Add the vlan */
 285 static void s2io_vlan_rx_register(struct net_device *dev,
 286                                         struct vlan_group *grp)
 287 {
 288         nic_t *nic = dev->priv;
 289         unsigned long flags;
 290
 291         spin_lock_irqsave(&nic->tx_lock, flags);
 292         nic->vlgrp = grp;
 293         spin_unlock_irqrestore(&nic->tx_lock, flags);
 294 }
 295
 296 /* Unregister the vlan */
 297 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 298 {
 299         nic_t *nic = dev->priv;
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&nic->tx_lock, flags);
 303         if (nic->vlgrp)
 304                 nic->vlgrp->vlan_devices[vid] = NULL;
 305         spin_unlock_irqrestore(&nic->tx_lock, flags);
 306 }
 307
 308 /*
 309  * Constants to be programmed into the Xena's registers, to configure
 310  * the XAUI.
 311  */
 312
 313 #define END_SIGN        0x0
 314 static const u64 herc_act_dtx_cfg[] = {
 315         /* Set address */
 316         0x8000051536750000ULL, 0x80000515367500E0ULL,
 317         /* Write data */
 318         0x8000051536750004ULL, 0x80000515367500E4ULL,
 319         /* Set address */
 320         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 321         /* Write data */
 322         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 323         /* Set address */
 324         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 325         /* Write data */
 326         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 327         /* Set address */
 328         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 329         /* Write data */
 330         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 331         /* Done */
 332         END_SIGN
 333 };
 334
 335 static const u64 xena_dtx_cfg[] = {
 336         /* Set address */
 337         0x8000051500000000ULL, 0x80000515000000E0ULL,
 338         /* Write data */
 339         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 340         /* Set address */
 341         0x8001051500000000ULL, 0x80010515000000E0ULL,
 342         /* Write data */
 343         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 344         /* Set address */
 345         0x8002051500000000ULL, 0x80020515000000E0ULL,
 346         /* Write data */
 347         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 348         END_SIGN
 349 };
 350
 351 /*
 352  * Constants for Fixing the MacAddress problem seen mostly on
 353  * Alpha machines.
 354  */
 355 static const u64 fix_mac[] = {
 356         0x0060000000000000ULL, 0x0060600000000000ULL,
 357         0x0040600000000000ULL, 0x0000600000000000ULL,
 358         0x0020600000000000ULL, 0x0060600000000000ULL,
 359         0x0020600000000000ULL, 0x0060600000000000ULL,
 360         0x0020600000000000ULL, 0x0060600000000000ULL,
 361         0x0020600000000000ULL, 0x0060600000000000ULL,
 362         0x0020600000000000ULL, 0x0060600000000000ULL,
 363         0x0020600000000000ULL, 0x0060600000000000ULL,
 364         0x0020600000000000ULL, 0x0060600000000000ULL,
 365         0x0020600000000000ULL, 0x0060600000000000ULL,
 366         0x0020600000000000ULL, 0x0060600000000000ULL,
 367         0x0020600000000000ULL, 0x0060600000000000ULL,
 368         0x0020600000000000ULL, 0x0000600000000000ULL,
 369         0x0040600000000000ULL, 0x0060600000000000ULL,
 370         END_SIGN
 371 };
 372
 373 /* Module Loadable parameters. */
 374 static unsigned int tx_fifo_num = 1;
 375 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 376     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 377 static unsigned int rx_ring_num = 1;
 378 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 379     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 380 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 381     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 382 static unsigned int rx_ring_mode = 1;
 383 static unsigned int use_continuous_tx_intrs = 1;
 384 static unsigned int rmac_pause_time = 0x100;
 385 static unsigned int mc_pause_threshold_q0q3 = 187;
 386 static unsigned int mc_pause_threshold_q4q7 = 187;
 387 static unsigned int shared_splits;
 388 static unsigned int tmac_util_period = 5;
 389 static unsigned int rmac_util_period = 5;
 390 static unsigned int bimodal = 0;
 391 static unsigned int l3l4hdr_size = 128;
 392 #ifndef CONFIG_S2IO_NAPI
 393 static unsigned int indicate_max_pkts;
 394 #endif
 395 /* Frequency of Rx desc syncs expressed as power of 2 */
 396 static unsigned int rxsync_frequency = 3;
 397 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 398 static unsigned int intr_type = 0;
 399 /* Large receive offload feature */
 400 static unsigned int lro = 0;
 401 /* Max pkts to be aggregated by LRO at one time. If not specified,
 402  * aggregation happens until we hit max IP pkt size(64K)
 403  */
 404 static unsigned int lro_max_pkts = 0xFFFF;
 405
 406 /*
 407  * S2IO device table.
 408  * This table lists all the devices that this driver supports.
 409  */
 410 static struct pci_device_id s2io_tbl[] __devinitdata = {
 411         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 412          PCI_ANY_ID, PCI_ANY_ID},
 413         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 414          PCI_ANY_ID, PCI_ANY_ID},
 415         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 416          PCI_ANY_ID, PCI_ANY_ID},
 417         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 418          PCI_ANY_ID, PCI_ANY_ID},
 419         {0,}
 420 };
 421
 422 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 423
 424 static struct pci_driver s2io_driver = {
 425       .name = "S2IO",
 426       .id_table = s2io_tbl,
 427       .probe = s2io_init_nic,
 428       .remove = __devexit_p(s2io_rem_nic),
 429 };
 430
 431 /* A simplifier macro used both by init and free shared_mem Fns(). */
 432 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 433
 434 /**
 435  * init_shared_mem - Allocation and Initialization of Memory
 436  * @nic: Device private variable.
 437  * Description: The function allocates all the memory areas shared
 438  * between the NIC and the driver. This includes Tx descriptors,
 439  * Rx descriptors and the statistics block.
 440  */
 441
 442 static int init_shared_mem(struct s2io_nic *nic)
 443 {
 444         u32 size;
 445         void *tmp_v_addr, *tmp_v_addr_next;
 446         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 447         RxD_block_t *pre_rxd_blk = NULL;
 448         int i, j, blk_cnt, rx_sz, tx_sz;
 449         int lst_size, lst_per_page;
 450         struct net_device *dev = nic->dev;
 451         unsigned long tmp;
 452         buffAdd_t *ba;
 453
 454         mac_info_t *mac_control;
 455         struct config_param *config;
 456
 457         mac_control = &nic->mac_control;
 458         config = &nic->config;
 459
 460
 461         /* Allocation and initialization of TXDLs in FIOFs */
 462         size = 0;
 463         for (i = 0; i < config->tx_fifo_num; i++) {
 464                 size += config->tx_cfg[i].fifo_len;
 465         }
 466         if (size > MAX_AVAILABLE_TXDS) {
 467                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 468                           __FUNCTION__);
 469                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 470                 return FAILURE;
 471         }
 472
 473         lst_size = (sizeof(TxD_t) * config->max_txds);
 474         tx_sz = lst_size * size;
 475         lst_per_page = PAGE_SIZE / lst_size;
 476
 477         for (i = 0; i < config->tx_fifo_num; i++) {
 478                 int fifo_len = config->tx_cfg[i].fifo_len;
 479                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 480                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 481                                                           GFP_KERNEL);
 482                 if (!mac_control->fifos[i].list_info) {
 483                         DBG_PRINT(ERR_DBG,
 484                                   "Malloc failed for list_info\n");
 485                         return -ENOMEM;
 486                 }
 487                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 488         }
 489         for (i = 0; i < config->tx_fifo_num; i++) {
 490                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 491                                                 lst_per_page);
 492                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 493                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 494                     config->tx_cfg[i].fifo_len - 1;
 495                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 496                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 497                     config->tx_cfg[i].fifo_len - 1;
 498                 mac_control->fifos[i].fifo_no = i;
 499                 mac_control->fifos[i].nic = nic;
 500                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 501
 502                 for (j = 0; j < page_num; j++) {
 503                         int k = 0;
 504                         dma_addr_t tmp_p;
 505                         void *tmp_v;
 506                         tmp_v = pci_alloc_consistent(nic->pdev,
 507                                                      PAGE_SIZE, &tmp_p);
 508                         if (!tmp_v) {
 509                                 DBG_PRINT(ERR_DBG,
 510                                           "pci_alloc_consistent ");
 511                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 512                                 return -ENOMEM;
 513                         }
 514                         /* If we got a zero DMA address(can happen on
 515                          * certain platforms like PPC), reallocate.
 516                          * Store virtual address of page we don't want,
 517                          * to be freed later.
 518                          */
 519                         if (!tmp_p) {
 520                                 mac_control->zerodma_virt_addr = tmp_v;
 521                                 DBG_PRINT(INIT_DBG,
 522                                 "%s: Zero DMA address for TxDL. ", dev->name);
 523                                 DBG_PRINT(INIT_DBG,
 524                                 "Virtual address %p\n", tmp_v);
 525                                 tmp_v = pci_alloc_consistent(nic->pdev,
 526                                                      PAGE_SIZE, &tmp_p);
 527                                 if (!tmp_v) {
 528                                         DBG_PRINT(ERR_DBG,
 529                                           "pci_alloc_consistent ");
 530                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 531                                         return -ENOMEM;
 532                                 }
 533                         }
 534                         while (k < lst_per_page) {
 535                                 int l = (j * lst_per_page) + k;
 536                                 if (l == config->tx_cfg[i].fifo_len)
 537                                         break;
 538                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 539                                     tmp_v + (k * lst_size);
 540                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 541                                     tmp_p + (k * lst_size);
 542                                 k++;
 543                         }
 544                 }
 545         }
 546
 547         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 548         if (!nic->ufo_in_band_v)
 549                 return -ENOMEM;
 550
 551         /* Allocation and initialization of RXDs in Rings */
 552         size = 0;
 553         for (i = 0; i < config->rx_ring_num; i++) {
 554                 if (config->rx_cfg[i].num_rxd %
 555                     (rxd_count[nic->rxd_mode] + 1)) {
 556                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 557                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 558                                   i);
 559                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 560                         return FAILURE;
 561                 }
 562                 size += config->rx_cfg[i].num_rxd;
 563                 mac_control->rings[i].block_count =
 564                         config->rx_cfg[i].num_rxd /
 565                         (rxd_count[nic->rxd_mode] + 1 );
 566                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 567                         mac_control->rings[i].block_count;
 568         }
 569         if (nic->rxd_mode == RXD_MODE_1)
 570                 size = (size * (sizeof(RxD1_t)));
 571         else
 572                 size = (size * (sizeof(RxD3_t)));
 573         rx_sz = size;
 574
 575         for (i = 0; i < config->rx_ring_num; i++) {
 576                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 577                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 578                 mac_control->rings[i].rx_curr_get_info.ring_len =
 579                     config->rx_cfg[i].num_rxd - 1;
 580                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 581                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 582                 mac_control->rings[i].rx_curr_put_info.ring_len =
 583                     config->rx_cfg[i].num_rxd - 1;
 584                 mac_control->rings[i].nic = nic;
 585                 mac_control->rings[i].ring_no = i;
 586
 587                 blk_cnt = config->rx_cfg[i].num_rxd /
 588                                 (rxd_count[nic->rxd_mode] + 1);
 589                 /*  Allocating all the Rx blocks */
 590                 for (j = 0; j < blk_cnt; j++) {
 591                         rx_block_info_t *rx_blocks;
 592                         int l;
 593
 594                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 595                         size = SIZE_OF_BLOCK; //size is always page size
 596                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 597                                                           &tmp_p_addr);
 598                         if (tmp_v_addr == NULL) {
 599                                 /*
 600                                  * In case of failure, free_shared_mem()
 601                                  * is called, which should free any
 602                                  * memory that was alloced till the
 603                                  * failure happened.
 604                                  */
 605                                 rx_blocks->block_virt_addr = tmp_v_addr;
 606                                 return -ENOMEM;
 607                         }
 608                         memset(tmp_v_addr, 0, size);
 609                         rx_blocks->block_virt_addr = tmp_v_addr;
 610                         rx_blocks->block_dma_addr = tmp_p_addr;
 611                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 612                                                   rxd_count[nic->rxd_mode],
 613                                                   GFP_KERNEL);
 614                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 615                                 rx_blocks->rxds[l].virt_addr =
 616                                         rx_blocks->block_virt_addr +
 617                                         (rxd_size[nic->rxd_mode] * l);
 618                                 rx_blocks->rxds[l].dma_addr =
 619                                         rx_blocks->block_dma_addr +
 620                                         (rxd_size[nic->rxd_mode] * l);
 621                         }
 622                 }
 623                 /* Interlinking all Rx Blocks */
 624                 for (j = 0; j < blk_cnt; j++) {
 625                         tmp_v_addr =
 626                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 627                         tmp_v_addr_next =
 628                                 mac_control->rings[i].rx_blocks[(j + 1) %
 629                                               blk_cnt].block_virt_addr;
 630                         tmp_p_addr =
 631                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 632                         tmp_p_addr_next =
 633                                 mac_control->rings[i].rx_blocks[(j + 1) %
 634                                               blk_cnt].block_dma_addr;
 635
 636                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 637                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 638                             (unsigned long) tmp_v_addr_next;
 639                         pre_rxd_blk->pNext_RxD_Blk_physical =
 640                             (u64) tmp_p_addr_next;
 641                 }
 642         }
 643         if (nic->rxd_mode >= RXD_MODE_3A) {
 644                 /*
 645                  * Allocation of Storages for buffer addresses in 2BUFF mode
 646                  * and the buffers as well.
 647                  */
 648                 for (i = 0; i < config->rx_ring_num; i++) {
 649                         blk_cnt = config->rx_cfg[i].num_rxd /
 650                            (rxd_count[nic->rxd_mode]+ 1);
 651                         mac_control->rings[i].ba =
 652                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 653                                      GFP_KERNEL);
 654                         if (!mac_control->rings[i].ba)
 655                                 return -ENOMEM;
 656                         for (j = 0; j < blk_cnt; j++) {
 657                                 int k = 0;
 658                                 mac_control->rings[i].ba[j] =
 659                                         kmalloc((sizeof(buffAdd_t) *
 660                                                 (rxd_count[nic->rxd_mode] + 1)),
 661                                                 GFP_KERNEL);
 662                                 if (!mac_control->rings[i].ba[j])
 663                                         return -ENOMEM;
 664                                 while (k != rxd_count[nic->rxd_mode]) {
 665                                         ba = &mac_control->rings[i].ba[j][k];
 666
 667                                         ba->ba_0_org = (void *) kmalloc
 668                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 669                                         if (!ba->ba_0_org)
 670                                                 return -ENOMEM;
 671                                         tmp = (unsigned long)ba->ba_0_org;
 672                                         tmp += ALIGN_SIZE;
 673                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 674                                         ba->ba_0 = (void *) tmp;
 675
 676                                         ba->ba_1_org = (void *) kmalloc
 677                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 678                                         if (!ba->ba_1_org)
 679                                                 return -ENOMEM;
 680                                         tmp = (unsigned long) ba->ba_1_org;
 681                                         tmp += ALIGN_SIZE;
 682                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 683                                         ba->ba_1 = (void *) tmp;
 684                                         k++;
 685                                 }
 686                         }
 687                 }
 688         }
 689
 690         /* Allocation and initialization of Statistics block */
 691         size = sizeof(StatInfo_t);
 692         mac_control->stats_mem = pci_alloc_consistent
 693             (nic->pdev, size, &mac_control->stats_mem_phy);
 694
 695         if (!mac_control->stats_mem) {
 696                 /*
 697                  * In case of failure, free_shared_mem() is called, which
 698                  * should free any memory that was alloced till the
 699                  * failure happened.
 700                  */
 701                 return -ENOMEM;
 702         }
 703         mac_control->stats_mem_sz = size;
 704
 705         tmp_v_addr = mac_control->stats_mem;
 706         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 707         memset(tmp_v_addr, 0, size);
 708         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 709                   (unsigned long long) tmp_p_addr);
 710
 711         return SUCCESS;
 712 }
 713
 714 /**
 715  * free_shared_mem - Free the allocated Memory
 716  * @nic:  Device private variable.
 717  * Description: This function is to free all memory locations allocated by
 718  * the init_shared_mem() function and return it to the kernel.
 719  */
 720
 721 static void free_shared_mem(struct s2io_nic *nic)
 722 {
 723         int i, j, blk_cnt, size;
 724         void *tmp_v_addr;
 725         dma_addr_t tmp_p_addr;
 726         mac_info_t *mac_control;
 727         struct config_param *config;
 728         int lst_size, lst_per_page;
 729         struct net_device *dev = nic->dev;
 730
 731         if (!nic)
 732                 return;
 733
 734         mac_control = &nic->mac_control;
 735         config = &nic->config;
 736
 737         lst_size = (sizeof(TxD_t) * config->max_txds);
 738         lst_per_page = PAGE_SIZE / lst_size;
 739
 740         for (i = 0; i < config->tx_fifo_num; i++) {
 741                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 742                                                 lst_per_page);
 743                 for (j = 0; j < page_num; j++) {
 744                         int mem_blks = (j * lst_per_page);
 745                         if (!mac_control->fifos[i].list_info)
 746                                 return;
 747                         if (!mac_control->fifos[i].list_info[mem_blks].
 748                                  list_virt_addr)
 749                                 break;
 750                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 751                                             mac_control->fifos[i].
 752                                             list_info[mem_blks].
 753                                             list_virt_addr,
 754                                             mac_control->fifos[i].
 755                                             list_info[mem_blks].
 756                                             list_phy_addr);
 757                 }
 758                 /* If we got a zero DMA address during allocation,
 759                  * free the page now
 760                  */
 761                 if (mac_control->zerodma_virt_addr) {
 762                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 763                                             mac_control->zerodma_virt_addr,
 764                                             (dma_addr_t)0);
 765                         DBG_PRINT(INIT_DBG,
 766                                 "%s: Freeing TxDL with zero DMA addr. ",
 767                                 dev->name);
 768                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 769                                 mac_control->zerodma_virt_addr);
 770                 }
 771                 kfree(mac_control->fifos[i].list_info);
 772         }
 773
 774         size = SIZE_OF_BLOCK;
 775         for (i = 0; i < config->rx_ring_num; i++) {
 776                 blk_cnt = mac_control->rings[i].block_count;
 777                 for (j = 0; j < blk_cnt; j++) {
 778                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 779                                 block_virt_addr;
 780                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 781                                 block_dma_addr;
 782                         if (tmp_v_addr == NULL)
 783                                 break;
 784                         pci_free_consistent(nic->pdev, size,
 785                                             tmp_v_addr, tmp_p_addr);
 786                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 787                 }
 788         }
 789
 790         if (nic->rxd_mode >= RXD_MODE_3A) {
 791                 /* Freeing buffer storage addresses in 2BUFF mode. */
 792                 for (i = 0; i < config->rx_ring_num; i++) {
 793                         blk_cnt = config->rx_cfg[i].num_rxd /
 794                             (rxd_count[nic->rxd_mode] + 1);
 795                         for (j = 0; j < blk_cnt; j++) {
 796                                 int k = 0;
 797                                 if (!mac_control->rings[i].ba[j])
 798                                         continue;
 799                                 while (k != rxd_count[nic->rxd_mode]) {
 800                                         buffAdd_t *ba =
 801                                                 &mac_control->rings[i].ba[j][k];
 802                                         kfree(ba->ba_0_org);
 803                                         kfree(ba->ba_1_org);
 804                                         k++;
 805                                 }
 806                                 kfree(mac_control->rings[i].ba[j]);
 807                         }
 808                         kfree(mac_control->rings[i].ba);
 809                 }
 810         }
 811
 812         if (mac_control->stats_mem) {
 813                 pci_free_consistent(nic->pdev,
 814                                     mac_control->stats_mem_sz,
 815                                     mac_control->stats_mem,
 816                                     mac_control->stats_mem_phy);
 817         }
 818         if (nic->ufo_in_band_v)
 819                 kfree(nic->ufo_in_band_v);
 820 }
 821
 822 /**
 823  * s2io_verify_pci_mode -
 824  */
 825
 826 static int s2io_verify_pci_mode(nic_t *nic)
 827 {
 828         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 829         register u64 val64 = 0;
 830         int     mode;
 831
 832         val64 = readq(&bar0->pci_mode);
 833         mode = (u8)GET_PCI_MODE(val64);
 834
 835         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 836                 return -1;      /* Unknown PCI mode */
 837         return mode;
 838 }
 839
 840 #define NEC_VENID   0x1033
 841 #define NEC_DEVID   0x0125
 842 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 843 {
 844         struct pci_dev *tdev = NULL;
 845         while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 846                 if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
 847                         if (tdev->bus == s2io_pdev->bus->parent)
 848                                 return 1;
 849                 }
 850         }
 851         return 0;
 852 }
 853
 854 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 855 /**
 856  * s2io_print_pci_mode -
 857  */
 858 static int s2io_print_pci_mode(nic_t *nic)
 859 {
 860         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 861         register u64 val64 = 0;
 862         int     mode;
 863         struct config_param *config = &nic->config;
 864
 865         val64 = readq(&bar0->pci_mode);
 866         mode = (u8)GET_PCI_MODE(val64);
 867
 868         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 869                 return -1;      /* Unknown PCI mode */
 870
 871         config->bus_speed = bus_speed[mode];
 872
 873         if (s2io_on_nec_bridge(nic->pdev)) {
 874                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 875                                                         nic->dev->name);
 876                 return mode;
 877         }
 878
 879         if (val64 & PCI_MODE_32_BITS) {
 880                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 881         } else {
 882                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 883         }
 884
 885         switch(mode) {
 886                 case PCI_MODE_PCI_33:
 887                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 888                         break;
 889                 case PCI_MODE_PCI_66:
 890                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 891                         break;
 892                 case PCI_MODE_PCIX_M1_66:
 893                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 894                         break;
 895                 case PCI_MODE_PCIX_M1_100:
 896                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 897                         break;
 898                 case PCI_MODE_PCIX_M1_133:
 899                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 900                         break;
 901                 case PCI_MODE_PCIX_M2_66:
 902                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 903                         break;
 904                 case PCI_MODE_PCIX_M2_100:
 905                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 906                         break;
 907                 case PCI_MODE_PCIX_M2_133:
 908                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 909                         break;
 910                 default:
 911                         return -1;      /* Unsupported bus speed */
 912         }
 913
 914         return mode;
 915 }
 916
 917 /**
 918  *  init_nic - Initialization of hardware
 919  *  @nic: device peivate variable
 920  *  Description: The function sequentially configures every block
 921  *  of the H/W from their reset values.
 922  *  Return Value:  SUCCESS on success and
 923  *  '-1' on failure (endian settings incorrect).
 924  */
 925
 926 static int init_nic(struct s2io_nic *nic)
 927 {
 928         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 929         struct net_device *dev = nic->dev;
 930         register u64 val64 = 0;
 931         void __iomem *add;
 932         u32 time;
 933         int i, j;
 934         mac_info_t *mac_control;
 935         struct config_param *config;
 936         int dtx_cnt = 0;
 937         unsigned long long mem_share;
 938         int mem_size;
 939
 940         mac_control = &nic->mac_control;
 941         config = &nic->config;
 942
 943         /* to set the swapper controle on the card */
 944         if(s2io_set_swapper(nic)) {
 945                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 946                 return -1;
 947         }
 948
 949         /*
 950          * Herc requires EOI to be removed from reset before XGXS, so..
 951          */
 952         if (nic->device_type & XFRAME_II_DEVICE) {
 953                 val64 = 0xA500000000ULL;
 954                 writeq(val64, &bar0->sw_reset);
 955                 msleep(500);
 956                 val64 = readq(&bar0->sw_reset);
 957         }
 958
 959         /* Remove XGXS from reset state */
 960         val64 = 0;
 961         writeq(val64, &bar0->sw_reset);
 962         msleep(500);
 963         val64 = readq(&bar0->sw_reset);
 964
 965         /*  Enable Receiving broadcasts */
 966         add = &bar0->mac_cfg;
 967         val64 = readq(&bar0->mac_cfg);
 968         val64 |= MAC_RMAC_BCAST_ENABLE;
 969         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 970         writel((u32) val64, add);
 971         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 972         writel((u32) (val64 >> 32), (add + 4));
 973
 974         /* Read registers in all blocks */
 975         val64 = readq(&bar0->mac_int_mask);
 976         val64 = readq(&bar0->mc_int_mask);
 977         val64 = readq(&bar0->xgxs_int_mask);
 978
 979         /*  Set MTU */
 980         val64 = dev->mtu;
 981         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 982
 983         if (nic->device_type & XFRAME_II_DEVICE) {
 984                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 985                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 986                                           &bar0->dtx_control, UF);
 987                         if (dtx_cnt & 0x1)
 988                                 msleep(1); /* Necessary!! */
 989                         dtx_cnt++;
 990                 }
 991         } else {
 992                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 993                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 994                                           &bar0->dtx_control, UF);
 995                         val64 = readq(&bar0->dtx_control);
 996                         dtx_cnt++;
 997                 }
 998         }
 999
1000         /*  Tx DMA Initialization */
1001         val64 = 0;
1002         writeq(val64, &bar0->tx_fifo_partition_0);
1003         writeq(val64, &bar0->tx_fifo_partition_1);
1004         writeq(val64, &bar0->tx_fifo_partition_2);
1005         writeq(val64, &bar0->tx_fifo_partition_3);
1006
1007
1008         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1009                 val64 |=
1010                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1011                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1012                                     ((i * 32) + 5), 3);
1013
1014                 if (i == (config->tx_fifo_num - 1)) {
1015                         if (i % 2 == 0)
1016                                 i++;
1017                 }
1018
1019                 switch (i) {
1020                 case 1:
1021                         writeq(val64, &bar0->tx_fifo_partition_0);
1022                         val64 = 0;
1023                         break;
1024                 case 3:
1025                         writeq(val64, &bar0->tx_fifo_partition_1);
1026                         val64 = 0;
1027                         break;
1028                 case 5:
1029                         writeq(val64, &bar0->tx_fifo_partition_2);
1030                         val64 = 0;
1031                         break;
1032                 case 7:
1033                         writeq(val64, &bar0->tx_fifo_partition_3);
1034                         break;
1035                 }
1036         }
1037
1038         /*
1039          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1040          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1041          */
1042         if ((nic->device_type == XFRAME_I_DEVICE) &&
1043                 (get_xena_rev_id(nic->pdev) < 4))
1044                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1045
1046         val64 = readq(&bar0->tx_fifo_partition_0);
1047         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1048                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1049
1050         /*
1051          * Initialization of Tx_PA_CONFIG register to ignore packet
1052          * integrity checking.
1053          */
1054         val64 = readq(&bar0->tx_pa_cfg);
1055         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1056             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1057         writeq(val64, &bar0->tx_pa_cfg);
1058
1059         /* Rx DMA intialization. */
1060         val64 = 0;
1061         for (i = 0; i < config->rx_ring_num; i++) {
1062                 val64 |=
1063                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1064                          3);
1065         }
1066         writeq(val64, &bar0->rx_queue_priority);
1067
1068         /*
1069          * Allocating equal share of memory to all the
1070          * configured Rings.
1071          */
1072         val64 = 0;
1073         if (nic->device_type & XFRAME_II_DEVICE)
1074                 mem_size = 32;
1075         else
1076                 mem_size = 64;
1077
1078         for (i = 0; i < config->rx_ring_num; i++) {
1079                 switch (i) {
1080                 case 0:
1081                         mem_share = (mem_size / config->rx_ring_num +
1082                                      mem_size % config->rx_ring_num);
1083                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1084                         continue;
1085                 case 1:
1086                         mem_share = (mem_size / config->rx_ring_num);
1087                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1088                         continue;
1089                 case 2:
1090                         mem_share = (mem_size / config->rx_ring_num);
1091                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1092                         continue;
1093                 case 3:
1094                         mem_share = (mem_size / config->rx_ring_num);
1095                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1096                         continue;
1097                 case 4:
1098                         mem_share = (mem_size / config->rx_ring_num);
1099                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1100                         continue;
1101                 case 5:
1102                         mem_share = (mem_size / config->rx_ring_num);
1103                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1104                         continue;
1105                 case 6:
1106                         mem_share = (mem_size / config->rx_ring_num);
1107                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1108                         continue;
1109                 case 7:
1110                         mem_share = (mem_size / config->rx_ring_num);
1111                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1112                         continue;
1113                 }
1114         }
1115         writeq(val64, &bar0->rx_queue_cfg);
1116
1117         /*
1118          * Filling Tx round robin registers
1119          * as per the number of FIFOs
1120          */
1121         switch (config->tx_fifo_num) {
1122         case 1:
1123                 val64 = 0x0000000000000000ULL;
1124                 writeq(val64, &bar0->tx_w_round_robin_0);
1125                 writeq(val64, &bar0->tx_w_round_robin_1);
1126                 writeq(val64, &bar0->tx_w_round_robin_2);
1127                 writeq(val64, &bar0->tx_w_round_robin_3);
1128                 writeq(val64, &bar0->tx_w_round_robin_4);
1129                 break;
1130         case 2:
1131                 val64 = 0x0000010000010000ULL;
1132                 writeq(val64, &bar0->tx_w_round_robin_0);
1133                 val64 = 0x0100000100000100ULL;
1134                 writeq(val64, &bar0->tx_w_round_robin_1);
1135                 val64 = 0x0001000001000001ULL;
1136                 writeq(val64, &bar0->tx_w_round_robin_2);
1137                 val64 = 0x0000010000010000ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_3);
1139                 val64 = 0x0100000000000000ULL;
1140                 writeq(val64, &bar0->tx_w_round_robin_4);
1141                 break;
1142         case 3:
1143                 val64 = 0x0001000102000001ULL;
1144                 writeq(val64, &bar0->tx_w_round_robin_0);
1145                 val64 = 0x0001020000010001ULL;
1146                 writeq(val64, &bar0->tx_w_round_robin_1);
1147                 val64 = 0x0200000100010200ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_2);
1149                 val64 = 0x0001000102000001ULL;
1150                 writeq(val64, &bar0->tx_w_round_robin_3);
1151                 val64 = 0x0001020000000000ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_4);
1153                 break;
1154         case 4:
1155                 val64 = 0x0001020300010200ULL;
1156                 writeq(val64, &bar0->tx_w_round_robin_0);
1157                 val64 = 0x0100000102030001ULL;
1158                 writeq(val64, &bar0->tx_w_round_robin_1);
1159                 val64 = 0x0200010000010203ULL;
1160                 writeq(val64, &bar0->tx_w_round_robin_2);
1161                 val64 = 0x0001020001000001ULL;
1162                 writeq(val64, &bar0->tx_w_round_robin_3);
1163                 val64 = 0x0203000100000000ULL;
1164                 writeq(val64, &bar0->tx_w_round_robin_4);
1165                 break;
1166         case 5:
1167                 val64 = 0x0001000203000102ULL;
1168                 writeq(val64, &bar0->tx_w_round_robin_0);
1169                 val64 = 0x0001020001030004ULL;
1170                 writeq(val64, &bar0->tx_w_round_robin_1);
1171                 val64 = 0x0001000203000102ULL;
1172                 writeq(val64, &bar0->tx_w_round_robin_2);
1173                 val64 = 0x0001020001030004ULL;
1174                 writeq(val64, &bar0->tx_w_round_robin_3);
1175                 val64 = 0x0001000000000000ULL;
1176                 writeq(val64, &bar0->tx_w_round_robin_4);
1177                 break;
1178         case 6:
1179                 val64 = 0x0001020304000102ULL;
1180                 writeq(val64, &bar0->tx_w_round_robin_0);
1181                 val64 = 0x0304050001020001ULL;
1182                 writeq(val64, &bar0->tx_w_round_robin_1);
1183                 val64 = 0x0203000100000102ULL;
1184                 writeq(val64, &bar0->tx_w_round_robin_2);
1185                 val64 = 0x0304000102030405ULL;
1186                 writeq(val64, &bar0->tx_w_round_robin_3);
1187                 val64 = 0x0001000200000000ULL;
1188                 writeq(val64, &bar0->tx_w_round_robin_4);
1189                 break;
1190         case 7:
1191                 val64 = 0x0001020001020300ULL;
1192                 writeq(val64, &bar0->tx_w_round_robin_0);
1193                 val64 = 0x0102030400010203ULL;
1194                 writeq(val64, &bar0->tx_w_round_robin_1);
1195                 val64 = 0x0405060001020001ULL;
1196                 writeq(val64, &bar0->tx_w_round_robin_2);
1197                 val64 = 0x0304050000010200ULL;
1198                 writeq(val64, &bar0->tx_w_round_robin_3);
1199                 val64 = 0x0102030000000000ULL;
1200                 writeq(val64, &bar0->tx_w_round_robin_4);
1201                 break;
1202         case 8:
1203                 val64 = 0x0001020300040105ULL;
1204                 writeq(val64, &bar0->tx_w_round_robin_0);
1205                 val64 = 0x0200030106000204ULL;
1206                 writeq(val64, &bar0->tx_w_round_robin_1);
1207                 val64 = 0x0103000502010007ULL;
1208                 writeq(val64, &bar0->tx_w_round_robin_2);
1209                 val64 = 0x0304010002060500ULL;
1210                 writeq(val64, &bar0->tx_w_round_robin_3);
1211                 val64 = 0x0103020400000000ULL;
1212                 writeq(val64, &bar0->tx_w_round_robin_4);
1213                 break;
1214         }
1215
1216         /* Enable Tx FIFO partition 0. */
1217         val64 = readq(&bar0->tx_fifo_partition_0);
1218         val64 |= (TX_FIFO_PARTITION_EN);
1219         writeq(val64, &bar0->tx_fifo_partition_0);
1220
1221         /* Filling the Rx round robin registers as per the
1222          * number of Rings and steering based on QoS.
1223          */
1224         switch (config->rx_ring_num) {
1225         case 1:
1226                 val64 = 0x8080808080808080ULL;
1227                 writeq(val64, &bar0->rts_qos_steering);
1228                 break;
1229         case 2:
1230                 val64 = 0x0000010000010000ULL;
1231                 writeq(val64, &bar0->rx_w_round_robin_0);
1232                 val64 = 0x0100000100000100ULL;
1233                 writeq(val64, &bar0->rx_w_round_robin_1);
1234                 val64 = 0x0001000001000001ULL;
1235                 writeq(val64, &bar0->rx_w_round_robin_2);
1236                 val64 = 0x0000010000010000ULL;
1237                 writeq(val64, &bar0->rx_w_round_robin_3);
1238                 val64 = 0x0100000000000000ULL;
1239                 writeq(val64, &bar0->rx_w_round_robin_4);
1240
1241                 val64 = 0x8080808040404040ULL;
1242                 writeq(val64, &bar0->rts_qos_steering);
1243                 break;
1244         case 3:
1245                 val64 = 0x0001000102000001ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_0);
1247                 val64 = 0x0001020000010001ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_1);
1249                 val64 = 0x0200000100010200ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_2);
1251                 val64 = 0x0001000102000001ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_3);
1253                 val64 = 0x0001020000000000ULL;
1254                 writeq(val64, &bar0->rx_w_round_robin_4);
1255
1256                 val64 = 0x8080804040402020ULL;
1257                 writeq(val64, &bar0->rts_qos_steering);
1258                 break;
1259         case 4:
1260                 val64 = 0x0001020300010200ULL;
1261                 writeq(val64, &bar0->rx_w_round_robin_0);
1262                 val64 = 0x0100000102030001ULL;
1263                 writeq(val64, &bar0->rx_w_round_robin_1);
1264                 val64 = 0x0200010000010203ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_2);
1266                 val64 = 0x0001020001000001ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_3);
1268                 val64 = 0x0203000100000000ULL;
1269                 writeq(val64, &bar0->rx_w_round_robin_4);
1270
1271                 val64 = 0x8080404020201010ULL;
1272                 writeq(val64, &bar0->rts_qos_steering);
1273                 break;
1274         case 5:
1275                 val64 = 0x0001000203000102ULL;
1276                 writeq(val64, &bar0->rx_w_round_robin_0);
1277                 val64 = 0x0001020001030004ULL;
1278                 writeq(val64, &bar0->rx_w_round_robin_1);
1279                 val64 = 0x0001000203000102ULL;
1280                 writeq(val64, &bar0->rx_w_round_robin_2);
1281                 val64 = 0x0001020001030004ULL;
1282                 writeq(val64, &bar0->rx_w_round_robin_3);
1283                 val64 = 0x0001000000000000ULL;
1284                 writeq(val64, &bar0->rx_w_round_robin_4);
1285
1286                 val64 = 0x8080404020201008ULL;
1287                 writeq(val64, &bar0->rts_qos_steering);
1288                 break;
1289         case 6:
1290                 val64 = 0x0001020304000102ULL;
1291                 writeq(val64, &bar0->rx_w_round_robin_0);
1292                 val64 = 0x0304050001020001ULL;
1293                 writeq(val64, &bar0->rx_w_round_robin_1);
1294                 val64 = 0x0203000100000102ULL;
1295                 writeq(val64, &bar0->rx_w_round_robin_2);
1296                 val64 = 0x0304000102030405ULL;
1297                 writeq(val64, &bar0->rx_w_round_robin_3);
1298                 val64 = 0x0001000200000000ULL;
1299                 writeq(val64, &bar0->rx_w_round_robin_4);
1300
1301                 val64 = 0x8080404020100804ULL;
1302                 writeq(val64, &bar0->rts_qos_steering);
1303                 break;
1304         case 7:
1305                 val64 = 0x0001020001020300ULL;
1306                 writeq(val64, &bar0->rx_w_round_robin_0);
1307                 val64 = 0x0102030400010203ULL;
1308                 writeq(val64, &bar0->rx_w_round_robin_1);
1309                 val64 = 0x0405060001020001ULL;
1310                 writeq(val64, &bar0->rx_w_round_robin_2);
1311                 val64 = 0x0304050000010200ULL;
1312                 writeq(val64, &bar0->rx_w_round_robin_3);
1313                 val64 = 0x0102030000000000ULL;
1314                 writeq(val64, &bar0->rx_w_round_robin_4);
1315
1316                 val64 = 0x8080402010080402ULL;
1317                 writeq(val64, &bar0->rts_qos_steering);
1318                 break;
1319         case 8:
1320                 val64 = 0x0001020300040105ULL;
1321                 writeq(val64, &bar0->rx_w_round_robin_0);
1322                 val64 = 0x0200030106000204ULL;
1323                 writeq(val64, &bar0->rx_w_round_robin_1);
1324                 val64 = 0x0103000502010007ULL;
1325                 writeq(val64, &bar0->rx_w_round_robin_2);
1326                 val64 = 0x0304010002060500ULL;
1327                 writeq(val64, &bar0->rx_w_round_robin_3);
1328                 val64 = 0x0103020400000000ULL;
1329                 writeq(val64, &bar0->rx_w_round_robin_4);
1330
1331                 val64 = 0x8040201008040201ULL;
1332                 writeq(val64, &bar0->rts_qos_steering);
1333                 break;
1334         }
1335
1336         /* UDP Fix */
1337         val64 = 0;
1338         for (i = 0; i < 8; i++)
1339                 writeq(val64, &bar0->rts_frm_len_n[i]);
1340
1341         /* Set the default rts frame length for the rings configured */
1342         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1343         for (i = 0 ; i < config->rx_ring_num ; i++)
1344                 writeq(val64, &bar0->rts_frm_len_n[i]);
1345
1346         /* Set the frame length for the configured rings
1347          * desired by the user
1348          */
1349         for (i = 0; i < config->rx_ring_num; i++) {
1350                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1351                  * specified frame length steering.
1352                  * If the user provides the frame length then program
1353                  * the rts_frm_len register for those values or else
1354                  * leave it as it is.
1355                  */
1356                 if (rts_frm_len[i] != 0) {
1357                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1358                                 &bar0->rts_frm_len_n[i]);
1359                 }
1360         }
1361
1362         /* Program statistics memory */
1363         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1364
1365         if (nic->device_type == XFRAME_II_DEVICE) {
1366                 val64 = STAT_BC(0x320);
1367                 writeq(val64, &bar0->stat_byte_cnt);
1368         }
1369
1370         /*
1371          * Initializing the sampling rate for the device to calculate the
1372          * bandwidth utilization.
1373          */
1374         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1375             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1376         writeq(val64, &bar0->mac_link_util);
1377
1378
1379         /*
1380          * Initializing the Transmit and Receive Traffic Interrupt
1381          * Scheme.
1382          */
1383         /*
1384          * TTI Initialization. Default Tx timer gets us about
1385          * 250 interrupts per sec. Continuous interrupts are enabled
1386          * by default.
1387          */
1388         if (nic->device_type == XFRAME_II_DEVICE) {
1389                 int count = (nic->config.bus_speed * 125)/2;
1390                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1391         } else {
1392
1393                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1394         }
1395         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1396             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1397             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1398                 if (use_continuous_tx_intrs)
1399                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1400         writeq(val64, &bar0->tti_data1_mem);
1401
1402         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1403             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1404             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1405         writeq(val64, &bar0->tti_data2_mem);
1406
1407         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1408         writeq(val64, &bar0->tti_command_mem);
1409
1410         /*
1411          * Once the operation completes, the Strobe bit of the command
1412          * register will be reset. We poll for this particular condition
1413          * We wait for a maximum of 500ms for the operation to complete,
1414          * if it's not complete by then we return error.
1415          */
1416         time = 0;
1417         while (TRUE) {
1418                 val64 = readq(&bar0->tti_command_mem);
1419                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1420                         break;
1421                 }
1422                 if (time > 10) {
1423                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1424                                   dev->name);
1425                         return -1;
1426                 }
1427                 msleep(50);
1428                 time++;
1429         }
1430
1431         if (nic->config.bimodal) {
1432                 int k = 0;
1433                 for (k = 0; k < config->rx_ring_num; k++) {
1434                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1435                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1436                         writeq(val64, &bar0->tti_command_mem);
1437
1438                 /*
1439                  * Once the operation completes, the Strobe bit of the command
1440                  * register will be reset. We poll for this particular condition
1441                  * We wait for a maximum of 500ms for the operation to complete,
1442                  * if it's not complete by then we return error.
1443                 */
1444                         time = 0;
1445                         while (TRUE) {
1446                                 val64 = readq(&bar0->tti_command_mem);
1447                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1448                                         break;
1449                                 }
1450                                 if (time > 10) {
1451                                         DBG_PRINT(ERR_DBG,
1452                                                 "%s: TTI init Failed\n",
1453                                         dev->name);
1454                                         return -1;
1455                                 }
1456                                 time++;
1457                                 msleep(50);
1458                         }
1459                 }
1460         } else {
1461
1462                 /* RTI Initialization */
1463                 if (nic->device_type == XFRAME_II_DEVICE) {
1464                         /*
1465                          * Programmed to generate Apprx 500 Intrs per
1466                          * second
1467                          */
1468                         int count = (nic->config.bus_speed * 125)/4;
1469                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1470                 } else {
1471                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1472                 }
1473                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1474                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1475                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1476
1477                 writeq(val64, &bar0->rti_data1_mem);
1478
1479                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1480                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1481                 if (nic->intr_type == MSI_X)
1482                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1483                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1484                 else
1485                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1486                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1487                 writeq(val64, &bar0->rti_data2_mem);
1488
1489                 for (i = 0; i < config->rx_ring_num; i++) {
1490                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1491                                         | RTI_CMD_MEM_OFFSET(i);
1492                         writeq(val64, &bar0->rti_command_mem);
1493
1494                         /*
1495                          * Once the operation completes, the Strobe bit of the
1496                          * command register will be reset. We poll for this
1497                          * particular condition. We wait for a maximum of 500ms
1498                          * for the operation to complete, if it's not complete
1499                          * by then we return error.
1500                          */
1501                         time = 0;
1502                         while (TRUE) {
1503                                 val64 = readq(&bar0->rti_command_mem);
1504                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1505                                         break;
1506                                 }
1507                                 if (time > 10) {
1508                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1509                                                   dev->name);
1510                                         return -1;
1511                                 }
1512                                 time++;
1513                                 msleep(50);
1514                         }
1515                 }
1516         }
1517
1518         /*
1519          * Initializing proper values as Pause threshold into all
1520          * the 8 Queues on Rx side.
1521          */
1522         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1523         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1524
1525         /* Disable RMAC PAD STRIPPING */
1526         add = &bar0->mac_cfg;
1527         val64 = readq(&bar0->mac_cfg);
1528         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1529         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1530         writel((u32) (val64), add);
1531         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1532         writel((u32) (val64 >> 32), (add + 4));
1533         val64 = readq(&bar0->mac_cfg);
1534
1535         /* Enable FCS stripping by adapter */
1536         add = &bar0->mac_cfg;
1537         val64 = readq(&bar0->mac_cfg);
1538         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1539         if (nic->device_type == XFRAME_II_DEVICE)
1540                 writeq(val64, &bar0->mac_cfg);
1541         else {
1542                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543                 writel((u32) (val64), add);
1544                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545                 writel((u32) (val64 >> 32), (add + 4));
1546         }
1547
1548         /*
1549          * Set the time value to be inserted in the pause frame
1550          * generated by xena.
1551          */
1552         val64 = readq(&bar0->rmac_pause_cfg);
1553         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1554         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1555         writeq(val64, &bar0->rmac_pause_cfg);
1556
1557         /*
1558          * Set the Threshold Limit for Generating the pause frame
1559          * If the amount of data in any Queue exceeds ratio of
1560          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1561          * pause frame is generated
1562          */
1563         val64 = 0;
1564         for (i = 0; i < 4; i++) {
1565                 val64 |=
1566                     (((u64) 0xFF00 | nic->mac_control.
1567                       mc_pause_threshold_q0q3)
1568                      << (i * 2 * 8));
1569         }
1570         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1571
1572         val64 = 0;
1573         for (i = 0; i < 4; i++) {
1574                 val64 |=
1575                     (((u64) 0xFF00 | nic->mac_control.
1576                       mc_pause_threshold_q4q7)
1577                      << (i * 2 * 8));
1578         }
1579         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1580
1581         /*
1582          * TxDMA will stop Read request if the number of read split has
1583          * exceeded the limit pointed by shared_splits
1584          */
1585         val64 = readq(&bar0->pic_control);
1586         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1587         writeq(val64, &bar0->pic_control);
1588
1589         if (nic->config.bus_speed == 266) {
1590                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1591                 writeq(0x0, &bar0->read_retry_delay);
1592                 writeq(0x0, &bar0->write_retry_delay);
1593         }
1594
1595         /*
1596          * Programming the Herc to split every write transaction
1597          * that does not start on an ADB to reduce disconnects.
1598          */
1599         if (nic->device_type == XFRAME_II_DEVICE) {
1600                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1601                 writeq(val64, &bar0->misc_control);
1602                 val64 = readq(&bar0->pic_control2);
1603                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1604                 writeq(val64, &bar0->pic_control2);
1605         }
1606         if (strstr(nic->product_name, "CX4")) {
1607                 val64 = TMAC_AVG_IPG(0x17);
1608                 writeq(val64, &bar0->tmac_avg_ipg);
1609         }
1610
1611         return SUCCESS;
1612 }
1613 #define LINK_UP_DOWN_INTERRUPT          1
1614 #define MAC_RMAC_ERR_TIMER              2
1615
1616 static int s2io_link_fault_indication(nic_t *nic)
1617 {
1618         if (nic->intr_type != INTA)
1619                 return MAC_RMAC_ERR_TIMER;
1620         if (nic->device_type == XFRAME_II_DEVICE)
1621                 return LINK_UP_DOWN_INTERRUPT;
1622         else
1623                 return MAC_RMAC_ERR_TIMER;
1624 }
1625
1626 /**
1627  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1628  *  @nic: device private variable,
1629  *  @mask: A mask indicating which Intr block must be modified and,
1630  *  @flag: A flag indicating whether to enable or disable the Intrs.
1631  *  Description: This function will either disable or enable the interrupts
1632  *  depending on the flag argument. The mask argument can be used to
1633  *  enable/disable any Intr block.
1634  *  Return Value: NONE.
1635  */
1636
1637 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1638 {
1639         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1640         register u64 val64 = 0, temp64 = 0;
1641
1642         /*  Top level interrupt classification */
1643         /*  PIC Interrupts */
1644         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1645                 /*  Enable PIC Intrs in the general intr mask register */
1646                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1647                 if (flag == ENABLE_INTRS) {
1648                         temp64 = readq(&bar0->general_int_mask);
1649                         temp64 &= ~((u64) val64);
1650                         writeq(temp64, &bar0->general_int_mask);
1651                         /*
1652                          * If Hercules adapter enable GPIO otherwise
1653                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1654                          * interrupts for now.
1655                          * TODO
1656                          */
1657                         if (s2io_link_fault_indication(nic) ==
1658                                         LINK_UP_DOWN_INTERRUPT ) {
1659                                 temp64 = readq(&bar0->pic_int_mask);
1660                                 temp64 &= ~((u64) PIC_INT_GPIO);
1661                                 writeq(temp64, &bar0->pic_int_mask);
1662                                 temp64 = readq(&bar0->gpio_int_mask);
1663                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1664                                 writeq(temp64, &bar0->gpio_int_mask);
1665                         } else {
1666                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1667                         }
1668                         /*
1669                          * No MSI Support is available presently, so TTI and
1670                          * RTI interrupts are also disabled.
1671                          */
1672                 } else if (flag == DISABLE_INTRS) {
1673                         /*
1674                          * Disable PIC Intrs in the general
1675                          * intr mask register
1676                          */
1677                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1678                         temp64 = readq(&bar0->general_int_mask);
1679                         val64 |= temp64;
1680                         writeq(val64, &bar0->general_int_mask);
1681                 }
1682         }
1683
1684         /*  DMA Interrupts */
1685         /*  Enabling/Disabling Tx DMA interrupts */
1686         if (mask & TX_DMA_INTR) {
1687                 /* Enable TxDMA Intrs in the general intr mask register */
1688                 val64 = TXDMA_INT_M;
1689                 if (flag == ENABLE_INTRS) {
1690                         temp64 = readq(&bar0->general_int_mask);
1691                         temp64 &= ~((u64) val64);
1692                         writeq(temp64, &bar0->general_int_mask);
1693                         /*
1694                          * Keep all interrupts other than PFC interrupt
1695                          * and PCC interrupt disabled in DMA level.
1696                          */
1697                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1698                                                       TXDMA_PCC_INT_M);
1699                         writeq(val64, &bar0->txdma_int_mask);
1700                         /*
1701                          * Enable only the MISC error 1 interrupt in PFC block
1702                          */
1703                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1704                         writeq(val64, &bar0->pfc_err_mask);
1705                         /*
1706                          * Enable only the FB_ECC error interrupt in PCC block
1707                          */
1708                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1709                         writeq(val64, &bar0->pcc_err_mask);
1710                 } else if (flag == DISABLE_INTRS) {
1711                         /*
1712                          * Disable TxDMA Intrs in the general intr mask
1713                          * register
1714                          */
1715                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1716                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1717                         temp64 = readq(&bar0->general_int_mask);
1718                         val64 |= temp64;
1719                         writeq(val64, &bar0->general_int_mask);
1720                 }
1721         }
1722
1723         /*  Enabling/Disabling Rx DMA interrupts */
1724         if (mask & RX_DMA_INTR) {
1725                 /*  Enable RxDMA Intrs in the general intr mask register */
1726                 val64 = RXDMA_INT_M;
1727                 if (flag == ENABLE_INTRS) {
1728                         temp64 = readq(&bar0->general_int_mask);
1729                         temp64 &= ~((u64) val64);
1730                         writeq(temp64, &bar0->general_int_mask);
1731                         /*
1732                          * All RxDMA block interrupts are disabled for now
1733                          * TODO
1734                          */
1735                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1736                 } else if (flag == DISABLE_INTRS) {
1737                         /*
1738                          * Disable RxDMA Intrs in the general intr mask
1739                          * register
1740                          */
1741                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1742                         temp64 = readq(&bar0->general_int_mask);
1743                         val64 |= temp64;
1744                         writeq(val64, &bar0->general_int_mask);
1745                 }
1746         }
1747
1748         /*  MAC Interrupts */
1749         /*  Enabling/Disabling MAC interrupts */
1750         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1751                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1752                 if (flag == ENABLE_INTRS) {
1753                         temp64 = readq(&bar0->general_int_mask);
1754                         temp64 &= ~((u64) val64);
1755                         writeq(temp64, &bar0->general_int_mask);
1756                         /*
1757                          * All MAC block error interrupts are disabled for now
1758                          * TODO
1759                          */
1760                 } else if (flag == DISABLE_INTRS) {
1761                         /*
1762                          * Disable MAC Intrs in the general intr mask register
1763                          */
1764                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1765                         writeq(DISABLE_ALL_INTRS,
1766                                &bar0->mac_rmac_err_mask);
1767
1768                         temp64 = readq(&bar0->general_int_mask);
1769                         val64 |= temp64;
1770                         writeq(val64, &bar0->general_int_mask);
1771                 }
1772         }
1773
1774         /*  XGXS Interrupts */
1775         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1776                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1777                 if (flag == ENABLE_INTRS) {
1778                         temp64 = readq(&bar0->general_int_mask);
1779                         temp64 &= ~((u64) val64);
1780                         writeq(temp64, &bar0->general_int_mask);
1781                         /*
1782                          * All XGXS block error interrupts are disabled for now
1783                          * TODO
1784                          */
1785                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1786                 } else if (flag == DISABLE_INTRS) {
1787                         /*
1788                          * Disable MC Intrs in the general intr mask register
1789                          */
1790                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1791                         temp64 = readq(&bar0->general_int_mask);
1792                         val64 |= temp64;
1793                         writeq(val64, &bar0->general_int_mask);
1794                 }
1795         }
1796
1797         /*  Memory Controller(MC) interrupts */
1798         if (mask & MC_INTR) {
1799                 val64 = MC_INT_M;
1800                 if (flag == ENABLE_INTRS) {
1801                         temp64 = readq(&bar0->general_int_mask);
1802                         temp64 &= ~((u64) val64);
1803                         writeq(temp64, &bar0->general_int_mask);
1804                         /*
1805                          * Enable all MC Intrs.
1806                          */
1807                         writeq(0x0, &bar0->mc_int_mask);
1808                         writeq(0x0, &bar0->mc_err_mask);
1809                 } else if (flag == DISABLE_INTRS) {
1810                         /*
1811                          * Disable MC Intrs in the general intr mask register
1812                          */
1813                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1814                         temp64 = readq(&bar0->general_int_mask);
1815                         val64 |= temp64;
1816                         writeq(val64, &bar0->general_int_mask);
1817                 }
1818         }
1819
1820
1821         /*  Tx traffic interrupts */
1822         if (mask & TX_TRAFFIC_INTR) {
1823                 val64 = TXTRAFFIC_INT_M;
1824                 if (flag == ENABLE_INTRS) {
1825                         temp64 = readq(&bar0->general_int_mask);
1826                         temp64 &= ~((u64) val64);
1827                         writeq(temp64, &bar0->general_int_mask);
1828                         /*
1829                          * Enable all the Tx side interrupts
1830                          * writing 0 Enables all 64 TX interrupt levels
1831                          */
1832                         writeq(0x0, &bar0->tx_traffic_mask);
1833                 } else if (flag == DISABLE_INTRS) {
1834                         /*
1835                          * Disable Tx Traffic Intrs in the general intr mask
1836                          * register.
1837                          */
1838                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1839                         temp64 = readq(&bar0->general_int_mask);
1840                         val64 |= temp64;
1841                         writeq(val64, &bar0->general_int_mask);
1842                 }
1843         }
1844
1845         /*  Rx traffic interrupts */
1846         if (mask & RX_TRAFFIC_INTR) {
1847                 val64 = RXTRAFFIC_INT_M;
1848                 if (flag == ENABLE_INTRS) {
1849                         temp64 = readq(&bar0->general_int_mask);
1850                         temp64 &= ~((u64) val64);
1851                         writeq(temp64, &bar0->general_int_mask);
1852                         /* writing 0 Enables all 8 RX interrupt levels */
1853                         writeq(0x0, &bar0->rx_traffic_mask);
1854                 } else if (flag == DISABLE_INTRS) {
1855                         /*
1856                          * Disable Rx Traffic Intrs in the general intr mask
1857                          * register.
1858                          */
1859                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1860                         temp64 = readq(&bar0->general_int_mask);
1861                         val64 |= temp64;
1862                         writeq(val64, &bar0->general_int_mask);
1863                 }
1864         }
1865 }
1866
1867 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1868 {
1869         int ret = 0;
1870
1871         if (flag == FALSE) {
1872                 if ((!herc && (rev_id >= 4)) || herc) {
1873                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1874                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1875                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1876                                 ret = 1;
1877                         }
1878                 }else {
1879                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1880                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1881                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1882                                 ret = 1;
1883                         }
1884                 }
1885         } else {
1886                 if ((!herc && (rev_id >= 4)) || herc) {
1887                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1888                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1889                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1890                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1891                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1892                                 ret = 1;
1893                         }
1894                 } else {
1895                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1896                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1897                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1898                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1899                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1900                                 ret = 1;
1901                         }
1902                 }
1903         }
1904
1905         return ret;
1906 }
1907 /**
1908  *  verify_xena_quiescence - Checks whether the H/W is ready
1909  *  @val64 :  Value read from adapter status register.
1910  *  @flag : indicates if the adapter enable bit was ever written once
1911  *  before.
1912  *  Description: Returns whether the H/W is ready to go or not. Depending
1913  *  on whether adapter enable bit was written or not the comparison
1914  *  differs and the calling function passes the input argument flag to
1915  *  indicate this.
1916  *  Return: 1 If xena is quiescence
1917  *          0 If Xena is not quiescence
1918  */
1919
1920 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1921 {
1922         int ret = 0, herc;
1923         u64 tmp64 = ~((u64) val64);
1924         int rev_id = get_xena_rev_id(sp->pdev);
1925
1926         herc = (sp->device_type == XFRAME_II_DEVICE);
1927         if (!
1928             (tmp64 &
1929              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1930               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1931               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1932               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1933               ADAPTER_STATUS_P_PLL_LOCK))) {
1934                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1935         }
1936
1937         return ret;
1938 }
1939
1940 /**
1941  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1942  * @sp: Pointer to device specifc structure
1943  * Description :
1944  * New procedure to clear mac address reading  problems on Alpha platforms
1945  *
1946  */
1947
1948 static void fix_mac_address(nic_t * sp)
1949 {
1950         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1951         u64 val64;
1952         int i = 0;
1953
1954         while (fix_mac[i] != END_SIGN) {
1955                 writeq(fix_mac[i++], &bar0->gpio_control);
1956                 udelay(10);
1957                 val64 = readq(&bar0->gpio_control);
1958         }
1959 }
1960
1961 /**
1962  *  start_nic - Turns the device on
1963  *  @nic : device private variable.
1964  *  Description:
1965  *  This function actually turns the device on. Before this  function is
1966  *  called,all Registers are configured from their reset states
1967  *  and shared memory is allocated but the NIC is still quiescent. On
1968  *  calling this function, the device interrupts are cleared and the NIC is
1969  *  literally switched on by writing into the adapter control register.
1970  *  Return Value:
1971  *  SUCCESS on success and -1 on failure.
1972  */
1973
1974 static int start_nic(struct s2io_nic *nic)
1975 {
1976         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1977         struct net_device *dev = nic->dev;
1978         register u64 val64 = 0;
1979         u16 subid, i;
1980         mac_info_t *mac_control;
1981         struct config_param *config;
1982
1983         mac_control = &nic->mac_control;
1984         config = &nic->config;
1985
1986         /*  PRC Initialization and configuration */
1987         for (i = 0; i < config->rx_ring_num; i++) {
1988                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1989                        &bar0->prc_rxd0_n[i]);
1990
1991                 val64 = readq(&bar0->prc_ctrl_n[i]);
1992                 if (nic->config.bimodal)
1993                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1994                 if (nic->rxd_mode == RXD_MODE_1)
1995                         val64 |= PRC_CTRL_RC_ENABLED;
1996                 else
1997                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1998                 if (nic->device_type == XFRAME_II_DEVICE)
1999                         val64 |= PRC_CTRL_GROUP_READS;
2000                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2001                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2002                 writeq(val64, &bar0->prc_ctrl_n[i]);
2003         }
2004
2005         if (nic->rxd_mode == RXD_MODE_3B) {
2006                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2007                 val64 = readq(&bar0->rx_pa_cfg);
2008                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2009                 writeq(val64, &bar0->rx_pa_cfg);
2010         }
2011
2012         /*
2013          * Enabling MC-RLDRAM. After enabling the device, we timeout
2014          * for around 100ms, which is approximately the time required
2015          * for the device to be ready for operation.
2016          */
2017         val64 = readq(&bar0->mc_rldram_mrs);
2018         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2019         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2020         val64 = readq(&bar0->mc_rldram_mrs);
2021
2022         msleep(100);    /* Delay by around 100 ms. */
2023
2024         /* Enabling ECC Protection. */
2025         val64 = readq(&bar0->adapter_control);
2026         val64 &= ~ADAPTER_ECC_EN;
2027         writeq(val64, &bar0->adapter_control);
2028
2029         /*
2030          * Clearing any possible Link state change interrupts that
2031          * could have popped up just before Enabling the card.
2032          */
2033         val64 = readq(&bar0->mac_rmac_err_reg);
2034         if (val64)
2035                 writeq(val64, &bar0->mac_rmac_err_reg);
2036
2037         /*
2038          * Verify if the device is ready to be enabled, if so enable
2039          * it.
2040          */
2041         val64 = readq(&bar0->adapter_status);
2042         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2043                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2044                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2045                           (unsigned long long) val64);
2046                 return FAILURE;
2047         }
2048
2049         /*
2050          * With some switches, link might be already up at this point.
2051          * Because of this weird behavior, when we enable laser,
2052          * we may not get link. We need to handle this. We cannot
2053          * figure out which switch is misbehaving. So we are forced to
2054          * make a global change.
2055          */
2056
2057         /* Enabling Laser. */
2058         val64 = readq(&bar0->adapter_control);
2059         val64 |= ADAPTER_EOI_TX_ON;
2060         writeq(val64, &bar0->adapter_control);
2061
2062         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2063                 /*
2064                  * Dont see link state interrupts initally on some switches,
2065                  * so directly scheduling the link state task here.
2066                  */
2067                 schedule_work(&nic->set_link_task);
2068         }
2069         /* SXE-002: Initialize link and activity LED */
2070         subid = nic->pdev->subsystem_device;
2071         if (((subid & 0xFF) >= 0x07) &&
2072             (nic->device_type == XFRAME_I_DEVICE)) {
2073                 val64 = readq(&bar0->gpio_control);
2074                 val64 |= 0x0000800000000000ULL;
2075                 writeq(val64, &bar0->gpio_control);
2076                 val64 = 0x0411040400000000ULL;
2077                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2078         }
2079
2080         return SUCCESS;
2081 }
2082 /**
2083  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2084  */
2085 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2086 {
2087         nic_t *nic = fifo_data->nic;
2088         struct sk_buff *skb;
2089         TxD_t *txds;
2090         u16 j, frg_cnt;
2091
2092         txds = txdlp;
2093         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2094                 pci_unmap_single(nic->pdev, (dma_addr_t)
2095                         txds->Buffer_Pointer, sizeof(u64),
2096                         PCI_DMA_TODEVICE);
2097                 txds++;
2098         }
2099
2100         skb = (struct sk_buff *) ((unsigned long)
2101                         txds->Host_Control);
2102         if (!skb) {
2103                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2104                 return NULL;
2105         }
2106         pci_unmap_single(nic->pdev, (dma_addr_t)
2107                          txds->Buffer_Pointer,
2108                          skb->len - skb->data_len,
2109                          PCI_DMA_TODEVICE);
2110         frg_cnt = skb_shinfo(skb)->nr_frags;
2111         if (frg_cnt) {
2112                 txds++;
2113                 for (j = 0; j < frg_cnt; j++, txds++) {
2114                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2115                         if (!txds->Buffer_Pointer)
2116                                 break;
2117                         pci_unmap_page(nic->pdev, (dma_addr_t)
2118                                         txds->Buffer_Pointer,
2119                                        frag->size, PCI_DMA_TODEVICE);
2120                 }
2121         }
2122         txdlp->Host_Control = 0;
2123         return(skb);
2124 }
2125
2126 /**
2127  *  free_tx_buffers - Free all queued Tx buffers
2128  *  @nic : device private variable.
2129  *  Description:
2130  *  Free all queued Tx buffers.
2131  *  Return Value: void
2132 */
2133
2134 static void free_tx_buffers(struct s2io_nic *nic)
2135 {
2136         struct net_device *dev = nic->dev;
2137         struct sk_buff *skb;
2138         TxD_t *txdp;
2139         int i, j;
2140         mac_info_t *mac_control;
2141         struct config_param *config;
2142         int cnt = 0;
2143
2144         mac_control = &nic->mac_control;
2145         config = &nic->config;
2146
2147         for (i = 0; i < config->tx_fifo_num; i++) {
2148                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2149                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2150                             list_virt_addr;
2151                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2152                         if (skb) {
2153                                 dev_kfree_skb(skb);
2154                                 cnt++;
2155                         }
2156                 }
2157                 DBG_PRINT(INTR_DBG,
2158                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2159                           dev->name, cnt, i);
2160                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2161                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2162         }
2163 }
2164
2165 /**
2166  *   stop_nic -  To stop the nic
2167  *   @nic ; device private variable.
2168  *   Description:
2169  *   This function does exactly the opposite of what the start_nic()
2170  *   function does. This function is called to stop the device.
2171  *   Return Value:
2172  *   void.
2173  */
2174
2175 static void stop_nic(struct s2io_nic *nic)
2176 {
2177         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2178         register u64 val64 = 0;
2179         u16 interruptible;
2180         mac_info_t *mac_control;
2181         struct config_param *config;
2182
2183         mac_control = &nic->mac_control;
2184         config = &nic->config;
2185
2186         /*  Disable all interrupts */
2187         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2188         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2189         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2190         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2191
2192         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2193         val64 = readq(&bar0->adapter_control);
2194         val64 &= ~(ADAPTER_CNTL_EN);
2195         writeq(val64, &bar0->adapter_control);
2196 }
2197
2198 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2199 {
2200         struct net_device *dev = nic->dev;
2201         struct sk_buff *frag_list;
2202         void *tmp;
2203
2204         /* Buffer-1 receives L3/L4 headers */
2205         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2206                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2207                         PCI_DMA_FROMDEVICE);
2208
2209         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2210         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2211         if (skb_shinfo(skb)->frag_list == NULL) {
2212                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2213                 return -ENOMEM ;
2214         }
2215         frag_list = skb_shinfo(skb)->frag_list;
2216         frag_list->next = NULL;
2217         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2218         frag_list->data = tmp;
2219         frag_list->tail = tmp;
2220
2221         /* Buffer-2 receives L4 data payload */
2222         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2223                                 frag_list->data, dev->mtu,
2224                                 PCI_DMA_FROMDEVICE);
2225         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2226         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2227
2228         return SUCCESS;
2229 }
2230
2231 /**
2232  *  fill_rx_buffers - Allocates the Rx side skbs
2233  *  @nic:  device private variable
2234  *  @ring_no: ring number
2235  *  Description:
2236  *  The function allocates Rx side skbs and puts the physical
2237  *  address of these buffers into the RxD buffer pointers, so that the NIC
2238  *  can DMA the received frame into these locations.
2239  *  The NIC supports 3 receive modes, viz
2240  *  1. single buffer,
2241  *  2. three buffer and
2242  *  3. Five buffer modes.
2243  *  Each mode defines how many fragments the received frame will be split
2244  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2245  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2246  *  is split into 3 fragments. As of now only single buffer mode is
2247  *  supported.
2248  *   Return Value:
2249  *  SUCCESS on success or an appropriate -ve value on failure.
2250  */
2251
2252 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2253 {
2254         struct net_device *dev = nic->dev;
2255         struct sk_buff *skb;
2256         RxD_t *rxdp;
2257         int off, off1, size, block_no, block_no1;
2258         u32 alloc_tab = 0;
2259         u32 alloc_cnt;
2260         mac_info_t *mac_control;
2261         struct config_param *config;
2262         u64 tmp;
2263         buffAdd_t *ba;
2264 #ifndef CONFIG_S2IO_NAPI
2265         unsigned long flags;
2266 #endif
2267         RxD_t *first_rxdp = NULL;
2268
2269         mac_control = &nic->mac_control;
2270         config = &nic->config;
2271         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2272             atomic_read(&nic->rx_bufs_left[ring_no]);
2273
2274         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2275         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2276         while (alloc_tab < alloc_cnt) {
2277                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2278                     block_index;
2279                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2280
2281                 rxdp = mac_control->rings[ring_no].
2282                                 rx_blocks[block_no].rxds[off].virt_addr;
2283
2284                 if ((block_no == block_no1) && (off == off1) &&
2285                                         (rxdp->Host_Control)) {
2286                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2287                                   dev->name);
2288                         DBG_PRINT(INTR_DBG, " info equated\n");
2289                         goto end;
2290                 }
2291                 if (off && (off == rxd_count[nic->rxd_mode])) {
2292                         mac_control->rings[ring_no].rx_curr_put_info.
2293                             block_index++;
2294                         if (mac_control->rings[ring_no].rx_curr_put_info.
2295                             block_index == mac_control->rings[ring_no].
2296                                         block_count)
2297                                 mac_control->rings[ring_no].rx_curr_put_info.
2298                                         block_index = 0;
2299                         block_no = mac_control->rings[ring_no].
2300                                         rx_curr_put_info.block_index;
2301                         if (off == rxd_count[nic->rxd_mode])
2302                                 off = 0;
2303                         mac_control->rings[ring_no].rx_curr_put_info.
2304                                 offset = off;
2305                         rxdp = mac_control->rings[ring_no].
2306                                 rx_blocks[block_no].block_virt_addr;
2307                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2308                                   dev->name, rxdp);
2309                 }
2310 #ifndef CONFIG_S2IO_NAPI
2311                 spin_lock_irqsave(&nic->put_lock, flags);
2312                 mac_control->rings[ring_no].put_pos =
2313                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2314                 spin_unlock_irqrestore(&nic->put_lock, flags);
2315 #endif
2316                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2317                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2318                                 (rxdp->Control_2 & BIT(0)))) {
2319                         mac_control->rings[ring_no].rx_curr_put_info.
2320                                         offset = off;
2321                         goto end;
2322                 }
2323                 /* calculate size of skb based on ring mode */
2324                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2325                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2326                 if (nic->rxd_mode == RXD_MODE_1)
2327                         size += NET_IP_ALIGN;
2328                 else if (nic->rxd_mode == RXD_MODE_3B)
2329                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2330                 else
2331                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2332
2333                 /* allocate skb */
2334                 skb = dev_alloc_skb(size);
2335                 if(!skb) {
2336                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2337                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2338                         if (first_rxdp) {
2339                                 wmb();
2340                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2341                         }
2342                         return -ENOMEM ;
2343                 }
2344                 if (nic->rxd_mode == RXD_MODE_1) {
2345                         /* 1 buffer mode - normal operation mode */
2346                         memset(rxdp, 0, sizeof(RxD1_t));
2347                         skb_reserve(skb, NET_IP_ALIGN);
2348                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2349                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2350                                 PCI_DMA_FROMDEVICE);
2351                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2352
2353                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2354                         /*
2355                          * 2 or 3 buffer mode -
2356                          * Both 2 buffer mode and 3 buffer mode provides 128
2357                          * byte aligned receive buffers.
2358                          *
2359                          * 3 buffer mode provides header separation where in
2360                          * skb->data will have L3/L4 headers where as
2361                          * skb_shinfo(skb)->frag_list will have the L4 data
2362                          * payload
2363                          */
2364
2365                         memset(rxdp, 0, sizeof(RxD3_t));
2366                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2367                         skb_reserve(skb, BUF0_LEN);
2368                         tmp = (u64)(unsigned long) skb->data;
2369                         tmp += ALIGN_SIZE;
2370                         tmp &= ~ALIGN_SIZE;
2371                         skb->data = (void *) (unsigned long)tmp;
2372                         skb->tail = (void *) (unsigned long)tmp;
2373
2374                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2375                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2376                                            PCI_DMA_FROMDEVICE);
2377                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2378                         if (nic->rxd_mode == RXD_MODE_3B) {
2379                                 /* Two buffer mode */
2380
2381                                 /*
2382                                  * Buffer2 will have L3/L4 header plus
2383                                  * L4 payload
2384                                  */
2385                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2386                                 (nic->pdev, skb->data, dev->mtu + 4,
2387                                                 PCI_DMA_FROMDEVICE);
2388
2389                                 /* Buffer-1 will be dummy buffer not used */
2390                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2391                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2392                                         PCI_DMA_FROMDEVICE);
2393                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2394                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2395                                                                 (dev->mtu + 4);
2396                         } else {
2397                                 /* 3 buffer mode */
2398                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2399                                         dev_kfree_skb_irq(skb);
2400                                         if (first_rxdp) {
2401                                                 wmb();
2402                                                 first_rxdp->Control_1 |=
2403                                                         RXD_OWN_XENA;
2404                                         }
2405                                         return -ENOMEM ;
2406                                 }
2407                         }
2408                         rxdp->Control_2 |= BIT(0);
2409                 }
2410                 rxdp->Host_Control = (unsigned long) (skb);
2411                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2412                         rxdp->Control_1 |= RXD_OWN_XENA;
2413                 off++;
2414                 if (off == (rxd_count[nic->rxd_mode] + 1))
2415                         off = 0;
2416                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2417
2418                 rxdp->Control_2 |= SET_RXD_MARKER;
2419                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2420                         if (first_rxdp) {
2421                                 wmb();
2422                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2423                         }
2424                         first_rxdp = rxdp;
2425                 }
2426                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2427                 alloc_tab++;
2428         }
2429
2430       end:
2431         /* Transfer ownership of first descriptor to adapter just before
2432          * exiting. Before that, use memory barrier so that ownership
2433          * and other fields are seen by adapter correctly.
2434          */
2435         if (first_rxdp) {
2436                 wmb();
2437                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2438         }
2439
2440         return SUCCESS;
2441 }
2442
2443 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2444 {
2445         struct net_device *dev = sp->dev;
2446         int j;
2447         struct sk_buff *skb;
2448         RxD_t *rxdp;
2449         mac_info_t *mac_control;
2450         buffAdd_t *ba;
2451
2452         mac_control = &sp->mac_control;
2453         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2454                 rxdp = mac_control->rings[ring_no].
2455                                 rx_blocks[blk].rxds[j].virt_addr;
2456                 skb = (struct sk_buff *)
2457                         ((unsigned long) rxdp->Host_Control);
2458                 if (!skb) {
2459                         continue;
2460                 }
2461                 if (sp->rxd_mode == RXD_MODE_1) {
2462                         pci_unmap_single(sp->pdev, (dma_addr_t)
2463                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2464                                  dev->mtu +
2465                                  HEADER_ETHERNET_II_802_3_SIZE
2466                                  + HEADER_802_2_SIZE +
2467                                  HEADER_SNAP_SIZE,
2468                                  PCI_DMA_FROMDEVICE);
2469                         memset(rxdp, 0, sizeof(RxD1_t));
2470                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2471                         ba = &mac_control->rings[ring_no].
2472                                 ba[blk][j];
2473                         pci_unmap_single(sp->pdev, (dma_addr_t)
2474                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2475                                  BUF0_LEN,
2476                                  PCI_DMA_FROMDEVICE);
2477                         pci_unmap_single(sp->pdev, (dma_addr_t)
2478                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2479                                  BUF1_LEN,
2480                                  PCI_DMA_FROMDEVICE);
2481                         pci_unmap_single(sp->pdev, (dma_addr_t)
2482                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2483                                  dev->mtu + 4,
2484                                  PCI_DMA_FROMDEVICE);
2485                         memset(rxdp, 0, sizeof(RxD3_t));
2486                 } else {
2487                         pci_unmap_single(sp->pdev, (dma_addr_t)
2488                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2489                                 PCI_DMA_FROMDEVICE);
2490                         pci_unmap_single(sp->pdev, (dma_addr_t)
2491                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2492                                 l3l4hdr_size + 4,
2493                                 PCI_DMA_FROMDEVICE);
2494                         pci_unmap_single(sp->pdev, (dma_addr_t)
2495                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2496                                 PCI_DMA_FROMDEVICE);
2497                         memset(rxdp, 0, sizeof(RxD3_t));
2498                 }
2499                 dev_kfree_skb(skb);
2500                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2501         }
2502 }
2503
2504 /**
2505  *  free_rx_buffers - Frees all Rx buffers
2506  *  @sp: device private variable.
2507  *  Description:
2508  *  This function will free all Rx buffers allocated by host.
2509  *  Return Value:
2510  *  NONE.
2511  */
2512
2513 static void free_rx_buffers(struct s2io_nic *sp)
2514 {
2515         struct net_device *dev = sp->dev;
2516         int i, blk = 0, buf_cnt = 0;
2517         mac_info_t *mac_control;
2518         struct config_param *config;
2519
2520         mac_control = &sp->mac_control;
2521         config = &sp->config;
2522
2523         for (i = 0; i < config->rx_ring_num; i++) {
2524                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2525                         free_rxd_blk(sp,i,blk);
2526
2527                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2528                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2529                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2530                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2531                 atomic_set(&sp->rx_bufs_left[i], 0);
2532                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2533                           dev->name, buf_cnt, i);
2534         }
2535 }
2536
2537 /**
2538  * s2io_poll - Rx interrupt handler for NAPI support
2539  * @dev : pointer to the device structure.
2540  * @budget : The number of packets that were budgeted to be processed
2541  * during  one pass through the 'Poll" function.
2542  * Description:
2543  * Comes into picture only if NAPI support has been incorporated. It does
2544  * the same thing that rx_intr_handler does, but not in a interrupt context
2545  * also It will process only a given number of packets.
2546  * Return value:
2547  * 0 on success and 1 if there are No Rx packets to be processed.
2548  */
2549
2550 #if defined(CONFIG_S2IO_NAPI)
2551 static int s2io_poll(struct net_device *dev, int *budget)
2552 {
2553         nic_t *nic = dev->priv;
2554         int pkt_cnt = 0, org_pkts_to_process;
2555         mac_info_t *mac_control;
2556         struct config_param *config;
2557         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2558         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2559         int i;
2560
2561         atomic_inc(&nic->isr_cnt);
2562         mac_control = &nic->mac_control;
2563         config = &nic->config;
2564
2565         nic->pkts_to_process = *budget;
2566         if (nic->pkts_to_process > dev->quota)
2567                 nic->pkts_to_process = dev->quota;
2568         org_pkts_to_process = nic->pkts_to_process;
2569
2570         writeq(val64, &bar0->rx_traffic_int);
2571         val64 = readl(&bar0->rx_traffic_int);
2572
2573         for (i = 0; i < config->rx_ring_num; i++) {
2574                 rx_intr_handler(&mac_control->rings[i]);
2575                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2576                 if (!nic->pkts_to_process) {
2577                         /* Quota for the current iteration has been met */
2578                         goto no_rx;
2579                 }
2580         }
2581         if (!pkt_cnt)
2582                 pkt_cnt = 1;
2583
2584         dev->quota -= pkt_cnt;
2585         *budget -= pkt_cnt;
2586         netif_rx_complete(dev);
2587
2588         for (i = 0; i < config->rx_ring_num; i++) {
2589                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2590                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2591                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2592                         break;
2593                 }
2594         }
2595         /* Re enable the Rx interrupts. */
2596         writeq(0x0, &bar0->rx_traffic_mask);
2597         val64 = readl(&bar0->rx_traffic_mask);
2598         atomic_dec(&nic->isr_cnt);
2599         return 0;
2600
2601 no_rx:
2602         dev->quota -= pkt_cnt;
2603         *budget -= pkt_cnt;
2604
2605         for (i = 0; i < config->rx_ring_num; i++) {
2606                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2607                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2608                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2609                         break;
2610                 }
2611         }
2612         atomic_dec(&nic->isr_cnt);
2613         return 1;
2614 }
2615 #endif
2616
2617 /**
2618  * s2io_netpoll - Rx interrupt service handler for netpoll support
2619  * @dev : pointer to the device structure.
2620  * Description:
2621  * Polling 'interrupt' - used by things like netconsole to send skbs
2622  * without having to re-enable interrupts. It's not called while
2623  * the interrupt routine is executing.
2624  */
2625
2626 #ifdef CONFIG_NET_POLL_CONTROLLER
2627 static void s2io_netpoll(struct net_device *dev)
2628 {
2629         nic_t *nic = dev->priv;
2630         mac_info_t *mac_control;
2631         struct config_param *config;
2632         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2633         u64 val64;
2634         int i;
2635
2636         disable_irq(dev->irq);
2637
2638         atomic_inc(&nic->isr_cnt);
2639         mac_control = &nic->mac_control;
2640         config = &nic->config;
2641
2642         val64 = readq(&bar0->rx_traffic_int);
2643         writeq(val64, &bar0->rx_traffic_int);
2644
2645         for (i = 0; i < config->rx_ring_num; i++)
2646                 rx_intr_handler(&mac_control->rings[i]);
2647
2648         for (i = 0; i < config->rx_ring_num; i++) {
2649                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2650                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2651                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2652                         break;
2653                 }
2654         }
2655         atomic_dec(&nic->isr_cnt);
2656         enable_irq(dev->irq);
2657         return;
2658 }
2659 #endif
2660
2661 /**
2662  *  rx_intr_handler - Rx interrupt handler
2663  *  @nic: device private variable.
2664  *  Description:
2665  *  If the interrupt is because of a received frame or if the
2666  *  receive ring contains fresh as yet un-processed frames,this function is
2667  *  called. It picks out the RxD at which place the last Rx processing had
2668  *  stopped and sends the skb to the OSM's Rx handler and then increments
2669  *  the offset.
2670  *  Return Value:
2671  *  NONE.
2672  */
2673 static void rx_intr_handler(ring_info_t *ring_data)
2674 {
2675         nic_t *nic = ring_data->nic;
2676         struct net_device *dev = (struct net_device *) nic->dev;
2677         int get_block, put_block, put_offset;
2678         rx_curr_get_info_t get_info, put_info;
2679         RxD_t *rxdp;
2680         struct sk_buff *skb;
2681 #ifndef CONFIG_S2IO_NAPI
2682         int pkt_cnt = 0;
2683 #endif
2684         int i;
2685
2686         spin_lock(&nic->rx_lock);
2687         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2688                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2689                           __FUNCTION__, dev->name);
2690                 spin_unlock(&nic->rx_lock);
2691                 return;
2692         }
2693
2694         get_info = ring_data->rx_curr_get_info;
2695         get_block = get_info.block_index;
2696         put_info = ring_data->rx_curr_put_info;
2697         put_block = put_info.block_index;
2698         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2699 #ifndef CONFIG_S2IO_NAPI
2700         spin_lock(&nic->put_lock);
2701         put_offset = ring_data->put_pos;
2702         spin_unlock(&nic->put_lock);
2703 #else
2704         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2705                 put_info.offset;
2706 #endif
2707         while (RXD_IS_UP2DT(rxdp)) {
2708                 /* If your are next to put index then it's FIFO full condition */
2709                 if ((get_block == put_block) &&
2710                     (get_info.offset + 1) == put_info.offset) {
2711                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2712                         break;
2713                 }
2714                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2715                 if (skb == NULL) {
2716                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2717                                   dev->name);
2718                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2719                         spin_unlock(&nic->rx_lock);
2720                         return;
2721                 }
2722                 if (nic->rxd_mode == RXD_MODE_1) {
2723                         pci_unmap_single(nic->pdev, (dma_addr_t)
2724                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2725                                  dev->mtu +
2726                                  HEADER_ETHERNET_II_802_3_SIZE +
2727                                  HEADER_802_2_SIZE +
2728                                  HEADER_SNAP_SIZE,
2729                                  PCI_DMA_FROMDEVICE);
2730                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2731                         pci_unmap_single(nic->pdev, (dma_addr_t)
2732                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2733                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2734                         pci_unmap_single(nic->pdev, (dma_addr_t)
2735                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2736                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2737                         pci_unmap_single(nic->pdev, (dma_addr_t)
2738                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2739                                  dev->mtu + 4,
2740                                  PCI_DMA_FROMDEVICE);
2741                 } else {
2742                         pci_unmap_single(nic->pdev, (dma_addr_t)
2743                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2744                                          PCI_DMA_FROMDEVICE);
2745                         pci_unmap_single(nic->pdev, (dma_addr_t)
2746                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2747                                          l3l4hdr_size + 4,
2748                                          PCI_DMA_FROMDEVICE);
2749                         pci_unmap_single(nic->pdev, (dma_addr_t)
2750                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2751                                          dev->mtu, PCI_DMA_FROMDEVICE);
2752                 }
2753                 prefetch(skb->data);
2754                 rx_osm_handler(ring_data, rxdp);
2755                 get_info.offset++;
2756                 ring_data->rx_curr_get_info.offset = get_info.offset;
2757                 rxdp = ring_data->rx_blocks[get_block].
2758                                 rxds[get_info.offset].virt_addr;
2759                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2760                         get_info.offset = 0;
2761                         ring_data->rx_curr_get_info.offset = get_info.offset;
2762                         get_block++;
2763                         if (get_block == ring_data->block_count)
2764                                 get_block = 0;
2765                         ring_data->rx_curr_get_info.block_index = get_block;
2766                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2767                 }
2768
2769 #ifdef CONFIG_S2IO_NAPI
2770                 nic->pkts_to_process -= 1;
2771                 if (!nic->pkts_to_process)
2772                         break;
2773 #else
2774                 pkt_cnt++;
2775                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2776                         break;
2777 #endif
2778         }
2779         if (nic->lro) {
2780                 /* Clear all LRO sessions before exiting */
2781                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2782                         lro_t *lro = &nic->lro0_n[i];
2783                         if (lro->in_use) {
2784                                 update_L3L4_header(nic, lro);
2785                                 queue_rx_frame(lro->parent);
2786                                 clear_lro_session(lro);
2787                         }
2788                 }
2789         }
2790
2791         spin_unlock(&nic->rx_lock);
2792 }
2793
2794 /**
2795  *  tx_intr_handler - Transmit interrupt handler
2796  *  @nic : device private variable
2797  *  Description:
2798  *  If an interrupt was raised to indicate DMA complete of the
2799  *  Tx packet, this function is called. It identifies the last TxD
2800  *  whose buffer was freed and frees all skbs whose data have already
2801  *  DMA'ed into the NICs internal memory.
2802  *  Return Value:
2803  *  NONE
2804  */
2805
2806 static void tx_intr_handler(fifo_info_t *fifo_data)
2807 {
2808         nic_t *nic = fifo_data->nic;
2809         struct net_device *dev = (struct net_device *) nic->dev;
2810         tx_curr_get_info_t get_info, put_info;
2811         struct sk_buff *skb;
2812         TxD_t *txdlp;
2813
2814         get_info = fifo_data->tx_curr_get_info;
2815         put_info = fifo_data->tx_curr_put_info;
2816         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2817             list_virt_addr;
2818         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2819                (get_info.offset != put_info.offset) &&
2820                (txdlp->Host_Control)) {
2821                 /* Check for TxD errors */
2822                 if (txdlp->Control_1 & TXD_T_CODE) {
2823                         unsigned long long err;
2824                         err = txdlp->Control_1 & TXD_T_CODE;
2825                         if (err & 0x1) {
2826                                 nic->mac_control.stats_info->sw_stat.
2827                                                 parity_err_cnt++;
2828                         }
2829                         if ((err >> 48) == 0xA) {
2830                                 DBG_PRINT(TX_DBG, "TxD returned due \
2831 to loss of link\n");
2832                         }
2833                         else {
2834                                 DBG_PRINT(ERR_DBG, "***TxD error \
2835 %llx\n", err);
2836                         }
2837                 }
2838
2839                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2840                 if (skb == NULL) {
2841                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2842                         __FUNCTION__);
2843                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2844                         return;
2845                 }
2846
2847                 /* Updating the statistics block */
2848                 nic->stats.tx_bytes += skb->len;
2849                 dev_kfree_skb_irq(skb);
2850
2851                 get_info.offset++;
2852                 if (get_info.offset == get_info.fifo_len + 1)
2853                         get_info.offset = 0;
2854                 txdlp = (TxD_t *) fifo_data->list_info
2855                     [get_info.offset].list_virt_addr;
2856                 fifo_data->tx_curr_get_info.offset =
2857                     get_info.offset;
2858         }
2859
2860         spin_lock(&nic->tx_lock);
2861         if (netif_queue_stopped(dev))
2862                 netif_wake_queue(dev);
2863         spin_unlock(&nic->tx_lock);
2864 }
2865
2866 /**
2867  *  s2io_mdio_write - Function to write in to MDIO registers
2868  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2869  *  @addr     : address value
2870  *  @value    : data value
2871  *  @dev      : pointer to net_device structure
2872  *  Description:
2873  *  This function is used to write values to the MDIO registers
2874  *  NONE
2875  */
2876 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2877 {
2878         u64 val64 = 0x0;
2879         nic_t *sp = dev->priv;
2880         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2881
2882         //address transaction
2883         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2884                         | MDIO_MMD_DEV_ADDR(mmd_type)
2885                         | MDIO_MMS_PRT_ADDR(0x0);
2886         writeq(val64, &bar0->mdio_control);
2887         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2888         writeq(val64, &bar0->mdio_control);
2889         udelay(100);
2890
2891         //Data transaction
2892         val64 = 0x0;
2893         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2894                         | MDIO_MMD_DEV_ADDR(mmd_type)
2895                         | MDIO_MMS_PRT_ADDR(0x0)
2896                         | MDIO_MDIO_DATA(value)
2897                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2898         writeq(val64, &bar0->mdio_control);
2899         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2900         writeq(val64, &bar0->mdio_control);
2901         udelay(100);
2902
2903         val64 = 0x0;
2904         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2905         | MDIO_MMD_DEV_ADDR(mmd_type)
2906         | MDIO_MMS_PRT_ADDR(0x0)
2907         | MDIO_OP(MDIO_OP_READ_TRANS);
2908         writeq(val64, &bar0->mdio_control);
2909         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2910         writeq(val64, &bar0->mdio_control);
2911         udelay(100);
2912
2913 }
2914
2915 /**
2916  *  s2io_mdio_read - Function to write in to MDIO registers
2917  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2918  *  @addr     : address value
2919  *  @dev      : pointer to net_device structure
2920  *  Description:
2921  *  This function is used to read values to the MDIO registers
2922  *  NONE
2923  */
2924 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2925 {
2926         u64 val64 = 0x0;
2927         u64 rval64 = 0x0;
2928         nic_t *sp = dev->priv;
2929         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2930
2931         /* address transaction */
2932         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2933                         | MDIO_MMD_DEV_ADDR(mmd_type)
2934                         | MDIO_MMS_PRT_ADDR(0x0);
2935         writeq(val64, &bar0->mdio_control);
2936         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2937         writeq(val64, &bar0->mdio_control);
2938         udelay(100);
2939
2940         /* Data transaction */
2941         val64 = 0x0;
2942         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2943                         | MDIO_MMD_DEV_ADDR(mmd_type)
2944                         | MDIO_MMS_PRT_ADDR(0x0)
2945                         | MDIO_OP(MDIO_OP_READ_TRANS);
2946         writeq(val64, &bar0->mdio_control);
2947         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2948         writeq(val64, &bar0->mdio_control);
2949         udelay(100);
2950
2951         /* Read the value from regs */
2952         rval64 = readq(&bar0->mdio_control);
2953         rval64 = rval64 & 0xFFFF0000;
2954         rval64 = rval64 >> 16;
2955         return rval64;
2956 }
2957 /**
2958  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2959  *  @counter      : couter value to be updated
2960  *  @flag         : flag to indicate the status
2961  *  @type         : counter type
2962  *  Description:
2963  *  This function is to check the status of the xpak counters value
2964  *  NONE
2965  */
2966
2967 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2968 {
2969         u64 mask = 0x3;
2970         u64 val64;
2971         int i;
2972         for(i = 0; i <index; i++)
2973                 mask = mask << 0x2;
2974
2975         if(flag > 0)
2976         {
2977                 *counter = *counter + 1;
2978                 val64 = *regs_stat & mask;
2979                 val64 = val64 >> (index * 0x2);
2980                 val64 = val64 + 1;
2981                 if(val64 == 3)
2982                 {
2983                         switch(type)
2984                         {
2985                         case 1:
2986                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2987                                           "service. Excessive temperatures may "
2988                                           "result in premature transceiver "
2989                                           "failure \n");
2990                         break;
2991                         case 2:
2992                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2993                                           "service Excessive bias currents may "
2994                                           "indicate imminent laser diode "
2995                                           "failure \n");
2996                         break;
2997                         case 3:
2998                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2999                                           "service Excessive laser output "
3000                                           "power may saturate far-end "
3001                                           "receiver\n");
3002                         break;
3003                         default:
3004                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3005                                           "type \n");
3006                         }
3007                         val64 = 0x0;
3008                 }
3009                 val64 = val64 << (index * 0x2);
3010                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3011
3012         } else {
3013                 *regs_stat = *regs_stat & (~mask);
3014         }
3015 }
3016
3017 /**
3018  *  s2io_updt_xpak_counter - Function to update the xpak counters
3019  *  @dev         : pointer to net_device struct
3020  *  Description:
3021  *  This function is to upate the status of the xpak counters value
3022  *  NONE
3023  */
3024 static void s2io_updt_xpak_counter(struct net_device *dev)
3025 {
3026         u16 flag  = 0x0;
3027         u16 type  = 0x0;
3028         u16 val16 = 0x0;
3029         u64 val64 = 0x0;
3030         u64 addr  = 0x0;
3031
3032         nic_t *sp = dev->priv;
3033         StatInfo_t *stat_info = sp->mac_control.stats_info;
3034
3035         /* Check the communication with the MDIO slave */
3036         addr = 0x0000;
3037         val64 = 0x0;
3038         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3039         if((val64 == 0xFFFF) || (val64 == 0x0000))
3040         {
3041                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3042                           "Returned %llx\n", (unsigned long long)val64);
3043                 return;
3044         }
3045
3046         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3047         if(val64 != 0x2040)
3048         {
3049                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3050                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3051                           (unsigned long long)val64);
3052                 return;
3053         }
3054
3055         /* Loading the DOM register to MDIO register */
3056         addr = 0xA100;
3057         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3058         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3059
3060         /* Reading the Alarm flags */
3061         addr = 0xA070;
3062         val64 = 0x0;
3063         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3064
3065         flag = CHECKBIT(val64, 0x7);
3066         type = 1;
3067         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3068                                 &stat_info->xpak_stat.xpak_regs_stat,
3069                                 0x0, flag, type);
3070
3071         if(CHECKBIT(val64, 0x6))
3072                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3073
3074         flag = CHECKBIT(val64, 0x3);
3075         type = 2;
3076         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3077                                 &stat_info->xpak_stat.xpak_regs_stat,
3078                                 0x2, flag, type);
3079
3080         if(CHECKBIT(val64, 0x2))
3081                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3082
3083         flag = CHECKBIT(val64, 0x1);
3084         type = 3;
3085         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3086                                 &stat_info->xpak_stat.xpak_regs_stat,
3087                                 0x4, flag, type);
3088
3089         if(CHECKBIT(val64, 0x0))
3090                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3091
3092         /* Reading the Warning flags */
3093         addr = 0xA074;
3094         val64 = 0x0;
3095         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3096
3097         if(CHECKBIT(val64, 0x7))
3098                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3099
3100         if(CHECKBIT(val64, 0x6))
3101                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3102
3103         if(CHECKBIT(val64, 0x3))
3104                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3105
3106         if(CHECKBIT(val64, 0x2))
3107                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3108
3109         if(CHECKBIT(val64, 0x1))
3110                 stat_info->xpak_stat.warn_laser_output_power_high++;
3111
3112         if(CHECKBIT(val64, 0x0))
3113                 stat_info->xpak_stat.warn_laser_output_power_low++;
3114 }
3115
3116 /**
3117  *  alarm_intr_handler - Alarm Interrrupt handler
3118  *  @nic: device private variable
3119  *  Description: If the interrupt was neither because of Rx packet or Tx
3120  *  complete, this function is called. If the interrupt was to indicate
3121  *  a loss of link, the OSM link status handler is invoked for any other
3122  *  alarm interrupt the block that raised the interrupt is displayed
3123  *  and a H/W reset is issued.
3124  *  Return Value:
3125  *  NONE
3126 */
3127
3128 static void alarm_intr_handler(struct s2io_nic *nic)
3129 {
3130         struct net_device *dev = (struct net_device *) nic->dev;
3131         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3132         register u64 val64 = 0, err_reg = 0;
3133         u64 cnt;
3134         int i;
3135         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3136         /* Handling the XPAK counters update */
3137         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3138                 /* waiting for an hour */
3139                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3140         } else {
3141                 s2io_updt_xpak_counter(dev);
3142                 /* reset the count to zero */
3143                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3144         }
3145
3146         /* Handling link status change error Intr */
3147         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3148                 err_reg = readq(&bar0->mac_rmac_err_reg);
3149                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3150                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3151                         schedule_work(&nic->set_link_task);
3152                 }
3153         }
3154
3155         /* Handling Ecc errors */
3156         val64 = readq(&bar0->mc_err_reg);
3157         writeq(val64, &bar0->mc_err_reg);
3158         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3159                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3160                         nic->mac_control.stats_info->sw_stat.
3161                                 double_ecc_errs++;
3162                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3163                                   dev->name);
3164                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3165                         if (nic->device_type != XFRAME_II_DEVICE) {
3166                                 /* Reset XframeI only if critical error */
3167                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3168                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3169                                         netif_stop_queue(dev);
3170                                         schedule_work(&nic->rst_timer_task);
3171                                         nic->mac_control.stats_info->sw_stat.
3172                                                         soft_reset_cnt++;
3173                                 }
3174                         }
3175                 } else {
3176                         nic->mac_control.stats_info->sw_stat.
3177                                 single_ecc_errs++;
3178                 }
3179         }
3180
3181         /* In case of a serious error, the device will be Reset. */
3182         val64 = readq(&bar0->serr_source);
3183         if (val64 & SERR_SOURCE_ANY) {
3184                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3185                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3186                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3187                           (unsigned long long)val64);
3188                 netif_stop_queue(dev);
3189                 schedule_work(&nic->rst_timer_task);
3190                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3191         }
3192
3193         /*
3194          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3195          * Error occurs, the adapter will be recycled by disabling the
3196          * adapter enable bit and enabling it again after the device
3197          * becomes Quiescent.
3198          */
3199         val64 = readq(&bar0->pcc_err_reg);
3200         writeq(val64, &bar0->pcc_err_reg);
3201         if (val64 & PCC_FB_ECC_DB_ERR) {
3202                 u64 ac = readq(&bar0->adapter_control);
3203                 ac &= ~(ADAPTER_CNTL_EN);
3204                 writeq(ac, &bar0->adapter_control);
3205                 ac = readq(&bar0->adapter_control);
3206                 schedule_work(&nic->set_link_task);
3207         }
3208         /* Check for data parity error */
3209         val64 = readq(&bar0->pic_int_status);
3210         if (val64 & PIC_INT_GPIO) {
3211                 val64 = readq(&bar0->gpio_int_reg);
3212                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3213                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3214                         schedule_work(&nic->rst_timer_task);
3215                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3216                 }
3217         }
3218
3219         /* Check for ring full counter */
3220         if (nic->device_type & XFRAME_II_DEVICE) {
3221                 val64 = readq(&bar0->ring_bump_counter1);
3222                 for (i=0; i<4; i++) {
3223                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3224                         cnt >>= 64 - ((i+1)*16);
3225                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3226                                 += cnt;
3227                 }
3228
3229                 val64 = readq(&bar0->ring_bump_counter2);
3230                 for (i=0; i<4; i++) {
3231                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3232                         cnt >>= 64 - ((i+1)*16);
3233                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3234                                 += cnt;
3235                 }
3236         }
3237
3238         /* Other type of interrupts are not being handled now,  TODO */
3239 }
3240
3241 /**
3242  *  wait_for_cmd_complete - waits for a command to complete.
3243  *  @sp : private member of the device structure, which is a pointer to the
3244  *  s2io_nic structure.
3245  *  Description: Function that waits for a command to Write into RMAC
3246  *  ADDR DATA registers to be completed and returns either success or
3247  *  error depending on whether the command was complete or not.
3248  *  Return value:
3249  *   SUCCESS on success and FAILURE on failure.
3250  */
3251
3252 static int wait_for_cmd_complete(void *addr, u64 busy_bit)
3253 {
3254         int ret = FAILURE, cnt = 0;
3255         u64 val64;
3256
3257         while (TRUE) {
3258                 val64 = readq(addr);
3259                 if (!(val64 & busy_bit)) {
3260                         ret = SUCCESS;
3261                         break;
3262                 }
3263
3264                 if(in_interrupt())
3265                         mdelay(50);
3266                 else
3267                         msleep(50);
3268
3269                 if (cnt++ > 10)
3270                         break;
3271         }
3272         return ret;
3273 }
3274
3275 /**
3276  *  s2io_reset - Resets the card.
3277  *  @sp : private member of the device structure.
3278  *  Description: Function to Reset the card. This function then also
3279  *  restores the previously saved PCI configuration space registers as
3280  *  the card reset also resets the configuration space.
3281  *  Return value:
3282  *  void.
3283  */
3284
3285 static void s2io_reset(nic_t * sp)
3286 {
3287         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3288         u64 val64;
3289         u16 subid, pci_cmd;
3290
3291         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3292         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3293
3294         val64 = SW_RESET_ALL;
3295         writeq(val64, &bar0->sw_reset);
3296
3297         /*
3298          * At this stage, if the PCI write is indeed completed, the
3299          * card is reset and so is the PCI Config space of the device.
3300          * So a read cannot be issued at this stage on any of the
3301          * registers to ensure the write into "sw_reset" register
3302          * has gone through.
3303          * Question: Is there any system call that will explicitly force
3304          * all the write commands still pending on the bus to be pushed
3305          * through?
3306          * As of now I'am just giving a 250ms delay and hoping that the
3307          * PCI write to sw_reset register is done by this time.
3308          */
3309         msleep(250);
3310         if (strstr(sp->product_name, "CX4")) {
3311                 msleep(750);
3312         }
3313
3314         /* Restore the PCI state saved during initialization. */
3315         pci_restore_state(sp->pdev);
3316         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3317                                      pci_cmd);
3318         s2io_init_pci(sp);
3319
3320         msleep(250);
3321
3322         /* Set swapper to enable I/O register access */
3323         s2io_set_swapper(sp);
3324
3325         /* Restore the MSIX table entries from local variables */
3326         restore_xmsi_data(sp);
3327
3328         /* Clear certain PCI/PCI-X fields after reset */
3329         if (sp->device_type == XFRAME_II_DEVICE) {
3330                 /* Clear parity err detect bit */
3331                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3332
3333                 /* Clearing PCIX Ecc status register */
3334                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3335
3336                 /* Clearing PCI_STATUS error reflected here */
3337                 writeq(BIT(62), &bar0->txpic_int_reg);
3338         }
3339
3340         /* Reset device statistics maintained by OS */
3341         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3342
3343         /* SXE-002: Configure link and activity LED to turn it off */
3344         subid = sp->pdev->subsystem_device;
3345         if (((subid & 0xFF) >= 0x07) &&
3346             (sp->device_type == XFRAME_I_DEVICE)) {
3347                 val64 = readq(&bar0->gpio_control);
3348                 val64 |= 0x0000800000000000ULL;
3349                 writeq(val64, &bar0->gpio_control);
3350                 val64 = 0x0411040400000000ULL;
3351                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3352         }
3353
3354         /*
3355          * Clear spurious ECC interrupts that would have occured on
3356          * XFRAME II cards after reset.
3357          */
3358         if (sp->device_type == XFRAME_II_DEVICE) {
3359                 val64 = readq(&bar0->pcc_err_reg);
3360                 writeq(val64, &bar0->pcc_err_reg);
3361         }
3362
3363         sp->device_enabled_once = FALSE;
3364 }
3365
3366 /**
3367  *  s2io_set_swapper - to set the swapper controle on the card
3368  *  @sp : private member of the device structure,
3369  *  pointer to the s2io_nic structure.
3370  *  Description: Function to set the swapper control on the card
3371  *  correctly depending on the 'endianness' of the system.
3372  *  Return value:
3373  *  SUCCESS on success and FAILURE on failure.
3374  */
3375
3376 static int s2io_set_swapper(nic_t * sp)
3377 {
3378         struct net_device *dev = sp->dev;
3379         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3380         u64 val64, valt, valr;
3381
3382         /*
3383          * Set proper endian settings and verify the same by reading
3384          * the PIF Feed-back register.
3385          */
3386
3387         val64 = readq(&bar0->pif_rd_swapper_fb);
3388         if (val64 != 0x0123456789ABCDEFULL) {
3389                 int i = 0;
3390                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3391                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3392                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3393                                 0};                     /* FE=0, SE=0 */
3394
3395                 while(i<4) {
3396                         writeq(value[i], &bar0->swapper_ctrl);
3397                         val64 = readq(&bar0->pif_rd_swapper_fb);
3398                         if (val64 == 0x0123456789ABCDEFULL)
3399                                 break;
3400                         i++;
3401                 }
3402                 if (i == 4) {
3403                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3404                                 dev->name);
3405                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3406                                 (unsigned long long) val64);
3407                         return FAILURE;
3408                 }
3409                 valr = value[i];
3410         } else {
3411                 valr = readq(&bar0->swapper_ctrl);
3412         }
3413
3414         valt = 0x0123456789ABCDEFULL;
3415         writeq(valt, &bar0->xmsi_address);
3416         val64 = readq(&bar0->xmsi_address);
3417
3418         if(val64 != valt) {
3419                 int i = 0;
3420                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3421                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3422                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3423                                 0};                     /* FE=0, SE=0 */
3424
3425                 while(i<4) {
3426                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3427                         writeq(valt, &bar0->xmsi_address);
3428                         val64 = readq(&bar0->xmsi_address);
3429                         if(val64 == valt)
3430                                 break;
3431                         i++;
3432                 }
3433                 if(i == 4) {
3434                         unsigned long long x = val64;
3435                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3436                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3437                         return FAILURE;
3438                 }
3439         }
3440         val64 = readq(&bar0->swapper_ctrl);
3441         val64 &= 0xFFFF000000000000ULL;
3442
3443 #ifdef  __BIG_ENDIAN
3444         /*
3445          * The device by default set to a big endian format, so a
3446          * big endian driver need not set anything.
3447          */
3448         val64 |= (SWAPPER_CTRL_TXP_FE |
3449                  SWAPPER_CTRL_TXP_SE |
3450                  SWAPPER_CTRL_TXD_R_FE |
3451                  SWAPPER_CTRL_TXD_W_FE |
3452                  SWAPPER_CTRL_TXF_R_FE |
3453                  SWAPPER_CTRL_RXD_R_FE |
3454                  SWAPPER_CTRL_RXD_W_FE |
3455                  SWAPPER_CTRL_RXF_W_FE |
3456                  SWAPPER_CTRL_XMSI_FE |
3457                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3458         if (sp->intr_type == INTA)
3459                 val64 |= SWAPPER_CTRL_XMSI_SE;
3460         writeq(val64, &bar0->swapper_ctrl);
3461 #else
3462         /*
3463          * Initially we enable all bits to make it accessible by the
3464          * driver, then we selectively enable only those bits that
3465          * we want to set.
3466          */
3467         val64 |= (SWAPPER_CTRL_TXP_FE |
3468                  SWAPPER_CTRL_TXP_SE |
3469                  SWAPPER_CTRL_TXD_R_FE |
3470                  SWAPPER_CTRL_TXD_R_SE |
3471                  SWAPPER_CTRL_TXD_W_FE |
3472                  SWAPPER_CTRL_TXD_W_SE |
3473                  SWAPPER_CTRL_TXF_R_FE |
3474                  SWAPPER_CTRL_RXD_R_FE |
3475                  SWAPPER_CTRL_RXD_R_SE |
3476                  SWAPPER_CTRL_RXD_W_FE |
3477                  SWAPPER_CTRL_RXD_W_SE |
3478                  SWAPPER_CTRL_RXF_W_FE |
3479                  SWAPPER_CTRL_XMSI_FE |
3480                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3481         if (sp->intr_type == INTA)
3482                 val64 |= SWAPPER_CTRL_XMSI_SE;
3483         writeq(val64, &bar0->swapper_ctrl);
3484 #endif
3485         val64 = readq(&bar0->swapper_ctrl);
3486
3487         /*
3488          * Verifying if endian settings are accurate by reading a
3489          * feedback register.
3490          */
3491         val64 = readq(&bar0->pif_rd_swapper_fb);
3492         if (val64 != 0x0123456789ABCDEFULL) {
3493                 /* Endian settings are incorrect, calls for another dekko. */
3494                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3495                           dev->name);
3496                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3497                           (unsigned long long) val64);
3498                 return FAILURE;
3499         }
3500
3501         return SUCCESS;
3502 }
3503
3504 static int wait_for_msix_trans(nic_t *nic, int i)
3505 {
3506         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3507         u64 val64;
3508         int ret = 0, cnt = 0;
3509
3510         do {
3511                 val64 = readq(&bar0->xmsi_access);
3512                 if (!(val64 & BIT(15)))
3513                         break;
3514                 mdelay(1);
3515                 cnt++;
3516         } while(cnt < 5);
3517         if (cnt == 5) {
3518                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3519                 ret = 1;
3520         }
3521
3522         return ret;
3523 }
3524
3525 static void restore_xmsi_data(nic_t *nic)
3526 {
3527         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3528         u64 val64;
3529         int i;
3530
3531         for (i=0; i< nic->avail_msix_vectors; i++) {
3532                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3533                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3534                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3535                 writeq(val64, &bar0->xmsi_access);
3536                 if (wait_for_msix_trans(nic, i)) {
3537                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3538                         continue;
3539                 }
3540         }
3541 }
3542
3543 static void store_xmsi_data(nic_t *nic)
3544 {
3545         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3546         u64 val64, addr, data;
3547         int i;
3548
3549         /* Store and display */
3550         for (i=0; i< nic->avail_msix_vectors; i++) {
3551                 val64 = (BIT(15) | vBIT(i, 26, 6));
3552                 writeq(val64, &bar0->xmsi_access);
3553                 if (wait_for_msix_trans(nic, i)) {
3554                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3555                         continue;
3556                 }
3557                 addr = readq(&bar0->xmsi_address);
3558                 data = readq(&bar0->xmsi_data);
3559                 if (addr && data) {
3560                         nic->msix_info[i].addr = addr;
3561                         nic->msix_info[i].data = data;
3562                 }
3563         }
3564 }
3565
3566 int s2io_enable_msi(nic_t *nic)
3567 {
3568         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3569         u16 msi_ctrl, msg_val;
3570         struct config_param *config = &nic->config;
3571         struct net_device *dev = nic->dev;
3572         u64 val64, tx_mat, rx_mat;
3573         int i, err;
3574
3575         val64 = readq(&bar0->pic_control);
3576         val64 &= ~BIT(1);
3577         writeq(val64, &bar0->pic_control);
3578
3579         err = pci_enable_msi(nic->pdev);
3580         if (err) {
3581                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3582                           nic->dev->name);
3583                 return err;
3584         }
3585
3586         /*
3587          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3588          * for interrupt handling.
3589          */
3590         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3591         msg_val ^= 0x1;
3592         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3593         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3594
3595         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3596         msi_ctrl |= 0x10;
3597         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3598
3599         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3600         tx_mat = readq(&bar0->tx_mat0_n[0]);
3601         for (i=0; i<config->tx_fifo_num; i++) {
3602                 tx_mat |= TX_MAT_SET(i, 1);
3603         }
3604         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3605
3606         rx_mat = readq(&bar0->rx_mat);
3607         for (i=0; i<config->rx_ring_num; i++) {
3608                 rx_mat |= RX_MAT_SET(i, 1);
3609         }
3610         writeq(rx_mat, &bar0->rx_mat);
3611
3612         dev->irq = nic->pdev->irq;
3613         return 0;
3614 }
3615
3616 static int s2io_enable_msi_x(nic_t *nic)
3617 {
3618         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3619         u64 tx_mat, rx_mat;
3620         u16 msi_control; /* Temp variable */
3621         int ret, i, j, msix_indx = 1;
3622
3623         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3624                                GFP_KERNEL);
3625         if (nic->entries == NULL) {
3626                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3627                 return -ENOMEM;
3628         }
3629         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3630
3631         nic->s2io_entries =
3632                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3633                                    GFP_KERNEL);
3634         if (nic->s2io_entries == NULL) {
3635                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3636                 kfree(nic->entries);
3637                 return -ENOMEM;
3638         }
3639         memset(nic->s2io_entries, 0,
3640                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3641
3642         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3643                 nic->entries[i].entry = i;
3644                 nic->s2io_entries[i].entry = i;
3645                 nic->s2io_entries[i].arg = NULL;
3646                 nic->s2io_entries[i].in_use = 0;
3647         }
3648
3649         tx_mat = readq(&bar0->tx_mat0_n[0]);
3650         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3651                 tx_mat |= TX_MAT_SET(i, msix_indx);
3652                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3653                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3654                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3655         }
3656         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3657
3658         if (!nic->config.bimodal) {
3659                 rx_mat = readq(&bar0->rx_mat);
3660                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3661                         rx_mat |= RX_MAT_SET(j, msix_indx);
3662                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3663                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3664                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3665                 }
3666                 writeq(rx_mat, &bar0->rx_mat);
3667         } else {
3668                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3669                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3670                         tx_mat |= TX_MAT_SET(i, msix_indx);
3671                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3672                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3673                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3674                 }
3675                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3676         }
3677
3678         nic->avail_msix_vectors = 0;
3679         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3680         /* We fail init if error or we get less vectors than min required */
3681         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3682                 nic->avail_msix_vectors = ret;
3683                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3684         }
3685         if (ret) {
3686                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3687                 kfree(nic->entries);
3688                 kfree(nic->s2io_entries);
3689                 nic->entries = NULL;
3690                 nic->s2io_entries = NULL;
3691                 nic->avail_msix_vectors = 0;
3692                 return -ENOMEM;
3693         }
3694         if (!nic->avail_msix_vectors)
3695                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3696
3697         /*
3698          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3699          * in the herc NIC. (Temp change, needs to be removed later)
3700          */
3701         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3702         msi_control |= 0x1; /* Enable MSI */
3703         pci_write_config_word(nic->pdev, 0x42, msi_control);
3704
3705         return 0;
3706 }
3707
3708 /* ********************************************************* *
3709  * Functions defined below concern the OS part of the driver *
3710  * ********************************************************* */
3711
3712 /**
3713  *  s2io_open - open entry point of the driver
3714  *  @dev : pointer to the device structure.
3715  *  Description:
3716  *  This function is the open entry point of the driver. It mainly calls a
3717  *  function to allocate Rx buffers and inserts them into the buffer
3718  *  descriptors and then enables the Rx part of the NIC.
3719  *  Return value:
3720  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3721  *   file on failure.
3722  */
3723
3724 static int s2io_open(struct net_device *dev)
3725 {
3726         nic_t *sp = dev->priv;
3727         int err = 0;
3728
3729         /*
3730          * Make sure you have link off by default every time
3731          * Nic is initialized
3732          */
3733         netif_carrier_off(dev);
3734         sp->last_link_state = 0;
3735
3736         /* Initialize H/W and enable interrupts */
3737         err = s2io_card_up(sp);
3738         if (err) {
3739                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3740                           dev->name);
3741                 goto hw_init_failed;
3742         }
3743
3744         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3745                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3746                 s2io_card_down(sp);
3747                 err = -ENODEV;
3748                 goto hw_init_failed;
3749         }
3750
3751         netif_start_queue(dev);
3752         return 0;
3753
3754 hw_init_failed:
3755         if (sp->intr_type == MSI_X) {
3756                 if (sp->entries)
3757                         kfree(sp->entries);
3758                 if (sp->s2io_entries)
3759                         kfree(sp->s2io_entries);
3760         }
3761         return err;
3762 }
3763
3764 /**
3765  *  s2io_close -close entry point of the driver
3766  *  @dev : device pointer.
3767  *  Description:
3768  *  This is the stop entry point of the driver. It needs to undo exactly
3769  *  whatever was done by the open entry point,thus it's usually referred to
3770  *  as the close function.Among other things this function mainly stops the
3771  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3772  *  Return value:
3773  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3774  *  file on failure.
3775  */
3776
3777 static int s2io_close(struct net_device *dev)
3778 {
3779         nic_t *sp = dev->priv;
3780
3781         flush_scheduled_work();
3782         netif_stop_queue(dev);
3783         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3784         s2io_card_down(sp);
3785
3786         sp->device_close_flag = TRUE;   /* Device is shut down. */
3787         return 0;
3788 }
3789
3790 /**
3791  *  s2io_xmit - Tx entry point of te driver
3792  *  @skb : the socket buffer containing the Tx data.
3793  *  @dev : device pointer.
3794  *  Description :
3795  *  This function is the Tx entry point of the driver. S2IO NIC supports
3796  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3797  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3798  *  not be upadted.
3799  *  Return value:
3800  *  0 on success & 1 on failure.
3801  */
3802
3803 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3804 {
3805         nic_t *sp = dev->priv;
3806         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3807         register u64 val64;
3808         TxD_t *txdp;
3809         TxFIFO_element_t __iomem *tx_fifo;
3810         unsigned long flags;
3811 #ifdef NETIF_F_TSO
3812         int mss;
3813 #endif
3814         u16 vlan_tag = 0;
3815         int vlan_priority = 0;
3816         mac_info_t *mac_control;
3817         struct config_param *config;
3818
3819         mac_control = &sp->mac_control;
3820         config = &sp->config;
3821
3822         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3823         spin_lock_irqsave(&sp->tx_lock, flags);
3824         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3825                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3826                           dev->name);
3827                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3828                 dev_kfree_skb(skb);
3829                 return 0;
3830         }
3831
3832         queue = 0;
3833
3834         /* Get Fifo number to Transmit based on vlan priority */
3835         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3836                 vlan_tag = vlan_tx_tag_get(skb);
3837                 vlan_priority = vlan_tag >> 13;
3838                 queue = config->fifo_mapping[vlan_priority];
3839         }
3840
3841         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3842         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3843         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3844                 list_virt_addr;
3845
3846         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3847         /* Avoid "put" pointer going beyond "get" pointer */
3848         if (txdp->Host_Control ||
3849                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3850                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3851                 netif_stop_queue(dev);
3852                 dev_kfree_skb(skb);
3853                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3854                 return 0;
3855         }
3856
3857         /* A buffer with no data will be dropped */
3858         if (!skb->len) {
3859                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3860                 dev_kfree_skb(skb);
3861                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3862                 return 0;
3863         }
3864
3865         txdp->Control_1 = 0;
3866         txdp->Control_2 = 0;
3867 #ifdef NETIF_F_TSO
3868         mss = skb_shinfo(skb)->gso_size;
3869         if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3870                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3871                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3872         }
3873 #endif
3874         if (skb->ip_summed == CHECKSUM_HW) {
3875                 txdp->Control_2 |=
3876                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3877                      TXD_TX_CKO_UDP_EN);
3878         }
3879         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3880         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3881         txdp->Control_2 |= config->tx_intr_type;
3882
3883         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3884                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3885                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3886         }
3887
3888         frg_len = skb->len - skb->data_len;
3889         if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP) {
3890                 int ufo_size;
3891
3892                 ufo_size = skb_shinfo(skb)->gso_size;
3893                 ufo_size &= ~7;
3894                 txdp->Control_1 |= TXD_UFO_EN;
3895                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3896                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3897 #ifdef __BIG_ENDIAN
3898                 sp->ufo_in_band_v[put_off] =
3899                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3900 #else
3901                 sp->ufo_in_band_v[put_off] =
3902                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3903 #endif
3904                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3905                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3906                                         sp->ufo_in_band_v,
3907                                         sizeof(u64), PCI_DMA_TODEVICE);
3908                 txdp++;
3909                 txdp->Control_1 = 0;
3910                 txdp->Control_2 = 0;
3911         }
3912
3913         txdp->Buffer_Pointer = pci_map_single
3914             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3915         txdp->Host_Control = (unsigned long) skb;
3916         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3917
3918         if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
3919                 txdp->Control_1 |= TXD_UFO_EN;
3920
3921         frg_cnt = skb_shinfo(skb)->nr_frags;
3922         /* For fragmented SKB. */
3923         for (i = 0; i < frg_cnt; i++) {
3924                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3925                 /* A '0' length fragment will be ignored */
3926                 if (!frag->size)
3927                         continue;
3928                 txdp++;
3929                 txdp->Buffer_Pointer = (u64) pci_map_page
3930                     (sp->pdev, frag->page, frag->page_offset,
3931                      frag->size, PCI_DMA_TODEVICE);
3932                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3933                 if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
3934                         txdp->Control_1 |= TXD_UFO_EN;
3935         }
3936         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3937
3938         if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
3939                 frg_cnt++; /* as Txd0 was used for inband header */
3940
3941         tx_fifo = mac_control->tx_FIFO_start[queue];
3942         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3943         writeq(val64, &tx_fifo->TxDL_Pointer);
3944
3945         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3946                  TX_FIFO_LAST_LIST);
3947
3948 #ifdef NETIF_F_TSO
3949         if (mss)
3950                 val64 |= TX_FIFO_SPECIAL_FUNC;
3951 #endif
3952         if (skb_shinfo(skb)->gso_type == SKB_GSO_UDP)
3953                 val64 |= TX_FIFO_SPECIAL_FUNC;
3954         writeq(val64, &tx_fifo->List_Control);
3955
3956         mmiowb();
3957
3958         put_off++;
3959         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3960                 put_off = 0;
3961         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3962
3963         /* Avoid "put" pointer going beyond "get" pointer */
3964         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3965                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
3966                 DBG_PRINT(TX_DBG,
3967                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3968                           put_off, get_off);
3969                 netif_stop_queue(dev);
3970         }
3971
3972         dev->trans_start = jiffies;
3973         spin_unlock_irqrestore(&sp->tx_lock, flags);
3974
3975         return 0;
3976 }
3977
3978 static void
3979 s2io_alarm_handle(unsigned long data)
3980 {
3981         nic_t *sp = (nic_t *)data;
3982
3983         alarm_intr_handler(sp);
3984         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3985 }
3986
3987 static irqreturn_t
3988 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3989 {
3990         struct net_device *dev = (struct net_device *) dev_id;
3991         nic_t *sp = dev->priv;
3992         int i;
3993         int ret;
3994         mac_info_t *mac_control;
3995         struct config_param *config;
3996
3997         atomic_inc(&sp->isr_cnt);
3998         mac_control = &sp->mac_control;
3999         config = &sp->config;
4000         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4001
4002         /* If Intr is because of Rx Traffic */
4003         for (i = 0; i < config->rx_ring_num; i++)
4004                 rx_intr_handler(&mac_control->rings[i]);
4005
4006         /* If Intr is because of Tx Traffic */
4007         for (i = 0; i < config->tx_fifo_num; i++)
4008                 tx_intr_handler(&mac_control->fifos[i]);
4009
4010         /*
4011          * If the Rx buffer count is below the panic threshold then
4012          * reallocate the buffers from the interrupt handler itself,
4013          * else schedule a tasklet to reallocate the buffers.
4014          */
4015         for (i = 0; i < config->rx_ring_num; i++) {
4016                 if (!sp->lro) {
4017                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
4018                         int level = rx_buffer_level(sp, rxb_size, i);
4019
4020                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
4021                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
4022                                                         dev->name);
4023                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4024                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
4025                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
4026                                                   dev->name);
4027                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
4028                                         clear_bit(0, (&sp->tasklet_status));
4029                                         atomic_dec(&sp->isr_cnt);
4030                                         return IRQ_HANDLED;
4031                                 }
4032                                 clear_bit(0, (&sp->tasklet_status));
4033                         } else if (level == LOW) {
4034                                 tasklet_schedule(&sp->task);
4035                         }
4036                 }
4037                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
4038                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4039                                                         dev->name);
4040                                 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4041                                 break;
4042                 }
4043         }
4044
4045         atomic_dec(&sp->isr_cnt);
4046         return IRQ_HANDLED;
4047 }
4048
4049 static irqreturn_t
4050 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
4051 {
4052         ring_info_t *ring = (ring_info_t *)dev_id;
4053         nic_t *sp = ring->nic;
4054         struct net_device *dev = (struct net_device *) dev_id;
4055         int rxb_size, level, rng_n;
4056
4057         atomic_inc(&sp->isr_cnt);
4058         rx_intr_handler(ring);
4059
4060         rng_n = ring->ring_no;
4061         if (!sp->lro) {
4062                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4063                 level = rx_buffer_level(sp, rxb_size, rng_n);
4064
4065                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4066                         int ret;
4067                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4068                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4069                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4070                                 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4071                                           __FUNCTION__);
4072                                 clear_bit(0, (&sp->tasklet_status));
4073                                 return IRQ_HANDLED;
4074                         }
4075                         clear_bit(0, (&sp->tasklet_status));
4076                 } else if (level == LOW) {
4077                         tasklet_schedule(&sp->task);
4078                 }
4079         }
4080         else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4081                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
4082                         DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4083         }
4084
4085         atomic_dec(&sp->isr_cnt);
4086
4087         return IRQ_HANDLED;
4088 }
4089
4090 static irqreturn_t
4091 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
4092 {
4093         fifo_info_t *fifo = (fifo_info_t *)dev_id;
4094         nic_t *sp = fifo->nic;
4095
4096         atomic_inc(&sp->isr_cnt);
4097         tx_intr_handler(fifo);
4098         atomic_dec(&sp->isr_cnt);
4099         return IRQ_HANDLED;
4100 }
4101 static void s2io_txpic_intr_handle(nic_t *sp)
4102 {
4103         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4104         u64 val64;
4105
4106         val64 = readq(&bar0->pic_int_status);
4107         if (val64 & PIC_INT_GPIO) {
4108                 val64 = readq(&bar0->gpio_int_reg);
4109                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4110                     (val64 & GPIO_INT_REG_LINK_UP)) {
4111                         /*
4112                          * This is unstable state so clear both up/down
4113                          * interrupt and adapter to re-evaluate the link state.
4114                          */
4115                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4116                         val64 |= GPIO_INT_REG_LINK_UP;
4117                         writeq(val64, &bar0->gpio_int_reg);
4118                         val64 = readq(&bar0->gpio_int_mask);
4119                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4120                                    GPIO_INT_MASK_LINK_DOWN);
4121                         writeq(val64, &bar0->gpio_int_mask);
4122                 }
4123                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4124                         val64 = readq(&bar0->adapter_status);
4125                         if (verify_xena_quiescence(sp, val64,
4126                                                    sp->device_enabled_once)) {
4127                                 /* Enable Adapter */
4128                                 val64 = readq(&bar0->adapter_control);
4129                                 val64 |= ADAPTER_CNTL_EN;
4130                                 writeq(val64, &bar0->adapter_control);
4131                                 val64 |= ADAPTER_LED_ON;
4132                                 writeq(val64, &bar0->adapter_control);
4133                                 if (!sp->device_enabled_once)
4134                                         sp->device_enabled_once = 1;
4135
4136                                 s2io_link(sp, LINK_UP);
4137                                 /*
4138                                  * unmask link down interrupt and mask link-up
4139                                  * intr
4140                                  */
4141                                 val64 = readq(&bar0->gpio_int_mask);
4142                                 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4143                                 val64 |= GPIO_INT_MASK_LINK_UP;
4144                                 writeq(val64, &bar0->gpio_int_mask);
4145
4146                         }
4147                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4148                         val64 = readq(&bar0->adapter_status);
4149                         if (verify_xena_quiescence(sp, val64,
4150                                                    sp->device_enabled_once)) {
4151                                 s2io_link(sp, LINK_DOWN);
4152                                 /* Link is down so unmaks link up interrupt */
4153                                 val64 = readq(&bar0->gpio_int_mask);
4154                                 val64 &= ~GPIO_INT_MASK_LINK_UP;
4155                                 val64 |= GPIO_INT_MASK_LINK_DOWN;
4156                                 writeq(val64, &bar0->gpio_int_mask);
4157                         }
4158                 }
4159         }
4160         val64 = readq(&bar0->gpio_int_mask);
4161 }
4162
4163 /**
4164  *  s2io_isr - ISR handler of the device .
4165  *  @irq: the irq of the device.
4166  *  @dev_id: a void pointer to the dev structure of the NIC.
4167  *  @pt_regs: pointer to the registers pushed on the stack.
4168  *  Description:  This function is the ISR handler of the device. It
4169  *  identifies the reason for the interrupt and calls the relevant
4170  *  service routines. As a contongency measure, this ISR allocates the
4171  *  recv buffers, if their numbers are below the panic value which is
4172  *  presently set to 25% of the original number of rcv buffers allocated.
4173  *  Return value:
4174  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4175  *   IRQ_NONE: will be returned if interrupt is not from our device
4176  */
4177 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
4178 {
4179         struct net_device *dev = (struct net_device *) dev_id;
4180         nic_t *sp = dev->priv;
4181         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4182         int i;
4183         u64 reason = 0, val64, org_mask;
4184         mac_info_t *mac_control;
4185         struct config_param *config;
4186
4187         atomic_inc(&sp->isr_cnt);
4188         mac_control = &sp->mac_control;
4189         config = &sp->config;
4190
4191         /*
4192          * Identify the cause for interrupt and call the appropriate
4193          * interrupt handler. Causes for the interrupt could be;
4194          * 1. Rx of packet.
4195          * 2. Tx complete.
4196          * 3. Link down.
4197          * 4. Error in any functional blocks of the NIC.
4198          */
4199         reason = readq(&bar0->general_int_status);
4200
4201         if (!reason) {
4202                 /* The interrupt was not raised by Xena. */
4203                 atomic_dec(&sp->isr_cnt);
4204                 return IRQ_NONE;
4205         }
4206
4207         val64 = 0xFFFFFFFFFFFFFFFFULL;
4208         /* Store current mask before masking all interrupts */
4209         org_mask = readq(&bar0->general_int_mask);
4210         writeq(val64, &bar0->general_int_mask);
4211
4212 #ifdef CONFIG_S2IO_NAPI
4213         if (reason & GEN_INTR_RXTRAFFIC) {
4214                 if (netif_rx_schedule_prep(dev)) {
4215                         writeq(val64, &bar0->rx_traffic_mask);
4216                         __netif_rx_schedule(dev);
4217                 }
4218         }
4219 #else
4220         /*
4221          * Rx handler is called by default, without checking for the
4222          * cause of interrupt.
4223          * rx_traffic_int reg is an R1 register, writing all 1's
4224          * will ensure that the actual interrupt causing bit get's
4225          * cleared and hence a read can be avoided.
4226          */
4227         writeq(val64, &bar0->rx_traffic_int);
4228         for (i = 0; i < config->rx_ring_num; i++) {
4229                 rx_intr_handler(&mac_control->rings[i]);
4230         }
4231 #endif
4232
4233         /*
4234          * tx_traffic_int reg is an R1 register, writing all 1's
4235          * will ensure that the actual interrupt causing bit get's
4236          * cleared and hence a read can be avoided.
4237          */
4238         writeq(val64, &bar0->tx_traffic_int);
4239
4240         for (i = 0; i < config->tx_fifo_num; i++)
4241                 tx_intr_handler(&mac_control->fifos[i]);
4242
4243         if (reason & GEN_INTR_TXPIC)
4244                 s2io_txpic_intr_handle(sp);
4245         /*
4246          * If the Rx buffer count is below the panic threshold then
4247          * reallocate the buffers from the interrupt handler itself,
4248          * else schedule a tasklet to reallocate the buffers.
4249          */
4250 #ifndef CONFIG_S2IO_NAPI
4251         for (i = 0; i < config->rx_ring_num; i++) {
4252                 if (!sp->lro) {
4253                         int ret;
4254                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
4255                         int level = rx_buffer_level(sp, rxb_size, i);
4256
4257                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
4258                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
4259                                                         dev->name);
4260                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4261                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
4262                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
4263                                                   dev->name);
4264                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
4265                                         clear_bit(0, (&sp->tasklet_status));
4266                                         atomic_dec(&sp->isr_cnt);
4267                                         writeq(org_mask, &bar0->general_int_mask);
4268                                         return IRQ_HANDLED;
4269                                 }
4270                                 clear_bit(0, (&sp->tasklet_status));
4271                         } else if (level == LOW) {
4272                                 tasklet_schedule(&sp->task);
4273                         }
4274                 }
4275                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
4276                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
4277                                                         dev->name);
4278                                 DBG_PRINT(ERR_DBG, " in Rx intr!!\n");
4279                                 break;
4280                 }
4281         }
4282 #endif
4283         writeq(org_mask, &bar0->general_int_mask);
4284         atomic_dec(&sp->isr_cnt);
4285         return IRQ_HANDLED;
4286 }
4287
4288 /**
4289  * s2io_updt_stats -
4290  */
4291 static void s2io_updt_stats(nic_t *sp)
4292 {
4293         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4294         u64 val64;
4295         int cnt = 0;
4296
4297         if (atomic_read(&sp->card_state) == CARD_UP) {
4298                 /* Apprx 30us on a 133 MHz bus */
4299                 val64 = SET_UPDT_CLICKS(10) |
4300                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4301                 writeq(val64, &bar0->stat_cfg);
4302                 do {
4303                         udelay(100);
4304                         val64 = readq(&bar0->stat_cfg);
4305                         if (!(val64 & BIT(0)))
4306                                 break;
4307                         cnt++;
4308                         if (cnt == 5)
4309                                 break; /* Updt failed */
4310                 } while(1);
4311         }
4312 }
4313
4314 /**
4315  *  s2io_get_stats - Updates the device statistics structure.
4316  *  @dev : pointer to the device structure.
4317  *  Description:
4318  *  This function updates the device statistics structure in the s2io_nic
4319  *  structure and returns a pointer to the same.
4320  *  Return value:
4321  *  pointer to the updated net_device_stats structure.
4322  */
4323
4324 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4325 {
4326         nic_t *sp = dev->priv;
4327         mac_info_t *mac_control;
4328         struct config_param *config;
4329
4330
4331         mac_control = &sp->mac_control;
4332         config = &sp->config;
4333
4334         /* Configure Stats for immediate updt */
4335         s2io_updt_stats(sp);
4336
4337         sp->stats.tx_packets =
4338                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4339         sp->stats.tx_errors =
4340                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4341         sp->stats.rx_errors =
4342                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
4343         sp->stats.multicast =
4344                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4345         sp->stats.rx_length_errors =
4346                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
4347
4348         return (&sp->stats);
4349 }
4350
4351 /**
4352  *  s2io_set_multicast - entry point for multicast address enable/disable.
4353  *  @dev : pointer to the device structure
4354  *  Description:
4355  *  This function is a driver entry point which gets called by the kernel
4356  *  whenever multicast addresses must be enabled/disabled. This also gets
4357  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4358  *  determine, if multicast address must be enabled or if promiscuous mode
4359  *  is to be disabled etc.
4360  *  Return value:
4361  *  void.
4362  */
4363
4364 static void s2io_set_multicast(struct net_device *dev)
4365 {
4366         int i, j, prev_cnt;
4367         struct dev_mc_list *mclist;
4368         nic_t *sp = dev->priv;
4369         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4370         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4371             0xfeffffffffffULL;
4372         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4373         void __iomem *add;
4374
4375         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4376                 /*  Enable all Multicast addresses */
4377                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4378                        &bar0->rmac_addr_data0_mem);
4379                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4380                        &bar0->rmac_addr_data1_mem);
4381                 val64 = RMAC_ADDR_CMD_MEM_WE |
4382                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4383                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4384                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4385                 /* Wait till command completes */
4386                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4387                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4388
4389                 sp->m_cast_flg = 1;
4390                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4391         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4392                 /*  Disable all Multicast addresses */
4393                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4394                        &bar0->rmac_addr_data0_mem);
4395                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4396                        &bar0->rmac_addr_data1_mem);
4397                 val64 = RMAC_ADDR_CMD_MEM_WE |
4398                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4399                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4400                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4401                 /* Wait till command completes */
4402                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4403                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4404
4405                 sp->m_cast_flg = 0;
4406                 sp->all_multi_pos = 0;
4407         }
4408
4409         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4410                 /*  Put the NIC into promiscuous mode */
4411                 add = &bar0->mac_cfg;
4412                 val64 = readq(&bar0->mac_cfg);
4413                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4414
4415                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4416                 writel((u32) val64, add);
4417                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4418                 writel((u32) (val64 >> 32), (add + 4));
4419
4420                 val64 = readq(&bar0->mac_cfg);
4421                 sp->promisc_flg = 1;
4422                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4423                           dev->name);
4424         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4425                 /*  Remove the NIC from promiscuous mode */
4426                 add = &bar0->mac_cfg;
4427                 val64 = readq(&bar0->mac_cfg);
4428                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4429
4430                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4431                 writel((u32) val64, add);
4432                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4433                 writel((u32) (val64 >> 32), (add + 4));
4434
4435                 val64 = readq(&bar0->mac_cfg);
4436                 sp->promisc_flg = 0;
4437                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4438                           dev->name);
4439         }
4440
4441         /*  Update individual M_CAST address list */
4442         if ((!sp->m_cast_flg) && dev->mc_count) {
4443                 if (dev->mc_count >
4444                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4445                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4446                                   dev->name);
4447                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4448                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4449                         return;
4450                 }
4451
4452                 prev_cnt = sp->mc_addr_count;
4453                 sp->mc_addr_count = dev->mc_count;
4454
4455                 /* Clear out the previous list of Mc in the H/W. */
4456                 for (i = 0; i < prev_cnt; i++) {
4457                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4458                                &bar0->rmac_addr_data0_mem);
4459                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4460                                 &bar0->rmac_addr_data1_mem);
4461                         val64 = RMAC_ADDR_CMD_MEM_WE |
4462                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4463                             RMAC_ADDR_CMD_MEM_OFFSET
4464                             (MAC_MC_ADDR_START_OFFSET + i);
4465                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4466
4467                         /* Wait for command completes */
4468                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4469                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4470                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4471                                           dev->name);
4472                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4473                                 return;
4474                         }
4475                 }
4476
4477                 /* Create the new Rx filter list and update the same in H/W. */
4478                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4479                      i++, mclist = mclist->next) {
4480                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4481                                ETH_ALEN);
4482                         mac_addr = 0;
4483                         for (j = 0; j < ETH_ALEN; j++) {
4484                                 mac_addr |= mclist->dmi_addr[j];
4485                                 mac_addr <<= 8;
4486                         }
4487                         mac_addr >>= 8;
4488                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4489                                &bar0->rmac_addr_data0_mem);
4490                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4491                                 &bar0->rmac_addr_data1_mem);
4492                         val64 = RMAC_ADDR_CMD_MEM_WE |
4493                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4494                             RMAC_ADDR_CMD_MEM_OFFSET
4495                             (i + MAC_MC_ADDR_START_OFFSET);
4496                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4497
4498                         /* Wait for command completes */
4499                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4500                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4501                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4502                                           dev->name);
4503                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4504                                 return;
4505                         }
4506                 }
4507         }
4508 }
4509
4510 /**
4511  *  s2io_set_mac_addr - Programs the Xframe mac address
4512  *  @dev : pointer to the device structure.
4513  *  @addr: a uchar pointer to the new mac address which is to be set.
4514  *  Description : This procedure will program the Xframe to receive
4515  *  frames with new Mac Address
4516  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4517  *  as defined in errno.h file on failure.
4518  */
4519
4520 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4521 {
4522         nic_t *sp = dev->priv;
4523         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4524         register u64 val64, mac_addr = 0;
4525         int i;
4526
4527         /*
4528          * Set the new MAC address as the new unicast filter and reflect this
4529          * change on the device address registered with the OS. It will be
4530          * at offset 0.
4531          */
4532         for (i = 0; i < ETH_ALEN; i++) {
4533                 mac_addr <<= 8;
4534                 mac_addr |= addr[i];
4535         }
4536
4537         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4538                &bar0->rmac_addr_data0_mem);
4539
4540         val64 =
4541             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4542             RMAC_ADDR_CMD_MEM_OFFSET(0);
4543         writeq(val64, &bar0->rmac_addr_cmd_mem);
4544         /* Wait till command completes */
4545         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4546                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4547                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4548                 return FAILURE;
4549         }
4550
4551         return SUCCESS;
4552 }
4553
4554 /**
4555  * s2io_ethtool_sset - Sets different link parameters.
4556  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4557  * @info: pointer to the structure with parameters given by ethtool to set
4558  * link information.
4559  * Description:
4560  * The function sets different link parameters provided by the user onto
4561  * the NIC.
4562  * Return value:
4563  * 0 on success.
4564 */
4565
4566 static int s2io_ethtool_sset(struct net_device *dev,
4567                              struct ethtool_cmd *info)
4568 {
4569         nic_t *sp = dev->priv;
4570         if ((info->autoneg == AUTONEG_ENABLE) ||
4571             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4572                 return -EINVAL;
4573         else {
4574                 s2io_close(sp->dev);
4575                 s2io_open(sp->dev);
4576         }
4577
4578         return 0;
4579 }
4580
4581 /**
4582  * s2io_ethtol_gset - Return link specific information.
4583  * @sp : private member of the device structure, pointer to the
4584  *      s2io_nic structure.
4585  * @info : pointer to the structure with parameters given by ethtool
4586  * to return link information.
4587  * Description:
4588  * Returns link specific information like speed, duplex etc.. to ethtool.
4589  * Return value :
4590  * return 0 on success.
4591  */
4592
4593 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4594 {
4595         nic_t *sp = dev->priv;
4596         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4597         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4598         info->port = PORT_FIBRE;
4599         /* info->transceiver?? TODO */
4600
4601         if (netif_carrier_ok(sp->dev)) {
4602                 info->speed = 10000;
4603                 info->duplex = DUPLEX_FULL;
4604         } else {
4605                 info->speed = -1;
4606                 info->duplex = -1;
4607         }
4608
4609         info->autoneg = AUTONEG_DISABLE;
4610         return 0;
4611 }
4612
4613 /**
4614  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4615  * @sp : private member of the device structure, which is a pointer to the
4616  * s2io_nic structure.
4617  * @info : pointer to the structure with parameters given by ethtool to
4618  * return driver information.
4619  * Description:
4620  * Returns driver specefic information like name, version etc.. to ethtool.
4621  * Return value:
4622  *  void
4623  */
4624
4625 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4626                                   struct ethtool_drvinfo *info)
4627 {
4628         nic_t *sp = dev->priv;
4629
4630         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4631         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4632         strncpy(info->fw_version, "", sizeof(info->fw_version));
4633         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4634         info->regdump_len = XENA_REG_SPACE;
4635         info->eedump_len = XENA_EEPROM_SPACE;
4636         info->testinfo_len = S2IO_TEST_LEN;
4637         info->n_stats = S2IO_STAT_LEN;
4638 }
4639
4640 /**
4641  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4642  *  @sp: private member of the device structure, which is a pointer to the
4643  *  s2io_nic structure.
4644  *  @regs : pointer to the structure with parameters given by ethtool for
4645  *  dumping the registers.
4646  *  @reg_space: The input argumnet into which all the registers are dumped.
4647  *  Description:
4648  *  Dumps the entire register space of xFrame NIC into the user given
4649  *  buffer area.
4650  * Return value :
4651  * void .
4652 */
4653
4654 static void s2io_ethtool_gregs(struct net_device *dev,
4655                                struct ethtool_regs *regs, void *space)
4656 {
4657         int i;
4658         u64 reg;
4659         u8 *reg_space = (u8 *) space;
4660         nic_t *sp = dev->priv;
4661
4662         regs->len = XENA_REG_SPACE;
4663         regs->version = sp->pdev->subsystem_device;
4664
4665         for (i = 0; i < regs->len; i += 8) {
4666                 reg = readq(sp->bar0 + i);
4667                 memcpy((reg_space + i), &reg, 8);
4668         }
4669 }
4670
4671 /**
4672  *  s2io_phy_id  - timer function that alternates adapter LED.
4673  *  @data : address of the private member of the device structure, which
4674  *  is a pointer to the s2io_nic structure, provided as an u32.
4675  * Description: This is actually the timer function that alternates the
4676  * adapter LED bit of the adapter control bit to set/reset every time on
4677  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4678  *  once every second.
4679 */
4680 static void s2io_phy_id(unsigned long data)
4681 {
4682         nic_t *sp = (nic_t *) data;
4683         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4684         u64 val64 = 0;
4685         u16 subid;
4686
4687         subid = sp->pdev->subsystem_device;
4688         if ((sp->device_type == XFRAME_II_DEVICE) ||
4689                    ((subid & 0xFF) >= 0x07)) {
4690                 val64 = readq(&bar0->gpio_control);
4691                 val64 ^= GPIO_CTRL_GPIO_0;
4692                 writeq(val64, &bar0->gpio_control);
4693         } else {
4694                 val64 = readq(&bar0->adapter_control);
4695                 val64 ^= ADAPTER_LED_ON;
4696                 writeq(val64, &bar0->adapter_control);
4697         }
4698
4699         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4700 }
4701
4702 /**
4703  * s2io_ethtool_idnic - To physically identify the nic on the system.
4704  * @sp : private member of the device structure, which is a pointer to the
4705  * s2io_nic structure.
4706  * @id : pointer to the structure with identification parameters given by
4707  * ethtool.
4708  * Description: Used to physically identify the NIC on the system.
4709  * The Link LED will blink for a time specified by the user for
4710  * identification.
4711  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4712  * identification is possible only if it's link is up.
4713  * Return value:
4714  * int , returns 0 on success
4715  */
4716
4717 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4718 {
4719         u64 val64 = 0, last_gpio_ctrl_val;
4720         nic_t *sp = dev->priv;
4721         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4722         u16 subid;
4723
4724         subid = sp->pdev->subsystem_device;
4725         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4726         if ((sp->device_type == XFRAME_I_DEVICE) &&
4727                 ((subid & 0xFF) < 0x07)) {
4728                 val64 = readq(&bar0->adapter_control);
4729                 if (!(val64 & ADAPTER_CNTL_EN)) {
4730                         printk(KERN_ERR
4731                                "Adapter Link down, cannot blink LED\n");
4732                         return -EFAULT;
4733                 }
4734         }
4735         if (sp->id_timer.function == NULL) {
4736                 init_timer(&sp->id_timer);
4737                 sp->id_timer.function = s2io_phy_id;
4738                 sp->id_timer.data = (unsigned long) sp;
4739         }
4740         mod_timer(&sp->id_timer, jiffies);
4741         if (data)
4742                 msleep_interruptible(data * HZ);
4743         else
4744                 msleep_interruptible(MAX_FLICKER_TIME);
4745         del_timer_sync(&sp->id_timer);
4746
4747         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4748                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4749                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4750         }
4751
4752         return 0;
4753 }
4754
4755 /**
4756  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4757  * @sp : private member of the device structure, which is a pointer to the
4758  *      s2io_nic structure.
4759  * @ep : pointer to the structure with pause parameters given by ethtool.
4760  * Description:
4761  * Returns the Pause frame generation and reception capability of the NIC.
4762  * Return value:
4763  *  void
4764  */
4765 static void s2io_ethtool_getpause_data(struct net_device *dev,
4766                                        struct ethtool_pauseparam *ep)
4767 {
4768         u64 val64;
4769         nic_t *sp = dev->priv;
4770         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4771
4772         val64 = readq(&bar0->rmac_pause_cfg);
4773         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4774                 ep->tx_pause = TRUE;
4775         if (val64 & RMAC_PAUSE_RX_ENABLE)
4776                 ep->rx_pause = TRUE;
4777         ep->autoneg = FALSE;
4778 }
4779
4780 /**
4781  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4782  * @sp : private member of the device structure, which is a pointer to the
4783  *      s2io_nic structure.
4784  * @ep : pointer to the structure with pause parameters given by ethtool.
4785  * Description:
4786  * It can be used to set or reset Pause frame generation or reception
4787  * support of the NIC.
4788  * Return value:
4789  * int, returns 0 on Success
4790  */
4791
4792 static int s2io_ethtool_setpause_data(struct net_device *dev,
4793                                struct ethtool_pauseparam *ep)
4794 {
4795         u64 val64;
4796         nic_t *sp = dev->priv;
4797         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4798
4799         val64 = readq(&bar0->rmac_pause_cfg);
4800         if (ep->tx_pause)
4801                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4802         else
4803                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4804         if (ep->rx_pause)
4805                 val64 |= RMAC_PAUSE_RX_ENABLE;
4806         else
4807                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4808         writeq(val64, &bar0->rmac_pause_cfg);
4809         return 0;
4810 }
4811
4812 /**
4813  * read_eeprom - reads 4 bytes of data from user given offset.
4814  * @sp : private member of the device structure, which is a pointer to the
4815  *      s2io_nic structure.
4816  * @off : offset at which the data must be written
4817  * @data : Its an output parameter where the data read at the given
4818  *      offset is stored.
4819  * Description:
4820  * Will read 4 bytes of data from the user given offset and return the
4821  * read data.
4822  * NOTE: Will allow to read only part of the EEPROM visible through the
4823  *   I2C bus.
4824  * Return value:
4825  *  -1 on failure and 0 on success.
4826  */
4827
4828 #define S2IO_DEV_ID             5
4829 static int read_eeprom(nic_t * sp, int off, u64 * data)
4830 {
4831         int ret = -1;
4832         u32 exit_cnt = 0;
4833         u64 val64;
4834         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4835
4836         if (sp->device_type == XFRAME_I_DEVICE) {
4837                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4838                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4839                     I2C_CONTROL_CNTL_START;
4840                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4841
4842                 while (exit_cnt < 5) {
4843                         val64 = readq(&bar0->i2c_control);
4844                         if (I2C_CONTROL_CNTL_END(val64)) {
4845                                 *data = I2C_CONTROL_GET_DATA(val64);
4846                                 ret = 0;
4847                                 break;
4848                         }
4849                         msleep(50);
4850                         exit_cnt++;
4851                 }
4852         }
4853
4854         if (sp->device_type == XFRAME_II_DEVICE) {
4855                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4856                         SPI_CONTROL_BYTECNT(0x3) |
4857                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4858                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4859                 val64 |= SPI_CONTROL_REQ;
4860                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4861                 while (exit_cnt < 5) {
4862                         val64 = readq(&bar0->spi_control);
4863                         if (val64 & SPI_CONTROL_NACK) {
4864                                 ret = 1;
4865                                 break;
4866                         } else if (val64 & SPI_CONTROL_DONE) {
4867                                 *data = readq(&bar0->spi_data);
4868                                 *data &= 0xffffff;
4869                                 ret = 0;
4870                                 break;
4871                         }
4872                         msleep(50);
4873                         exit_cnt++;
4874                 }
4875         }
4876         return ret;
4877 }
4878
4879 /**
4880  *  write_eeprom - actually writes the relevant part of the data value.
4881  *  @sp : private member of the device structure, which is a pointer to the
4882  *       s2io_nic structure.
4883  *  @off : offset at which the data must be written
4884  *  @data : The data that is to be written
4885  *  @cnt : Number of bytes of the data that are actually to be written into
4886  *  the Eeprom. (max of 3)
4887  * Description:
4888  *  Actually writes the relevant part of the data value into the Eeprom
4889  *  through the I2C bus.
4890  * Return value:
4891  *  0 on success, -1 on failure.
4892  */
4893
4894 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4895 {
4896         int exit_cnt = 0, ret = -1;
4897         u64 val64;
4898         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4899
4900         if (sp->device_type == XFRAME_I_DEVICE) {
4901                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4902                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4903                     I2C_CONTROL_CNTL_START;
4904                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4905
4906                 while (exit_cnt < 5) {
4907                         val64 = readq(&bar0->i2c_control);
4908                         if (I2C_CONTROL_CNTL_END(val64)) {
4909                                 if (!(val64 & I2C_CONTROL_NACK))
4910                                         ret = 0;
4911                                 break;
4912                         }
4913                         msleep(50);
4914                         exit_cnt++;
4915                 }
4916         }
4917
4918         if (sp->device_type == XFRAME_II_DEVICE) {
4919                 int write_cnt = (cnt == 8) ? 0 : cnt;
4920                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4921
4922                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4923                         SPI_CONTROL_BYTECNT(write_cnt) |
4924                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4925                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4926                 val64 |= SPI_CONTROL_REQ;
4927                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4928                 while (exit_cnt < 5) {
4929                         val64 = readq(&bar0->spi_control);
4930                         if (val64 & SPI_CONTROL_NACK) {
4931                                 ret = 1;
4932                                 break;
4933                         } else if (val64 & SPI_CONTROL_DONE) {
4934                                 ret = 0;
4935                                 break;
4936                         }
4937                         msleep(50);
4938                         exit_cnt++;
4939                 }
4940         }
4941         return ret;
4942 }
4943 static void s2io_vpd_read(nic_t *nic)
4944 {
4945         u8 vpd_data[256],data;
4946         int i=0, cnt, fail = 0;
4947         int vpd_addr = 0x80;
4948
4949         if (nic->device_type == XFRAME_II_DEVICE) {
4950                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4951                 vpd_addr = 0x80;
4952         }
4953         else {
4954                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4955                 vpd_addr = 0x50;
4956         }
4957
4958         for (i = 0; i < 256; i +=4 ) {
4959                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4960                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
4961                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4962                 for (cnt = 0; cnt <5; cnt++) {
4963                         msleep(2);
4964                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4965                         if (data == 0x80)
4966                                 break;
4967                 }
4968                 if (cnt >= 5) {
4969                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4970                         fail = 1;
4971                         break;
4972                 }
4973                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
4974                                       (u32 *)&vpd_data[i]);
4975         }
4976         if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4977                 memset(nic->product_name, 0, vpd_data[1]);
4978                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4979         }
4980 }
4981
4982 /**
4983  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4984  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4985  *  @eeprom : pointer to the user level structure provided by ethtool,
4986  *  containing all relevant information.
4987  *  @data_buf : user defined value to be written into Eeprom.
4988  *  Description: Reads the values stored in the Eeprom at given offset
4989  *  for a given length. Stores these values int the input argument data
4990  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4991  *  Return value:
4992  *  int  0 on success
4993  */
4994
4995 static int s2io_ethtool_geeprom(struct net_device *dev,
4996                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4997 {
4998         u32 i, valid;
4999         u64 data;
5000         nic_t *sp = dev->priv;
5001
5002         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5003
5004         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5005                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5006
5007         for (i = 0; i < eeprom->len; i += 4) {
5008                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5009                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5010                         return -EFAULT;
5011                 }
5012                 valid = INV(data);
5013                 memcpy((data_buf + i), &valid, 4);
5014         }
5015         return 0;
5016 }
5017
5018 /**
5019  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5020  *  @sp : private member of the device structure, which is a pointer to the
5021  *  s2io_nic structure.
5022  *  @eeprom : pointer to the user level structure provided by ethtool,
5023  *  containing all relevant information.
5024  *  @data_buf ; user defined value to be written into Eeprom.
5025  *  Description:
5026  *  Tries to write the user provided value in the Eeprom, at the offset
5027  *  given by the user.
5028  *  Return value:
5029  *  0 on success, -EFAULT on failure.
5030  */
5031
5032 static int s2io_ethtool_seeprom(struct net_device *dev,
5033                                 struct ethtool_eeprom *eeprom,
5034                                 u8 * data_buf)
5035 {
5036         int len = eeprom->len, cnt = 0;
5037         u64 valid = 0, data;
5038         nic_t *sp = dev->priv;
5039
5040         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5041                 DBG_PRINT(ERR_DBG,
5042                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5043                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5044                           eeprom->magic);
5045                 return -EFAULT;
5046         }
5047
5048         while (len) {
5049                 data = (u32) data_buf[cnt] & 0x000000FF;
5050                 if (data) {
5051                         valid = (u32) (data << 24);
5052                 } else
5053                         valid = data;
5054
5055                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5056                         DBG_PRINT(ERR_DBG,
5057                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5058                         DBG_PRINT(ERR_DBG,
5059                                   "write into the specified offset\n");
5060                         return -EFAULT;
5061                 }
5062                 cnt++;
5063                 len--;
5064         }
5065
5066         return 0;
5067 }
5068
5069 /**
5070  * s2io_register_test - reads and writes into all clock domains.
5071  * @sp : private member of the device structure, which is a pointer to the
5072  * s2io_nic structure.
5073  * @data : variable that returns the result of each of the test conducted b
5074  * by the driver.
5075  * Description:
5076  * Read and write into all clock domains. The NIC has 3 clock domains,
5077  * see that registers in all the three regions are accessible.
5078  * Return value:
5079  * 0 on success.
5080  */
5081
5082 static int s2io_register_test(nic_t * sp, uint64_t * data)
5083 {
5084         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5085         u64 val64 = 0, exp_val;
5086         int fail = 0;
5087
5088         val64 = readq(&bar0->pif_rd_swapper_fb);
5089         if (val64 != 0x123456789abcdefULL) {
5090                 fail = 1;
5091                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5092         }
5093
5094         val64 = readq(&bar0->rmac_pause_cfg);
5095         if (val64 != 0xc000ffff00000000ULL) {
5096                 fail = 1;
5097                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5098         }
5099
5100         val64 = readq(&bar0->rx_queue_cfg);
5101         if (sp->device_type == XFRAME_II_DEVICE)
5102                 exp_val = 0x0404040404040404ULL;
5103         else
5104                 exp_val = 0x0808080808080808ULL;
5105         if (val64 != exp_val) {
5106                 fail = 1;
5107                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5108         }
5109
5110         val64 = readq(&bar0->xgxs_efifo_cfg);
5111         if (val64 != 0x000000001923141EULL) {
5112                 fail = 1;
5113                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5114         }
5115
5116         val64 = 0x5A5A5A5A5A5A5A5AULL;
5117         writeq(val64, &bar0->xmsi_data);
5118         val64 = readq(&bar0->xmsi_data);
5119         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5120                 fail = 1;
5121                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5122         }
5123
5124         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5125         writeq(val64, &bar0->xmsi_data);
5126         val64 = readq(&bar0->xmsi_data);
5127         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5128                 fail = 1;
5129                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5130         }
5131
5132         *data = fail;
5133         return fail;
5134 }
5135
5136 /**
5137  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5138  * @sp : private member of the device structure, which is a pointer to the
5139  * s2io_nic structure.
5140  * @data:variable that returns the result of each of the test conducted by
5141  * the driver.
5142  * Description:
5143  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5144  * register.
5145  * Return value:
5146  * 0 on success.
5147  */
5148
5149 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5150 {
5151         int fail = 0;
5152         u64 ret_data, org_4F0, org_7F0;
5153         u8 saved_4F0 = 0, saved_7F0 = 0;
5154         struct net_device *dev = sp->dev;
5155
5156         /* Test Write Error at offset 0 */
5157         /* Note that SPI interface allows write access to all areas
5158          * of EEPROM. Hence doing all negative testing only for Xframe I.
5159          */
5160         if (sp->device_type == XFRAME_I_DEVICE)
5161                 if (!write_eeprom(sp, 0, 0, 3))
5162                         fail = 1;
5163
5164         /* Save current values at offsets 0x4F0 and 0x7F0 */
5165         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5166                 saved_4F0 = 1;
5167         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5168                 saved_7F0 = 1;
5169
5170         /* Test Write at offset 4f0 */
5171         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5172                 fail = 1;
5173         if (read_eeprom(sp, 0x4F0, &ret_data))
5174                 fail = 1;
5175
5176         if (ret_data != 0x012345) {
5177                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5178                         "Data written %llx Data read %llx\n",
5179                         dev->name, (unsigned long long)0x12345,
5180                         (unsigned long long)ret_data);
5181                 fail = 1;
5182         }
5183
5184         /* Reset the EEPROM data go FFFF */
5185         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5186
5187         /* Test Write Request Error at offset 0x7c */
5188         if (sp->device_type == XFRAME_I_DEVICE)
5189                 if (!write_eeprom(sp, 0x07C, 0, 3))
5190                         fail = 1;
5191
5192         /* Test Write Request at offset 0x7f0 */
5193         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5194                 fail = 1;
5195         if (read_eeprom(sp, 0x7F0, &ret_data))
5196                 fail = 1;
5197
5198         if (ret_data != 0x012345) {
5199                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5200                         "Data written %llx Data read %llx\n",
5201                         dev->name, (unsigned long long)0x12345,
5202                         (unsigned long long)ret_data);
5203                 fail = 1;
5204         }
5205
5206         /* Reset the EEPROM data go FFFF */
5207         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5208
5209         if (sp->device_type == XFRAME_I_DEVICE) {
5210                 /* Test Write Error at offset 0x80 */
5211                 if (!write_eeprom(sp, 0x080, 0, 3))
5212                         fail = 1;
5213
5214                 /* Test Write Error at offset 0xfc */
5215                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5216                         fail = 1;
5217
5218                 /* Test Write Error at offset 0x100 */
5219                 if (!write_eeprom(sp, 0x100, 0, 3))
5220                         fail = 1;
5221
5222                 /* Test Write Error at offset 4ec */
5223                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5224                         fail = 1;
5225         }
5226
5227         /* Restore values at offsets 0x4F0 and 0x7F0 */
5228         if (saved_4F0)
5229                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5230         if (saved_7F0)
5231                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5232
5233         *data = fail;
5234         return fail;
5235 }
5236
5237 /**
5238  * s2io_bist_test - invokes the MemBist test of the card .
5239  * @sp : private member of the device structure, which is a pointer to the
5240  * s2io_nic structure.
5241  * @data:variable that returns the result of each of the test conducted by
5242  * the driver.
5243  * Description:
5244  * This invokes the MemBist test of the card. We give around
5245  * 2 secs time for the Test to complete. If it's still not complete
5246  * within this peiod, we consider that the test failed.
5247  * Return value:
5248  * 0 on success and -1 on failure.
5249  */
5250
5251 static int s2io_bist_test(nic_t * sp, uint64_t * data)
5252 {
5253         u8 bist = 0;
5254         int cnt = 0, ret = -1;
5255
5256         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5257         bist |= PCI_BIST_START;
5258         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5259
5260         while (cnt < 20) {
5261                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5262                 if (!(bist & PCI_BIST_START)) {
5263                         *data = (bist & PCI_BIST_CODE_MASK);
5264                         ret = 0;
5265                         break;
5266                 }
5267                 msleep(100);
5268                 cnt++;
5269         }
5270
5271         return ret;
5272 }
5273
5274 /**
5275  * s2io-link_test - verifies the link state of the nic
5276  * @sp ; private member of the device structure, which is a pointer to the
5277  * s2io_nic structure.
5278  * @data: variable that returns the result of each of the test conducted by
5279  * the driver.
5280  * Description:
5281  * The function verifies the link state of the NIC and updates the input
5282  * argument 'data' appropriately.
5283  * Return value:
5284  * 0 on success.
5285  */
5286
5287 static int s2io_link_test(nic_t * sp, uint64_t * data)
5288 {
5289         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5290         u64 val64;
5291
5292         val64 = readq(&bar0->adapter_status);
5293         if(!(LINK_IS_UP(val64)))
5294                 *data = 1;
5295         else
5296                 *data = 0;
5297
5298         return 0;
5299 }
5300
5301 /**
5302  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5303  * @sp - private member of the device structure, which is a pointer to the
5304  * s2io_nic structure.
5305  * @data - variable that returns the result of each of the test
5306  * conducted by the driver.
5307  * Description:
5308  *  This is one of the offline test that tests the read and write
5309  *  access to the RldRam chip on the NIC.
5310  * Return value:
5311  *  0 on success.
5312  */
5313
5314 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5315 {
5316         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5317         u64 val64;
5318         int cnt, iteration = 0, test_fail = 0;
5319
5320         val64 = readq(&bar0->adapter_control);
5321         val64 &= ~ADAPTER_ECC_EN;
5322         writeq(val64, &bar0->adapter_control);
5323
5324         val64 = readq(&bar0->mc_rldram_test_ctrl);
5325         val64 |= MC_RLDRAM_TEST_MODE;
5326         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5327
5328         val64 = readq(&bar0->mc_rldram_mrs);
5329         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5330         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5331
5332         val64 |= MC_RLDRAM_MRS_ENABLE;
5333         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5334
5335         while (iteration < 2) {
5336                 val64 = 0x55555555aaaa0000ULL;
5337                 if (iteration == 1) {
5338                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5339                 }
5340                 writeq(val64, &bar0->mc_rldram_test_d0);
5341
5342                 val64 = 0xaaaa5a5555550000ULL;
5343                 if (iteration == 1) {
5344                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5345                 }
5346                 writeq(val64, &bar0->mc_rldram_test_d1);
5347
5348                 val64 = 0x55aaaaaaaa5a0000ULL;
5349                 if (iteration == 1) {
5350                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5351                 }
5352                 writeq(val64, &bar0->mc_rldram_test_d2);
5353
5354                 val64 = (u64) (0x0000003ffffe0100ULL);
5355                 writeq(val64, &bar0->mc_rldram_test_add);
5356
5357                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5358                         MC_RLDRAM_TEST_GO;
5359                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5360
5361                 for (cnt = 0; cnt < 5; cnt++) {
5362                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5363                         if (val64 & MC_RLDRAM_TEST_DONE)
5364                                 break;
5365                         msleep(200);
5366                 }
5367
5368                 if (cnt == 5)
5369                         break;
5370
5371                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5372                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5373
5374                 for (cnt = 0; cnt < 5; cnt++) {
5375                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5376                         if (val64 & MC_RLDRAM_TEST_DONE)
5377                                 break;
5378                         msleep(500);
5379                 }
5380
5381                 if (cnt == 5)
5382                         break;
5383
5384                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5385                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5386                         test_fail = 1;
5387
5388                 iteration++;
5389         }
5390
5391         *data = test_fail;
5392
5393         /* Bring the adapter out of test mode */
5394         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5395
5396         return test_fail;
5397 }
5398
5399 /**
5400  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5401  *  @sp : private member of the device structure, which is a pointer to the
5402  *  s2io_nic structure.
5403  *  @ethtest : pointer to a ethtool command specific structure that will be
5404  *  returned to the user.
5405  *  @data : variable that returns the result of each of the test
5406  * conducted by the driver.
5407  * Description:
5408  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5409  *  the health of the card.
5410  * Return value:
5411  *  void
5412  */
5413
5414 static void s2io_ethtool_test(struct net_device *dev,
5415                               struct ethtool_test *ethtest,
5416                               uint64_t * data)
5417 {
5418         nic_t *sp = dev->priv;
5419         int orig_state = netif_running(sp->dev);
5420
5421         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5422                 /* Offline Tests. */
5423                 if (orig_state)
5424                         s2io_close(sp->dev);
5425
5426                 if (s2io_register_test(sp, &data[0]))
5427                         ethtest->flags |= ETH_TEST_FL_FAILED;
5428
5429                 s2io_reset(sp);
5430
5431                 if (s2io_rldram_test(sp, &data[3]))
5432                         ethtest->flags |= ETH_TEST_FL_FAILED;
5433
5434                 s2io_reset(sp);
5435
5436                 if (s2io_eeprom_test(sp, &data[1]))
5437                         ethtest->flags |= ETH_TEST_FL_FAILED;
5438
5439                 if (s2io_bist_test(sp, &data[4]))
5440                         ethtest->flags |= ETH_TEST_FL_FAILED;
5441
5442                 if (orig_state)
5443                         s2io_open(sp->dev);
5444
5445                 data[2] = 0;
5446         } else {
5447                 /* Online Tests. */
5448                 if (!orig_state) {
5449                         DBG_PRINT(ERR_DBG,
5450                                   "%s: is not up, cannot run test\n",
5451                                   dev->name);
5452                         data[0] = -1;
5453                         data[1] = -1;
5454                         data[2] = -1;
5455                         data[3] = -1;
5456                         data[4] = -1;
5457                 }
5458
5459                 if (s2io_link_test(sp, &data[2]))
5460                         ethtest->flags |= ETH_TEST_FL_FAILED;
5461
5462                 data[0] = 0;
5463                 data[1] = 0;
5464                 data[3] = 0;
5465                 data[4] = 0;
5466         }
5467 }
5468
5469 static void s2io_get_ethtool_stats(struct net_device *dev,
5470                                    struct ethtool_stats *estats,
5471                                    u64 * tmp_stats)
5472 {
5473         int i = 0;
5474         nic_t *sp = dev->priv;
5475         StatInfo_t *stat_info = sp->mac_control.stats_info;
5476
5477         s2io_updt_stats(sp);
5478         tmp_stats[i++] =
5479                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5480                 le32_to_cpu(stat_info->tmac_frms);
5481         tmp_stats[i++] =
5482                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5483                 le32_to_cpu(stat_info->tmac_data_octets);
5484         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5485         tmp_stats[i++] =
5486                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5487                 le32_to_cpu(stat_info->tmac_mcst_frms);
5488         tmp_stats[i++] =
5489                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5490                 le32_to_cpu(stat_info->tmac_bcst_frms);
5491         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5492         tmp_stats[i++] =
5493                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5494                 le32_to_cpu(stat_info->tmac_ttl_octets);
5495         tmp_stats[i++] =
5496                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5497                 le32_to_cpu(stat_info->tmac_ucst_frms);
5498         tmp_stats[i++] =
5499                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5500                 le32_to_cpu(stat_info->tmac_nucst_frms);
5501         tmp_stats[i++] =
5502                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5503                 le32_to_cpu(stat_info->tmac_any_err_frms);
5504         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5505         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5506         tmp_stats[i++] =
5507                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5508                 le32_to_cpu(stat_info->tmac_vld_ip);
5509         tmp_stats[i++] =
5510                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5511                 le32_to_cpu(stat_info->tmac_drop_ip);
5512         tmp_stats[i++] =
5513                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5514                 le32_to_cpu(stat_info->tmac_icmp);
5515         tmp_stats[i++] =
5516                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5517                 le32_to_cpu(stat_info->tmac_rst_tcp);
5518         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5519         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5520                 le32_to_cpu(stat_info->tmac_udp);
5521         tmp_stats[i++] =
5522                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5523                 le32_to_cpu(stat_info->rmac_vld_frms);
5524         tmp_stats[i++] =
5525                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5526                 le32_to_cpu(stat_info->rmac_data_octets);
5527         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5528         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5529         tmp_stats[i++] =
5530                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5531                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5532         tmp_stats[i++] =
5533                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5534                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5535         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5536         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5537         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5538         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5539         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5540         tmp_stats[i++] =
5541                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5542                 le32_to_cpu(stat_info->rmac_ttl_octets);
5543         tmp_stats[i++] =
5544                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5545                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5546         tmp_stats[i++] =
5547                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5548                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5549         tmp_stats[i++] =
5550                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5551                 le32_to_cpu(stat_info->rmac_discarded_frms);
5552         tmp_stats[i++] =
5553                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5554                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5555         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5556         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5557         tmp_stats[i++] =
5558                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5559                 le32_to_cpu(stat_info->rmac_usized_frms);
5560         tmp_stats[i++] =
5561                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5562                 le32_to_cpu(stat_info->rmac_osized_frms);
5563         tmp_stats[i++] =
5564                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5565                 le32_to_cpu(stat_info->rmac_frag_frms);
5566         tmp_stats[i++] =
5567                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5568                 le32_to_cpu(stat_info->rmac_jabber_frms);
5569         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5570         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5571         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5572         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5573         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5574         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5575         tmp_stats[i++] =
5576                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5577                 le32_to_cpu(stat_info->rmac_ip);
5578         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5579         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5580         tmp_stats[i++] =
5581                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5582                 le32_to_cpu(stat_info->rmac_drop_ip);
5583         tmp_stats[i++] =
5584                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5585                 le32_to_cpu(stat_info->rmac_icmp);
5586         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5587         tmp_stats[i++] =
5588                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5589                 le32_to_cpu(stat_info->rmac_udp);
5590         tmp_stats[i++] =
5591                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5592                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5593         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5594         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5595         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5596         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5597         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5598         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5599         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5600         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5601         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5602         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5603         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5604         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5605         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5606         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5607         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5608         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5609         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5610         tmp_stats[i++] =
5611                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5612                 le32_to_cpu(stat_info->rmac_pause_cnt);
5613         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5614         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5615         tmp_stats[i++] =
5616                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5617                 le32_to_cpu(stat_info->rmac_accepted_ip);
5618         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5619         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5620         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5621         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5622         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5623         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5624         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5625         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5626         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5627         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5628         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5629         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5630         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5631         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5632         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5633         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5634         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5635         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5636         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5637         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5638         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5639         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5640         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5641         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5642         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5643         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5644         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5645         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5646         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5647         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5648         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5649         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5650         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5651         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5652         tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5653         tmp_stats[i++] = 0;
5654         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5655         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5656         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5657         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5658         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5659         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5660         tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5661         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5662         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5663         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5664         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5665         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5666         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5667         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5668         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5669         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5670         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5671         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5672         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5673         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5674         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5675         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5676         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5677         if (stat_info->sw_stat.num_aggregations) {
5678                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5679                 int count = 0;
5680                 /*
5681                  * Since 64-bit divide does not work on all platforms,
5682                  * do repeated subtraction.
5683                  */
5684                 while (tmp >= stat_info->sw_stat.num_aggregations) {
5685                         tmp -= stat_info->sw_stat.num_aggregations;
5686                         count++;
5687                 }
5688                 tmp_stats[i++] = count;
5689         }
5690         else
5691                 tmp_stats[i++] = 0;
5692 }
5693
5694 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5695 {
5696         return (XENA_REG_SPACE);
5697 }
5698
5699
5700 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5701 {
5702         nic_t *sp = dev->priv;
5703
5704         return (sp->rx_csum);
5705 }
5706
5707 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5708 {
5709         nic_t *sp = dev->priv;
5710
5711         if (data)
5712                 sp->rx_csum = 1;
5713         else
5714                 sp->rx_csum = 0;
5715
5716         return 0;
5717 }
5718
5719 static int s2io_get_eeprom_len(struct net_device *dev)
5720 {
5721         return (XENA_EEPROM_SPACE);
5722 }
5723
5724 static int s2io_ethtool_self_test_count(struct net_device *dev)
5725 {
5726         return (S2IO_TEST_LEN);
5727 }
5728
5729 static void s2io_ethtool_get_strings(struct net_device *dev,
5730                                      u32 stringset, u8 * data)
5731 {
5732         switch (stringset) {
5733         case ETH_SS_TEST:
5734                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5735                 break;
5736         case ETH_SS_STATS:
5737                 memcpy(data, &ethtool_stats_keys,
5738                        sizeof(ethtool_stats_keys));
5739         }
5740 }
5741 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5742 {
5743         return (S2IO_STAT_LEN);
5744 }
5745
5746 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5747 {
5748         if (data)
5749                 dev->features |= NETIF_F_IP_CSUM;
5750         else
5751                 dev->features &= ~NETIF_F_IP_CSUM;
5752
5753         return 0;
5754 }
5755
5756
5757 static struct ethtool_ops netdev_ethtool_ops = {
5758         .get_settings = s2io_ethtool_gset,
5759         .set_settings = s2io_ethtool_sset,
5760         .get_drvinfo = s2io_ethtool_gdrvinfo,
5761         .get_regs_len = s2io_ethtool_get_regs_len,
5762         .get_regs = s2io_ethtool_gregs,
5763         .get_link = ethtool_op_get_link,
5764         .get_eeprom_len = s2io_get_eeprom_len,
5765         .get_eeprom = s2io_ethtool_geeprom,
5766         .set_eeprom = s2io_ethtool_seeprom,
5767         .get_pauseparam = s2io_ethtool_getpause_data,
5768         .set_pauseparam = s2io_ethtool_setpause_data,
5769         .get_rx_csum = s2io_ethtool_get_rx_csum,
5770         .set_rx_csum = s2io_ethtool_set_rx_csum,
5771         .get_tx_csum = ethtool_op_get_tx_csum,
5772         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5773         .get_sg = ethtool_op_get_sg,
5774         .set_sg = ethtool_op_set_sg,
5775 #ifdef NETIF_F_TSO
5776         .get_tso = ethtool_op_get_tso,
5777         .set_tso = ethtool_op_set_tso,
5778 #endif
5779         .get_ufo = ethtool_op_get_ufo,
5780         .set_ufo = ethtool_op_set_ufo,
5781         .self_test_count = s2io_ethtool_self_test_count,
5782         .self_test = s2io_ethtool_test,
5783         .get_strings = s2io_ethtool_get_strings,
5784         .phys_id = s2io_ethtool_idnic,
5785         .get_stats_count = s2io_ethtool_get_stats_count,
5786         .get_ethtool_stats = s2io_get_ethtool_stats
5787 };
5788
5789 /**
5790  *  s2io_ioctl - Entry point for the Ioctl
5791  *  @dev :  Device pointer.
5792  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5793  *  a proprietary structure used to pass information to the driver.
5794  *  @cmd :  This is used to distinguish between the different commands that
5795  *  can be passed to the IOCTL functions.
5796  *  Description:
5797  *  Currently there are no special functionality supported in IOCTL, hence
5798  *  function always return EOPNOTSUPPORTED
5799  */
5800
5801 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5802 {
5803         return -EOPNOTSUPP;
5804 }
5805
5806 /**
5807  *  s2io_change_mtu - entry point to change MTU size for the device.
5808  *   @dev : device pointer.
5809  *   @new_mtu : the new MTU size for the device.
5810  *   Description: A driver entry point to change MTU size for the device.
5811  *   Before changing the MTU the device must be stopped.
5812  *  Return value:
5813  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5814  *   file on failure.
5815  */
5816
5817 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5818 {
5819         nic_t *sp = dev->priv;
5820
5821         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5822                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5823                           dev->name);
5824                 return -EPERM;
5825         }
5826
5827         dev->mtu = new_mtu;
5828         if (netif_running(dev)) {
5829                 s2io_card_down(sp);
5830                 netif_stop_queue(dev);
5831                 if (s2io_card_up(sp)) {
5832                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5833                                   __FUNCTION__);
5834                 }
5835                 if (netif_queue_stopped(dev))
5836                         netif_wake_queue(dev);
5837         } else { /* Device is down */
5838                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5839                 u64 val64 = new_mtu;
5840
5841                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5842         }
5843
5844         return 0;
5845 }
5846
5847 /**
5848  *  s2io_tasklet - Bottom half of the ISR.
5849  *  @dev_adr : address of the device structure in dma_addr_t format.
5850  *  Description:
5851  *  This is the tasklet or the bottom half of the ISR. This is
5852  *  an extension of the ISR which is scheduled by the scheduler to be run
5853  *  when the load on the CPU is low. All low priority tasks of the ISR can
5854  *  be pushed into the tasklet. For now the tasklet is used only to
5855  *  replenish the Rx buffers in the Rx buffer descriptors.
5856  *  Return value:
5857  *  void.
5858  */
5859
5860 static void s2io_tasklet(unsigned long dev_addr)
5861 {
5862         struct net_device *dev = (struct net_device *) dev_addr;
5863         nic_t *sp = dev->priv;
5864         int i, ret;
5865         mac_info_t *mac_control;
5866         struct config_param *config;
5867
5868         mac_control = &sp->mac_control;
5869         config = &sp->config;
5870
5871         if (!TASKLET_IN_USE) {
5872                 for (i = 0; i < config->rx_ring_num; i++) {
5873                         ret = fill_rx_buffers(sp, i);
5874                         if (ret == -ENOMEM) {
5875                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5876                                           dev->name);
5877                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5878                                 break;
5879                         } else if (ret == -EFILL) {
5880                                 DBG_PRINT(ERR_DBG,
5881                                           "%s: Rx Ring %d is full\n",
5882                                           dev->name, i);
5883                                 break;
5884                         }
5885                 }
5886                 clear_bit(0, (&sp->tasklet_status));
5887         }
5888 }
5889
5890 /**
5891  * s2io_set_link - Set the LInk status
5892  * @data: long pointer to device private structue
5893  * Description: Sets the link status for the adapter
5894  */
5895
5896 static void s2io_set_link(unsigned long data)
5897 {
5898         nic_t *nic = (nic_t *) data;
5899         struct net_device *dev = nic->dev;
5900         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5901         register u64 val64;
5902         u16 subid;
5903
5904         if (test_and_set_bit(0, &(nic->link_state))) {
5905                 /* The card is being reset, no point doing anything */
5906                 return;
5907         }
5908
5909         subid = nic->pdev->subsystem_device;
5910         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5911                 /*
5912                  * Allow a small delay for the NICs self initiated
5913                  * cleanup to complete.
5914                  */
5915                 msleep(100);
5916         }
5917
5918         val64 = readq(&bar0->adapter_status);
5919         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5920                 if (LINK_IS_UP(val64)) {
5921                         val64 = readq(&bar0->adapter_control);
5922                         val64 |= ADAPTER_CNTL_EN;
5923                         writeq(val64, &bar0->adapter_control);
5924                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5925                                                              subid)) {
5926                                 val64 = readq(&bar0->gpio_control);
5927                                 val64 |= GPIO_CTRL_GPIO_0;
5928                                 writeq(val64, &bar0->gpio_control);
5929                                 val64 = readq(&bar0->gpio_control);
5930                         } else {
5931                                 val64 |= ADAPTER_LED_ON;
5932                                 writeq(val64, &bar0->adapter_control);
5933                         }
5934                         if (s2io_link_fault_indication(nic) ==
5935                                                 MAC_RMAC_ERR_TIMER) {
5936                                 val64 = readq(&bar0->adapter_status);
5937                                 if (!LINK_IS_UP(val64)) {
5938                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5939                                         DBG_PRINT(ERR_DBG, " Link down");
5940                                         DBG_PRINT(ERR_DBG, "after ");
5941                                         DBG_PRINT(ERR_DBG, "enabling ");
5942                                         DBG_PRINT(ERR_DBG, "device \n");
5943                                 }
5944                         }
5945                         if (nic->device_enabled_once == FALSE) {
5946                                 nic->device_enabled_once = TRUE;
5947                         }
5948                         s2io_link(nic, LINK_UP);
5949                 } else {
5950                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5951                                                               subid)) {
5952                                 val64 = readq(&bar0->gpio_control);
5953                                 val64 &= ~GPIO_CTRL_GPIO_0;
5954                                 writeq(val64, &bar0->gpio_control);
5955                                 val64 = readq(&bar0->gpio_control);
5956                         }
5957                         s2io_link(nic, LINK_DOWN);
5958                 }
5959         } else {                /* NIC is not Quiescent. */
5960                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5961                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5962                 netif_stop_queue(dev);
5963         }
5964         clear_bit(0, &(nic->link_state));
5965 }
5966
5967 static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5968                            struct sk_buff **skb, u64 *temp0, u64 *temp1,
5969                            u64 *temp2, int size)
5970 {
5971         struct net_device *dev = sp->dev;
5972         struct sk_buff *frag_list;
5973
5974         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5975                 /* allocate skb */
5976                 if (*skb) {
5977                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5978                         /*
5979                          * As Rx frame are not going to be processed,
5980                          * using same mapped address for the Rxd
5981                          * buffer pointer
5982                          */
5983                         ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
5984                 } else {
5985                         *skb = dev_alloc_skb(size);
5986                         if (!(*skb)) {
5987                                 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5988                                 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5989                                 return -ENOMEM ;
5990                         }
5991                         /* storing the mapped addr in a temp variable
5992                          * such it will be used for next rxd whose
5993                          * Host Control is NULL
5994                          */
5995                         ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
5996                                 pci_map_single( sp->pdev, (*skb)->data,
5997                                         size - NET_IP_ALIGN,
5998                                         PCI_DMA_FROMDEVICE);
5999                         rxdp->Host_Control = (unsigned long) (*skb);
6000                 }
6001         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6002                 /* Two buffer Mode */
6003                 if (*skb) {
6004                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6005                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6006                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6007                 } else {
6008                         *skb = dev_alloc_skb(size);
6009                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6010                                 pci_map_single(sp->pdev, (*skb)->data,
6011                                                dev->mtu + 4,
6012                                                PCI_DMA_FROMDEVICE);
6013                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6014                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6015                                                 PCI_DMA_FROMDEVICE);
6016                         rxdp->Host_Control = (unsigned long) (*skb);
6017
6018                         /* Buffer-1 will be dummy buffer not used */
6019                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6020                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6021                                                PCI_DMA_FROMDEVICE);
6022                 }
6023         } else if ((rxdp->Host_Control == 0)) {
6024                 /* Three buffer mode */
6025                 if (*skb) {
6026                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6027                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6028                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6029                 } else {
6030                         *skb = dev_alloc_skb(size);
6031
6032                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6033                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6034                                                PCI_DMA_FROMDEVICE);
6035                         /* Buffer-1 receives L3/L4 headers */
6036                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6037                                 pci_map_single( sp->pdev, (*skb)->data,
6038                                                 l3l4hdr_size + 4,
6039                                                 PCI_DMA_FROMDEVICE);
6040                         /*
6041                          * skb_shinfo(skb)->frag_list will have L4
6042                          * data payload
6043                          */
6044                         skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6045                                                                    ALIGN_SIZE);
6046                         if (skb_shinfo(*skb)->frag_list == NULL) {
6047                                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6048                                           failed\n ", dev->name);
6049                                 return -ENOMEM ;
6050                         }
6051                         frag_list = skb_shinfo(*skb)->frag_list;
6052                         frag_list->next = NULL;
6053                         /*
6054                          * Buffer-2 receives L4 data payload
6055                          */
6056                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6057                                 pci_map_single( sp->pdev, frag_list->data,
6058                                                 dev->mtu, PCI_DMA_FROMDEVICE);
6059                 }
6060         }
6061         return 0;
6062 }
6063 static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6064 {
6065         struct net_device *dev = sp->dev;
6066         if (sp->rxd_mode == RXD_MODE_1) {
6067                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6068         } else if (sp->rxd_mode == RXD_MODE_3B) {
6069                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6070                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6071                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6072         } else {
6073                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6074                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6075                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6076         }
6077 }
6078
6079 static  int rxd_owner_bit_reset(nic_t *sp)
6080 {
6081         int i, j, k, blk_cnt = 0, size;
6082         mac_info_t * mac_control = &sp->mac_control;
6083         struct config_param *config = &sp->config;
6084         struct net_device *dev = sp->dev;
6085         RxD_t *rxdp = NULL;
6086         struct sk_buff *skb = NULL;
6087         buffAdd_t *ba = NULL;
6088         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6089
6090         /* Calculate the size based on ring mode */
6091         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6092                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6093         if (sp->rxd_mode == RXD_MODE_1)
6094                 size += NET_IP_ALIGN;
6095         else if (sp->rxd_mode == RXD_MODE_3B)
6096                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6097         else
6098                 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6099
6100         for (i = 0; i < config->rx_ring_num; i++) {
6101                 blk_cnt = config->rx_cfg[i].num_rxd /
6102                         (rxd_count[sp->rxd_mode] +1);
6103
6104                 for (j = 0; j < blk_cnt; j++) {
6105                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6106                                 rxdp = mac_control->rings[i].
6107                                         rx_blocks[j].rxds[k].virt_addr;
6108                                 if(sp->rxd_mode >= RXD_MODE_3A)
6109                                         ba = &mac_control->rings[i].ba[j][k];
6110                                 set_rxd_buffer_pointer(sp, rxdp, ba,
6111                                                        &skb,(u64 *)&temp0_64,
6112                                                        (u64 *)&temp1_64,
6113                                                        (u64 *)&temp2_64, size);
6114
6115                                 set_rxd_buffer_size(sp, rxdp, size);
6116                                 wmb();
6117                                 /* flip the Ownership bit to Hardware */
6118                                 rxdp->Control_1 |= RXD_OWN_XENA;
6119                         }
6120                 }
6121         }
6122         return 0;
6123
6124 }
6125
6126 static int s2io_add_isr(nic_t * sp)
6127 {
6128         int ret = 0;
6129         struct net_device *dev = sp->dev;
6130         int err = 0;
6131
6132         if (sp->intr_type == MSI)
6133                 ret = s2io_enable_msi(sp);
6134         else if (sp->intr_type == MSI_X)
6135                 ret = s2io_enable_msi_x(sp);
6136         if (ret) {
6137                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6138                 sp->intr_type = INTA;
6139         }
6140
6141         /* Store the values of the MSIX table in the nic_t structure */
6142         store_xmsi_data(sp);
6143
6144         /* After proper initialization of H/W, register ISR */
6145         if (sp->intr_type == MSI) {
6146                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6147                         IRQF_SHARED, sp->name, dev);
6148                 if (err) {
6149                         pci_disable_msi(sp->pdev);
6150                         DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6151                                   dev->name);
6152                         return -1;
6153                 }
6154         }
6155         if (sp->intr_type == MSI_X) {
6156                 int i;
6157
6158                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6159                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6160                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6161                                         dev->name, i);
6162                                 err = request_irq(sp->entries[i].vector,
6163                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6164                                                   sp->s2io_entries[i].arg);
6165                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6166                                 (unsigned long long)sp->msix_info[i].addr);
6167                         } else {
6168                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6169                                         dev->name, i);
6170                                 err = request_irq(sp->entries[i].vector,
6171                                           s2io_msix_ring_handle, 0, sp->desc[i],
6172                                                   sp->s2io_entries[i].arg);
6173                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6174                                 (unsigned long long)sp->msix_info[i].addr);
6175                         }
6176                         if (err) {
6177                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6178                                           "failed\n", dev->name, i);
6179                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6180                                 return -1;
6181                         }
6182                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6183                 }
6184         }
6185         if (sp->intr_type == INTA) {
6186                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6187                                 sp->name, dev);
6188                 if (err) {
6189                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6190                                   dev->name);
6191                         return -1;
6192                 }
6193         }
6194         return 0;
6195 }
6196 static void s2io_rem_isr(nic_t * sp)
6197 {
6198         int cnt = 0;
6199         struct net_device *dev = sp->dev;
6200
6201         if (sp->intr_type == MSI_X) {
6202                 int i;
6203                 u16 msi_control;
6204
6205                 for (i=1; (sp->s2io_entries[i].in_use ==
6206                         MSIX_REGISTERED_SUCCESS); i++) {
6207                         int vector = sp->entries[i].vector;
6208                         void *arg = sp->s2io_entries[i].arg;
6209
6210                         free_irq(vector, arg);
6211                 }
6212                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6213                 msi_control &= 0xFFFE; /* Disable MSI */
6214                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6215
6216                 pci_disable_msix(sp->pdev);
6217         } else {
6218                 free_irq(sp->pdev->irq, dev);
6219                 if (sp->intr_type == MSI) {
6220                         u16 val;
6221
6222                         pci_disable_msi(sp->pdev);
6223                         pci_read_config_word(sp->pdev, 0x4c, &val);
6224                         val ^= 0x1;
6225                         pci_write_config_word(sp->pdev, 0x4c, val);
6226                 }
6227         }
6228         /* Waiting till all Interrupt handlers are complete */
6229         cnt = 0;
6230         do {
6231                 msleep(10);
6232                 if (!atomic_read(&sp->isr_cnt))
6233                         break;
6234                 cnt++;
6235         } while(cnt < 5);
6236 }
6237
6238 static void s2io_card_down(nic_t * sp)
6239 {
6240         int cnt = 0;
6241         XENA_dev_config_t __iomem *bar0 = sp->bar0;
6242         unsigned long flags;
6243         register u64 val64 = 0;
6244
6245         del_timer_sync(&sp->alarm_timer);
6246         /* If s2io_set_link task is executing, wait till it completes. */
6247         while (test_and_set_bit(0, &(sp->link_state))) {
6248                 msleep(50);
6249         }
6250         atomic_set(&sp->card_state, CARD_DOWN);
6251
6252         /* disable Tx and Rx traffic on the NIC */
6253         stop_nic(sp);
6254
6255         s2io_rem_isr(sp);
6256
6257         /* Kill tasklet. */
6258         tasklet_kill(&sp->task);
6259
6260         /* Check if the device is Quiescent and then Reset the NIC */
6261         do {
6262                 /* As per the HW requirement we need to replenish the
6263                  * receive buffer to avoid the ring bump. Since there is
6264                  * no intention of processing the Rx frame at this pointwe are
6265                  * just settting the ownership bit of rxd in Each Rx
6266                  * ring to HW and set the appropriate buffer size
6267                  * based on the ring mode
6268                  */
6269                 rxd_owner_bit_reset(sp);
6270
6271                 val64 = readq(&bar0->adapter_status);
6272                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
6273                         break;
6274                 }
6275
6276                 msleep(50);
6277                 cnt++;
6278                 if (cnt == 10) {
6279                         DBG_PRINT(ERR_DBG,
6280                                   "s2io_close:Device not Quiescent ");
6281                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6282                                   (unsigned long long) val64);
6283                         break;
6284                 }
6285         } while (1);
6286         s2io_reset(sp);
6287
6288         spin_lock_irqsave(&sp->tx_lock, flags);
6289         /* Free all Tx buffers */
6290         free_tx_buffers(sp);
6291         spin_unlock_irqrestore(&sp->tx_lock, flags);
6292
6293         /* Free all Rx buffers */
6294         spin_lock_irqsave(&sp->rx_lock, flags);
6295         free_rx_buffers(sp);
6296         spin_unlock_irqrestore(&sp->rx_lock, flags);
6297
6298         clear_bit(0, &(sp->link_state));
6299 }
6300
6301 static int s2io_card_up(nic_t * sp)
6302 {
6303         int i, ret = 0;
6304         mac_info_t *mac_control;
6305         struct config_param *config;
6306         struct net_device *dev = (struct net_device *) sp->dev;
6307         u16 interruptible;
6308
6309         /* Initialize the H/W I/O registers */
6310         if (init_nic(sp) != 0) {
6311                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6312                           dev->name);
6313                 s2io_reset(sp);
6314                 return -ENODEV;
6315         }
6316
6317         /*
6318          * Initializing the Rx buffers. For now we are considering only 1
6319          * Rx ring and initializing buffers into 30 Rx blocks
6320          */
6321         mac_control = &sp->mac_control;
6322         config = &sp->config;
6323
6324         for (i = 0; i < config->rx_ring_num; i++) {
6325                 if ((ret = fill_rx_buffers(sp, i))) {
6326                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6327                                   dev->name);
6328                         s2io_reset(sp);
6329                         free_rx_buffers(sp);
6330                         return -ENOMEM;
6331                 }
6332                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6333                           atomic_read(&sp->rx_bufs_left[i]));
6334         }
6335
6336         /* Setting its receive mode */
6337         s2io_set_multicast(dev);
6338
6339         if (sp->lro) {
6340                 /* Initialize max aggregatable pkts based on MTU */
6341                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6342                 /* Check if we can use(if specified) user provided value */
6343                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6344                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6345         }
6346
6347         /* Enable Rx Traffic and interrupts on the NIC */
6348         if (start_nic(sp)) {
6349                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6350                 s2io_reset(sp);
6351                 free_rx_buffers(sp);
6352                 return -ENODEV;
6353         }
6354
6355         /* Add interrupt service routine */
6356         if (s2io_add_isr(sp) != 0) {
6357                 if (sp->intr_type == MSI_X)
6358                         s2io_rem_isr(sp);
6359                 s2io_reset(sp);
6360                 free_rx_buffers(sp);
6361                 return -ENODEV;
6362         }
6363
6364         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6365
6366         /* Enable tasklet for the device */
6367         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6368
6369         /*  Enable select interrupts */
6370         if (sp->intr_type != INTA)
6371                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6372         else {
6373                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6374                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6375                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6376                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6377         }
6378
6379
6380         atomic_set(&sp->card_state, CARD_UP);
6381         return 0;
6382 }
6383
6384 /**
6385  * s2io_restart_nic - Resets the NIC.
6386  * @data : long pointer to the device private structure
6387  * Description:
6388  * This function is scheduled to be run by the s2io_tx_watchdog
6389  * function after 0.5 secs to reset the NIC. The idea is to reduce
6390  * the run time of the watch dog routine which is run holding a
6391  * spin lock.
6392  */
6393
6394 static void s2io_restart_nic(unsigned long data)
6395 {
6396         struct net_device *dev = (struct net_device *) data;
6397         nic_t *sp = dev->priv;
6398
6399         s2io_card_down(sp);
6400         if (s2io_card_up(sp)) {
6401                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6402                           dev->name);
6403         }
6404         netif_wake_queue(dev);
6405         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6406                   dev->name);
6407
6408 }
6409
6410 /**
6411  *  s2io_tx_watchdog - Watchdog for transmit side.
6412  *  @dev : Pointer to net device structure
6413  *  Description:
6414  *  This function is triggered if the Tx Queue is stopped
6415  *  for a pre-defined amount of time when the Interface is still up.
6416  *  If the Interface is jammed in such a situation, the hardware is
6417  *  reset (by s2io_close) and restarted again (by s2io_open) to
6418  *  overcome any problem that might have been caused in the hardware.
6419  *  Return value:
6420  *  void
6421  */
6422
6423 static void s2io_tx_watchdog(struct net_device *dev)
6424 {
6425         nic_t *sp = dev->priv;
6426
6427         if (netif_carrier_ok(dev)) {
6428                 schedule_work(&sp->rst_timer_task);
6429                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6430         }
6431 }
6432
6433 /**
6434  *   rx_osm_handler - To perform some OS related operations on SKB.
6435  *   @sp: private member of the device structure,pointer to s2io_nic structure.
6436  *   @skb : the socket buffer pointer.
6437  *   @len : length of the packet
6438  *   @cksum : FCS checksum of the frame.
6439  *   @ring_no : the ring from which this RxD was extracted.
6440  *   Description:
6441  *   This function is called by the Tx interrupt serivce routine to perform
6442  *   some OS related operations on the SKB before passing it to the upper
6443  *   layers. It mainly checks if the checksum is OK, if so adds it to the
6444  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
6445  *   to the upper layer. If the checksum is wrong, it increments the Rx
6446  *   packet error count, frees the SKB and returns error.
6447  *   Return value:
6448  *   SUCCESS on success and -1 on failure.
6449  */
6450 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6451 {
6452         nic_t *sp = ring_data->nic;
6453         struct net_device *dev = (struct net_device *) sp->dev;
6454         struct sk_buff *skb = (struct sk_buff *)
6455                 ((unsigned long) rxdp->Host_Control);
6456         int ring_no = ring_data->ring_no;
6457         u16 l3_csum, l4_csum;
6458         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6459         lro_t *lro;
6460
6461         skb->dev = dev;
6462
6463         if (err) {
6464                 /* Check for parity error */
6465                 if (err & 0x1) {
6466                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6467                 }
6468
6469                 /*
6470                 * Drop the packet if bad transfer code. Exception being
6471                 * 0x5, which could be due to unsupported IPv6 extension header.
6472                 * In this case, we let stack handle the packet.
6473                 * Note that in this case, since checksum will be incorrect,
6474                 * stack will validate the same.
6475                 */
6476                 if (err && ((err >> 48) != 0x5)) {
6477                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6478                                 dev->name, err);
6479                         sp->stats.rx_crc_errors++;
6480                         dev_kfree_skb(skb);
6481                         atomic_dec(&sp->rx_bufs_left[ring_no]);
6482                         rxdp->Host_Control = 0;
6483                         return 0;
6484                 }
6485         }
6486
6487         /* Updating statistics */
6488         rxdp->Host_Control = 0;
6489         sp->rx_pkt_count++;
6490         sp->stats.rx_packets++;
6491         if (sp->rxd_mode == RXD_MODE_1) {
6492                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6493
6494                 sp->stats.rx_bytes += len;
6495                 skb_put(skb, len);
6496
6497         } else if (sp->rxd_mode >= RXD_MODE_3A) {
6498                 int get_block = ring_data->rx_curr_get_info.block_index;
6499                 int get_off = ring_data->rx_curr_get_info.offset;
6500                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6501                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6502                 unsigned char *buff = skb_push(skb, buf0_len);
6503
6504                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6505                 sp->stats.rx_bytes += buf0_len + buf2_len;
6506                 memcpy(buff, ba->ba_0, buf0_len);
6507
6508                 if (sp->rxd_mode == RXD_MODE_3A) {
6509                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6510
6511                         skb_put(skb, buf1_len);
6512                         skb->len += buf2_len;
6513                         skb->data_len += buf2_len;
6514                         skb->truesize += buf2_len;
6515                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6516                         sp->stats.rx_bytes += buf1_len;
6517
6518                 } else
6519                         skb_put(skb, buf2_len);
6520         }
6521
6522         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6523             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6524             (sp->rx_csum)) {
6525                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6526                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6527                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6528                         /*
6529                          * NIC verifies if the Checksum of the received
6530                          * frame is Ok or not and accordingly returns
6531                          * a flag in the RxD.
6532                          */
6533                         skb->ip_summed = CHECKSUM_UNNECESSARY;
6534                         if (sp->lro) {
6535                                 u32 tcp_len;
6536                                 u8 *tcp;
6537                                 int ret = 0;
6538
6539                                 ret = s2io_club_tcp_session(skb->data, &tcp,
6540                                                 &tcp_len, &lro, rxdp, sp);
6541                                 switch (ret) {
6542                                         case 3: /* Begin anew */
6543                                                 lro->parent = skb;
6544                                                 goto aggregate;
6545                                         case 1: /* Aggregate */
6546                                         {
6547                                                 lro_append_pkt(sp, lro,
6548                                                         skb, tcp_len);
6549                                                 goto aggregate;
6550                                         }
6551                                         case 4: /* Flush session */
6552                                         {
6553                                                 lro_append_pkt(sp, lro,
6554                                                         skb, tcp_len);
6555                                                 queue_rx_frame(lro->parent);
6556                                                 clear_lro_session(lro);
6557                                                 sp->mac_control.stats_info->
6558                                                     sw_stat.flush_max_pkts++;
6559                                                 goto aggregate;
6560                                         }
6561                                         case 2: /* Flush both */
6562                                                 lro->parent->data_len =
6563                                                         lro->frags_len;
6564                                                 sp->mac_control.stats_info->
6565                                                      sw_stat.sending_both++;
6566                                                 queue_rx_frame(lro->parent);
6567                                                 clear_lro_session(lro);
6568                                                 goto send_up;
6569                                         case 0: /* sessions exceeded */
6570                                         case -1: /* non-TCP or not
6571                                                   * L2 aggregatable
6572                                                   */
6573                                         case 5: /*
6574                                                  * First pkt in session not
6575                                                  * L3/L4 aggregatable
6576                                                  */
6577                                                 break;
6578                                         default:
6579                                                 DBG_PRINT(ERR_DBG,
6580                                                         "%s: Samadhana!!\n",
6581                                                          __FUNCTION__);
6582                                                 BUG();
6583                                 }
6584                         }
6585                 } else {
6586                         /*
6587                          * Packet with erroneous checksum, let the
6588                          * upper layers deal with it.
6589                          */
6590                         skb->ip_summed = CHECKSUM_NONE;
6591                 }
6592         } else {
6593                 skb->ip_summed = CHECKSUM_NONE;
6594         }
6595
6596         if (!sp->lro) {
6597                 skb->protocol = eth_type_trans(skb, dev);
6598 #ifdef CONFIG_S2IO_NAPI
6599                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6600                         /* Queueing the vlan frame to the upper layer */
6601                         vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6602                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
6603                 } else {
6604                         netif_receive_skb(skb);
6605                 }
6606 #else
6607                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6608                         /* Queueing the vlan frame to the upper layer */
6609                         vlan_hwaccel_rx(skb, sp->vlgrp,
6610                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
6611                 } else {
6612                         netif_rx(skb);
6613                 }
6614 #endif
6615         } else {
6616 send_up:
6617                 queue_rx_frame(skb);
6618         }
6619         dev->last_rx = jiffies;
6620 aggregate:
6621         atomic_dec(&sp->rx_bufs_left[ring_no]);
6622         return SUCCESS;
6623 }
6624
6625 /**
6626  *  s2io_link - stops/starts the Tx queue.
6627  *  @sp : private member of the device structure, which is a pointer to the
6628  *  s2io_nic structure.
6629  *  @link : inidicates whether link is UP/DOWN.
6630  *  Description:
6631  *  This function stops/starts the Tx queue depending on whether the link
6632  *  status of the NIC is is down or up. This is called by the Alarm
6633  *  interrupt handler whenever a link change interrupt comes up.
6634  *  Return value:
6635  *  void.
6636  */
6637
6638 static void s2io_link(nic_t * sp, int link)
6639 {
6640         struct net_device *dev = (struct net_device *) sp->dev;
6641
6642         if (link != sp->last_link_state) {
6643                 if (link == LINK_DOWN) {
6644                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6645                         netif_carrier_off(dev);
6646                 } else {
6647                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6648                         netif_carrier_on(dev);
6649                 }
6650         }
6651         sp->last_link_state = link;
6652 }
6653
6654 /**
6655  *  get_xena_rev_id - to identify revision ID of xena.
6656  *  @pdev : PCI Dev structure
6657  *  Description:
6658  *  Function to identify the Revision ID of xena.
6659  *  Return value:
6660  *  returns the revision ID of the device.
6661  */
6662
6663 static int get_xena_rev_id(struct pci_dev *pdev)
6664 {
6665         u8 id = 0;
6666         int ret;
6667         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6668         return id;
6669 }
6670
6671 /**
6672  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6673  *  @sp : private member of the device structure, which is a pointer to the
6674  *  s2io_nic structure.
6675  *  Description:
6676  *  This function initializes a few of the PCI and PCI-X configuration registers
6677  *  with recommended values.
6678  *  Return value:
6679  *  void
6680  */
6681
6682 static void s2io_init_pci(nic_t * sp)
6683 {
6684         u16 pci_cmd = 0, pcix_cmd = 0;
6685
6686         /* Enable Data Parity Error Recovery in PCI-X command register. */
6687         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6688                              &(pcix_cmd));
6689         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6690                               (pcix_cmd | 1));
6691         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6692                              &(pcix_cmd));
6693
6694         /* Set the PErr Response bit in PCI command register. */
6695         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6696         pci_write_config_word(sp->pdev, PCI_COMMAND,
6697                               (pci_cmd | PCI_COMMAND_PARITY));
6698         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6699 }
6700
6701 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
6702 MODULE_LICENSE("GPL");
6703 MODULE_VERSION(DRV_VERSION);
6704
6705 module_param(tx_fifo_num, int, 0);
6706 module_param(rx_ring_num, int, 0);
6707 module_param(rx_ring_mode, int, 0);
6708 module_param_array(tx_fifo_len, uint, NULL, 0);
6709 module_param_array(rx_ring_sz, uint, NULL, 0);
6710 module_param_array(rts_frm_len, uint, NULL, 0);
6711 module_param(use_continuous_tx_intrs, int, 1);
6712 module_param(rmac_pause_time, int, 0);
6713 module_param(mc_pause_threshold_q0q3, int, 0);
6714 module_param(mc_pause_threshold_q4q7, int, 0);
6715 module_param(shared_splits, int, 0);
6716 module_param(tmac_util_period, int, 0);
6717 module_param(rmac_util_period, int, 0);
6718 module_param(bimodal, bool, 0);
6719 module_param(l3l4hdr_size, int , 0);
6720 #ifndef CONFIG_S2IO_NAPI
6721 module_param(indicate_max_pkts, int, 0);
6722 #endif
6723 module_param(rxsync_frequency, int, 0);
6724 module_param(intr_type, int, 0);
6725 module_param(lro, int, 0);
6726 module_param(lro_max_pkts, int, 0);
6727
6728 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6729 {
6730         if ( tx_fifo_num > 8) {
6731                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6732                          "supported\n");
6733                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6734                 tx_fifo_num = 8;
6735         }
6736         if ( rx_ring_num > 8) {
6737                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6738                          "supported\n");
6739                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6740                 rx_ring_num = 8;
6741         }
6742 #ifdef CONFIG_S2IO_NAPI
6743         if (*dev_intr_type != INTA) {
6744                 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
6745                           "MSI/MSI-X is enabled. Defaulting to INTA\n");
6746                 *dev_intr_type = INTA;
6747         }
6748 #endif
6749 #ifndef CONFIG_PCI_MSI
6750         if (*dev_intr_type != INTA) {
6751                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6752                           "MSI/MSI-X. Defaulting to INTA\n");
6753                 *dev_intr_type = INTA;
6754         }
6755 #else
6756         if (*dev_intr_type > MSI_X) {
6757                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6758                           "Defaulting to INTA\n");
6759                 *dev_intr_type = INTA;
6760         }
6761 #endif
6762         if ((*dev_intr_type == MSI_X) &&
6763                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6764                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6765                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6766                                         "Defaulting to INTA\n");
6767                 *dev_intr_type = INTA;
6768         }
6769         if (rx_ring_mode > 3) {
6770                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6771                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6772                 rx_ring_mode = 3;
6773         }
6774         return SUCCESS;
6775 }
6776
6777 /**
6778  *  s2io_init_nic - Initialization of the adapter .
6779  *  @pdev : structure containing the PCI related information of the device.
6780  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6781  *  Description:
6782  *  The function initializes an adapter identified by the pci_dec structure.
6783  *  All OS related initialization including memory and device structure and
6784  *  initlaization of the device private variable is done. Also the swapper
6785  *  control register is initialized to enable read and write into the I/O
6786  *  registers of the device.
6787  *  Return value:
6788  *  returns 0 on success and negative on failure.
6789  */
6790
6791 static int __devinit
6792 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6793 {
6794         nic_t *sp;
6795         struct net_device *dev;
6796         int i, j, ret;
6797         int dma_flag = FALSE;
6798         u32 mac_up, mac_down;
6799         u64 val64 = 0, tmp64 = 0;
6800         XENA_dev_config_t __iomem *bar0 = NULL;
6801         u16 subid;
6802         mac_info_t *mac_control;
6803         struct config_param *config;
6804         int mode;
6805         u8 dev_intr_type = intr_type;
6806
6807         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6808                 return ret;
6809
6810         if ((ret = pci_enable_device(pdev))) {
6811                 DBG_PRINT(ERR_DBG,
6812                           "s2io_init_nic: pci_enable_device failed\n");
6813                 return ret;
6814         }
6815
6816         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6817                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6818                 dma_flag = TRUE;
6819                 if (pci_set_consistent_dma_mask
6820                     (pdev, DMA_64BIT_MASK)) {
6821                         DBG_PRINT(ERR_DBG,
6822                                   "Unable to obtain 64bit DMA for \
6823                                         consistent allocations\n");
6824                         pci_disable_device(pdev);
6825                         return -ENOMEM;
6826                 }
6827         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6828                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6829         } else {
6830                 pci_disable_device(pdev);
6831                 return -ENOMEM;
6832         }
6833         if (dev_intr_type != MSI_X) {
6834                 if (pci_request_regions(pdev, s2io_driver_name)) {
6835                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
6836                             pci_disable_device(pdev);
6837                         return -ENODEV;
6838                 }
6839         }
6840         else {
6841                 if (!(request_mem_region(pci_resource_start(pdev, 0),
6842                          pci_resource_len(pdev, 0), s2io_driver_name))) {
6843                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6844                         pci_disable_device(pdev);
6845                         return -ENODEV;
6846                 }
6847                 if (!(request_mem_region(pci_resource_start(pdev, 2),
6848                          pci_resource_len(pdev, 2), s2io_driver_name))) {
6849                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6850                         release_mem_region(pci_resource_start(pdev, 0),
6851                                    pci_resource_len(pdev, 0));
6852                         pci_disable_device(pdev);
6853                         return -ENODEV;
6854                 }
6855         }
6856
6857         dev = alloc_etherdev(sizeof(nic_t));
6858         if (dev == NULL) {
6859                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6860                 pci_disable_device(pdev);
6861                 pci_release_regions(pdev);
6862                 return -ENODEV;
6863         }
6864
6865         pci_set_master(pdev);
6866         pci_set_drvdata(pdev, dev);
6867         SET_MODULE_OWNER(dev);
6868         SET_NETDEV_DEV(dev, &pdev->dev);
6869
6870         /*  Private member variable initialized to s2io NIC structure */
6871         sp = dev->priv;
6872         memset(sp, 0, sizeof(nic_t));
6873         sp->dev = dev;
6874         sp->pdev = pdev;
6875         sp->high_dma_flag = dma_flag;
6876         sp->device_enabled_once = FALSE;
6877         if (rx_ring_mode == 1)
6878                 sp->rxd_mode = RXD_MODE_1;
6879         if (rx_ring_mode == 2)
6880                 sp->rxd_mode = RXD_MODE_3B;
6881         if (rx_ring_mode == 3)
6882                 sp->rxd_mode = RXD_MODE_3A;
6883
6884         sp->intr_type = dev_intr_type;
6885
6886         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6887                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6888                 sp->device_type = XFRAME_II_DEVICE;
6889         else
6890                 sp->device_type = XFRAME_I_DEVICE;
6891
6892         sp->lro = lro;
6893
6894         /* Initialize some PCI/PCI-X fields of the NIC. */
6895         s2io_init_pci(sp);
6896
6897         /*
6898          * Setting the device configuration parameters.
6899          * Most of these parameters can be specified by the user during
6900          * module insertion as they are module loadable parameters. If
6901          * these parameters are not not specified during load time, they
6902          * are initialized with default values.
6903          */
6904         mac_control = &sp->mac_control;
6905         config = &sp->config;
6906
6907         /* Tx side parameters. */
6908         config->tx_fifo_num = tx_fifo_num;
6909         for (i = 0; i < MAX_TX_FIFOS; i++) {
6910                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6911                 config->tx_cfg[i].fifo_priority = i;
6912         }
6913
6914         /* mapping the QoS priority to the configured fifos */
6915         for (i = 0; i < MAX_TX_FIFOS; i++)
6916                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6917
6918         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6919         for (i = 0; i < config->tx_fifo_num; i++) {
6920                 config->tx_cfg[i].f_no_snoop =
6921                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6922                 if (config->tx_cfg[i].fifo_len < 65) {
6923                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6924                         break;
6925                 }
6926         }
6927         /* + 2 because one Txd for skb->data and one Txd for UFO */
6928         config->max_txds = MAX_SKB_FRAGS + 2;
6929
6930         /* Rx side parameters. */
6931         config->rx_ring_num = rx_ring_num;
6932         for (i = 0; i < MAX_RX_RINGS; i++) {
6933                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6934                     (rxd_count[sp->rxd_mode] + 1);
6935                 config->rx_cfg[i].ring_priority = i;
6936         }
6937
6938         for (i = 0; i < rx_ring_num; i++) {
6939                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6940                 config->rx_cfg[i].f_no_snoop =
6941                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6942         }
6943
6944         /*  Setting Mac Control parameters */
6945         mac_control->rmac_pause_time = rmac_pause_time;
6946         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6947         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6948
6949
6950         /* Initialize Ring buffer parameters. */
6951         for (i = 0; i < config->rx_ring_num; i++)
6952                 atomic_set(&sp->rx_bufs_left[i], 0);
6953
6954         /* Initialize the number of ISRs currently running */
6955         atomic_set(&sp->isr_cnt, 0);
6956
6957         /*  initialize the shared memory used by the NIC and the host */
6958         if (init_shared_mem(sp)) {
6959                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6960                           __FUNCTION__);
6961                 ret = -ENOMEM;
6962                 goto mem_alloc_failed;
6963         }
6964
6965         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6966                                      pci_resource_len(pdev, 0));
6967         if (!sp->bar0) {
6968                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6969                           dev->name);
6970                 ret = -ENOMEM;
6971                 goto bar0_remap_failed;
6972         }
6973
6974         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6975                                      pci_resource_len(pdev, 2));
6976         if (!sp->bar1) {
6977                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6978                           dev->name);
6979                 ret = -ENOMEM;
6980                 goto bar1_remap_failed;
6981         }
6982
6983         dev->irq = pdev->irq;
6984         dev->base_addr = (unsigned long) sp->bar0;
6985
6986         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6987         for (j = 0; j < MAX_TX_FIFOS; j++) {
6988                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6989                     (sp->bar1 + (j * 0x00020000));
6990         }
6991
6992         /*  Driver entry points */
6993         dev->open = &s2io_open;
6994         dev->stop = &s2io_close;
6995         dev->hard_start_xmit = &s2io_xmit;
6996         dev->get_stats = &s2io_get_stats;
6997         dev->set_multicast_list = &s2io_set_multicast;
6998         dev->do_ioctl = &s2io_ioctl;
6999         dev->change_mtu = &s2io_change_mtu;
7000         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7001         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7002         dev->vlan_rx_register = s2io_vlan_rx_register;
7003         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
7004
7005         /*
7006          * will use eth_mac_addr() for  dev->set_mac_address
7007          * mac address will be set every time dev->open() is called
7008          */
7009 #if defined(CONFIG_S2IO_NAPI)
7010         dev->poll = s2io_poll;
7011         dev->weight = 32;
7012 #endif
7013
7014 #ifdef CONFIG_NET_POLL_CONTROLLER
7015         dev->poll_controller = s2io_netpoll;
7016 #endif
7017
7018         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7019         if (sp->high_dma_flag == TRUE)
7020                 dev->features |= NETIF_F_HIGHDMA;
7021 #ifdef NETIF_F_TSO
7022         dev->features |= NETIF_F_TSO;
7023 #endif
7024 #ifdef NETIF_F_TSO6
7025         dev->features |= NETIF_F_TSO6;
7026 #endif
7027         if (sp->device_type & XFRAME_II_DEVICE) {
7028                 dev->features |= NETIF_F_UFO;
7029                 dev->features |= NETIF_F_HW_CSUM;
7030         }
7031
7032         dev->tx_timeout = &s2io_tx_watchdog;
7033         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7034         INIT_WORK(&sp->rst_timer_task,
7035                   (void (*)(void *)) s2io_restart_nic, dev);
7036         INIT_WORK(&sp->set_link_task,
7037                   (void (*)(void *)) s2io_set_link, sp);
7038
7039         pci_save_state(sp->pdev);
7040
7041         /* Setting swapper control on the NIC, for proper reset operation */
7042         if (s2io_set_swapper(sp)) {
7043                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7044                           dev->name);
7045                 ret = -EAGAIN;
7046                 goto set_swap_failed;
7047         }
7048
7049         /* Verify if the Herc works on the slot its placed into */
7050         if (sp->device_type & XFRAME_II_DEVICE) {
7051                 mode = s2io_verify_pci_mode(sp);
7052                 if (mode < 0) {
7053                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7054                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7055                         ret = -EBADSLT;
7056                         goto set_swap_failed;
7057                 }
7058         }
7059
7060         /* Not needed for Herc */
7061         if (sp->device_type & XFRAME_I_DEVICE) {
7062                 /*
7063                  * Fix for all "FFs" MAC address problems observed on
7064                  * Alpha platforms
7065                  */
7066                 fix_mac_address(sp);
7067                 s2io_reset(sp);
7068         }
7069
7070         /*
7071          * MAC address initialization.
7072          * For now only one mac address will be read and used.
7073          */
7074         bar0 = sp->bar0;
7075         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7076             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7077         writeq(val64, &bar0->rmac_addr_cmd_mem);
7078         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7079                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
7080         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7081         mac_down = (u32) tmp64;
7082         mac_up = (u32) (tmp64 >> 32);
7083
7084         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7085
7086         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7087         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7088         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7089         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7090         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7091         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7092
7093         /*  Set the factory defined MAC address initially   */
7094         dev->addr_len = ETH_ALEN;
7095         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7096
7097         /*
7098          * Initialize the tasklet status and link state flags
7099          * and the card state parameter
7100          */
7101         atomic_set(&(sp->card_state), 0);
7102         sp->tasklet_status = 0;
7103         sp->link_state = 0;
7104
7105         /* Initialize spinlocks */
7106         spin_lock_init(&sp->tx_lock);
7107 #ifndef CONFIG_S2IO_NAPI
7108         spin_lock_init(&sp->put_lock);
7109 #endif
7110         spin_lock_init(&sp->rx_lock);
7111
7112         /*
7113          * SXE-002: Configure link and activity LED to init state
7114          * on driver load.
7115          */
7116         subid = sp->pdev->subsystem_device;
7117         if ((subid & 0xFF) >= 0x07) {
7118                 val64 = readq(&bar0->gpio_control);
7119                 val64 |= 0x0000800000000000ULL;
7120                 writeq(val64, &bar0->gpio_control);
7121                 val64 = 0x0411040400000000ULL;
7122                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7123                 val64 = readq(&bar0->gpio_control);
7124         }
7125
7126         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7127
7128         if (register_netdev(dev)) {
7129                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7130                 ret = -ENODEV;
7131                 goto register_failed;
7132         }
7133         s2io_vpd_read(sp);
7134         DBG_PRINT(ERR_DBG, "%s: Neterion %s",dev->name, sp->product_name);
7135         DBG_PRINT(ERR_DBG, "(rev %d), Driver version %s\n",
7136                                 get_xena_rev_id(sp->pdev),
7137                                 s2io_driver_version);
7138         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
7139         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7140                           "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
7141                           sp->def_mac_addr[0].mac_addr[0],
7142                           sp->def_mac_addr[0].mac_addr[1],
7143                           sp->def_mac_addr[0].mac_addr[2],
7144                           sp->def_mac_addr[0].mac_addr[3],
7145                           sp->def_mac_addr[0].mac_addr[4],
7146                           sp->def_mac_addr[0].mac_addr[5]);
7147         if (sp->device_type & XFRAME_II_DEVICE) {
7148                 mode = s2io_print_pci_mode(sp);
7149                 if (mode < 0) {
7150                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7151                         ret = -EBADSLT;
7152                         unregister_netdev(dev);
7153                         goto set_swap_failed;
7154                 }
7155         }
7156         switch(sp->rxd_mode) {
7157                 case RXD_MODE_1:
7158                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7159                                                 dev->name);
7160                     break;
7161                 case RXD_MODE_3B:
7162                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7163                                                 dev->name);
7164                     break;
7165                 case RXD_MODE_3A:
7166                     DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7167                                                 dev->name);
7168                     break;
7169         }
7170 #ifdef CONFIG_S2IO_NAPI
7171         DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7172 #endif
7173         switch(sp->intr_type) {
7174                 case INTA:
7175                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7176                     break;
7177                 case MSI:
7178                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7179                     break;
7180                 case MSI_X:
7181                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7182                     break;
7183         }
7184         if (sp->lro)
7185                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7186                           dev->name);
7187
7188         /* Initialize device name */
7189         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7190
7191         /* Initialize bimodal Interrupts */
7192         sp->config.bimodal = bimodal;
7193         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7194                 sp->config.bimodal = 0;
7195                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7196                         dev->name);
7197         }
7198
7199         /*
7200          * Make Link state as off at this point, when the Link change
7201          * interrupt comes the state will be automatically changed to
7202          * the right state.
7203          */
7204         netif_carrier_off(dev);
7205
7206         return 0;
7207
7208       register_failed:
7209       set_swap_failed:
7210         iounmap(sp->bar1);
7211       bar1_remap_failed:
7212         iounmap(sp->bar0);
7213       bar0_remap_failed:
7214       mem_alloc_failed:
7215         free_shared_mem(sp);
7216         pci_disable_device(pdev);
7217         if (dev_intr_type != MSI_X)
7218                 pci_release_regions(pdev);
7219         else {
7220                 release_mem_region(pci_resource_start(pdev, 0),
7221                         pci_resource_len(pdev, 0));
7222                 release_mem_region(pci_resource_start(pdev, 2),
7223                         pci_resource_len(pdev, 2));
7224         }
7225         pci_set_drvdata(pdev, NULL);
7226         free_netdev(dev);
7227
7228         return ret;
7229 }
7230
7231 /**
7232  * s2io_rem_nic - Free the PCI device
7233  * @pdev: structure containing the PCI related information of the device.
7234  * Description: This function is called by the Pci subsystem to release a
7235  * PCI device and free up all resource held up by the device. This could
7236  * be in response to a Hot plug event or when the driver is to be removed
7237  * from memory.
7238  */
7239
7240 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7241 {
7242         struct net_device *dev =
7243             (struct net_device *) pci_get_drvdata(pdev);
7244         nic_t *sp;
7245
7246         if (dev == NULL) {
7247                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7248                 return;
7249         }
7250
7251         sp = dev->priv;
7252         unregister_netdev(dev);
7253
7254         free_shared_mem(sp);
7255         iounmap(sp->bar0);
7256         iounmap(sp->bar1);
7257         pci_disable_device(pdev);
7258         if (sp->intr_type != MSI_X)
7259                 pci_release_regions(pdev);
7260         else {
7261                 release_mem_region(pci_resource_start(pdev, 0),
7262                         pci_resource_len(pdev, 0));
7263                 release_mem_region(pci_resource_start(pdev, 2),
7264                         pci_resource_len(pdev, 2));
7265         }
7266         pci_set_drvdata(pdev, NULL);
7267         free_netdev(dev);
7268 }
7269
7270 /**
7271  * s2io_starter - Entry point for the driver
7272  * Description: This function is the entry point for the driver. It verifies
7273  * the module loadable parameters and initializes PCI configuration space.
7274  */
7275
7276 int __init s2io_starter(void)
7277 {
7278         return pci_module_init(&s2io_driver);
7279 }
7280
7281 /**
7282  * s2io_closer - Cleanup routine for the driver
7283  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7284  */
7285
7286 static void s2io_closer(void)
7287 {
7288         pci_unregister_driver(&s2io_driver);
7289         DBG_PRINT(INIT_DBG, "cleanup done\n");
7290 }
7291
7292 module_init(s2io_starter);
7293 module_exit(s2io_closer);
7294
7295 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7296                 struct tcphdr **tcp, RxD_t *rxdp)
7297 {
7298         int ip_off;
7299         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7300
7301         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7302                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7303                           __FUNCTION__);
7304                 return -1;
7305         }
7306
7307         /* TODO:
7308          * By default the VLAN field in the MAC is stripped by the card, if this
7309          * feature is turned off in rx_pa_cfg register, then the ip_off field
7310          * has to be shifted by a further 2 bytes
7311          */
7312         switch (l2_type) {
7313                 case 0: /* DIX type */
7314                 case 4: /* DIX type with VLAN */
7315                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7316                         break;
7317                 /* LLC, SNAP etc are considered non-mergeable */
7318                 default:
7319                         return -1;
7320         }
7321
7322         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7323         ip_len = (u8)((*ip)->ihl);
7324         ip_len <<= 2;
7325         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7326
7327         return 0;
7328 }
7329
7330 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7331                                   struct tcphdr *tcp)
7332 {
7333         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7334         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7335            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7336                 return -1;
7337         return 0;
7338 }
7339
7340 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7341 {
7342         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7343 }
7344
7345 static void initiate_new_session(lro_t *lro, u8 *l2h,
7346                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7347 {
7348         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7349         lro->l2h = l2h;
7350         lro->iph = ip;
7351         lro->tcph = tcp;
7352         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7353         lro->tcp_ack = ntohl(tcp->ack_seq);
7354         lro->sg_num = 1;
7355         lro->total_len = ntohs(ip->tot_len);
7356         lro->frags_len = 0;
7357         /*
7358          * check if we saw TCP timestamp. Other consistency checks have
7359          * already been done.
7360          */
7361         if (tcp->doff == 8) {
7362                 u32 *ptr;
7363                 ptr = (u32 *)(tcp+1);
7364                 lro->saw_ts = 1;
7365                 lro->cur_tsval = *(ptr+1);
7366                 lro->cur_tsecr = *(ptr+2);
7367         }
7368         lro->in_use = 1;
7369 }
7370
7371 static void update_L3L4_header(nic_t *sp, lro_t *lro)
7372 {
7373         struct iphdr *ip = lro->iph;
7374         struct tcphdr *tcp = lro->tcph;
7375         u16 nchk;
7376         StatInfo_t *statinfo = sp->mac_control.stats_info;
7377         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7378
7379         /* Update L3 header */
7380         ip->tot_len = htons(lro->total_len);
7381         ip->check = 0;
7382         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7383         ip->check = nchk;
7384
7385         /* Update L4 header */
7386         tcp->ack_seq = lro->tcp_ack;
7387         tcp->window = lro->window;
7388
7389         /* Update tsecr field if this session has timestamps enabled */
7390         if (lro->saw_ts) {
7391                 u32 *ptr = (u32 *)(tcp + 1);
7392                 *(ptr+2) = lro->cur_tsecr;
7393         }
7394
7395         /* Update counters required for calculation of
7396          * average no. of packets aggregated.
7397          */
7398         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7399         statinfo->sw_stat.num_aggregations++;
7400 }
7401
7402 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7403                 struct tcphdr *tcp, u32 l4_pyld)
7404 {
7405         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7406         lro->total_len += l4_pyld;
7407         lro->frags_len += l4_pyld;
7408         lro->tcp_next_seq += l4_pyld;
7409         lro->sg_num++;
7410
7411         /* Update ack seq no. and window ad(from this pkt) in LRO object */
7412         lro->tcp_ack = tcp->ack_seq;
7413         lro->window = tcp->window;
7414
7415         if (lro->saw_ts) {
7416                 u32 *ptr;
7417                 /* Update tsecr and tsval from this packet */
7418                 ptr = (u32 *) (tcp + 1);
7419                 lro->cur_tsval = *(ptr + 1);
7420                 lro->cur_tsecr = *(ptr + 2);
7421         }
7422 }
7423
7424 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7425                                     struct tcphdr *tcp, u32 tcp_pyld_len)
7426 {
7427         u8 *ptr;
7428
7429         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7430
7431         if (!tcp_pyld_len) {
7432                 /* Runt frame or a pure ack */
7433                 return -1;
7434         }
7435
7436         if (ip->ihl != 5) /* IP has options */
7437                 return -1;
7438
7439         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7440                                                                 !tcp->ack) {
7441                 /*
7442                  * Currently recognize only the ack control word and
7443                  * any other control field being set would result in
7444                  * flushing the LRO session
7445                  */
7446                 return -1;
7447         }
7448
7449         /*
7450          * Allow only one TCP timestamp option. Don't aggregate if
7451          * any other options are detected.
7452          */
7453         if (tcp->doff != 5 && tcp->doff != 8)
7454                 return -1;
7455
7456         if (tcp->doff == 8) {
7457                 ptr = (u8 *)(tcp + 1);
7458                 while (*ptr == TCPOPT_NOP)
7459                         ptr++;
7460                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7461                         return -1;
7462
7463                 /* Ensure timestamp value increases monotonically */
7464                 if (l_lro)
7465                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7466                                 return -1;
7467
7468                 /* timestamp echo reply should be non-zero */
7469                 if (*((u32 *)(ptr+6)) == 0)
7470                         return -1;
7471         }
7472
7473         return 0;
7474 }
7475
7476 static int
7477 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7478                       RxD_t *rxdp, nic_t *sp)
7479 {
7480         struct iphdr *ip;
7481         struct tcphdr *tcph;
7482         int ret = 0, i;
7483
7484         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7485                                          rxdp))) {
7486                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7487                           ip->saddr, ip->daddr);
7488         } else {
7489                 return ret;
7490         }
7491
7492         tcph = (struct tcphdr *)*tcp;
7493         *tcp_len = get_l4_pyld_length(ip, tcph);
7494         for (i=0; i<MAX_LRO_SESSIONS; i++) {
7495                 lro_t *l_lro = &sp->lro0_n[i];
7496                 if (l_lro->in_use) {
7497                         if (check_for_socket_match(l_lro, ip, tcph))
7498                                 continue;
7499                         /* Sock pair matched */
7500                         *lro = l_lro;
7501
7502                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7503                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7504                                           "0x%x, actual 0x%x\n", __FUNCTION__,
7505                                           (*lro)->tcp_next_seq,
7506                                           ntohl(tcph->seq));
7507
7508                                 sp->mac_control.stats_info->
7509                                    sw_stat.outof_sequence_pkts++;
7510                                 ret = 2;
7511                                 break;
7512                         }
7513
7514                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7515                                 ret = 1; /* Aggregate */
7516                         else
7517                                 ret = 2; /* Flush both */
7518                         break;
7519                 }
7520         }
7521
7522         if (ret == 0) {
7523                 /* Before searching for available LRO objects,
7524                  * check if the pkt is L3/L4 aggregatable. If not
7525                  * don't create new LRO session. Just send this
7526                  * packet up.
7527                  */
7528                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7529                         return 5;
7530                 }
7531
7532                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7533                         lro_t *l_lro = &sp->lro0_n[i];
7534                         if (!(l_lro->in_use)) {
7535                                 *lro = l_lro;
7536                                 ret = 3; /* Begin anew */
7537                                 break;
7538                         }
7539                 }
7540         }
7541
7542         if (ret == 0) { /* sessions exceeded */
7543                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7544                           __FUNCTION__);
7545                 *lro = NULL;
7546                 return ret;
7547         }
7548
7549         switch (ret) {
7550                 case 3:
7551                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7552                         break;
7553                 case 2:
7554                         update_L3L4_header(sp, *lro);
7555                         break;
7556                 case 1:
7557                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7558                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7559                                 update_L3L4_header(sp, *lro);
7560                                 ret = 4; /* Flush the LRO */
7561                         }
7562                         break;
7563                 default:
7564                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7565                                 __FUNCTION__);
7566                         break;
7567         }
7568
7569         return ret;
7570 }
7571
7572 static void clear_lro_session(lro_t *lro)
7573 {
7574         static u16 lro_struct_size = sizeof(lro_t);
7575
7576         memset(lro, 0, lro_struct_size);
7577 }
7578
7579 static void queue_rx_frame(struct sk_buff *skb)
7580 {
7581         struct net_device *dev = skb->dev;
7582
7583         skb->protocol = eth_type_trans(skb, dev);
7584 #ifdef CONFIG_S2IO_NAPI
7585         netif_receive_skb(skb);
7586 #else
7587         netif_rx(skb);
7588 #endif
7589 }
7590
7591 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7592                            u32 tcp_len)
7593 {
7594         struct sk_buff *tmp, *first = lro->parent;
7595
7596         first->len += tcp_len;
7597         first->data_len = lro->frags_len;
7598         skb_pull(skb, (skb->len - tcp_len));
7599         if ((tmp = skb_shinfo(first)->frag_list)) {
7600                 while (tmp->next)
7601                         tmp = tmp->next;
7602                 tmp->next = skb;
7603         }
7604         else
7605                 skb_shinfo(first)->frag_list = skb;
7606         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7607         return;
7608 }