drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #define RTL8169_VERSION "2.3LK-NAPI"
  35 #define MODULENAME "r8169"
  36 #define PFX MODULENAME ": "
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  41
  42 #ifdef RTL8169_DEBUG
  43 #define assert(expr) \
  44         if (!(expr)) {                                  \
  45                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  46                 #expr,__FILE__,__func__,__LINE__);              \
  47         }
  48 #define dprintk(fmt, args...) \
  49         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  50 #else
  51 #define assert(expr) do {} while (0)
  52 #define dprintk(fmt, args...)   do {} while (0)
  53 #endif /* RTL8169_DEBUG */
  54
  55 #define R8169_MSG_DEFAULT \
  56         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  57
  58 #define TX_BUFFS_AVAIL(tp) \
  59         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 /* MAC address length */
  66 #define MAC_ADDR_LEN    6
  67
  68 #define MAX_READ_REQUEST_SHIFT  12
  69 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  70 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  71 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  72 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  73 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  74
  75 #define R8169_REGS_SIZE         256
  76 #define R8169_NAPI_WEIGHT       64
  77 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  78 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  79 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  80 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  81 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  82
  83 #define RTL8169_TX_TIMEOUT      (6*HZ)
  84 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  85
  86 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  87 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  88 #define RTL_EEPROM_SIG_ADDR     0x0000
  89
  90 /* write/read MMIO register */
  91 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  92 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  93 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  94 #define RTL_R8(reg)             readb (ioaddr + (reg))
  95 #define RTL_R16(reg)            readw (ioaddr + (reg))
  96 #define RTL_R32(reg)            readl (ioaddr + (reg))
  97
  98 enum mac_version {
  99         RTL_GIGA_MAC_NONE   = 0x00,
 100         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 101         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 102         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 103         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 104         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 105         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 106         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 107         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 108         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 109         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 110         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 111         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 112         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 113         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 114         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 115         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 116         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 117         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 118         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 119         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 120         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 121         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 122         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 123         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 124         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 125         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 126         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
 127         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 128         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
 129         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
 130         RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
 131 };
 132
 133 #define _R(NAME,MAC,MASK) \
 134         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 135
 136 static const struct {
 137         const char *name;
 138         u8 mac_version;
 139         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 140 } rtl_chip_info[] = {
 141         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 142         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 143         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 144         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 145         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 146         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 147         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 148         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 149         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 150         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 151         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 152         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 153         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 154         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 155         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 156         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 157         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 158         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 159         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 160         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 161         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 162         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 163         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 164         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 165         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 166         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 167         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
 168         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
 169         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
 170         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E
 171         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_31, 0xff7e1880)  // PCI-E
 172 };
 173 #undef _R
 174
 175 enum cfg_version {
 176         RTL_CFG_0 = 0x00,
 177         RTL_CFG_1,
 178         RTL_CFG_2
 179 };
 180
 181 static void rtl_hw_start_8169(struct net_device *);
 182 static void rtl_hw_start_8168(struct net_device *);
 183 static void rtl_hw_start_8101(struct net_device *);
 184
 185 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 186         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 187         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 188         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 189         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 190         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 191         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 192         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 193         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 194         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 195                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 196         { 0x0001,                               0x8168,
 197                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 198         {0,},
 199 };
 200
 201 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 202
 203 static int rx_buf_sz = 16383;
 204 static int use_dac;
 205 static struct {
 206         u32 msg_enable;
 207 } debug = { -1 };
 208
 209 enum rtl_registers {
 210         MAC0            = 0,    /* Ethernet hardware address. */
 211         MAC4            = 4,
 212         MAR0            = 8,    /* Multicast filter. */
 213         CounterAddrLow          = 0x10,
 214         CounterAddrHigh         = 0x14,
 215         TxDescStartAddrLow      = 0x20,
 216         TxDescStartAddrHigh     = 0x24,
 217         TxHDescStartAddrLow     = 0x28,
 218         TxHDescStartAddrHigh    = 0x2c,
 219         FLASH           = 0x30,
 220         ERSR            = 0x36,
 221         ChipCmd         = 0x37,
 222         TxPoll          = 0x38,
 223         IntrMask        = 0x3c,
 224         IntrStatus      = 0x3e,
 225         TxConfig        = 0x40,
 226         RxConfig        = 0x44,
 227         RxMissed        = 0x4c,
 228         Cfg9346         = 0x50,
 229         Config0         = 0x51,
 230         Config1         = 0x52,
 231         Config2         = 0x53,
 232         Config3         = 0x54,
 233         Config4         = 0x55,
 234         Config5         = 0x56,
 235         MultiIntr       = 0x5c,
 236         PHYAR           = 0x60,
 237         PHYstatus       = 0x6c,
 238         RxMaxSize       = 0xda,
 239         CPlusCmd        = 0xe0,
 240         IntrMitigate    = 0xe2,
 241         RxDescAddrLow   = 0xe4,
 242         RxDescAddrHigh  = 0xe8,
 243         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 244
 245 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 246
 247         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 248
 249 #define TxPacketMax     (8064 >> 7)
 250
 251         FuncEvent       = 0xf0,
 252         FuncEventMask   = 0xf4,
 253         FuncPresetState = 0xf8,
 254         FuncForceEvent  = 0xfc,
 255 };
 256
 257 enum rtl8110_registers {
 258         TBICSR                  = 0x64,
 259         TBI_ANAR                = 0x68,
 260         TBI_LPAR                = 0x6a,
 261 };
 262
 263 enum rtl8168_8101_registers {
 264         CSIDR                   = 0x64,
 265         CSIAR                   = 0x68,
 266 #define CSIAR_FLAG                      0x80000000
 267 #define CSIAR_WRITE_CMD                 0x80000000
 268 #define CSIAR_BYTE_ENABLE               0x0f
 269 #define CSIAR_BYTE_ENABLE_SHIFT         12
 270 #define CSIAR_ADDR_MASK                 0x0fff
 271         PMCH                    = 0x6f,
 272         EPHYAR                  = 0x80,
 273 #define EPHYAR_FLAG                     0x80000000
 274 #define EPHYAR_WRITE_CMD                0x80000000
 275 #define EPHYAR_REG_MASK                 0x1f
 276 #define EPHYAR_REG_SHIFT                16
 277 #define EPHYAR_DATA_MASK                0xffff
 278         DLLPR                   = 0xd0,
 279 #define PM_SWITCH                       (1 << 6)
 280         DBG_REG                 = 0xd1,
 281 #define FIX_NAK_1                       (1 << 4)
 282 #define FIX_NAK_2                       (1 << 3)
 283         TWSI                    = 0xd2,
 284         MCU                     = 0xd3,
 285 #define EN_NDP                          (1 << 3)
 286 #define EN_OOB_RESET                    (1 << 2)
 287         EFUSEAR                 = 0xdc,
 288 #define EFUSEAR_FLAG                    0x80000000
 289 #define EFUSEAR_WRITE_CMD               0x80000000
 290 #define EFUSEAR_READ_CMD                0x00000000
 291 #define EFUSEAR_REG_MASK                0x03ff
 292 #define EFUSEAR_REG_SHIFT               8
 293 #define EFUSEAR_DATA_MASK               0xff
 294 };
 295
 296 enum rtl8168_registers {
 297         ERIDR                   = 0x70,
 298         ERIAR                   = 0x74,
 299 #define ERIAR_FLAG                      0x80000000
 300 #define ERIAR_WRITE_CMD                 0x80000000
 301 #define ERIAR_READ_CMD                  0x00000000
 302 #define ERIAR_ADDR_BYTE_ALIGN           4
 303 #define ERIAR_EXGMAC                    0
 304 #define ERIAR_MSIX                      1
 305 #define ERIAR_ASF                       2
 306 #define ERIAR_TYPE_SHIFT                16
 307 #define ERIAR_BYTEEN                    0x0f
 308 #define ERIAR_BYTEEN_SHIFT              12
 309         EPHY_RXER_NUM           = 0x7c,
 310         OCPDR                   = 0xb0, /* OCP GPHY access */
 311 #define OCPDR_WRITE_CMD                 0x80000000
 312 #define OCPDR_READ_CMD                  0x00000000
 313 #define OCPDR_REG_MASK                  0x7f
 314 #define OCPDR_GPHY_REG_SHIFT            16
 315 #define OCPDR_DATA_MASK                 0xffff
 316         OCPAR                   = 0xb4,
 317 #define OCPAR_FLAG                      0x80000000
 318 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 319 #define OCPAR_GPHY_READ_CMD             0x0000f060
 320         RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
 321 };
 322
 323 enum rtl_register_content {
 324         /* InterruptStatusBits */
 325         SYSErr          = 0x8000,
 326         PCSTimeout      = 0x4000,
 327         SWInt           = 0x0100,
 328         TxDescUnavail   = 0x0080,
 329         RxFIFOOver      = 0x0040,
 330         LinkChg         = 0x0020,
 331         RxOverflow      = 0x0010,
 332         TxErr           = 0x0008,
 333         TxOK            = 0x0004,
 334         RxErr           = 0x0002,
 335         RxOK            = 0x0001,
 336
 337         /* RxStatusDesc */
 338         RxFOVF  = (1 << 23),
 339         RxRWT   = (1 << 22),
 340         RxRES   = (1 << 21),
 341         RxRUNT  = (1 << 20),
 342         RxCRC   = (1 << 19),
 343
 344         /* ChipCmdBits */
 345         CmdReset        = 0x10,
 346         CmdRxEnb        = 0x08,
 347         CmdTxEnb        = 0x04,
 348         RxBufEmpty      = 0x01,
 349
 350         /* TXPoll register p.5 */
 351         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 352         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 353         FSWInt          = 0x01,         /* Forced software interrupt */
 354
 355         /* Cfg9346Bits */
 356         Cfg9346_Lock    = 0x00,
 357         Cfg9346_Unlock  = 0xc0,
 358
 359         /* rx_mode_bits */
 360         AcceptErr       = 0x20,
 361         AcceptRunt      = 0x10,
 362         AcceptBroadcast = 0x08,
 363         AcceptMulticast = 0x04,
 364         AcceptMyPhys    = 0x02,
 365         AcceptAllPhys   = 0x01,
 366
 367         /* RxConfigBits */
 368         RxCfgFIFOShift  = 13,
 369         RxCfgDMAShift   =  8,
 370
 371         /* TxConfigBits */
 372         TxInterFrameGapShift = 24,
 373         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 374
 375         /* Config1 register p.24 */
 376         LEDS1           = (1 << 7),
 377         LEDS0           = (1 << 6),
 378         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 379         Speed_down      = (1 << 4),
 380         MEMMAP          = (1 << 3),
 381         IOMAP           = (1 << 2),
 382         VPD             = (1 << 1),
 383         PMEnable        = (1 << 0),     /* Power Management Enable */
 384
 385         /* Config2 register p. 25 */
 386         PCI_Clock_66MHz = 0x01,
 387         PCI_Clock_33MHz = 0x00,
 388
 389         /* Config3 register p.25 */
 390         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 391         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 392         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 393
 394         /* Config5 register p.27 */
 395         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 396         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 397         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 398         LanWake         = (1 << 1),     /* LanWake enable/disable */
 399         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 400
 401         /* TBICSR p.28 */
 402         TBIReset        = 0x80000000,
 403         TBILoopback     = 0x40000000,
 404         TBINwEnable     = 0x20000000,
 405         TBINwRestart    = 0x10000000,
 406         TBILinkOk       = 0x02000000,
 407         TBINwComplete   = 0x01000000,
 408
 409         /* CPlusCmd p.31 */
 410         EnableBist      = (1 << 15),    // 8168 8101
 411         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 412         Normal_mode     = (1 << 13),    // unused
 413         Force_half_dup  = (1 << 12),    // 8168 8101
 414         Force_rxflow_en = (1 << 11),    // 8168 8101
 415         Force_txflow_en = (1 << 10),    // 8168 8101
 416         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 417         ASF             = (1 << 8),     // 8168 8101
 418         PktCntrDisable  = (1 << 7),     // 8168 8101
 419         Mac_dbgo_sel    = 0x001c,       // 8168
 420         RxVlan          = (1 << 6),
 421         RxChkSum        = (1 << 5),
 422         PCIDAC          = (1 << 4),
 423         PCIMulRW        = (1 << 3),
 424         INTT_0          = 0x0000,       // 8168
 425         INTT_1          = 0x0001,       // 8168
 426         INTT_2          = 0x0002,       // 8168
 427         INTT_3          = 0x0003,       // 8168
 428
 429         /* rtl8169_PHYstatus */
 430         TBI_Enable      = 0x80,
 431         TxFlowCtrl      = 0x40,
 432         RxFlowCtrl      = 0x20,
 433         _1000bpsF       = 0x10,
 434         _100bps         = 0x08,
 435         _10bps          = 0x04,
 436         LinkStatus      = 0x02,
 437         FullDup         = 0x01,
 438
 439         /* _TBICSRBit */
 440         TBILinkOK       = 0x02000000,
 441
 442         /* DumpCounterCommand */
 443         CounterDump     = 0x8,
 444 };
 445
 446 enum desc_status_bit {
 447         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 448         RingEnd         = (1 << 30), /* End of descriptor ring */
 449         FirstFrag       = (1 << 29), /* First segment of a packet */
 450         LastFrag        = (1 << 28), /* Final segment of a packet */
 451
 452         /* Tx private */
 453         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 454         MSSShift        = 16,        /* MSS value position */
 455         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 456         IPCS            = (1 << 18), /* Calculate IP checksum */
 457         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 458         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 459         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 460
 461         /* Rx private */
 462         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 463         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 464
 465 #define RxProtoUDP      (PID1)
 466 #define RxProtoTCP      (PID0)
 467 #define RxProtoIP       (PID1 | PID0)
 468 #define RxProtoMask     RxProtoIP
 469
 470         IPFail          = (1 << 16), /* IP checksum failed */
 471         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 472         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 473         RxVlanTag       = (1 << 16), /* VLAN tag available */
 474 };
 475
 476 #define RsvdMask        0x3fffc000
 477
 478 struct TxDesc {
 479         __le32 opts1;
 480         __le32 opts2;
 481         __le64 addr;
 482 };
 483
 484 struct RxDesc {
 485         __le32 opts1;
 486         __le32 opts2;
 487         __le64 addr;
 488 };
 489
 490 struct ring_info {
 491         struct sk_buff  *skb;
 492         u32             len;
 493         u8              __pad[sizeof(void *) - sizeof(u32)];
 494 };
 495
 496 enum features {
 497         RTL_FEATURE_WOL         = (1 << 0),
 498         RTL_FEATURE_MSI         = (1 << 1),
 499         RTL_FEATURE_GMII        = (1 << 2),
 500 };
 501
 502 struct rtl8169_counters {
 503         __le64  tx_packets;
 504         __le64  rx_packets;
 505         __le64  tx_errors;
 506         __le32  rx_errors;
 507         __le16  rx_missed;
 508         __le16  align_errors;
 509         __le32  tx_one_collision;
 510         __le32  tx_multi_collision;
 511         __le64  rx_unicast;
 512         __le64  rx_broadcast;
 513         __le32  rx_multicast;
 514         __le16  tx_aborted;
 515         __le16  tx_underun;
 516 };
 517
 518 struct rtl8169_private {
 519         void __iomem *mmio_addr;        /* memory map physical address */
 520         struct pci_dev *pci_dev;        /* Index of PCI device */
 521         struct net_device *dev;
 522         struct napi_struct napi;
 523         spinlock_t lock;                /* spin lock flag */
 524         u32 msg_enable;
 525         int chipset;
 526         int mac_version;
 527         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 528         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 529         u32 dirty_rx;
 530         u32 dirty_tx;
 531         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 532         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 533         dma_addr_t TxPhyAddr;
 534         dma_addr_t RxPhyAddr;
 535         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 536         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 537         struct timer_list timer;
 538         u16 cp_cmd;
 539         u16 intr_event;
 540         u16 napi_event;
 541         u16 intr_mask;
 542         int phy_1000_ctrl_reg;
 543
 544         struct mdio_ops {
 545                 void (*write)(void __iomem *, int, int);
 546                 int (*read)(void __iomem *, int);
 547         } mdio_ops;
 548
 549         struct pll_power_ops {
 550                 void (*down)(struct rtl8169_private *);
 551                 void (*up)(struct rtl8169_private *);
 552         } pll_power_ops;
 553
 554         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 555         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 556         void (*phy_reset_enable)(struct rtl8169_private *tp);
 557         void (*hw_start)(struct net_device *);
 558         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 559         unsigned int (*link_ok)(void __iomem *);
 560         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 561         int pcie_cap;
 562         struct delayed_work task;
 563         unsigned features;
 564
 565         struct mii_if_info mii;
 566         struct rtl8169_counters counters;
 567         u32 saved_wolopts;
 568
 569         const struct firmware *fw;
 570 };
 571
 572 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 573 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 574 module_param(use_dac, int, 0);
 575 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 576 module_param_named(debug, debug.msg_enable, int, 0);
 577 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 578 MODULE_LICENSE("GPL");
 579 MODULE_VERSION(RTL8169_VERSION);
 580 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 581 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 582 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 583
 584 static int rtl8169_open(struct net_device *dev);
 585 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 586                                       struct net_device *dev);
 587 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 588 static int rtl8169_init_ring(struct net_device *dev);
 589 static void rtl_hw_start(struct net_device *dev);
 590 static int rtl8169_close(struct net_device *dev);
 591 static void rtl_set_rx_mode(struct net_device *dev);
 592 static void rtl8169_tx_timeout(struct net_device *dev);
 593 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 594 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 595                                 void __iomem *, u32 budget);
 596 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 597 static void rtl8169_down(struct net_device *dev);
 598 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 599 static int rtl8169_poll(struct napi_struct *napi, int budget);
 600
 601 static const unsigned int rtl8169_rx_config =
 602         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 603
 604 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 605 {
 606         void __iomem *ioaddr = tp->mmio_addr;
 607         int i;
 608
 609         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 610         for (i = 0; i < 20; i++) {
 611                 udelay(100);
 612                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 613                         break;
 614         }
 615         return RTL_R32(OCPDR);
 616 }
 617
 618 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 619 {
 620         void __iomem *ioaddr = tp->mmio_addr;
 621         int i;
 622
 623         RTL_W32(OCPDR, data);
 624         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 625         for (i = 0; i < 20; i++) {
 626                 udelay(100);
 627                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 628                         break;
 629         }
 630 }
 631
 632 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 633 {
 634         void __iomem *ioaddr = tp->mmio_addr;
 635         int i;
 636
 637         RTL_W8(ERIDR, cmd);
 638         RTL_W32(ERIAR, 0x800010e8);
 639         msleep(2);
 640         for (i = 0; i < 5; i++) {
 641                 udelay(100);
 642                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 643                         break;
 644         }
 645
 646         ocp_write(tp, 0x1, 0x30, 0x00000001);
 647 }
 648
 649 #define OOB_CMD_RESET           0x00
 650 #define OOB_CMD_DRIVER_START    0x05
 651 #define OOB_CMD_DRIVER_STOP     0x06
 652
 653 static void rtl8168_driver_start(struct rtl8169_private *tp)
 654 {
 655         int i;
 656         u32 reg;
 657
 658         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 659
 660         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 661                 reg = 0xb8;
 662         else
 663                 reg = 0x10;
 664
 665         for (i = 0; i < 10; i++) {
 666                 msleep(10);
 667                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 668                         break;
 669         }
 670 }
 671
 672 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 673 {
 674         int i;
 675         u32 reg;
 676
 677         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 678
 679         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 680                 reg = 0xb8;
 681         else
 682                 reg = 0x10;
 683
 684         for (i = 0; i < 10; i++) {
 685                 msleep(10);
 686                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 687                         break;
 688         }
 689 }
 690
 691 static int r8168dp_check_dash(struct rtl8169_private *tp)
 692 {
 693         u32 reg;
 694
 695         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 696                 reg = 0xb8;
 697         else
 698                 reg = 0x10;
 699
 700         if (ocp_read(tp, 0xF, reg) & 0x00008000)
 701                 return 1;
 702         else
 703                 return 0;
 704 }
 705
 706 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 707 {
 708         int i;
 709
 710         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 711
 712         for (i = 20; i > 0; i--) {
 713                 /*
 714                  * Check if the RTL8169 has completed writing to the specified
 715                  * MII register.
 716                  */
 717                 if (!(RTL_R32(PHYAR) & 0x80000000))
 718                         break;
 719                 udelay(25);
 720         }
 721         /*
 722          * According to hardware specs a 20us delay is required after write
 723          * complete indication, but before sending next command.
 724          */
 725         udelay(20);
 726 }
 727
 728 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 729 {
 730         int i, value = -1;
 731
 732         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 733
 734         for (i = 20; i > 0; i--) {
 735                 /*
 736                  * Check if the RTL8169 has completed retrieving data from
 737                  * the specified MII register.
 738                  */
 739                 if (RTL_R32(PHYAR) & 0x80000000) {
 740                         value = RTL_R32(PHYAR) & 0xffff;
 741                         break;
 742                 }
 743                 udelay(25);
 744         }
 745         /*
 746          * According to hardware specs a 20us delay is required after read
 747          * complete indication, but before sending next command.
 748          */
 749         udelay(20);
 750
 751         return value;
 752 }
 753
 754 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 755 {
 756         int i;
 757
 758         RTL_W32(OCPDR, data |
 759                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 760         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 761         RTL_W32(EPHY_RXER_NUM, 0);
 762
 763         for (i = 0; i < 100; i++) {
 764                 mdelay(1);
 765                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 766                         break;
 767         }
 768 }
 769
 770 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 771 {
 772         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 773                 (value & OCPDR_DATA_MASK));
 774 }
 775
 776 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 777 {
 778         int i;
 779
 780         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 781
 782         mdelay(1);
 783         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 784         RTL_W32(EPHY_RXER_NUM, 0);
 785
 786         for (i = 0; i < 100; i++) {
 787                 mdelay(1);
 788                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 789                         break;
 790         }
 791
 792         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 793 }
 794
 795 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 796
 797 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 798 {
 799         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 800 }
 801
 802 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 803 {
 804         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 805 }
 806
 807 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 808 {
 809         r8168dp_2_mdio_start(ioaddr);
 810
 811         r8169_mdio_write(ioaddr, reg_addr, value);
 812
 813         r8168dp_2_mdio_stop(ioaddr);
 814 }
 815
 816 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 817 {
 818         int value;
 819
 820         r8168dp_2_mdio_start(ioaddr);
 821
 822         value = r8169_mdio_read(ioaddr, reg_addr);
 823
 824         r8168dp_2_mdio_stop(ioaddr);
 825
 826         return value;
 827 }
 828
 829 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 830 {
 831         tp->mdio_ops.write(tp->mmio_addr, location, val);
 832 }
 833
 834 static int rtl_readphy(struct rtl8169_private *tp, int location)
 835 {
 836         return tp->mdio_ops.read(tp->mmio_addr, location);
 837 }
 838
 839 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 840 {
 841         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 842 }
 843
 844 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 845 {
 846         int val;
 847
 848         val = rtl_readphy(tp, reg_addr);
 849         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 850 }
 851
 852 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 853                            int val)
 854 {
 855         struct rtl8169_private *tp = netdev_priv(dev);
 856
 857         rtl_writephy(tp, location, val);
 858 }
 859
 860 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 861 {
 862         struct rtl8169_private *tp = netdev_priv(dev);
 863
 864         return rtl_readphy(tp, location);
 865 }
 866
 867 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 868 {
 869         unsigned int i;
 870
 871         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 872                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 873
 874         for (i = 0; i < 100; i++) {
 875                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 876                         break;
 877                 udelay(10);
 878         }
 879 }
 880
 881 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 882 {
 883         u16 value = 0xffff;
 884         unsigned int i;
 885
 886         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 887
 888         for (i = 0; i < 100; i++) {
 889                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 890                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 891                         break;
 892                 }
 893                 udelay(10);
 894         }
 895
 896         return value;
 897 }
 898
 899 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 900 {
 901         unsigned int i;
 902
 903         RTL_W32(CSIDR, value);
 904         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 905                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 906
 907         for (i = 0; i < 100; i++) {
 908                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 909                         break;
 910                 udelay(10);
 911         }
 912 }
 913
 914 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 915 {
 916         u32 value = ~0x00;
 917         unsigned int i;
 918
 919         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 920                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 921
 922         for (i = 0; i < 100; i++) {
 923                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 924                         value = RTL_R32(CSIDR);
 925                         break;
 926                 }
 927                 udelay(10);
 928         }
 929
 930         return value;
 931 }
 932
 933 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 934 {
 935         u8 value = 0xff;
 936         unsigned int i;
 937
 938         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 939
 940         for (i = 0; i < 300; i++) {
 941                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 942                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 943                         break;
 944                 }
 945                 udelay(100);
 946         }
 947
 948         return value;
 949 }
 950
 951 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 952 {
 953         RTL_W16(IntrMask, 0x0000);
 954
 955         RTL_W16(IntrStatus, 0xffff);
 956 }
 957
 958 static void rtl8169_asic_down(void __iomem *ioaddr)
 959 {
 960         RTL_W8(ChipCmd, 0x00);
 961         rtl8169_irq_mask_and_ack(ioaddr);
 962         RTL_R16(CPlusCmd);
 963 }
 964
 965 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 966 {
 967         void __iomem *ioaddr = tp->mmio_addr;
 968
 969         return RTL_R32(TBICSR) & TBIReset;
 970 }
 971
 972 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 973 {
 974         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 975 }
 976
 977 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 978 {
 979         return RTL_R32(TBICSR) & TBILinkOk;
 980 }
 981
 982 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 983 {
 984         return RTL_R8(PHYstatus) & LinkStatus;
 985 }
 986
 987 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 988 {
 989         void __iomem *ioaddr = tp->mmio_addr;
 990
 991         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 992 }
 993
 994 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
 995 {
 996         unsigned int val;
 997
 998         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
 999         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1000 }
1001
1002 static void __rtl8169_check_link_status(struct net_device *dev,
1003                                       struct rtl8169_private *tp,
1004                                       void __iomem *ioaddr,
1005                                       bool pm)
1006 {
1007         unsigned long flags;
1008
1009         spin_lock_irqsave(&tp->lock, flags);
1010         if (tp->link_ok(ioaddr)) {
1011                 /* This is to cancel a scheduled suspend if there's one. */
1012                 if (pm)
1013                         pm_request_resume(&tp->pci_dev->dev);
1014                 netif_carrier_on(dev);
1015                 if (net_ratelimit())
1016                         netif_info(tp, ifup, dev, "link up\n");
1017         } else {
1018                 netif_carrier_off(dev);
1019                 netif_info(tp, ifdown, dev, "link down\n");
1020                 if (pm)
1021                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1022         }
1023         spin_unlock_irqrestore(&tp->lock, flags);
1024 }
1025
1026 static void rtl8169_check_link_status(struct net_device *dev,
1027                                       struct rtl8169_private *tp,
1028                                       void __iomem *ioaddr)
1029 {
1030         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1031 }
1032
1033 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1034
1035 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1036 {
1037         void __iomem *ioaddr = tp->mmio_addr;
1038         u8 options;
1039         u32 wolopts = 0;
1040
1041         options = RTL_R8(Config1);
1042         if (!(options & PMEnable))
1043                 return 0;
1044
1045         options = RTL_R8(Config3);
1046         if (options & LinkUp)
1047                 wolopts |= WAKE_PHY;
1048         if (options & MagicPacket)
1049                 wolopts |= WAKE_MAGIC;
1050
1051         options = RTL_R8(Config5);
1052         if (options & UWF)
1053                 wolopts |= WAKE_UCAST;
1054         if (options & BWF)
1055                 wolopts |= WAKE_BCAST;
1056         if (options & MWF)
1057                 wolopts |= WAKE_MCAST;
1058
1059         return wolopts;
1060 }
1061
1062 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063 {
1064         struct rtl8169_private *tp = netdev_priv(dev);
1065
1066         spin_lock_irq(&tp->lock);
1067
1068         wol->supported = WAKE_ANY;
1069         wol->wolopts = __rtl8169_get_wol(tp);
1070
1071         spin_unlock_irq(&tp->lock);
1072 }
1073
1074 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1075 {
1076         void __iomem *ioaddr = tp->mmio_addr;
1077         unsigned int i;
1078         static const struct {
1079                 u32 opt;
1080                 u16 reg;
1081                 u8  mask;
1082         } cfg[] = {
1083                 { WAKE_ANY,   Config1, PMEnable },
1084                 { WAKE_PHY,   Config3, LinkUp },
1085                 { WAKE_MAGIC, Config3, MagicPacket },
1086                 { WAKE_UCAST, Config5, UWF },
1087                 { WAKE_BCAST, Config5, BWF },
1088                 { WAKE_MCAST, Config5, MWF },
1089                 { WAKE_ANY,   Config5, LanWake }
1090         };
1091
1092         RTL_W8(Cfg9346, Cfg9346_Unlock);
1093
1094         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1095                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1096                 if (wolopts & cfg[i].opt)
1097                         options |= cfg[i].mask;
1098                 RTL_W8(cfg[i].reg, options);
1099         }
1100
1101         RTL_W8(Cfg9346, Cfg9346_Lock);
1102 }
1103
1104 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1105 {
1106         struct rtl8169_private *tp = netdev_priv(dev);
1107
1108         spin_lock_irq(&tp->lock);
1109
1110         if (wol->wolopts)
1111                 tp->features |= RTL_FEATURE_WOL;
1112         else
1113                 tp->features &= ~RTL_FEATURE_WOL;
1114         __rtl8169_set_wol(tp, wol->wolopts);
1115         spin_unlock_irq(&tp->lock);
1116
1117         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1118
1119         return 0;
1120 }
1121
1122 static void rtl8169_get_drvinfo(struct net_device *dev,
1123                                 struct ethtool_drvinfo *info)
1124 {
1125         struct rtl8169_private *tp = netdev_priv(dev);
1126
1127         strcpy(info->driver, MODULENAME);
1128         strcpy(info->version, RTL8169_VERSION);
1129         strcpy(info->bus_info, pci_name(tp->pci_dev));
1130 }
1131
1132 static int rtl8169_get_regs_len(struct net_device *dev)
1133 {
1134         return R8169_REGS_SIZE;
1135 }
1136
1137 static int rtl8169_set_speed_tbi(struct net_device *dev,
1138                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1139 {
1140         struct rtl8169_private *tp = netdev_priv(dev);
1141         void __iomem *ioaddr = tp->mmio_addr;
1142         int ret = 0;
1143         u32 reg;
1144
1145         reg = RTL_R32(TBICSR);
1146         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1147             (duplex == DUPLEX_FULL)) {
1148                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1149         } else if (autoneg == AUTONEG_ENABLE)
1150                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1151         else {
1152                 netif_warn(tp, link, dev,
1153                            "incorrect speed setting refused in TBI mode\n");
1154                 ret = -EOPNOTSUPP;
1155         }
1156
1157         return ret;
1158 }
1159
1160 static int rtl8169_set_speed_xmii(struct net_device *dev,
1161                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1162 {
1163         struct rtl8169_private *tp = netdev_priv(dev);
1164         int giga_ctrl, bmcr;
1165         int rc = -EINVAL;
1166
1167         rtl_writephy(tp, 0x1f, 0x0000);
1168
1169         if (autoneg == AUTONEG_ENABLE) {
1170                 int auto_nego;
1171
1172                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1173                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1174                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1175
1176                 if (adv & ADVERTISED_10baseT_Half)
1177                         auto_nego |= ADVERTISE_10HALF;
1178                 if (adv & ADVERTISED_10baseT_Full)
1179                         auto_nego |= ADVERTISE_10FULL;
1180                 if (adv & ADVERTISED_100baseT_Half)
1181                         auto_nego |= ADVERTISE_100HALF;
1182                 if (adv & ADVERTISED_100baseT_Full)
1183                         auto_nego |= ADVERTISE_100FULL;
1184
1185                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1186
1187                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1188                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1189
1190                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1191                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1192                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1193                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1194                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1195                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1196                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1197                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1198                     (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1199                     (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1200                     (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1201                         if (adv & ADVERTISED_1000baseT_Half)
1202                                 giga_ctrl |= ADVERTISE_1000HALF;
1203                         if (adv & ADVERTISED_1000baseT_Full)
1204                                 giga_ctrl |= ADVERTISE_1000FULL;
1205                 } else if (adv & (ADVERTISED_1000baseT_Half |
1206                                   ADVERTISED_1000baseT_Full)) {
1207                         netif_info(tp, link, dev,
1208                                    "PHY does not support 1000Mbps\n");
1209                         goto out;
1210                 }
1211
1212                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1213
1214                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1215                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1216         } else {
1217                 giga_ctrl = 0;
1218
1219                 if (speed == SPEED_10)
1220                         bmcr = 0;
1221                 else if (speed == SPEED_100)
1222                         bmcr = BMCR_SPEED100;
1223                 else
1224                         goto out;
1225
1226                 if (duplex == DUPLEX_FULL)
1227                         bmcr |= BMCR_FULLDPLX;
1228         }
1229
1230         tp->phy_1000_ctrl_reg = giga_ctrl;
1231
1232         rtl_writephy(tp, MII_BMCR, bmcr);
1233
1234         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1235             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1236                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1237                         rtl_writephy(tp, 0x17, 0x2138);
1238                         rtl_writephy(tp, 0x0e, 0x0260);
1239                 } else {
1240                         rtl_writephy(tp, 0x17, 0x2108);
1241                         rtl_writephy(tp, 0x0e, 0x0000);
1242                 }
1243         }
1244
1245         rc = 0;
1246 out:
1247         return rc;
1248 }
1249
1250 static int rtl8169_set_speed(struct net_device *dev,
1251                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1252 {
1253         struct rtl8169_private *tp = netdev_priv(dev);
1254         int ret;
1255
1256         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1257
1258         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1259                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1260
1261         return ret;
1262 }
1263
1264 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1265 {
1266         struct rtl8169_private *tp = netdev_priv(dev);
1267         unsigned long flags;
1268         int ret;
1269
1270         spin_lock_irqsave(&tp->lock, flags);
1271         ret = rtl8169_set_speed(dev,
1272                 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1273         spin_unlock_irqrestore(&tp->lock, flags);
1274
1275         return ret;
1276 }
1277
1278 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1279 {
1280         struct rtl8169_private *tp = netdev_priv(dev);
1281
1282         return tp->cp_cmd & RxChkSum;
1283 }
1284
1285 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1286 {
1287         struct rtl8169_private *tp = netdev_priv(dev);
1288         void __iomem *ioaddr = tp->mmio_addr;
1289         unsigned long flags;
1290
1291         spin_lock_irqsave(&tp->lock, flags);
1292
1293         if (data)
1294                 tp->cp_cmd |= RxChkSum;
1295         else
1296                 tp->cp_cmd &= ~RxChkSum;
1297
1298         RTL_W16(CPlusCmd, tp->cp_cmd);
1299         RTL_R16(CPlusCmd);
1300
1301         spin_unlock_irqrestore(&tp->lock, flags);
1302
1303         return 0;
1304 }
1305
1306 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1307                                       struct sk_buff *skb)
1308 {
1309         return (vlan_tx_tag_present(skb)) ?
1310                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1311 }
1312
1313 #define NETIF_F_HW_VLAN_TX_RX   (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX)
1314
1315 static void rtl8169_vlan_mode(struct net_device *dev)
1316 {
1317         struct rtl8169_private *tp = netdev_priv(dev);
1318         void __iomem *ioaddr = tp->mmio_addr;
1319         unsigned long flags;
1320
1321         spin_lock_irqsave(&tp->lock, flags);
1322         if (dev->features & NETIF_F_HW_VLAN_RX)
1323                 tp->cp_cmd |= RxVlan;
1324         else
1325                 tp->cp_cmd &= ~RxVlan;
1326         RTL_W16(CPlusCmd, tp->cp_cmd);
1327         /* PCI commit */
1328         RTL_R16(CPlusCmd);
1329         spin_unlock_irqrestore(&tp->lock, flags);
1330
1331         dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX;
1332 }
1333
1334 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1335 {
1336         u32 opts2 = le32_to_cpu(desc->opts2);
1337
1338         if (opts2 & RxVlanTag)
1339                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1340
1341         desc->opts2 = 0;
1342 }
1343
1344 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1345 {
1346         struct rtl8169_private *tp = netdev_priv(dev);
1347         void __iomem *ioaddr = tp->mmio_addr;
1348         u32 status;
1349
1350         cmd->supported =
1351                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1352         cmd->port = PORT_FIBRE;
1353         cmd->transceiver = XCVR_INTERNAL;
1354
1355         status = RTL_R32(TBICSR);
1356         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1357         cmd->autoneg = !!(status & TBINwEnable);
1358
1359         cmd->speed = SPEED_1000;
1360         cmd->duplex = DUPLEX_FULL; /* Always set */
1361
1362         return 0;
1363 }
1364
1365 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1366 {
1367         struct rtl8169_private *tp = netdev_priv(dev);
1368
1369         return mii_ethtool_gset(&tp->mii, cmd);
1370 }
1371
1372 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 {
1374         struct rtl8169_private *tp = netdev_priv(dev);
1375         unsigned long flags;
1376         int rc;
1377
1378         spin_lock_irqsave(&tp->lock, flags);
1379
1380         rc = tp->get_settings(dev, cmd);
1381
1382         spin_unlock_irqrestore(&tp->lock, flags);
1383         return rc;
1384 }
1385
1386 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1387                              void *p)
1388 {
1389         struct rtl8169_private *tp = netdev_priv(dev);
1390         unsigned long flags;
1391
1392         if (regs->len > R8169_REGS_SIZE)
1393                 regs->len = R8169_REGS_SIZE;
1394
1395         spin_lock_irqsave(&tp->lock, flags);
1396         memcpy_fromio(p, tp->mmio_addr, regs->len);
1397         spin_unlock_irqrestore(&tp->lock, flags);
1398 }
1399
1400 static u32 rtl8169_get_msglevel(struct net_device *dev)
1401 {
1402         struct rtl8169_private *tp = netdev_priv(dev);
1403
1404         return tp->msg_enable;
1405 }
1406
1407 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1408 {
1409         struct rtl8169_private *tp = netdev_priv(dev);
1410
1411         tp->msg_enable = value;
1412 }
1413
1414 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1415         "tx_packets",
1416         "rx_packets",
1417         "tx_errors",
1418         "rx_errors",
1419         "rx_missed",
1420         "align_errors",
1421         "tx_single_collisions",
1422         "tx_multi_collisions",
1423         "unicast",
1424         "broadcast",
1425         "multicast",
1426         "tx_aborted",
1427         "tx_underrun",
1428 };
1429
1430 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1431 {
1432         switch (sset) {
1433         case ETH_SS_STATS:
1434                 return ARRAY_SIZE(rtl8169_gstrings);
1435         default:
1436                 return -EOPNOTSUPP;
1437         }
1438 }
1439
1440 static void rtl8169_update_counters(struct net_device *dev)
1441 {
1442         struct rtl8169_private *tp = netdev_priv(dev);
1443         void __iomem *ioaddr = tp->mmio_addr;
1444         struct rtl8169_counters *counters;
1445         dma_addr_t paddr;
1446         u32 cmd;
1447         int wait = 1000;
1448         struct device *d = &tp->pci_dev->dev;
1449
1450         /*
1451          * Some chips are unable to dump tally counters when the receiver
1452          * is disabled.
1453          */
1454         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1455                 return;
1456
1457         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1458         if (!counters)
1459                 return;
1460
1461         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1462         cmd = (u64)paddr & DMA_BIT_MASK(32);
1463         RTL_W32(CounterAddrLow, cmd);
1464         RTL_W32(CounterAddrLow, cmd | CounterDump);
1465
1466         while (wait--) {
1467                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1468                         /* copy updated counters */
1469                         memcpy(&tp->counters, counters, sizeof(*counters));
1470                         break;
1471                 }
1472                 udelay(10);
1473         }
1474
1475         RTL_W32(CounterAddrLow, 0);
1476         RTL_W32(CounterAddrHigh, 0);
1477
1478         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1479 }
1480
1481 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1482                                       struct ethtool_stats *stats, u64 *data)
1483 {
1484         struct rtl8169_private *tp = netdev_priv(dev);
1485
1486         ASSERT_RTNL();
1487
1488         rtl8169_update_counters(dev);
1489
1490         data[0] = le64_to_cpu(tp->counters.tx_packets);
1491         data[1] = le64_to_cpu(tp->counters.rx_packets);
1492         data[2] = le64_to_cpu(tp->counters.tx_errors);
1493         data[3] = le32_to_cpu(tp->counters.rx_errors);
1494         data[4] = le16_to_cpu(tp->counters.rx_missed);
1495         data[5] = le16_to_cpu(tp->counters.align_errors);
1496         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1497         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1498         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1499         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1500         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1501         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1502         data[12] = le16_to_cpu(tp->counters.tx_underun);
1503 }
1504
1505 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1506 {
1507         switch(stringset) {
1508         case ETH_SS_STATS:
1509                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1510                 break;
1511         }
1512 }
1513
1514 static int rtl8169_set_flags(struct net_device *dev, u32 data)
1515 {
1516         struct rtl8169_private *tp = netdev_priv(dev);
1517         unsigned long old_feat = dev->features;
1518         int rc;
1519
1520         if ((tp->mac_version == RTL_GIGA_MAC_VER_05) &&
1521             !(data & ETH_FLAG_RXVLAN)) {
1522                 netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n");
1523                 return -EINVAL;
1524         }
1525
1526         rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN);
1527         if (rc)
1528                 return rc;
1529
1530         if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX)
1531                 rtl8169_vlan_mode(dev);
1532
1533         return 0;
1534 }
1535
1536 static const struct ethtool_ops rtl8169_ethtool_ops = {
1537         .get_drvinfo            = rtl8169_get_drvinfo,
1538         .get_regs_len           = rtl8169_get_regs_len,
1539         .get_link               = ethtool_op_get_link,
1540         .get_settings           = rtl8169_get_settings,
1541         .set_settings           = rtl8169_set_settings,
1542         .get_msglevel           = rtl8169_get_msglevel,
1543         .set_msglevel           = rtl8169_set_msglevel,
1544         .get_rx_csum            = rtl8169_get_rx_csum,
1545         .set_rx_csum            = rtl8169_set_rx_csum,
1546         .set_tx_csum            = ethtool_op_set_tx_csum,
1547         .set_sg                 = ethtool_op_set_sg,
1548         .set_tso                = ethtool_op_set_tso,
1549         .get_regs               = rtl8169_get_regs,
1550         .get_wol                = rtl8169_get_wol,
1551         .set_wol                = rtl8169_set_wol,
1552         .get_strings            = rtl8169_get_strings,
1553         .get_sset_count         = rtl8169_get_sset_count,
1554         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1555         .set_flags              = rtl8169_set_flags,
1556         .get_flags              = ethtool_op_get_flags,
1557 };
1558
1559 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1560                                     void __iomem *ioaddr)
1561 {
1562         /*
1563          * The driver currently handles the 8168Bf and the 8168Be identically
1564          * but they can be identified more specifically through the test below
1565          * if needed:
1566          *
1567          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1568          *
1569          * Same thing for the 8101Eb and the 8101Ec:
1570          *
1571          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1572          */
1573         static const struct {
1574                 u32 mask;
1575                 u32 val;
1576                 int mac_version;
1577         } mac_info[] = {
1578                 /* 8168D family. */
1579                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1580                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1581                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1582
1583                 /* 8168DP family. */
1584                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1585                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1586                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1587
1588                 /* 8168C family. */
1589                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1590                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1591                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1592                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1593                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1594                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1595                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1596                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1597                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1598
1599                 /* 8168B family. */
1600                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1601                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1602                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1603                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1604
1605                 /* 8101 family. */
1606                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1607                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1608                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1609                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1610                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1611                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1612                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1613                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1614                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1615                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1616                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1617                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1618                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1619                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1620                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1621                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1622                 /* FIXME: where did these entries come from ? -- FR */
1623                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1624                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1625
1626                 /* 8110 family. */
1627                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1628                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1629                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1630                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1631                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1632                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1633
1634                 /* Catch-all */
1635                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1636         }, *p = mac_info;
1637         u32 reg;
1638
1639         reg = RTL_R32(TxConfig);
1640         while ((reg & p->mask) != p->val)
1641                 p++;
1642         tp->mac_version = p->mac_version;
1643 }
1644
1645 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1646 {
1647         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1648 }
1649
1650 struct phy_reg {
1651         u16 reg;
1652         u16 val;
1653 };
1654
1655 static void rtl_writephy_batch(struct rtl8169_private *tp,
1656                                const struct phy_reg *regs, int len)
1657 {
1658         while (len-- > 0) {
1659                 rtl_writephy(tp, regs->reg, regs->val);
1660                 regs++;
1661         }
1662 }
1663
1664 #define PHY_READ                0x00000000
1665 #define PHY_DATA_OR             0x10000000
1666 #define PHY_DATA_AND            0x20000000
1667 #define PHY_BJMPN               0x30000000
1668 #define PHY_READ_EFUSE          0x40000000
1669 #define PHY_READ_MAC_BYTE       0x50000000
1670 #define PHY_WRITE_MAC_BYTE      0x60000000
1671 #define PHY_CLEAR_READCOUNT     0x70000000
1672 #define PHY_WRITE               0x80000000
1673 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1674 #define PHY_COMP_EQ_SKIPN       0xa0000000
1675 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1676 #define PHY_WRITE_PREVIOUS      0xc0000000
1677 #define PHY_SKIPN               0xd0000000
1678 #define PHY_DELAY_MS            0xe0000000
1679 #define PHY_WRITE_ERI_WORD      0xf0000000
1680
1681 static void
1682 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1683 {
1684         __le32 *phytable = (__le32 *)fw->data;
1685         struct net_device *dev = tp->dev;
1686         size_t index, fw_size = fw->size / sizeof(*phytable);
1687         u32 predata, count;
1688
1689         if (fw->size % sizeof(*phytable)) {
1690                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1691                 return;
1692         }
1693
1694         for (index = 0; index < fw_size; index++) {
1695                 u32 action = le32_to_cpu(phytable[index]);
1696                 u32 regno = (action & 0x0fff0000) >> 16;
1697
1698                 switch(action & 0xf0000000) {
1699                 case PHY_READ:
1700                 case PHY_DATA_OR:
1701                 case PHY_DATA_AND:
1702                 case PHY_READ_EFUSE:
1703                 case PHY_CLEAR_READCOUNT:
1704                 case PHY_WRITE:
1705                 case PHY_WRITE_PREVIOUS:
1706                 case PHY_DELAY_MS:
1707                         break;
1708
1709                 case PHY_BJMPN:
1710                         if (regno > index) {
1711                                 netif_err(tp, probe, tp->dev,
1712                                         "Out of range of firmware\n");
1713                                 return;
1714                         }
1715                         break;
1716                 case PHY_READCOUNT_EQ_SKIP:
1717                         if (index + 2 >= fw_size) {
1718                                 netif_err(tp, probe, tp->dev,
1719                                         "Out of range of firmware\n");
1720                                 return;
1721                         }
1722                         break;
1723                 case PHY_COMP_EQ_SKIPN:
1724                 case PHY_COMP_NEQ_SKIPN:
1725                 case PHY_SKIPN:
1726                         if (index + 1 + regno >= fw_size) {
1727                                 netif_err(tp, probe, tp->dev,
1728                                         "Out of range of firmware\n");
1729                                 return;
1730                         }
1731                         break;
1732
1733                 case PHY_READ_MAC_BYTE:
1734                 case PHY_WRITE_MAC_BYTE:
1735                 case PHY_WRITE_ERI_WORD:
1736                 default:
1737                         netif_err(tp, probe, tp->dev,
1738                                   "Invalid action 0x%08x\n", action);
1739                         return;
1740                 }
1741         }
1742
1743         predata = 0;
1744         count = 0;
1745
1746         for (index = 0; index < fw_size; ) {
1747                 u32 action = le32_to_cpu(phytable[index]);
1748                 u32 data = action & 0x0000ffff;
1749                 u32 regno = (action & 0x0fff0000) >> 16;
1750
1751                 if (!action)
1752                         break;
1753
1754                 switch(action & 0xf0000000) {
1755                 case PHY_READ:
1756                         predata = rtl_readphy(tp, regno);
1757                         count++;
1758                         index++;
1759                         break;
1760                 case PHY_DATA_OR:
1761                         predata |= data;
1762                         index++;
1763                         break;
1764                 case PHY_DATA_AND:
1765                         predata &= data;
1766                         index++;
1767                         break;
1768                 case PHY_BJMPN:
1769                         index -= regno;
1770                         break;
1771                 case PHY_READ_EFUSE:
1772                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1773                         index++;
1774                         break;
1775                 case PHY_CLEAR_READCOUNT:
1776                         count = 0;
1777                         index++;
1778                         break;
1779                 case PHY_WRITE:
1780                         rtl_writephy(tp, regno, data);
1781                         index++;
1782                         break;
1783                 case PHY_READCOUNT_EQ_SKIP:
1784                         if (count == data)
1785                                 index += 2;
1786                         else
1787                                 index += 1;
1788                         break;
1789                 case PHY_COMP_EQ_SKIPN:
1790                         if (predata == data)
1791                                 index += regno;
1792                         index++;
1793                         break;
1794                 case PHY_COMP_NEQ_SKIPN:
1795                         if (predata != data)
1796                                 index += regno;
1797                         index++;
1798                         break;
1799                 case PHY_WRITE_PREVIOUS:
1800                         rtl_writephy(tp, regno, predata);
1801                         index++;
1802                         break;
1803                 case PHY_SKIPN:
1804                         index += regno + 1;
1805                         break;
1806                 case PHY_DELAY_MS:
1807                         mdelay(data);
1808                         index++;
1809                         break;
1810
1811                 case PHY_READ_MAC_BYTE:
1812                 case PHY_WRITE_MAC_BYTE:
1813                 case PHY_WRITE_ERI_WORD:
1814                 default:
1815                         BUG();
1816                 }
1817         }
1818 }
1819
1820 static void rtl_release_firmware(struct rtl8169_private *tp)
1821 {
1822         release_firmware(tp->fw);
1823         tp->fw = NULL;
1824 }
1825
1826 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1827 {
1828         const struct firmware **fw = &tp->fw;
1829         int rc = !*fw;
1830
1831         if (rc) {
1832                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1833                 if (rc < 0)
1834                         goto out;
1835         }
1836
1837         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1838         rtl_phy_write_fw(tp, *fw);
1839 out:
1840         return rc;
1841 }
1842
1843 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1844 {
1845         static const struct phy_reg phy_reg_init[] = {
1846                 { 0x1f, 0x0001 },
1847                 { 0x06, 0x006e },
1848                 { 0x08, 0x0708 },
1849                 { 0x15, 0x4000 },
1850                 { 0x18, 0x65c7 },
1851
1852                 { 0x1f, 0x0001 },
1853                 { 0x03, 0x00a1 },
1854                 { 0x02, 0x0008 },
1855                 { 0x01, 0x0120 },
1856                 { 0x00, 0x1000 },
1857                 { 0x04, 0x0800 },
1858                 { 0x04, 0x0000 },
1859
1860                 { 0x03, 0xff41 },
1861                 { 0x02, 0xdf60 },
1862                 { 0x01, 0x0140 },
1863                 { 0x00, 0x0077 },
1864                 { 0x04, 0x7800 },
1865                 { 0x04, 0x7000 },
1866
1867                 { 0x03, 0x802f },
1868                 { 0x02, 0x4f02 },
1869                 { 0x01, 0x0409 },
1870                 { 0x00, 0xf0f9 },
1871                 { 0x04, 0x9800 },
1872                 { 0x04, 0x9000 },
1873
1874                 { 0x03, 0xdf01 },
1875                 { 0x02, 0xdf20 },
1876                 { 0x01, 0xff95 },
1877                 { 0x00, 0xba00 },
1878                 { 0x04, 0xa800 },
1879                 { 0x04, 0xa000 },
1880
1881                 { 0x03, 0xff41 },
1882                 { 0x02, 0xdf20 },
1883                 { 0x01, 0x0140 },
1884                 { 0x00, 0x00bb },
1885                 { 0x04, 0xb800 },
1886                 { 0x04, 0xb000 },
1887
1888                 { 0x03, 0xdf41 },
1889                 { 0x02, 0xdc60 },
1890                 { 0x01, 0x6340 },
1891                 { 0x00, 0x007d },
1892                 { 0x04, 0xd800 },
1893                 { 0x04, 0xd000 },
1894
1895                 { 0x03, 0xdf01 },
1896                 { 0x02, 0xdf20 },
1897                 { 0x01, 0x100a },
1898                 { 0x00, 0xa0ff },
1899                 { 0x04, 0xf800 },
1900                 { 0x04, 0xf000 },
1901
1902                 { 0x1f, 0x0000 },
1903                 { 0x0b, 0x0000 },
1904                 { 0x00, 0x9200 }
1905         };
1906
1907         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1908 }
1909
1910 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1911 {
1912         static const struct phy_reg phy_reg_init[] = {
1913                 { 0x1f, 0x0002 },
1914                 { 0x01, 0x90d0 },
1915                 { 0x1f, 0x0000 }
1916         };
1917
1918         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1919 }
1920
1921 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1922 {
1923         struct pci_dev *pdev = tp->pci_dev;
1924         u16 vendor_id, device_id;
1925
1926         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1927         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1928
1929         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1930                 return;
1931
1932         rtl_writephy(tp, 0x1f, 0x0001);
1933         rtl_writephy(tp, 0x10, 0xf01b);
1934         rtl_writephy(tp, 0x1f, 0x0000);
1935 }
1936
1937 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1938 {
1939         static const struct phy_reg phy_reg_init[] = {
1940                 { 0x1f, 0x0001 },
1941                 { 0x04, 0x0000 },
1942                 { 0x03, 0x00a1 },
1943                 { 0x02, 0x0008 },
1944                 { 0x01, 0x0120 },
1945                 { 0x00, 0x1000 },
1946                 { 0x04, 0x0800 },
1947                 { 0x04, 0x9000 },
1948                 { 0x03, 0x802f },
1949                 { 0x02, 0x4f02 },
1950                 { 0x01, 0x0409 },
1951                 { 0x00, 0xf099 },
1952                 { 0x04, 0x9800 },
1953                 { 0x04, 0xa000 },
1954                 { 0x03, 0xdf01 },
1955                 { 0x02, 0xdf20 },
1956                 { 0x01, 0xff95 },
1957                 { 0x00, 0xba00 },
1958                 { 0x04, 0xa800 },
1959                 { 0x04, 0xf000 },
1960                 { 0x03, 0xdf01 },
1961                 { 0x02, 0xdf20 },
1962                 { 0x01, 0x101a },
1963                 { 0x00, 0xa0ff },
1964                 { 0x04, 0xf800 },
1965                 { 0x04, 0x0000 },
1966                 { 0x1f, 0x0000 },
1967
1968                 { 0x1f, 0x0001 },
1969                 { 0x10, 0xf41b },
1970                 { 0x14, 0xfb54 },
1971                 { 0x18, 0xf5c7 },
1972                 { 0x1f, 0x0000 },
1973
1974                 { 0x1f, 0x0001 },
1975                 { 0x17, 0x0cc0 },
1976                 { 0x1f, 0x0000 }
1977         };
1978
1979         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1980
1981         rtl8169scd_hw_phy_config_quirk(tp);
1982 }
1983
1984 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1985 {
1986         static const struct phy_reg phy_reg_init[] = {
1987                 { 0x1f, 0x0001 },
1988                 { 0x04, 0x0000 },
1989                 { 0x03, 0x00a1 },
1990                 { 0x02, 0x0008 },
1991                 { 0x01, 0x0120 },
1992                 { 0x00, 0x1000 },
1993                 { 0x04, 0x0800 },
1994                 { 0x04, 0x9000 },
1995                 { 0x03, 0x802f },
1996                 { 0x02, 0x4f02 },
1997                 { 0x01, 0x0409 },
1998                 { 0x00, 0xf099 },
1999                 { 0x04, 0x9800 },
2000                 { 0x04, 0xa000 },
2001                 { 0x03, 0xdf01 },
2002                 { 0x02, 0xdf20 },
2003                 { 0x01, 0xff95 },
2004                 { 0x00, 0xba00 },
2005                 { 0x04, 0xa800 },
2006                 { 0x04, 0xf000 },
2007                 { 0x03, 0xdf01 },
2008                 { 0x02, 0xdf20 },
2009                 { 0x01, 0x101a },
2010                 { 0x00, 0xa0ff },
2011                 { 0x04, 0xf800 },
2012                 { 0x04, 0x0000 },
2013                 { 0x1f, 0x0000 },
2014
2015                 { 0x1f, 0x0001 },
2016                 { 0x0b, 0x8480 },
2017                 { 0x1f, 0x0000 },
2018
2019                 { 0x1f, 0x0001 },
2020                 { 0x18, 0x67c7 },
2021                 { 0x04, 0x2000 },
2022                 { 0x03, 0x002f },
2023                 { 0x02, 0x4360 },
2024                 { 0x01, 0x0109 },
2025                 { 0x00, 0x3022 },
2026                 { 0x04, 0x2800 },
2027                 { 0x1f, 0x0000 },
2028
2029                 { 0x1f, 0x0001 },
2030                 { 0x17, 0x0cc0 },
2031                 { 0x1f, 0x0000 }
2032         };
2033
2034         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2035 }
2036
2037 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2038 {
2039         static const struct phy_reg phy_reg_init[] = {
2040                 { 0x10, 0xf41b },
2041                 { 0x1f, 0x0000 }
2042         };
2043
2044         rtl_writephy(tp, 0x1f, 0x0001);
2045         rtl_patchphy(tp, 0x16, 1 << 0);
2046
2047         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2048 }
2049
2050 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2051 {
2052         static const struct phy_reg phy_reg_init[] = {
2053                 { 0x1f, 0x0001 },
2054                 { 0x10, 0xf41b },
2055                 { 0x1f, 0x0000 }
2056         };
2057
2058         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2059 }
2060
2061 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2062 {
2063         static const struct phy_reg phy_reg_init[] = {
2064                 { 0x1f, 0x0000 },
2065                 { 0x1d, 0x0f00 },
2066                 { 0x1f, 0x0002 },
2067                 { 0x0c, 0x1ec8 },
2068                 { 0x1f, 0x0000 }
2069         };
2070
2071         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2072 }
2073
2074 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2075 {
2076         static const struct phy_reg phy_reg_init[] = {
2077                 { 0x1f, 0x0001 },
2078                 { 0x1d, 0x3d98 },
2079                 { 0x1f, 0x0000 }
2080         };
2081
2082         rtl_writephy(tp, 0x1f, 0x0000);
2083         rtl_patchphy(tp, 0x14, 1 << 5);
2084         rtl_patchphy(tp, 0x0d, 1 << 5);
2085
2086         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2087 }
2088
2089 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2090 {
2091         static const struct phy_reg phy_reg_init[] = {
2092                 { 0x1f, 0x0001 },
2093                 { 0x12, 0x2300 },
2094                 { 0x1f, 0x0002 },
2095                 { 0x00, 0x88d4 },
2096                 { 0x01, 0x82b1 },
2097                 { 0x03, 0x7002 },
2098                 { 0x08, 0x9e30 },
2099                 { 0x09, 0x01f0 },
2100                 { 0x0a, 0x5500 },
2101                 { 0x0c, 0x00c8 },
2102                 { 0x1f, 0x0003 },
2103                 { 0x12, 0xc096 },
2104                 { 0x16, 0x000a },
2105                 { 0x1f, 0x0000 },
2106                 { 0x1f, 0x0000 },
2107                 { 0x09, 0x2000 },
2108                 { 0x09, 0x0000 }
2109         };
2110
2111         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2112
2113         rtl_patchphy(tp, 0x14, 1 << 5);
2114         rtl_patchphy(tp, 0x0d, 1 << 5);
2115         rtl_writephy(tp, 0x1f, 0x0000);
2116 }
2117
2118 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2119 {
2120         static const struct phy_reg phy_reg_init[] = {
2121                 { 0x1f, 0x0001 },
2122                 { 0x12, 0x2300 },
2123                 { 0x03, 0x802f },
2124                 { 0x02, 0x4f02 },
2125                 { 0x01, 0x0409 },
2126                 { 0x00, 0xf099 },
2127                 { 0x04, 0x9800 },
2128                 { 0x04, 0x9000 },
2129                 { 0x1d, 0x3d98 },
2130                 { 0x1f, 0x0002 },
2131                 { 0x0c, 0x7eb8 },
2132                 { 0x06, 0x0761 },
2133                 { 0x1f, 0x0003 },
2134                 { 0x16, 0x0f0a },
2135                 { 0x1f, 0x0000 }
2136         };
2137
2138         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2139
2140         rtl_patchphy(tp, 0x16, 1 << 0);
2141         rtl_patchphy(tp, 0x14, 1 << 5);
2142         rtl_patchphy(tp, 0x0d, 1 << 5);
2143         rtl_writephy(tp, 0x1f, 0x0000);
2144 }
2145
2146 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2147 {
2148         static const struct phy_reg phy_reg_init[] = {
2149                 { 0x1f, 0x0001 },
2150                 { 0x12, 0x2300 },
2151                 { 0x1d, 0x3d98 },
2152                 { 0x1f, 0x0002 },
2153                 { 0x0c, 0x7eb8 },
2154                 { 0x06, 0x5461 },
2155                 { 0x1f, 0x0003 },
2156                 { 0x16, 0x0f0a },
2157                 { 0x1f, 0x0000 }
2158         };
2159
2160         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2161
2162         rtl_patchphy(tp, 0x16, 1 << 0);
2163         rtl_patchphy(tp, 0x14, 1 << 5);
2164         rtl_patchphy(tp, 0x0d, 1 << 5);
2165         rtl_writephy(tp, 0x1f, 0x0000);
2166 }
2167
2168 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2169 {
2170         rtl8168c_3_hw_phy_config(tp);
2171 }
2172
2173 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2174 {
2175         static const struct phy_reg phy_reg_init_0[] = {
2176                 /* Channel Estimation */
2177                 { 0x1f, 0x0001 },
2178                 { 0x06, 0x4064 },
2179                 { 0x07, 0x2863 },
2180                 { 0x08, 0x059c },
2181                 { 0x09, 0x26b4 },
2182                 { 0x0a, 0x6a19 },
2183                 { 0x0b, 0xdcc8 },
2184                 { 0x10, 0xf06d },
2185                 { 0x14, 0x7f68 },
2186                 { 0x18, 0x7fd9 },
2187                 { 0x1c, 0xf0ff },
2188                 { 0x1d, 0x3d9c },
2189                 { 0x1f, 0x0003 },
2190                 { 0x12, 0xf49f },
2191                 { 0x13, 0x070b },
2192                 { 0x1a, 0x05ad },
2193                 { 0x14, 0x94c0 },
2194
2195                 /*
2196                  * Tx Error Issue
2197                  * enhance line driver power
2198                  */
2199                 { 0x1f, 0x0002 },
2200                 { 0x06, 0x5561 },
2201                 { 0x1f, 0x0005 },
2202                 { 0x05, 0x8332 },
2203                 { 0x06, 0x5561 },
2204
2205                 /*
2206                  * Can not link to 1Gbps with bad cable
2207                  * Decrease SNR threshold form 21.07dB to 19.04dB
2208                  */
2209                 { 0x1f, 0x0001 },
2210                 { 0x17, 0x0cc0 },
2211
2212                 { 0x1f, 0x0000 },
2213                 { 0x0d, 0xf880 }
2214         };
2215         void __iomem *ioaddr = tp->mmio_addr;
2216
2217         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2218
2219         /*
2220          * Rx Error Issue
2221          * Fine Tune Switching regulator parameter
2222          */
2223         rtl_writephy(tp, 0x1f, 0x0002);
2224         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2225         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2226
2227         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2228                 static const struct phy_reg phy_reg_init[] = {
2229                         { 0x1f, 0x0002 },
2230                         { 0x05, 0x669a },
2231                         { 0x1f, 0x0005 },
2232                         { 0x05, 0x8330 },
2233                         { 0x06, 0x669a },
2234                         { 0x1f, 0x0002 }
2235                 };
2236                 int val;
2237
2238                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2239
2240                 val = rtl_readphy(tp, 0x0d);
2241
2242                 if ((val & 0x00ff) != 0x006c) {
2243                         static const u32 set[] = {
2244                                 0x0065, 0x0066, 0x0067, 0x0068,
2245                                 0x0069, 0x006a, 0x006b, 0x006c
2246                         };
2247                         int i;
2248
2249                         rtl_writephy(tp, 0x1f, 0x0002);
2250
2251                         val &= 0xff00;
2252                         for (i = 0; i < ARRAY_SIZE(set); i++)
2253                                 rtl_writephy(tp, 0x0d, val | set[i]);
2254                 }
2255         } else {
2256                 static const struct phy_reg phy_reg_init[] = {
2257                         { 0x1f, 0x0002 },
2258                         { 0x05, 0x6662 },
2259                         { 0x1f, 0x0005 },
2260                         { 0x05, 0x8330 },
2261                         { 0x06, 0x6662 }
2262                 };
2263
2264                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2265         }
2266
2267         /* RSET couple improve */
2268         rtl_writephy(tp, 0x1f, 0x0002);
2269         rtl_patchphy(tp, 0x0d, 0x0300);
2270         rtl_patchphy(tp, 0x0f, 0x0010);
2271
2272         /* Fine tune PLL performance */
2273         rtl_writephy(tp, 0x1f, 0x0002);
2274         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2275         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2276
2277         rtl_writephy(tp, 0x1f, 0x0005);
2278         rtl_writephy(tp, 0x05, 0x001b);
2279         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2280             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2281                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2282         }
2283
2284         rtl_writephy(tp, 0x1f, 0x0000);
2285 }
2286
2287 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2288 {
2289         static const struct phy_reg phy_reg_init_0[] = {
2290                 /* Channel Estimation */
2291                 { 0x1f, 0x0001 },
2292                 { 0x06, 0x4064 },
2293                 { 0x07, 0x2863 },
2294                 { 0x08, 0x059c },
2295                 { 0x09, 0x26b4 },
2296                 { 0x0a, 0x6a19 },
2297                 { 0x0b, 0xdcc8 },
2298                 { 0x10, 0xf06d },
2299                 { 0x14, 0x7f68 },
2300                 { 0x18, 0x7fd9 },
2301                 { 0x1c, 0xf0ff },
2302                 { 0x1d, 0x3d9c },
2303                 { 0x1f, 0x0003 },
2304                 { 0x12, 0xf49f },
2305                 { 0x13, 0x070b },
2306                 { 0x1a, 0x05ad },
2307                 { 0x14, 0x94c0 },
2308
2309                 /*
2310                  * Tx Error Issue
2311                  * enhance line driver power
2312                  */
2313                 { 0x1f, 0x0002 },
2314                 { 0x06, 0x5561 },
2315                 { 0x1f, 0x0005 },
2316                 { 0x05, 0x8332 },
2317                 { 0x06, 0x5561 },
2318
2319                 /*
2320                  * Can not link to 1Gbps with bad cable
2321                  * Decrease SNR threshold form 21.07dB to 19.04dB
2322                  */
2323                 { 0x1f, 0x0001 },
2324                 { 0x17, 0x0cc0 },
2325
2326                 { 0x1f, 0x0000 },
2327                 { 0x0d, 0xf880 }
2328         };
2329         void __iomem *ioaddr = tp->mmio_addr;
2330
2331         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2332
2333         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2334                 static const struct phy_reg phy_reg_init[] = {
2335                         { 0x1f, 0x0002 },
2336                         { 0x05, 0x669a },
2337                         { 0x1f, 0x0005 },
2338                         { 0x05, 0x8330 },
2339                         { 0x06, 0x669a },
2340
2341                         { 0x1f, 0x0002 }
2342                 };
2343                 int val;
2344
2345                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2346
2347                 val = rtl_readphy(tp, 0x0d);
2348                 if ((val & 0x00ff) != 0x006c) {
2349                         static const u32 set[] = {
2350                                 0x0065, 0x0066, 0x0067, 0x0068,
2351                                 0x0069, 0x006a, 0x006b, 0x006c
2352                         };
2353                         int i;
2354
2355                         rtl_writephy(tp, 0x1f, 0x0002);
2356
2357                         val &= 0xff00;
2358                         for (i = 0; i < ARRAY_SIZE(set); i++)
2359                                 rtl_writephy(tp, 0x0d, val | set[i]);
2360                 }
2361         } else {
2362                 static const struct phy_reg phy_reg_init[] = {
2363                         { 0x1f, 0x0002 },
2364                         { 0x05, 0x2642 },
2365                         { 0x1f, 0x0005 },
2366                         { 0x05, 0x8330 },
2367                         { 0x06, 0x2642 }
2368                 };
2369
2370                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2371         }
2372
2373         /* Fine tune PLL performance */
2374         rtl_writephy(tp, 0x1f, 0x0002);
2375         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2376         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2377
2378         /* Switching regulator Slew rate */
2379         rtl_writephy(tp, 0x1f, 0x0002);
2380         rtl_patchphy(tp, 0x0f, 0x0017);
2381
2382         rtl_writephy(tp, 0x1f, 0x0005);
2383         rtl_writephy(tp, 0x05, 0x001b);
2384         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2385             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2386                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2387         }
2388
2389         rtl_writephy(tp, 0x1f, 0x0000);
2390 }
2391
2392 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2393 {
2394         static const struct phy_reg phy_reg_init[] = {
2395                 { 0x1f, 0x0002 },
2396                 { 0x10, 0x0008 },
2397                 { 0x0d, 0x006c },
2398
2399                 { 0x1f, 0x0000 },
2400                 { 0x0d, 0xf880 },
2401
2402                 { 0x1f, 0x0001 },
2403                 { 0x17, 0x0cc0 },
2404
2405                 { 0x1f, 0x0001 },
2406                 { 0x0b, 0xa4d8 },
2407                 { 0x09, 0x281c },
2408                 { 0x07, 0x2883 },
2409                 { 0x0a, 0x6b35 },
2410                 { 0x1d, 0x3da4 },
2411                 { 0x1c, 0xeffd },
2412                 { 0x14, 0x7f52 },
2413                 { 0x18, 0x7fc6 },
2414                 { 0x08, 0x0601 },
2415                 { 0x06, 0x4063 },
2416                 { 0x10, 0xf074 },
2417                 { 0x1f, 0x0003 },
2418                 { 0x13, 0x0789 },
2419                 { 0x12, 0xf4bd },
2420                 { 0x1a, 0x04fd },
2421                 { 0x14, 0x84b0 },
2422                 { 0x1f, 0x0000 },
2423                 { 0x00, 0x9200 },
2424
2425                 { 0x1f, 0x0005 },
2426                 { 0x01, 0x0340 },
2427                 { 0x1f, 0x0001 },
2428                 { 0x04, 0x4000 },
2429                 { 0x03, 0x1d21 },
2430                 { 0x02, 0x0c32 },
2431                 { 0x01, 0x0200 },
2432                 { 0x00, 0x5554 },
2433                 { 0x04, 0x4800 },
2434                 { 0x04, 0x4000 },
2435                 { 0x04, 0xf000 },
2436                 { 0x03, 0xdf01 },
2437                 { 0x02, 0xdf20 },
2438                 { 0x01, 0x101a },
2439                 { 0x00, 0xa0ff },
2440                 { 0x04, 0xf800 },
2441                 { 0x04, 0xf000 },
2442                 { 0x1f, 0x0000 },
2443
2444                 { 0x1f, 0x0007 },
2445                 { 0x1e, 0x0023 },
2446                 { 0x16, 0x0000 },
2447                 { 0x1f, 0x0000 }
2448         };
2449
2450         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2451 }
2452
2453 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2454 {
2455         static const struct phy_reg phy_reg_init[] = {
2456                 { 0x1f, 0x0001 },
2457                 { 0x17, 0x0cc0 },
2458
2459                 { 0x1f, 0x0007 },
2460                 { 0x1e, 0x002d },
2461                 { 0x18, 0x0040 },
2462                 { 0x1f, 0x0000 }
2463         };
2464
2465         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2466         rtl_patchphy(tp, 0x0d, 1 << 5);
2467 }
2468
2469 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2470 {
2471         static const struct phy_reg phy_reg_init[] = {
2472                 { 0x1f, 0x0003 },
2473                 { 0x08, 0x441d },
2474                 { 0x01, 0x9100 },
2475                 { 0x1f, 0x0000 }
2476         };
2477
2478         rtl_writephy(tp, 0x1f, 0x0000);
2479         rtl_patchphy(tp, 0x11, 1 << 12);
2480         rtl_patchphy(tp, 0x19, 1 << 13);
2481         rtl_patchphy(tp, 0x10, 1 << 15);
2482
2483         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2484 }
2485
2486 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2487 {
2488         static const struct phy_reg phy_reg_init[] = {
2489                 { 0x1f, 0x0005 },
2490                 { 0x1a, 0x0000 },
2491                 { 0x1f, 0x0000 },
2492
2493                 { 0x1f, 0x0004 },
2494                 { 0x1c, 0x0000 },
2495                 { 0x1f, 0x0000 },
2496
2497                 { 0x1f, 0x0001 },
2498                 { 0x15, 0x7701 },
2499                 { 0x1f, 0x0000 }
2500         };
2501
2502         /* Disable ALDPS before ram code */
2503         rtl_writephy(tp, 0x1f, 0x0000);
2504         rtl_writephy(tp, 0x18, 0x0310);
2505         msleep(100);
2506
2507         if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2508                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2509
2510         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2511 }
2512
2513 static void rtl_hw_phy_config(struct net_device *dev)
2514 {
2515         struct rtl8169_private *tp = netdev_priv(dev);
2516
2517         rtl8169_print_mac_version(tp);
2518
2519         switch (tp->mac_version) {
2520         case RTL_GIGA_MAC_VER_01:
2521                 break;
2522         case RTL_GIGA_MAC_VER_02:
2523         case RTL_GIGA_MAC_VER_03:
2524                 rtl8169s_hw_phy_config(tp);
2525                 break;
2526         case RTL_GIGA_MAC_VER_04:
2527                 rtl8169sb_hw_phy_config(tp);
2528                 break;
2529         case RTL_GIGA_MAC_VER_05:
2530                 rtl8169scd_hw_phy_config(tp);
2531                 break;
2532         case RTL_GIGA_MAC_VER_06:
2533                 rtl8169sce_hw_phy_config(tp);
2534                 break;
2535         case RTL_GIGA_MAC_VER_07:
2536         case RTL_GIGA_MAC_VER_08:
2537         case RTL_GIGA_MAC_VER_09:
2538                 rtl8102e_hw_phy_config(tp);
2539                 break;
2540         case RTL_GIGA_MAC_VER_11:
2541                 rtl8168bb_hw_phy_config(tp);
2542                 break;
2543         case RTL_GIGA_MAC_VER_12:
2544                 rtl8168bef_hw_phy_config(tp);
2545                 break;
2546         case RTL_GIGA_MAC_VER_17:
2547                 rtl8168bef_hw_phy_config(tp);
2548                 break;
2549         case RTL_GIGA_MAC_VER_18:
2550                 rtl8168cp_1_hw_phy_config(tp);
2551                 break;
2552         case RTL_GIGA_MAC_VER_19:
2553                 rtl8168c_1_hw_phy_config(tp);
2554                 break;
2555         case RTL_GIGA_MAC_VER_20:
2556                 rtl8168c_2_hw_phy_config(tp);
2557                 break;
2558         case RTL_GIGA_MAC_VER_21:
2559                 rtl8168c_3_hw_phy_config(tp);
2560                 break;
2561         case RTL_GIGA_MAC_VER_22:
2562                 rtl8168c_4_hw_phy_config(tp);
2563                 break;
2564         case RTL_GIGA_MAC_VER_23:
2565         case RTL_GIGA_MAC_VER_24:
2566                 rtl8168cp_2_hw_phy_config(tp);
2567                 break;
2568         case RTL_GIGA_MAC_VER_25:
2569                 rtl8168d_1_hw_phy_config(tp);
2570                 break;
2571         case RTL_GIGA_MAC_VER_26:
2572                 rtl8168d_2_hw_phy_config(tp);
2573                 break;
2574         case RTL_GIGA_MAC_VER_27:
2575                 rtl8168d_3_hw_phy_config(tp);
2576                 break;
2577         case RTL_GIGA_MAC_VER_28:
2578                 rtl8168d_4_hw_phy_config(tp);
2579                 break;
2580         case RTL_GIGA_MAC_VER_29:
2581         case RTL_GIGA_MAC_VER_30:
2582                 rtl8105e_hw_phy_config(tp);
2583                 break;
2584
2585         default:
2586                 break;
2587         }
2588 }
2589
2590 static void rtl8169_phy_timer(unsigned long __opaque)
2591 {
2592         struct net_device *dev = (struct net_device *)__opaque;
2593         struct rtl8169_private *tp = netdev_priv(dev);
2594         struct timer_list *timer = &tp->timer;
2595         void __iomem *ioaddr = tp->mmio_addr;
2596         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2597
2598         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2599
2600         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2601                 return;
2602
2603         spin_lock_irq(&tp->lock);
2604
2605         if (tp->phy_reset_pending(tp)) {
2606                 /*
2607                  * A busy loop could burn quite a few cycles on nowadays CPU.
2608                  * Let's delay the execution of the timer for a few ticks.
2609                  */
2610                 timeout = HZ/10;
2611                 goto out_mod_timer;
2612         }
2613
2614         if (tp->link_ok(ioaddr))
2615                 goto out_unlock;
2616
2617         netif_warn(tp, link, dev, "PHY reset until link up\n");
2618
2619         tp->phy_reset_enable(tp);
2620
2621 out_mod_timer:
2622         mod_timer(timer, jiffies + timeout);
2623 out_unlock:
2624         spin_unlock_irq(&tp->lock);
2625 }
2626
2627 static inline void rtl8169_delete_timer(struct net_device *dev)
2628 {
2629         struct rtl8169_private *tp = netdev_priv(dev);
2630         struct timer_list *timer = &tp->timer;
2631
2632         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2633                 return;
2634
2635         del_timer_sync(timer);
2636 }
2637
2638 static inline void rtl8169_request_timer(struct net_device *dev)
2639 {
2640         struct rtl8169_private *tp = netdev_priv(dev);
2641         struct timer_list *timer = &tp->timer;
2642
2643         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2644                 return;
2645
2646         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2647 }
2648
2649 #ifdef CONFIG_NET_POLL_CONTROLLER
2650 /*
2651  * Polling 'interrupt' - used by things like netconsole to send skbs
2652  * without having to re-enable interrupts. It's not called while
2653  * the interrupt routine is executing.
2654  */
2655 static void rtl8169_netpoll(struct net_device *dev)
2656 {
2657         struct rtl8169_private *tp = netdev_priv(dev);
2658         struct pci_dev *pdev = tp->pci_dev;
2659
2660         disable_irq(pdev->irq);
2661         rtl8169_interrupt(pdev->irq, dev);
2662         enable_irq(pdev->irq);
2663 }
2664 #endif
2665
2666 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2667                                   void __iomem *ioaddr)
2668 {
2669         iounmap(ioaddr);
2670         pci_release_regions(pdev);
2671         pci_clear_mwi(pdev);
2672         pci_disable_device(pdev);
2673         free_netdev(dev);
2674 }
2675
2676 static void rtl8169_phy_reset(struct net_device *dev,
2677                               struct rtl8169_private *tp)
2678 {
2679         unsigned int i;
2680
2681         tp->phy_reset_enable(tp);
2682         for (i = 0; i < 100; i++) {
2683                 if (!tp->phy_reset_pending(tp))
2684                         return;
2685                 msleep(1);
2686         }
2687         netif_err(tp, link, dev, "PHY reset failed\n");
2688 }
2689
2690 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2691 {
2692         void __iomem *ioaddr = tp->mmio_addr;
2693
2694         rtl_hw_phy_config(dev);
2695
2696         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2697                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2698                 RTL_W8(0x82, 0x01);
2699         }
2700
2701         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2702
2703         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2704                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2705
2706         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2707                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2708                 RTL_W8(0x82, 0x01);
2709                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2710                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2711         }
2712
2713         rtl8169_phy_reset(dev, tp);
2714
2715         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2716                 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2717                 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2718                 (tp->mii.supports_gmii ?
2719                         ADVERTISED_1000baseT_Half |
2720                         ADVERTISED_1000baseT_Full : 0));
2721
2722         if (RTL_R8(PHYstatus) & TBI_Enable)
2723                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2724 }
2725
2726 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2727 {
2728         void __iomem *ioaddr = tp->mmio_addr;
2729         u32 high;
2730         u32 low;
2731
2732         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2733         high = addr[4] | (addr[5] << 8);
2734
2735         spin_lock_irq(&tp->lock);
2736
2737         RTL_W8(Cfg9346, Cfg9346_Unlock);
2738
2739         RTL_W32(MAC4, high);
2740         RTL_R32(MAC4);
2741
2742         RTL_W32(MAC0, low);
2743         RTL_R32(MAC0);
2744
2745         RTL_W8(Cfg9346, Cfg9346_Lock);
2746
2747         spin_unlock_irq(&tp->lock);
2748 }
2749
2750 static int rtl_set_mac_address(struct net_device *dev, void *p)
2751 {
2752         struct rtl8169_private *tp = netdev_priv(dev);
2753         struct sockaddr *addr = p;
2754
2755         if (!is_valid_ether_addr(addr->sa_data))
2756                 return -EADDRNOTAVAIL;
2757
2758         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2759
2760         rtl_rar_set(tp, dev->dev_addr);
2761
2762         return 0;
2763 }
2764
2765 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2766 {
2767         struct rtl8169_private *tp = netdev_priv(dev);
2768         struct mii_ioctl_data *data = if_mii(ifr);
2769
2770         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2771 }
2772
2773 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2774 {
2775         switch (cmd) {
2776         case SIOCGMIIPHY:
2777                 data->phy_id = 32; /* Internal PHY */
2778                 return 0;
2779
2780         case SIOCGMIIREG:
2781                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2782                 return 0;
2783
2784         case SIOCSMIIREG:
2785                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2786                 return 0;
2787         }
2788         return -EOPNOTSUPP;
2789 }
2790
2791 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2792 {
2793         return -EOPNOTSUPP;
2794 }
2795
2796 static const struct rtl_cfg_info {
2797         void (*hw_start)(struct net_device *);
2798         unsigned int region;
2799         unsigned int align;
2800         u16 intr_event;
2801         u16 napi_event;
2802         unsigned features;
2803         u8 default_ver;
2804 } rtl_cfg_infos [] = {
2805         [RTL_CFG_0] = {
2806                 .hw_start       = rtl_hw_start_8169,
2807                 .region         = 1,
2808                 .align          = 0,
2809                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2810                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2811                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2812                 .features       = RTL_FEATURE_GMII,
2813                 .default_ver    = RTL_GIGA_MAC_VER_01,
2814         },
2815         [RTL_CFG_1] = {
2816                 .hw_start       = rtl_hw_start_8168,
2817                 .region         = 2,
2818                 .align          = 8,
2819                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2820                                   TxErr | TxOK | RxOK | RxErr,
2821                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2822                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2823                 .default_ver    = RTL_GIGA_MAC_VER_11,
2824         },
2825         [RTL_CFG_2] = {
2826                 .hw_start       = rtl_hw_start_8101,
2827                 .region         = 2,
2828                 .align          = 8,
2829                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2830                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2831                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2832                 .features       = RTL_FEATURE_MSI,
2833                 .default_ver    = RTL_GIGA_MAC_VER_13,
2834         }
2835 };
2836
2837 /* Cfg9346_Unlock assumed. */
2838 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2839                             const struct rtl_cfg_info *cfg)
2840 {
2841         unsigned msi = 0;
2842         u8 cfg2;
2843
2844         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2845         if (cfg->features & RTL_FEATURE_MSI) {
2846                 if (pci_enable_msi(pdev)) {
2847                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2848                 } else {
2849                         cfg2 |= MSIEnable;
2850                         msi = RTL_FEATURE_MSI;
2851                 }
2852         }
2853         RTL_W8(Config2, cfg2);
2854         return msi;
2855 }
2856
2857 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2858 {
2859         if (tp->features & RTL_FEATURE_MSI) {
2860                 pci_disable_msi(pdev);
2861                 tp->features &= ~RTL_FEATURE_MSI;
2862         }
2863 }
2864
2865 static const struct net_device_ops rtl8169_netdev_ops = {
2866         .ndo_open               = rtl8169_open,
2867         .ndo_stop               = rtl8169_close,
2868         .ndo_get_stats          = rtl8169_get_stats,
2869         .ndo_start_xmit         = rtl8169_start_xmit,
2870         .ndo_tx_timeout         = rtl8169_tx_timeout,
2871         .ndo_validate_addr      = eth_validate_addr,
2872         .ndo_change_mtu         = rtl8169_change_mtu,
2873         .ndo_set_mac_address    = rtl_set_mac_address,
2874         .ndo_do_ioctl           = rtl8169_ioctl,
2875         .ndo_set_multicast_list = rtl_set_rx_mode,
2876 #ifdef CONFIG_NET_POLL_CONTROLLER
2877         .ndo_poll_controller    = rtl8169_netpoll,
2878 #endif
2879
2880 };
2881
2882 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2883 {
2884         struct mdio_ops *ops = &tp->mdio_ops;
2885
2886         switch (tp->mac_version) {
2887         case RTL_GIGA_MAC_VER_27:
2888                 ops->write      = r8168dp_1_mdio_write;
2889                 ops->read       = r8168dp_1_mdio_read;
2890                 break;
2891         case RTL_GIGA_MAC_VER_28:
2892         case RTL_GIGA_MAC_VER_31:
2893                 ops->write      = r8168dp_2_mdio_write;
2894                 ops->read       = r8168dp_2_mdio_read;
2895                 break;
2896         default:
2897                 ops->write      = r8169_mdio_write;
2898                 ops->read       = r8169_mdio_read;
2899                 break;
2900         }
2901 }
2902
2903 static void r810x_phy_power_down(struct rtl8169_private *tp)
2904 {
2905         rtl_writephy(tp, 0x1f, 0x0000);
2906         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2907 }
2908
2909 static void r810x_phy_power_up(struct rtl8169_private *tp)
2910 {
2911         rtl_writephy(tp, 0x1f, 0x0000);
2912         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2913 }
2914
2915 static void r810x_pll_power_down(struct rtl8169_private *tp)
2916 {
2917         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2918                 rtl_writephy(tp, 0x1f, 0x0000);
2919                 rtl_writephy(tp, MII_BMCR, 0x0000);
2920                 return;
2921         }
2922
2923         r810x_phy_power_down(tp);
2924 }
2925
2926 static void r810x_pll_power_up(struct rtl8169_private *tp)
2927 {
2928         r810x_phy_power_up(tp);
2929 }
2930
2931 static void r8168_phy_power_up(struct rtl8169_private *tp)
2932 {
2933         rtl_writephy(tp, 0x1f, 0x0000);
2934         rtl_writephy(tp, 0x0e, 0x0000);
2935         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2936 }
2937
2938 static void r8168_phy_power_down(struct rtl8169_private *tp)
2939 {
2940         rtl_writephy(tp, 0x1f, 0x0000);
2941         rtl_writephy(tp, 0x0e, 0x0200);
2942         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2943 }
2944
2945 static void r8168_pll_power_down(struct rtl8169_private *tp)
2946 {
2947         void __iomem *ioaddr = tp->mmio_addr;
2948
2949         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2950              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
2951              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
2952             r8168dp_check_dash(tp)) {
2953                 return;
2954         }
2955
2956         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2957              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2958             (RTL_R16(CPlusCmd) & ASF)) {
2959                 return;
2960         }
2961
2962         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2963                 rtl_writephy(tp, 0x1f, 0x0000);
2964                 rtl_writephy(tp, MII_BMCR, 0x0000);
2965
2966                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2967                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2968                 return;
2969         }
2970
2971         r8168_phy_power_down(tp);
2972
2973         switch (tp->mac_version) {
2974         case RTL_GIGA_MAC_VER_25:
2975         case RTL_GIGA_MAC_VER_26:
2976         case RTL_GIGA_MAC_VER_27:
2977         case RTL_GIGA_MAC_VER_28:
2978         case RTL_GIGA_MAC_VER_31:
2979                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2980                 break;
2981         }
2982 }
2983
2984 static void r8168_pll_power_up(struct rtl8169_private *tp)
2985 {
2986         void __iomem *ioaddr = tp->mmio_addr;
2987
2988         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2989              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
2990              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
2991             r8168dp_check_dash(tp)) {
2992                 return;
2993         }
2994
2995         switch (tp->mac_version) {
2996         case RTL_GIGA_MAC_VER_25:
2997         case RTL_GIGA_MAC_VER_26:
2998         case RTL_GIGA_MAC_VER_27:
2999         case RTL_GIGA_MAC_VER_28:
3000         case RTL_GIGA_MAC_VER_31:
3001                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3002                 break;
3003         }
3004
3005         r8168_phy_power_up(tp);
3006 }
3007
3008 static void rtl_pll_power_op(struct rtl8169_private *tp,
3009                              void (*op)(struct rtl8169_private *))
3010 {
3011         if (op)
3012                 op(tp);
3013 }
3014
3015 static void rtl_pll_power_down(struct rtl8169_private *tp)
3016 {
3017         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3018 }
3019
3020 static void rtl_pll_power_up(struct rtl8169_private *tp)
3021 {
3022         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3023 }
3024
3025 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3026 {
3027         struct pll_power_ops *ops = &tp->pll_power_ops;
3028
3029         switch (tp->mac_version) {
3030         case RTL_GIGA_MAC_VER_07:
3031         case RTL_GIGA_MAC_VER_08:
3032         case RTL_GIGA_MAC_VER_09:
3033         case RTL_GIGA_MAC_VER_10:
3034         case RTL_GIGA_MAC_VER_16:
3035         case RTL_GIGA_MAC_VER_29:
3036         case RTL_GIGA_MAC_VER_30:
3037                 ops->down       = r810x_pll_power_down;
3038                 ops->up         = r810x_pll_power_up;
3039                 break;
3040
3041         case RTL_GIGA_MAC_VER_11:
3042         case RTL_GIGA_MAC_VER_12:
3043         case RTL_GIGA_MAC_VER_17:
3044         case RTL_GIGA_MAC_VER_18:
3045         case RTL_GIGA_MAC_VER_19:
3046         case RTL_GIGA_MAC_VER_20:
3047         case RTL_GIGA_MAC_VER_21:
3048         case RTL_GIGA_MAC_VER_22:
3049         case RTL_GIGA_MAC_VER_23:
3050         case RTL_GIGA_MAC_VER_24:
3051         case RTL_GIGA_MAC_VER_25:
3052         case RTL_GIGA_MAC_VER_26:
3053         case RTL_GIGA_MAC_VER_27:
3054         case RTL_GIGA_MAC_VER_28:
3055         case RTL_GIGA_MAC_VER_31:
3056                 ops->down       = r8168_pll_power_down;
3057                 ops->up         = r8168_pll_power_up;
3058                 break;
3059
3060         default:
3061                 ops->down       = NULL;
3062                 ops->up         = NULL;
3063                 break;
3064         }
3065 }
3066
3067 static int __devinit
3068 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3069 {
3070         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3071         const unsigned int region = cfg->region;
3072         struct rtl8169_private *tp;
3073         struct mii_if_info *mii;
3074         struct net_device *dev;
3075         void __iomem *ioaddr;
3076         unsigned int i;
3077         int rc;
3078
3079         if (netif_msg_drv(&debug)) {
3080                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3081                        MODULENAME, RTL8169_VERSION);
3082         }
3083
3084         dev = alloc_etherdev(sizeof (*tp));
3085         if (!dev) {
3086                 if (netif_msg_drv(&debug))
3087                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3088                 rc = -ENOMEM;
3089                 goto out;
3090         }
3091
3092         SET_NETDEV_DEV(dev, &pdev->dev);
3093         dev->netdev_ops = &rtl8169_netdev_ops;
3094         tp = netdev_priv(dev);
3095         tp->dev = dev;
3096         tp->pci_dev = pdev;
3097         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3098
3099         mii = &tp->mii;
3100         mii->dev = dev;
3101         mii->mdio_read = rtl_mdio_read;
3102         mii->mdio_write = rtl_mdio_write;
3103         mii->phy_id_mask = 0x1f;
3104         mii->reg_num_mask = 0x1f;
3105         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3106
3107         /* disable ASPM completely as that cause random device stop working
3108          * problems as well as full system hangs for some PCIe devices users */
3109         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3110                                      PCIE_LINK_STATE_CLKPM);
3111
3112         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3113         rc = pci_enable_device(pdev);
3114         if (rc < 0) {
3115                 netif_err(tp, probe, dev, "enable failure\n");
3116                 goto err_out_free_dev_1;
3117         }
3118
3119         if (pci_set_mwi(pdev) < 0)
3120                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3121
3122         /* make sure PCI base addr 1 is MMIO */
3123         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3124                 netif_err(tp, probe, dev,
3125                           "region #%d not an MMIO resource, aborting\n",
3126                           region);
3127                 rc = -ENODEV;
3128                 goto err_out_mwi_2;
3129         }
3130
3131         /* check for weird/broken PCI region reporting */
3132         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3133                 netif_err(tp, probe, dev,
3134                           "Invalid PCI region size(s), aborting\n");
3135                 rc = -ENODEV;
3136                 goto err_out_mwi_2;
3137         }
3138
3139         rc = pci_request_regions(pdev, MODULENAME);
3140         if (rc < 0) {
3141                 netif_err(tp, probe, dev, "could not request regions\n");
3142                 goto err_out_mwi_2;
3143         }
3144
3145         tp->cp_cmd = RxChkSum;
3146
3147         if ((sizeof(dma_addr_t) > 4) &&
3148             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3149                 tp->cp_cmd |= PCIDAC;
3150                 dev->features |= NETIF_F_HIGHDMA;
3151         } else {
3152                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3153                 if (rc < 0) {
3154                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3155                         goto err_out_free_res_3;
3156                 }
3157         }
3158
3159         /* ioremap MMIO region */
3160         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3161         if (!ioaddr) {
3162                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3163                 rc = -EIO;
3164                 goto err_out_free_res_3;
3165         }
3166
3167         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3168         if (!tp->pcie_cap)
3169                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3170
3171         RTL_W16(IntrMask, 0x0000);
3172
3173         /* Soft reset the chip. */
3174         RTL_W8(ChipCmd, CmdReset);
3175
3176         /* Check that the chip has finished the reset. */
3177         for (i = 0; i < 100; i++) {
3178                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3179                         break;
3180                 msleep_interruptible(1);
3181         }
3182
3183         RTL_W16(IntrStatus, 0xffff);
3184
3185         pci_set_master(pdev);
3186
3187         /* Identify chip attached to board */
3188         rtl8169_get_mac_version(tp, ioaddr);
3189
3190         /*
3191          * Pretend we are using VLANs; This bypasses a nasty bug where
3192          * Interrupts stop flowing on high load on 8110SCd controllers.
3193          */
3194         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3195                 tp->cp_cmd |= RxVlan;
3196
3197         rtl_init_mdio_ops(tp);
3198         rtl_init_pll_power_ops(tp);
3199
3200         /* Use appropriate default if unknown */
3201         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3202                 netif_notice(tp, probe, dev,
3203                              "unknown MAC, using family default\n");
3204                 tp->mac_version = cfg->default_ver;
3205         }
3206
3207         rtl8169_print_mac_version(tp);
3208
3209         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3210                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3211                         break;
3212         }
3213         if (i == ARRAY_SIZE(rtl_chip_info)) {
3214                 dev_err(&pdev->dev,
3215                         "driver bug, MAC version not found in rtl_chip_info\n");
3216                 goto err_out_msi_4;
3217         }
3218         tp->chipset = i;
3219
3220         RTL_W8(Cfg9346, Cfg9346_Unlock);
3221         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3222         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3223         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3224                 tp->features |= RTL_FEATURE_WOL;
3225         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3226                 tp->features |= RTL_FEATURE_WOL;
3227         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3228         RTL_W8(Cfg9346, Cfg9346_Lock);
3229
3230         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3231             (RTL_R8(PHYstatus) & TBI_Enable)) {
3232                 tp->set_speed = rtl8169_set_speed_tbi;
3233                 tp->get_settings = rtl8169_gset_tbi;
3234                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3235                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3236                 tp->link_ok = rtl8169_tbi_link_ok;
3237                 tp->do_ioctl = rtl_tbi_ioctl;
3238
3239                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3240         } else {
3241                 tp->set_speed = rtl8169_set_speed_xmii;
3242                 tp->get_settings = rtl8169_gset_xmii;
3243                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3244                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3245                 tp->link_ok = rtl8169_xmii_link_ok;
3246                 tp->do_ioctl = rtl_xmii_ioctl;
3247         }
3248
3249         spin_lock_init(&tp->lock);
3250
3251         tp->mmio_addr = ioaddr;
3252
3253         /* Get MAC address */
3254         for (i = 0; i < MAC_ADDR_LEN; i++)
3255                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3256         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3257
3258         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3259         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3260         dev->irq = pdev->irq;
3261         dev->base_addr = (unsigned long) ioaddr;
3262
3263         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3264
3265         dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO;
3266
3267         tp->intr_mask = 0xffff;
3268         tp->hw_start = cfg->hw_start;
3269         tp->intr_event = cfg->intr_event;
3270         tp->napi_event = cfg->napi_event;
3271
3272         init_timer(&tp->timer);
3273         tp->timer.data = (unsigned long) dev;
3274         tp->timer.function = rtl8169_phy_timer;
3275
3276         rc = register_netdev(dev);
3277         if (rc < 0)
3278                 goto err_out_msi_4;
3279
3280         pci_set_drvdata(pdev, dev);
3281
3282         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3283                    rtl_chip_info[tp->chipset].name,
3284                    dev->base_addr, dev->dev_addr,
3285                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3286
3287         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3288             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3289             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3290                 rtl8168_driver_start(tp);
3291         }
3292
3293         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3294
3295         if (pci_dev_run_wake(pdev))
3296                 pm_runtime_put_noidle(&pdev->dev);
3297
3298         netif_carrier_off(dev);
3299
3300 out:
3301         return rc;
3302
3303 err_out_msi_4:
3304         rtl_disable_msi(pdev, tp);
3305         iounmap(ioaddr);
3306 err_out_free_res_3:
3307         pci_release_regions(pdev);
3308 err_out_mwi_2:
3309         pci_clear_mwi(pdev);
3310         pci_disable_device(pdev);
3311 err_out_free_dev_1:
3312         free_netdev(dev);
3313         goto out;
3314 }
3315
3316 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3317 {
3318         struct net_device *dev = pci_get_drvdata(pdev);
3319         struct rtl8169_private *tp = netdev_priv(dev);
3320
3321         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3322             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3323             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3324                 rtl8168_driver_stop(tp);
3325         }
3326
3327         cancel_delayed_work_sync(&tp->task);
3328
3329         rtl_release_firmware(tp);
3330
3331         unregister_netdev(dev);
3332
3333         if (pci_dev_run_wake(pdev))
3334                 pm_runtime_get_noresume(&pdev->dev);
3335
3336         /* restore original MAC address */
3337         rtl_rar_set(tp, dev->perm_addr);
3338
3339         rtl_disable_msi(pdev, tp);
3340         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3341         pci_set_drvdata(pdev, NULL);
3342 }
3343
3344 static int rtl8169_open(struct net_device *dev)
3345 {
3346         struct rtl8169_private *tp = netdev_priv(dev);
3347         void __iomem *ioaddr = tp->mmio_addr;
3348         struct pci_dev *pdev = tp->pci_dev;
3349         int retval = -ENOMEM;
3350
3351         pm_runtime_get_sync(&pdev->dev);
3352
3353         /*
3354          * Rx and Tx desscriptors needs 256 bytes alignment.
3355          * dma_alloc_coherent provides more.
3356          */
3357         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3358                                              &tp->TxPhyAddr, GFP_KERNEL);
3359         if (!tp->TxDescArray)
3360                 goto err_pm_runtime_put;
3361
3362         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3363                                              &tp->RxPhyAddr, GFP_KERNEL);
3364         if (!tp->RxDescArray)
3365                 goto err_free_tx_0;
3366
3367         retval = rtl8169_init_ring(dev);
3368         if (retval < 0)
3369                 goto err_free_rx_1;
3370
3371         INIT_DELAYED_WORK(&tp->task, NULL);
3372
3373         smp_mb();
3374
3375         retval = request_irq(dev->irq, rtl8169_interrupt,
3376                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3377                              dev->name, dev);
3378         if (retval < 0)
3379                 goto err_release_ring_2;
3380
3381         napi_enable(&tp->napi);
3382
3383         rtl8169_init_phy(dev, tp);
3384
3385         rtl8169_vlan_mode(dev);
3386
3387         rtl_pll_power_up(tp);
3388
3389         rtl_hw_start(dev);
3390
3391         rtl8169_request_timer(dev);
3392
3393         tp->saved_wolopts = 0;
3394         pm_runtime_put_noidle(&pdev->dev);
3395
3396         rtl8169_check_link_status(dev, tp, ioaddr);
3397 out:
3398         return retval;
3399
3400 err_release_ring_2:
3401         rtl8169_rx_clear(tp);
3402 err_free_rx_1:
3403         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3404                           tp->RxPhyAddr);
3405         tp->RxDescArray = NULL;
3406 err_free_tx_0:
3407         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3408                           tp->TxPhyAddr);
3409         tp->TxDescArray = NULL;
3410 err_pm_runtime_put:
3411         pm_runtime_put_noidle(&pdev->dev);
3412         goto out;
3413 }
3414
3415 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3416 {
3417         void __iomem *ioaddr = tp->mmio_addr;
3418
3419         /* Disable interrupts */
3420         rtl8169_irq_mask_and_ack(ioaddr);
3421
3422         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3423             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3424             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3425                 while (RTL_R8(TxPoll) & NPQ)
3426                         udelay(20);
3427
3428         }
3429
3430         /* Reset the chipset */
3431         RTL_W8(ChipCmd, CmdReset);
3432
3433         /* PCI commit */
3434         RTL_R8(ChipCmd);
3435 }
3436
3437 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3438 {
3439         void __iomem *ioaddr = tp->mmio_addr;
3440         u32 cfg = rtl8169_rx_config;
3441
3442         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3443         RTL_W32(RxConfig, cfg);
3444
3445         /* Set DMA burst size and Interframe Gap Time */
3446         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3447                 (InterFrameGap << TxInterFrameGapShift));
3448 }
3449
3450 static void rtl_hw_start(struct net_device *dev)
3451 {
3452         struct rtl8169_private *tp = netdev_priv(dev);
3453         void __iomem *ioaddr = tp->mmio_addr;
3454         unsigned int i;
3455
3456         /* Soft reset the chip. */
3457         RTL_W8(ChipCmd, CmdReset);
3458
3459         /* Check that the chip has finished the reset. */
3460         for (i = 0; i < 100; i++) {
3461                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3462                         break;
3463                 msleep_interruptible(1);
3464         }
3465
3466         tp->hw_start(dev);
3467
3468         netif_start_queue(dev);
3469 }
3470
3471
3472 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3473                                          void __iomem *ioaddr)
3474 {
3475         /*
3476          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3477          * register to be written before TxDescAddrLow to work.
3478          * Switching from MMIO to I/O access fixes the issue as well.
3479          */
3480         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3481         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3482         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3483         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3484 }
3485
3486 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3487 {
3488         u16 cmd;
3489
3490         cmd = RTL_R16(CPlusCmd);
3491         RTL_W16(CPlusCmd, cmd);
3492         return cmd;
3493 }
3494
3495 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3496 {
3497         /* Low hurts. Let's disable the filtering. */
3498         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3499 }
3500
3501 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3502 {
3503         static const struct {
3504                 u32 mac_version;
3505                 u32 clk;
3506                 u32 val;
3507         } cfg2_info [] = {
3508                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3509                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3510                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3511                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3512         }, *p = cfg2_info;
3513         unsigned int i;
3514         u32 clk;
3515
3516         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3517         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3518                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3519                         RTL_W32(0x7c, p->val);
3520                         break;
3521                 }
3522         }
3523 }
3524
3525 static void rtl_hw_start_8169(struct net_device *dev)
3526 {
3527         struct rtl8169_private *tp = netdev_priv(dev);
3528         void __iomem *ioaddr = tp->mmio_addr;
3529         struct pci_dev *pdev = tp->pci_dev;
3530
3531         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3532                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3533                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3534         }
3535
3536         RTL_W8(Cfg9346, Cfg9346_Unlock);
3537         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3538             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3539             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3540             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3541                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3542
3543         RTL_W8(EarlyTxThres, NoEarlyTx);
3544
3545         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3546
3547         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3548             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3549             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3550             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3551                 rtl_set_rx_tx_config_registers(tp);
3552
3553         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3554
3555         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3556             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3557                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3558                         "Bit-3 and bit-14 MUST be 1\n");
3559                 tp->cp_cmd |= (1 << 14);
3560         }
3561
3562         RTL_W16(CPlusCmd, tp->cp_cmd);
3563
3564         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3565
3566         /*
3567          * Undocumented corner. Supposedly:
3568          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3569          */
3570         RTL_W16(IntrMitigate, 0x0000);
3571
3572         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3573
3574         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3575             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3576             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3577             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3578                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3579                 rtl_set_rx_tx_config_registers(tp);
3580         }
3581
3582         RTL_W8(Cfg9346, Cfg9346_Lock);
3583
3584         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3585         RTL_R8(IntrMask);
3586
3587         RTL_W32(RxMissed, 0);
3588
3589         rtl_set_rx_mode(dev);
3590
3591         /* no early-rx interrupts */
3592         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3593
3594         /* Enable all known interrupts by setting the interrupt mask. */
3595         RTL_W16(IntrMask, tp->intr_event);
3596 }
3597
3598 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3599 {
3600         struct net_device *dev = pci_get_drvdata(pdev);
3601         struct rtl8169_private *tp = netdev_priv(dev);
3602         int cap = tp->pcie_cap;
3603
3604         if (cap) {
3605                 u16 ctl;
3606
3607                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3608                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3609                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3610         }
3611 }
3612
3613 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3614 {
3615         u32 csi;
3616
3617         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3618         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3619 }
3620
3621 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3622 {
3623         rtl_csi_access_enable(ioaddr, 0x17000000);
3624 }
3625
3626 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3627 {
3628         rtl_csi_access_enable(ioaddr, 0x27000000);
3629 }
3630
3631 struct ephy_info {
3632         unsigned int offset;
3633         u16 mask;
3634         u16 bits;
3635 };
3636
3637 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3638 {
3639         u16 w;
3640
3641         while (len-- > 0) {
3642                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3643                 rtl_ephy_write(ioaddr, e->offset, w);
3644                 e++;
3645         }
3646 }
3647
3648 static void rtl_disable_clock_request(struct pci_dev *pdev)
3649 {
3650         struct net_device *dev = pci_get_drvdata(pdev);
3651         struct rtl8169_private *tp = netdev_priv(dev);
3652         int cap = tp->pcie_cap;
3653
3654         if (cap) {
3655                 u16 ctl;
3656
3657                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3658                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3659                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3660         }
3661 }
3662
3663 static void rtl_enable_clock_request(struct pci_dev *pdev)
3664 {
3665         struct net_device *dev = pci_get_drvdata(pdev);
3666         struct rtl8169_private *tp = netdev_priv(dev);
3667         int cap = tp->pcie_cap;
3668
3669         if (cap) {
3670                 u16 ctl;
3671
3672                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3673                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3674                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3675         }
3676 }
3677
3678 #define R8168_CPCMD_QUIRK_MASK (\
3679         EnableBist | \
3680         Mac_dbgo_oe | \
3681         Force_half_dup | \
3682         Force_rxflow_en | \
3683         Force_txflow_en | \
3684         Cxpl_dbg_sel | \
3685         ASF | \
3686         PktCntrDisable | \
3687         Mac_dbgo_sel)
3688
3689 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3690 {
3691         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3692
3693         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3694
3695         rtl_tx_performance_tweak(pdev,
3696                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3697 }
3698
3699 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3700 {
3701         rtl_hw_start_8168bb(ioaddr, pdev);
3702
3703         RTL_W8(MaxTxPacketSize, TxPacketMax);
3704
3705         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3706 }
3707
3708 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3709 {
3710         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3711
3712         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3713
3714         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3715
3716         rtl_disable_clock_request(pdev);
3717
3718         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3719 }
3720
3721 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3722 {
3723         static const struct ephy_info e_info_8168cp[] = {
3724                 { 0x01, 0,      0x0001 },
3725                 { 0x02, 0x0800, 0x1000 },
3726                 { 0x03, 0,      0x0042 },
3727                 { 0x06, 0x0080, 0x0000 },
3728                 { 0x07, 0,      0x2000 }
3729         };
3730
3731         rtl_csi_access_enable_2(ioaddr);
3732
3733         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3734
3735         __rtl_hw_start_8168cp(ioaddr, pdev);
3736 }
3737
3738 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3739 {
3740         rtl_csi_access_enable_2(ioaddr);
3741
3742         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3743
3744         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3745
3746         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3747 }
3748
3749 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3750 {
3751         rtl_csi_access_enable_2(ioaddr);
3752
3753         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3754
3755         /* Magic. */
3756         RTL_W8(DBG_REG, 0x20);
3757
3758         RTL_W8(MaxTxPacketSize, TxPacketMax);
3759
3760         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3761
3762         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3763 }
3764
3765 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3766 {
3767         static const struct ephy_info e_info_8168c_1[] = {
3768                 { 0x02, 0x0800, 0x1000 },
3769                 { 0x03, 0,      0x0002 },
3770                 { 0x06, 0x0080, 0x0000 }
3771         };
3772
3773         rtl_csi_access_enable_2(ioaddr);
3774
3775         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3776
3777         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3778
3779         __rtl_hw_start_8168cp(ioaddr, pdev);
3780 }
3781
3782 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3783 {
3784         static const struct ephy_info e_info_8168c_2[] = {
3785                 { 0x01, 0,      0x0001 },
3786                 { 0x03, 0x0400, 0x0220 }
3787         };
3788
3789         rtl_csi_access_enable_2(ioaddr);
3790
3791         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3792
3793         __rtl_hw_start_8168cp(ioaddr, pdev);
3794 }
3795
3796 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3797 {
3798         rtl_hw_start_8168c_2(ioaddr, pdev);
3799 }
3800
3801 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3802 {
3803         rtl_csi_access_enable_2(ioaddr);
3804
3805         __rtl_hw_start_8168cp(ioaddr, pdev);
3806 }
3807
3808 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3809 {
3810         rtl_csi_access_enable_2(ioaddr);
3811
3812         rtl_disable_clock_request(pdev);
3813
3814         RTL_W8(MaxTxPacketSize, TxPacketMax);
3815
3816         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3817
3818         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3819 }
3820
3821 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
3822 {
3823         rtl_csi_access_enable_1(ioaddr);
3824
3825         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3826
3827         RTL_W8(MaxTxPacketSize, TxPacketMax);
3828
3829         rtl_disable_clock_request(pdev);
3830 }
3831
3832 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3833 {
3834         static const struct ephy_info e_info_8168d_4[] = {
3835                 { 0x0b, ~0,     0x48 },
3836                 { 0x19, 0x20,   0x50 },
3837                 { 0x0c, ~0,     0x20 }
3838         };
3839         int i;
3840
3841         rtl_csi_access_enable_1(ioaddr);
3842
3843         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3844
3845         RTL_W8(MaxTxPacketSize, TxPacketMax);
3846
3847         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3848                 const struct ephy_info *e = e_info_8168d_4 + i;
3849                 u16 w;
3850
3851                 w = rtl_ephy_read(ioaddr, e->offset);
3852                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3853         }
3854
3855         rtl_enable_clock_request(pdev);
3856 }
3857
3858 static void rtl_hw_start_8168(struct net_device *dev)
3859 {
3860         struct rtl8169_private *tp = netdev_priv(dev);
3861         void __iomem *ioaddr = tp->mmio_addr;
3862         struct pci_dev *pdev = tp->pci_dev;
3863
3864         RTL_W8(Cfg9346, Cfg9346_Unlock);
3865
3866         RTL_W8(MaxTxPacketSize, TxPacketMax);
3867
3868         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3869
3870         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3871
3872         RTL_W16(CPlusCmd, tp->cp_cmd);
3873
3874         RTL_W16(IntrMitigate, 0x5151);
3875
3876         /* Work around for RxFIFO overflow. */
3877         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3878             tp->mac_version == RTL_GIGA_MAC_VER_22) {
3879                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3880                 tp->intr_event &= ~RxOverflow;
3881         }
3882
3883         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3884
3885         rtl_set_rx_mode(dev);
3886
3887         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3888                 (InterFrameGap << TxInterFrameGapShift));
3889
3890         RTL_R8(IntrMask);
3891
3892         switch (tp->mac_version) {
3893         case RTL_GIGA_MAC_VER_11:
3894                 rtl_hw_start_8168bb(ioaddr, pdev);
3895                 break;
3896
3897         case RTL_GIGA_MAC_VER_12:
3898         case RTL_GIGA_MAC_VER_17:
3899                 rtl_hw_start_8168bef(ioaddr, pdev);
3900                 break;
3901
3902         case RTL_GIGA_MAC_VER_18:
3903                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3904                 break;
3905
3906         case RTL_GIGA_MAC_VER_19:
3907                 rtl_hw_start_8168c_1(ioaddr, pdev);
3908                 break;
3909
3910         case RTL_GIGA_MAC_VER_20:
3911                 rtl_hw_start_8168c_2(ioaddr, pdev);
3912                 break;
3913
3914         case RTL_GIGA_MAC_VER_21:
3915                 rtl_hw_start_8168c_3(ioaddr, pdev);
3916                 break;
3917
3918         case RTL_GIGA_MAC_VER_22:
3919                 rtl_hw_start_8168c_4(ioaddr, pdev);
3920                 break;
3921
3922         case RTL_GIGA_MAC_VER_23:
3923                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3924                 break;
3925
3926         case RTL_GIGA_MAC_VER_24:
3927                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3928                 break;
3929
3930         case RTL_GIGA_MAC_VER_25:
3931         case RTL_GIGA_MAC_VER_26:
3932         case RTL_GIGA_MAC_VER_27:
3933                 rtl_hw_start_8168d(ioaddr, pdev);
3934                 break;
3935
3936         case RTL_GIGA_MAC_VER_28:
3937                 rtl_hw_start_8168d_4(ioaddr, pdev);
3938                 break;
3939         case RTL_GIGA_MAC_VER_31:
3940                 rtl_hw_start_8168dp(ioaddr, pdev);
3941                 break;
3942
3943
3944         default:
3945                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3946                         dev->name, tp->mac_version);
3947                 break;
3948         }
3949
3950         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3951
3952         RTL_W8(Cfg9346, Cfg9346_Lock);
3953
3954         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3955
3956         RTL_W16(IntrMask, tp->intr_event);
3957 }
3958
3959 #define R810X_CPCMD_QUIRK_MASK (\
3960         EnableBist | \
3961         Mac_dbgo_oe | \
3962         Force_half_dup | \
3963         Force_rxflow_en | \
3964         Force_txflow_en | \
3965         Cxpl_dbg_sel | \
3966         ASF | \
3967         PktCntrDisable | \
3968         Mac_dbgo_sel)
3969
3970 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3971 {
3972         static const struct ephy_info e_info_8102e_1[] = {
3973                 { 0x01, 0, 0x6e65 },
3974                 { 0x02, 0, 0x091f },
3975                 { 0x03, 0, 0xc2f9 },
3976                 { 0x06, 0, 0xafb5 },
3977                 { 0x07, 0, 0x0e00 },
3978                 { 0x19, 0, 0xec80 },
3979                 { 0x01, 0, 0x2e65 },
3980                 { 0x01, 0, 0x6e65 }
3981         };
3982         u8 cfg1;
3983
3984         rtl_csi_access_enable_2(ioaddr);
3985
3986         RTL_W8(DBG_REG, FIX_NAK_1);
3987
3988         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3989
3990         RTL_W8(Config1,
3991                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3992         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3993
3994         cfg1 = RTL_R8(Config1);
3995         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3996                 RTL_W8(Config1, cfg1 & ~LEDS0);
3997
3998         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3999 }
4000
4001 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4002 {
4003         rtl_csi_access_enable_2(ioaddr);
4004
4005         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4006
4007         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4008         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4009 }
4010
4011 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4012 {
4013         rtl_hw_start_8102e_2(ioaddr, pdev);
4014
4015         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4016 }
4017
4018 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4019 {
4020         static const struct ephy_info e_info_8105e_1[] = {
4021                 { 0x07, 0, 0x4000 },
4022                 { 0x19, 0, 0x0200 },
4023                 { 0x19, 0, 0x0020 },
4024                 { 0x1e, 0, 0x2000 },
4025                 { 0x03, 0, 0x0001 },
4026                 { 0x19, 0, 0x0100 },
4027                 { 0x19, 0, 0x0004 },
4028                 { 0x0a, 0, 0x0020 }
4029         };
4030
4031         /* Force LAN exit from ASPM if Rx/Tx are not idel */
4032         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4033
4034         /* disable Early Tally Counter */
4035         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4036
4037         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4038         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4039
4040         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4041 }
4042
4043 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4044 {
4045         rtl_hw_start_8105e_1(ioaddr, pdev);
4046         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4047 }
4048
4049 static void rtl_hw_start_8101(struct net_device *dev)
4050 {
4051         struct rtl8169_private *tp = netdev_priv(dev);
4052         void __iomem *ioaddr = tp->mmio_addr;
4053         struct pci_dev *pdev = tp->pci_dev;
4054
4055         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4056             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
4057                 int cap = tp->pcie_cap;
4058
4059                 if (cap) {
4060                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4061                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4062                 }
4063         }
4064
4065         RTL_W8(Cfg9346, Cfg9346_Unlock);
4066
4067         switch (tp->mac_version) {
4068         case RTL_GIGA_MAC_VER_07:
4069                 rtl_hw_start_8102e_1(ioaddr, pdev);
4070                 break;
4071
4072         case RTL_GIGA_MAC_VER_08:
4073                 rtl_hw_start_8102e_3(ioaddr, pdev);
4074                 break;
4075
4076         case RTL_GIGA_MAC_VER_09:
4077                 rtl_hw_start_8102e_2(ioaddr, pdev);
4078                 break;
4079
4080         case RTL_GIGA_MAC_VER_29:
4081                 rtl_hw_start_8105e_1(ioaddr, pdev);
4082                 break;
4083         case RTL_GIGA_MAC_VER_30:
4084                 rtl_hw_start_8105e_2(ioaddr, pdev);
4085                 break;
4086         }
4087
4088         RTL_W8(Cfg9346, Cfg9346_Lock);
4089
4090         RTL_W8(MaxTxPacketSize, TxPacketMax);
4091
4092         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4093
4094         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4095         RTL_W16(CPlusCmd, tp->cp_cmd);
4096
4097         RTL_W16(IntrMitigate, 0x0000);
4098
4099         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4100
4101         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4102         rtl_set_rx_tx_config_registers(tp);
4103
4104         RTL_R8(IntrMask);
4105
4106         rtl_set_rx_mode(dev);
4107
4108         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4109
4110         RTL_W16(IntrMask, tp->intr_event);
4111 }
4112
4113 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4114 {
4115         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4116                 return -EINVAL;
4117
4118         dev->mtu = new_mtu;
4119         return 0;
4120 }
4121
4122 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4123 {
4124         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4125         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4126 }
4127
4128 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4129                                      void **data_buff, struct RxDesc *desc)
4130 {
4131         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4132                          DMA_FROM_DEVICE);
4133
4134         kfree(*data_buff);
4135         *data_buff = NULL;
4136         rtl8169_make_unusable_by_asic(desc);
4137 }
4138
4139 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4140 {
4141         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4142
4143         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4144 }
4145
4146 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4147                                        u32 rx_buf_sz)
4148 {
4149         desc->addr = cpu_to_le64(mapping);
4150         wmb();
4151         rtl8169_mark_to_asic(desc, rx_buf_sz);
4152 }
4153
4154 static inline void *rtl8169_align(void *data)
4155 {
4156         return (void *)ALIGN((long)data, 16);
4157 }
4158
4159 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4160                                              struct RxDesc *desc)
4161 {
4162         void *data;
4163         dma_addr_t mapping;
4164         struct device *d = &tp->pci_dev->dev;
4165         struct net_device *dev = tp->dev;
4166         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4167
4168         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4169         if (!data)
4170                 return NULL;
4171
4172         if (rtl8169_align(data) != data) {
4173                 kfree(data);
4174                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4175                 if (!data)
4176                         return NULL;
4177         }
4178
4179         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4180                                  DMA_FROM_DEVICE);
4181         if (unlikely(dma_mapping_error(d, mapping))) {
4182                 if (net_ratelimit())
4183                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4184                 goto err_out;
4185         }
4186
4187         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4188         return data;
4189
4190 err_out:
4191         kfree(data);
4192         return NULL;
4193 }
4194
4195 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4196 {
4197         unsigned int i;
4198
4199         for (i = 0; i < NUM_RX_DESC; i++) {
4200                 if (tp->Rx_databuff[i]) {
4201                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4202                                             tp->RxDescArray + i);
4203                 }
4204         }
4205 }
4206
4207 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4208 {
4209         desc->opts1 |= cpu_to_le32(RingEnd);
4210 }
4211
4212 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4213 {
4214         unsigned int i;
4215
4216         for (i = 0; i < NUM_RX_DESC; i++) {
4217                 void *data;
4218
4219                 if (tp->Rx_databuff[i])
4220                         continue;
4221
4222                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4223                 if (!data) {
4224                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4225                         goto err_out;
4226                 }
4227                 tp->Rx_databuff[i] = data;
4228         }
4229
4230         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4231         return 0;
4232
4233 err_out:
4234         rtl8169_rx_clear(tp);
4235         return -ENOMEM;
4236 }
4237
4238 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4239 {
4240         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4241 }
4242
4243 static int rtl8169_init_ring(struct net_device *dev)
4244 {
4245         struct rtl8169_private *tp = netdev_priv(dev);
4246
4247         rtl8169_init_ring_indexes(tp);
4248
4249         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4250         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4251
4252         return rtl8169_rx_fill(tp);
4253 }
4254
4255 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4256                                  struct TxDesc *desc)
4257 {
4258         unsigned int len = tx_skb->len;
4259
4260         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4261
4262         desc->opts1 = 0x00;
4263         desc->opts2 = 0x00;
4264         desc->addr = 0x00;
4265         tx_skb->len = 0;
4266 }
4267
4268 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4269                                    unsigned int n)
4270 {
4271         unsigned int i;
4272
4273         for (i = 0; i < n; i++) {
4274                 unsigned int entry = (start + i) % NUM_TX_DESC;
4275                 struct ring_info *tx_skb = tp->tx_skb + entry;
4276                 unsigned int len = tx_skb->len;
4277
4278                 if (len) {
4279                         struct sk_buff *skb = tx_skb->skb;
4280
4281                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4282                                              tp->TxDescArray + entry);
4283                         if (skb) {
4284                                 tp->dev->stats.tx_dropped++;
4285                                 dev_kfree_skb(skb);
4286                                 tx_skb->skb = NULL;
4287                         }
4288                 }
4289         }
4290 }
4291
4292 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4293 {
4294         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4295         tp->cur_tx = tp->dirty_tx = 0;
4296 }
4297
4298 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4299 {
4300         struct rtl8169_private *tp = netdev_priv(dev);
4301
4302         PREPARE_DELAYED_WORK(&tp->task, task);
4303         schedule_delayed_work(&tp->task, 4);
4304 }
4305
4306 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4307 {
4308         struct rtl8169_private *tp = netdev_priv(dev);
4309         void __iomem *ioaddr = tp->mmio_addr;
4310
4311         synchronize_irq(dev->irq);
4312
4313         /* Wait for any pending NAPI task to complete */
4314         napi_disable(&tp->napi);
4315
4316         rtl8169_irq_mask_and_ack(ioaddr);
4317
4318         tp->intr_mask = 0xffff;
4319         RTL_W16(IntrMask, tp->intr_event);
4320         napi_enable(&tp->napi);
4321 }
4322
4323 static void rtl8169_reinit_task(struct work_struct *work)
4324 {
4325         struct rtl8169_private *tp =
4326                 container_of(work, struct rtl8169_private, task.work);
4327         struct net_device *dev = tp->dev;
4328         int ret;
4329
4330         rtnl_lock();
4331
4332         if (!netif_running(dev))
4333                 goto out_unlock;
4334
4335         rtl8169_wait_for_quiescence(dev);
4336         rtl8169_close(dev);
4337
4338         ret = rtl8169_open(dev);
4339         if (unlikely(ret < 0)) {
4340                 if (net_ratelimit())
4341                         netif_err(tp, drv, dev,
4342                                   "reinit failure (status = %d). Rescheduling\n",
4343                                   ret);
4344                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4345         }
4346
4347 out_unlock:
4348         rtnl_unlock();
4349 }
4350
4351 static void rtl8169_reset_task(struct work_struct *work)
4352 {
4353         struct rtl8169_private *tp =
4354                 container_of(work, struct rtl8169_private, task.work);
4355         struct net_device *dev = tp->dev;
4356
4357         rtnl_lock();
4358
4359         if (!netif_running(dev))
4360                 goto out_unlock;
4361
4362         rtl8169_wait_for_quiescence(dev);
4363
4364         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4365         rtl8169_tx_clear(tp);
4366
4367         if (tp->dirty_rx == tp->cur_rx) {
4368                 rtl8169_init_ring_indexes(tp);
4369                 rtl_hw_start(dev);
4370                 netif_wake_queue(dev);
4371                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4372         } else {
4373                 if (net_ratelimit())
4374                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4375                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4376         }
4377
4378 out_unlock:
4379         rtnl_unlock();
4380 }
4381
4382 static void rtl8169_tx_timeout(struct net_device *dev)
4383 {
4384         struct rtl8169_private *tp = netdev_priv(dev);
4385
4386         rtl8169_hw_reset(tp);
4387
4388         /* Let's wait a bit while any (async) irq lands on */
4389         rtl8169_schedule_work(dev, rtl8169_reset_task);
4390 }
4391
4392 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4393                               u32 opts1)
4394 {
4395         struct skb_shared_info *info = skb_shinfo(skb);
4396         unsigned int cur_frag, entry;
4397         struct TxDesc * uninitialized_var(txd);
4398         struct device *d = &tp->pci_dev->dev;
4399
4400         entry = tp->cur_tx;
4401         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4402                 skb_frag_t *frag = info->frags + cur_frag;
4403                 dma_addr_t mapping;
4404                 u32 status, len;
4405                 void *addr;
4406
4407                 entry = (entry + 1) % NUM_TX_DESC;
4408
4409                 txd = tp->TxDescArray + entry;
4410                 len = frag->size;
4411                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4412                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4413                 if (unlikely(dma_mapping_error(d, mapping))) {
4414                         if (net_ratelimit())
4415                                 netif_err(tp, drv, tp->dev,
4416                                           "Failed to map TX fragments DMA!\n");
4417                         goto err_out;
4418                 }
4419
4420                 /* anti gcc 2.95.3 bugware (sic) */
4421                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4422
4423                 txd->opts1 = cpu_to_le32(status);
4424                 txd->addr = cpu_to_le64(mapping);
4425
4426                 tp->tx_skb[entry].len = len;
4427         }
4428
4429         if (cur_frag) {
4430                 tp->tx_skb[entry].skb = skb;
4431                 txd->opts1 |= cpu_to_le32(LastFrag);
4432         }
4433
4434         return cur_frag;
4435
4436 err_out:
4437         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4438         return -EIO;
4439 }
4440
4441 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4442 {
4443         if (dev->features & NETIF_F_TSO) {
4444                 u32 mss = skb_shinfo(skb)->gso_size;
4445
4446                 if (mss)
4447                         return LargeSend | ((mss & MSSMask) << MSSShift);
4448         }
4449         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4450                 const struct iphdr *ip = ip_hdr(skb);
4451
4452                 if (ip->protocol == IPPROTO_TCP)
4453                         return IPCS | TCPCS;
4454                 else if (ip->protocol == IPPROTO_UDP)
4455                         return IPCS | UDPCS;
4456                 WARN_ON(1);     /* we need a WARN() */
4457         }
4458         return 0;
4459 }
4460
4461 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4462                                       struct net_device *dev)
4463 {
4464         struct rtl8169_private *tp = netdev_priv(dev);
4465         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4466         struct TxDesc *txd = tp->TxDescArray + entry;
4467         void __iomem *ioaddr = tp->mmio_addr;
4468         struct device *d = &tp->pci_dev->dev;
4469         dma_addr_t mapping;
4470         u32 status, len;
4471         u32 opts1;
4472         int frags;
4473
4474         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4475                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4476                 goto err_stop_0;
4477         }
4478
4479         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4480                 goto err_stop_0;
4481
4482         len = skb_headlen(skb);
4483         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4484         if (unlikely(dma_mapping_error(d, mapping))) {
4485                 if (net_ratelimit())
4486                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4487                 goto err_dma_0;
4488         }
4489
4490         tp->tx_skb[entry].len = len;
4491         txd->addr = cpu_to_le64(mapping);
4492         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4493
4494         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4495
4496         frags = rtl8169_xmit_frags(tp, skb, opts1);
4497         if (frags < 0)
4498                 goto err_dma_1;
4499         else if (frags)
4500                 opts1 |= FirstFrag;
4501         else {
4502                 opts1 |= FirstFrag | LastFrag;
4503                 tp->tx_skb[entry].skb = skb;
4504         }
4505
4506         wmb();
4507
4508         /* anti gcc 2.95.3 bugware (sic) */
4509         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4510         txd->opts1 = cpu_to_le32(status);
4511
4512         tp->cur_tx += frags + 1;
4513
4514         wmb();
4515
4516         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4517
4518         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4519                 netif_stop_queue(dev);
4520                 smp_rmb();
4521                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4522                         netif_wake_queue(dev);
4523         }
4524
4525         return NETDEV_TX_OK;
4526
4527 err_dma_1:
4528         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4529 err_dma_0:
4530         dev_kfree_skb(skb);
4531         dev->stats.tx_dropped++;
4532         return NETDEV_TX_OK;
4533
4534 err_stop_0:
4535         netif_stop_queue(dev);
4536         dev->stats.tx_dropped++;
4537         return NETDEV_TX_BUSY;
4538 }
4539
4540 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4541 {
4542         struct rtl8169_private *tp = netdev_priv(dev);
4543         struct pci_dev *pdev = tp->pci_dev;
4544         u16 pci_status, pci_cmd;
4545
4546         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4547         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4548
4549         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4550                   pci_cmd, pci_status);
4551
4552         /*
4553          * The recovery sequence below admits a very elaborated explanation:
4554          * - it seems to work;
4555          * - I did not see what else could be done;
4556          * - it makes iop3xx happy.
4557          *
4558          * Feel free to adjust to your needs.
4559          */
4560         if (pdev->broken_parity_status)
4561                 pci_cmd &= ~PCI_COMMAND_PARITY;
4562         else
4563                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4564
4565         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4566
4567         pci_write_config_word(pdev, PCI_STATUS,
4568                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4569                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4570                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4571
4572         /* The infamous DAC f*ckup only happens at boot time */
4573         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4574                 void __iomem *ioaddr = tp->mmio_addr;
4575
4576                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4577                 tp->cp_cmd &= ~PCIDAC;
4578                 RTL_W16(CPlusCmd, tp->cp_cmd);
4579                 dev->features &= ~NETIF_F_HIGHDMA;
4580         }
4581
4582         rtl8169_hw_reset(tp);
4583
4584         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4585 }
4586
4587 static void rtl8169_tx_interrupt(struct net_device *dev,
4588                                  struct rtl8169_private *tp,
4589                                  void __iomem *ioaddr)
4590 {
4591         unsigned int dirty_tx, tx_left;
4592
4593         dirty_tx = tp->dirty_tx;
4594         smp_rmb();
4595         tx_left = tp->cur_tx - dirty_tx;
4596
4597         while (tx_left > 0) {
4598                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4599                 struct ring_info *tx_skb = tp->tx_skb + entry;
4600                 u32 status;
4601
4602                 rmb();
4603                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4604                 if (status & DescOwn)
4605                         break;
4606
4607                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4608                                      tp->TxDescArray + entry);
4609                 if (status & LastFrag) {
4610                         dev->stats.tx_packets++;
4611                         dev->stats.tx_bytes += tx_skb->skb->len;
4612                         dev_kfree_skb(tx_skb->skb);
4613                         tx_skb->skb = NULL;
4614                 }
4615                 dirty_tx++;
4616                 tx_left--;
4617         }
4618
4619         if (tp->dirty_tx != dirty_tx) {
4620                 tp->dirty_tx = dirty_tx;
4621                 smp_wmb();
4622                 if (netif_queue_stopped(dev) &&
4623                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4624                         netif_wake_queue(dev);
4625                 }
4626                 /*
4627                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4628                  * too close. Let's kick an extra TxPoll request when a burst
4629                  * of start_xmit activity is detected (if it is not detected,
4630                  * it is slow enough). -- FR
4631                  */
4632                 smp_rmb();
4633                 if (tp->cur_tx != dirty_tx)
4634                         RTL_W8(TxPoll, NPQ);
4635         }
4636 }
4637
4638 static inline int rtl8169_fragmented_frame(u32 status)
4639 {
4640         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4641 }
4642
4643 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4644 {
4645         u32 status = opts1 & RxProtoMask;
4646
4647         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4648             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4649                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4650         else
4651                 skb_checksum_none_assert(skb);
4652 }
4653
4654 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4655                                            struct rtl8169_private *tp,
4656                                            int pkt_size,
4657                                            dma_addr_t addr)
4658 {
4659         struct sk_buff *skb;
4660         struct device *d = &tp->pci_dev->dev;
4661
4662         data = rtl8169_align(data);
4663         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4664         prefetch(data);
4665         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4666         if (skb)
4667                 memcpy(skb->data, data, pkt_size);
4668         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4669
4670         return skb;
4671 }
4672
4673 /*
4674  * Warning : rtl8169_rx_interrupt() might be called :
4675  * 1) from NAPI (softirq) context
4676  *      (polling = 1 : we should call netif_receive_skb())
4677  * 2) from process context (rtl8169_reset_task())
4678  *      (polling = 0 : we must call netif_rx() instead)
4679  */
4680 static int rtl8169_rx_interrupt(struct net_device *dev,
4681                                 struct rtl8169_private *tp,
4682                                 void __iomem *ioaddr, u32 budget)
4683 {
4684         unsigned int cur_rx, rx_left;
4685         unsigned int count;
4686         int polling = (budget != ~(u32)0) ? 1 : 0;
4687
4688         cur_rx = tp->cur_rx;
4689         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4690         rx_left = min(rx_left, budget);
4691
4692         for (; rx_left > 0; rx_left--, cur_rx++) {
4693                 unsigned int entry = cur_rx % NUM_RX_DESC;
4694                 struct RxDesc *desc = tp->RxDescArray + entry;
4695                 u32 status;
4696
4697                 rmb();
4698                 status = le32_to_cpu(desc->opts1);
4699
4700                 if (status & DescOwn)
4701                         break;
4702                 if (unlikely(status & RxRES)) {
4703                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4704                                    status);
4705                         dev->stats.rx_errors++;
4706                         if (status & (RxRWT | RxRUNT))
4707                                 dev->stats.rx_length_errors++;
4708                         if (status & RxCRC)
4709                                 dev->stats.rx_crc_errors++;
4710                         if (status & RxFOVF) {
4711                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4712                                 dev->stats.rx_fifo_errors++;
4713                         }
4714                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4715                 } else {
4716                         struct sk_buff *skb;
4717                         dma_addr_t addr = le64_to_cpu(desc->addr);
4718                         int pkt_size = (status & 0x00001FFF) - 4;
4719
4720                         /*
4721                          * The driver does not support incoming fragmented
4722                          * frames. They are seen as a symptom of over-mtu
4723                          * sized frames.
4724                          */
4725                         if (unlikely(rtl8169_fragmented_frame(status))) {
4726                                 dev->stats.rx_dropped++;
4727                                 dev->stats.rx_length_errors++;
4728                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4729                                 continue;
4730                         }
4731
4732                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4733                                                   tp, pkt_size, addr);
4734                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4735                         if (!skb) {
4736                                 dev->stats.rx_dropped++;
4737                                 continue;
4738                         }
4739
4740                         rtl8169_rx_csum(skb, status);
4741                         skb_put(skb, pkt_size);
4742                         skb->protocol = eth_type_trans(skb, dev);
4743
4744                         rtl8169_rx_vlan_tag(desc, skb);
4745
4746                         if (likely(polling))
4747                                 napi_gro_receive(&tp->napi, skb);
4748                         else
4749                                 netif_rx(skb);
4750
4751                         dev->stats.rx_bytes += pkt_size;
4752                         dev->stats.rx_packets++;
4753                 }
4754
4755                 /* Work around for AMD plateform. */
4756                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4757                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4758                         desc->opts2 = 0;
4759                         cur_rx++;
4760                 }
4761         }
4762
4763         count = cur_rx - tp->cur_rx;
4764         tp->cur_rx = cur_rx;
4765
4766         tp->dirty_rx += count;
4767
4768         return count;
4769 }
4770
4771 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4772 {
4773         struct net_device *dev = dev_instance;
4774         struct rtl8169_private *tp = netdev_priv(dev);
4775         void __iomem *ioaddr = tp->mmio_addr;
4776         int handled = 0;
4777         int status;
4778
4779         /* loop handling interrupts until we have no new ones or
4780          * we hit a invalid/hotplug case.
4781          */
4782         status = RTL_R16(IntrStatus);
4783         while (status && status != 0xffff) {
4784                 handled = 1;
4785
4786                 /* Handle all of the error cases first. These will reset
4787                  * the chip, so just exit the loop.
4788                  */
4789                 if (unlikely(!netif_running(dev))) {
4790                         rtl8169_asic_down(ioaddr);
4791                         break;
4792                 }
4793
4794                 if (unlikely(status & RxFIFOOver)) {
4795                         switch (tp->mac_version) {
4796                         /* Work around for rx fifo overflow */
4797                         case RTL_GIGA_MAC_VER_11:
4798                         case RTL_GIGA_MAC_VER_22:
4799                         case RTL_GIGA_MAC_VER_26:
4800                                 netif_stop_queue(dev);
4801                                 rtl8169_tx_timeout(dev);
4802                                 goto done;
4803                         /* Testers needed. */
4804                         case RTL_GIGA_MAC_VER_17:
4805                         case RTL_GIGA_MAC_VER_19:
4806                         case RTL_GIGA_MAC_VER_20:
4807                         case RTL_GIGA_MAC_VER_21:
4808                         case RTL_GIGA_MAC_VER_23:
4809                         case RTL_GIGA_MAC_VER_24:
4810                         case RTL_GIGA_MAC_VER_27:
4811                         case RTL_GIGA_MAC_VER_28:
4812                         case RTL_GIGA_MAC_VER_31:
4813                         /* Experimental science. Pktgen proof. */
4814                         case RTL_GIGA_MAC_VER_12:
4815                         case RTL_GIGA_MAC_VER_25:
4816                                 if (status == RxFIFOOver)
4817                                         goto done;
4818                                 break;
4819                         default:
4820                                 break;
4821                         }
4822                 }
4823
4824                 if (unlikely(status & SYSErr)) {
4825                         rtl8169_pcierr_interrupt(dev);
4826                         break;
4827                 }
4828
4829                 if (status & LinkChg)
4830                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4831
4832                 /* We need to see the lastest version of tp->intr_mask to
4833                  * avoid ignoring an MSI interrupt and having to wait for
4834                  * another event which may never come.
4835                  */
4836                 smp_rmb();
4837                 if (status & tp->intr_mask & tp->napi_event) {
4838                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4839                         tp->intr_mask = ~tp->napi_event;
4840
4841                         if (likely(napi_schedule_prep(&tp->napi)))
4842                                 __napi_schedule(&tp->napi);
4843                         else
4844                                 netif_info(tp, intr, dev,
4845                                            "interrupt %04x in poll\n", status);
4846                 }
4847
4848                 /* We only get a new MSI interrupt when all active irq
4849                  * sources on the chip have been acknowledged. So, ack
4850                  * everything we've seen and check if new sources have become
4851                  * active to avoid blocking all interrupts from the chip.
4852                  */
4853                 RTL_W16(IntrStatus,
4854                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4855                 status = RTL_R16(IntrStatus);
4856         }
4857 done:
4858         return IRQ_RETVAL(handled);
4859 }
4860
4861 static int rtl8169_poll(struct napi_struct *napi, int budget)
4862 {
4863         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4864         struct net_device *dev = tp->dev;
4865         void __iomem *ioaddr = tp->mmio_addr;
4866         int work_done;
4867
4868         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4869         rtl8169_tx_interrupt(dev, tp, ioaddr);
4870
4871         if (work_done < budget) {
4872                 napi_complete(napi);
4873
4874                 /* We need for force the visibility of tp->intr_mask
4875                  * for other CPUs, as we can loose an MSI interrupt
4876                  * and potentially wait for a retransmit timeout if we don't.
4877                  * The posted write to IntrMask is safe, as it will
4878                  * eventually make it to the chip and we won't loose anything
4879                  * until it does.
4880                  */
4881                 tp->intr_mask = 0xffff;
4882                 wmb();
4883                 RTL_W16(IntrMask, tp->intr_event);
4884         }
4885
4886         return work_done;
4887 }
4888
4889 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4890 {
4891         struct rtl8169_private *tp = netdev_priv(dev);
4892
4893         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4894                 return;
4895
4896         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4897         RTL_W32(RxMissed, 0);
4898 }
4899
4900 static void rtl8169_down(struct net_device *dev)
4901 {
4902         struct rtl8169_private *tp = netdev_priv(dev);
4903         void __iomem *ioaddr = tp->mmio_addr;
4904
4905         rtl8169_delete_timer(dev);
4906
4907         netif_stop_queue(dev);
4908
4909         napi_disable(&tp->napi);
4910
4911         spin_lock_irq(&tp->lock);
4912
4913         rtl8169_asic_down(ioaddr);
4914         /*
4915          * At this point device interrupts can not be enabled in any function,
4916          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4917          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4918          */
4919         rtl8169_rx_missed(dev, ioaddr);
4920
4921         spin_unlock_irq(&tp->lock);
4922
4923         synchronize_irq(dev->irq);
4924
4925         /* Give a racing hard_start_xmit a few cycles to complete. */
4926         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4927
4928         rtl8169_tx_clear(tp);
4929
4930         rtl8169_rx_clear(tp);
4931
4932         rtl_pll_power_down(tp);
4933 }
4934
4935 static int rtl8169_close(struct net_device *dev)
4936 {
4937         struct rtl8169_private *tp = netdev_priv(dev);
4938         struct pci_dev *pdev = tp->pci_dev;
4939
4940         pm_runtime_get_sync(&pdev->dev);
4941
4942         /* update counters before going down */
4943         rtl8169_update_counters(dev);
4944
4945         rtl8169_down(dev);
4946
4947         free_irq(dev->irq, dev);
4948
4949         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4950                           tp->RxPhyAddr);
4951         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4952                           tp->TxPhyAddr);
4953         tp->TxDescArray = NULL;
4954         tp->RxDescArray = NULL;
4955
4956         pm_runtime_put_sync(&pdev->dev);
4957
4958         return 0;
4959 }
4960
4961 static void rtl_set_rx_mode(struct net_device *dev)
4962 {
4963         struct rtl8169_private *tp = netdev_priv(dev);
4964         void __iomem *ioaddr = tp->mmio_addr;
4965         unsigned long flags;
4966         u32 mc_filter[2];       /* Multicast hash filter */
4967         int rx_mode;
4968         u32 tmp = 0;
4969
4970         if (dev->flags & IFF_PROMISC) {
4971                 /* Unconditionally log net taps. */
4972                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4973                 rx_mode =
4974                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4975                     AcceptAllPhys;
4976                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4977         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4978                    (dev->flags & IFF_ALLMULTI)) {
4979                 /* Too many to filter perfectly -- accept all multicasts. */
4980                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4981                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4982         } else {
4983                 struct netdev_hw_addr *ha;
4984
4985                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4986                 mc_filter[1] = mc_filter[0] = 0;
4987                 netdev_for_each_mc_addr(ha, dev) {
4988                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4989                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4990                         rx_mode |= AcceptMulticast;
4991                 }
4992         }
4993
4994         spin_lock_irqsave(&tp->lock, flags);
4995
4996         tmp = rtl8169_rx_config | rx_mode |
4997               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4998
4999         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5000                 u32 data = mc_filter[0];
5001
5002                 mc_filter[0] = swab32(mc_filter[1]);
5003                 mc_filter[1] = swab32(data);
5004         }
5005
5006         RTL_W32(MAR0 + 4, mc_filter[1]);
5007         RTL_W32(MAR0 + 0, mc_filter[0]);
5008
5009         RTL_W32(RxConfig, tmp);
5010
5011         spin_unlock_irqrestore(&tp->lock, flags);
5012 }
5013
5014 /**
5015  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5016  *  @dev: The Ethernet Device to get statistics for
5017  *
5018  *  Get TX/RX statistics for rtl8169
5019  */
5020 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5021 {
5022         struct rtl8169_private *tp = netdev_priv(dev);
5023         void __iomem *ioaddr = tp->mmio_addr;
5024         unsigned long flags;
5025
5026         if (netif_running(dev)) {
5027                 spin_lock_irqsave(&tp->lock, flags);
5028                 rtl8169_rx_missed(dev, ioaddr);
5029                 spin_unlock_irqrestore(&tp->lock, flags);
5030         }
5031
5032         return &dev->stats;
5033 }
5034
5035 static void rtl8169_net_suspend(struct net_device *dev)
5036 {
5037         struct rtl8169_private *tp = netdev_priv(dev);
5038
5039         if (!netif_running(dev))
5040                 return;
5041
5042         rtl_pll_power_down(tp);
5043
5044         netif_device_detach(dev);
5045         netif_stop_queue(dev);
5046 }
5047
5048 #ifdef CONFIG_PM
5049
5050 static int rtl8169_suspend(struct device *device)
5051 {
5052         struct pci_dev *pdev = to_pci_dev(device);
5053         struct net_device *dev = pci_get_drvdata(pdev);
5054
5055         rtl8169_net_suspend(dev);
5056
5057         return 0;
5058 }
5059
5060 static void __rtl8169_resume(struct net_device *dev)
5061 {
5062         struct rtl8169_private *tp = netdev_priv(dev);
5063
5064         netif_device_attach(dev);
5065
5066         rtl_pll_power_up(tp);
5067
5068         rtl8169_schedule_work(dev, rtl8169_reset_task);
5069 }
5070
5071 static int rtl8169_resume(struct device *device)
5072 {
5073         struct pci_dev *pdev = to_pci_dev(device);
5074         struct net_device *dev = pci_get_drvdata(pdev);
5075         struct rtl8169_private *tp = netdev_priv(dev);
5076
5077         rtl8169_init_phy(dev, tp);
5078
5079         if (netif_running(dev))
5080                 __rtl8169_resume(dev);
5081
5082         return 0;
5083 }
5084
5085 static int rtl8169_runtime_suspend(struct device *device)
5086 {
5087         struct pci_dev *pdev = to_pci_dev(device);
5088         struct net_device *dev = pci_get_drvdata(pdev);
5089         struct rtl8169_private *tp = netdev_priv(dev);
5090
5091         if (!tp->TxDescArray)
5092                 return 0;
5093
5094         spin_lock_irq(&tp->lock);
5095         tp->saved_wolopts = __rtl8169_get_wol(tp);
5096         __rtl8169_set_wol(tp, WAKE_ANY);
5097         spin_unlock_irq(&tp->lock);
5098
5099         rtl8169_net_suspend(dev);
5100
5101         return 0;
5102 }
5103
5104 static int rtl8169_runtime_resume(struct device *device)
5105 {
5106         struct pci_dev *pdev = to_pci_dev(device);
5107         struct net_device *dev = pci_get_drvdata(pdev);
5108         struct rtl8169_private *tp = netdev_priv(dev);
5109
5110         if (!tp->TxDescArray)
5111                 return 0;
5112
5113         spin_lock_irq(&tp->lock);
5114         __rtl8169_set_wol(tp, tp->saved_wolopts);
5115         tp->saved_wolopts = 0;
5116         spin_unlock_irq(&tp->lock);
5117
5118         rtl8169_init_phy(dev, tp);
5119
5120         __rtl8169_resume(dev);
5121
5122         return 0;
5123 }
5124
5125 static int rtl8169_runtime_idle(struct device *device)
5126 {
5127         struct pci_dev *pdev = to_pci_dev(device);
5128         struct net_device *dev = pci_get_drvdata(pdev);
5129         struct rtl8169_private *tp = netdev_priv(dev);
5130
5131         return tp->TxDescArray ? -EBUSY : 0;
5132 }
5133
5134 static const struct dev_pm_ops rtl8169_pm_ops = {
5135         .suspend = rtl8169_suspend,
5136         .resume = rtl8169_resume,
5137         .freeze = rtl8169_suspend,
5138         .thaw = rtl8169_resume,
5139         .poweroff = rtl8169_suspend,
5140         .restore = rtl8169_resume,
5141         .runtime_suspend = rtl8169_runtime_suspend,
5142         .runtime_resume = rtl8169_runtime_resume,
5143         .runtime_idle = rtl8169_runtime_idle,
5144 };
5145
5146 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5147
5148 #else /* !CONFIG_PM */
5149
5150 #define RTL8169_PM_OPS  NULL
5151
5152 #endif /* !CONFIG_PM */
5153
5154 static void rtl_shutdown(struct pci_dev *pdev)
5155 {
5156         struct net_device *dev = pci_get_drvdata(pdev);
5157         struct rtl8169_private *tp = netdev_priv(dev);
5158         void __iomem *ioaddr = tp->mmio_addr;
5159
5160         rtl8169_net_suspend(dev);
5161
5162         /* restore original MAC address */
5163         rtl_rar_set(tp, dev->perm_addr);
5164
5165         spin_lock_irq(&tp->lock);
5166
5167         rtl8169_asic_down(ioaddr);
5168
5169         spin_unlock_irq(&tp->lock);
5170
5171         if (system_state == SYSTEM_POWER_OFF) {
5172                 /* WoL fails with some 8168 when the receiver is disabled. */
5173                 if (tp->features & RTL_FEATURE_WOL) {
5174                         pci_clear_master(pdev);
5175
5176                         RTL_W8(ChipCmd, CmdRxEnb);
5177                         /* PCI commit */
5178                         RTL_R8(ChipCmd);
5179                 }
5180
5181                 pci_wake_from_d3(pdev, true);
5182                 pci_set_power_state(pdev, PCI_D3hot);
5183         }
5184 }
5185
5186 static struct pci_driver rtl8169_pci_driver = {
5187         .name           = MODULENAME,
5188         .id_table       = rtl8169_pci_tbl,
5189         .probe          = rtl8169_init_one,
5190         .remove         = __devexit_p(rtl8169_remove_one),
5191         .shutdown       = rtl_shutdown,
5192         .driver.pm      = RTL8169_PM_OPS,
5193 };
5194
5195 static int __init rtl8169_init_module(void)
5196 {
5197         return pci_register_driver(&rtl8169_pci_driver);
5198 }
5199
5200 static void __exit rtl8169_cleanup_module(void)
5201 {
5202         pci_unregister_driver(&rtl8169_pci_driver);
5203 }
5204
5205 module_init(rtl8169_init_module);
5206 module_exit(rtl8169_cleanup_module);