2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
29 #include <asm/system.h>
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define assert(expr) \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
127 #define _R(NAME,MAC,MASK) \
128 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130 static const struct {
133 u32 RxConfigMask; /* Clears the bits supported by this chip */
134 } rtl_chip_info[] = {
135 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
136 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
137 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
138 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
141 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
142 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
151 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
159 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
161 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
171 static void rtl_hw_start_8169(struct net_device *);
172 static void rtl_hw_start_8168(struct net_device *);
173 static void rtl_hw_start_8101(struct net_device *);
175 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
182 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
184 { PCI_VENDOR_ID_LINKSYS, 0x1032,
185 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
187 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
191 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
193 static int rx_buf_sz = 16383;
200 MAC0 = 0, /* Ethernet hardware address. */
202 MAR0 = 8, /* Multicast filter. */
203 CounterAddrLow = 0x10,
204 CounterAddrHigh = 0x14,
205 TxDescStartAddrLow = 0x20,
206 TxDescStartAddrHigh = 0x24,
207 TxHDescStartAddrLow = 0x28,
208 TxHDescStartAddrHigh = 0x2c,
231 RxDescAddrLow = 0xe4,
232 RxDescAddrHigh = 0xe8,
233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
235 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
239 #define TxPacketMax (8064 >> 7)
242 FuncEventMask = 0xf4,
243 FuncPresetState = 0xf8,
244 FuncForceEvent = 0xfc,
247 enum rtl8110_registers {
253 enum rtl8168_8101_registers {
256 #define CSIAR_FLAG 0x80000000
257 #define CSIAR_WRITE_CMD 0x80000000
258 #define CSIAR_BYTE_ENABLE 0x0f
259 #define CSIAR_BYTE_ENABLE_SHIFT 12
260 #define CSIAR_ADDR_MASK 0x0fff
263 #define EPHYAR_FLAG 0x80000000
264 #define EPHYAR_WRITE_CMD 0x80000000
265 #define EPHYAR_REG_MASK 0x1f
266 #define EPHYAR_REG_SHIFT 16
267 #define EPHYAR_DATA_MASK 0xffff
269 #define FIX_NAK_1 (1 << 4)
270 #define FIX_NAK_2 (1 << 3)
272 #define EFUSEAR_FLAG 0x80000000
273 #define EFUSEAR_WRITE_CMD 0x80000000
274 #define EFUSEAR_READ_CMD 0x00000000
275 #define EFUSEAR_REG_MASK 0x03ff
276 #define EFUSEAR_REG_SHIFT 8
277 #define EFUSEAR_DATA_MASK 0xff
280 enum rtl8168_registers {
281 EPHY_RXER_NUM = 0x7c,
282 OCPDR = 0xb0, /* OCP GPHY access */
283 #define OCPDR_WRITE_CMD 0x80000000
284 #define OCPDR_READ_CMD 0x00000000
285 #define OCPDR_REG_MASK 0x7f
286 #define OCPDR_GPHY_REG_SHIFT 16
287 #define OCPDR_DATA_MASK 0xffff
289 #define OCPAR_FLAG 0x80000000
290 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
291 #define OCPAR_GPHY_READ_CMD 0x0000f060
294 enum rtl_register_content {
295 /* InterruptStatusBits */
299 TxDescUnavail = 0x0080,
321 /* TXPoll register p.5 */
322 HPQ = 0x80, /* Poll cmd on the high prio queue */
323 NPQ = 0x40, /* Poll cmd on the low prio queue */
324 FSWInt = 0x01, /* Forced software interrupt */
328 Cfg9346_Unlock = 0xc0,
333 AcceptBroadcast = 0x08,
334 AcceptMulticast = 0x04,
336 AcceptAllPhys = 0x01,
343 TxInterFrameGapShift = 24,
344 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
346 /* Config1 register p.24 */
349 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
350 Speed_down = (1 << 4),
354 PMEnable = (1 << 0), /* Power Management Enable */
356 /* Config2 register p. 25 */
357 PCI_Clock_66MHz = 0x01,
358 PCI_Clock_33MHz = 0x00,
360 /* Config3 register p.25 */
361 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
362 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
363 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
365 /* Config5 register p.27 */
366 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
367 MWF = (1 << 5), /* Accept Multicast wakeup frame */
368 UWF = (1 << 4), /* Accept Unicast wakeup frame */
369 LanWake = (1 << 1), /* LanWake enable/disable */
370 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
373 TBIReset = 0x80000000,
374 TBILoopback = 0x40000000,
375 TBINwEnable = 0x20000000,
376 TBINwRestart = 0x10000000,
377 TBILinkOk = 0x02000000,
378 TBINwComplete = 0x01000000,
381 EnableBist = (1 << 15), // 8168 8101
382 Mac_dbgo_oe = (1 << 14), // 8168 8101
383 Normal_mode = (1 << 13), // unused
384 Force_half_dup = (1 << 12), // 8168 8101
385 Force_rxflow_en = (1 << 11), // 8168 8101
386 Force_txflow_en = (1 << 10), // 8168 8101
387 Cxpl_dbg_sel = (1 << 9), // 8168 8101
388 ASF = (1 << 8), // 8168 8101
389 PktCntrDisable = (1 << 7), // 8168 8101
390 Mac_dbgo_sel = 0x001c, // 8168
395 INTT_0 = 0x0000, // 8168
396 INTT_1 = 0x0001, // 8168
397 INTT_2 = 0x0002, // 8168
398 INTT_3 = 0x0003, // 8168
400 /* rtl8169_PHYstatus */
411 TBILinkOK = 0x02000000,
413 /* DumpCounterCommand */
417 enum desc_status_bit {
418 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
419 RingEnd = (1 << 30), /* End of descriptor ring */
420 FirstFrag = (1 << 29), /* First segment of a packet */
421 LastFrag = (1 << 28), /* Final segment of a packet */
424 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
425 MSSShift = 16, /* MSS value position */
426 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
427 IPCS = (1 << 18), /* Calculate IP checksum */
428 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
429 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
430 TxVlanTag = (1 << 17), /* Add VLAN tag */
433 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
434 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
436 #define RxProtoUDP (PID1)
437 #define RxProtoTCP (PID0)
438 #define RxProtoIP (PID1 | PID0)
439 #define RxProtoMask RxProtoIP
441 IPFail = (1 << 16), /* IP checksum failed */
442 UDPFail = (1 << 15), /* UDP/IP checksum failed */
443 TCPFail = (1 << 14), /* TCP/IP checksum failed */
444 RxVlanTag = (1 << 16), /* VLAN tag available */
447 #define RsvdMask 0x3fffc000
464 u8 __pad[sizeof(void *) - sizeof(u32)];
468 RTL_FEATURE_WOL = (1 << 0),
469 RTL_FEATURE_MSI = (1 << 1),
470 RTL_FEATURE_GMII = (1 << 2),
473 struct rtl8169_counters {
480 __le32 tx_one_collision;
481 __le32 tx_multi_collision;
489 struct rtl8169_private {
490 void __iomem *mmio_addr; /* memory map physical address */
491 struct pci_dev *pci_dev; /* Index of PCI device */
492 struct net_device *dev;
493 struct napi_struct napi;
494 spinlock_t lock; /* spin lock flag */
498 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
499 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
502 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
503 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
504 dma_addr_t TxPhyAddr;
505 dma_addr_t RxPhyAddr;
506 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
507 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
508 struct timer_list timer;
513 int phy_1000_ctrl_reg;
514 #ifdef CONFIG_R8169_VLAN
515 struct vlan_group *vlgrp;
519 void (*write)(void __iomem *, int, int);
520 int (*read)(void __iomem *, int);
523 struct pll_power_ops {
524 void (*down)(struct rtl8169_private *);
525 void (*up)(struct rtl8169_private *);
528 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
529 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
530 void (*phy_reset_enable)(struct rtl8169_private *tp);
531 void (*hw_start)(struct net_device *);
532 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
533 unsigned int (*link_ok)(void __iomem *);
534 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
536 struct delayed_work task;
539 struct mii_if_info mii;
540 struct rtl8169_counters counters;
544 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
545 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
546 module_param(use_dac, int, 0);
547 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
548 module_param_named(debug, debug.msg_enable, int, 0);
549 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
550 MODULE_LICENSE("GPL");
551 MODULE_VERSION(RTL8169_VERSION);
552 MODULE_FIRMWARE(FIRMWARE_8168D_1);
553 MODULE_FIRMWARE(FIRMWARE_8168D_2);
555 static int rtl8169_open(struct net_device *dev);
556 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
557 struct net_device *dev);
558 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
559 static int rtl8169_init_ring(struct net_device *dev);
560 static void rtl_hw_start(struct net_device *dev);
561 static int rtl8169_close(struct net_device *dev);
562 static void rtl_set_rx_mode(struct net_device *dev);
563 static void rtl8169_tx_timeout(struct net_device *dev);
564 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
565 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
566 void __iomem *, u32 budget);
567 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
568 static void rtl8169_down(struct net_device *dev);
569 static void rtl8169_rx_clear(struct rtl8169_private *tp);
570 static int rtl8169_poll(struct napi_struct *napi, int budget);
572 static const unsigned int rtl8169_rx_config =
573 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
575 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
579 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
581 for (i = 20; i > 0; i--) {
583 * Check if the RTL8169 has completed writing to the specified
586 if (!(RTL_R32(PHYAR) & 0x80000000))
591 * According to hardware specs a 20us delay is required after write
592 * complete indication, but before sending next command.
597 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
601 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
603 for (i = 20; i > 0; i--) {
605 * Check if the RTL8169 has completed retrieving data from
606 * the specified MII register.
608 if (RTL_R32(PHYAR) & 0x80000000) {
609 value = RTL_R32(PHYAR) & 0xffff;
615 * According to hardware specs a 20us delay is required after read
616 * complete indication, but before sending next command.
623 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
627 RTL_W32(OCPDR, data |
628 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
629 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
630 RTL_W32(EPHY_RXER_NUM, 0);
632 for (i = 0; i < 100; i++) {
634 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
639 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
641 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
642 (value & OCPDR_DATA_MASK));
645 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
649 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
652 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
653 RTL_W32(EPHY_RXER_NUM, 0);
655 for (i = 0; i < 100; i++) {
657 if (RTL_R32(OCPAR) & OCPAR_FLAG)
661 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
664 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
666 tp->mdio_ops.write(tp->mmio_addr, location, val);
669 static int rtl_readphy(struct rtl8169_private *tp, int location)
671 return tp->mdio_ops.read(tp->mmio_addr, location);
674 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
676 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
679 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
683 val = rtl_readphy(tp, reg_addr);
684 rtl_writephy(tp, reg_addr, (val | p) & ~m);
687 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
690 struct rtl8169_private *tp = netdev_priv(dev);
692 rtl_writephy(tp, location, val);
695 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
697 struct rtl8169_private *tp = netdev_priv(dev);
699 return rtl_readphy(tp, location);
702 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
706 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
707 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
709 for (i = 0; i < 100; i++) {
710 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
716 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
721 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
723 for (i = 0; i < 100; i++) {
724 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
725 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
734 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
738 RTL_W32(CSIDR, value);
739 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
740 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
742 for (i = 0; i < 100; i++) {
743 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
749 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
754 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
755 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
757 for (i = 0; i < 100; i++) {
758 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
759 value = RTL_R32(CSIDR);
768 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
773 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
775 for (i = 0; i < 300; i++) {
776 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
777 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
786 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
788 RTL_W16(IntrMask, 0x0000);
790 RTL_W16(IntrStatus, 0xffff);
793 static void rtl8169_asic_down(void __iomem *ioaddr)
795 RTL_W8(ChipCmd, 0x00);
796 rtl8169_irq_mask_and_ack(ioaddr);
800 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
802 void __iomem *ioaddr = tp->mmio_addr;
804 return RTL_R32(TBICSR) & TBIReset;
807 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
809 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
812 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
814 return RTL_R32(TBICSR) & TBILinkOk;
817 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
819 return RTL_R8(PHYstatus) & LinkStatus;
822 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
824 void __iomem *ioaddr = tp->mmio_addr;
826 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
829 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
833 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
834 rtl_writephy(tp, MII_BMCR, val & 0xffff);
837 static void __rtl8169_check_link_status(struct net_device *dev,
838 struct rtl8169_private *tp,
839 void __iomem *ioaddr,
844 spin_lock_irqsave(&tp->lock, flags);
845 if (tp->link_ok(ioaddr)) {
846 /* This is to cancel a scheduled suspend if there's one. */
848 pm_request_resume(&tp->pci_dev->dev);
849 netif_carrier_on(dev);
850 netif_info(tp, ifup, dev, "link up\n");
852 netif_carrier_off(dev);
853 netif_info(tp, ifdown, dev, "link down\n");
855 pm_schedule_suspend(&tp->pci_dev->dev, 100);
857 spin_unlock_irqrestore(&tp->lock, flags);
860 static void rtl8169_check_link_status(struct net_device *dev,
861 struct rtl8169_private *tp,
862 void __iomem *ioaddr)
864 __rtl8169_check_link_status(dev, tp, ioaddr, false);
867 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
869 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
871 void __iomem *ioaddr = tp->mmio_addr;
875 options = RTL_R8(Config1);
876 if (!(options & PMEnable))
879 options = RTL_R8(Config3);
880 if (options & LinkUp)
882 if (options & MagicPacket)
883 wolopts |= WAKE_MAGIC;
885 options = RTL_R8(Config5);
887 wolopts |= WAKE_UCAST;
889 wolopts |= WAKE_BCAST;
891 wolopts |= WAKE_MCAST;
896 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
898 struct rtl8169_private *tp = netdev_priv(dev);
900 spin_lock_irq(&tp->lock);
902 wol->supported = WAKE_ANY;
903 wol->wolopts = __rtl8169_get_wol(tp);
905 spin_unlock_irq(&tp->lock);
908 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
910 void __iomem *ioaddr = tp->mmio_addr;
912 static const struct {
917 { WAKE_ANY, Config1, PMEnable },
918 { WAKE_PHY, Config3, LinkUp },
919 { WAKE_MAGIC, Config3, MagicPacket },
920 { WAKE_UCAST, Config5, UWF },
921 { WAKE_BCAST, Config5, BWF },
922 { WAKE_MCAST, Config5, MWF },
923 { WAKE_ANY, Config5, LanWake }
926 RTL_W8(Cfg9346, Cfg9346_Unlock);
928 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
929 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
930 if (wolopts & cfg[i].opt)
931 options |= cfg[i].mask;
932 RTL_W8(cfg[i].reg, options);
935 RTL_W8(Cfg9346, Cfg9346_Lock);
938 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
940 struct rtl8169_private *tp = netdev_priv(dev);
942 spin_lock_irq(&tp->lock);
945 tp->features |= RTL_FEATURE_WOL;
947 tp->features &= ~RTL_FEATURE_WOL;
948 __rtl8169_set_wol(tp, wol->wolopts);
949 spin_unlock_irq(&tp->lock);
951 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
956 static void rtl8169_get_drvinfo(struct net_device *dev,
957 struct ethtool_drvinfo *info)
959 struct rtl8169_private *tp = netdev_priv(dev);
961 strcpy(info->driver, MODULENAME);
962 strcpy(info->version, RTL8169_VERSION);
963 strcpy(info->bus_info, pci_name(tp->pci_dev));
966 static int rtl8169_get_regs_len(struct net_device *dev)
968 return R8169_REGS_SIZE;
971 static int rtl8169_set_speed_tbi(struct net_device *dev,
972 u8 autoneg, u16 speed, u8 duplex)
974 struct rtl8169_private *tp = netdev_priv(dev);
975 void __iomem *ioaddr = tp->mmio_addr;
979 reg = RTL_R32(TBICSR);
980 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
981 (duplex == DUPLEX_FULL)) {
982 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
983 } else if (autoneg == AUTONEG_ENABLE)
984 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
986 netif_warn(tp, link, dev,
987 "incorrect speed setting refused in TBI mode\n");
994 static int rtl8169_set_speed_xmii(struct net_device *dev,
995 u8 autoneg, u16 speed, u8 duplex)
997 struct rtl8169_private *tp = netdev_priv(dev);
1000 if (autoneg == AUTONEG_ENABLE) {
1003 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1004 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1005 ADVERTISE_100HALF | ADVERTISE_100FULL);
1006 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1008 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1009 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1011 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1012 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1013 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1014 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1015 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1016 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1017 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1018 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1019 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1020 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1022 netif_info(tp, link, dev,
1023 "PHY does not support 1000Mbps\n");
1026 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1028 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1029 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1030 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1033 * Vendor specific (0x1f) and reserved (0x0e) MII
1036 rtl_writephy(tp, 0x1f, 0x0000);
1037 rtl_writephy(tp, 0x0e, 0x0000);
1040 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1041 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1045 if (speed == SPEED_10)
1047 else if (speed == SPEED_100)
1048 bmcr = BMCR_SPEED100;
1052 if (duplex == DUPLEX_FULL)
1053 bmcr |= BMCR_FULLDPLX;
1055 rtl_writephy(tp, 0x1f, 0x0000);
1058 tp->phy_1000_ctrl_reg = giga_ctrl;
1060 rtl_writephy(tp, MII_BMCR, bmcr);
1062 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1063 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1064 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1065 rtl_writephy(tp, 0x17, 0x2138);
1066 rtl_writephy(tp, 0x0e, 0x0260);
1068 rtl_writephy(tp, 0x17, 0x2108);
1069 rtl_writephy(tp, 0x0e, 0x0000);
1076 static int rtl8169_set_speed(struct net_device *dev,
1077 u8 autoneg, u16 speed, u8 duplex)
1079 struct rtl8169_private *tp = netdev_priv(dev);
1082 ret = tp->set_speed(dev, autoneg, speed, duplex);
1084 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1085 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1090 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1092 struct rtl8169_private *tp = netdev_priv(dev);
1093 unsigned long flags;
1096 spin_lock_irqsave(&tp->lock, flags);
1097 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1098 spin_unlock_irqrestore(&tp->lock, flags);
1103 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1105 struct rtl8169_private *tp = netdev_priv(dev);
1107 return tp->cp_cmd & RxChkSum;
1110 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1112 struct rtl8169_private *tp = netdev_priv(dev);
1113 void __iomem *ioaddr = tp->mmio_addr;
1114 unsigned long flags;
1116 spin_lock_irqsave(&tp->lock, flags);
1119 tp->cp_cmd |= RxChkSum;
1121 tp->cp_cmd &= ~RxChkSum;
1123 RTL_W16(CPlusCmd, tp->cp_cmd);
1126 spin_unlock_irqrestore(&tp->lock, flags);
1131 #ifdef CONFIG_R8169_VLAN
1133 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1134 struct sk_buff *skb)
1136 return (vlan_tx_tag_present(skb)) ?
1137 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1140 static void rtl8169_vlan_rx_register(struct net_device *dev,
1141 struct vlan_group *grp)
1143 struct rtl8169_private *tp = netdev_priv(dev);
1144 void __iomem *ioaddr = tp->mmio_addr;
1145 unsigned long flags;
1147 spin_lock_irqsave(&tp->lock, flags);
1150 * Do not disable RxVlan on 8110SCd.
1152 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1153 tp->cp_cmd |= RxVlan;
1155 tp->cp_cmd &= ~RxVlan;
1156 RTL_W16(CPlusCmd, tp->cp_cmd);
1158 spin_unlock_irqrestore(&tp->lock, flags);
1161 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1162 struct sk_buff *skb, int polling)
1164 u32 opts2 = le32_to_cpu(desc->opts2);
1165 struct vlan_group *vlgrp = tp->vlgrp;
1168 if (vlgrp && (opts2 & RxVlanTag)) {
1169 u16 vtag = swab16(opts2 & 0xffff);
1171 if (likely(polling))
1172 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1174 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1182 #else /* !CONFIG_R8169_VLAN */
1184 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1185 struct sk_buff *skb)
1190 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1191 struct sk_buff *skb, int polling)
1198 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1200 struct rtl8169_private *tp = netdev_priv(dev);
1201 void __iomem *ioaddr = tp->mmio_addr;
1205 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1206 cmd->port = PORT_FIBRE;
1207 cmd->transceiver = XCVR_INTERNAL;
1209 status = RTL_R32(TBICSR);
1210 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1211 cmd->autoneg = !!(status & TBINwEnable);
1213 cmd->speed = SPEED_1000;
1214 cmd->duplex = DUPLEX_FULL; /* Always set */
1219 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1221 struct rtl8169_private *tp = netdev_priv(dev);
1223 return mii_ethtool_gset(&tp->mii, cmd);
1226 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1228 struct rtl8169_private *tp = netdev_priv(dev);
1229 unsigned long flags;
1232 spin_lock_irqsave(&tp->lock, flags);
1234 rc = tp->get_settings(dev, cmd);
1236 spin_unlock_irqrestore(&tp->lock, flags);
1240 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1243 struct rtl8169_private *tp = netdev_priv(dev);
1244 unsigned long flags;
1246 if (regs->len > R8169_REGS_SIZE)
1247 regs->len = R8169_REGS_SIZE;
1249 spin_lock_irqsave(&tp->lock, flags);
1250 memcpy_fromio(p, tp->mmio_addr, regs->len);
1251 spin_unlock_irqrestore(&tp->lock, flags);
1254 static u32 rtl8169_get_msglevel(struct net_device *dev)
1256 struct rtl8169_private *tp = netdev_priv(dev);
1258 return tp->msg_enable;
1261 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1263 struct rtl8169_private *tp = netdev_priv(dev);
1265 tp->msg_enable = value;
1268 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1275 "tx_single_collisions",
1276 "tx_multi_collisions",
1284 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1288 return ARRAY_SIZE(rtl8169_gstrings);
1294 static void rtl8169_update_counters(struct net_device *dev)
1296 struct rtl8169_private *tp = netdev_priv(dev);
1297 void __iomem *ioaddr = tp->mmio_addr;
1298 struct rtl8169_counters *counters;
1302 struct device *d = &tp->pci_dev->dev;
1305 * Some chips are unable to dump tally counters when the receiver
1308 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1311 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1315 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1316 cmd = (u64)paddr & DMA_BIT_MASK(32);
1317 RTL_W32(CounterAddrLow, cmd);
1318 RTL_W32(CounterAddrLow, cmd | CounterDump);
1321 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1322 /* copy updated counters */
1323 memcpy(&tp->counters, counters, sizeof(*counters));
1329 RTL_W32(CounterAddrLow, 0);
1330 RTL_W32(CounterAddrHigh, 0);
1332 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1335 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1336 struct ethtool_stats *stats, u64 *data)
1338 struct rtl8169_private *tp = netdev_priv(dev);
1342 rtl8169_update_counters(dev);
1344 data[0] = le64_to_cpu(tp->counters.tx_packets);
1345 data[1] = le64_to_cpu(tp->counters.rx_packets);
1346 data[2] = le64_to_cpu(tp->counters.tx_errors);
1347 data[3] = le32_to_cpu(tp->counters.rx_errors);
1348 data[4] = le16_to_cpu(tp->counters.rx_missed);
1349 data[5] = le16_to_cpu(tp->counters.align_errors);
1350 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1351 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1352 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1353 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1354 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1355 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1356 data[12] = le16_to_cpu(tp->counters.tx_underun);
1359 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1363 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1368 static const struct ethtool_ops rtl8169_ethtool_ops = {
1369 .get_drvinfo = rtl8169_get_drvinfo,
1370 .get_regs_len = rtl8169_get_regs_len,
1371 .get_link = ethtool_op_get_link,
1372 .get_settings = rtl8169_get_settings,
1373 .set_settings = rtl8169_set_settings,
1374 .get_msglevel = rtl8169_get_msglevel,
1375 .set_msglevel = rtl8169_set_msglevel,
1376 .get_rx_csum = rtl8169_get_rx_csum,
1377 .set_rx_csum = rtl8169_set_rx_csum,
1378 .set_tx_csum = ethtool_op_set_tx_csum,
1379 .set_sg = ethtool_op_set_sg,
1380 .set_tso = ethtool_op_set_tso,
1381 .get_regs = rtl8169_get_regs,
1382 .get_wol = rtl8169_get_wol,
1383 .set_wol = rtl8169_set_wol,
1384 .get_strings = rtl8169_get_strings,
1385 .get_sset_count = rtl8169_get_sset_count,
1386 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1389 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1390 void __iomem *ioaddr)
1393 * The driver currently handles the 8168Bf and the 8168Be identically
1394 * but they can be identified more specifically through the test below
1397 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1399 * Same thing for the 8101Eb and the 8101Ec:
1401 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1403 static const struct {
1409 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1410 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1411 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1412 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1415 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1416 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1417 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1418 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1419 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1420 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1421 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1422 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1423 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1426 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1427 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1428 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1429 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1432 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1433 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1434 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1435 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1436 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1437 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1438 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1439 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1440 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1441 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1442 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1443 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1444 /* FIXME: where did these entries come from ? -- FR */
1445 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1446 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1449 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1450 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1451 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1452 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1453 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1454 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1457 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1461 reg = RTL_R32(TxConfig);
1462 while ((reg & p->mask) != p->val)
1464 tp->mac_version = p->mac_version;
1467 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1469 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1477 static void rtl_writephy_batch(struct rtl8169_private *tp,
1478 const struct phy_reg *regs, int len)
1481 rtl_writephy(tp, regs->reg, regs->val);
1486 #define PHY_READ 0x00000000
1487 #define PHY_DATA_OR 0x10000000
1488 #define PHY_DATA_AND 0x20000000
1489 #define PHY_BJMPN 0x30000000
1490 #define PHY_READ_EFUSE 0x40000000
1491 #define PHY_READ_MAC_BYTE 0x50000000
1492 #define PHY_WRITE_MAC_BYTE 0x60000000
1493 #define PHY_CLEAR_READCOUNT 0x70000000
1494 #define PHY_WRITE 0x80000000
1495 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1496 #define PHY_COMP_EQ_SKIPN 0xa0000000
1497 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1498 #define PHY_WRITE_PREVIOUS 0xc0000000
1499 #define PHY_SKIPN 0xd0000000
1500 #define PHY_DELAY_MS 0xe0000000
1501 #define PHY_WRITE_ERI_WORD 0xf0000000
1504 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1506 __le32 *phytable = (__le32 *)fw->data;
1507 struct net_device *dev = tp->dev;
1510 if (fw->size % sizeof(*phytable)) {
1511 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1515 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1516 u32 action = le32_to_cpu(phytable[i]);
1521 if ((action & 0xf0000000) != PHY_WRITE) {
1522 netif_err(tp, probe, dev,
1523 "unknown action 0x%08x\n", action);
1529 u32 action = le32_to_cpu(*phytable);
1530 u32 data = action & 0x0000ffff;
1531 u32 reg = (action & 0x0fff0000) >> 16;
1533 switch(action & 0xf0000000) {
1535 rtl_writephy(tp, reg, data);
1544 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1546 static const struct phy_reg phy_reg_init[] = {
1608 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1611 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1613 static const struct phy_reg phy_reg_init[] = {
1619 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1622 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1624 struct pci_dev *pdev = tp->pci_dev;
1625 u16 vendor_id, device_id;
1627 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1628 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1630 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1633 rtl_writephy(tp, 0x1f, 0x0001);
1634 rtl_writephy(tp, 0x10, 0xf01b);
1635 rtl_writephy(tp, 0x1f, 0x0000);
1638 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1640 static const struct phy_reg phy_reg_init[] = {
1680 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1682 rtl8169scd_hw_phy_config_quirk(tp);
1685 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1687 static const struct phy_reg phy_reg_init[] = {
1735 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1738 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1740 static const struct phy_reg phy_reg_init[] = {
1745 rtl_writephy(tp, 0x1f, 0x0001);
1746 rtl_patchphy(tp, 0x16, 1 << 0);
1748 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1751 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1753 static const struct phy_reg phy_reg_init[] = {
1759 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1762 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
1764 static const struct phy_reg phy_reg_init[] = {
1772 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1775 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
1777 static const struct phy_reg phy_reg_init[] = {
1783 rtl_writephy(tp, 0x1f, 0x0000);
1784 rtl_patchphy(tp, 0x14, 1 << 5);
1785 rtl_patchphy(tp, 0x0d, 1 << 5);
1787 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1790 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
1792 static const struct phy_reg phy_reg_init[] = {
1812 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1814 rtl_patchphy(tp, 0x14, 1 << 5);
1815 rtl_patchphy(tp, 0x0d, 1 << 5);
1816 rtl_writephy(tp, 0x1f, 0x0000);
1819 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
1821 static const struct phy_reg phy_reg_init[] = {
1839 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1841 rtl_patchphy(tp, 0x16, 1 << 0);
1842 rtl_patchphy(tp, 0x14, 1 << 5);
1843 rtl_patchphy(tp, 0x0d, 1 << 5);
1844 rtl_writephy(tp, 0x1f, 0x0000);
1847 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
1849 static const struct phy_reg phy_reg_init[] = {
1861 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1863 rtl_patchphy(tp, 0x16, 1 << 0);
1864 rtl_patchphy(tp, 0x14, 1 << 5);
1865 rtl_patchphy(tp, 0x0d, 1 << 5);
1866 rtl_writephy(tp, 0x1f, 0x0000);
1869 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
1871 rtl8168c_3_hw_phy_config(tp);
1874 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
1876 static const struct phy_reg phy_reg_init_0[] = {
1877 /* Channel Estimation */
1898 * enhance line driver power
1907 * Can not link to 1Gbps with bad cable
1908 * Decrease SNR threshold form 21.07dB to 19.04dB
1916 void __iomem *ioaddr = tp->mmio_addr;
1917 const struct firmware *fw;
1919 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1923 * Fine Tune Switching regulator parameter
1925 rtl_writephy(tp, 0x1f, 0x0002);
1926 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
1927 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
1929 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
1930 static const struct phy_reg phy_reg_init[] = {
1940 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1942 val = rtl_readphy(tp, 0x0d);
1944 if ((val & 0x00ff) != 0x006c) {
1945 static const u32 set[] = {
1946 0x0065, 0x0066, 0x0067, 0x0068,
1947 0x0069, 0x006a, 0x006b, 0x006c
1951 rtl_writephy(tp, 0x1f, 0x0002);
1954 for (i = 0; i < ARRAY_SIZE(set); i++)
1955 rtl_writephy(tp, 0x0d, val | set[i]);
1958 static const struct phy_reg phy_reg_init[] = {
1966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1969 /* RSET couple improve */
1970 rtl_writephy(tp, 0x1f, 0x0002);
1971 rtl_patchphy(tp, 0x0d, 0x0300);
1972 rtl_patchphy(tp, 0x0f, 0x0010);
1974 /* Fine tune PLL performance */
1975 rtl_writephy(tp, 0x1f, 0x0002);
1976 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
1977 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
1979 rtl_writephy(tp, 0x1f, 0x0005);
1980 rtl_writephy(tp, 0x05, 0x001b);
1981 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
1982 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
1983 rtl_phy_write_fw(tp, fw);
1984 release_firmware(fw);
1986 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
1989 rtl_writephy(tp, 0x1f, 0x0000);
1992 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
1994 static const struct phy_reg phy_reg_init_0[] = {
1995 /* Channel Estimation */
2016 * enhance line driver power
2025 * Can not link to 1Gbps with bad cable
2026 * Decrease SNR threshold form 21.07dB to 19.04dB
2034 void __iomem *ioaddr = tp->mmio_addr;
2035 const struct firmware *fw;
2037 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2039 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2040 static const struct phy_reg phy_reg_init[] = {
2051 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2053 val = rtl_readphy(tp, 0x0d);
2054 if ((val & 0x00ff) != 0x006c) {
2055 static const u32 set[] = {
2056 0x0065, 0x0066, 0x0067, 0x0068,
2057 0x0069, 0x006a, 0x006b, 0x006c
2061 rtl_writephy(tp, 0x1f, 0x0002);
2064 for (i = 0; i < ARRAY_SIZE(set); i++)
2065 rtl_writephy(tp, 0x0d, val | set[i]);
2068 static const struct phy_reg phy_reg_init[] = {
2076 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2079 /* Fine tune PLL performance */
2080 rtl_writephy(tp, 0x1f, 0x0002);
2081 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2082 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2084 /* Switching regulator Slew rate */
2085 rtl_writephy(tp, 0x1f, 0x0002);
2086 rtl_patchphy(tp, 0x0f, 0x0017);
2088 rtl_writephy(tp, 0x1f, 0x0005);
2089 rtl_writephy(tp, 0x05, 0x001b);
2090 if (rtl_readphy(tp, 0x06) == 0xb300 &&
2091 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2092 rtl_phy_write_fw(tp, fw);
2093 release_firmware(fw);
2095 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2098 rtl_writephy(tp, 0x1f, 0x0000);
2101 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2103 static const struct phy_reg phy_reg_init[] = {
2159 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2162 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2164 static const struct phy_reg phy_reg_init[] = {
2171 rtl_writephy(tp, 0x1f, 0x0000);
2172 rtl_patchphy(tp, 0x11, 1 << 12);
2173 rtl_patchphy(tp, 0x19, 1 << 13);
2174 rtl_patchphy(tp, 0x10, 1 << 15);
2176 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2179 static void rtl_hw_phy_config(struct net_device *dev)
2181 struct rtl8169_private *tp = netdev_priv(dev);
2183 rtl8169_print_mac_version(tp);
2185 switch (tp->mac_version) {
2186 case RTL_GIGA_MAC_VER_01:
2188 case RTL_GIGA_MAC_VER_02:
2189 case RTL_GIGA_MAC_VER_03:
2190 rtl8169s_hw_phy_config(tp);
2192 case RTL_GIGA_MAC_VER_04:
2193 rtl8169sb_hw_phy_config(tp);
2195 case RTL_GIGA_MAC_VER_05:
2196 rtl8169scd_hw_phy_config(tp);
2198 case RTL_GIGA_MAC_VER_06:
2199 rtl8169sce_hw_phy_config(tp);
2201 case RTL_GIGA_MAC_VER_07:
2202 case RTL_GIGA_MAC_VER_08:
2203 case RTL_GIGA_MAC_VER_09:
2204 rtl8102e_hw_phy_config(tp);
2206 case RTL_GIGA_MAC_VER_11:
2207 rtl8168bb_hw_phy_config(tp);
2209 case RTL_GIGA_MAC_VER_12:
2210 rtl8168bef_hw_phy_config(tp);
2212 case RTL_GIGA_MAC_VER_17:
2213 rtl8168bef_hw_phy_config(tp);
2215 case RTL_GIGA_MAC_VER_18:
2216 rtl8168cp_1_hw_phy_config(tp);
2218 case RTL_GIGA_MAC_VER_19:
2219 rtl8168c_1_hw_phy_config(tp);
2221 case RTL_GIGA_MAC_VER_20:
2222 rtl8168c_2_hw_phy_config(tp);
2224 case RTL_GIGA_MAC_VER_21:
2225 rtl8168c_3_hw_phy_config(tp);
2227 case RTL_GIGA_MAC_VER_22:
2228 rtl8168c_4_hw_phy_config(tp);
2230 case RTL_GIGA_MAC_VER_23:
2231 case RTL_GIGA_MAC_VER_24:
2232 rtl8168cp_2_hw_phy_config(tp);
2234 case RTL_GIGA_MAC_VER_25:
2235 rtl8168d_1_hw_phy_config(tp);
2237 case RTL_GIGA_MAC_VER_26:
2238 rtl8168d_2_hw_phy_config(tp);
2240 case RTL_GIGA_MAC_VER_27:
2241 rtl8168d_3_hw_phy_config(tp);
2249 static void rtl8169_phy_timer(unsigned long __opaque)
2251 struct net_device *dev = (struct net_device *)__opaque;
2252 struct rtl8169_private *tp = netdev_priv(dev);
2253 struct timer_list *timer = &tp->timer;
2254 void __iomem *ioaddr = tp->mmio_addr;
2255 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2257 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2259 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2262 spin_lock_irq(&tp->lock);
2264 if (tp->phy_reset_pending(tp)) {
2266 * A busy loop could burn quite a few cycles on nowadays CPU.
2267 * Let's delay the execution of the timer for a few ticks.
2273 if (tp->link_ok(ioaddr))
2276 netif_warn(tp, link, dev, "PHY reset until link up\n");
2278 tp->phy_reset_enable(tp);
2281 mod_timer(timer, jiffies + timeout);
2283 spin_unlock_irq(&tp->lock);
2286 static inline void rtl8169_delete_timer(struct net_device *dev)
2288 struct rtl8169_private *tp = netdev_priv(dev);
2289 struct timer_list *timer = &tp->timer;
2291 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2294 del_timer_sync(timer);
2297 static inline void rtl8169_request_timer(struct net_device *dev)
2299 struct rtl8169_private *tp = netdev_priv(dev);
2300 struct timer_list *timer = &tp->timer;
2302 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2305 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2308 #ifdef CONFIG_NET_POLL_CONTROLLER
2310 * Polling 'interrupt' - used by things like netconsole to send skbs
2311 * without having to re-enable interrupts. It's not called while
2312 * the interrupt routine is executing.
2314 static void rtl8169_netpoll(struct net_device *dev)
2316 struct rtl8169_private *tp = netdev_priv(dev);
2317 struct pci_dev *pdev = tp->pci_dev;
2319 disable_irq(pdev->irq);
2320 rtl8169_interrupt(pdev->irq, dev);
2321 enable_irq(pdev->irq);
2325 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2326 void __iomem *ioaddr)
2329 pci_release_regions(pdev);
2330 pci_clear_mwi(pdev);
2331 pci_disable_device(pdev);
2335 static void rtl8169_phy_reset(struct net_device *dev,
2336 struct rtl8169_private *tp)
2340 tp->phy_reset_enable(tp);
2341 for (i = 0; i < 100; i++) {
2342 if (!tp->phy_reset_pending(tp))
2346 netif_err(tp, link, dev, "PHY reset failed\n");
2349 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2351 void __iomem *ioaddr = tp->mmio_addr;
2353 rtl_hw_phy_config(dev);
2355 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2356 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2360 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2362 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2363 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2365 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2366 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2368 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2369 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2372 rtl8169_phy_reset(dev, tp);
2375 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2376 * only 8101. Don't panic.
2378 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2380 if (RTL_R8(PHYstatus) & TBI_Enable)
2381 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2384 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2386 void __iomem *ioaddr = tp->mmio_addr;
2390 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2391 high = addr[4] | (addr[5] << 8);
2393 spin_lock_irq(&tp->lock);
2395 RTL_W8(Cfg9346, Cfg9346_Unlock);
2397 RTL_W32(MAC4, high);
2403 RTL_W8(Cfg9346, Cfg9346_Lock);
2405 spin_unlock_irq(&tp->lock);
2408 static int rtl_set_mac_address(struct net_device *dev, void *p)
2410 struct rtl8169_private *tp = netdev_priv(dev);
2411 struct sockaddr *addr = p;
2413 if (!is_valid_ether_addr(addr->sa_data))
2414 return -EADDRNOTAVAIL;
2416 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2418 rtl_rar_set(tp, dev->dev_addr);
2423 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2425 struct rtl8169_private *tp = netdev_priv(dev);
2426 struct mii_ioctl_data *data = if_mii(ifr);
2428 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2431 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2435 data->phy_id = 32; /* Internal PHY */
2439 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2443 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2449 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2454 static const struct rtl_cfg_info {
2455 void (*hw_start)(struct net_device *);
2456 unsigned int region;
2462 } rtl_cfg_infos [] = {
2464 .hw_start = rtl_hw_start_8169,
2467 .intr_event = SYSErr | LinkChg | RxOverflow |
2468 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2469 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2470 .features = RTL_FEATURE_GMII,
2471 .default_ver = RTL_GIGA_MAC_VER_01,
2474 .hw_start = rtl_hw_start_8168,
2477 .intr_event = SYSErr | LinkChg | RxOverflow |
2478 TxErr | TxOK | RxOK | RxErr,
2479 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2480 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2481 .default_ver = RTL_GIGA_MAC_VER_11,
2484 .hw_start = rtl_hw_start_8101,
2487 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2488 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2489 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2490 .features = RTL_FEATURE_MSI,
2491 .default_ver = RTL_GIGA_MAC_VER_13,
2495 /* Cfg9346_Unlock assumed. */
2496 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2497 const struct rtl_cfg_info *cfg)
2502 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2503 if (cfg->features & RTL_FEATURE_MSI) {
2504 if (pci_enable_msi(pdev)) {
2505 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2508 msi = RTL_FEATURE_MSI;
2511 RTL_W8(Config2, cfg2);
2515 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2517 if (tp->features & RTL_FEATURE_MSI) {
2518 pci_disable_msi(pdev);
2519 tp->features &= ~RTL_FEATURE_MSI;
2523 static const struct net_device_ops rtl8169_netdev_ops = {
2524 .ndo_open = rtl8169_open,
2525 .ndo_stop = rtl8169_close,
2526 .ndo_get_stats = rtl8169_get_stats,
2527 .ndo_start_xmit = rtl8169_start_xmit,
2528 .ndo_tx_timeout = rtl8169_tx_timeout,
2529 .ndo_validate_addr = eth_validate_addr,
2530 .ndo_change_mtu = rtl8169_change_mtu,
2531 .ndo_set_mac_address = rtl_set_mac_address,
2532 .ndo_do_ioctl = rtl8169_ioctl,
2533 .ndo_set_multicast_list = rtl_set_rx_mode,
2534 #ifdef CONFIG_R8169_VLAN
2535 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2537 #ifdef CONFIG_NET_POLL_CONTROLLER
2538 .ndo_poll_controller = rtl8169_netpoll,
2543 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2545 struct mdio_ops *ops = &tp->mdio_ops;
2547 switch (tp->mac_version) {
2548 case RTL_GIGA_MAC_VER_27:
2549 ops->write = r8168dp_1_mdio_write;
2550 ops->read = r8168dp_1_mdio_read;
2553 ops->write = r8169_mdio_write;
2554 ops->read = r8169_mdio_read;
2559 static void r810x_phy_power_down(struct rtl8169_private *tp)
2561 rtl_writephy(tp, 0x1f, 0x0000);
2562 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2565 static void r810x_phy_power_up(struct rtl8169_private *tp)
2567 rtl_writephy(tp, 0x1f, 0x0000);
2568 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2571 static void r810x_pll_power_down(struct rtl8169_private *tp)
2573 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2574 rtl_writephy(tp, 0x1f, 0x0000);
2575 rtl_writephy(tp, MII_BMCR, 0x0000);
2579 r810x_phy_power_down(tp);
2582 static void r810x_pll_power_up(struct rtl8169_private *tp)
2584 r810x_phy_power_up(tp);
2587 static void r8168_phy_power_up(struct rtl8169_private *tp)
2589 rtl_writephy(tp, 0x1f, 0x0000);
2590 rtl_writephy(tp, 0x0e, 0x0000);
2591 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2594 static void r8168_phy_power_down(struct rtl8169_private *tp)
2596 rtl_writephy(tp, 0x1f, 0x0000);
2597 rtl_writephy(tp, 0x0e, 0x0200);
2598 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2601 static void r8168_pll_power_down(struct rtl8169_private *tp)
2603 void __iomem *ioaddr = tp->mmio_addr;
2605 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2608 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2609 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2610 (RTL_R16(CPlusCmd) & ASF)) {
2614 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2615 rtl_writephy(tp, 0x1f, 0x0000);
2616 rtl_writephy(tp, MII_BMCR, 0x0000);
2618 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2619 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2623 r8168_phy_power_down(tp);
2625 switch (tp->mac_version) {
2626 case RTL_GIGA_MAC_VER_25:
2627 case RTL_GIGA_MAC_VER_26:
2628 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2633 static void r8168_pll_power_up(struct rtl8169_private *tp)
2635 void __iomem *ioaddr = tp->mmio_addr;
2637 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2640 switch (tp->mac_version) {
2641 case RTL_GIGA_MAC_VER_25:
2642 case RTL_GIGA_MAC_VER_26:
2643 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2647 r8168_phy_power_up(tp);
2650 static void rtl_pll_power_op(struct rtl8169_private *tp,
2651 void (*op)(struct rtl8169_private *))
2657 static void rtl_pll_power_down(struct rtl8169_private *tp)
2659 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2662 static void rtl_pll_power_up(struct rtl8169_private *tp)
2664 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2667 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2669 struct pll_power_ops *ops = &tp->pll_power_ops;
2671 switch (tp->mac_version) {
2672 case RTL_GIGA_MAC_VER_07:
2673 case RTL_GIGA_MAC_VER_08:
2674 case RTL_GIGA_MAC_VER_09:
2675 case RTL_GIGA_MAC_VER_10:
2676 case RTL_GIGA_MAC_VER_16:
2677 ops->down = r810x_pll_power_down;
2678 ops->up = r810x_pll_power_up;
2681 case RTL_GIGA_MAC_VER_11:
2682 case RTL_GIGA_MAC_VER_12:
2683 case RTL_GIGA_MAC_VER_17:
2684 case RTL_GIGA_MAC_VER_18:
2685 case RTL_GIGA_MAC_VER_19:
2686 case RTL_GIGA_MAC_VER_20:
2687 case RTL_GIGA_MAC_VER_21:
2688 case RTL_GIGA_MAC_VER_22:
2689 case RTL_GIGA_MAC_VER_23:
2690 case RTL_GIGA_MAC_VER_24:
2691 case RTL_GIGA_MAC_VER_25:
2692 case RTL_GIGA_MAC_VER_26:
2693 case RTL_GIGA_MAC_VER_27:
2694 ops->down = r8168_pll_power_down;
2695 ops->up = r8168_pll_power_up;
2705 static int __devinit
2706 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2708 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2709 const unsigned int region = cfg->region;
2710 struct rtl8169_private *tp;
2711 struct mii_if_info *mii;
2712 struct net_device *dev;
2713 void __iomem *ioaddr;
2717 if (netif_msg_drv(&debug)) {
2718 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2719 MODULENAME, RTL8169_VERSION);
2722 dev = alloc_etherdev(sizeof (*tp));
2724 if (netif_msg_drv(&debug))
2725 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2730 SET_NETDEV_DEV(dev, &pdev->dev);
2731 dev->netdev_ops = &rtl8169_netdev_ops;
2732 tp = netdev_priv(dev);
2735 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2739 mii->mdio_read = rtl_mdio_read;
2740 mii->mdio_write = rtl_mdio_write;
2741 mii->phy_id_mask = 0x1f;
2742 mii->reg_num_mask = 0x1f;
2743 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2745 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2746 rc = pci_enable_device(pdev);
2748 netif_err(tp, probe, dev, "enable failure\n");
2749 goto err_out_free_dev_1;
2752 if (pci_set_mwi(pdev) < 0)
2753 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2755 /* make sure PCI base addr 1 is MMIO */
2756 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2757 netif_err(tp, probe, dev,
2758 "region #%d not an MMIO resource, aborting\n",
2764 /* check for weird/broken PCI region reporting */
2765 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2766 netif_err(tp, probe, dev,
2767 "Invalid PCI region size(s), aborting\n");
2772 rc = pci_request_regions(pdev, MODULENAME);
2774 netif_err(tp, probe, dev, "could not request regions\n");
2778 tp->cp_cmd = PCIMulRW | RxChkSum;
2780 if ((sizeof(dma_addr_t) > 4) &&
2781 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2782 tp->cp_cmd |= PCIDAC;
2783 dev->features |= NETIF_F_HIGHDMA;
2785 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2787 netif_err(tp, probe, dev, "DMA configuration failed\n");
2788 goto err_out_free_res_3;
2792 /* ioremap MMIO region */
2793 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2795 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2797 goto err_out_free_res_3;
2800 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2802 netif_info(tp, probe, dev, "no PCI Express capability\n");
2804 RTL_W16(IntrMask, 0x0000);
2806 /* Soft reset the chip. */
2807 RTL_W8(ChipCmd, CmdReset);
2809 /* Check that the chip has finished the reset. */
2810 for (i = 0; i < 100; i++) {
2811 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2813 msleep_interruptible(1);
2816 RTL_W16(IntrStatus, 0xffff);
2818 pci_set_master(pdev);
2820 /* Identify chip attached to board */
2821 rtl8169_get_mac_version(tp, ioaddr);
2823 rtl_init_mdio_ops(tp);
2824 rtl_init_pll_power_ops(tp);
2826 /* Use appropriate default if unknown */
2827 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2828 netif_notice(tp, probe, dev,
2829 "unknown MAC, using family default\n");
2830 tp->mac_version = cfg->default_ver;
2833 rtl8169_print_mac_version(tp);
2835 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2836 if (tp->mac_version == rtl_chip_info[i].mac_version)
2839 if (i == ARRAY_SIZE(rtl_chip_info)) {
2841 "driver bug, MAC version not found in rtl_chip_info\n");
2846 RTL_W8(Cfg9346, Cfg9346_Unlock);
2847 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2848 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2849 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2850 tp->features |= RTL_FEATURE_WOL;
2851 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2852 tp->features |= RTL_FEATURE_WOL;
2853 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2854 RTL_W8(Cfg9346, Cfg9346_Lock);
2856 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2857 (RTL_R8(PHYstatus) & TBI_Enable)) {
2858 tp->set_speed = rtl8169_set_speed_tbi;
2859 tp->get_settings = rtl8169_gset_tbi;
2860 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2861 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2862 tp->link_ok = rtl8169_tbi_link_ok;
2863 tp->do_ioctl = rtl_tbi_ioctl;
2865 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2867 tp->set_speed = rtl8169_set_speed_xmii;
2868 tp->get_settings = rtl8169_gset_xmii;
2869 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2870 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2871 tp->link_ok = rtl8169_xmii_link_ok;
2872 tp->do_ioctl = rtl_xmii_ioctl;
2875 spin_lock_init(&tp->lock);
2877 tp->mmio_addr = ioaddr;
2879 /* Get MAC address */
2880 for (i = 0; i < MAC_ADDR_LEN; i++)
2881 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2882 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2884 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2885 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2886 dev->irq = pdev->irq;
2887 dev->base_addr = (unsigned long) ioaddr;
2889 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2891 #ifdef CONFIG_R8169_VLAN
2892 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2894 dev->features |= NETIF_F_GRO;
2896 tp->intr_mask = 0xffff;
2897 tp->hw_start = cfg->hw_start;
2898 tp->intr_event = cfg->intr_event;
2899 tp->napi_event = cfg->napi_event;
2901 init_timer(&tp->timer);
2902 tp->timer.data = (unsigned long) dev;
2903 tp->timer.function = rtl8169_phy_timer;
2905 rc = register_netdev(dev);
2909 pci_set_drvdata(pdev, dev);
2911 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2912 rtl_chip_info[tp->chipset].name,
2913 dev->base_addr, dev->dev_addr,
2914 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
2916 rtl8169_init_phy(dev, tp);
2919 * Pretend we are using VLANs; This bypasses a nasty bug where
2920 * Interrupts stop flowing on high load on 8110SCd controllers.
2922 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2923 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
2925 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2927 if (pci_dev_run_wake(pdev))
2928 pm_runtime_put_noidle(&pdev->dev);
2934 rtl_disable_msi(pdev, tp);
2937 pci_release_regions(pdev);
2939 pci_clear_mwi(pdev);
2940 pci_disable_device(pdev);
2946 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2948 struct net_device *dev = pci_get_drvdata(pdev);
2949 struct rtl8169_private *tp = netdev_priv(dev);
2951 cancel_delayed_work_sync(&tp->task);
2953 unregister_netdev(dev);
2955 if (pci_dev_run_wake(pdev))
2956 pm_runtime_get_noresume(&pdev->dev);
2958 /* restore original MAC address */
2959 rtl_rar_set(tp, dev->perm_addr);
2961 rtl_disable_msi(pdev, tp);
2962 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2963 pci_set_drvdata(pdev, NULL);
2966 static int rtl8169_open(struct net_device *dev)
2968 struct rtl8169_private *tp = netdev_priv(dev);
2969 struct pci_dev *pdev = tp->pci_dev;
2970 int retval = -ENOMEM;
2972 pm_runtime_get_sync(&pdev->dev);
2975 * Rx and Tx desscriptors needs 256 bytes alignment.
2976 * dma_alloc_coherent provides more.
2978 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
2979 &tp->TxPhyAddr, GFP_KERNEL);
2980 if (!tp->TxDescArray)
2981 goto err_pm_runtime_put;
2983 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
2984 &tp->RxPhyAddr, GFP_KERNEL);
2985 if (!tp->RxDescArray)
2988 retval = rtl8169_init_ring(dev);
2992 INIT_DELAYED_WORK(&tp->task, NULL);
2996 retval = request_irq(dev->irq, rtl8169_interrupt,
2997 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3000 goto err_release_ring_2;
3002 napi_enable(&tp->napi);
3004 rtl_pll_power_up(tp);
3008 rtl8169_request_timer(dev);
3010 tp->saved_wolopts = 0;
3011 pm_runtime_put_noidle(&pdev->dev);
3013 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3018 rtl8169_rx_clear(tp);
3020 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3022 tp->RxDescArray = NULL;
3024 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3026 tp->TxDescArray = NULL;
3028 pm_runtime_put_noidle(&pdev->dev);
3032 static void rtl8169_hw_reset(void __iomem *ioaddr)
3034 /* Disable interrupts */
3035 rtl8169_irq_mask_and_ack(ioaddr);
3037 /* Reset the chipset */
3038 RTL_W8(ChipCmd, CmdReset);
3044 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3046 void __iomem *ioaddr = tp->mmio_addr;
3047 u32 cfg = rtl8169_rx_config;
3049 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3050 RTL_W32(RxConfig, cfg);
3052 /* Set DMA burst size and Interframe Gap Time */
3053 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3054 (InterFrameGap << TxInterFrameGapShift));
3057 static void rtl_hw_start(struct net_device *dev)
3059 struct rtl8169_private *tp = netdev_priv(dev);
3060 void __iomem *ioaddr = tp->mmio_addr;
3063 /* Soft reset the chip. */
3064 RTL_W8(ChipCmd, CmdReset);
3066 /* Check that the chip has finished the reset. */
3067 for (i = 0; i < 100; i++) {
3068 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3070 msleep_interruptible(1);
3075 netif_start_queue(dev);
3079 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3080 void __iomem *ioaddr)
3083 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3084 * register to be written before TxDescAddrLow to work.
3085 * Switching from MMIO to I/O access fixes the issue as well.
3087 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3088 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3089 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3090 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3093 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3097 cmd = RTL_R16(CPlusCmd);
3098 RTL_W16(CPlusCmd, cmd);
3102 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3104 /* Low hurts. Let's disable the filtering. */
3105 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3108 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3110 static const struct {
3115 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3116 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3117 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3118 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3123 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3124 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3125 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3126 RTL_W32(0x7c, p->val);
3132 static void rtl_hw_start_8169(struct net_device *dev)
3134 struct rtl8169_private *tp = netdev_priv(dev);
3135 void __iomem *ioaddr = tp->mmio_addr;
3136 struct pci_dev *pdev = tp->pci_dev;
3138 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3139 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3140 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3143 RTL_W8(Cfg9346, Cfg9346_Unlock);
3144 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3145 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3146 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3147 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3148 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3150 RTL_W8(EarlyTxThres, NoEarlyTx);
3152 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3154 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3155 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3156 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3157 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3158 rtl_set_rx_tx_config_registers(tp);
3160 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3162 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3163 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3164 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3165 "Bit-3 and bit-14 MUST be 1\n");
3166 tp->cp_cmd |= (1 << 14);
3169 RTL_W16(CPlusCmd, tp->cp_cmd);
3171 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3174 * Undocumented corner. Supposedly:
3175 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3177 RTL_W16(IntrMitigate, 0x0000);
3179 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3181 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3182 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3183 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3184 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3185 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3186 rtl_set_rx_tx_config_registers(tp);
3189 RTL_W8(Cfg9346, Cfg9346_Lock);
3191 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3194 RTL_W32(RxMissed, 0);
3196 rtl_set_rx_mode(dev);
3198 /* no early-rx interrupts */
3199 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3201 /* Enable all known interrupts by setting the interrupt mask. */
3202 RTL_W16(IntrMask, tp->intr_event);
3205 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3207 struct net_device *dev = pci_get_drvdata(pdev);
3208 struct rtl8169_private *tp = netdev_priv(dev);
3209 int cap = tp->pcie_cap;
3214 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3215 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3216 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3220 static void rtl_csi_access_enable(void __iomem *ioaddr)
3224 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3225 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3229 unsigned int offset;
3234 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3239 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3240 rtl_ephy_write(ioaddr, e->offset, w);
3245 static void rtl_disable_clock_request(struct pci_dev *pdev)
3247 struct net_device *dev = pci_get_drvdata(pdev);
3248 struct rtl8169_private *tp = netdev_priv(dev);
3249 int cap = tp->pcie_cap;
3254 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3255 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3256 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3260 #define R8168_CPCMD_QUIRK_MASK (\
3271 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3273 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3275 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3277 rtl_tx_performance_tweak(pdev,
3278 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3281 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3283 rtl_hw_start_8168bb(ioaddr, pdev);
3285 RTL_W8(MaxTxPacketSize, TxPacketMax);
3287 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3290 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3292 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3294 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3296 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3298 rtl_disable_clock_request(pdev);
3300 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3303 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3305 static const struct ephy_info e_info_8168cp[] = {
3306 { 0x01, 0, 0x0001 },
3307 { 0x02, 0x0800, 0x1000 },
3308 { 0x03, 0, 0x0042 },
3309 { 0x06, 0x0080, 0x0000 },
3313 rtl_csi_access_enable(ioaddr);
3315 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3317 __rtl_hw_start_8168cp(ioaddr, pdev);
3320 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3322 rtl_csi_access_enable(ioaddr);
3324 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3326 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3328 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3331 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3333 rtl_csi_access_enable(ioaddr);
3335 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3338 RTL_W8(DBG_REG, 0x20);
3340 RTL_W8(MaxTxPacketSize, TxPacketMax);
3342 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3344 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3347 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3349 static const struct ephy_info e_info_8168c_1[] = {
3350 { 0x02, 0x0800, 0x1000 },
3351 { 0x03, 0, 0x0002 },
3352 { 0x06, 0x0080, 0x0000 }
3355 rtl_csi_access_enable(ioaddr);
3357 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3359 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3361 __rtl_hw_start_8168cp(ioaddr, pdev);
3364 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3366 static const struct ephy_info e_info_8168c_2[] = {
3367 { 0x01, 0, 0x0001 },
3368 { 0x03, 0x0400, 0x0220 }
3371 rtl_csi_access_enable(ioaddr);
3373 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3375 __rtl_hw_start_8168cp(ioaddr, pdev);
3378 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3380 rtl_hw_start_8168c_2(ioaddr, pdev);
3383 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3385 rtl_csi_access_enable(ioaddr);
3387 __rtl_hw_start_8168cp(ioaddr, pdev);
3390 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3392 rtl_csi_access_enable(ioaddr);
3394 rtl_disable_clock_request(pdev);
3396 RTL_W8(MaxTxPacketSize, TxPacketMax);
3398 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3400 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3403 static void rtl_hw_start_8168(struct net_device *dev)
3405 struct rtl8169_private *tp = netdev_priv(dev);
3406 void __iomem *ioaddr = tp->mmio_addr;
3407 struct pci_dev *pdev = tp->pci_dev;
3409 RTL_W8(Cfg9346, Cfg9346_Unlock);
3411 RTL_W8(MaxTxPacketSize, TxPacketMax);
3413 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3415 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3417 RTL_W16(CPlusCmd, tp->cp_cmd);
3419 RTL_W16(IntrMitigate, 0x5151);
3421 /* Work around for RxFIFO overflow. */
3422 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3423 tp->intr_event |= RxFIFOOver | PCSTimeout;
3424 tp->intr_event &= ~RxOverflow;
3427 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3429 rtl_set_rx_mode(dev);
3431 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3432 (InterFrameGap << TxInterFrameGapShift));
3436 switch (tp->mac_version) {
3437 case RTL_GIGA_MAC_VER_11:
3438 rtl_hw_start_8168bb(ioaddr, pdev);
3441 case RTL_GIGA_MAC_VER_12:
3442 case RTL_GIGA_MAC_VER_17:
3443 rtl_hw_start_8168bef(ioaddr, pdev);
3446 case RTL_GIGA_MAC_VER_18:
3447 rtl_hw_start_8168cp_1(ioaddr, pdev);
3450 case RTL_GIGA_MAC_VER_19:
3451 rtl_hw_start_8168c_1(ioaddr, pdev);
3454 case RTL_GIGA_MAC_VER_20:
3455 rtl_hw_start_8168c_2(ioaddr, pdev);
3458 case RTL_GIGA_MAC_VER_21:
3459 rtl_hw_start_8168c_3(ioaddr, pdev);
3462 case RTL_GIGA_MAC_VER_22:
3463 rtl_hw_start_8168c_4(ioaddr, pdev);
3466 case RTL_GIGA_MAC_VER_23:
3467 rtl_hw_start_8168cp_2(ioaddr, pdev);
3470 case RTL_GIGA_MAC_VER_24:
3471 rtl_hw_start_8168cp_3(ioaddr, pdev);
3474 case RTL_GIGA_MAC_VER_25:
3475 case RTL_GIGA_MAC_VER_26:
3476 case RTL_GIGA_MAC_VER_27:
3477 rtl_hw_start_8168d(ioaddr, pdev);
3481 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3482 dev->name, tp->mac_version);
3486 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3488 RTL_W8(Cfg9346, Cfg9346_Lock);
3490 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3492 RTL_W16(IntrMask, tp->intr_event);
3495 #define R810X_CPCMD_QUIRK_MASK (\
3507 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3509 static const struct ephy_info e_info_8102e_1[] = {
3510 { 0x01, 0, 0x6e65 },
3511 { 0x02, 0, 0x091f },
3512 { 0x03, 0, 0xc2f9 },
3513 { 0x06, 0, 0xafb5 },
3514 { 0x07, 0, 0x0e00 },
3515 { 0x19, 0, 0xec80 },
3516 { 0x01, 0, 0x2e65 },
3521 rtl_csi_access_enable(ioaddr);
3523 RTL_W8(DBG_REG, FIX_NAK_1);
3525 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3528 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3529 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3531 cfg1 = RTL_R8(Config1);
3532 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3533 RTL_W8(Config1, cfg1 & ~LEDS0);
3535 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3537 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3540 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3542 rtl_csi_access_enable(ioaddr);
3544 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3546 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3547 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3549 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3552 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3554 rtl_hw_start_8102e_2(ioaddr, pdev);
3556 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3559 static void rtl_hw_start_8101(struct net_device *dev)
3561 struct rtl8169_private *tp = netdev_priv(dev);
3562 void __iomem *ioaddr = tp->mmio_addr;
3563 struct pci_dev *pdev = tp->pci_dev;
3565 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3566 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3567 int cap = tp->pcie_cap;
3570 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3571 PCI_EXP_DEVCTL_NOSNOOP_EN);
3575 switch (tp->mac_version) {
3576 case RTL_GIGA_MAC_VER_07:
3577 rtl_hw_start_8102e_1(ioaddr, pdev);
3580 case RTL_GIGA_MAC_VER_08:
3581 rtl_hw_start_8102e_3(ioaddr, pdev);
3584 case RTL_GIGA_MAC_VER_09:
3585 rtl_hw_start_8102e_2(ioaddr, pdev);
3589 RTL_W8(Cfg9346, Cfg9346_Unlock);
3591 RTL_W8(MaxTxPacketSize, TxPacketMax);
3593 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3595 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3597 RTL_W16(CPlusCmd, tp->cp_cmd);
3599 RTL_W16(IntrMitigate, 0x0000);
3601 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3603 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3604 rtl_set_rx_tx_config_registers(tp);
3606 RTL_W8(Cfg9346, Cfg9346_Lock);
3610 rtl_set_rx_mode(dev);
3612 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3614 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3616 RTL_W16(IntrMask, tp->intr_event);
3619 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3621 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3628 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3630 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3631 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3634 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3635 void **data_buff, struct RxDesc *desc)
3637 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3642 rtl8169_make_unusable_by_asic(desc);
3645 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3647 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3649 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3652 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3655 desc->addr = cpu_to_le64(mapping);
3657 rtl8169_mark_to_asic(desc, rx_buf_sz);
3660 static inline void *rtl8169_align(void *data)
3662 return (void *)ALIGN((long)data, 16);
3665 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3666 struct RxDesc *desc)
3670 struct device *d = &tp->pci_dev->dev;
3671 struct net_device *dev = tp->dev;
3672 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3674 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3678 if (rtl8169_align(data) != data) {
3680 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3685 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3687 if (unlikely(dma_mapping_error(d, mapping))) {
3688 if (net_ratelimit())
3689 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3693 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3701 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3705 for (i = 0; i < NUM_RX_DESC; i++) {
3706 if (tp->Rx_databuff[i]) {
3707 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3708 tp->RxDescArray + i);
3713 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3715 desc->opts1 |= cpu_to_le32(RingEnd);
3718 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3722 for (i = 0; i < NUM_RX_DESC; i++) {
3725 if (tp->Rx_databuff[i])
3728 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3730 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3733 tp->Rx_databuff[i] = data;
3736 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3740 rtl8169_rx_clear(tp);
3744 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3746 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3749 static int rtl8169_init_ring(struct net_device *dev)
3751 struct rtl8169_private *tp = netdev_priv(dev);
3753 rtl8169_init_ring_indexes(tp);
3755 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3756 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3758 return rtl8169_rx_fill(tp);
3761 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3762 struct TxDesc *desc)
3764 unsigned int len = tx_skb->len;
3766 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3774 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3779 for (i = 0; i < n; i++) {
3780 unsigned int entry = (start + i) % NUM_TX_DESC;
3781 struct ring_info *tx_skb = tp->tx_skb + entry;
3782 unsigned int len = tx_skb->len;
3785 struct sk_buff *skb = tx_skb->skb;
3787 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3788 tp->TxDescArray + entry);
3790 tp->dev->stats.tx_dropped++;
3798 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3800 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3801 tp->cur_tx = tp->dirty_tx = 0;
3804 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3806 struct rtl8169_private *tp = netdev_priv(dev);
3808 PREPARE_DELAYED_WORK(&tp->task, task);
3809 schedule_delayed_work(&tp->task, 4);
3812 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3814 struct rtl8169_private *tp = netdev_priv(dev);
3815 void __iomem *ioaddr = tp->mmio_addr;
3817 synchronize_irq(dev->irq);
3819 /* Wait for any pending NAPI task to complete */
3820 napi_disable(&tp->napi);
3822 rtl8169_irq_mask_and_ack(ioaddr);
3824 tp->intr_mask = 0xffff;
3825 RTL_W16(IntrMask, tp->intr_event);
3826 napi_enable(&tp->napi);
3829 static void rtl8169_reinit_task(struct work_struct *work)
3831 struct rtl8169_private *tp =
3832 container_of(work, struct rtl8169_private, task.work);
3833 struct net_device *dev = tp->dev;
3838 if (!netif_running(dev))
3841 rtl8169_wait_for_quiescence(dev);
3844 ret = rtl8169_open(dev);
3845 if (unlikely(ret < 0)) {
3846 if (net_ratelimit())
3847 netif_err(tp, drv, dev,
3848 "reinit failure (status = %d). Rescheduling\n",
3850 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3857 static void rtl8169_reset_task(struct work_struct *work)
3859 struct rtl8169_private *tp =
3860 container_of(work, struct rtl8169_private, task.work);
3861 struct net_device *dev = tp->dev;
3865 if (!netif_running(dev))
3868 rtl8169_wait_for_quiescence(dev);
3870 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3871 rtl8169_tx_clear(tp);
3873 if (tp->dirty_rx == tp->cur_rx) {
3874 rtl8169_init_ring_indexes(tp);
3876 netif_wake_queue(dev);
3877 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3879 if (net_ratelimit())
3880 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
3881 rtl8169_schedule_work(dev, rtl8169_reset_task);
3888 static void rtl8169_tx_timeout(struct net_device *dev)
3890 struct rtl8169_private *tp = netdev_priv(dev);
3892 rtl8169_hw_reset(tp->mmio_addr);
3894 /* Let's wait a bit while any (async) irq lands on */
3895 rtl8169_schedule_work(dev, rtl8169_reset_task);
3898 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3901 struct skb_shared_info *info = skb_shinfo(skb);
3902 unsigned int cur_frag, entry;
3903 struct TxDesc * uninitialized_var(txd);
3904 struct device *d = &tp->pci_dev->dev;
3907 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3908 skb_frag_t *frag = info->frags + cur_frag;
3913 entry = (entry + 1) % NUM_TX_DESC;
3915 txd = tp->TxDescArray + entry;
3917 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3918 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3919 if (unlikely(dma_mapping_error(d, mapping))) {
3920 if (net_ratelimit())
3921 netif_err(tp, drv, tp->dev,
3922 "Failed to map TX fragments DMA!\n");
3926 /* anti gcc 2.95.3 bugware (sic) */
3927 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3929 txd->opts1 = cpu_to_le32(status);
3930 txd->addr = cpu_to_le64(mapping);
3932 tp->tx_skb[entry].len = len;
3936 tp->tx_skb[entry].skb = skb;
3937 txd->opts1 |= cpu_to_le32(LastFrag);
3943 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3947 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3949 if (dev->features & NETIF_F_TSO) {
3950 u32 mss = skb_shinfo(skb)->gso_size;
3953 return LargeSend | ((mss & MSSMask) << MSSShift);
3955 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3956 const struct iphdr *ip = ip_hdr(skb);
3958 if (ip->protocol == IPPROTO_TCP)
3959 return IPCS | TCPCS;
3960 else if (ip->protocol == IPPROTO_UDP)
3961 return IPCS | UDPCS;
3962 WARN_ON(1); /* we need a WARN() */
3967 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
3968 struct net_device *dev)
3970 struct rtl8169_private *tp = netdev_priv(dev);
3971 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
3972 struct TxDesc *txd = tp->TxDescArray + entry;
3973 void __iomem *ioaddr = tp->mmio_addr;
3974 struct device *d = &tp->pci_dev->dev;
3980 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3981 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3985 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3988 len = skb_headlen(skb);
3989 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
3990 if (unlikely(dma_mapping_error(d, mapping))) {
3991 if (net_ratelimit())
3992 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3996 tp->tx_skb[entry].len = len;
3997 txd->addr = cpu_to_le64(mapping);
3998 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4000 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4002 frags = rtl8169_xmit_frags(tp, skb, opts1);
4008 opts1 |= FirstFrag | LastFrag;
4009 tp->tx_skb[entry].skb = skb;
4014 /* anti gcc 2.95.3 bugware (sic) */
4015 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4016 txd->opts1 = cpu_to_le32(status);
4018 tp->cur_tx += frags + 1;
4022 RTL_W8(TxPoll, NPQ); /* set polling bit */
4024 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4025 netif_stop_queue(dev);
4027 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4028 netif_wake_queue(dev);
4031 return NETDEV_TX_OK;
4034 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4037 dev->stats.tx_dropped++;
4038 return NETDEV_TX_OK;
4041 netif_stop_queue(dev);
4042 dev->stats.tx_dropped++;
4043 return NETDEV_TX_BUSY;
4046 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4048 struct rtl8169_private *tp = netdev_priv(dev);
4049 struct pci_dev *pdev = tp->pci_dev;
4050 void __iomem *ioaddr = tp->mmio_addr;
4051 u16 pci_status, pci_cmd;
4053 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4054 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4056 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4057 pci_cmd, pci_status);
4060 * The recovery sequence below admits a very elaborated explanation:
4061 * - it seems to work;
4062 * - I did not see what else could be done;
4063 * - it makes iop3xx happy.
4065 * Feel free to adjust to your needs.
4067 if (pdev->broken_parity_status)
4068 pci_cmd &= ~PCI_COMMAND_PARITY;
4070 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4072 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4074 pci_write_config_word(pdev, PCI_STATUS,
4075 pci_status & (PCI_STATUS_DETECTED_PARITY |
4076 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4077 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4079 /* The infamous DAC f*ckup only happens at boot time */
4080 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4081 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4082 tp->cp_cmd &= ~PCIDAC;
4083 RTL_W16(CPlusCmd, tp->cp_cmd);
4084 dev->features &= ~NETIF_F_HIGHDMA;
4087 rtl8169_hw_reset(ioaddr);
4089 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4092 static void rtl8169_tx_interrupt(struct net_device *dev,
4093 struct rtl8169_private *tp,
4094 void __iomem *ioaddr)
4096 unsigned int dirty_tx, tx_left;
4098 dirty_tx = tp->dirty_tx;
4100 tx_left = tp->cur_tx - dirty_tx;
4102 while (tx_left > 0) {
4103 unsigned int entry = dirty_tx % NUM_TX_DESC;
4104 struct ring_info *tx_skb = tp->tx_skb + entry;
4108 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4109 if (status & DescOwn)
4112 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4113 tp->TxDescArray + entry);
4114 if (status & LastFrag) {
4115 dev->stats.tx_packets++;
4116 dev->stats.tx_bytes += tx_skb->skb->len;
4117 dev_kfree_skb(tx_skb->skb);
4124 if (tp->dirty_tx != dirty_tx) {
4125 tp->dirty_tx = dirty_tx;
4127 if (netif_queue_stopped(dev) &&
4128 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4129 netif_wake_queue(dev);
4132 * 8168 hack: TxPoll requests are lost when the Tx packets are
4133 * too close. Let's kick an extra TxPoll request when a burst
4134 * of start_xmit activity is detected (if it is not detected,
4135 * it is slow enough). -- FR
4138 if (tp->cur_tx != dirty_tx)
4139 RTL_W8(TxPoll, NPQ);
4143 static inline int rtl8169_fragmented_frame(u32 status)
4145 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4148 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4150 u32 status = opts1 & RxProtoMask;
4152 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4153 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4154 skb->ip_summed = CHECKSUM_UNNECESSARY;
4156 skb_checksum_none_assert(skb);
4159 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4160 struct rtl8169_private *tp,
4164 struct sk_buff *skb;
4165 struct device *d = &tp->pci_dev->dev;
4167 data = rtl8169_align(data);
4168 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4170 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4172 memcpy(skb->data, data, pkt_size);
4173 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4179 * Warning : rtl8169_rx_interrupt() might be called :
4180 * 1) from NAPI (softirq) context
4181 * (polling = 1 : we should call netif_receive_skb())
4182 * 2) from process context (rtl8169_reset_task())
4183 * (polling = 0 : we must call netif_rx() instead)
4185 static int rtl8169_rx_interrupt(struct net_device *dev,
4186 struct rtl8169_private *tp,
4187 void __iomem *ioaddr, u32 budget)
4189 unsigned int cur_rx, rx_left;
4191 int polling = (budget != ~(u32)0) ? 1 : 0;
4193 cur_rx = tp->cur_rx;
4194 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4195 rx_left = min(rx_left, budget);
4197 for (; rx_left > 0; rx_left--, cur_rx++) {
4198 unsigned int entry = cur_rx % NUM_RX_DESC;
4199 struct RxDesc *desc = tp->RxDescArray + entry;
4203 status = le32_to_cpu(desc->opts1);
4205 if (status & DescOwn)
4207 if (unlikely(status & RxRES)) {
4208 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4210 dev->stats.rx_errors++;
4211 if (status & (RxRWT | RxRUNT))
4212 dev->stats.rx_length_errors++;
4214 dev->stats.rx_crc_errors++;
4215 if (status & RxFOVF) {
4216 rtl8169_schedule_work(dev, rtl8169_reset_task);
4217 dev->stats.rx_fifo_errors++;
4219 rtl8169_mark_to_asic(desc, rx_buf_sz);
4221 struct sk_buff *skb;
4222 dma_addr_t addr = le64_to_cpu(desc->addr);
4223 int pkt_size = (status & 0x00001FFF) - 4;
4226 * The driver does not support incoming fragmented
4227 * frames. They are seen as a symptom of over-mtu
4230 if (unlikely(rtl8169_fragmented_frame(status))) {
4231 dev->stats.rx_dropped++;
4232 dev->stats.rx_length_errors++;
4233 rtl8169_mark_to_asic(desc, rx_buf_sz);
4237 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4238 tp, pkt_size, addr);
4239 rtl8169_mark_to_asic(desc, rx_buf_sz);
4241 dev->stats.rx_dropped++;
4245 rtl8169_rx_csum(skb, status);
4246 skb_put(skb, pkt_size);
4247 skb->protocol = eth_type_trans(skb, dev);
4249 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4250 if (likely(polling))
4251 napi_gro_receive(&tp->napi, skb);
4256 dev->stats.rx_bytes += pkt_size;
4257 dev->stats.rx_packets++;
4260 /* Work around for AMD plateform. */
4261 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4262 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4268 count = cur_rx - tp->cur_rx;
4269 tp->cur_rx = cur_rx;
4271 tp->dirty_rx += count;
4276 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4278 struct net_device *dev = dev_instance;
4279 struct rtl8169_private *tp = netdev_priv(dev);
4280 void __iomem *ioaddr = tp->mmio_addr;
4284 /* loop handling interrupts until we have no new ones or
4285 * we hit a invalid/hotplug case.
4287 status = RTL_R16(IntrStatus);
4288 while (status && status != 0xffff) {
4291 /* Handle all of the error cases first. These will reset
4292 * the chip, so just exit the loop.
4294 if (unlikely(!netif_running(dev))) {
4295 rtl8169_asic_down(ioaddr);
4299 /* Work around for rx fifo overflow */
4300 if (unlikely(status & RxFIFOOver) &&
4301 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4302 netif_stop_queue(dev);
4303 rtl8169_tx_timeout(dev);
4307 if (unlikely(status & SYSErr)) {
4308 rtl8169_pcierr_interrupt(dev);
4312 if (status & LinkChg)
4313 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4315 /* We need to see the lastest version of tp->intr_mask to
4316 * avoid ignoring an MSI interrupt and having to wait for
4317 * another event which may never come.
4320 if (status & tp->intr_mask & tp->napi_event) {
4321 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4322 tp->intr_mask = ~tp->napi_event;
4324 if (likely(napi_schedule_prep(&tp->napi)))
4325 __napi_schedule(&tp->napi);
4327 netif_info(tp, intr, dev,
4328 "interrupt %04x in poll\n", status);
4331 /* We only get a new MSI interrupt when all active irq
4332 * sources on the chip have been acknowledged. So, ack
4333 * everything we've seen and check if new sources have become
4334 * active to avoid blocking all interrupts from the chip.
4337 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4338 status = RTL_R16(IntrStatus);
4341 return IRQ_RETVAL(handled);
4344 static int rtl8169_poll(struct napi_struct *napi, int budget)
4346 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4347 struct net_device *dev = tp->dev;
4348 void __iomem *ioaddr = tp->mmio_addr;
4351 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4352 rtl8169_tx_interrupt(dev, tp, ioaddr);
4354 if (work_done < budget) {
4355 napi_complete(napi);
4357 /* We need for force the visibility of tp->intr_mask
4358 * for other CPUs, as we can loose an MSI interrupt
4359 * and potentially wait for a retransmit timeout if we don't.
4360 * The posted write to IntrMask is safe, as it will
4361 * eventually make it to the chip and we won't loose anything
4364 tp->intr_mask = 0xffff;
4366 RTL_W16(IntrMask, tp->intr_event);
4372 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4374 struct rtl8169_private *tp = netdev_priv(dev);
4376 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4379 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4380 RTL_W32(RxMissed, 0);
4383 static void rtl8169_down(struct net_device *dev)
4385 struct rtl8169_private *tp = netdev_priv(dev);
4386 void __iomem *ioaddr = tp->mmio_addr;
4388 rtl8169_delete_timer(dev);
4390 netif_stop_queue(dev);
4392 napi_disable(&tp->napi);
4394 spin_lock_irq(&tp->lock);
4396 rtl8169_asic_down(ioaddr);
4398 * At this point device interrupts can not be enabled in any function,
4399 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4400 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4402 rtl8169_rx_missed(dev, ioaddr);
4404 spin_unlock_irq(&tp->lock);
4406 synchronize_irq(dev->irq);
4408 /* Give a racing hard_start_xmit a few cycles to complete. */
4409 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4411 rtl8169_tx_clear(tp);
4413 rtl8169_rx_clear(tp);
4415 rtl_pll_power_down(tp);
4418 static int rtl8169_close(struct net_device *dev)
4420 struct rtl8169_private *tp = netdev_priv(dev);
4421 struct pci_dev *pdev = tp->pci_dev;
4423 pm_runtime_get_sync(&pdev->dev);
4425 /* update counters before going down */
4426 rtl8169_update_counters(dev);
4430 free_irq(dev->irq, dev);
4432 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4434 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4436 tp->TxDescArray = NULL;
4437 tp->RxDescArray = NULL;
4439 pm_runtime_put_sync(&pdev->dev);
4444 static void rtl_set_rx_mode(struct net_device *dev)
4446 struct rtl8169_private *tp = netdev_priv(dev);
4447 void __iomem *ioaddr = tp->mmio_addr;
4448 unsigned long flags;
4449 u32 mc_filter[2]; /* Multicast hash filter */
4453 if (dev->flags & IFF_PROMISC) {
4454 /* Unconditionally log net taps. */
4455 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4457 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4459 mc_filter[1] = mc_filter[0] = 0xffffffff;
4460 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4461 (dev->flags & IFF_ALLMULTI)) {
4462 /* Too many to filter perfectly -- accept all multicasts. */
4463 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4464 mc_filter[1] = mc_filter[0] = 0xffffffff;
4466 struct netdev_hw_addr *ha;
4468 rx_mode = AcceptBroadcast | AcceptMyPhys;
4469 mc_filter[1] = mc_filter[0] = 0;
4470 netdev_for_each_mc_addr(ha, dev) {
4471 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4472 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4473 rx_mode |= AcceptMulticast;
4477 spin_lock_irqsave(&tp->lock, flags);
4479 tmp = rtl8169_rx_config | rx_mode |
4480 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4482 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4483 u32 data = mc_filter[0];
4485 mc_filter[0] = swab32(mc_filter[1]);
4486 mc_filter[1] = swab32(data);
4489 RTL_W32(MAR0 + 4, mc_filter[1]);
4490 RTL_W32(MAR0 + 0, mc_filter[0]);
4492 RTL_W32(RxConfig, tmp);
4494 spin_unlock_irqrestore(&tp->lock, flags);
4498 * rtl8169_get_stats - Get rtl8169 read/write statistics
4499 * @dev: The Ethernet Device to get statistics for
4501 * Get TX/RX statistics for rtl8169
4503 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4505 struct rtl8169_private *tp = netdev_priv(dev);
4506 void __iomem *ioaddr = tp->mmio_addr;
4507 unsigned long flags;
4509 if (netif_running(dev)) {
4510 spin_lock_irqsave(&tp->lock, flags);
4511 rtl8169_rx_missed(dev, ioaddr);
4512 spin_unlock_irqrestore(&tp->lock, flags);
4518 static void rtl8169_net_suspend(struct net_device *dev)
4520 struct rtl8169_private *tp = netdev_priv(dev);
4522 if (!netif_running(dev))
4525 rtl_pll_power_down(tp);
4527 netif_device_detach(dev);
4528 netif_stop_queue(dev);
4533 static int rtl8169_suspend(struct device *device)
4535 struct pci_dev *pdev = to_pci_dev(device);
4536 struct net_device *dev = pci_get_drvdata(pdev);
4538 rtl8169_net_suspend(dev);
4543 static void __rtl8169_resume(struct net_device *dev)
4545 struct rtl8169_private *tp = netdev_priv(dev);
4547 netif_device_attach(dev);
4549 rtl_pll_power_up(tp);
4551 rtl8169_schedule_work(dev, rtl8169_reset_task);
4554 static int rtl8169_resume(struct device *device)
4556 struct pci_dev *pdev = to_pci_dev(device);
4557 struct net_device *dev = pci_get_drvdata(pdev);
4558 struct rtl8169_private *tp = netdev_priv(dev);
4560 rtl8169_init_phy(dev, tp);
4562 if (netif_running(dev))
4563 __rtl8169_resume(dev);
4568 static int rtl8169_runtime_suspend(struct device *device)
4570 struct pci_dev *pdev = to_pci_dev(device);
4571 struct net_device *dev = pci_get_drvdata(pdev);
4572 struct rtl8169_private *tp = netdev_priv(dev);
4574 if (!tp->TxDescArray)
4577 spin_lock_irq(&tp->lock);
4578 tp->saved_wolopts = __rtl8169_get_wol(tp);
4579 __rtl8169_set_wol(tp, WAKE_ANY);
4580 spin_unlock_irq(&tp->lock);
4582 rtl8169_net_suspend(dev);
4587 static int rtl8169_runtime_resume(struct device *device)
4589 struct pci_dev *pdev = to_pci_dev(device);
4590 struct net_device *dev = pci_get_drvdata(pdev);
4591 struct rtl8169_private *tp = netdev_priv(dev);
4593 if (!tp->TxDescArray)
4596 spin_lock_irq(&tp->lock);
4597 __rtl8169_set_wol(tp, tp->saved_wolopts);
4598 tp->saved_wolopts = 0;
4599 spin_unlock_irq(&tp->lock);
4601 rtl8169_init_phy(dev, tp);
4603 __rtl8169_resume(dev);
4608 static int rtl8169_runtime_idle(struct device *device)
4610 struct pci_dev *pdev = to_pci_dev(device);
4611 struct net_device *dev = pci_get_drvdata(pdev);
4612 struct rtl8169_private *tp = netdev_priv(dev);
4614 return tp->TxDescArray ? -EBUSY : 0;
4617 static const struct dev_pm_ops rtl8169_pm_ops = {
4618 .suspend = rtl8169_suspend,
4619 .resume = rtl8169_resume,
4620 .freeze = rtl8169_suspend,
4621 .thaw = rtl8169_resume,
4622 .poweroff = rtl8169_suspend,
4623 .restore = rtl8169_resume,
4624 .runtime_suspend = rtl8169_runtime_suspend,
4625 .runtime_resume = rtl8169_runtime_resume,
4626 .runtime_idle = rtl8169_runtime_idle,
4629 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4631 #else /* !CONFIG_PM */
4633 #define RTL8169_PM_OPS NULL
4635 #endif /* !CONFIG_PM */
4637 static void rtl_shutdown(struct pci_dev *pdev)
4639 struct net_device *dev = pci_get_drvdata(pdev);
4640 struct rtl8169_private *tp = netdev_priv(dev);
4641 void __iomem *ioaddr = tp->mmio_addr;
4643 rtl8169_net_suspend(dev);
4645 /* restore original MAC address */
4646 rtl_rar_set(tp, dev->perm_addr);
4648 spin_lock_irq(&tp->lock);
4650 rtl8169_asic_down(ioaddr);
4652 spin_unlock_irq(&tp->lock);
4654 if (system_state == SYSTEM_POWER_OFF) {
4655 /* WoL fails with some 8168 when the receiver is disabled. */
4656 if (tp->features & RTL_FEATURE_WOL) {
4657 pci_clear_master(pdev);
4659 RTL_W8(ChipCmd, CmdRxEnb);
4664 pci_wake_from_d3(pdev, true);
4665 pci_set_power_state(pdev, PCI_D3hot);
4669 static struct pci_driver rtl8169_pci_driver = {
4671 .id_table = rtl8169_pci_tbl,
4672 .probe = rtl8169_init_one,
4673 .remove = __devexit_p(rtl8169_remove_one),
4674 .shutdown = rtl_shutdown,
4675 .driver.pm = RTL8169_PM_OPS,
4678 static int __init rtl8169_init_module(void)
4680 return pci_register_driver(&rtl8169_pci_driver);
4683 static void __exit rtl8169_cleanup_module(void)
4685 pci_unregister_driver(&rtl8169_pci_driver);
4688 module_init(rtl8169_init_module);
4689 module_exit(rtl8169_cleanup_module);