2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qlge for copyright and licensing details.
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
14 * General definitions...
16 #define DRV_NAME "qlge"
17 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
18 #define DRV_VERSION "v1.00.00-b3"
21 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
26 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
27 "%s: " fmt, __func__, ##args); \
30 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
32 #define QLGE_VENDOR_ID 0x1077
33 #define QLGE_DEVICE_ID_8012 0x8012
34 #define QLGE_DEVICE_ID_8000 0x8000
36 #define MAX_TX_RINGS MAX_CPUS
37 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
39 #define NUM_TX_RING_ENTRIES 256
40 #define NUM_RX_RING_ENTRIES 256
42 #define NUM_SMALL_BUFFERS 512
43 #define NUM_LARGE_BUFFERS 512
45 #define SMALL_BUFFER_SIZE 256
46 #define LARGE_BUFFER_SIZE PAGE_SIZE
47 #define MAX_SPLIT_SIZE 1023
48 #define QLGE_SB_PAD 32
51 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
52 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
53 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
54 #define UDELAY_COUNT 3
55 #define UDELAY_DELAY 100
58 #define TX_DESC_PER_IOCB 8
59 /* The maximum number of frags we handle is based
62 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
63 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
64 #else /* all other page sizes */
65 #define TX_DESC_PER_OAL 0
68 #define DB_PAGE_SIZE 4096
70 /* MPI test register definitions. This register
71 * is used for determining alternate NIC function's
75 MPI_TEST_FUNC_PORT_CFG = 0x1002,
76 MPI_TEST_NIC1_FUNC_SHIFT = 1,
77 MPI_TEST_NIC2_FUNC_SHIFT = 5,
78 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
82 * Processor Address Register (PROC_ADDR) bit definitions.
89 PROC_ADDR_RDY = (1 << 31),
90 PROC_ADDR_R = (1 << 30),
91 PROC_ADDR_ERR = (1 << 29),
92 PROC_ADDR_DA = (1 << 28),
93 PROC_ADDR_FUNC0_MBI = 0x00001180,
94 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
95 PROC_ADDR_FUNC0_CTL = 0x000011a1,
96 PROC_ADDR_FUNC2_MBI = 0x00001280,
97 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
98 PROC_ADDR_FUNC2_CTL = 0x000012a1,
99 PROC_ADDR_MPI_RISC = 0x00000000,
100 PROC_ADDR_MDE = 0x00010000,
101 PROC_ADDR_REGBLOCK = 0x00020000,
102 PROC_ADDR_RISC_REG = 0x00030000,
106 * System Register (SYS) bit definitions.
115 SYS_OMP_DLY_MASK = 0x3f000000,
117 * There are no values defined as of edit #15.
123 * Reset/Failover Register (RST_FO) bit definitions.
126 RST_FO_TFO = (1 << 0),
127 RST_FO_RR_MASK = 0x00060000,
128 RST_FO_RR_CQ_CAM = 0x00000000,
129 RST_FO_RR_DROP = 0x00000001,
130 RST_FO_RR_DQ = 0x00000002,
131 RST_FO_RR_RCV_FUNC_CQ = 0x00000003,
132 RST_FO_FRB = (1 << 12),
133 RST_FO_MOP = (1 << 13),
134 RST_FO_REG = (1 << 14),
135 RST_FO_FR = (1 << 15),
139 * Function Specific Control Register (FSC) bit definitions.
142 FSC_DBRST_MASK = 0x00070000,
143 FSC_DBRST_256 = 0x00000000,
144 FSC_DBRST_512 = 0x00000001,
145 FSC_DBRST_768 = 0x00000002,
146 FSC_DBRST_1024 = 0x00000003,
147 FSC_DBL_MASK = 0x00180000,
148 FSC_DBL_DBRST = 0x00000000,
149 FSC_DBL_MAX_PLD = 0x00000008,
150 FSC_DBL_MAX_BRST = 0x00000010,
151 FSC_DBL_128_BYTES = 0x00000018,
153 FSC_EPC_MASK = 0x00c00000,
154 FSC_EPC_INBOUND = (1 << 6),
155 FSC_EPC_OUTBOUND = (1 << 7),
156 FSC_VM_PAGESIZE_MASK = 0x07000000,
157 FSC_VM_PAGE_2K = 0x00000100,
158 FSC_VM_PAGE_4K = 0x00000200,
159 FSC_VM_PAGE_8K = 0x00000300,
160 FSC_VM_PAGE_64K = 0x00000600,
168 * Host Command Status Register (CSR) bit definitions.
171 CSR_ERR_STS_MASK = 0x0000003f,
173 * There are no valued defined as of edit #15.
178 CSR_CMD_PARM_SHIFT = 22,
179 CSR_CMD_NOP = 0x00000000,
180 CSR_CMD_SET_RST = 0x10000000,
181 CSR_CMD_CLR_RST = 0x20000000,
182 CSR_CMD_SET_PAUSE = 0x30000000,
183 CSR_CMD_CLR_PAUSE = 0x40000000,
184 CSR_CMD_SET_H2R_INT = 0x50000000,
185 CSR_CMD_CLR_H2R_INT = 0x60000000,
186 CSR_CMD_PAR_EN = 0x70000000,
187 CSR_CMD_SET_BAD_PAR = 0x80000000,
188 CSR_CMD_CLR_BAD_PAR = 0x90000000,
189 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
193 * Configuration Register (CFG) bit definitions.
204 CFG_Q_MASK = 0x7f000000,
208 * Status Register (STS) bit definitions.
217 STS_FUNC_ID_MASK = 0x000000c0,
218 STS_FUNC_ID_SHIFT = 6,
227 * Interrupt Enable Register (INTR_EN) bit definitions.
230 INTR_EN_INTR_MASK = 0x007f0000,
231 INTR_EN_TYPE_MASK = 0x03000000,
232 INTR_EN_TYPE_ENABLE = 0x00000100,
233 INTR_EN_TYPE_DISABLE = 0x00000200,
234 INTR_EN_TYPE_READ = 0x00000300,
235 INTR_EN_IHD = (1 << 13),
236 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
237 INTR_EN_EI = (1 << 14),
238 INTR_EN_EN = (1 << 15),
242 * Interrupt Mask Register (INTR_MASK) bit definitions.
245 INTR_MASK_PI = (1 << 0),
246 INTR_MASK_HL0 = (1 << 1),
247 INTR_MASK_LH0 = (1 << 2),
248 INTR_MASK_HL1 = (1 << 3),
249 INTR_MASK_LH1 = (1 << 4),
250 INTR_MASK_SE = (1 << 5),
251 INTR_MASK_LSC = (1 << 6),
252 INTR_MASK_MC = (1 << 7),
253 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
257 * Register (REV_ID) bit definitions.
260 REV_ID_MASK = 0x0000000f,
261 REV_ID_NICROLL_SHIFT = 0,
262 REV_ID_NICREV_SHIFT = 4,
263 REV_ID_XGROLL_SHIFT = 8,
264 REV_ID_XGREV_SHIFT = 12,
265 REV_ID_CHIPREV_SHIFT = 28,
269 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
272 FRC_ECC_ERR_VW = (1 << 12),
273 FRC_ECC_ERR_VB = (1 << 13),
274 FRC_ECC_ERR_NI = (1 << 14),
275 FRC_ECC_ERR_NO = (1 << 15),
276 FRC_ECC_PFE_SHIFT = 16,
277 FRC_ECC_ERR_DO = (1 << 18),
278 FRC_ECC_P14 = (1 << 19),
282 * Error Status Register (ERR_STS) bit definitions.
285 ERR_STS_NOF = (1 << 0),
286 ERR_STS_NIF = (1 << 1),
287 ERR_STS_DRP = (1 << 2),
288 ERR_STS_XGP = (1 << 3),
289 ERR_STS_FOU = (1 << 4),
290 ERR_STS_FOC = (1 << 5),
291 ERR_STS_FOF = (1 << 6),
292 ERR_STS_FIU = (1 << 7),
293 ERR_STS_FIC = (1 << 8),
294 ERR_STS_FIF = (1 << 9),
295 ERR_STS_MOF = (1 << 10),
296 ERR_STS_TA = (1 << 11),
297 ERR_STS_MA = (1 << 12),
298 ERR_STS_MPE = (1 << 13),
299 ERR_STS_SCE = (1 << 14),
300 ERR_STS_STE = (1 << 15),
301 ERR_STS_FOW = (1 << 16),
302 ERR_STS_UE = (1 << 17),
303 ERR_STS_MCH = (1 << 26),
304 ERR_STS_LOC_SHIFT = 27,
308 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
311 RAM_DBG_ADDR_FW = (1 << 30),
312 RAM_DBG_ADDR_FR = (1 << 31),
316 * Semaphore Register (SEM) bit definitions.
321 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
326 SEM_XGMAC0_SHIFT = 0,
327 SEM_XGMAC1_SHIFT = 2,
329 SEM_MAC_ADDR_SHIFT = 6,
331 SEM_PROBE_SHIFT = 10,
332 SEM_RT_IDX_SHIFT = 12,
333 SEM_PROC_REG_SHIFT = 14,
334 SEM_XGMAC0_MASK = 0x00030000,
335 SEM_XGMAC1_MASK = 0x000c0000,
336 SEM_ICB_MASK = 0x00300000,
337 SEM_MAC_ADDR_MASK = 0x00c00000,
338 SEM_FLASH_MASK = 0x03000000,
339 SEM_PROBE_MASK = 0x0c000000,
340 SEM_RT_IDX_MASK = 0x30000000,
341 SEM_PROC_REG_MASK = 0xc0000000,
345 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
348 XGMAC_ADDR_RDY = (1 << 31),
349 XGMAC_ADDR_R = (1 << 30),
350 XGMAC_ADDR_XME = (1 << 29),
352 /* XGMAC control registers */
353 PAUSE_SRC_LO = 0x00000100,
354 PAUSE_SRC_HI = 0x00000104,
355 GLOBAL_CFG = 0x00000108,
356 GLOBAL_CFG_RESET = (1 << 0),
357 GLOBAL_CFG_JUMBO = (1 << 6),
358 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
359 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
361 TX_CFG_RESET = (1 << 0),
362 TX_CFG_EN = (1 << 1),
363 TX_CFG_PREAM = (1 << 2),
365 RX_CFG_RESET = (1 << 0),
366 RX_CFG_EN = (1 << 1),
367 RX_CFG_PREAM = (1 << 2),
368 FLOW_CTL = 0x0000011c,
369 PAUSE_OPCODE = 0x00000120,
370 PAUSE_TIMER = 0x00000124,
371 PAUSE_FRM_DEST_LO = 0x00000128,
372 PAUSE_FRM_DEST_HI = 0x0000012c,
373 MAC_TX_PARAMS = 0x00000134,
374 MAC_TX_PARAMS_JUMBO = (1 << 31),
375 MAC_TX_PARAMS_SIZE_SHIFT = 16,
376 MAC_RX_PARAMS = 0x00000138,
377 MAC_SYS_INT = 0x00000144,
378 MAC_SYS_INT_MASK = 0x00000148,
379 MAC_MGMT_INT = 0x0000014c,
380 MAC_MGMT_IN_MASK = 0x00000150,
381 EXT_ARB_MODE = 0x000001fc,
383 /* XGMAC TX statistics registers */
384 TX_PKTS = 0x00000200,
385 TX_BYTES = 0x00000208,
386 TX_MCAST_PKTS = 0x00000210,
387 TX_BCAST_PKTS = 0x00000218,
388 TX_UCAST_PKTS = 0x00000220,
389 TX_CTL_PKTS = 0x00000228,
390 TX_PAUSE_PKTS = 0x00000230,
391 TX_64_PKT = 0x00000238,
392 TX_65_TO_127_PKT = 0x00000240,
393 TX_128_TO_255_PKT = 0x00000248,
394 TX_256_511_PKT = 0x00000250,
395 TX_512_TO_1023_PKT = 0x00000258,
396 TX_1024_TO_1518_PKT = 0x00000260,
397 TX_1519_TO_MAX_PKT = 0x00000268,
398 TX_UNDERSIZE_PKT = 0x00000270,
399 TX_OVERSIZE_PKT = 0x00000278,
401 /* XGMAC statistics control registers */
402 RX_HALF_FULL_DET = 0x000002a0,
403 TX_HALF_FULL_DET = 0x000002a4,
404 RX_OVERFLOW_DET = 0x000002a8,
405 TX_OVERFLOW_DET = 0x000002ac,
406 RX_HALF_FULL_MASK = 0x000002b0,
407 TX_HALF_FULL_MASK = 0x000002b4,
408 RX_OVERFLOW_MASK = 0x000002b8,
409 TX_OVERFLOW_MASK = 0x000002bc,
410 STAT_CNT_CTL = 0x000002c0,
411 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
412 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
413 AUX_RX_HALF_FULL_DET = 0x000002d0,
414 AUX_TX_HALF_FULL_DET = 0x000002d4,
415 AUX_RX_OVERFLOW_DET = 0x000002d8,
416 AUX_TX_OVERFLOW_DET = 0x000002dc,
417 AUX_RX_HALF_FULL_MASK = 0x000002f0,
418 AUX_TX_HALF_FULL_MASK = 0x000002f4,
419 AUX_RX_OVERFLOW_MASK = 0x000002f8,
420 AUX_TX_OVERFLOW_MASK = 0x000002fc,
422 /* XGMAC RX statistics registers */
423 RX_BYTES = 0x00000300,
424 RX_BYTES_OK = 0x00000308,
425 RX_PKTS = 0x00000310,
426 RX_PKTS_OK = 0x00000318,
427 RX_BCAST_PKTS = 0x00000320,
428 RX_MCAST_PKTS = 0x00000328,
429 RX_UCAST_PKTS = 0x00000330,
430 RX_UNDERSIZE_PKTS = 0x00000338,
431 RX_OVERSIZE_PKTS = 0x00000340,
432 RX_JABBER_PKTS = 0x00000348,
433 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
434 RX_DROP_EVENTS = 0x00000358,
435 RX_FCERR_PKTS = 0x00000360,
436 RX_ALIGN_ERR = 0x00000368,
437 RX_SYMBOL_ERR = 0x00000370,
438 RX_MAC_ERR = 0x00000378,
439 RX_CTL_PKTS = 0x00000380,
440 RX_PAUSE_PKTS = 0x00000388,
441 RX_64_PKTS = 0x00000390,
442 RX_65_TO_127_PKTS = 0x00000398,
443 RX_128_255_PKTS = 0x000003a0,
444 RX_256_511_PKTS = 0x000003a8,
445 RX_512_TO_1023_PKTS = 0x000003b0,
446 RX_1024_TO_1518_PKTS = 0x000003b8,
447 RX_1519_TO_MAX_PKTS = 0x000003c0,
448 RX_LEN_ERR_PKTS = 0x000003c8,
450 /* XGMAC MDIO control registers */
451 MDIO_TX_DATA = 0x00000400,
452 MDIO_RX_DATA = 0x00000410,
453 MDIO_CMD = 0x00000420,
454 MDIO_PHY_ADDR = 0x00000430,
455 MDIO_PORT = 0x00000440,
456 MDIO_STATUS = 0x00000450,
458 /* XGMAC AUX statistics registers */
462 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
465 ETS_QUEUE_SHIFT = 29,
469 ETS_FC_COS_SHIFT = 23,
473 * Flash Address Register (FLASH_ADDR) bit definitions.
476 FLASH_ADDR_RDY = (1 << 31),
477 FLASH_ADDR_R = (1 << 30),
478 FLASH_ADDR_ERR = (1 << 29),
482 * Stop CQ Processing Register (CQ_STOP) bit definitions.
485 CQ_STOP_QUEUE_MASK = (0x007f0000),
486 CQ_STOP_TYPE_MASK = (0x03000000),
487 CQ_STOP_TYPE_START = 0x00000100,
488 CQ_STOP_TYPE_STOP = 0x00000200,
489 CQ_STOP_TYPE_READ = 0x00000300,
490 CQ_STOP_EN = (1 << 15),
494 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
497 MAC_ADDR_IDX_SHIFT = 4,
498 MAC_ADDR_TYPE_SHIFT = 16,
499 MAC_ADDR_TYPE_MASK = 0x000f0000,
500 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
501 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
502 MAC_ADDR_TYPE_VLAN = 0x00020000,
503 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
504 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
505 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
506 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
507 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
508 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
509 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
510 MAC_ADDR_ADR = (1 << 25),
511 MAC_ADDR_RS = (1 << 26),
512 MAC_ADDR_E = (1 << 27),
513 MAC_ADDR_MR = (1 << 30),
514 MAC_ADDR_MW = (1 << 31),
515 MAX_MULTICAST_ENTRIES = 32,
519 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
522 SPLT_HDR_EP = (1 << 31),
526 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
529 FC_RCV_CFG_ECT = (1 << 15),
530 FC_RCV_CFG_DFH = (1 << 20),
531 FC_RCV_CFG_DVF = (1 << 21),
532 FC_RCV_CFG_RCE = (1 << 27),
533 FC_RCV_CFG_RFE = (1 << 28),
534 FC_RCV_CFG_TEE = (1 << 29),
535 FC_RCV_CFG_TCE = (1 << 30),
536 FC_RCV_CFG_TFE = (1 << 31),
540 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
543 NIC_RCV_CFG_PPE = (1 << 0),
544 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
545 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
546 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
547 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
548 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
549 NIC_RCV_CFG_RV = (1 << 3),
550 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
551 NIC_RCV_CFG_DFQ_SHIFT = 8,
552 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
556 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
559 MGMT_RCV_CFG_ARP = (1 << 0),
560 MGMT_RCV_CFG_DHC = (1 << 1),
561 MGMT_RCV_CFG_DHS = (1 << 2),
562 MGMT_RCV_CFG_NP = (1 << 3),
563 MGMT_RCV_CFG_I6N = (1 << 4),
564 MGMT_RCV_CFG_I6R = (1 << 5),
565 MGMT_RCV_CFG_DH6 = (1 << 6),
566 MGMT_RCV_CFG_UD1 = (1 << 7),
567 MGMT_RCV_CFG_UD0 = (1 << 8),
568 MGMT_RCV_CFG_BCT = (1 << 9),
569 MGMT_RCV_CFG_MCT = (1 << 10),
570 MGMT_RCV_CFG_DM = (1 << 11),
571 MGMT_RCV_CFG_RM = (1 << 12),
572 MGMT_RCV_CFG_STL = (1 << 13),
573 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
574 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
575 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
576 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
577 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
581 * Routing Index Register (RT_IDX) bit definitions.
584 RT_IDX_IDX_SHIFT = 8,
585 RT_IDX_TYPE_MASK = 0x000f0000,
586 RT_IDX_TYPE_RT = 0x00000000,
587 RT_IDX_TYPE_RT_INV = 0x00010000,
588 RT_IDX_TYPE_NICQ = 0x00020000,
589 RT_IDX_TYPE_NICQ_INV = 0x00030000,
590 RT_IDX_DST_MASK = 0x00700000,
591 RT_IDX_DST_RSS = 0x00000000,
592 RT_IDX_DST_CAM_Q = 0x00100000,
593 RT_IDX_DST_COS_Q = 0x00200000,
594 RT_IDX_DST_DFLT_Q = 0x00300000,
595 RT_IDX_DST_DEST_Q = 0x00400000,
596 RT_IDX_RS = (1 << 26),
597 RT_IDX_E = (1 << 27),
598 RT_IDX_MR = (1 << 30),
599 RT_IDX_MW = (1 << 31),
601 /* Nic Queue format - type 2 bits */
602 RT_IDX_BCAST = (1 << 0),
603 RT_IDX_MCAST = (1 << 1),
604 RT_IDX_MCAST_MATCH = (1 << 2),
605 RT_IDX_MCAST_REG_MATCH = (1 << 3),
606 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
607 RT_IDX_FC_MACH = (1 << 5),
608 RT_IDX_ETH_FCOE = (1 << 6),
609 RT_IDX_CAM_HIT = (1 << 7),
610 RT_IDX_CAM_BIT0 = (1 << 8),
611 RT_IDX_CAM_BIT1 = (1 << 9),
612 RT_IDX_VLAN_TAG = (1 << 10),
613 RT_IDX_VLAN_MATCH = (1 << 11),
614 RT_IDX_VLAN_FILTER = (1 << 12),
615 RT_IDX_ETH_SKIP1 = (1 << 13),
616 RT_IDX_ETH_SKIP2 = (1 << 14),
617 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
618 RT_IDX_802_3 = (1 << 16),
619 RT_IDX_LLDP = (1 << 17),
620 RT_IDX_UNUSED018 = (1 << 18),
621 RT_IDX_UNUSED019 = (1 << 19),
622 RT_IDX_UNUSED20 = (1 << 20),
623 RT_IDX_UNUSED21 = (1 << 21),
624 RT_IDX_ERR = (1 << 22),
625 RT_IDX_VALID = (1 << 23),
626 RT_IDX_TU_CSUM_ERR = (1 << 24),
627 RT_IDX_IP_CSUM_ERR = (1 << 25),
628 RT_IDX_MAC_ERR = (1 << 26),
629 RT_IDX_RSS_TCP6 = (1 << 27),
630 RT_IDX_RSS_TCP4 = (1 << 28),
631 RT_IDX_RSS_IPV6 = (1 << 29),
632 RT_IDX_RSS_IPV4 = (1 << 30),
633 RT_IDX_RSS_MATCH = (1 << 31),
635 /* Hierarchy for the NIC Queue Mask */
636 RT_IDX_ALL_ERR_SLOT = 0,
637 RT_IDX_MAC_ERR_SLOT = 0,
638 RT_IDX_IP_CSUM_ERR_SLOT = 1,
639 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
640 RT_IDX_BCAST_SLOT = 3,
641 RT_IDX_MCAST_MATCH_SLOT = 4,
642 RT_IDX_ALLMULTI_SLOT = 5,
643 RT_IDX_UNUSED6_SLOT = 6,
644 RT_IDX_UNUSED7_SLOT = 7,
645 RT_IDX_RSS_MATCH_SLOT = 8,
646 RT_IDX_RSS_IPV4_SLOT = 8,
647 RT_IDX_RSS_IPV6_SLOT = 9,
648 RT_IDX_RSS_TCP4_SLOT = 10,
649 RT_IDX_RSS_TCP6_SLOT = 11,
650 RT_IDX_CAM_HIT_SLOT = 12,
651 RT_IDX_UNUSED013 = 13,
652 RT_IDX_UNUSED014 = 14,
653 RT_IDX_PROMISCUOUS_SLOT = 15,
654 RT_IDX_MAX_SLOTS = 16,
658 * Control Register Set Map
661 PROC_ADDR = 0, /* Use semaphore */
662 PROC_DATA = 0x04, /* Use semaphore */
668 ICB_RID = 0x1c, /* Use semaphore */
669 ICB_L = 0x20, /* Use semaphore */
670 ICB_H = 0x24, /* Use semaphore */
687 GPIO_1 = 0x68, /* Use semaphore */
688 GPIO_2 = 0x6c, /* Use semaphore */
689 GPIO_3 = 0x70, /* Use semaphore */
691 XGMAC_ADDR = 0x78, /* Use semaphore */
692 XGMAC_DATA = 0x7c, /* Use semaphore */
695 FLASH_ADDR = 0x88, /* Use semaphore */
696 FLASH_DATA = 0x8c, /* Use semaphore */
699 WQ_PAGE_TBL_LO = 0x98,
700 WQ_PAGE_TBL_HI = 0x9c,
701 CQ_PAGE_TBL_LO = 0xa0,
702 CQ_PAGE_TBL_HI = 0xa4,
703 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
704 MAC_ADDR_DATA = 0xac, /* Use semaphore */
710 FC_PAUSE_THRES = 0xc4,
711 NIC_PAUSE_THRES = 0xc8,
721 XG_SERDES_ADDR = 0xf0,
722 XG_SERDES_DATA = 0xf4,
723 PRB_MX_ADDR = 0xf8, /* Use semaphore */
724 PRB_MX_DATA = 0xfc, /* Use semaphore */
731 CAM_OUT_ROUTE_FC = 0,
732 CAM_OUT_ROUTE_NIC = 1,
733 CAM_OUT_FUNC_SHIFT = 2,
734 CAM_OUT_RV = (1 << 4),
735 CAM_OUT_SH = (1 << 15),
736 CAM_OUT_CQ_ID_SHIFT = 5,
740 * Mailbox definitions
743 /* Asynchronous Event Notifications */
744 AEN_SYS_ERR = 0x00008002,
745 AEN_LINK_UP = 0x00008011,
746 AEN_LINK_DOWN = 0x00008012,
747 AEN_IDC_CMPLT = 0x00008100,
748 AEN_IDC_REQ = 0x00008101,
749 AEN_IDC_EXT = 0x00008102,
750 AEN_DCBX_CHG = 0x00008110,
751 AEN_AEN_LOST = 0x00008120,
752 AEN_AEN_SFP_IN = 0x00008130,
753 AEN_AEN_SFP_OUT = 0x00008131,
754 AEN_FW_INIT_DONE = 0x00008400,
755 AEN_FW_INIT_FAIL = 0x00008401,
757 /* Mailbox Command Opcodes. */
758 MB_CMD_NOP = 0x00000000,
759 MB_CMD_EX_FW = 0x00000002,
760 MB_CMD_MB_TEST = 0x00000006,
761 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
762 MB_CMD_ABOUT_FW = 0x00000008,
763 MB_CMD_COPY_RISC_RAM = 0x0000000a,
764 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
765 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
766 MB_CMD_WRITE_RAM = 0x0000000d,
767 MB_CMD_INIT_RISC_RAM = 0x0000000e,
768 MB_CMD_READ_RAM = 0x0000000f,
769 MB_CMD_STOP_FW = 0x00000014,
770 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
771 MB_CMD_WRITE_SFP = 0x00000030,
772 MB_CMD_READ_SFP = 0x00000031,
773 MB_CMD_INIT_FW = 0x00000060,
774 MB_CMD_GET_IFCB = 0x00000061,
775 MB_CMD_GET_FW_STATE = 0x00000069,
776 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
777 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
778 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
780 MB_WOL_MAGIC_PKT = (1 << 1),
781 MB_WOL_FLTR = (1 << 2),
782 MB_WOL_UCAST = (1 << 3),
783 MB_WOL_MCAST = (1 << 4),
784 MB_WOL_BCAST = (1 << 5),
785 MB_WOL_LINK_UP = (1 << 6),
786 MB_WOL_LINK_DOWN = (1 << 7),
787 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
788 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
789 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
790 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
791 MB_CMD_SET_WOL_IMMED = 0x00000115,
792 MB_CMD_PORT_RESET = 0x00000120,
793 MB_CMD_SET_PORT_CFG = 0x00000122,
794 MB_CMD_GET_PORT_CFG = 0x00000123,
795 MB_CMD_GET_LINK_STS = 0x00000124,
797 /* Mailbox Command Status. */
798 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
799 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
800 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
801 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
802 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
803 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
804 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
808 u32 mbox_in[MAILBOX_COUNT];
809 u32 mbox_out[MAILBOX_COUNT];
814 struct flash_params_8012 {
824 /* 8000 device's flash is a different structure
825 * at a different offset in flash.
827 #define FUNC0_FLASH_OFFSET 0x140200
828 #define FUNC1_FLASH_OFFSET 0x140600
830 /* Flash related data structures. */
831 struct flash_params_8000 {
832 u8 dev_id_str[4]; /* "8000" */
852 __le16 subsys_ven_id;
853 __le16 subsys_dev_id;
858 struct flash_params_8012 flash_params_8012;
859 struct flash_params_8000 flash_params_8000;
863 * doorbell space for the rx ring context
865 struct rx_doorbell_context {
866 u32 cnsmr_idx; /* 0x00 */
867 u32 valid; /* 0x04 */
868 u32 reserved[4]; /* 0x08-0x14 */
869 u32 lbq_prod_idx; /* 0x18 */
870 u32 sbq_prod_idx; /* 0x1c */
874 * doorbell space for the tx ring context
876 struct tx_doorbell_context {
877 u32 prod_idx; /* 0x00 */
878 u32 valid; /* 0x04 */
879 u32 reserved[4]; /* 0x08-0x14 */
880 u32 lbq_prod_idx; /* 0x18 */
881 u32 sbq_prod_idx; /* 0x1c */
884 /* DATA STRUCTURES SHARED WITH HARDWARE. */
888 #define TX_DESC_LEN_MASK 0x000fffff
889 #define TX_DESC_C 0x40000000
890 #define TX_DESC_E 0x80000000
891 } __attribute((packed));
894 * IOCB Definitions...
897 #define OPCODE_OB_MAC_IOCB 0x01
898 #define OPCODE_OB_MAC_TSO_IOCB 0x02
899 #define OPCODE_IB_MAC_IOCB 0x20
900 #define OPCODE_IB_MPI_IOCB 0x21
901 #define OPCODE_IB_AE_IOCB 0x3f
903 struct ob_mac_iocb_req {
906 #define OB_MAC_IOCB_REQ_OI 0x01
907 #define OB_MAC_IOCB_REQ_I 0x02
908 #define OB_MAC_IOCB_REQ_D 0x08
909 #define OB_MAC_IOCB_REQ_F 0x10
912 #define OB_MAC_IOCB_DFP 0x02
913 #define OB_MAC_IOCB_V 0x04
916 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
923 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
924 } __attribute((packed));
926 struct ob_mac_iocb_rsp {
929 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
930 #define OB_MAC_IOCB_RSP_I 0x02 /* */
931 #define OB_MAC_IOCB_RSP_E 0x08 /* */
932 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
933 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
934 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
937 #define OB_MAC_IOCB_RSP_B 0x80 /* */
941 } __attribute((packed));
943 struct ob_mac_tso_iocb_req {
946 #define OB_MAC_TSO_IOCB_OI 0x01
947 #define OB_MAC_TSO_IOCB_I 0x02
948 #define OB_MAC_TSO_IOCB_D 0x08
949 #define OB_MAC_TSO_IOCB_IP4 0x40
950 #define OB_MAC_TSO_IOCB_IP6 0x80
952 #define OB_MAC_TSO_IOCB_LSO 0x20
953 #define OB_MAC_TSO_IOCB_UC 0x40
954 #define OB_MAC_TSO_IOCB_TC 0x80
956 #define OB_MAC_TSO_IOCB_IC 0x01
957 #define OB_MAC_TSO_IOCB_DFP 0x02
958 #define OB_MAC_TSO_IOCB_V 0x04
963 __le16 total_hdrs_len;
964 __le16 net_trans_offset;
965 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
968 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
969 } __attribute((packed));
971 struct ob_mac_tso_iocb_rsp {
974 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
975 #define OB_MAC_TSO_IOCB_RSP_I 0x02
976 #define OB_MAC_TSO_IOCB_RSP_E 0x08
977 #define OB_MAC_TSO_IOCB_RSP_S 0x10
978 #define OB_MAC_TSO_IOCB_RSP_L 0x20
979 #define OB_MAC_TSO_IOCB_RSP_P 0x40
982 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
985 __le32 reserved2[13];
986 } __attribute((packed));
988 struct ib_mac_iocb_rsp {
989 u8 opcode; /* 0x20 */
991 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
992 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
993 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
994 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
995 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
996 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
997 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
998 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
999 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1000 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1001 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1002 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1004 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1005 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1006 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1007 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1008 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1009 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1010 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1011 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1012 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1013 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1014 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1015 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1017 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1018 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1019 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1020 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1021 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1022 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1023 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1024 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1025 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1026 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1027 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1028 __le32 data_len; /* */
1029 __le64 data_addr; /* */
1031 __le16 vlan_id; /* 12 bits */
1032 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1033 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1034 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1037 __le32 reserved2[6];
1040 #define IB_MAC_IOCB_RSP_HV 0x20
1041 #define IB_MAC_IOCB_RSP_HS 0x40
1042 #define IB_MAC_IOCB_RSP_HL 0x80
1043 __le32 hdr_len; /* */
1044 __le64 hdr_addr; /* */
1045 } __attribute((packed));
1047 struct ib_ae_iocb_rsp {
1050 #define IB_AE_IOCB_RSP_OI 0x01
1051 #define IB_AE_IOCB_RSP_I 0x02
1053 #define LINK_UP_EVENT 0x00
1054 #define LINK_DOWN_EVENT 0x01
1055 #define CAM_LOOKUP_ERR_EVENT 0x06
1056 #define SOFT_ECC_ERROR_EVENT 0x07
1057 #define MGMT_ERR_EVENT 0x08
1058 #define TEN_GIG_MAC_EVENT 0x09
1059 #define GPI0_H2L_EVENT 0x10
1060 #define GPI0_L2H_EVENT 0x20
1061 #define GPI1_H2L_EVENT 0x11
1062 #define GPI1_L2H_EVENT 0x21
1063 #define PCI_ERR_ANON_BUF_RD 0x40
1065 __le32 reserved[15];
1066 } __attribute((packed));
1069 * These three structures are for generic
1070 * handling of ib and ob iocbs.
1072 struct ql_net_rsp_iocb {
1077 __le32 reserved[14];
1078 } __attribute((packed));
1080 struct net_req_iocb {
1085 __le32 reserved1[30];
1086 } __attribute((packed));
1089 * tx ring initialization control block for chip.
1091 * "Work Queue Initialization Control Block"
1095 #define Q_LEN_V (1 << 4)
1096 #define Q_LEN_CPP_CONT 0x0000
1097 #define Q_LEN_CPP_16 0x0001
1098 #define Q_LEN_CPP_32 0x0002
1099 #define Q_LEN_CPP_64 0x0003
1100 #define Q_LEN_CPP_512 0x0006
1102 #define Q_PRI_SHIFT 1
1103 #define Q_FLAGS_LC 0x1000
1104 #define Q_FLAGS_LB 0x2000
1105 #define Q_FLAGS_LI 0x4000
1106 #define Q_FLAGS_LO 0x8000
1108 #define Q_CQ_ID_RSS_RV 0x8000
1111 __le64 cnsmr_idx_addr;
1112 } __attribute((packed));
1115 * rx ring initialization control block for chip.
1117 * "Completion Queue Initialization Control Block"
1124 #define FLAGS_LV 0x08
1125 #define FLAGS_LS 0x10
1126 #define FLAGS_LL 0x20
1127 #define FLAGS_LI 0x40
1128 #define FLAGS_LC 0x80
1130 #define LEN_V (1 << 4)
1131 #define LEN_CPP_CONT 0x0000
1132 #define LEN_CPP_32 0x0001
1133 #define LEN_CPP_64 0x0002
1134 #define LEN_CPP_128 0x0003
1137 __le64 prod_idx_addr;
1141 __le16 lbq_buf_size;
1142 __le16 lbq_len; /* entry count */
1144 __le16 sbq_buf_size;
1145 __le16 sbq_len; /* entry count */
1146 } __attribute((packed));
1150 #define RSS_L4K 0x80
1152 #define RSS_L6K 0x01
1156 #define RSS_RI4 0x10
1157 #define RSS_RT4 0x20
1158 #define RSS_RI6 0x40
1159 #define RSS_RT6 0x80
1161 __le32 hash_cq_id[256];
1162 __le32 ipv6_hash_key[10];
1163 __le32 ipv4_hash_key[4];
1164 } __attribute((packed));
1166 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1169 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1173 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1174 DECLARE_PCI_UNMAP_LEN(maplen);
1177 struct tx_ring_desc {
1178 struct sk_buff *skb;
1179 struct ob_mac_iocb_req *queue_entry;
1182 struct map_list map[MAX_SKB_FRAGS + 1];
1184 struct tx_ring_desc *next;
1189 struct page *lbq_page;
1190 struct sk_buff *skb;
1194 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1195 DECLARE_PCI_UNMAP_LEN(maplen);
1198 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1204 struct wqicb wqicb; /* structure used to inform chip of new queue */
1205 void *wq_base; /* pci_alloc:virtual addr for tx */
1206 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1207 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1208 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1209 u32 wq_size; /* size in bytes of queue area */
1210 u32 wq_len; /* number of entries in queue */
1211 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1212 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1213 u16 prod_idx; /* current value for prod idx */
1214 u16 cq_id; /* completion (rx) queue for tx completions */
1215 u8 wq_id; /* queue id for this entry */
1217 struct tx_ring_desc *q; /* descriptor list for the queue */
1219 atomic_t tx_count; /* counts down for every outstanding IO */
1220 atomic_t queue_stopped; /* Turns queue off when full. */
1221 struct delayed_work tx_work;
1222 struct ql_adapter *qdev;
1226 * Type of inbound queue.
1229 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1230 TX_Q = 3, /* Handles outbound completions. */
1231 RX_Q = 4, /* Handles inbound completions. */
1235 struct cqicb cqicb; /* The chip's completion queue init control block. */
1237 /* Completion queue elements. */
1239 dma_addr_t cq_base_dma;
1243 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1244 dma_addr_t prod_idx_sh_reg_dma;
1245 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1246 u32 cnsmr_idx; /* current sw idx */
1247 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1248 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1250 /* Large buffer queue elements. */
1251 u32 lbq_len; /* entry count */
1252 u32 lbq_size; /* size in bytes of queue */
1255 dma_addr_t lbq_base_dma;
1256 void *lbq_base_indirect;
1257 dma_addr_t lbq_base_indirect_dma;
1258 struct bq_desc *lbq; /* array of control blocks */
1259 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1260 u32 lbq_prod_idx; /* current sw prod idx */
1261 u32 lbq_curr_idx; /* next entry we expect */
1262 u32 lbq_clean_idx; /* beginning of new descs */
1263 u32 lbq_free_cnt; /* free buffer desc cnt */
1265 /* Small buffer queue elements. */
1266 u32 sbq_len; /* entry count */
1267 u32 sbq_size; /* size in bytes of queue */
1270 dma_addr_t sbq_base_dma;
1271 void *sbq_base_indirect;
1272 dma_addr_t sbq_base_indirect_dma;
1273 struct bq_desc *sbq; /* array of control blocks */
1274 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1275 u32 sbq_prod_idx; /* current sw prod idx */
1276 u32 sbq_curr_idx; /* next entry we expect */
1277 u32 sbq_clean_idx; /* beginning of new descs */
1278 u32 sbq_free_cnt; /* free buffer desc cnt */
1280 /* Misc. handler elements. */
1281 u32 type; /* Type of queue, tx, rx, or default. */
1282 u32 irq; /* Which vector this ring is assigned. */
1283 u32 cpu; /* Which CPU this should run on. */
1284 char name[IFNAMSIZ + 5];
1285 struct napi_struct napi;
1286 struct delayed_work rx_work;
1288 struct ql_adapter *qdev;
1292 * RSS Initialization Control Block
1300 * These stats come from offset 200h to 278h
1301 * in the XGMAC register.
1311 u64 tx_65_to_127_pkt;
1312 u64 tx_128_to_255_pkt;
1314 u64 tx_512_to_1023_pkt;
1315 u64 tx_1024_to_1518_pkt;
1316 u64 tx_1519_to_max_pkt;
1317 u64 tx_undersize_pkt;
1318 u64 tx_oversize_pkt;
1321 * These stats come from offset 300h to 3C8h
1322 * in the XGMAC register.
1331 u64 rx_undersize_pkts;
1332 u64 rx_oversize_pkts;
1334 u64 rx_undersize_fcerr_pkts;
1343 u64 rx_65_to_127_pkts;
1344 u64 rx_128_255_pkts;
1345 u64 rx_256_511_pkts;
1346 u64 rx_512_to_1023_pkts;
1347 u64 rx_1024_to_1518_pkts;
1348 u64 rx_1519_to_max_pkts;
1349 u64 rx_len_err_pkts;
1353 * intr_context structure is used during initialization
1354 * to hook the interrupts. It is also used in a single
1355 * irq environment as a context to the ISR.
1357 struct intr_context {
1358 struct ql_adapter *qdev;
1361 u32 intr_en_mask; /* value/mask used to enable this intr */
1362 u32 intr_dis_mask; /* value/mask used to disable this intr */
1363 u32 intr_read_mask; /* value/mask used to read this intr */
1364 char name[IFNAMSIZ * 2];
1365 atomic_t irq_cnt; /* irq_cnt is used in single vector
1366 * environment. It's incremented for each
1367 * irq handler that is scheduled. When each
1368 * handler finishes it decrements irq_cnt and
1369 * enables interrupts if it's zero. */
1370 irq_handler_t handler;
1373 /* adapter flags definitions. */
1375 QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */
1376 QL_LEGACY_ENABLED = (1 << 3),
1377 QL_MSI_ENABLED = (1 << 3),
1378 QL_MSIX_ENABLED = (1 << 4),
1379 QL_DMA64 = (1 << 5),
1380 QL_PROMISCUOUS = (1 << 6),
1381 QL_ALLMULTI = (1 << 7),
1382 QL_PORT_CFG = (1 << 8),
1383 QL_CAM_RT_SET = (1 << 9),
1386 /* link_status bit definitions */
1388 STS_LOOPBACK_MASK = 0x00000700,
1389 STS_LOOPBACK_PCS = 0x00000100,
1390 STS_LOOPBACK_HSS = 0x00000200,
1391 STS_LOOPBACK_EXT = 0x00000300,
1392 STS_PAUSE_MASK = 0x000000c0,
1393 STS_PAUSE_STD = 0x00000040,
1394 STS_PAUSE_PRI = 0x00000080,
1395 STS_SPEED_MASK = 0x00000038,
1396 STS_SPEED_100Mb = 0x00000000,
1397 STS_SPEED_1Gb = 0x00000008,
1398 STS_SPEED_10Gb = 0x00000010,
1399 STS_LINK_TYPE_MASK = 0x00000007,
1400 STS_LINK_TYPE_XFI = 0x00000001,
1401 STS_LINK_TYPE_XAUI = 0x00000002,
1402 STS_LINK_TYPE_XFI_BP = 0x00000003,
1403 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1404 STS_LINK_TYPE_10GBASET = 0x00000005,
1407 /* link_config bit definitions */
1409 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1410 CFG_PAUSE_MASK = 0x00000060,
1411 CFG_PAUSE_STD = 0x00000020,
1412 CFG_PAUSE_PRI = 0x00000040,
1413 CFG_DCBX = 0x00000010,
1414 CFG_LOOPBACK_MASK = 0x00000007,
1415 CFG_LOOPBACK_PCS = 0x00000002,
1416 CFG_LOOPBACK_HSS = 0x00000004,
1417 CFG_LOOPBACK_EXT = 0x00000006,
1418 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
1421 struct nic_operations {
1423 int (*get_flash) (struct ql_adapter *);
1424 int (*port_initialize) (struct ql_adapter *);
1428 * The main Adapter structure definition.
1429 * This structure has all fields relevant to the hardware.
1433 unsigned long flags;
1436 struct nic_stats nic_stats;
1438 struct vlan_group *vlgrp;
1440 /* PCI Configuration information for this device */
1441 struct pci_dev *pdev;
1442 struct net_device *ndev; /* Parent NET device */
1444 /* Hardware information */
1447 u32 func; /* PCI function for this adapter */
1448 u32 alt_func; /* PCI function for alternate adapter */
1449 u32 port; /* Port number this adapter */
1451 spinlock_t adapter_lock;
1453 spinlock_t stats_lock;
1455 /* PCI Bus Relative Register Addresses */
1456 void __iomem *reg_base;
1457 void __iomem *doorbell_area;
1458 u32 doorbell_area_size;
1462 /* Page for Shadow Registers */
1463 void *rx_ring_shadow_reg_area;
1464 dma_addr_t rx_ring_shadow_reg_dma;
1465 void *tx_ring_shadow_reg_area;
1466 dma_addr_t tx_ring_shadow_reg_dma;
1470 struct mbox_params idc_mbc;
1471 struct mutex mpi_mutex;
1476 struct msix_entry *msi_x_entry;
1477 struct intr_context intr_context[MAX_RX_RINGS];
1479 int tx_ring_count; /* One per online CPU. */
1480 u32 rss_ring_first_cq_id;/* index of first inbound (rss) rx_ring */
1481 u32 rss_ring_count; /* One per online CPU. */
1484 * one default queue +
1485 * (CPU count * outbound completion rx_ring) +
1486 * (CPU count * inbound (RSS) completion rx_ring)
1492 struct rx_ring rx_ring[MAX_RX_RINGS];
1493 struct tx_ring tx_ring[MAX_TX_RINGS];
1496 u32 default_rx_queue;
1498 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1499 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1500 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1501 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1510 union flash_params flash;
1512 struct net_device_stats stats;
1513 struct workqueue_struct *q_workqueue;
1514 struct workqueue_struct *workqueue;
1515 struct delayed_work asic_reset_work;
1516 struct delayed_work mpi_reset_work;
1517 struct delayed_work mpi_work;
1518 struct delayed_work mpi_port_cfg_work;
1519 struct delayed_work mpi_idc_work;
1520 struct completion ide_completion;
1521 struct nic_operations *nic_ops;
1526 * Typical Register accessor for memory mapped device.
1528 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1530 return readl(qdev->reg_base + reg);
1534 * Typical Register accessor for memory mapped device.
1536 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1538 writel(val, qdev->reg_base + reg);
1542 * Doorbell Registers:
1543 * Doorbell registers are virtual registers in the PCI memory space.
1544 * The space is allocated by the chip during PCI initialization. The
1545 * device driver finds the doorbell address in BAR 3 in PCI config space.
1546 * The registers are used to control outbound and inbound queues. For
1547 * example, the producer index for an outbound queue. Each queue uses
1548 * 1 4k chunk of memory. The lower half of the space is for outbound
1549 * queues. The upper half is for inbound queues.
1551 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1559 * Outbound queues have a consumer index that is maintained by the chip.
1560 * Inbound queues have a producer index that is maintained by the chip.
1561 * For lower overhead, these registers are "shadowed" to host memory
1562 * which allows the device driver to track the queue progress without
1563 * PCI reads. When an entry is placed on an inbound queue, the chip will
1564 * update the relevant index register and then copy the value to the
1565 * shadow register in host memory.
1567 static inline u32 ql_read_sh_reg(__le32 *addr)
1570 reg = le32_to_cpu(*addr);
1575 extern char qlge_driver_name[];
1576 extern const char qlge_driver_version[];
1577 extern const struct ethtool_ops qlge_ethtool_ops;
1579 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1580 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1581 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1582 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1584 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1585 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1587 void ql_queue_fw_error(struct ql_adapter *qdev);
1588 void ql_mpi_work(struct work_struct *work);
1589 void ql_mpi_reset_work(struct work_struct *work);
1590 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1591 void ql_queue_asic_error(struct ql_adapter *qdev);
1592 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
1593 void ql_set_ethtool_ops(struct net_device *ndev);
1594 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1595 void ql_mpi_idc_work(struct work_struct *work);
1596 void ql_mpi_port_cfg_work(struct work_struct *work);
1597 int ql_mb_get_fw_state(struct ql_adapter *qdev);
1598 int ql_cam_route_initialize(struct ql_adapter *qdev);
1599 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1600 int ql_mb_about_fw(struct ql_adapter *qdev);
1607 /* #define QL_IB_DUMP */
1608 /* #define QL_OB_DUMP */
1612 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1613 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1614 extern void ql_dump_regs(struct ql_adapter *qdev);
1615 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1616 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1617 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1619 #define QL_DUMP_REGS(qdev)
1620 #define QL_DUMP_ROUTE(qdev)
1621 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1625 extern void ql_dump_stat(struct ql_adapter *qdev);
1626 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1628 #define QL_DUMP_STAT(qdev)
1632 extern void ql_dump_qdev(struct ql_adapter *qdev);
1633 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1635 #define QL_DUMP_QDEV(qdev)
1639 extern void ql_dump_wqicb(struct wqicb *wqicb);
1640 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1641 extern void ql_dump_ricb(struct ricb *ricb);
1642 extern void ql_dump_cqicb(struct cqicb *cqicb);
1643 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1644 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1645 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1646 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1647 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1648 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1649 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1650 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1651 ql_dump_hw_cb(qdev, size, bit, q_id)
1653 #define QL_DUMP_RICB(ricb)
1654 #define QL_DUMP_WQICB(wqicb)
1655 #define QL_DUMP_TX_RING(tx_ring)
1656 #define QL_DUMP_CQICB(cqicb)
1657 #define QL_DUMP_RX_RING(rx_ring)
1658 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1662 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1663 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1664 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1665 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1666 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1668 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1669 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1673 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1674 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1676 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1680 extern void ql_dump_all(struct ql_adapter *qdev);
1681 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1683 #define QL_DUMP_ALL(qdev)
1686 #endif /* _QLGE_H_ */