drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/delay.h>
  35 #include <linux/mm.h>
  36
  37 #include "qla3xxx.h"
  38
  39 #define DRV_NAME        "qla3xxx"
  40 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  41 #define DRV_VERSION     "v2.03.00-k5"
  42 #define PFX             DRV_NAME " "
  43
  44 static const char ql3xxx_driver_name[] = DRV_NAME;
  45 static const char ql3xxx_driver_version[] = DRV_VERSION;
  46
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  49 MODULE_LICENSE("GPL");
  50 MODULE_VERSION(DRV_VERSION);
  51
  52 static const u32 default_msg
  53     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  54     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  55
  56 static int debug = -1;          /* defaults above */
  57 module_param(debug, int, 0);
  58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  59
  60 static int msi;
  61 module_param(msi, int, 0);
  62 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  63
  64 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  67         /* required last entry */
  68         {0,}
  69 };
  70
  71 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  72
  73 /*
  74  *  These are the known PHY's which are used
  75  */
  76 typedef enum {
  77    PHY_TYPE_UNKNOWN   = 0,
  78    PHY_VITESSE_VSC8211,
  79    PHY_AGERE_ET1011C,
  80    MAX_PHY_DEV_TYPES
  81 } PHY_DEVICE_et;
  82
  83 typedef struct {
  84         PHY_DEVICE_et phyDevice;
  85         u32             phyIdOUI;
  86         u16             phyIdModel;
  87         char            *name;
  88 } PHY_DEVICE_INFO_t;
  89
  90 static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
  91         {{PHY_TYPE_UNKNOWN,    0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
  92          {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
  93          {PHY_AGERE_ET1011C,   0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
  94 };
  95
  96
  97 /*
  98  * Caller must take hw_lock.
  99  */
 100 static int ql_sem_spinlock(struct ql3_adapter *qdev,
 101                             u32 sem_mask, u32 sem_bits)
 102 {
 103         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 104         u32 value;
 105         unsigned int seconds = 3;
 106
 107         do {
 108                 writel((sem_mask | sem_bits),
 109                        &port_regs->CommonRegs.semaphoreReg);
 110                 value = readl(&port_regs->CommonRegs.semaphoreReg);
 111                 if ((value & (sem_mask >> 16)) == sem_bits)
 112                         return 0;
 113                 ssleep(1);
 114         } while(--seconds);
 115         return -1;
 116 }
 117
 118 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
 119 {
 120         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 121         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
 122         readl(&port_regs->CommonRegs.semaphoreReg);
 123 }
 124
 125 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 126 {
 127         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 128         u32 value;
 129
 130         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 131         value = readl(&port_regs->CommonRegs.semaphoreReg);
 132         return ((value & (sem_mask >> 16)) == sem_bits);
 133 }
 134
 135 /*
 136  * Caller holds hw_lock.
 137  */
 138 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 139 {
 140         int i = 0;
 141
 142         while (1) {
 143                 if (!ql_sem_lock(qdev,
 144                                  QL_DRVR_SEM_MASK,
 145                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 146                                   * 2) << 1)) {
 147                         if (i < 10) {
 148                                 ssleep(1);
 149                                 i++;
 150                         } else {
 151                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 152                                        "driver lock...\n",
 153                                        qdev->ndev->name);
 154                                 return 0;
 155                         }
 156                 } else {
 157                         printk(KERN_DEBUG PFX
 158                                "%s: driver lock acquired.\n",
 159                                qdev->ndev->name);
 160                         return 1;
 161                 }
 162         }
 163 }
 164
 165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 166 {
 167         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 168
 169         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 170                         &port_regs->CommonRegs.ispControlStatus);
 171         readl(&port_regs->CommonRegs.ispControlStatus);
 172         qdev->current_page = page;
 173 }
 174
 175 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 176                               u32 __iomem * reg)
 177 {
 178         u32 value;
 179         unsigned long hw_flags;
 180
 181         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 182         value = readl(reg);
 183         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 184
 185         return value;
 186 }
 187
 188 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 189                               u32 __iomem * reg)
 190 {
 191         return readl(reg);
 192 }
 193
 194 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 195 {
 196         u32 value;
 197         unsigned long hw_flags;
 198
 199         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 200
 201         if (qdev->current_page != 0)
 202                 ql_set_register_page(qdev,0);
 203         value = readl(reg);
 204
 205         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 206         return value;
 207 }
 208
 209 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 210 {
 211         if (qdev->current_page != 0)
 212                 ql_set_register_page(qdev,0);
 213         return readl(reg);
 214 }
 215
 216 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 217                                 u32 __iomem *reg, u32 value)
 218 {
 219         unsigned long hw_flags;
 220
 221         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 222         writel(value, reg);
 223         readl(reg);
 224         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 225         return;
 226 }
 227
 228 static void ql_write_common_reg(struct ql3_adapter *qdev,
 229                                 u32 __iomem *reg, u32 value)
 230 {
 231         writel(value, reg);
 232         readl(reg);
 233         return;
 234 }
 235
 236 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 237                                 u32 __iomem *reg, u32 value)
 238 {
 239         writel(value, reg);
 240         readl(reg);
 241         udelay(1);
 242         return;
 243 }
 244
 245 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 246                                u32 __iomem *reg, u32 value)
 247 {
 248         if (qdev->current_page != 0)
 249                 ql_set_register_page(qdev,0);
 250         writel(value, reg);
 251         readl(reg);
 252         return;
 253 }
 254
 255 /*
 256  * Caller holds hw_lock. Only called during init.
 257  */
 258 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 259                                u32 __iomem *reg, u32 value)
 260 {
 261         if (qdev->current_page != 1)
 262                 ql_set_register_page(qdev,1);
 263         writel(value, reg);
 264         readl(reg);
 265         return;
 266 }
 267
 268 /*
 269  * Caller holds hw_lock. Only called during init.
 270  */
 271 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 272                                u32 __iomem *reg, u32 value)
 273 {
 274         if (qdev->current_page != 2)
 275                 ql_set_register_page(qdev,2);
 276         writel(value, reg);
 277         readl(reg);
 278         return;
 279 }
 280
 281 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 282 {
 283         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 284
 285         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 286                             (ISP_IMR_ENABLE_INT << 16));
 287
 288 }
 289
 290 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 291 {
 292         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 293
 294         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 295                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 296
 297 }
 298
 299 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 300                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 301 {
 302         dma_addr_t map;
 303         int err;
 304         lrg_buf_cb->next = NULL;
 305
 306         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 307                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 308         } else {
 309                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 310                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 311         }
 312
 313         if (!lrg_buf_cb->skb) {
 314                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 315                                                    qdev->lrg_buffer_len);
 316                 if (unlikely(!lrg_buf_cb->skb)) {
 317                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 318                                qdev->ndev->name);
 319                         qdev->lrg_buf_skb_check++;
 320                 } else {
 321                         /*
 322                          * We save some space to copy the ethhdr from first
 323                          * buffer
 324                          */
 325                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 326                         map = pci_map_single(qdev->pdev,
 327                                              lrg_buf_cb->skb->data,
 328                                              qdev->lrg_buffer_len -
 329                                              QL_HEADER_SPACE,
 330                                              PCI_DMA_FROMDEVICE);
 331                         err = pci_dma_mapping_error(qdev->pdev, map);
 332                         if(err) {
 333                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
 334                                        qdev->ndev->name, err);
 335                                 dev_kfree_skb(lrg_buf_cb->skb);
 336                                 lrg_buf_cb->skb = NULL;
 337
 338                                 qdev->lrg_buf_skb_check++;
 339                                 return;
 340                         }
 341
 342                         lrg_buf_cb->buf_phy_addr_low =
 343                             cpu_to_le32(LS_64BITS(map));
 344                         lrg_buf_cb->buf_phy_addr_high =
 345                             cpu_to_le32(MS_64BITS(map));
 346                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 347                         pci_unmap_len_set(lrg_buf_cb, maplen,
 348                                           qdev->lrg_buffer_len -
 349                                           QL_HEADER_SPACE);
 350                 }
 351         }
 352
 353         qdev->lrg_buf_free_count++;
 354 }
 355
 356 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 357                                                            *qdev)
 358 {
 359         struct ql_rcv_buf_cb *lrg_buf_cb;
 360
 361         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 362                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 363                         qdev->lrg_buf_free_tail = NULL;
 364                 qdev->lrg_buf_free_count--;
 365         }
 366
 367         return lrg_buf_cb;
 368 }
 369
 370 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 371 static u32 dataBits = EEPROM_NO_DATA_BITS;
 372
 373 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 374 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 375                             unsigned short *value);
 376
 377 /*
 378  * Caller holds hw_lock.
 379  */
 380 static void fm93c56a_select(struct ql3_adapter *qdev)
 381 {
 382         struct ql3xxx_port_registers __iomem *port_regs =
 383                         qdev->mem_map_registers;
 384
 385         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 386         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 387                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 388         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 389                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 390 }
 391
 392 /*
 393  * Caller holds hw_lock.
 394  */
 395 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 396 {
 397         int i;
 398         u32 mask;
 399         u32 dataBit;
 400         u32 previousBit;
 401         struct ql3xxx_port_registers __iomem *port_regs =
 402                         qdev->mem_map_registers;
 403
 404         /* Clock in a zero, then do the start bit */
 405         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 406                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 407                             AUBURN_EEPROM_DO_1);
 408         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 409                             ISP_NVRAM_MASK | qdev->
 410                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 411                             AUBURN_EEPROM_CLK_RISE);
 412         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 413                             ISP_NVRAM_MASK | qdev->
 414                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 415                             AUBURN_EEPROM_CLK_FALL);
 416
 417         mask = 1 << (FM93C56A_CMD_BITS - 1);
 418         /* Force the previous data bit to be different */
 419         previousBit = 0xffff;
 420         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 421                 dataBit =
 422                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 423                 if (previousBit != dataBit) {
 424                         /*
 425                          * If the bit changed, then change the DO state to
 426                          * match
 427                          */
 428                         ql_write_nvram_reg(qdev,
 429                                             &port_regs->CommonRegs.
 430                                             serialPortInterfaceReg,
 431                                             ISP_NVRAM_MASK | qdev->
 432                                             eeprom_cmd_data | dataBit);
 433                         previousBit = dataBit;
 434                 }
 435                 ql_write_nvram_reg(qdev,
 436                                     &port_regs->CommonRegs.
 437                                     serialPortInterfaceReg,
 438                                     ISP_NVRAM_MASK | qdev->
 439                                     eeprom_cmd_data | dataBit |
 440                                     AUBURN_EEPROM_CLK_RISE);
 441                 ql_write_nvram_reg(qdev,
 442                                     &port_regs->CommonRegs.
 443                                     serialPortInterfaceReg,
 444                                     ISP_NVRAM_MASK | qdev->
 445                                     eeprom_cmd_data | dataBit |
 446                                     AUBURN_EEPROM_CLK_FALL);
 447                 cmd = cmd << 1;
 448         }
 449
 450         mask = 1 << (addrBits - 1);
 451         /* Force the previous data bit to be different */
 452         previousBit = 0xffff;
 453         for (i = 0; i < addrBits; i++) {
 454                 dataBit =
 455                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 456                     AUBURN_EEPROM_DO_0;
 457                 if (previousBit != dataBit) {
 458                         /*
 459                          * If the bit changed, then change the DO state to
 460                          * match
 461                          */
 462                         ql_write_nvram_reg(qdev,
 463                                             &port_regs->CommonRegs.
 464                                             serialPortInterfaceReg,
 465                                             ISP_NVRAM_MASK | qdev->
 466                                             eeprom_cmd_data | dataBit);
 467                         previousBit = dataBit;
 468                 }
 469                 ql_write_nvram_reg(qdev,
 470                                     &port_regs->CommonRegs.
 471                                     serialPortInterfaceReg,
 472                                     ISP_NVRAM_MASK | qdev->
 473                                     eeprom_cmd_data | dataBit |
 474                                     AUBURN_EEPROM_CLK_RISE);
 475                 ql_write_nvram_reg(qdev,
 476                                     &port_regs->CommonRegs.
 477                                     serialPortInterfaceReg,
 478                                     ISP_NVRAM_MASK | qdev->
 479                                     eeprom_cmd_data | dataBit |
 480                                     AUBURN_EEPROM_CLK_FALL);
 481                 eepromAddr = eepromAddr << 1;
 482         }
 483 }
 484
 485 /*
 486  * Caller holds hw_lock.
 487  */
 488 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 489 {
 490         struct ql3xxx_port_registers __iomem *port_regs =
 491                         qdev->mem_map_registers;
 492         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 493         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 494                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 495 }
 496
 497 /*
 498  * Caller holds hw_lock.
 499  */
 500 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 501 {
 502         int i;
 503         u32 data = 0;
 504         u32 dataBit;
 505         struct ql3xxx_port_registers __iomem *port_regs =
 506                         qdev->mem_map_registers;
 507
 508         /* Read the data bits */
 509         /* The first bit is a dummy.  Clock right over it. */
 510         for (i = 0; i < dataBits; i++) {
 511                 ql_write_nvram_reg(qdev,
 512                                     &port_regs->CommonRegs.
 513                                     serialPortInterfaceReg,
 514                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 515                                     AUBURN_EEPROM_CLK_RISE);
 516                 ql_write_nvram_reg(qdev,
 517                                     &port_regs->CommonRegs.
 518                                     serialPortInterfaceReg,
 519                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 520                                     AUBURN_EEPROM_CLK_FALL);
 521                 dataBit =
 522                     (ql_read_common_reg
 523                      (qdev,
 524                       &port_regs->CommonRegs.
 525                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 526                 data = (data << 1) | dataBit;
 527         }
 528         *value = (u16) data;
 529 }
 530
 531 /*
 532  * Caller holds hw_lock.
 533  */
 534 static void eeprom_readword(struct ql3_adapter *qdev,
 535                             u32 eepromAddr, unsigned short *value)
 536 {
 537         fm93c56a_select(qdev);
 538         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 539         fm93c56a_datain(qdev, value);
 540         fm93c56a_deselect(qdev);
 541 }
 542
 543 static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
 544 {
 545         __le16 *p = (__le16 *)ndev->dev_addr;
 546         p[0] = cpu_to_le16(addr[0]);
 547         p[1] = cpu_to_le16(addr[1]);
 548         p[2] = cpu_to_le16(addr[2]);
 549 }
 550
 551 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 552 {
 553         u16 *pEEPROMData;
 554         u16 checksum = 0;
 555         u32 index;
 556         unsigned long hw_flags;
 557
 558         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 559
 560         pEEPROMData = (u16 *) & qdev->nvram_data;
 561         qdev->eeprom_cmd_data = 0;
 562         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 563                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 564                          2) << 10)) {
 565                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 566                         __func__);
 567                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 568                 return -1;
 569         }
 570
 571         for (index = 0; index < EEPROM_SIZE; index++) {
 572                 eeprom_readword(qdev, index, pEEPROMData);
 573                 checksum += *pEEPROMData;
 574                 pEEPROMData++;
 575         }
 576         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 577
 578         if (checksum != 0) {
 579                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 580                        qdev->ndev->name, checksum);
 581                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 582                 return -1;
 583         }
 584
 585         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 586         return checksum;
 587 }
 588
 589 static const u32 PHYAddr[2] = {
 590         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 591 };
 592
 593 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 594 {
 595         struct ql3xxx_port_registers __iomem *port_regs =
 596                         qdev->mem_map_registers;
 597         u32 temp;
 598         int count = 1000;
 599
 600         while (count) {
 601                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 602                 if (!(temp & MAC_MII_STATUS_BSY))
 603                         return 0;
 604                 udelay(10);
 605                 count--;
 606         }
 607         return -1;
 608 }
 609
 610 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 611 {
 612         struct ql3xxx_port_registers __iomem *port_regs =
 613                         qdev->mem_map_registers;
 614         u32 scanControl;
 615
 616         if (qdev->numPorts > 1) {
 617                 /* Auto scan will cycle through multiple ports */
 618                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 619         } else {
 620                 scanControl = MAC_MII_CONTROL_SC;
 621         }
 622
 623         /*
 624          * Scan register 1 of PHY/PETBI,
 625          * Set up to scan both devices
 626          * The autoscan starts from the first register, completes
 627          * the last one before rolling over to the first
 628          */
 629         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 630                            PHYAddr[0] | MII_SCAN_REGISTER);
 631
 632         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 633                            (scanControl) |
 634                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 635 }
 636
 637 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 638 {
 639         u8 ret;
 640         struct ql3xxx_port_registers __iomem *port_regs =
 641                                         qdev->mem_map_registers;
 642
 643         /* See if scan mode is enabled before we turn it off */
 644         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 645             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 646                 /* Scan is enabled */
 647                 ret = 1;
 648         } else {
 649                 /* Scan is disabled */
 650                 ret = 0;
 651         }
 652
 653         /*
 654          * When disabling scan mode you must first change the MII register
 655          * address
 656          */
 657         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 658                            PHYAddr[0] | MII_SCAN_REGISTER);
 659
 660         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 661                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 662                              MAC_MII_CONTROL_RC) << 16));
 663
 664         return ret;
 665 }
 666
 667 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 668                                u16 regAddr, u16 value, u32 phyAddr)
 669 {
 670         struct ql3xxx_port_registers __iomem *port_regs =
 671                         qdev->mem_map_registers;
 672         u8 scanWasEnabled;
 673
 674         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 675
 676         if (ql_wait_for_mii_ready(qdev)) {
 677                 if (netif_msg_link(qdev))
 678                         printk(KERN_WARNING PFX
 679                                "%s Timed out waiting for management port to "
 680                                "get free before issuing command.\n",
 681                                qdev->ndev->name);
 682                 return -1;
 683         }
 684
 685         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 686                            phyAddr | regAddr);
 687
 688         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 689
 690         /* Wait for write to complete 9/10/04 SJP */
 691         if (ql_wait_for_mii_ready(qdev)) {
 692                 if (netif_msg_link(qdev))
 693                         printk(KERN_WARNING PFX
 694                                "%s: Timed out waiting for management port to "
 695                                "get free before issuing command.\n",
 696                                qdev->ndev->name);
 697                 return -1;
 698         }
 699
 700         if (scanWasEnabled)
 701                 ql_mii_enable_scan_mode(qdev);
 702
 703         return 0;
 704 }
 705
 706 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 707                               u16 * value, u32 phyAddr)
 708 {
 709         struct ql3xxx_port_registers __iomem *port_regs =
 710                         qdev->mem_map_registers;
 711         u8 scanWasEnabled;
 712         u32 temp;
 713
 714         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 715
 716         if (ql_wait_for_mii_ready(qdev)) {
 717                 if (netif_msg_link(qdev))
 718                         printk(KERN_WARNING PFX
 719                                "%s: Timed out waiting for management port to "
 720                                "get free before issuing command.\n",
 721                                qdev->ndev->name);
 722                 return -1;
 723         }
 724
 725         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 726                            phyAddr | regAddr);
 727
 728         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 729                            (MAC_MII_CONTROL_RC << 16));
 730
 731         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 732                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 733
 734         /* Wait for the read to complete */
 735         if (ql_wait_for_mii_ready(qdev)) {
 736                 if (netif_msg_link(qdev))
 737                         printk(KERN_WARNING PFX
 738                                "%s: Timed out waiting for management port to "
 739                                "get free after issuing command.\n",
 740                                qdev->ndev->name);
 741                 return -1;
 742         }
 743
 744         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 745         *value = (u16) temp;
 746
 747         if (scanWasEnabled)
 748                 ql_mii_enable_scan_mode(qdev);
 749
 750         return 0;
 751 }
 752
 753 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 754 {
 755         struct ql3xxx_port_registers __iomem *port_regs =
 756                         qdev->mem_map_registers;
 757
 758         ql_mii_disable_scan_mode(qdev);
 759
 760         if (ql_wait_for_mii_ready(qdev)) {
 761                 if (netif_msg_link(qdev))
 762                         printk(KERN_WARNING PFX
 763                                "%s: Timed out waiting for management port to "
 764                                "get free before issuing command.\n",
 765                                qdev->ndev->name);
 766                 return -1;
 767         }
 768
 769         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 770                            qdev->PHYAddr | regAddr);
 771
 772         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 773
 774         /* Wait for write to complete. */
 775         if (ql_wait_for_mii_ready(qdev)) {
 776                 if (netif_msg_link(qdev))
 777                         printk(KERN_WARNING PFX
 778                                "%s: Timed out waiting for management port to "
 779                                "get free before issuing command.\n",
 780                                qdev->ndev->name);
 781                 return -1;
 782         }
 783
 784         ql_mii_enable_scan_mode(qdev);
 785
 786         return 0;
 787 }
 788
 789 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 790 {
 791         u32 temp;
 792         struct ql3xxx_port_registers __iomem *port_regs =
 793                         qdev->mem_map_registers;
 794
 795         ql_mii_disable_scan_mode(qdev);
 796
 797         if (ql_wait_for_mii_ready(qdev)) {
 798                 if (netif_msg_link(qdev))
 799                         printk(KERN_WARNING PFX
 800                                "%s: Timed out waiting for management port to "
 801                                "get free before issuing command.\n",
 802                                qdev->ndev->name);
 803                 return -1;
 804         }
 805
 806         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 807                            qdev->PHYAddr | regAddr);
 808
 809         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 810                            (MAC_MII_CONTROL_RC << 16));
 811
 812         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 813                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 814
 815         /* Wait for the read to complete */
 816         if (ql_wait_for_mii_ready(qdev)) {
 817                 if (netif_msg_link(qdev))
 818                         printk(KERN_WARNING PFX
 819                                "%s: Timed out waiting for management port to "
 820                                "get free before issuing command.\n",
 821                                qdev->ndev->name);
 822                 return -1;
 823         }
 824
 825         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 826         *value = (u16) temp;
 827
 828         ql_mii_enable_scan_mode(qdev);
 829
 830         return 0;
 831 }
 832
 833 static void ql_petbi_reset(struct ql3_adapter *qdev)
 834 {
 835         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 836 }
 837
 838 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 839 {
 840         u16 reg;
 841
 842         /* Enable Auto-negotiation sense */
 843         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 844         reg |= PETBI_TBI_AUTO_SENSE;
 845         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 846
 847         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 848                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 849
 850         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 851                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 852                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 853
 854 }
 855
 856 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
 857 {
 858         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 859                             PHYAddr[qdev->mac_index]);
 860 }
 861
 862 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
 863 {
 864         u16 reg;
 865
 866         /* Enable Auto-negotiation sense */
 867         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
 868                            PHYAddr[qdev->mac_index]);
 869         reg |= PETBI_TBI_AUTO_SENSE;
 870         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
 871                             PHYAddr[qdev->mac_index]);
 872
 873         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 874                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
 875                             PHYAddr[qdev->mac_index]);
 876
 877         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 878                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 879                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 880                             PHYAddr[qdev->mac_index]);
 881 }
 882
 883 static void ql_petbi_init(struct ql3_adapter *qdev)
 884 {
 885         ql_petbi_reset(qdev);
 886         ql_petbi_start_neg(qdev);
 887 }
 888
 889 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
 890 {
 891         ql_petbi_reset_ex(qdev);
 892         ql_petbi_start_neg_ex(qdev);
 893 }
 894
 895 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 896 {
 897         u16 reg;
 898
 899         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 900                 return 0;
 901
 902         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 903 }
 904
 905 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
 906 {
 907         printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
 908         /* power down device bit 11 = 1 */
 909         ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
 910         /* enable diagnostic mode bit 2 = 1 */
 911         ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
 912         /* 1000MB amplitude adjust (see Agere errata) */
 913         ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
 914         /* 1000MB amplitude adjust (see Agere errata) */
 915         ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
 916         /* 100MB amplitude adjust (see Agere errata) */
 917         ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
 918         /* 100MB amplitude adjust (see Agere errata) */
 919         ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
 920         /* 10MB amplitude adjust (see Agere errata) */
 921         ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
 922         /* 10MB amplitude adjust (see Agere errata) */
 923         ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
 924         /* point to hidden reg 0x2806 */
 925         ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
 926         /* Write new PHYAD w/bit 5 set */
 927         ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
 928         /*
 929          * Disable diagnostic mode bit 2 = 0
 930          * Power up device bit 11 = 0
 931          * Link up (on) and activity (blink)
 932          */
 933         ql_mii_write_reg(qdev, 0x12, 0x840a);
 934         ql_mii_write_reg(qdev, 0x00, 0x1140);
 935         ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
 936 }
 937
 938 static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
 939                                  u16 phyIdReg0, u16 phyIdReg1)
 940 {
 941         PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
 942         u32   oui;
 943         u16   model;
 944         int i;
 945
 946         if (phyIdReg0 == 0xffff) {
 947                 return result;
 948         }
 949
 950         if (phyIdReg1 == 0xffff) {
 951                 return result;
 952         }
 953
 954         /* oui is split between two registers */
 955         oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
 956
 957         model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
 958
 959         /* Scan table for this PHY */
 960         for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
 961                 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
 962                 {
 963                         result = PHY_DEVICES[i].phyDevice;
 964
 965                         printk(KERN_INFO "%s: Phy: %s\n",
 966                                 qdev->ndev->name, PHY_DEVICES[i].name);
 967
 968                         break;
 969                 }
 970         }
 971
 972         return result;
 973 }
 974
 975 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 976 {
 977         u16 reg;
 978
 979         switch(qdev->phyType) {
 980         case PHY_AGERE_ET1011C:
 981         {
 982                 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
 983                         return 0;
 984
 985                 reg = (reg >> 8) & 3;
 986                 break;
 987         }
 988         default:
 989         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 990                 return 0;
 991
 992         reg = (((reg & 0x18) >> 3) & 3);
 993         }
 994
 995         switch(reg) {
 996                 case 2:
 997                 return SPEED_1000;
 998                 case 1:
 999                 return SPEED_100;
1000                 case 0:
1001                 return SPEED_10;
1002                 default:
1003                 return -1;
1004         }
1005 }
1006
1007 static int ql_is_full_dup(struct ql3_adapter *qdev)
1008 {
1009         u16 reg;
1010
1011         switch(qdev->phyType) {
1012         case PHY_AGERE_ET1011C:
1013         {
1014                 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1015                         return 0;
1016
1017                 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1018         }
1019         case PHY_VITESSE_VSC8211:
1020         default:
1021         {
1022                 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1023                         return 0;
1024                 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1025         }
1026         }
1027 }
1028
1029 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1030 {
1031         u16 reg;
1032
1033         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1034                 return 0;
1035
1036         return (reg & PHY_NEG_PAUSE) != 0;
1037 }
1038
1039 static int PHY_Setup(struct ql3_adapter *qdev)
1040 {
1041         u16   reg1;
1042         u16   reg2;
1043         bool  agereAddrChangeNeeded = false;
1044         u32 miiAddr = 0;
1045         int err;
1046
1047         /*  Determine the PHY we are using by reading the ID's */
1048         err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1049         if(err != 0) {
1050                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1051                        qdev->ndev->name);
1052                 return err;
1053         }
1054
1055         err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1056         if(err != 0) {
1057                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1058                        qdev->ndev->name);
1059                 return err;
1060         }
1061
1062         /*  Check if we have a Agere PHY */
1063         if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1064
1065                 /* Determine which MII address we should be using
1066                    determined by the index of the card */
1067                 if (qdev->mac_index == 0) {
1068                         miiAddr = MII_AGERE_ADDR_1;
1069                 } else {
1070                         miiAddr = MII_AGERE_ADDR_2;
1071                 }
1072
1073                 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1074                 if(err != 0) {
1075                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1076                                qdev->ndev->name);
1077                         return err;
1078                 }
1079
1080                 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1081                 if(err != 0) {
1082                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1083                                qdev->ndev->name);
1084                         return err;
1085                 }
1086
1087                 /*  We need to remember to initialize the Agere PHY */
1088                 agereAddrChangeNeeded = true;
1089         }
1090
1091         /*  Determine the particular PHY we have on board to apply
1092             PHY specific initializations */
1093         qdev->phyType = getPhyType(qdev, reg1, reg2);
1094
1095         if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1096                 /* need this here so address gets changed */
1097                 phyAgereSpecificInit(qdev, miiAddr);
1098         } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1099                 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1100                 return -EIO;
1101         }
1102
1103         return 0;
1104 }
1105
1106 /*
1107  * Caller holds hw_lock.
1108  */
1109 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1110 {
1111         struct ql3xxx_port_registers __iomem *port_regs =
1112                         qdev->mem_map_registers;
1113         u32 value;
1114
1115         if (enable)
1116                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1117         else
1118                 value = (MAC_CONFIG_REG_PE << 16);
1119
1120         if (qdev->mac_index)
1121                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1122         else
1123                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1124 }
1125
1126 /*
1127  * Caller holds hw_lock.
1128  */
1129 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1130 {
1131         struct ql3xxx_port_registers __iomem *port_regs =
1132                         qdev->mem_map_registers;
1133         u32 value;
1134
1135         if (enable)
1136                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1137         else
1138                 value = (MAC_CONFIG_REG_SR << 16);
1139
1140         if (qdev->mac_index)
1141                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142         else
1143                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144 }
1145
1146 /*
1147  * Caller holds hw_lock.
1148  */
1149 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1150 {
1151         struct ql3xxx_port_registers __iomem *port_regs =
1152                         qdev->mem_map_registers;
1153         u32 value;
1154
1155         if (enable)
1156                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1157         else
1158                 value = (MAC_CONFIG_REG_GM << 16);
1159
1160         if (qdev->mac_index)
1161                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162         else
1163                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164 }
1165
1166 /*
1167  * Caller holds hw_lock.
1168  */
1169 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1170 {
1171         struct ql3xxx_port_registers __iomem *port_regs =
1172                         qdev->mem_map_registers;
1173         u32 value;
1174
1175         if (enable)
1176                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1177         else
1178                 value = (MAC_CONFIG_REG_FD << 16);
1179
1180         if (qdev->mac_index)
1181                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182         else
1183                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184 }
1185
1186 /*
1187  * Caller holds hw_lock.
1188  */
1189 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1190 {
1191         struct ql3xxx_port_registers __iomem *port_regs =
1192                         qdev->mem_map_registers;
1193         u32 value;
1194
1195         if (enable)
1196                 value =
1197                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1198                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1199         else
1200                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1201
1202         if (qdev->mac_index)
1203                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1204         else
1205                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1206 }
1207
1208 /*
1209  * Caller holds hw_lock.
1210  */
1211 static int ql_is_fiber(struct ql3_adapter *qdev)
1212 {
1213         struct ql3xxx_port_registers __iomem *port_regs =
1214                         qdev->mem_map_registers;
1215         u32 bitToCheck = 0;
1216         u32 temp;
1217
1218         switch (qdev->mac_index) {
1219         case 0:
1220                 bitToCheck = PORT_STATUS_SM0;
1221                 break;
1222         case 1:
1223                 bitToCheck = PORT_STATUS_SM1;
1224                 break;
1225         }
1226
1227         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228         return (temp & bitToCheck) != 0;
1229 }
1230
1231 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1232 {
1233         u16 reg;
1234         ql_mii_read_reg(qdev, 0x00, &reg);
1235         return (reg & 0x1000) != 0;
1236 }
1237
1238 /*
1239  * Caller holds hw_lock.
1240  */
1241 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1242 {
1243         struct ql3xxx_port_registers __iomem *port_regs =
1244                         qdev->mem_map_registers;
1245         u32 bitToCheck = 0;
1246         u32 temp;
1247
1248         switch (qdev->mac_index) {
1249         case 0:
1250                 bitToCheck = PORT_STATUS_AC0;
1251                 break;
1252         case 1:
1253                 bitToCheck = PORT_STATUS_AC1;
1254                 break;
1255         }
1256
1257         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1258         if (temp & bitToCheck) {
1259                 if (netif_msg_link(qdev))
1260                         printk(KERN_INFO PFX
1261                                "%s: Auto-Negotiate complete.\n",
1262                                qdev->ndev->name);
1263                 return 1;
1264         } else {
1265                 if (netif_msg_link(qdev))
1266                         printk(KERN_WARNING PFX
1267                                "%s: Auto-Negotiate incomplete.\n",
1268                                qdev->ndev->name);
1269                 return 0;
1270         }
1271 }
1272
1273 /*
1274  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1275  */
1276 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1277 {
1278         if (ql_is_fiber(qdev))
1279                 return ql_is_petbi_neg_pause(qdev);
1280         else
1281                 return ql_is_phy_neg_pause(qdev);
1282 }
1283
1284 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1285 {
1286         struct ql3xxx_port_registers __iomem *port_regs =
1287                         qdev->mem_map_registers;
1288         u32 bitToCheck = 0;
1289         u32 temp;
1290
1291         switch (qdev->mac_index) {
1292         case 0:
1293                 bitToCheck = PORT_STATUS_AE0;
1294                 break;
1295         case 1:
1296                 bitToCheck = PORT_STATUS_AE1;
1297                 break;
1298         }
1299         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1300         return (temp & bitToCheck) != 0;
1301 }
1302
1303 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1304 {
1305         if (ql_is_fiber(qdev))
1306                 return SPEED_1000;
1307         else
1308                 return ql_phy_get_speed(qdev);
1309 }
1310
1311 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1312 {
1313         if (ql_is_fiber(qdev))
1314                 return 1;
1315         else
1316                 return ql_is_full_dup(qdev);
1317 }
1318
1319 /*
1320  * Caller holds hw_lock.
1321  */
1322 static int ql_link_down_detect(struct ql3_adapter *qdev)
1323 {
1324         struct ql3xxx_port_registers __iomem *port_regs =
1325                         qdev->mem_map_registers;
1326         u32 bitToCheck = 0;
1327         u32 temp;
1328
1329         switch (qdev->mac_index) {
1330         case 0:
1331                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1332                 break;
1333         case 1:
1334                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1335                 break;
1336         }
1337
1338         temp =
1339             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1340         return (temp & bitToCheck) != 0;
1341 }
1342
1343 /*
1344  * Caller holds hw_lock.
1345  */
1346 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1347 {
1348         struct ql3xxx_port_registers __iomem *port_regs =
1349                         qdev->mem_map_registers;
1350
1351         switch (qdev->mac_index) {
1352         case 0:
1353                 ql_write_common_reg(qdev,
1354                                     &port_regs->CommonRegs.ispControlStatus,
1355                                     (ISP_CONTROL_LINK_DN_0) |
1356                                     (ISP_CONTROL_LINK_DN_0 << 16));
1357                 break;
1358
1359         case 1:
1360                 ql_write_common_reg(qdev,
1361                                     &port_regs->CommonRegs.ispControlStatus,
1362                                     (ISP_CONTROL_LINK_DN_1) |
1363                                     (ISP_CONTROL_LINK_DN_1 << 16));
1364                 break;
1365
1366         default:
1367                 return 1;
1368         }
1369
1370         return 0;
1371 }
1372
1373 /*
1374  * Caller holds hw_lock.
1375  */
1376 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1377 {
1378         struct ql3xxx_port_registers __iomem *port_regs =
1379                         qdev->mem_map_registers;
1380         u32 bitToCheck = 0;
1381         u32 temp;
1382
1383         switch (qdev->mac_index) {
1384         case 0:
1385                 bitToCheck = PORT_STATUS_F1_ENABLED;
1386                 break;
1387         case 1:
1388                 bitToCheck = PORT_STATUS_F3_ENABLED;
1389                 break;
1390         default:
1391                 break;
1392         }
1393
1394         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1395         if (temp & bitToCheck) {
1396                 if (netif_msg_link(qdev))
1397                         printk(KERN_DEBUG PFX
1398                                "%s: is not link master.\n", qdev->ndev->name);
1399                 return 0;
1400         } else {
1401                 if (netif_msg_link(qdev))
1402                         printk(KERN_DEBUG PFX
1403                                "%s: is link master.\n", qdev->ndev->name);
1404                 return 1;
1405         }
1406 }
1407
1408 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1409 {
1410         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1411                             PHYAddr[qdev->mac_index]);
1412 }
1413
1414 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1415 {
1416         u16 reg;
1417         u16 portConfiguration;
1418
1419         if(qdev->phyType == PHY_AGERE_ET1011C) {
1420                 /* turn off external loopback */
1421                 ql_mii_write_reg(qdev, 0x13, 0x0000);
1422         }
1423
1424         if(qdev->mac_index == 0)
1425                 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1426         else
1427                 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1428
1429         /*  Some HBA's in the field are set to 0 and they need to
1430             be reinterpreted with a default value */
1431         if(portConfiguration == 0)
1432                 portConfiguration = PORT_CONFIG_DEFAULT;
1433
1434         /* Set the 1000 advertisements */
1435         ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1436                            PHYAddr[qdev->mac_index]);
1437         reg &= ~PHY_GIG_ALL_PARAMS;
1438
1439         if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1440                 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1441                         reg |= PHY_GIG_ADV_1000F;
1442                 else
1443                         reg |= PHY_GIG_ADV_1000H;
1444         }
1445
1446         ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1447                             PHYAddr[qdev->mac_index]);
1448
1449         /* Set the 10/100 & pause negotiation advertisements */
1450         ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1451                            PHYAddr[qdev->mac_index]);
1452         reg &= ~PHY_NEG_ALL_PARAMS;
1453
1454         if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1455                 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1456
1457         if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1458                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1459                         reg |= PHY_NEG_ADV_100F;
1460
1461                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1462                         reg |= PHY_NEG_ADV_10F;
1463         }
1464
1465         if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1466                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1467                         reg |= PHY_NEG_ADV_100H;
1468
1469                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1470                         reg |= PHY_NEG_ADV_10H;
1471         }
1472
1473         if(portConfiguration &
1474            PORT_CONFIG_1000MB_SPEED) {
1475                 reg |= 1;
1476         }
1477
1478         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1479                             PHYAddr[qdev->mac_index]);
1480
1481         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1482
1483         ql_mii_write_reg_ex(qdev, CONTROL_REG,
1484                             reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1485                             PHYAddr[qdev->mac_index]);
1486 }
1487
1488 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1489 {
1490         ql_phy_reset_ex(qdev);
1491         PHY_Setup(qdev);
1492         ql_phy_start_neg_ex(qdev);
1493 }
1494
1495 /*
1496  * Caller holds hw_lock.
1497  */
1498 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1499 {
1500         struct ql3xxx_port_registers __iomem *port_regs =
1501                         qdev->mem_map_registers;
1502         u32 bitToCheck = 0;
1503         u32 temp, linkState;
1504
1505         switch (qdev->mac_index) {
1506         case 0:
1507                 bitToCheck = PORT_STATUS_UP0;
1508                 break;
1509         case 1:
1510                 bitToCheck = PORT_STATUS_UP1;
1511                 break;
1512         }
1513         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1514         if (temp & bitToCheck) {
1515                 linkState = LS_UP;
1516         } else {
1517                 linkState = LS_DOWN;
1518                 if (netif_msg_link(qdev))
1519                         printk(KERN_WARNING PFX
1520                                "%s: Link is down.\n", qdev->ndev->name);
1521         }
1522         return linkState;
1523 }
1524
1525 static int ql_port_start(struct ql3_adapter *qdev)
1526 {
1527         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1528                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1529                          2) << 7)) {
1530                 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1531                        qdev->ndev->name);
1532                 return -1;
1533         }
1534
1535         if (ql_is_fiber(qdev)) {
1536                 ql_petbi_init(qdev);
1537         } else {
1538                 /* Copper port */
1539                 ql_phy_init_ex(qdev);
1540         }
1541
1542         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1543         return 0;
1544 }
1545
1546 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1547 {
1548
1549         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1550                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1551                          2) << 7))
1552                 return -1;
1553
1554         if (!ql_auto_neg_error(qdev)) {
1555                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1556                         /* configure the MAC */
1557                         if (netif_msg_link(qdev))
1558                                 printk(KERN_DEBUG PFX
1559                                        "%s: Configuring link.\n",
1560                                        qdev->ndev->
1561                                        name);
1562                         ql_mac_cfg_soft_reset(qdev, 1);
1563                         ql_mac_cfg_gig(qdev,
1564                                        (ql_get_link_speed
1565                                         (qdev) ==
1566                                         SPEED_1000));
1567                         ql_mac_cfg_full_dup(qdev,
1568                                             ql_is_link_full_dup
1569                                             (qdev));
1570                         ql_mac_cfg_pause(qdev,
1571                                          ql_is_neg_pause
1572                                          (qdev));
1573                         ql_mac_cfg_soft_reset(qdev, 0);
1574
1575                         /* enable the MAC */
1576                         if (netif_msg_link(qdev))
1577                                 printk(KERN_DEBUG PFX
1578                                        "%s: Enabling mac.\n",
1579                                        qdev->ndev->
1580                                                name);
1581                         ql_mac_enable(qdev, 1);
1582                 }
1583
1584                 if (netif_msg_link(qdev))
1585                         printk(KERN_DEBUG PFX
1586                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1587                                qdev->ndev->name);
1588                 qdev->port_link_state = LS_UP;
1589                 netif_start_queue(qdev->ndev);
1590                 netif_carrier_on(qdev->ndev);
1591                 if (netif_msg_link(qdev))
1592                         printk(KERN_INFO PFX
1593                                "%s: Link is up at %d Mbps, %s duplex.\n",
1594                                qdev->ndev->name,
1595                                ql_get_link_speed(qdev),
1596                                ql_is_link_full_dup(qdev)
1597                                ? "full" : "half");
1598
1599         } else {        /* Remote error detected */
1600
1601                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1602                         if (netif_msg_link(qdev))
1603                                 printk(KERN_DEBUG PFX
1604                                        "%s: Remote error detected. "
1605                                        "Calling ql_port_start().\n",
1606                                        qdev->ndev->
1607                                        name);
1608                         /*
1609                          * ql_port_start() is shared code and needs
1610                          * to lock the PHY on it's own.
1611                          */
1612                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1613                         if(ql_port_start(qdev)) {/* Restart port */
1614                                 return -1;
1615                         } else
1616                                 return 0;
1617                 }
1618         }
1619         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1620         return 0;
1621 }
1622
1623 static void ql_link_state_machine_work(struct work_struct *work)
1624 {
1625         struct ql3_adapter *qdev =
1626                 container_of(work, struct ql3_adapter, link_state_work.work);
1627
1628         u32 curr_link_state;
1629         unsigned long hw_flags;
1630
1631         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1632
1633         curr_link_state = ql_get_link_state(qdev);
1634
1635         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1636                 if (netif_msg_link(qdev))
1637                         printk(KERN_INFO PFX
1638                                "%s: Reset in progress, skip processing link "
1639                                "state.\n", qdev->ndev->name);
1640
1641                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1642
1643                 /* Restart timer on 2 second interval. */
1644                 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);\
1645
1646                 return;
1647         }
1648
1649         switch (qdev->port_link_state) {
1650         default:
1651                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1652                         ql_port_start(qdev);
1653                 }
1654                 qdev->port_link_state = LS_DOWN;
1655                 /* Fall Through */
1656
1657         case LS_DOWN:
1658                 if (netif_msg_link(qdev))
1659                         printk(KERN_DEBUG PFX
1660                                "%s: port_link_state = LS_DOWN.\n",
1661                                qdev->ndev->name);
1662                 if (curr_link_state == LS_UP) {
1663                         if (netif_msg_link(qdev))
1664                                 printk(KERN_DEBUG PFX
1665                                        "%s: curr_link_state = LS_UP.\n",
1666                                        qdev->ndev->name);
1667                         if (ql_is_auto_neg_complete(qdev))
1668                                 ql_finish_auto_neg(qdev);
1669
1670                         if (qdev->port_link_state == LS_UP)
1671                                 ql_link_down_detect_clear(qdev);
1672
1673                 }
1674                 break;
1675
1676         case LS_UP:
1677                 /*
1678                  * See if the link is currently down or went down and came
1679                  * back up
1680                  */
1681                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1682                         if (netif_msg_link(qdev))
1683                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1684                                        qdev->ndev->name);
1685                         qdev->port_link_state = LS_DOWN;
1686                 }
1687                 break;
1688         }
1689         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1690
1691         /* Restart timer on 2 second interval. */
1692         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1693 }
1694
1695 /*
1696  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1697  */
1698 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1699 {
1700         if (ql_this_adapter_controls_port(qdev))
1701                 set_bit(QL_LINK_MASTER,&qdev->flags);
1702         else
1703                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1704 }
1705
1706 /*
1707  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1708  */
1709 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1710 {
1711         ql_mii_enable_scan_mode(qdev);
1712
1713         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1714                 if (ql_this_adapter_controls_port(qdev))
1715                         ql_petbi_init_ex(qdev);
1716         } else {
1717                 if (ql_this_adapter_controls_port(qdev))
1718                         ql_phy_init_ex(qdev);
1719         }
1720 }
1721
1722 /*
1723  * MII_Setup needs to be called before taking the PHY out of reset so that the
1724  * management interface clock speed can be set properly.  It would be better if
1725  * we had a way to disable MDC until after the PHY is out of reset, but we
1726  * don't have that capability.
1727  */
1728 static int ql_mii_setup(struct ql3_adapter *qdev)
1729 {
1730         u32 reg;
1731         struct ql3xxx_port_registers __iomem *port_regs =
1732                         qdev->mem_map_registers;
1733
1734         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1735                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1736                          2) << 7))
1737                 return -1;
1738
1739         if (qdev->device_id == QL3032_DEVICE_ID)
1740                 ql_write_page0_reg(qdev,
1741                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1742
1743         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1744         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1745
1746         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1747                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1748
1749         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1750         return 0;
1751 }
1752
1753 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1754 {
1755         u32 supported;
1756
1757         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1758                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1759                     | SUPPORTED_Autoneg;
1760         } else {
1761                 supported = SUPPORTED_10baseT_Half
1762                     | SUPPORTED_10baseT_Full
1763                     | SUPPORTED_100baseT_Half
1764                     | SUPPORTED_100baseT_Full
1765                     | SUPPORTED_1000baseT_Half
1766                     | SUPPORTED_1000baseT_Full
1767                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1768         }
1769
1770         return supported;
1771 }
1772
1773 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1774 {
1775         int status;
1776         unsigned long hw_flags;
1777         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1778         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1779                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1780                          2) << 7)) {
1781                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1782                 return 0;
1783         }
1784         status = ql_is_auto_cfg(qdev);
1785         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1786         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1787         return status;
1788 }
1789
1790 static u32 ql_get_speed(struct ql3_adapter *qdev)
1791 {
1792         u32 status;
1793         unsigned long hw_flags;
1794         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1795         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1796                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1797                          2) << 7)) {
1798                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1799                 return 0;
1800         }
1801         status = ql_get_link_speed(qdev);
1802         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1803         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1804         return status;
1805 }
1806
1807 static int ql_get_full_dup(struct ql3_adapter *qdev)
1808 {
1809         int status;
1810         unsigned long hw_flags;
1811         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1812         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1813                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1814                          2) << 7)) {
1815                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1816                 return 0;
1817         }
1818         status = ql_is_link_full_dup(qdev);
1819         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1820         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1821         return status;
1822 }
1823
1824
1825 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1826 {
1827         struct ql3_adapter *qdev = netdev_priv(ndev);
1828
1829         ecmd->transceiver = XCVR_INTERNAL;
1830         ecmd->supported = ql_supported_modes(qdev);
1831
1832         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1833                 ecmd->port = PORT_FIBRE;
1834         } else {
1835                 ecmd->port = PORT_TP;
1836                 ecmd->phy_address = qdev->PHYAddr;
1837         }
1838         ecmd->advertising = ql_supported_modes(qdev);
1839         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1840         ecmd->speed = ql_get_speed(qdev);
1841         ecmd->duplex = ql_get_full_dup(qdev);
1842         return 0;
1843 }
1844
1845 static void ql_get_drvinfo(struct net_device *ndev,
1846                            struct ethtool_drvinfo *drvinfo)
1847 {
1848         struct ql3_adapter *qdev = netdev_priv(ndev);
1849         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1850         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1851         strncpy(drvinfo->fw_version, "N/A", 32);
1852         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1853         drvinfo->regdump_len = 0;
1854         drvinfo->eedump_len = 0;
1855 }
1856
1857 static u32 ql_get_msglevel(struct net_device *ndev)
1858 {
1859         struct ql3_adapter *qdev = netdev_priv(ndev);
1860         return qdev->msg_enable;
1861 }
1862
1863 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1864 {
1865         struct ql3_adapter *qdev = netdev_priv(ndev);
1866         qdev->msg_enable = value;
1867 }
1868
1869 static void ql_get_pauseparam(struct net_device *ndev,
1870                               struct ethtool_pauseparam *pause)
1871 {
1872         struct ql3_adapter *qdev = netdev_priv(ndev);
1873         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1874
1875         u32 reg;
1876         if(qdev->mac_index == 0)
1877                 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1878         else
1879                 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1880
1881         pause->autoneg  = ql_get_auto_cfg_status(qdev);
1882         pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1883         pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1884 }
1885
1886 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1887         .get_settings = ql_get_settings,
1888         .get_drvinfo = ql_get_drvinfo,
1889         .get_link = ethtool_op_get_link,
1890         .get_msglevel = ql_get_msglevel,
1891         .set_msglevel = ql_set_msglevel,
1892         .get_pauseparam = ql_get_pauseparam,
1893 };
1894
1895 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1896 {
1897         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1898         dma_addr_t map;
1899         int err;
1900
1901         while (lrg_buf_cb) {
1902                 if (!lrg_buf_cb->skb) {
1903                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1904                                                            qdev->lrg_buffer_len);
1905                         if (unlikely(!lrg_buf_cb->skb)) {
1906                                 printk(KERN_DEBUG PFX
1907                                        "%s: Failed netdev_alloc_skb().\n",
1908                                        qdev->ndev->name);
1909                                 break;
1910                         } else {
1911                                 /*
1912                                  * We save some space to copy the ethhdr from
1913                                  * first buffer
1914                                  */
1915                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1916                                 map = pci_map_single(qdev->pdev,
1917                                                      lrg_buf_cb->skb->data,
1918                                                      qdev->lrg_buffer_len -
1919                                                      QL_HEADER_SPACE,
1920                                                      PCI_DMA_FROMDEVICE);
1921
1922                                 err = pci_dma_mapping_error(qdev->pdev, map);
1923                                 if(err) {
1924                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1925                                                qdev->ndev->name, err);
1926                                         dev_kfree_skb(lrg_buf_cb->skb);
1927                                         lrg_buf_cb->skb = NULL;
1928                                         break;
1929                                 }
1930
1931
1932                                 lrg_buf_cb->buf_phy_addr_low =
1933                                     cpu_to_le32(LS_64BITS(map));
1934                                 lrg_buf_cb->buf_phy_addr_high =
1935                                     cpu_to_le32(MS_64BITS(map));
1936                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1937                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1938                                                   qdev->lrg_buffer_len -
1939                                                   QL_HEADER_SPACE);
1940                                 --qdev->lrg_buf_skb_check;
1941                                 if (!qdev->lrg_buf_skb_check)
1942                                         return 1;
1943                         }
1944                 }
1945                 lrg_buf_cb = lrg_buf_cb->next;
1946         }
1947         return 0;
1948 }
1949
1950 /*
1951  * Caller holds hw_lock.
1952  */
1953 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1954 {
1955         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1956         if (qdev->small_buf_release_cnt >= 16) {
1957                 while (qdev->small_buf_release_cnt >= 16) {
1958                         qdev->small_buf_q_producer_index++;
1959
1960                         if (qdev->small_buf_q_producer_index ==
1961                             NUM_SBUFQ_ENTRIES)
1962                                 qdev->small_buf_q_producer_index = 0;
1963                         qdev->small_buf_release_cnt -= 8;
1964                 }
1965                 wmb();
1966                 writel(qdev->small_buf_q_producer_index,
1967                         &port_regs->CommonRegs.rxSmallQProducerIndex);
1968         }
1969 }
1970
1971 /*
1972  * Caller holds hw_lock.
1973  */
1974 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1975 {
1976         struct bufq_addr_element *lrg_buf_q_ele;
1977         int i;
1978         struct ql_rcv_buf_cb *lrg_buf_cb;
1979         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1980
1981         if ((qdev->lrg_buf_free_count >= 8)
1982             && (qdev->lrg_buf_release_cnt >= 16)) {
1983
1984                 if (qdev->lrg_buf_skb_check)
1985                         if (!ql_populate_free_queue(qdev))
1986                                 return;
1987
1988                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1989
1990                 while ((qdev->lrg_buf_release_cnt >= 16)
1991                        && (qdev->lrg_buf_free_count >= 8)) {
1992
1993                         for (i = 0; i < 8; i++) {
1994                                 lrg_buf_cb =
1995                                     ql_get_from_lrg_buf_free_list(qdev);
1996                                 lrg_buf_q_ele->addr_high =
1997                                     lrg_buf_cb->buf_phy_addr_high;
1998                                 lrg_buf_q_ele->addr_low =
1999                                     lrg_buf_cb->buf_phy_addr_low;
2000                                 lrg_buf_q_ele++;
2001
2002                                 qdev->lrg_buf_release_cnt--;
2003                         }
2004
2005                         qdev->lrg_buf_q_producer_index++;
2006
2007                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
2008                                 qdev->lrg_buf_q_producer_index = 0;
2009
2010                         if (qdev->lrg_buf_q_producer_index ==
2011                             (qdev->num_lbufq_entries - 1)) {
2012                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2013                         }
2014                 }
2015                 wmb();
2016                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2017                 writel(qdev->lrg_buf_q_producer_index,
2018                         &port_regs->CommonRegs.rxLargeQProducerIndex);
2019         }
2020 }
2021
2022 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2023                                    struct ob_mac_iocb_rsp *mac_rsp)
2024 {
2025         struct ql_tx_buf_cb *tx_cb;
2026         int i;
2027         int retval = 0;
2028
2029         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2030                 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2031         }
2032
2033         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2034
2035         /*  Check the transmit response flags for any errors */
2036         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2037                 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2038
2039                 qdev->ndev->stats.tx_errors++;
2040                 retval = -EIO;
2041                 goto frame_not_sent;
2042         }
2043
2044         if(tx_cb->seg_count == 0) {
2045                 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2046
2047                 qdev->ndev->stats.tx_errors++;
2048                 retval = -EIO;
2049                 goto invalid_seg_count;
2050         }
2051
2052         pci_unmap_single(qdev->pdev,
2053                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2054                          pci_unmap_len(&tx_cb->map[0], maplen),
2055                          PCI_DMA_TODEVICE);
2056         tx_cb->seg_count--;
2057         if (tx_cb->seg_count) {
2058                 for (i = 1; i < tx_cb->seg_count; i++) {
2059                         pci_unmap_page(qdev->pdev,
2060                                        pci_unmap_addr(&tx_cb->map[i],
2061                                                       mapaddr),
2062                                        pci_unmap_len(&tx_cb->map[i], maplen),
2063                                        PCI_DMA_TODEVICE);
2064                 }
2065         }
2066         qdev->ndev->stats.tx_packets++;
2067         qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
2068
2069 frame_not_sent:
2070         dev_kfree_skb_irq(tx_cb->skb);
2071         tx_cb->skb = NULL;
2072
2073 invalid_seg_count:
2074         atomic_inc(&qdev->tx_count);
2075 }
2076
2077 static void ql_get_sbuf(struct ql3_adapter *qdev)
2078 {
2079         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2080                 qdev->small_buf_index = 0;
2081         qdev->small_buf_release_cnt++;
2082 }
2083
2084 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2085 {
2086         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2087         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2088         qdev->lrg_buf_release_cnt++;
2089         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2090                 qdev->lrg_buf_index = 0;
2091         return(lrg_buf_cb);
2092 }
2093
2094 /*
2095  * The difference between 3022 and 3032 for inbound completions:
2096  * 3022 uses two buffers per completion.  The first buffer contains
2097  * (some) header info, the second the remainder of the headers plus
2098  * the data.  For this chip we reserve some space at the top of the
2099  * receive buffer so that the header info in buffer one can be
2100  * prepended to the buffer two.  Buffer two is the sent up while
2101  * buffer one is returned to the hardware to be reused.
2102  * 3032 receives all of it's data and headers in one buffer for a
2103  * simpler process.  3032 also supports checksum verification as
2104  * can be seen in ql_process_macip_rx_intr().
2105  */
2106 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2107                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2108 {
2109         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2110         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2111         struct sk_buff *skb;
2112         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2113
2114         /*
2115          * Get the inbound address list (small buffer).
2116          */
2117         ql_get_sbuf(qdev);
2118
2119         if (qdev->device_id == QL3022_DEVICE_ID)
2120                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2121
2122         /* start of second buffer */
2123         lrg_buf_cb2 = ql_get_lbuf(qdev);
2124         skb = lrg_buf_cb2->skb;
2125
2126         qdev->ndev->stats.rx_packets++;
2127         qdev->ndev->stats.rx_bytes += length;
2128
2129         skb_put(skb, length);
2130         pci_unmap_single(qdev->pdev,
2131                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2132                          pci_unmap_len(lrg_buf_cb2, maplen),
2133                          PCI_DMA_FROMDEVICE);
2134         prefetch(skb->data);
2135         skb->ip_summed = CHECKSUM_NONE;
2136         skb->protocol = eth_type_trans(skb, qdev->ndev);
2137
2138         netif_receive_skb(skb);
2139         lrg_buf_cb2->skb = NULL;
2140
2141         if (qdev->device_id == QL3022_DEVICE_ID)
2142                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2143         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2144 }
2145
2146 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2147                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2148 {
2149         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2150         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2151         struct sk_buff *skb1 = NULL, *skb2;
2152         struct net_device *ndev = qdev->ndev;
2153         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2154         u16 size = 0;
2155
2156         /*
2157          * Get the inbound address list (small buffer).
2158          */
2159
2160         ql_get_sbuf(qdev);
2161
2162         if (qdev->device_id == QL3022_DEVICE_ID) {
2163                 /* start of first buffer on 3022 */
2164                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2165                 skb1 = lrg_buf_cb1->skb;
2166                 size = ETH_HLEN;
2167                 if (*((u16 *) skb1->data) != 0xFFFF)
2168                         size += VLAN_ETH_HLEN - ETH_HLEN;
2169         }
2170
2171         /* start of second buffer */
2172         lrg_buf_cb2 = ql_get_lbuf(qdev);
2173         skb2 = lrg_buf_cb2->skb;
2174
2175         skb_put(skb2, length);  /* Just the second buffer length here. */
2176         pci_unmap_single(qdev->pdev,
2177                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2178                          pci_unmap_len(lrg_buf_cb2, maplen),
2179                          PCI_DMA_FROMDEVICE);
2180         prefetch(skb2->data);
2181
2182         skb2->ip_summed = CHECKSUM_NONE;
2183         if (qdev->device_id == QL3022_DEVICE_ID) {
2184                 /*
2185                  * Copy the ethhdr from first buffer to second. This
2186                  * is necessary for 3022 IP completions.
2187                  */
2188                 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2189                                                  skb_push(skb2, size), size);
2190         } else {
2191                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2192                 if (checksum &
2193                         (IB_IP_IOCB_RSP_3032_ICE |
2194                          IB_IP_IOCB_RSP_3032_CE)) {
2195                         printk(KERN_ERR
2196                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
2197                                __func__,
2198                                ((checksum &
2199                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2200                                 "UDP"),checksum);
2201                 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2202                                 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2203                                 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2204                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
2205                 }
2206         }
2207         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2208
2209         netif_receive_skb(skb2);
2210         ndev->stats.rx_packets++;
2211         ndev->stats.rx_bytes += length;
2212         lrg_buf_cb2->skb = NULL;
2213
2214         if (qdev->device_id == QL3022_DEVICE_ID)
2215                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2216         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2217 }
2218
2219 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2220                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
2221 {
2222         struct net_rsp_iocb *net_rsp;
2223         struct net_device *ndev = qdev->ndev;
2224         int work_done = 0;
2225
2226         /* While there are entries in the completion queue. */
2227         while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2228                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2229
2230                 net_rsp = qdev->rsp_current;
2231                 rmb();
2232                 /*
2233                  * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2234                  * inbound completion is for a VLAN.
2235                  */
2236                 if (qdev->device_id == QL3032_DEVICE_ID)
2237                         net_rsp->opcode &= 0x7f;
2238                 switch (net_rsp->opcode) {
2239
2240                 case OPCODE_OB_MAC_IOCB_FN0:
2241                 case OPCODE_OB_MAC_IOCB_FN2:
2242                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2243                                                net_rsp);
2244                         (*tx_cleaned)++;
2245                         break;
2246
2247                 case OPCODE_IB_MAC_IOCB:
2248                 case OPCODE_IB_3032_MAC_IOCB:
2249                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2250                                                net_rsp);
2251                         (*rx_cleaned)++;
2252                         break;
2253
2254                 case OPCODE_IB_IP_IOCB:
2255                 case OPCODE_IB_3032_IP_IOCB:
2256                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2257                                                  net_rsp);
2258                         (*rx_cleaned)++;
2259                         break;
2260                 default:
2261                         {
2262                                 u32 *tmp = (u32 *) net_rsp;
2263                                 printk(KERN_ERR PFX
2264                                        "%s: Hit default case, not "
2265                                        "handled!\n"
2266                                        "        dropping the packet, opcode = "
2267                                        "%x.\n",
2268                                        ndev->name, net_rsp->opcode);
2269                                 printk(KERN_ERR PFX
2270                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2271                                        (unsigned long int)tmp[0],
2272                                        (unsigned long int)tmp[1],
2273                                        (unsigned long int)tmp[2],
2274                                        (unsigned long int)tmp[3]);
2275                         }
2276                 }
2277
2278                 qdev->rsp_consumer_index++;
2279
2280                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2281                         qdev->rsp_consumer_index = 0;
2282                         qdev->rsp_current = qdev->rsp_q_virt_addr;
2283                 } else {
2284                         qdev->rsp_current++;
2285                 }
2286
2287                 work_done = *tx_cleaned + *rx_cleaned;
2288         }
2289
2290         return work_done;
2291 }
2292
2293 static int ql_poll(struct napi_struct *napi, int budget)
2294 {
2295         struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2296         struct net_device *ndev = qdev->ndev;
2297         int rx_cleaned = 0, tx_cleaned = 0;
2298         unsigned long hw_flags;
2299         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2300
2301         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2302
2303         if (tx_cleaned + rx_cleaned != budget) {
2304                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2305                 __netif_rx_complete(ndev, napi);
2306                 ql_update_small_bufq_prod_index(qdev);
2307                 ql_update_lrg_bufq_prod_index(qdev);
2308                 writel(qdev->rsp_consumer_index,
2309                             &port_regs->CommonRegs.rspQConsumerIndex);
2310                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2311
2312                 ql_enable_interrupts(qdev);
2313         }
2314         return tx_cleaned + rx_cleaned;
2315 }
2316
2317 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2318 {
2319
2320         struct net_device *ndev = dev_id;
2321         struct ql3_adapter *qdev = netdev_priv(ndev);
2322         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2323         u32 value;
2324         int handled = 1;
2325         u32 var;
2326
2327         port_regs = qdev->mem_map_registers;
2328
2329         value =
2330             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2331
2332         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2333                 spin_lock(&qdev->adapter_lock);
2334                 netif_stop_queue(qdev->ndev);
2335                 netif_carrier_off(qdev->ndev);
2336                 ql_disable_interrupts(qdev);
2337                 qdev->port_link_state = LS_DOWN;
2338                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2339
2340                 if (value & ISP_CONTROL_FE) {
2341                         /*
2342                          * Chip Fatal Error.
2343                          */
2344                         var =
2345                             ql_read_page0_reg_l(qdev,
2346                                               &port_regs->PortFatalErrStatus);
2347                         printk(KERN_WARNING PFX
2348                                "%s: Resetting chip. PortFatalErrStatus "
2349                                "register = 0x%x\n", ndev->name, var);
2350                         set_bit(QL_RESET_START,&qdev->flags) ;
2351                 } else {
2352                         /*
2353                          * Soft Reset Requested.
2354                          */
2355                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2356                         printk(KERN_ERR PFX
2357                                "%s: Another function issued a reset to the "
2358                                "chip. ISR value = %x.\n", ndev->name, value);
2359                 }
2360                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2361                 spin_unlock(&qdev->adapter_lock);
2362         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2363                 ql_disable_interrupts(qdev);
2364                 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2365                         __netif_rx_schedule(ndev, &qdev->napi);
2366                 }
2367         } else {
2368                 return IRQ_NONE;
2369         }
2370
2371         return IRQ_RETVAL(handled);
2372 }
2373
2374 /*
2375  * Get the total number of segments needed for the
2376  * given number of fragments.  This is necessary because
2377  * outbound address lists (OAL) will be used when more than
2378  * two frags are given.  Each address list has 5 addr/len
2379  * pairs.  The 5th pair in each AOL is used to  point to
2380  * the next AOL if more frags are coming.
2381  * That is why the frags:segment count  ratio is not linear.
2382  */
2383 static int ql_get_seg_count(struct ql3_adapter *qdev,
2384                             unsigned short frags)
2385 {
2386         if (qdev->device_id == QL3022_DEVICE_ID)
2387                 return 1;
2388
2389         switch(frags) {
2390         case 0: return 1;       /* just the skb->data seg */
2391         case 1: return 2;       /* skb->data + 1 frag */
2392         case 2: return 3;       /* skb->data + 2 frags */
2393         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2394         case 4: return 6;
2395         case 5: return 7;
2396         case 6: return 8;
2397         case 7: return 10;
2398         case 8: return 11;
2399         case 9: return 12;
2400         case 10: return 13;
2401         case 11: return 15;
2402         case 12: return 16;
2403         case 13: return 17;
2404         case 14: return 18;
2405         case 15: return 20;
2406         case 16: return 21;
2407         case 17: return 22;
2408         case 18: return 23;
2409         }
2410         return -1;
2411 }
2412
2413 static void ql_hw_csum_setup(const struct sk_buff *skb,
2414                              struct ob_mac_iocb_req *mac_iocb_ptr)
2415 {
2416         const struct iphdr *ip = ip_hdr(skb);
2417
2418         mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2419         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2420
2421         if (ip->protocol == IPPROTO_TCP) {
2422                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2423                         OB_3032MAC_IOCB_REQ_IC;
2424         } else {
2425                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2426                         OB_3032MAC_IOCB_REQ_IC;
2427         }
2428
2429 }
2430
2431 /*
2432  * Map the buffers for this transmit.  This will return
2433  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2434  */
2435 static int ql_send_map(struct ql3_adapter *qdev,
2436                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2437                                 struct ql_tx_buf_cb *tx_cb,
2438                                 struct sk_buff *skb)
2439 {
2440         struct oal *oal;
2441         struct oal_entry *oal_entry;
2442         int len = skb_headlen(skb);
2443         dma_addr_t map;
2444         int err;
2445         int completed_segs, i;
2446         int seg_cnt, seg = 0;
2447         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2448
2449         seg_cnt = tx_cb->seg_count;
2450         /*
2451          * Map the skb buffer first.
2452          */
2453         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2454
2455         err = pci_dma_mapping_error(qdev->pdev, map);
2456         if(err) {
2457                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2458                        qdev->ndev->name, err);
2459
2460                 return NETDEV_TX_BUSY;
2461         }
2462
2463         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2464         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2465         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2466         oal_entry->len = cpu_to_le32(len);
2467         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2468         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2469         seg++;
2470
2471         if (seg_cnt == 1) {
2472                 /* Terminate the last segment. */
2473                 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2474         } else {
2475                 oal = tx_cb->oal;
2476                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2477                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2478                         oal_entry++;
2479                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2480                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2481                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2482                             (seg == 17 && seg_cnt > 18)) {
2483                                 /* Continuation entry points to outbound address list. */
2484                                 map = pci_map_single(qdev->pdev, oal,
2485                                                      sizeof(struct oal),
2486                                                      PCI_DMA_TODEVICE);
2487
2488                                 err = pci_dma_mapping_error(qdev->pdev, map);
2489                                 if(err) {
2490
2491                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2492                                                qdev->ndev->name, err);
2493                                         goto map_error;
2494                                 }
2495
2496                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2497                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2498                                 oal_entry->len =
2499                                     cpu_to_le32(sizeof(struct oal) |
2500                                                 OAL_CONT_ENTRY);
2501                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2502                                                    map);
2503                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2504                                                   sizeof(struct oal));
2505                                 oal_entry = (struct oal_entry *)oal;
2506                                 oal++;
2507                                 seg++;
2508                         }
2509
2510                         map =
2511                             pci_map_page(qdev->pdev, frag->page,
2512                                          frag->page_offset, frag->size,
2513                                          PCI_DMA_TODEVICE);
2514
2515                         err = pci_dma_mapping_error(qdev->pdev, map);
2516                         if(err) {
2517                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2518                                        qdev->ndev->name, err);
2519                                 goto map_error;
2520                         }
2521
2522                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2523                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2524                         oal_entry->len = cpu_to_le32(frag->size);
2525                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2526                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2527                                           frag->size);
2528                 }
2529                 /* Terminate the last segment. */
2530                 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2531         }
2532
2533         return NETDEV_TX_OK;
2534
2535 map_error:
2536         /* A PCI mapping failed and now we will need to back out
2537          * We need to traverse through the oal's and associated pages which
2538          * have been mapped and now we must unmap them to clean up properly
2539          */
2540
2541         seg = 1;
2542         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2543         oal = tx_cb->oal;
2544         for (i=0; i<completed_segs; i++,seg++) {
2545                 oal_entry++;
2546
2547                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2548                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2549                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2550                    (seg == 17 && seg_cnt > 18)) {
2551                         pci_unmap_single(qdev->pdev,
2552                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2553                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2554                                  PCI_DMA_TODEVICE);
2555                         oal++;
2556                         seg++;
2557                 }
2558
2559                 pci_unmap_page(qdev->pdev,
2560                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2561                                pci_unmap_len(&tx_cb->map[seg], maplen),
2562                                PCI_DMA_TODEVICE);
2563         }
2564
2565         pci_unmap_single(qdev->pdev,
2566                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2567                          pci_unmap_addr(&tx_cb->map[0], maplen),
2568                          PCI_DMA_TODEVICE);
2569
2570         return NETDEV_TX_BUSY;
2571
2572 }
2573
2574 /*
2575  * The difference between 3022 and 3032 sends:
2576  * 3022 only supports a simple single segment transmission.
2577  * 3032 supports checksumming and scatter/gather lists (fragments).
2578  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2579  * in the IOCB plus a chain of outbound address lists (OAL) that
2580  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2581  * will used to point to an OAL when more ALP entries are required.
2582  * The IOCB is always the top of the chain followed by one or more
2583  * OALs (when necessary).
2584  */
2585 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2586 {
2587         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2588         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2589         struct ql_tx_buf_cb *tx_cb;
2590         u32 tot_len = skb->len;
2591         struct ob_mac_iocb_req *mac_iocb_ptr;
2592
2593         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2594                 return NETDEV_TX_BUSY;
2595         }
2596
2597         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2598         if((tx_cb->seg_count = ql_get_seg_count(qdev,
2599                                                 (skb_shinfo(skb)->nr_frags))) == -1) {
2600                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2601                 return NETDEV_TX_OK;
2602         }
2603
2604         mac_iocb_ptr = tx_cb->queue_entry;
2605         memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2606         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2607         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2608         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2609         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2610         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2611         tx_cb->skb = skb;
2612         if (qdev->device_id == QL3032_DEVICE_ID &&
2613             skb->ip_summed == CHECKSUM_PARTIAL)
2614                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2615
2616         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2617                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2618                 return NETDEV_TX_BUSY;
2619         }
2620
2621         wmb();
2622         qdev->req_producer_index++;
2623         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2624                 qdev->req_producer_index = 0;
2625         wmb();
2626         ql_write_common_reg_l(qdev,
2627                             &port_regs->CommonRegs.reqQProducerIndex,
2628                             qdev->req_producer_index);
2629
2630         ndev->trans_start = jiffies;
2631         if (netif_msg_tx_queued(qdev))
2632                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2633                        ndev->name, qdev->req_producer_index, skb->len);
2634
2635         atomic_dec(&qdev->tx_count);
2636         return NETDEV_TX_OK;
2637 }
2638
2639 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2640 {
2641         qdev->req_q_size =
2642             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2643
2644         qdev->req_q_virt_addr =
2645             pci_alloc_consistent(qdev->pdev,
2646                                  (size_t) qdev->req_q_size,
2647                                  &qdev->req_q_phy_addr);
2648
2649         if ((qdev->req_q_virt_addr == NULL) ||
2650             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2651                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2652                        qdev->ndev->name);
2653                 return -ENOMEM;
2654         }
2655
2656         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2657
2658         qdev->rsp_q_virt_addr =
2659             pci_alloc_consistent(qdev->pdev,
2660                                  (size_t) qdev->rsp_q_size,
2661                                  &qdev->rsp_q_phy_addr);
2662
2663         if ((qdev->rsp_q_virt_addr == NULL) ||
2664             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2665                 printk(KERN_ERR PFX
2666                        "%s: rspQ allocation failed\n",
2667                        qdev->ndev->name);
2668                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2669                                     qdev->req_q_virt_addr,
2670                                     qdev->req_q_phy_addr);
2671                 return -ENOMEM;
2672         }
2673
2674         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2675
2676         return 0;
2677 }
2678
2679 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2680 {
2681         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2682                 printk(KERN_INFO PFX
2683                        "%s: Already done.\n", qdev->ndev->name);
2684                 return;
2685         }
2686
2687         pci_free_consistent(qdev->pdev,
2688                             qdev->req_q_size,
2689                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2690
2691         qdev->req_q_virt_addr = NULL;
2692
2693         pci_free_consistent(qdev->pdev,
2694                             qdev->rsp_q_size,
2695                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2696
2697         qdev->rsp_q_virt_addr = NULL;
2698
2699         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2700 }
2701
2702 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2703 {
2704         /* Create Large Buffer Queue */
2705         qdev->lrg_buf_q_size =
2706             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2707         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2708                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2709         else
2710                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2711
2712         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2713         if (qdev->lrg_buf == NULL) {
2714                 printk(KERN_ERR PFX
2715                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2716                 return -ENOMEM;
2717         }
2718
2719         qdev->lrg_buf_q_alloc_virt_addr =
2720             pci_alloc_consistent(qdev->pdev,
2721                                  qdev->lrg_buf_q_alloc_size,
2722                                  &qdev->lrg_buf_q_alloc_phy_addr);
2723
2724         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2725                 printk(KERN_ERR PFX
2726                        "%s: lBufQ failed\n", qdev->ndev->name);
2727                 return -ENOMEM;
2728         }
2729         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2730         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2731
2732         /* Create Small Buffer Queue */
2733         qdev->small_buf_q_size =
2734             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2735         if (qdev->small_buf_q_size < PAGE_SIZE)
2736                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2737         else
2738                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2739
2740         qdev->small_buf_q_alloc_virt_addr =
2741             pci_alloc_consistent(qdev->pdev,
2742                                  qdev->small_buf_q_alloc_size,
2743                                  &qdev->small_buf_q_alloc_phy_addr);
2744
2745         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2746                 printk(KERN_ERR PFX
2747                        "%s: Small Buffer Queue allocation failed.\n",
2748                        qdev->ndev->name);
2749                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2750                                     qdev->lrg_buf_q_alloc_virt_addr,
2751                                     qdev->lrg_buf_q_alloc_phy_addr);
2752                 return -ENOMEM;
2753         }
2754
2755         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2756         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2757         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2758         return 0;
2759 }
2760
2761 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2762 {
2763         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2764                 printk(KERN_INFO PFX
2765                        "%s: Already done.\n", qdev->ndev->name);
2766                 return;
2767         }
2768         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2769         pci_free_consistent(qdev->pdev,
2770                             qdev->lrg_buf_q_alloc_size,
2771                             qdev->lrg_buf_q_alloc_virt_addr,
2772                             qdev->lrg_buf_q_alloc_phy_addr);
2773
2774         qdev->lrg_buf_q_virt_addr = NULL;
2775
2776         pci_free_consistent(qdev->pdev,
2777                             qdev->small_buf_q_alloc_size,
2778                             qdev->small_buf_q_alloc_virt_addr,
2779                             qdev->small_buf_q_alloc_phy_addr);
2780
2781         qdev->small_buf_q_virt_addr = NULL;
2782
2783         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2784 }
2785
2786 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2787 {
2788         int i;
2789         struct bufq_addr_element *small_buf_q_entry;
2790
2791         /* Currently we allocate on one of memory and use it for smallbuffers */
2792         qdev->small_buf_total_size =
2793             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2794              QL_SMALL_BUFFER_SIZE);
2795
2796         qdev->small_buf_virt_addr =
2797             pci_alloc_consistent(qdev->pdev,
2798                                  qdev->small_buf_total_size,
2799                                  &qdev->small_buf_phy_addr);
2800
2801         if (qdev->small_buf_virt_addr == NULL) {
2802                 printk(KERN_ERR PFX
2803                        "%s: Failed to get small buffer memory.\n",
2804                        qdev->ndev->name);
2805                 return -ENOMEM;
2806         }
2807
2808         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2809         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2810
2811         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2812
2813         /* Initialize the small buffer queue. */
2814         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2815                 small_buf_q_entry->addr_high =
2816                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2817                 small_buf_q_entry->addr_low =
2818                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2819                                 (i * QL_SMALL_BUFFER_SIZE));
2820                 small_buf_q_entry++;
2821         }
2822         qdev->small_buf_index = 0;
2823         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2824         return 0;
2825 }
2826
2827 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2828 {
2829         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2830                 printk(KERN_INFO PFX
2831                        "%s: Already done.\n", qdev->ndev->name);
2832                 return;
2833         }
2834         if (qdev->small_buf_virt_addr != NULL) {
2835                 pci_free_consistent(qdev->pdev,
2836                                     qdev->small_buf_total_size,
2837                                     qdev->small_buf_virt_addr,
2838                                     qdev->small_buf_phy_addr);
2839
2840                 qdev->small_buf_virt_addr = NULL;
2841         }
2842 }
2843
2844 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2845 {
2846         int i = 0;
2847         struct ql_rcv_buf_cb *lrg_buf_cb;
2848
2849         for (i = 0; i < qdev->num_large_buffers; i++) {
2850                 lrg_buf_cb = &qdev->lrg_buf[i];
2851                 if (lrg_buf_cb->skb) {
2852                         dev_kfree_skb(lrg_buf_cb->skb);
2853                         pci_unmap_single(qdev->pdev,
2854                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2855                                          pci_unmap_len(lrg_buf_cb, maplen),
2856                                          PCI_DMA_FROMDEVICE);
2857                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2858                 } else {
2859                         break;
2860                 }
2861         }
2862 }
2863
2864 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2865 {
2866         int i;
2867         struct ql_rcv_buf_cb *lrg_buf_cb;
2868         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2869
2870         for (i = 0; i < qdev->num_large_buffers; i++) {
2871                 lrg_buf_cb = &qdev->lrg_buf[i];
2872                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2873                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2874                 buf_addr_ele++;
2875         }
2876         qdev->lrg_buf_index = 0;
2877         qdev->lrg_buf_skb_check = 0;
2878 }
2879
2880 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2881 {
2882         int i;
2883         struct ql_rcv_buf_cb *lrg_buf_cb;
2884         struct sk_buff *skb;
2885         dma_addr_t map;
2886         int err;
2887
2888         for (i = 0; i < qdev->num_large_buffers; i++) {
2889                 skb = netdev_alloc_skb(qdev->ndev,
2890                                        qdev->lrg_buffer_len);
2891                 if (unlikely(!skb)) {
2892                         /* Better luck next round */
2893                         printk(KERN_ERR PFX
2894                                "%s: large buff alloc failed, "
2895                                "for %d bytes at index %d.\n",
2896                                qdev->ndev->name,
2897                                qdev->lrg_buffer_len * 2, i);
2898                         ql_free_large_buffers(qdev);
2899                         return -ENOMEM;
2900                 } else {
2901
2902                         lrg_buf_cb = &qdev->lrg_buf[i];
2903                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2904                         lrg_buf_cb->index = i;
2905                         lrg_buf_cb->skb = skb;
2906                         /*
2907                          * We save some space to copy the ethhdr from first
2908                          * buffer
2909                          */
2910                         skb_reserve(skb, QL_HEADER_SPACE);
2911                         map = pci_map_single(qdev->pdev,
2912                                              skb->data,
2913                                              qdev->lrg_buffer_len -
2914                                              QL_HEADER_SPACE,
2915                                              PCI_DMA_FROMDEVICE);
2916
2917                         err = pci_dma_mapping_error(qdev->pdev, map);
2918                         if(err) {
2919                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2920                                        qdev->ndev->name, err);
2921                                 ql_free_large_buffers(qdev);
2922                                 return -ENOMEM;
2923                         }
2924
2925                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2926                         pci_unmap_len_set(lrg_buf_cb, maplen,
2927                                           qdev->lrg_buffer_len -
2928                                           QL_HEADER_SPACE);
2929                         lrg_buf_cb->buf_phy_addr_low =
2930                             cpu_to_le32(LS_64BITS(map));
2931                         lrg_buf_cb->buf_phy_addr_high =
2932                             cpu_to_le32(MS_64BITS(map));
2933                 }
2934         }
2935         return 0;
2936 }
2937
2938 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2939 {
2940         struct ql_tx_buf_cb *tx_cb;
2941         int i;
2942
2943         tx_cb = &qdev->tx_buf[0];
2944         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2945                 if (tx_cb->oal) {
2946                         kfree(tx_cb->oal);
2947                         tx_cb->oal = NULL;
2948                 }
2949                 tx_cb++;
2950         }
2951 }
2952
2953 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2954 {
2955         struct ql_tx_buf_cb *tx_cb;
2956         int i;
2957         struct ob_mac_iocb_req *req_q_curr =
2958                                         qdev->req_q_virt_addr;
2959
2960         /* Create free list of transmit buffers */
2961         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2962
2963                 tx_cb = &qdev->tx_buf[i];
2964                 tx_cb->skb = NULL;
2965                 tx_cb->queue_entry = req_q_curr;
2966                 req_q_curr++;
2967                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2968                 if (tx_cb->oal == NULL)
2969                         return -1;
2970         }
2971         return 0;
2972 }
2973
2974 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2975 {
2976         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2977                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2978                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2979         }
2980         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2981                 /*
2982                  * Bigger buffers, so less of them.
2983                  */
2984                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2985                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2986         } else {
2987                 printk(KERN_ERR PFX
2988                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2989                        qdev->ndev->name);
2990                 return -ENOMEM;
2991         }
2992         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2993         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2994         qdev->max_frame_size =
2995             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2996
2997         /*
2998          * First allocate a page of shared memory and use it for shadow
2999          * locations of Network Request Queue Consumer Address Register and
3000          * Network Completion Queue Producer Index Register
3001          */
3002         qdev->shadow_reg_virt_addr =
3003             pci_alloc_consistent(qdev->pdev,
3004                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3005
3006         if (qdev->shadow_reg_virt_addr != NULL) {
3007                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3008                 qdev->req_consumer_index_phy_addr_high =
3009                     MS_64BITS(qdev->shadow_reg_phy_addr);
3010                 qdev->req_consumer_index_phy_addr_low =
3011                     LS_64BITS(qdev->shadow_reg_phy_addr);
3012
3013                 qdev->prsp_producer_index =
3014                     (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3015                 qdev->rsp_producer_index_phy_addr_high =
3016                     qdev->req_consumer_index_phy_addr_high;
3017                 qdev->rsp_producer_index_phy_addr_low =
3018                     qdev->req_consumer_index_phy_addr_low + 8;
3019         } else {
3020                 printk(KERN_ERR PFX
3021                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3022                 return -ENOMEM;
3023         }
3024
3025         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3026                 printk(KERN_ERR PFX
3027                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
3028                        qdev->ndev->name);
3029                 goto err_req_rsp;
3030         }
3031
3032         if (ql_alloc_buffer_queues(qdev) != 0) {
3033                 printk(KERN_ERR PFX
3034                        "%s: ql_alloc_buffer_queues failed.\n",
3035                        qdev->ndev->name);
3036                 goto err_buffer_queues;
3037         }
3038
3039         if (ql_alloc_small_buffers(qdev) != 0) {
3040                 printk(KERN_ERR PFX
3041                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3042                 goto err_small_buffers;
3043         }
3044
3045         if (ql_alloc_large_buffers(qdev) != 0) {
3046                 printk(KERN_ERR PFX
3047                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3048                 goto err_small_buffers;
3049         }
3050
3051         /* Initialize the large buffer queue. */
3052         ql_init_large_buffers(qdev);
3053         if (ql_create_send_free_list(qdev))
3054                 goto err_free_list;
3055
3056         qdev->rsp_current = qdev->rsp_q_virt_addr;
3057
3058         return 0;
3059 err_free_list:
3060         ql_free_send_free_list(qdev);
3061 err_small_buffers:
3062         ql_free_buffer_queues(qdev);
3063 err_buffer_queues:
3064         ql_free_net_req_rsp_queues(qdev);
3065 err_req_rsp:
3066         pci_free_consistent(qdev->pdev,
3067                             PAGE_SIZE,
3068                             qdev->shadow_reg_virt_addr,
3069                             qdev->shadow_reg_phy_addr);
3070
3071         return -ENOMEM;
3072 }
3073
3074 static void ql_free_mem_resources(struct ql3_adapter *qdev)
3075 {
3076         ql_free_send_free_list(qdev);
3077         ql_free_large_buffers(qdev);
3078         ql_free_small_buffers(qdev);
3079         ql_free_buffer_queues(qdev);
3080         ql_free_net_req_rsp_queues(qdev);
3081         if (qdev->shadow_reg_virt_addr != NULL) {
3082                 pci_free_consistent(qdev->pdev,
3083                                     PAGE_SIZE,
3084                                     qdev->shadow_reg_virt_addr,
3085                                     qdev->shadow_reg_phy_addr);
3086                 qdev->shadow_reg_virt_addr = NULL;
3087         }
3088 }
3089
3090 static int ql_init_misc_registers(struct ql3_adapter *qdev)
3091 {
3092         struct ql3xxx_local_ram_registers __iomem *local_ram =
3093             (void __iomem *)qdev->mem_map_registers;
3094
3095         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3096                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3097                          2) << 4))
3098                 return -1;
3099
3100         ql_write_page2_reg(qdev,
3101                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3102
3103         ql_write_page2_reg(qdev,
3104                            &local_ram->maxBufletCount,
3105                            qdev->nvram_data.bufletCount);
3106
3107         ql_write_page2_reg(qdev,
3108                            &local_ram->freeBufletThresholdLow,
3109                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3110                            (qdev->nvram_data.tcpWindowThreshold0));
3111
3112         ql_write_page2_reg(qdev,
3113                            &local_ram->freeBufletThresholdHigh,
3114                            qdev->nvram_data.tcpWindowThreshold50);
3115
3116         ql_write_page2_reg(qdev,
3117                            &local_ram->ipHashTableBase,
3118                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
3119                            qdev->nvram_data.ipHashTableBaseLo);
3120         ql_write_page2_reg(qdev,
3121                            &local_ram->ipHashTableCount,
3122                            qdev->nvram_data.ipHashTableSize);
3123         ql_write_page2_reg(qdev,
3124                            &local_ram->tcpHashTableBase,
3125                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3126                            qdev->nvram_data.tcpHashTableBaseLo);
3127         ql_write_page2_reg(qdev,
3128                            &local_ram->tcpHashTableCount,
3129                            qdev->nvram_data.tcpHashTableSize);
3130         ql_write_page2_reg(qdev,
3131                            &local_ram->ncbBase,
3132                            (qdev->nvram_data.ncbTableBaseHi << 16) |
3133                            qdev->nvram_data.ncbTableBaseLo);
3134         ql_write_page2_reg(qdev,
3135                            &local_ram->maxNcbCount,
3136                            qdev->nvram_data.ncbTableSize);
3137         ql_write_page2_reg(qdev,
3138                            &local_ram->drbBase,
3139                            (qdev->nvram_data.drbTableBaseHi << 16) |
3140                            qdev->nvram_data.drbTableBaseLo);
3141         ql_write_page2_reg(qdev,
3142                            &local_ram->maxDrbCount,
3143                            qdev->nvram_data.drbTableSize);
3144         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3145         return 0;
3146 }
3147
3148 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3149 {
3150         u32 value;
3151         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3152         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3153                                                 (void __iomem *)port_regs;
3154         u32 delay = 10;
3155         int status = 0;
3156
3157         if(ql_mii_setup(qdev))
3158                 return -1;
3159
3160         /* Bring out PHY out of reset */
3161         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3162                             (ISP_SERIAL_PORT_IF_WE |
3163                              (ISP_SERIAL_PORT_IF_WE << 16)));
3164
3165         qdev->port_link_state = LS_DOWN;
3166         netif_carrier_off(qdev->ndev);
3167
3168         /* V2 chip fix for ARS-39168. */
3169         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3170                             (ISP_SERIAL_PORT_IF_SDE |
3171                              (ISP_SERIAL_PORT_IF_SDE << 16)));
3172
3173         /* Request Queue Registers */
3174         *((u32 *) (qdev->preq_consumer_index)) = 0;
3175         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3176         qdev->req_producer_index = 0;
3177
3178         ql_write_page1_reg(qdev,
3179                            &hmem_regs->reqConsumerIndexAddrHigh,
3180                            qdev->req_consumer_index_phy_addr_high);
3181         ql_write_page1_reg(qdev,
3182                            &hmem_regs->reqConsumerIndexAddrLow,
3183                            qdev->req_consumer_index_phy_addr_low);
3184
3185         ql_write_page1_reg(qdev,
3186                            &hmem_regs->reqBaseAddrHigh,
3187                            MS_64BITS(qdev->req_q_phy_addr));
3188         ql_write_page1_reg(qdev,
3189                            &hmem_regs->reqBaseAddrLow,
3190                            LS_64BITS(qdev->req_q_phy_addr));
3191         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3192
3193         /* Response Queue Registers */
3194         *((__le16 *) (qdev->prsp_producer_index)) = 0;
3195         qdev->rsp_consumer_index = 0;
3196         qdev->rsp_current = qdev->rsp_q_virt_addr;
3197
3198         ql_write_page1_reg(qdev,
3199                            &hmem_regs->rspProducerIndexAddrHigh,
3200                            qdev->rsp_producer_index_phy_addr_high);
3201
3202         ql_write_page1_reg(qdev,
3203                            &hmem_regs->rspProducerIndexAddrLow,
3204                            qdev->rsp_producer_index_phy_addr_low);
3205
3206         ql_write_page1_reg(qdev,
3207                            &hmem_regs->rspBaseAddrHigh,
3208                            MS_64BITS(qdev->rsp_q_phy_addr));
3209
3210         ql_write_page1_reg(qdev,
3211                            &hmem_regs->rspBaseAddrLow,
3212                            LS_64BITS(qdev->rsp_q_phy_addr));
3213
3214         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3215
3216         /* Large Buffer Queue */
3217         ql_write_page1_reg(qdev,
3218                            &hmem_regs->rxLargeQBaseAddrHigh,
3219                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
3220
3221         ql_write_page1_reg(qdev,
3222                            &hmem_regs->rxLargeQBaseAddrLow,
3223                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
3224
3225         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3226
3227         ql_write_page1_reg(qdev,
3228                            &hmem_regs->rxLargeBufferLength,
3229                            qdev->lrg_buffer_len);
3230
3231         /* Small Buffer Queue */
3232         ql_write_page1_reg(qdev,
3233                            &hmem_regs->rxSmallQBaseAddrHigh,
3234                            MS_64BITS(qdev->small_buf_q_phy_addr));
3235
3236         ql_write_page1_reg(qdev,
3237                            &hmem_regs->rxSmallQBaseAddrLow,
3238                            LS_64BITS(qdev->small_buf_q_phy_addr));
3239
3240         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3241         ql_write_page1_reg(qdev,
3242                            &hmem_regs->rxSmallBufferLength,
3243                            QL_SMALL_BUFFER_SIZE);
3244
3245         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3246         qdev->small_buf_release_cnt = 8;
3247         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3248         qdev->lrg_buf_release_cnt = 8;
3249         qdev->lrg_buf_next_free =
3250             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3251         qdev->small_buf_index = 0;
3252         qdev->lrg_buf_index = 0;
3253         qdev->lrg_buf_free_count = 0;
3254         qdev->lrg_buf_free_head = NULL;
3255         qdev->lrg_buf_free_tail = NULL;
3256
3257         ql_write_common_reg(qdev,
3258                             &port_regs->CommonRegs.
3259                             rxSmallQProducerIndex,
3260                             qdev->small_buf_q_producer_index);
3261         ql_write_common_reg(qdev,
3262                             &port_regs->CommonRegs.
3263                             rxLargeQProducerIndex,
3264                             qdev->lrg_buf_q_producer_index);
3265
3266         /*
3267          * Find out if the chip has already been initialized.  If it has, then
3268          * we skip some of the initialization.
3269          */
3270         clear_bit(QL_LINK_MASTER, &qdev->flags);
3271         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3272         if ((value & PORT_STATUS_IC) == 0) {
3273
3274                 /* Chip has not been configured yet, so let it rip. */
3275                 if(ql_init_misc_registers(qdev)) {
3276                         status = -1;
3277                         goto out;
3278                 }
3279
3280                 value = qdev->nvram_data.tcpMaxWindowSize;
3281                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3282
3283                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3284
3285                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3286                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3287                                  * 2) << 13)) {
3288                         status = -1;
3289                         goto out;
3290                 }
3291                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3292                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3293                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3294                                      16) | (INTERNAL_CHIP_SD |
3295                                             INTERNAL_CHIP_WE)));
3296                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3297         }
3298
3299         if (qdev->mac_index)
3300                 ql_write_page0_reg(qdev,
3301                                    &port_regs->mac1MaxFrameLengthReg,
3302                                    qdev->max_frame_size);
3303         else
3304                 ql_write_page0_reg(qdev,
3305                                            &port_regs->mac0MaxFrameLengthReg,
3306                                            qdev->max_frame_size);
3307
3308         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3309                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3310                          2) << 7)) {
3311                 status = -1;
3312                 goto out;
3313         }
3314
3315         PHY_Setup(qdev);
3316         ql_init_scan_mode(qdev);
3317         ql_get_phy_owner(qdev);
3318
3319         /* Load the MAC Configuration */
3320
3321         /* Program lower 32 bits of the MAC address */
3322         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3323                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3324         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3325                            ((qdev->ndev->dev_addr[2] << 24)
3326                             | (qdev->ndev->dev_addr[3] << 16)
3327                             | (qdev->ndev->dev_addr[4] << 8)
3328                             | qdev->ndev->dev_addr[5]));
3329
3330         /* Program top 16 bits of the MAC address */
3331         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3332                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3333         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3334                            ((qdev->ndev->dev_addr[0] << 8)
3335                             | qdev->ndev->dev_addr[1]));
3336
3337         /* Enable Primary MAC */
3338         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3339                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3340                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3341
3342         /* Clear Primary and Secondary IP addresses */
3343         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3344                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3345                             (qdev->mac_index << 2)));
3346         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3347
3348         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3349                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3350                             ((qdev->mac_index << 2) + 1)));
3351         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3352
3353         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3354
3355         /* Indicate Configuration Complete */
3356         ql_write_page0_reg(qdev,
3357                            &port_regs->portControl,
3358                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3359
3360         do {
3361                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3362                 if (value & PORT_STATUS_IC)
3363                         break;
3364                 msleep(500);
3365         } while (--delay);
3366
3367         if (delay == 0) {
3368                 printk(KERN_ERR PFX
3369                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3370                 status = -1;
3371                 goto out;
3372         }
3373
3374         /* Enable Ethernet Function */
3375         if (qdev->device_id == QL3032_DEVICE_ID) {
3376                 value =
3377                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3378                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3379                         QL3032_PORT_CONTROL_ET);
3380                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3381                                    ((value << 16) | value));
3382         } else {
3383                 value =
3384                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3385                      PORT_CONTROL_HH);
3386                 ql_write_page0_reg(qdev, &port_regs->portControl,
3387                                    ((value << 16) | value));
3388         }
3389
3390
3391 out:
3392         return status;
3393 }
3394
3395 /*
3396  * Caller holds hw_lock.
3397  */
3398 static int ql_adapter_reset(struct ql3_adapter *qdev)
3399 {
3400         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3401         int status = 0;
3402         u16 value;
3403         int max_wait_time;
3404
3405         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3406         clear_bit(QL_RESET_DONE, &qdev->flags);
3407
3408         /*
3409          * Issue soft reset to chip.
3410          */
3411         printk(KERN_DEBUG PFX
3412                "%s: Issue soft reset to chip.\n",
3413                qdev->ndev->name);
3414         ql_write_common_reg(qdev,
3415                             &port_regs->CommonRegs.ispControlStatus,
3416                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3417
3418         /* Wait 3 seconds for reset to complete. */
3419         printk(KERN_DEBUG PFX
3420                "%s: Wait 10 milliseconds for reset to complete.\n",
3421                qdev->ndev->name);
3422
3423         /* Wait until the firmware tells us the Soft Reset is done */
3424         max_wait_time = 5;
3425         do {
3426                 value =
3427                     ql_read_common_reg(qdev,
3428                                        &port_regs->CommonRegs.ispControlStatus);
3429                 if ((value & ISP_CONTROL_SR) == 0)
3430                         break;
3431
3432                 ssleep(1);
3433         } while ((--max_wait_time));
3434
3435         /*
3436          * Also, make sure that the Network Reset Interrupt bit has been
3437          * cleared after the soft reset has taken place.
3438          */
3439         value =
3440             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3441         if (value & ISP_CONTROL_RI) {
3442                 printk(KERN_DEBUG PFX
3443                        "ql_adapter_reset: clearing RI after reset.\n");
3444                 ql_write_common_reg(qdev,
3445                                     &port_regs->CommonRegs.
3446                                     ispControlStatus,
3447                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3448         }
3449
3450         if (max_wait_time == 0) {
3451                 /* Issue Force Soft Reset */
3452                 ql_write_common_reg(qdev,
3453                                     &port_regs->CommonRegs.
3454                                     ispControlStatus,
3455                                     ((ISP_CONTROL_FSR << 16) |
3456                                      ISP_CONTROL_FSR));
3457                 /*
3458                  * Wait until the firmware tells us the Force Soft Reset is
3459                  * done
3460                  */
3461                 max_wait_time = 5;
3462                 do {
3463                         value =
3464                             ql_read_common_reg(qdev,
3465                                                &port_regs->CommonRegs.
3466                                                ispControlStatus);
3467                         if ((value & ISP_CONTROL_FSR) == 0) {
3468                                 break;
3469                         }
3470                         ssleep(1);
3471                 } while ((--max_wait_time));
3472         }
3473         if (max_wait_time == 0)
3474                 status = 1;
3475
3476         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3477         set_bit(QL_RESET_DONE, &qdev->flags);
3478         return status;
3479 }
3480
3481 static void ql_set_mac_info(struct ql3_adapter *qdev)
3482 {
3483         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3484         u32 value, port_status;
3485         u8 func_number;
3486
3487         /* Get the function number */
3488         value =
3489             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3490         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3491         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3492         switch (value & ISP_CONTROL_FN_MASK) {
3493         case ISP_CONTROL_FN0_NET:
3494                 qdev->mac_index = 0;
3495                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3496                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3497                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3498                 if (port_status & PORT_STATUS_SM0)
3499                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3500                 else
3501                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3502                 break;
3503
3504         case ISP_CONTROL_FN1_NET:
3505                 qdev->mac_index = 1;
3506                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3507                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3508                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3509                 if (port_status & PORT_STATUS_SM1)
3510                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3511                 else
3512                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3513                 break;
3514
3515         case ISP_CONTROL_FN0_SCSI:
3516         case ISP_CONTROL_FN1_SCSI:
3517         default:
3518                 printk(KERN_DEBUG PFX
3519                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3520                        qdev->ndev->name,value);
3521                 break;
3522         }
3523         qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3524 }
3525
3526 static void ql_display_dev_info(struct net_device *ndev)
3527 {
3528         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3529         struct pci_dev *pdev = qdev->pdev;
3530
3531         printk(KERN_INFO PFX
3532                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3533                DRV_NAME, qdev->index, qdev->chip_rev_id,
3534                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3535                qdev->pci_slot);
3536         printk(KERN_INFO PFX
3537                "%s Interface.\n",
3538                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3539
3540         /*
3541          * Print PCI bus width/type.
3542          */
3543         printk(KERN_INFO PFX
3544                "Bus interface is %s %s.\n",
3545                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3546                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3547
3548         printk(KERN_INFO PFX
3549                "mem  IO base address adjusted = 0x%p\n",
3550                qdev->mem_map_registers);
3551         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3552
3553         if (netif_msg_probe(qdev))
3554                 printk(KERN_INFO PFX
3555                        "%s: MAC address %pM\n",
3556                        ndev->name, ndev->dev_addr);
3557 }
3558
3559 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3560 {
3561         struct net_device *ndev = qdev->ndev;
3562         int retval = 0;
3563
3564         netif_stop_queue(ndev);
3565         netif_carrier_off(ndev);
3566
3567         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3568         clear_bit(QL_LINK_MASTER,&qdev->flags);
3569
3570         ql_disable_interrupts(qdev);
3571
3572         free_irq(qdev->pdev->irq, ndev);
3573
3574         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3575                 printk(KERN_INFO PFX
3576                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3577                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3578                 pci_disable_msi(qdev->pdev);
3579         }
3580
3581         del_timer_sync(&qdev->adapter_timer);
3582
3583         napi_disable(&qdev->napi);
3584
3585         if (do_reset) {
3586                 int soft_reset;
3587                 unsigned long hw_flags;
3588
3589                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3590                 if (ql_wait_for_drvr_lock(qdev)) {
3591                         if ((soft_reset = ql_adapter_reset(qdev))) {
3592                                 printk(KERN_ERR PFX
3593                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3594                                        ndev->name, qdev->index);
3595                         }
3596                         printk(KERN_ERR PFX
3597                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3598                 } else {
3599                         printk(KERN_ERR PFX
3600                                "%s: Could not acquire driver lock to do "
3601                                "reset!\n", ndev->name);
3602                         retval = -1;
3603                 }
3604                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3605         }
3606         ql_free_mem_resources(qdev);
3607         return retval;
3608 }
3609
3610 static int ql_adapter_up(struct ql3_adapter *qdev)
3611 {
3612         struct net_device *ndev = qdev->ndev;
3613         int err;
3614         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3615         unsigned long hw_flags;
3616
3617         if (ql_alloc_mem_resources(qdev)) {
3618                 printk(KERN_ERR PFX
3619                        "%s Unable to  allocate buffers.\n", ndev->name);
3620                 return -ENOMEM;
3621         }
3622
3623         if (qdev->msi) {
3624                 if (pci_enable_msi(qdev->pdev)) {
3625                         printk(KERN_ERR PFX
3626                                "%s: User requested MSI, but MSI failed to "
3627                                "initialize.  Continuing without MSI.\n",
3628                                qdev->ndev->name);
3629                         qdev->msi = 0;
3630                 } else {
3631                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3632                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3633                         irq_flags &= ~IRQF_SHARED;
3634                 }
3635         }
3636
3637         if ((err = request_irq(qdev->pdev->irq,
3638                                ql3xxx_isr,
3639                                irq_flags, ndev->name, ndev))) {
3640                 printk(KERN_ERR PFX
3641                        "%s: Failed to reserve interrupt %d already in use.\n",
3642                        ndev->name, qdev->pdev->irq);
3643                 goto err_irq;
3644         }
3645
3646         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3647
3648         if ((err = ql_wait_for_drvr_lock(qdev))) {
3649                 if ((err = ql_adapter_initialize(qdev))) {
3650                         printk(KERN_ERR PFX
3651                                "%s: Unable to initialize adapter.\n",
3652                                ndev->name);
3653                         goto err_init;
3654                 }
3655                 printk(KERN_ERR PFX
3656                                 "%s: Releaseing driver lock.\n",ndev->name);
3657                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3658         } else {
3659                 printk(KERN_ERR PFX
3660                        "%s: Could not aquire driver lock.\n",
3661                        ndev->name);
3662                 goto err_lock;
3663         }
3664
3665         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3666
3667         set_bit(QL_ADAPTER_UP,&qdev->flags);
3668
3669         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3670
3671         napi_enable(&qdev->napi);
3672         ql_enable_interrupts(qdev);
3673         return 0;
3674
3675 err_init:
3676         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3677 err_lock:
3678         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3679         free_irq(qdev->pdev->irq, ndev);
3680 err_irq:
3681         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3682                 printk(KERN_INFO PFX
3683                        "%s: calling pci_disable_msi().\n",
3684                        qdev->ndev->name);
3685                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3686                 pci_disable_msi(qdev->pdev);
3687         }
3688         return err;
3689 }
3690
3691 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3692 {
3693         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3694                 printk(KERN_ERR PFX
3695                                 "%s: Driver up/down cycle failed, "
3696                                 "closing device\n",qdev->ndev->name);
3697                 rtnl_lock();
3698                 dev_close(qdev->ndev);
3699                 rtnl_unlock();
3700                 return -1;
3701         }
3702         return 0;
3703 }
3704
3705 static int ql3xxx_close(struct net_device *ndev)
3706 {
3707         struct ql3_adapter *qdev = netdev_priv(ndev);
3708
3709         /*
3710          * Wait for device to recover from a reset.
3711          * (Rarely happens, but possible.)
3712          */
3713         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3714                 msleep(50);
3715
3716         ql_adapter_down(qdev,QL_DO_RESET);
3717         return 0;
3718 }
3719
3720 static int ql3xxx_open(struct net_device *ndev)
3721 {
3722         struct ql3_adapter *qdev = netdev_priv(ndev);
3723         return (ql_adapter_up(qdev));
3724 }
3725
3726 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3727 {
3728         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3729         struct ql3xxx_port_registers __iomem *port_regs =
3730                         qdev->mem_map_registers;
3731         struct sockaddr *addr = p;
3732         unsigned long hw_flags;
3733
3734         if (netif_running(ndev))
3735                 return -EBUSY;
3736
3737         if (!is_valid_ether_addr(addr->sa_data))
3738                 return -EADDRNOTAVAIL;
3739
3740         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3741
3742         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3743         /* Program lower 32 bits of the MAC address */
3744         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3745                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3746         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3747                            ((ndev->dev_addr[2] << 24) | (ndev->
3748                                                          dev_addr[3] << 16) |
3749                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3750
3751         /* Program top 16 bits of the MAC address */
3752         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3753                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3754         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3755                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3756         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3757
3758         return 0;
3759 }
3760
3761 static void ql3xxx_tx_timeout(struct net_device *ndev)
3762 {
3763         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3764
3765         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3766         /*
3767          * Stop the queues, we've got a problem.
3768          */
3769         netif_stop_queue(ndev);
3770
3771         /*
3772          * Wake up the worker to process this event.
3773          */
3774         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3775 }
3776
3777 static void ql_reset_work(struct work_struct *work)
3778 {
3779         struct ql3_adapter *qdev =
3780                 container_of(work, struct ql3_adapter, reset_work.work);
3781         struct net_device *ndev = qdev->ndev;
3782         u32 value;
3783         struct ql_tx_buf_cb *tx_cb;
3784         int max_wait_time, i;
3785         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3786         unsigned long hw_flags;
3787
3788         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3789                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3790
3791                 /*
3792                  * Loop through the active list and return the skb.
3793                  */
3794                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3795                         int j;
3796                         tx_cb = &qdev->tx_buf[i];
3797                         if (tx_cb->skb) {
3798                                 printk(KERN_DEBUG PFX
3799                                        "%s: Freeing lost SKB.\n",
3800                                        qdev->ndev->name);
3801                                 pci_unmap_single(qdev->pdev,
3802                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3803                                          pci_unmap_len(&tx_cb->map[0], maplen),
3804                                          PCI_DMA_TODEVICE);
3805                                 for(j=1;j<tx_cb->seg_count;j++) {
3806                                         pci_unmap_page(qdev->pdev,
3807                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3808                                                pci_unmap_len(&tx_cb->map[j],maplen),
3809                                                PCI_DMA_TODEVICE);
3810                                 }
3811                                 dev_kfree_skb(tx_cb->skb);
3812                                 tx_cb->skb = NULL;
3813                         }
3814                 }
3815
3816                 printk(KERN_ERR PFX
3817                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3818                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3819                 ql_write_common_reg(qdev,
3820                                     &port_regs->CommonRegs.
3821                                     ispControlStatus,
3822                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3823                 /*
3824                  * Wait the for Soft Reset to Complete.
3825                  */
3826                 max_wait_time = 10;
3827                 do {
3828                         value = ql_read_common_reg(qdev,
3829                                                    &port_regs->CommonRegs.
3830
3831                                                    ispControlStatus);
3832                         if ((value & ISP_CONTROL_SR) == 0) {
3833                                 printk(KERN_DEBUG PFX
3834                                        "%s: reset completed.\n",
3835                                        qdev->ndev->name);
3836                                 break;
3837                         }
3838
3839                         if (value & ISP_CONTROL_RI) {
3840                                 printk(KERN_DEBUG PFX
3841                                        "%s: clearing NRI after reset.\n",
3842                                        qdev->ndev->name);
3843                                 ql_write_common_reg(qdev,
3844                                                     &port_regs->
3845                                                     CommonRegs.
3846                                                     ispControlStatus,
3847                                                     ((ISP_CONTROL_RI <<
3848                                                       16) | ISP_CONTROL_RI));
3849                         }
3850
3851                         ssleep(1);
3852                 } while (--max_wait_time);
3853                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3854
3855                 if (value & ISP_CONTROL_SR) {
3856
3857                         /*
3858                          * Set the reset flags and clear the board again.
3859                          * Nothing else to do...
3860                          */
3861                         printk(KERN_ERR PFX
3862                                "%s: Timed out waiting for reset to "
3863                                "complete.\n", ndev->name);
3864                         printk(KERN_ERR PFX
3865                                "%s: Do a reset.\n", ndev->name);
3866                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3867                         clear_bit(QL_RESET_START,&qdev->flags);
3868                         ql_cycle_adapter(qdev,QL_DO_RESET);
3869                         return;
3870                 }
3871
3872                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3873                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3874                 clear_bit(QL_RESET_START,&qdev->flags);
3875                 ql_cycle_adapter(qdev,QL_NO_RESET);
3876         }
3877 }
3878
3879 static void ql_tx_timeout_work(struct work_struct *work)
3880 {
3881         struct ql3_adapter *qdev =
3882                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3883
3884         ql_cycle_adapter(qdev, QL_DO_RESET);
3885 }
3886
3887 static void ql_get_board_info(struct ql3_adapter *qdev)
3888 {
3889         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3890         u32 value;
3891
3892         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3893
3894         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3895         if (value & PORT_STATUS_64)
3896                 qdev->pci_width = 64;
3897         else
3898                 qdev->pci_width = 32;
3899         if (value & PORT_STATUS_X)
3900                 qdev->pci_x = 1;
3901         else
3902                 qdev->pci_x = 0;
3903         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3904 }
3905
3906 static void ql3xxx_timer(unsigned long ptr)
3907 {
3908         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3909         queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3910 }
3911
3912 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3913                                   const struct pci_device_id *pci_entry)
3914 {
3915         struct net_device *ndev = NULL;
3916         struct ql3_adapter *qdev = NULL;
3917         static int cards_found = 0;
3918         int pci_using_dac, err;
3919
3920         err = pci_enable_device(pdev);
3921         if (err) {
3922                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3923                        pci_name(pdev));
3924                 goto err_out;
3925         }
3926
3927         err = pci_request_regions(pdev, DRV_NAME);
3928         if (err) {
3929                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3930                        pci_name(pdev));
3931                 goto err_out_disable_pdev;
3932         }
3933
3934         pci_set_master(pdev);
3935
3936         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3937                 pci_using_dac = 1;
3938                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3939         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3940                 pci_using_dac = 0;
3941                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3942         }
3943
3944         if (err) {
3945                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3946                        pci_name(pdev));
3947                 goto err_out_free_regions;
3948         }
3949
3950         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3951         if (!ndev) {
3952                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3953                        pci_name(pdev));
3954                 err = -ENOMEM;
3955                 goto err_out_free_regions;
3956         }
3957
3958         SET_NETDEV_DEV(ndev, &pdev->dev);
3959
3960         pci_set_drvdata(pdev, ndev);
3961
3962         qdev = netdev_priv(ndev);
3963         qdev->index = cards_found;
3964         qdev->ndev = ndev;
3965         qdev->pdev = pdev;
3966         qdev->device_id = pci_entry->device;
3967         qdev->port_link_state = LS_DOWN;
3968         if (msi)
3969                 qdev->msi = 1;
3970
3971         qdev->msg_enable = netif_msg_init(debug, default_msg);
3972
3973         if (pci_using_dac)
3974                 ndev->features |= NETIF_F_HIGHDMA;
3975         if (qdev->device_id == QL3032_DEVICE_ID)
3976                 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3977
3978         qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3979         if (!qdev->mem_map_registers) {
3980                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3981                        pci_name(pdev));
3982                 err = -EIO;
3983                 goto err_out_free_ndev;
3984         }
3985
3986         spin_lock_init(&qdev->adapter_lock);
3987         spin_lock_init(&qdev->hw_lock);
3988
3989         /* Set driver entry points */
3990         ndev->open = ql3xxx_open;
3991         ndev->hard_start_xmit = ql3xxx_send;
3992         ndev->stop = ql3xxx_close;
3993         /* ndev->set_multicast_list
3994          * This device is one side of a two-function adapter
3995          * (NIC and iSCSI).  Promiscuous mode setting/clearing is
3996          * not allowed from the NIC side.
3997          */
3998         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3999         ndev->set_mac_address = ql3xxx_set_mac_address;
4000         ndev->tx_timeout = ql3xxx_tx_timeout;
4001         ndev->watchdog_timeo = 5 * HZ;
4002
4003         netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
4004
4005         ndev->irq = pdev->irq;
4006
4007         /* make sure the EEPROM is good */
4008         if (ql_get_nvram_params(qdev)) {
4009                 printk(KERN_ALERT PFX
4010                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4011                        qdev->index);
4012                 err = -EIO;
4013                 goto err_out_iounmap;
4014         }
4015
4016         ql_set_mac_info(qdev);
4017
4018         /* Validate and set parameters */
4019         if (qdev->mac_index) {
4020                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4021                 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
4022         } else {
4023                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4024                 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
4025         }
4026         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4027
4028         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4029
4030         /* Record PCI bus information. */
4031         ql_get_board_info(qdev);
4032
4033         /*
4034          * Set the Maximum Memory Read Byte Count value. We do this to handle
4035          * jumbo frames.
4036          */
4037         if (qdev->pci_x) {
4038                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4039         }
4040
4041         err = register_netdev(ndev);
4042         if (err) {
4043                 printk(KERN_ERR PFX "%s: cannot register net device\n",
4044                        pci_name(pdev));
4045                 goto err_out_iounmap;
4046         }
4047
4048         /* we're going to reset, so assume we have no link for now */
4049
4050         netif_carrier_off(ndev);
4051         netif_stop_queue(ndev);
4052
4053         qdev->workqueue = create_singlethread_workqueue(ndev->name);
4054         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4055         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4056         INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
4057
4058         init_timer(&qdev->adapter_timer);
4059         qdev->adapter_timer.function = ql3xxx_timer;
4060         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4061         qdev->adapter_timer.data = (unsigned long)qdev;
4062
4063         if(!cards_found) {
4064                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4065                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4066                    DRV_NAME, DRV_VERSION);
4067         }
4068         ql_display_dev_info(ndev);
4069
4070         cards_found++;
4071         return 0;
4072
4073 err_out_iounmap:
4074         iounmap(qdev->mem_map_registers);
4075 err_out_free_ndev:
4076         free_netdev(ndev);
4077 err_out_free_regions:
4078         pci_release_regions(pdev);
4079 err_out_disable_pdev:
4080         pci_disable_device(pdev);
4081         pci_set_drvdata(pdev, NULL);
4082 err_out:
4083         return err;
4084 }
4085
4086 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4087 {
4088         struct net_device *ndev = pci_get_drvdata(pdev);
4089         struct ql3_adapter *qdev = netdev_priv(ndev);
4090
4091         unregister_netdev(ndev);
4092         qdev = netdev_priv(ndev);
4093
4094         ql_disable_interrupts(qdev);
4095
4096         if (qdev->workqueue) {
4097                 cancel_delayed_work(&qdev->reset_work);
4098                 cancel_delayed_work(&qdev->tx_timeout_work);
4099                 destroy_workqueue(qdev->workqueue);
4100                 qdev->workqueue = NULL;
4101         }
4102
4103         iounmap(qdev->mem_map_registers);
4104         pci_release_regions(pdev);
4105         pci_set_drvdata(pdev, NULL);
4106         free_netdev(ndev);
4107 }
4108
4109 static struct pci_driver ql3xxx_driver = {
4110
4111         .name = DRV_NAME,
4112         .id_table = ql3xxx_pci_tbl,
4113         .probe = ql3xxx_probe,
4114         .remove = __devexit_p(ql3xxx_remove),
4115 };
4116
4117 static int __init ql3xxx_init_module(void)
4118 {
4119         return pci_register_driver(&ql3xxx_driver);
4120 }
4121
4122 static void __exit ql3xxx_exit(void)
4123 {
4124         pci_unregister_driver(&ql3xxx_driver);
4125 }
4126
4127 module_init(ql3xxx_init_module);
4128 module_exit(ql3xxx_exit);