drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define DRV_NAME        "pcnet32"
  25 #ifdef CONFIG_PCNET32_NAPI
  26 #define DRV_VERSION     "1.34-NAPI"
  27 #else
  28 #define DRV_VERSION     "1.34"
  29 #endif
  30 #define DRV_RELDATE     "14.Aug.2007"
  31 #define PFX             DRV_NAME ": "
  32
  33 static const char *const version =
  34     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  35
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/string.h>
  39 #include <linux/errno.h>
  40 #include <linux/ioport.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/delay.h>
  45 #include <linux/init.h>
  46 #include <linux/ethtool.h>
  47 #include <linux/mii.h>
  48 #include <linux/crc32.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/skbuff.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/bitops.h>
  55
  56 #include <asm/dma.h>
  57 #include <asm/io.h>
  58 #include <asm/uaccess.h>
  59 #include <asm/irq.h>
  60
  61 /*
  62  * PCI device identifiers for "new style" Linux PCI Device Drivers
  63  */
  64 static struct pci_device_id pcnet32_pci_tbl[] = {
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68         /*
  69          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70          * the incorrect vendor id.
  71          */
  72         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75         { }     /* terminate list */
  76 };
  77
  78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80 static int cards_found;
  81
  82 /*
  83  * VLB I/O addresses
  84  */
  85 static unsigned int pcnet32_portlist[] __initdata =
  86     { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88 static int pcnet32_debug = 0;
  89 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90 static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92 static struct net_device *pcnet32_dev;
  93
  94 static int max_interrupt_work = 2;
  95 static int rx_copybreak = 200;
  96
  97 #define PCNET32_PORT_AUI      0x00
  98 #define PCNET32_PORT_10BT     0x01
  99 #define PCNET32_PORT_GPSI     0x02
 100 #define PCNET32_PORT_MII      0x03
 101
 102 #define PCNET32_PORT_PORTSEL  0x03
 103 #define PCNET32_PORT_ASEL     0x04
 104 #define PCNET32_PORT_100      0x40
 105 #define PCNET32_PORT_FD       0x80
 106
 107 #define PCNET32_DMA_MASK 0xffffffff
 108
 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112 /*
 113  * table to translate option values from tulip
 114  * to internal options
 115  */
 116 static const unsigned char options_mapping[] = {
 117         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                 /* 14 MII 100BaseTx-FD */
 132         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133         PCNET32_PORT_ASEL                       /* 15 not supported    */
 134 };
 135
 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Loopback test  (offline)"
 138 };
 139
 140 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
 141
 142 #define PCNET32_NUM_REGS 136
 143
 144 #define MAX_UNITS 8             /* More are supported, limit only on options */
 145 static int options[MAX_UNITS];
 146 static int full_duplex[MAX_UNITS];
 147 static int homepna[MAX_UNITS];
 148
 149 /*
 150  *                              Theory of Operation
 151  *
 152  * This driver uses the same software structure as the normal lance
 153  * driver. So look for a verbose description in lance.c. The differences
 154  * to the normal lance driver is the use of the 32bit mode of PCnet32
 155  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156  * 16MB limitation and we don't need bounce buffers.
 157  */
 158
 159 /*
 160  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163  */
 164 #ifndef PCNET32_LOG_TX_BUFFERS
 165 #define PCNET32_LOG_TX_BUFFERS          4
 166 #define PCNET32_LOG_RX_BUFFERS          5
 167 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 169 #endif
 170
 171 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177 #define PKT_BUF_SZ              1544
 178
 179 /* Offsets from base I/O address. */
 180 #define PCNET32_WIO_RDP         0x10
 181 #define PCNET32_WIO_RAP         0x12
 182 #define PCNET32_WIO_RESET       0x14
 183 #define PCNET32_WIO_BDP         0x16
 184
 185 #define PCNET32_DWIO_RDP        0x10
 186 #define PCNET32_DWIO_RAP        0x14
 187 #define PCNET32_DWIO_RESET      0x18
 188 #define PCNET32_DWIO_BDP        0x1C
 189
 190 #define PCNET32_TOTAL_SIZE      0x20
 191
 192 #define CSR0            0
 193 #define CSR0_INIT       0x1
 194 #define CSR0_START      0x2
 195 #define CSR0_STOP       0x4
 196 #define CSR0_TXPOLL     0x8
 197 #define CSR0_INTEN      0x40
 198 #define CSR0_IDON       0x0100
 199 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 200 #define PCNET32_INIT_LOW        1
 201 #define PCNET32_INIT_HIGH       2
 202 #define CSR3            3
 203 #define CSR4            4
 204 #define CSR5            5
 205 #define CSR5_SUSPEND    0x0001
 206 #define CSR15           15
 207 #define PCNET32_MC_FILTER       8
 208
 209 #define PCNET32_79C970A 0x2621
 210
 211 /* The PCNET32 Rx and Tx ring descriptors. */
 212 struct pcnet32_rx_head {
 213         __le32  base;
 214         __le16  buf_length;     /* two`s complement of length */
 215         __le16  status;
 216         __le32  msg_length;
 217         __le32  reserved;
 218 };
 219
 220 struct pcnet32_tx_head {
 221         __le32  base;
 222         __le16  length;         /* two`s complement of length */
 223         __le16  status;
 224         __le32  misc;
 225         __le32  reserved;
 226 };
 227
 228 /* The PCNET32 32-Bit initialization block, described in databook. */
 229 struct pcnet32_init_block {
 230         __le16  mode;
 231         __le16  tlen_rlen;
 232         u8      phys_addr[6];
 233         __le16  reserved;
 234         __le32  filter[2];
 235         /* Receive and transmit ring base, along with extra bits. */
 236         __le32  rx_ring;
 237         __le32  tx_ring;
 238 };
 239
 240 /* PCnet32 access functions */
 241 struct pcnet32_access {
 242         u16     (*read_csr) (unsigned long, int);
 243         void    (*write_csr) (unsigned long, int, u16);
 244         u16     (*read_bcr) (unsigned long, int);
 245         void    (*write_bcr) (unsigned long, int, u16);
 246         u16     (*read_rap) (unsigned long);
 247         void    (*write_rap) (unsigned long, u16);
 248         void    (*reset) (unsigned long);
 249 };
 250
 251 /*
 252  * The first field of pcnet32_private is read by the ethernet device
 253  * so the structure should be allocated using pci_alloc_consistent().
 254  */
 255 struct pcnet32_private {
 256         struct pcnet32_init_block *init_block;
 257         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 258         struct pcnet32_rx_head  *rx_ring;
 259         struct pcnet32_tx_head  *tx_ring;
 260         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 261                                    returned by pci_alloc_consistent */
 262         struct pci_dev          *pci_dev;
 263         const char              *name;
 264         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 265         struct sk_buff          **tx_skbuff;
 266         struct sk_buff          **rx_skbuff;
 267         dma_addr_t              *tx_dma_addr;
 268         dma_addr_t              *rx_dma_addr;
 269         struct pcnet32_access   a;
 270         spinlock_t              lock;           /* Guard lock */
 271         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 272         unsigned int            rx_ring_size;   /* current rx ring size */
 273         unsigned int            tx_ring_size;   /* current tx ring size */
 274         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 275         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 276         unsigned short          rx_len_bits;
 277         unsigned short          tx_len_bits;
 278         dma_addr_t              rx_ring_dma_addr;
 279         dma_addr_t              tx_ring_dma_addr;
 280         unsigned int            dirty_rx,       /* ring entries to be freed. */
 281                                 dirty_tx;
 282
 283         struct net_device       *dev;
 284         struct napi_struct      napi;
 285         char                    tx_full;
 286         char                    phycount;       /* number of phys found */
 287         int                     options;
 288         unsigned int            shared_irq:1,   /* shared irq possible */
 289                                 dxsuflo:1,   /* disable transmit stop on uflo */
 290                                 mii:1;          /* mii port available */
 291         struct net_device       *next;
 292         struct mii_if_info      mii_if;
 293         struct timer_list       watchdog_timer;
 294         struct timer_list       blink_timer;
 295         u32                     msg_enable;     /* debug message level */
 296
 297         /* each bit indicates an available PHY */
 298         u32                     phymask;
 299         unsigned short          chip_version;   /* which variant this is */
 300 };
 301
 302 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 303 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 304 static int pcnet32_open(struct net_device *);
 305 static int pcnet32_init_ring(struct net_device *);
 306 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
 307 static void pcnet32_tx_timeout(struct net_device *dev);
 308 static irqreturn_t pcnet32_interrupt(int, void *);
 309 static int pcnet32_close(struct net_device *);
 310 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 311 static void pcnet32_load_multicast(struct net_device *dev);
 312 static void pcnet32_set_multicast_list(struct net_device *);
 313 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 314 static void pcnet32_watchdog(struct net_device *);
 315 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 316 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 317                        int val);
 318 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 319 static void pcnet32_ethtool_test(struct net_device *dev,
 320                                  struct ethtool_test *eth_test, u64 * data);
 321 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 322 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 323 static void pcnet32_led_blink_callback(struct net_device *dev);
 324 static int pcnet32_get_regs_len(struct net_device *dev);
 325 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 326                              void *ptr);
 327 static void pcnet32_purge_tx_ring(struct net_device *dev);
 328 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
 329 static void pcnet32_free_ring(struct net_device *dev);
 330 static void pcnet32_check_media(struct net_device *dev, int verbose);
 331
 332 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 333 {
 334         outw(index, addr + PCNET32_WIO_RAP);
 335         return inw(addr + PCNET32_WIO_RDP);
 336 }
 337
 338 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 339 {
 340         outw(index, addr + PCNET32_WIO_RAP);
 341         outw(val, addr + PCNET32_WIO_RDP);
 342 }
 343
 344 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 345 {
 346         outw(index, addr + PCNET32_WIO_RAP);
 347         return inw(addr + PCNET32_WIO_BDP);
 348 }
 349
 350 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 351 {
 352         outw(index, addr + PCNET32_WIO_RAP);
 353         outw(val, addr + PCNET32_WIO_BDP);
 354 }
 355
 356 static u16 pcnet32_wio_read_rap(unsigned long addr)
 357 {
 358         return inw(addr + PCNET32_WIO_RAP);
 359 }
 360
 361 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 362 {
 363         outw(val, addr + PCNET32_WIO_RAP);
 364 }
 365
 366 static void pcnet32_wio_reset(unsigned long addr)
 367 {
 368         inw(addr + PCNET32_WIO_RESET);
 369 }
 370
 371 static int pcnet32_wio_check(unsigned long addr)
 372 {
 373         outw(88, addr + PCNET32_WIO_RAP);
 374         return (inw(addr + PCNET32_WIO_RAP) == 88);
 375 }
 376
 377 static struct pcnet32_access pcnet32_wio = {
 378         .read_csr = pcnet32_wio_read_csr,
 379         .write_csr = pcnet32_wio_write_csr,
 380         .read_bcr = pcnet32_wio_read_bcr,
 381         .write_bcr = pcnet32_wio_write_bcr,
 382         .read_rap = pcnet32_wio_read_rap,
 383         .write_rap = pcnet32_wio_write_rap,
 384         .reset = pcnet32_wio_reset
 385 };
 386
 387 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 388 {
 389         outl(index, addr + PCNET32_DWIO_RAP);
 390         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 391 }
 392
 393 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 394 {
 395         outl(index, addr + PCNET32_DWIO_RAP);
 396         outl(val, addr + PCNET32_DWIO_RDP);
 397 }
 398
 399 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 400 {
 401         outl(index, addr + PCNET32_DWIO_RAP);
 402         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 403 }
 404
 405 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 406 {
 407         outl(index, addr + PCNET32_DWIO_RAP);
 408         outl(val, addr + PCNET32_DWIO_BDP);
 409 }
 410
 411 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 412 {
 413         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 414 }
 415
 416 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 417 {
 418         outl(val, addr + PCNET32_DWIO_RAP);
 419 }
 420
 421 static void pcnet32_dwio_reset(unsigned long addr)
 422 {
 423         inl(addr + PCNET32_DWIO_RESET);
 424 }
 425
 426 static int pcnet32_dwio_check(unsigned long addr)
 427 {
 428         outl(88, addr + PCNET32_DWIO_RAP);
 429         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 430 }
 431
 432 static struct pcnet32_access pcnet32_dwio = {
 433         .read_csr = pcnet32_dwio_read_csr,
 434         .write_csr = pcnet32_dwio_write_csr,
 435         .read_bcr = pcnet32_dwio_read_bcr,
 436         .write_bcr = pcnet32_dwio_write_bcr,
 437         .read_rap = pcnet32_dwio_read_rap,
 438         .write_rap = pcnet32_dwio_write_rap,
 439         .reset = pcnet32_dwio_reset
 440 };
 441
 442 static void pcnet32_netif_stop(struct net_device *dev)
 443 {
 444 #ifdef CONFIG_PCNET32_NAPI
 445         struct pcnet32_private *lp = netdev_priv(dev);
 446 #endif
 447         dev->trans_start = jiffies;
 448 #ifdef CONFIG_PCNET32_NAPI
 449         napi_disable(&lp->napi);
 450 #endif
 451         netif_tx_disable(dev);
 452 }
 453
 454 static void pcnet32_netif_start(struct net_device *dev)
 455 {
 456 #ifdef CONFIG_PCNET32_NAPI
 457         struct pcnet32_private *lp = netdev_priv(dev);
 458 #endif
 459         netif_wake_queue(dev);
 460 #ifdef CONFIG_PCNET32_NAPI
 461         napi_enable(&lp->napi);
 462 #endif
 463 }
 464
 465 /*
 466  * Allocate space for the new sized tx ring.
 467  * Free old resources
 468  * Save new resources.
 469  * Any failure keeps old resources.
 470  * Must be called with lp->lock held.
 471  */
 472 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 473                                     struct pcnet32_private *lp,
 474                                     unsigned int size)
 475 {
 476         dma_addr_t new_ring_dma_addr;
 477         dma_addr_t *new_dma_addr_list;
 478         struct pcnet32_tx_head *new_tx_ring;
 479         struct sk_buff **new_skb_list;
 480
 481         pcnet32_purge_tx_ring(dev);
 482
 483         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 484                                            sizeof(struct pcnet32_tx_head) *
 485                                            (1 << size),
 486                                            &new_ring_dma_addr);
 487         if (new_tx_ring == NULL) {
 488                 if (netif_msg_drv(lp))
 489                         printk("\n" KERN_ERR
 490                                "%s: Consistent memory allocation failed.\n",
 491                                dev->name);
 492                 return;
 493         }
 494         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 495
 496         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 497                                 GFP_ATOMIC);
 498         if (!new_dma_addr_list) {
 499                 if (netif_msg_drv(lp))
 500                         printk("\n" KERN_ERR
 501                                "%s: Memory allocation failed.\n", dev->name);
 502                 goto free_new_tx_ring;
 503         }
 504
 505         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 506                                 GFP_ATOMIC);
 507         if (!new_skb_list) {
 508                 if (netif_msg_drv(lp))
 509                         printk("\n" KERN_ERR
 510                                "%s: Memory allocation failed.\n", dev->name);
 511                 goto free_new_lists;
 512         }
 513
 514         kfree(lp->tx_skbuff);
 515         kfree(lp->tx_dma_addr);
 516         pci_free_consistent(lp->pci_dev,
 517                             sizeof(struct pcnet32_tx_head) *
 518                             lp->tx_ring_size, lp->tx_ring,
 519                             lp->tx_ring_dma_addr);
 520
 521         lp->tx_ring_size = (1 << size);
 522         lp->tx_mod_mask = lp->tx_ring_size - 1;
 523         lp->tx_len_bits = (size << 12);
 524         lp->tx_ring = new_tx_ring;
 525         lp->tx_ring_dma_addr = new_ring_dma_addr;
 526         lp->tx_dma_addr = new_dma_addr_list;
 527         lp->tx_skbuff = new_skb_list;
 528         return;
 529
 530     free_new_lists:
 531         kfree(new_dma_addr_list);
 532     free_new_tx_ring:
 533         pci_free_consistent(lp->pci_dev,
 534                             sizeof(struct pcnet32_tx_head) *
 535                             (1 << size),
 536                             new_tx_ring,
 537                             new_ring_dma_addr);
 538         return;
 539 }
 540
 541 /*
 542  * Allocate space for the new sized rx ring.
 543  * Re-use old receive buffers.
 544  *   alloc extra buffers
 545  *   free unneeded buffers
 546  *   free unneeded buffers
 547  * Save new resources.
 548  * Any failure keeps old resources.
 549  * Must be called with lp->lock held.
 550  */
 551 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 552                                     struct pcnet32_private *lp,
 553                                     unsigned int size)
 554 {
 555         dma_addr_t new_ring_dma_addr;
 556         dma_addr_t *new_dma_addr_list;
 557         struct pcnet32_rx_head *new_rx_ring;
 558         struct sk_buff **new_skb_list;
 559         int new, overlap;
 560
 561         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 562                                            sizeof(struct pcnet32_rx_head) *
 563                                            (1 << size),
 564                                            &new_ring_dma_addr);
 565         if (new_rx_ring == NULL) {
 566                 if (netif_msg_drv(lp))
 567                         printk("\n" KERN_ERR
 568                                "%s: Consistent memory allocation failed.\n",
 569                                dev->name);
 570                 return;
 571         }
 572         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 573
 574         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 575                                 GFP_ATOMIC);
 576         if (!new_dma_addr_list) {
 577                 if (netif_msg_drv(lp))
 578                         printk("\n" KERN_ERR
 579                                "%s: Memory allocation failed.\n", dev->name);
 580                 goto free_new_rx_ring;
 581         }
 582
 583         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 584                                 GFP_ATOMIC);
 585         if (!new_skb_list) {
 586                 if (netif_msg_drv(lp))
 587                         printk("\n" KERN_ERR
 588                                "%s: Memory allocation failed.\n", dev->name);
 589                 goto free_new_lists;
 590         }
 591
 592         /* first copy the current receive buffers */
 593         overlap = min(size, lp->rx_ring_size);
 594         for (new = 0; new < overlap; new++) {
 595                 new_rx_ring[new] = lp->rx_ring[new];
 596                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 597                 new_skb_list[new] = lp->rx_skbuff[new];
 598         }
 599         /* now allocate any new buffers needed */
 600         for (; new < size; new++ ) {
 601                 struct sk_buff *rx_skbuff;
 602                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
 603                 if (!(rx_skbuff = new_skb_list[new])) {
 604                         /* keep the original lists and buffers */
 605                         if (netif_msg_drv(lp))
 606                                 printk(KERN_ERR
 607                                        "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
 608                                        dev->name);
 609                         goto free_all_new;
 610                 }
 611                 skb_reserve(rx_skbuff, 2);
 612
 613                 new_dma_addr_list[new] =
 614                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 615                                            PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 616                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 617                 new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
 618                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 619         }
 620         /* and free any unneeded buffers */
 621         for (; new < lp->rx_ring_size; new++) {
 622                 if (lp->rx_skbuff[new]) {
 623                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 624                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 625                         dev_kfree_skb(lp->rx_skbuff[new]);
 626                 }
 627         }
 628
 629         kfree(lp->rx_skbuff);
 630         kfree(lp->rx_dma_addr);
 631         pci_free_consistent(lp->pci_dev,
 632                             sizeof(struct pcnet32_rx_head) *
 633                             lp->rx_ring_size, lp->rx_ring,
 634                             lp->rx_ring_dma_addr);
 635
 636         lp->rx_ring_size = (1 << size);
 637         lp->rx_mod_mask = lp->rx_ring_size - 1;
 638         lp->rx_len_bits = (size << 4);
 639         lp->rx_ring = new_rx_ring;
 640         lp->rx_ring_dma_addr = new_ring_dma_addr;
 641         lp->rx_dma_addr = new_dma_addr_list;
 642         lp->rx_skbuff = new_skb_list;
 643         return;
 644
 645     free_all_new:
 646         for (; --new >= lp->rx_ring_size; ) {
 647                 if (new_skb_list[new]) {
 648                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 649                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 650                         dev_kfree_skb(new_skb_list[new]);
 651                 }
 652         }
 653         kfree(new_skb_list);
 654     free_new_lists:
 655         kfree(new_dma_addr_list);
 656     free_new_rx_ring:
 657         pci_free_consistent(lp->pci_dev,
 658                             sizeof(struct pcnet32_rx_head) *
 659                             (1 << size),
 660                             new_rx_ring,
 661                             new_ring_dma_addr);
 662         return;
 663 }
 664
 665 static void pcnet32_purge_rx_ring(struct net_device *dev)
 666 {
 667         struct pcnet32_private *lp = netdev_priv(dev);
 668         int i;
 669
 670         /* free all allocated skbuffs */
 671         for (i = 0; i < lp->rx_ring_size; i++) {
 672                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 673                 wmb();          /* Make sure adapter sees owner change */
 674                 if (lp->rx_skbuff[i]) {
 675                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 676                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 677                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 678                 }
 679                 lp->rx_skbuff[i] = NULL;
 680                 lp->rx_dma_addr[i] = 0;
 681         }
 682 }
 683
 684 #ifdef CONFIG_NET_POLL_CONTROLLER
 685 static void pcnet32_poll_controller(struct net_device *dev)
 686 {
 687         disable_irq(dev->irq);
 688         pcnet32_interrupt(0, dev);
 689         enable_irq(dev->irq);
 690 }
 691 #endif
 692
 693 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 694 {
 695         struct pcnet32_private *lp = netdev_priv(dev);
 696         unsigned long flags;
 697         int r = -EOPNOTSUPP;
 698
 699         if (lp->mii) {
 700                 spin_lock_irqsave(&lp->lock, flags);
 701                 mii_ethtool_gset(&lp->mii_if, cmd);
 702                 spin_unlock_irqrestore(&lp->lock, flags);
 703                 r = 0;
 704         }
 705         return r;
 706 }
 707
 708 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 709 {
 710         struct pcnet32_private *lp = netdev_priv(dev);
 711         unsigned long flags;
 712         int r = -EOPNOTSUPP;
 713
 714         if (lp->mii) {
 715                 spin_lock_irqsave(&lp->lock, flags);
 716                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 717                 spin_unlock_irqrestore(&lp->lock, flags);
 718         }
 719         return r;
 720 }
 721
 722 static void pcnet32_get_drvinfo(struct net_device *dev,
 723                                 struct ethtool_drvinfo *info)
 724 {
 725         struct pcnet32_private *lp = netdev_priv(dev);
 726
 727         strcpy(info->driver, DRV_NAME);
 728         strcpy(info->version, DRV_VERSION);
 729         if (lp->pci_dev)
 730                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 731         else
 732                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 733 }
 734
 735 static u32 pcnet32_get_link(struct net_device *dev)
 736 {
 737         struct pcnet32_private *lp = netdev_priv(dev);
 738         unsigned long flags;
 739         int r;
 740
 741         spin_lock_irqsave(&lp->lock, flags);
 742         if (lp->mii) {
 743                 r = mii_link_ok(&lp->mii_if);
 744         } else if (lp->chip_version >= PCNET32_79C970A) {
 745                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 746                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 747         } else {        /* can not detect link on really old chips */
 748                 r = 1;
 749         }
 750         spin_unlock_irqrestore(&lp->lock, flags);
 751
 752         return r;
 753 }
 754
 755 static u32 pcnet32_get_msglevel(struct net_device *dev)
 756 {
 757         struct pcnet32_private *lp = netdev_priv(dev);
 758         return lp->msg_enable;
 759 }
 760
 761 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 762 {
 763         struct pcnet32_private *lp = netdev_priv(dev);
 764         lp->msg_enable = value;
 765 }
 766
 767 static int pcnet32_nway_reset(struct net_device *dev)
 768 {
 769         struct pcnet32_private *lp = netdev_priv(dev);
 770         unsigned long flags;
 771         int r = -EOPNOTSUPP;
 772
 773         if (lp->mii) {
 774                 spin_lock_irqsave(&lp->lock, flags);
 775                 r = mii_nway_restart(&lp->mii_if);
 776                 spin_unlock_irqrestore(&lp->lock, flags);
 777         }
 778         return r;
 779 }
 780
 781 static void pcnet32_get_ringparam(struct net_device *dev,
 782                                   struct ethtool_ringparam *ering)
 783 {
 784         struct pcnet32_private *lp = netdev_priv(dev);
 785
 786         ering->tx_max_pending = TX_MAX_RING_SIZE;
 787         ering->tx_pending = lp->tx_ring_size;
 788         ering->rx_max_pending = RX_MAX_RING_SIZE;
 789         ering->rx_pending = lp->rx_ring_size;
 790 }
 791
 792 static int pcnet32_set_ringparam(struct net_device *dev,
 793                                  struct ethtool_ringparam *ering)
 794 {
 795         struct pcnet32_private *lp = netdev_priv(dev);
 796         unsigned long flags;
 797         unsigned int size;
 798         ulong ioaddr = dev->base_addr;
 799         int i;
 800
 801         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 802                 return -EINVAL;
 803
 804         if (netif_running(dev))
 805                 pcnet32_netif_stop(dev);
 806
 807         spin_lock_irqsave(&lp->lock, flags);
 808         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 809
 810         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 811
 812         /* set the minimum ring size to 4, to allow the loopback test to work
 813          * unchanged.
 814          */
 815         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 816                 if (size <= (1 << i))
 817                         break;
 818         }
 819         if ((1 << i) != lp->tx_ring_size)
 820                 pcnet32_realloc_tx_ring(dev, lp, i);
 821
 822         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 823         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 824                 if (size <= (1 << i))
 825                         break;
 826         }
 827         if ((1 << i) != lp->rx_ring_size)
 828                 pcnet32_realloc_rx_ring(dev, lp, i);
 829
 830         lp->napi.weight = lp->rx_ring_size / 2;
 831
 832         if (netif_running(dev)) {
 833                 pcnet32_netif_start(dev);
 834                 pcnet32_restart(dev, CSR0_NORMAL);
 835         }
 836
 837         spin_unlock_irqrestore(&lp->lock, flags);
 838
 839         if (netif_msg_drv(lp))
 840                 printk(KERN_INFO
 841                        "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
 842                        lp->rx_ring_size, lp->tx_ring_size);
 843
 844         return 0;
 845 }
 846
 847 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 848                                 u8 * data)
 849 {
 850         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 851 }
 852
 853 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 854 {
 855         switch (sset) {
 856         case ETH_SS_TEST:
 857                 return PCNET32_TEST_LEN;
 858         default:
 859                 return -EOPNOTSUPP;
 860         }
 861 }
 862
 863 static void pcnet32_ethtool_test(struct net_device *dev,
 864                                  struct ethtool_test *test, u64 * data)
 865 {
 866         struct pcnet32_private *lp = netdev_priv(dev);
 867         int rc;
 868
 869         if (test->flags == ETH_TEST_FL_OFFLINE) {
 870                 rc = pcnet32_loopback_test(dev, data);
 871                 if (rc) {
 872                         if (netif_msg_hw(lp))
 873                                 printk(KERN_DEBUG "%s: Loopback test failed.\n",
 874                                        dev->name);
 875                         test->flags |= ETH_TEST_FL_FAILED;
 876                 } else if (netif_msg_hw(lp))
 877                         printk(KERN_DEBUG "%s: Loopback test passed.\n",
 878                                dev->name);
 879         } else if (netif_msg_hw(lp))
 880                 printk(KERN_DEBUG
 881                        "%s: No tests to run (specify 'Offline' on ethtool).",
 882                        dev->name);
 883 }                               /* end pcnet32_ethtool_test */
 884
 885 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 886 {
 887         struct pcnet32_private *lp = netdev_priv(dev);
 888         struct pcnet32_access *a = &lp->a;      /* access to registers */
 889         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 890         struct sk_buff *skb;    /* sk buff */
 891         int x, i;               /* counters */
 892         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 893         u16 status = 0x8300;    /* TX ring status */
 894         __le16 teststatus;      /* test of ring status */
 895         int rc;                 /* return code */
 896         int size;               /* size of packets */
 897         unsigned char *packet;  /* source packet data */
 898         static const int data_len = 60; /* length of source packets */
 899         unsigned long flags;
 900         unsigned long ticks;
 901
 902         rc = 1;                 /* default to fail */
 903
 904         if (netif_running(dev))
 905 #ifdef CONFIG_PCNET32_NAPI
 906                 pcnet32_netif_stop(dev);
 907 #else
 908                 pcnet32_close(dev);
 909 #endif
 910
 911         spin_lock_irqsave(&lp->lock, flags);
 912         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 913
 914         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 915
 916         /* Reset the PCNET32 */
 917         lp->a.reset(ioaddr);
 918         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
 919
 920         /* switch pcnet32 to 32bit mode */
 921         lp->a.write_bcr(ioaddr, 20, 2);
 922
 923         /* purge & init rings but don't actually restart */
 924         pcnet32_restart(dev, 0x0000);
 925
 926         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 927
 928         /* Initialize Transmit buffers. */
 929         size = data_len + 15;
 930         for (x = 0; x < numbuffs; x++) {
 931                 if (!(skb = dev_alloc_skb(size))) {
 932                         if (netif_msg_hw(lp))
 933                                 printk(KERN_DEBUG
 934                                        "%s: Cannot allocate skb at line: %d!\n",
 935                                        dev->name, __LINE__);
 936                         goto clean_up;
 937                 } else {
 938                         packet = skb->data;
 939                         skb_put(skb, size);     /* create space for data */
 940                         lp->tx_skbuff[x] = skb;
 941                         lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 942                         lp->tx_ring[x].misc = 0;
 943
 944                         /* put DA and SA into the skb */
 945                         for (i = 0; i < 6; i++)
 946                                 *packet++ = dev->dev_addr[i];
 947                         for (i = 0; i < 6; i++)
 948                                 *packet++ = dev->dev_addr[i];
 949                         /* type */
 950                         *packet++ = 0x08;
 951                         *packet++ = 0x06;
 952                         /* packet number */
 953                         *packet++ = x;
 954                         /* fill packet with data */
 955                         for (i = 0; i < data_len; i++)
 956                                 *packet++ = i;
 957
 958                         lp->tx_dma_addr[x] =
 959                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 960                                            PCI_DMA_TODEVICE);
 961                         lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 962                         wmb();  /* Make sure owner changes after all others are visible */
 963                         lp->tx_ring[x].status = cpu_to_le16(status);
 964                 }
 965         }
 966
 967         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 968         a->write_bcr(ioaddr, 32, x | 0x0002);
 969
 970         /* set int loopback in CSR15 */
 971         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 972         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 973
 974         teststatus = cpu_to_le16(0x8000);
 975         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 976
 977         /* Check status of descriptors */
 978         for (x = 0; x < numbuffs; x++) {
 979                 ticks = 0;
 980                 rmb();
 981                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 982                         spin_unlock_irqrestore(&lp->lock, flags);
 983                         msleep(1);
 984                         spin_lock_irqsave(&lp->lock, flags);
 985                         rmb();
 986                         ticks++;
 987                 }
 988                 if (ticks == 200) {
 989                         if (netif_msg_hw(lp))
 990                                 printk("%s: Desc %d failed to reset!\n",
 991                                        dev->name, x);
 992                         break;
 993                 }
 994         }
 995
 996         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 997         wmb();
 998         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 999                 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
1000
1001                 for (x = 0; x < numbuffs; x++) {
1002                         printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1003                         skb = lp->rx_skbuff[x];
1004                         for (i = 0; i < size; i++) {
1005                                 printk("%02x ", *(skb->data + i));
1006                         }
1007                         printk("\n");
1008                 }
1009         }
1010
1011         x = 0;
1012         rc = 0;
1013         while (x < numbuffs && !rc) {
1014                 skb = lp->rx_skbuff[x];
1015                 packet = lp->tx_skbuff[x]->data;
1016                 for (i = 0; i < size; i++) {
1017                         if (*(skb->data + i) != packet[i]) {
1018                                 if (netif_msg_hw(lp))
1019                                         printk(KERN_DEBUG
1020                                                "%s: Error in compare! %2x - %02x %02x\n",
1021                                                dev->name, i, *(skb->data + i),
1022                                                packet[i]);
1023                                 rc = 1;
1024                                 break;
1025                         }
1026                 }
1027                 x++;
1028         }
1029
1030       clean_up:
1031         *data1 = rc;
1032         pcnet32_purge_tx_ring(dev);
1033
1034         x = a->read_csr(ioaddr, CSR15);
1035         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1036
1037         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1038         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1039
1040 #ifdef CONFIG_PCNET32_NAPI
1041         if (netif_running(dev)) {
1042                 pcnet32_netif_start(dev);
1043                 pcnet32_restart(dev, CSR0_NORMAL);
1044         } else {
1045                 pcnet32_purge_rx_ring(dev);
1046                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1047         }
1048         spin_unlock_irqrestore(&lp->lock, flags);
1049 #else
1050         if (netif_running(dev)) {
1051                 spin_unlock_irqrestore(&lp->lock, flags);
1052                 pcnet32_open(dev);
1053         } else {
1054                 pcnet32_purge_rx_ring(dev);
1055                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1056                 spin_unlock_irqrestore(&lp->lock, flags);
1057         }
1058 #endif
1059
1060         return (rc);
1061 }                               /* end pcnet32_loopback_test  */
1062
1063 static void pcnet32_led_blink_callback(struct net_device *dev)
1064 {
1065         struct pcnet32_private *lp = netdev_priv(dev);
1066         struct pcnet32_access *a = &lp->a;
1067         ulong ioaddr = dev->base_addr;
1068         unsigned long flags;
1069         int i;
1070
1071         spin_lock_irqsave(&lp->lock, flags);
1072         for (i = 4; i < 8; i++) {
1073                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1074         }
1075         spin_unlock_irqrestore(&lp->lock, flags);
1076
1077         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1078 }
1079
1080 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1081 {
1082         struct pcnet32_private *lp = netdev_priv(dev);
1083         struct pcnet32_access *a = &lp->a;
1084         ulong ioaddr = dev->base_addr;
1085         unsigned long flags;
1086         int i, regs[4];
1087
1088         if (!lp->blink_timer.function) {
1089                 init_timer(&lp->blink_timer);
1090                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1091                 lp->blink_timer.data = (unsigned long)dev;
1092         }
1093
1094         /* Save the current value of the bcrs */
1095         spin_lock_irqsave(&lp->lock, flags);
1096         for (i = 4; i < 8; i++) {
1097                 regs[i - 4] = a->read_bcr(ioaddr, i);
1098         }
1099         spin_unlock_irqrestore(&lp->lock, flags);
1100
1101         mod_timer(&lp->blink_timer, jiffies);
1102         set_current_state(TASK_INTERRUPTIBLE);
1103
1104         /* AV: the limit here makes no sense whatsoever */
1105         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1106                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1107
1108         msleep_interruptible(data * 1000);
1109         del_timer_sync(&lp->blink_timer);
1110
1111         /* Restore the original value of the bcrs */
1112         spin_lock_irqsave(&lp->lock, flags);
1113         for (i = 4; i < 8; i++) {
1114                 a->write_bcr(ioaddr, i, regs[i - 4]);
1115         }
1116         spin_unlock_irqrestore(&lp->lock, flags);
1117
1118         return 0;
1119 }
1120
1121 /*
1122  * lp->lock must be held.
1123  */
1124 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1125                 int can_sleep)
1126 {
1127         int csr5;
1128         struct pcnet32_private *lp = netdev_priv(dev);
1129         struct pcnet32_access *a = &lp->a;
1130         ulong ioaddr = dev->base_addr;
1131         int ticks;
1132
1133         /* really old chips have to be stopped. */
1134         if (lp->chip_version < PCNET32_79C970A)
1135                 return 0;
1136
1137         /* set SUSPEND (SPND) - CSR5 bit 0 */
1138         csr5 = a->read_csr(ioaddr, CSR5);
1139         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1140
1141         /* poll waiting for bit to be set */
1142         ticks = 0;
1143         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1144                 spin_unlock_irqrestore(&lp->lock, *flags);
1145                 if (can_sleep)
1146                         msleep(1);
1147                 else
1148                         mdelay(1);
1149                 spin_lock_irqsave(&lp->lock, *flags);
1150                 ticks++;
1151                 if (ticks > 200) {
1152                         if (netif_msg_hw(lp))
1153                                 printk(KERN_DEBUG
1154                                        "%s: Error getting into suspend!\n",
1155                                        dev->name);
1156                         return 0;
1157                 }
1158         }
1159         return 1;
1160 }
1161
1162 /*
1163  * process one receive descriptor entry
1164  */
1165
1166 static void pcnet32_rx_entry(struct net_device *dev,
1167                              struct pcnet32_private *lp,
1168                              struct pcnet32_rx_head *rxp,
1169                              int entry)
1170 {
1171         int status = (short)le16_to_cpu(rxp->status) >> 8;
1172         int rx_in_place = 0;
1173         struct sk_buff *skb;
1174         short pkt_len;
1175
1176         if (status != 0x03) {   /* There was an error. */
1177                 /*
1178                  * There is a tricky error noted by John Murphy,
1179                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1180                  * buffers it's possible for a jabber packet to use two
1181                  * buffers, with only the last correctly noting the error.
1182                  */
1183                 if (status & 0x01)      /* Only count a general error at the */
1184                         dev->stats.rx_errors++; /* end of a packet. */
1185                 if (status & 0x20)
1186                         dev->stats.rx_frame_errors++;
1187                 if (status & 0x10)
1188                         dev->stats.rx_over_errors++;
1189                 if (status & 0x08)
1190                         dev->stats.rx_crc_errors++;
1191                 if (status & 0x04)
1192                         dev->stats.rx_fifo_errors++;
1193                 return;
1194         }
1195
1196         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1197
1198         /* Discard oversize frames. */
1199         if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1200                 if (netif_msg_drv(lp))
1201                         printk(KERN_ERR "%s: Impossible packet size %d!\n",
1202                                dev->name, pkt_len);
1203                 dev->stats.rx_errors++;
1204                 return;
1205         }
1206         if (pkt_len < 60) {
1207                 if (netif_msg_rx_err(lp))
1208                         printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1209                 dev->stats.rx_errors++;
1210                 return;
1211         }
1212
1213         if (pkt_len > rx_copybreak) {
1214                 struct sk_buff *newskb;
1215
1216                 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1217                         skb_reserve(newskb, 2);
1218                         skb = lp->rx_skbuff[entry];
1219                         pci_unmap_single(lp->pci_dev,
1220                                          lp->rx_dma_addr[entry],
1221                                          PKT_BUF_SZ - 2,
1222                                          PCI_DMA_FROMDEVICE);
1223                         skb_put(skb, pkt_len);
1224                         lp->rx_skbuff[entry] = newskb;
1225                         lp->rx_dma_addr[entry] =
1226                                             pci_map_single(lp->pci_dev,
1227                                                            newskb->data,
1228                                                            PKT_BUF_SZ - 2,
1229                                                            PCI_DMA_FROMDEVICE);
1230                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1231                         rx_in_place = 1;
1232                 } else
1233                         skb = NULL;
1234         } else {
1235                 skb = dev_alloc_skb(pkt_len + 2);
1236         }
1237
1238         if (skb == NULL) {
1239                 if (netif_msg_drv(lp))
1240                         printk(KERN_ERR
1241                                "%s: Memory squeeze, dropping packet.\n",
1242                                dev->name);
1243                 dev->stats.rx_dropped++;
1244                 return;
1245         }
1246         skb->dev = dev;
1247         if (!rx_in_place) {
1248                 skb_reserve(skb, 2);    /* 16 byte align */
1249                 skb_put(skb, pkt_len);  /* Make room */
1250                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1251                                             lp->rx_dma_addr[entry],
1252                                             pkt_len,
1253                                             PCI_DMA_FROMDEVICE);
1254                 skb_copy_to_linear_data(skb,
1255                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1256                                  pkt_len);
1257                 pci_dma_sync_single_for_device(lp->pci_dev,
1258                                                lp->rx_dma_addr[entry],
1259                                                pkt_len,
1260                                                PCI_DMA_FROMDEVICE);
1261         }
1262         dev->stats.rx_bytes += skb->len;
1263         skb->protocol = eth_type_trans(skb, dev);
1264 #ifdef CONFIG_PCNET32_NAPI
1265         netif_receive_skb(skb);
1266 #else
1267         netif_rx(skb);
1268 #endif
1269         dev->last_rx = jiffies;
1270         dev->stats.rx_packets++;
1271         return;
1272 }
1273
1274 static int pcnet32_rx(struct net_device *dev, int budget)
1275 {
1276         struct pcnet32_private *lp = netdev_priv(dev);
1277         int entry = lp->cur_rx & lp->rx_mod_mask;
1278         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1279         int npackets = 0;
1280
1281         /* If we own the next entry, it's a new packet. Send it up. */
1282         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1283                 pcnet32_rx_entry(dev, lp, rxp, entry);
1284                 npackets += 1;
1285                 /*
1286                  * The docs say that the buffer length isn't touched, but Andrew
1287                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1288                  */
1289                 rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
1290                 wmb();  /* Make sure owner changes after others are visible */
1291                 rxp->status = cpu_to_le16(0x8000);
1292                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1293                 rxp = &lp->rx_ring[entry];
1294         }
1295
1296         return npackets;
1297 }
1298
1299 static int pcnet32_tx(struct net_device *dev)
1300 {
1301         struct pcnet32_private *lp = netdev_priv(dev);
1302         unsigned int dirty_tx = lp->dirty_tx;
1303         int delta;
1304         int must_restart = 0;
1305
1306         while (dirty_tx != lp->cur_tx) {
1307                 int entry = dirty_tx & lp->tx_mod_mask;
1308                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1309
1310                 if (status < 0)
1311                         break;  /* It still hasn't been Txed */
1312
1313                 lp->tx_ring[entry].base = 0;
1314
1315                 if (status & 0x4000) {
1316                         /* There was a major error, log it. */
1317                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1318                         dev->stats.tx_errors++;
1319                         if (netif_msg_tx_err(lp))
1320                                 printk(KERN_ERR
1321                                        "%s: Tx error status=%04x err_status=%08x\n",
1322                                        dev->name, status,
1323                                        err_status);
1324                         if (err_status & 0x04000000)
1325                                 dev->stats.tx_aborted_errors++;
1326                         if (err_status & 0x08000000)
1327                                 dev->stats.tx_carrier_errors++;
1328                         if (err_status & 0x10000000)
1329                                 dev->stats.tx_window_errors++;
1330 #ifndef DO_DXSUFLO
1331                         if (err_status & 0x40000000) {
1332                                 dev->stats.tx_fifo_errors++;
1333                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1334                                 /* Remove this verbosity later! */
1335                                 if (netif_msg_tx_err(lp))
1336                                         printk(KERN_ERR
1337                                                "%s: Tx FIFO error!\n",
1338                                                dev->name);
1339                                 must_restart = 1;
1340                         }
1341 #else
1342                         if (err_status & 0x40000000) {
1343                                 dev->stats.tx_fifo_errors++;
1344                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1345                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1346                                         /* Remove this verbosity later! */
1347                                         if (netif_msg_tx_err(lp))
1348                                                 printk(KERN_ERR
1349                                                        "%s: Tx FIFO error!\n",
1350                                                        dev->name);
1351                                         must_restart = 1;
1352                                 }
1353                         }
1354 #endif
1355                 } else {
1356                         if (status & 0x1800)
1357                                 dev->stats.collisions++;
1358                         dev->stats.tx_packets++;
1359                 }
1360
1361                 /* We must free the original skb */
1362                 if (lp->tx_skbuff[entry]) {
1363                         pci_unmap_single(lp->pci_dev,
1364                                          lp->tx_dma_addr[entry],
1365                                          lp->tx_skbuff[entry]->
1366                                          len, PCI_DMA_TODEVICE);
1367                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1368                         lp->tx_skbuff[entry] = NULL;
1369                         lp->tx_dma_addr[entry] = 0;
1370                 }
1371                 dirty_tx++;
1372         }
1373
1374         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1375         if (delta > lp->tx_ring_size) {
1376                 if (netif_msg_drv(lp))
1377                         printk(KERN_ERR
1378                                "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1379                                dev->name, dirty_tx, lp->cur_tx,
1380                                lp->tx_full);
1381                 dirty_tx += lp->tx_ring_size;
1382                 delta -= lp->tx_ring_size;
1383         }
1384
1385         if (lp->tx_full &&
1386             netif_queue_stopped(dev) &&
1387             delta < lp->tx_ring_size - 2) {
1388                 /* The ring is no longer full, clear tbusy. */
1389                 lp->tx_full = 0;
1390                 netif_wake_queue(dev);
1391         }
1392         lp->dirty_tx = dirty_tx;
1393
1394         return must_restart;
1395 }
1396
1397 #ifdef CONFIG_PCNET32_NAPI
1398 static int pcnet32_poll(struct napi_struct *napi, int budget)
1399 {
1400         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1401         struct net_device *dev = lp->dev;
1402         unsigned long ioaddr = dev->base_addr;
1403         unsigned long flags;
1404         int work_done;
1405         u16 val;
1406
1407         work_done = pcnet32_rx(dev, budget);
1408
1409         spin_lock_irqsave(&lp->lock, flags);
1410         if (pcnet32_tx(dev)) {
1411                 /* reset the chip to clear the error condition, then restart */
1412                 lp->a.reset(ioaddr);
1413                 lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
1414                 pcnet32_restart(dev, CSR0_START);
1415                 netif_wake_queue(dev);
1416         }
1417         spin_unlock_irqrestore(&lp->lock, flags);
1418
1419         if (work_done < budget) {
1420                 spin_lock_irqsave(&lp->lock, flags);
1421
1422                 __netif_rx_complete(dev, napi);
1423
1424                 /* clear interrupt masks */
1425                 val = lp->a.read_csr(ioaddr, CSR3);
1426                 val &= 0x00ff;
1427                 lp->a.write_csr(ioaddr, CSR3, val);
1428
1429                 /* Set interrupt enable. */
1430                 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1431                 mmiowb();
1432                 spin_unlock_irqrestore(&lp->lock, flags);
1433         }
1434         return work_done;
1435 }
1436 #endif
1437
1438 #define PCNET32_REGS_PER_PHY    32
1439 #define PCNET32_MAX_PHYS        32
1440 static int pcnet32_get_regs_len(struct net_device *dev)
1441 {
1442         struct pcnet32_private *lp = netdev_priv(dev);
1443         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1444
1445         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1446 }
1447
1448 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1449                              void *ptr)
1450 {
1451         int i, csr0;
1452         u16 *buff = ptr;
1453         struct pcnet32_private *lp = netdev_priv(dev);
1454         struct pcnet32_access *a = &lp->a;
1455         ulong ioaddr = dev->base_addr;
1456         unsigned long flags;
1457
1458         spin_lock_irqsave(&lp->lock, flags);
1459
1460         csr0 = a->read_csr(ioaddr, CSR0);
1461         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1462                 pcnet32_suspend(dev, &flags, 1);
1463
1464         /* read address PROM */
1465         for (i = 0; i < 16; i += 2)
1466                 *buff++ = inw(ioaddr + i);
1467
1468         /* read control and status registers */
1469         for (i = 0; i < 90; i++) {
1470                 *buff++ = a->read_csr(ioaddr, i);
1471         }
1472
1473         *buff++ = a->read_csr(ioaddr, 112);
1474         *buff++ = a->read_csr(ioaddr, 114);
1475
1476         /* read bus configuration registers */
1477         for (i = 0; i < 30; i++) {
1478                 *buff++ = a->read_bcr(ioaddr, i);
1479         }
1480         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1481         for (i = 31; i < 36; i++) {
1482                 *buff++ = a->read_bcr(ioaddr, i);
1483         }
1484
1485         /* read mii phy registers */
1486         if (lp->mii) {
1487                 int j;
1488                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1489                         if (lp->phymask & (1 << j)) {
1490                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1491                                         lp->a.write_bcr(ioaddr, 33,
1492                                                         (j << 5) | i);
1493                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1494                                 }
1495                         }
1496                 }
1497         }
1498
1499         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1500                 int csr5;
1501
1502                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1503                 csr5 = a->read_csr(ioaddr, CSR5);
1504                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1505         }
1506
1507         spin_unlock_irqrestore(&lp->lock, flags);
1508 }
1509
1510 static const struct ethtool_ops pcnet32_ethtool_ops = {
1511         .get_settings           = pcnet32_get_settings,
1512         .set_settings           = pcnet32_set_settings,
1513         .get_drvinfo            = pcnet32_get_drvinfo,
1514         .get_msglevel           = pcnet32_get_msglevel,
1515         .set_msglevel           = pcnet32_set_msglevel,
1516         .nway_reset             = pcnet32_nway_reset,
1517         .get_link               = pcnet32_get_link,
1518         .get_ringparam          = pcnet32_get_ringparam,
1519         .set_ringparam          = pcnet32_set_ringparam,
1520         .get_strings            = pcnet32_get_strings,
1521         .self_test              = pcnet32_ethtool_test,
1522         .phys_id                = pcnet32_phys_id,
1523         .get_regs_len           = pcnet32_get_regs_len,
1524         .get_regs               = pcnet32_get_regs,
1525         .get_sset_count         = pcnet32_get_sset_count,
1526 };
1527
1528 /* only probes for non-PCI devices, the rest are handled by
1529  * pci_register_driver via pcnet32_probe_pci */
1530
1531 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1532 {
1533         unsigned int *port, ioaddr;
1534
1535         /* search for PCnet32 VLB cards at known addresses */
1536         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1537                 if (request_region
1538                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1539                         /* check if there is really a pcnet chip on that ioaddr */
1540                         if ((inb(ioaddr + 14) == 0x57)
1541                             && (inb(ioaddr + 15) == 0x57)) {
1542                                 pcnet32_probe1(ioaddr, 0, NULL);
1543                         } else {
1544                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1545                         }
1546                 }
1547         }
1548 }
1549
1550 static int __devinit
1551 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1552 {
1553         unsigned long ioaddr;
1554         int err;
1555
1556         err = pci_enable_device(pdev);
1557         if (err < 0) {
1558                 if (pcnet32_debug & NETIF_MSG_PROBE)
1559                         printk(KERN_ERR PFX
1560                                "failed to enable device -- err=%d\n", err);
1561                 return err;
1562         }
1563         pci_set_master(pdev);
1564
1565         ioaddr = pci_resource_start(pdev, 0);
1566         if (!ioaddr) {
1567                 if (pcnet32_debug & NETIF_MSG_PROBE)
1568                         printk(KERN_ERR PFX
1569                                "card has no PCI IO resources, aborting\n");
1570                 return -ENODEV;
1571         }
1572
1573         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1574                 if (pcnet32_debug & NETIF_MSG_PROBE)
1575                         printk(KERN_ERR PFX
1576                                "architecture does not support 32bit PCI busmaster DMA\n");
1577                 return -ENODEV;
1578         }
1579         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1580             NULL) {
1581                 if (pcnet32_debug & NETIF_MSG_PROBE)
1582                         printk(KERN_ERR PFX
1583                                "io address range already allocated\n");
1584                 return -EBUSY;
1585         }
1586
1587         err = pcnet32_probe1(ioaddr, 1, pdev);
1588         if (err < 0) {
1589                 pci_disable_device(pdev);
1590         }
1591         return err;
1592 }
1593
1594 /* pcnet32_probe1
1595  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1596  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1597  */
1598 static int __devinit
1599 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1600 {
1601         struct pcnet32_private *lp;
1602         int i, media;
1603         int fdx, mii, fset, dxsuflo;
1604         int chip_version;
1605         char *chipname;
1606         struct net_device *dev;
1607         struct pcnet32_access *a = NULL;
1608         u8 promaddr[6];
1609         int ret = -ENODEV;
1610
1611         /* reset the chip */
1612         pcnet32_wio_reset(ioaddr);
1613
1614         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1615         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1616                 a = &pcnet32_wio;
1617         } else {
1618                 pcnet32_dwio_reset(ioaddr);
1619                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1620                     && pcnet32_dwio_check(ioaddr)) {
1621                         a = &pcnet32_dwio;
1622                 } else
1623                         goto err_release_region;
1624         }
1625
1626         chip_version =
1627             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1628         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1629                 printk(KERN_INFO "  PCnet chip version is %#x.\n",
1630                        chip_version);
1631         if ((chip_version & 0xfff) != 0x003) {
1632                 if (pcnet32_debug & NETIF_MSG_PROBE)
1633                         printk(KERN_INFO PFX "Unsupported chip version.\n");
1634                 goto err_release_region;
1635         }
1636
1637         /* initialize variables */
1638         fdx = mii = fset = dxsuflo = 0;
1639         chip_version = (chip_version >> 12) & 0xffff;
1640
1641         switch (chip_version) {
1642         case 0x2420:
1643                 chipname = "PCnet/PCI 79C970";  /* PCI */
1644                 break;
1645         case 0x2430:
1646                 if (shared)
1647                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1648                 else
1649                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1650                 break;
1651         case 0x2621:
1652                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1653                 fdx = 1;
1654                 break;
1655         case 0x2623:
1656                 chipname = "PCnet/FAST 79C971"; /* PCI */
1657                 fdx = 1;
1658                 mii = 1;
1659                 fset = 1;
1660                 break;
1661         case 0x2624:
1662                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1663                 fdx = 1;
1664                 mii = 1;
1665                 fset = 1;
1666                 break;
1667         case 0x2625:
1668                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1669                 fdx = 1;
1670                 mii = 1;
1671                 break;
1672         case 0x2626:
1673                 chipname = "PCnet/Home 79C978"; /* PCI */
1674                 fdx = 1;
1675                 /*
1676                  * This is based on specs published at www.amd.com.  This section
1677                  * assumes that a card with a 79C978 wants to go into standard
1678                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1679                  * and the module option homepna=1 can select this instead.
1680                  */
1681                 media = a->read_bcr(ioaddr, 49);
1682                 media &= ~3;    /* default to 10Mb ethernet */
1683                 if (cards_found < MAX_UNITS && homepna[cards_found])
1684                         media |= 1;     /* switch to home wiring mode */
1685                 if (pcnet32_debug & NETIF_MSG_PROBE)
1686                         printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1687                                (media & 1) ? "1" : "10");
1688                 a->write_bcr(ioaddr, 49, media);
1689                 break;
1690         case 0x2627:
1691                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1692                 fdx = 1;
1693                 mii = 1;
1694                 break;
1695         case 0x2628:
1696                 chipname = "PCnet/PRO 79C976";
1697                 fdx = 1;
1698                 mii = 1;
1699                 break;
1700         default:
1701                 if (pcnet32_debug & NETIF_MSG_PROBE)
1702                         printk(KERN_INFO PFX
1703                                "PCnet version %#x, no PCnet32 chip.\n",
1704                                chip_version);
1705                 goto err_release_region;
1706         }
1707
1708         /*
1709          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1710          *  starting until the packet is loaded. Strike one for reliability, lose
1711          *  one for latency - although on PCI this isnt a big loss. Older chips
1712          *  have FIFO's smaller than a packet, so you can't do this.
1713          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1714          */
1715
1716         if (fset) {
1717                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1718                 a->write_csr(ioaddr, 80,
1719                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1720                 dxsuflo = 1;
1721         }
1722
1723         dev = alloc_etherdev(sizeof(*lp));
1724         if (!dev) {
1725                 if (pcnet32_debug & NETIF_MSG_PROBE)
1726                         printk(KERN_ERR PFX "Memory allocation failed.\n");
1727                 ret = -ENOMEM;
1728                 goto err_release_region;
1729         }
1730         SET_NETDEV_DEV(dev, &pdev->dev);
1731
1732         if (pcnet32_debug & NETIF_MSG_PROBE)
1733                 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1734
1735         /* In most chips, after a chip reset, the ethernet address is read from the
1736          * station address PROM at the base address and programmed into the
1737          * "Physical Address Registers" CSR12-14.
1738          * As a precautionary measure, we read the PROM values and complain if
1739          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1740          * is valid, then the PROM addr is used.
1741          */
1742         for (i = 0; i < 3; i++) {
1743                 unsigned int val;
1744                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1745                 /* There may be endianness issues here. */
1746                 dev->dev_addr[2 * i] = val & 0x0ff;
1747                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1748         }
1749
1750         /* read PROM address and compare with CSR address */
1751         for (i = 0; i < 6; i++)
1752                 promaddr[i] = inb(ioaddr + i);
1753
1754         if (memcmp(promaddr, dev->dev_addr, 6)
1755             || !is_valid_ether_addr(dev->dev_addr)) {
1756                 if (is_valid_ether_addr(promaddr)) {
1757                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1758                                 printk(" warning: CSR address invalid,\n");
1759                                 printk(KERN_INFO
1760                                        "    using instead PROM address of");
1761                         }
1762                         memcpy(dev->dev_addr, promaddr, 6);
1763                 }
1764         }
1765         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1766
1767         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1768         if (!is_valid_ether_addr(dev->perm_addr))
1769                 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1770
1771         if (pcnet32_debug & NETIF_MSG_PROBE) {
1772                 for (i = 0; i < 6; i++)
1773                         printk(" %2.2x", dev->dev_addr[i]);
1774
1775                 /* Version 0x2623 and 0x2624 */
1776                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1777                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1778                         printk("\n" KERN_INFO "    tx_start_pt(0x%04x):", i);
1779                         switch (i >> 10) {
1780                         case 0:
1781                                 printk("  20 bytes,");
1782                                 break;
1783                         case 1:
1784                                 printk("  64 bytes,");
1785                                 break;
1786                         case 2:
1787                                 printk(" 128 bytes,");
1788                                 break;
1789                         case 3:
1790                                 printk("~220 bytes,");
1791                                 break;
1792                         }
1793                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1794                         printk(" BCR18(%x):", i & 0xffff);
1795                         if (i & (1 << 5))
1796                                 printk("BurstWrEn ");
1797                         if (i & (1 << 6))
1798                                 printk("BurstRdEn ");
1799                         if (i & (1 << 7))
1800                                 printk("DWordIO ");
1801                         if (i & (1 << 11))
1802                                 printk("NoUFlow ");
1803                         i = a->read_bcr(ioaddr, 25);
1804                         printk("\n" KERN_INFO "    SRAMSIZE=0x%04x,", i << 8);
1805                         i = a->read_bcr(ioaddr, 26);
1806                         printk(" SRAM_BND=0x%04x,", i << 8);
1807                         i = a->read_bcr(ioaddr, 27);
1808                         if (i & (1 << 14))
1809                                 printk("LowLatRx");
1810                 }
1811         }
1812
1813         dev->base_addr = ioaddr;
1814         lp = netdev_priv(dev);
1815         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1816         if ((lp->init_block =
1817              pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1818                 if (pcnet32_debug & NETIF_MSG_PROBE)
1819                         printk(KERN_ERR PFX
1820                                "Consistent memory allocation failed.\n");
1821                 ret = -ENOMEM;
1822                 goto err_free_netdev;
1823         }
1824         lp->pci_dev = pdev;
1825
1826         lp->dev = dev;
1827
1828         spin_lock_init(&lp->lock);
1829
1830         SET_NETDEV_DEV(dev, &pdev->dev);
1831         lp->name = chipname;
1832         lp->shared_irq = shared;
1833         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1834         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1835         lp->tx_mod_mask = lp->tx_ring_size - 1;
1836         lp->rx_mod_mask = lp->rx_ring_size - 1;
1837         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1838         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1839         lp->mii_if.full_duplex = fdx;
1840         lp->mii_if.phy_id_mask = 0x1f;
1841         lp->mii_if.reg_num_mask = 0x1f;
1842         lp->dxsuflo = dxsuflo;
1843         lp->mii = mii;
1844         lp->chip_version = chip_version;
1845         lp->msg_enable = pcnet32_debug;
1846         if ((cards_found >= MAX_UNITS)
1847             || (options[cards_found] > sizeof(options_mapping)))
1848                 lp->options = PCNET32_PORT_ASEL;
1849         else
1850                 lp->options = options_mapping[options[cards_found]];
1851         lp->mii_if.dev = dev;
1852         lp->mii_if.mdio_read = mdio_read;
1853         lp->mii_if.mdio_write = mdio_write;
1854
1855         /* napi.weight is used in both the napi and non-napi cases */
1856         lp->napi.weight = lp->rx_ring_size / 2;
1857
1858 #ifdef CONFIG_PCNET32_NAPI
1859         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1860 #endif
1861
1862         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1863             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1864                 lp->options |= PCNET32_PORT_FD;
1865
1866         if (!a) {
1867                 if (pcnet32_debug & NETIF_MSG_PROBE)
1868                         printk(KERN_ERR PFX "No access methods\n");
1869                 ret = -ENODEV;
1870                 goto err_free_consistent;
1871         }
1872         lp->a = *a;
1873
1874         /* prior to register_netdev, dev->name is not yet correct */
1875         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1876                 ret = -ENOMEM;
1877                 goto err_free_ring;
1878         }
1879         /* detect special T1/E1 WAN card by checking for MAC address */
1880         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1881             && dev->dev_addr[2] == 0x75)
1882                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1883
1884         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1885         lp->init_block->tlen_rlen =
1886             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1887         for (i = 0; i < 6; i++)
1888                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1889         lp->init_block->filter[0] = 0x00000000;
1890         lp->init_block->filter[1] = 0x00000000;
1891         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1892         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1893
1894         /* switch pcnet32 to 32bit mode */
1895         a->write_bcr(ioaddr, 20, 2);
1896
1897         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1898         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1899
1900         if (pdev) {             /* use the IRQ provided by PCI */
1901                 dev->irq = pdev->irq;
1902                 if (pcnet32_debug & NETIF_MSG_PROBE)
1903                         printk(" assigned IRQ %d.\n", dev->irq);
1904         } else {
1905                 unsigned long irq_mask = probe_irq_on();
1906
1907                 /*
1908                  * To auto-IRQ we enable the initialization-done and DMA error
1909                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1910                  * boards will work.
1911                  */
1912                 /* Trigger an initialization just for the interrupt. */
1913                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1914                 mdelay(1);
1915
1916                 dev->irq = probe_irq_off(irq_mask);
1917                 if (!dev->irq) {
1918                         if (pcnet32_debug & NETIF_MSG_PROBE)
1919                                 printk(", failed to detect IRQ line.\n");
1920                         ret = -ENODEV;
1921                         goto err_free_ring;
1922                 }
1923                 if (pcnet32_debug & NETIF_MSG_PROBE)
1924                         printk(", probed IRQ %d.\n", dev->irq);
1925         }
1926
1927         /* Set the mii phy_id so that we can query the link state */
1928         if (lp->mii) {
1929                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1930
1931                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1932                 /* scan for PHYs */
1933                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1934                         unsigned short id1, id2;
1935
1936                         id1 = mdio_read(dev, i, MII_PHYSID1);
1937                         if (id1 == 0xffff)
1938                                 continue;
1939                         id2 = mdio_read(dev, i, MII_PHYSID2);
1940                         if (id2 == 0xffff)
1941                                 continue;
1942                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1943                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1944                         lp->phycount++;
1945                         lp->phymask |= (1 << i);
1946                         lp->mii_if.phy_id = i;
1947                         if (pcnet32_debug & NETIF_MSG_PROBE)
1948                                 printk(KERN_INFO PFX
1949                                        "Found PHY %04x:%04x at address %d.\n",
1950                                        id1, id2, i);
1951                 }
1952                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1953                 if (lp->phycount > 1) {
1954                         lp->options |= PCNET32_PORT_MII;
1955                 }
1956         }
1957
1958         init_timer(&lp->watchdog_timer);
1959         lp->watchdog_timer.data = (unsigned long)dev;
1960         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1961
1962         /* The PCNET32-specific entries in the device structure. */
1963         dev->open = &pcnet32_open;
1964         dev->hard_start_xmit = &pcnet32_start_xmit;
1965         dev->stop = &pcnet32_close;
1966         dev->get_stats = &pcnet32_get_stats;
1967         dev->set_multicast_list = &pcnet32_set_multicast_list;
1968         dev->do_ioctl = &pcnet32_ioctl;
1969         dev->ethtool_ops = &pcnet32_ethtool_ops;
1970         dev->tx_timeout = pcnet32_tx_timeout;
1971         dev->watchdog_timeo = (5 * HZ);
1972
1973 #ifdef CONFIG_NET_POLL_CONTROLLER
1974         dev->poll_controller = pcnet32_poll_controller;
1975 #endif
1976
1977         /* Fill in the generic fields of the device structure. */
1978         if (register_netdev(dev))
1979                 goto err_free_ring;
1980
1981         if (pdev) {
1982                 pci_set_drvdata(pdev, dev);
1983         } else {
1984                 lp->next = pcnet32_dev;
1985                 pcnet32_dev = dev;
1986         }
1987
1988         if (pcnet32_debug & NETIF_MSG_PROBE)
1989                 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1990         cards_found++;
1991
1992         /* enable LED writes */
1993         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1994
1995         return 0;
1996
1997       err_free_ring:
1998         pcnet32_free_ring(dev);
1999       err_free_consistent:
2000         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2001                             lp->init_block, lp->init_dma_addr);
2002       err_free_netdev:
2003         free_netdev(dev);
2004       err_release_region:
2005         release_region(ioaddr, PCNET32_TOTAL_SIZE);
2006         return ret;
2007 }
2008
2009 /* if any allocation fails, caller must also call pcnet32_free_ring */
2010 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2011 {
2012         struct pcnet32_private *lp = netdev_priv(dev);
2013
2014         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2015                                            sizeof(struct pcnet32_tx_head) *
2016                                            lp->tx_ring_size,
2017                                            &lp->tx_ring_dma_addr);
2018         if (lp->tx_ring == NULL) {
2019                 if (netif_msg_drv(lp))
2020                         printk("\n" KERN_ERR PFX
2021                                "%s: Consistent memory allocation failed.\n",
2022                                name);
2023                 return -ENOMEM;
2024         }
2025
2026         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2027                                            sizeof(struct pcnet32_rx_head) *
2028                                            lp->rx_ring_size,
2029                                            &lp->rx_ring_dma_addr);
2030         if (lp->rx_ring == NULL) {
2031                 if (netif_msg_drv(lp))
2032                         printk("\n" KERN_ERR PFX
2033                                "%s: Consistent memory allocation failed.\n",
2034                                name);
2035                 return -ENOMEM;
2036         }
2037
2038         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2039                                   GFP_ATOMIC);
2040         if (!lp->tx_dma_addr) {
2041                 if (netif_msg_drv(lp))
2042                         printk("\n" KERN_ERR PFX
2043                                "%s: Memory allocation failed.\n", name);
2044                 return -ENOMEM;
2045         }
2046
2047         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2048                                   GFP_ATOMIC);
2049         if (!lp->rx_dma_addr) {
2050                 if (netif_msg_drv(lp))
2051                         printk("\n" KERN_ERR PFX
2052                                "%s: Memory allocation failed.\n", name);
2053                 return -ENOMEM;
2054         }
2055
2056         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2057                                 GFP_ATOMIC);
2058         if (!lp->tx_skbuff) {
2059                 if (netif_msg_drv(lp))
2060                         printk("\n" KERN_ERR PFX
2061                                "%s: Memory allocation failed.\n", name);
2062                 return -ENOMEM;
2063         }
2064
2065         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2066                                 GFP_ATOMIC);
2067         if (!lp->rx_skbuff) {
2068                 if (netif_msg_drv(lp))
2069                         printk("\n" KERN_ERR PFX
2070                                "%s: Memory allocation failed.\n", name);
2071                 return -ENOMEM;
2072         }
2073
2074         return 0;
2075 }
2076
2077 static void pcnet32_free_ring(struct net_device *dev)
2078 {
2079         struct pcnet32_private *lp = netdev_priv(dev);
2080
2081         kfree(lp->tx_skbuff);
2082         lp->tx_skbuff = NULL;
2083
2084         kfree(lp->rx_skbuff);
2085         lp->rx_skbuff = NULL;
2086
2087         kfree(lp->tx_dma_addr);
2088         lp->tx_dma_addr = NULL;
2089
2090         kfree(lp->rx_dma_addr);
2091         lp->rx_dma_addr = NULL;
2092
2093         if (lp->tx_ring) {
2094                 pci_free_consistent(lp->pci_dev,
2095                                     sizeof(struct pcnet32_tx_head) *
2096                                     lp->tx_ring_size, lp->tx_ring,
2097                                     lp->tx_ring_dma_addr);
2098                 lp->tx_ring = NULL;
2099         }
2100
2101         if (lp->rx_ring) {
2102                 pci_free_consistent(lp->pci_dev,
2103                                     sizeof(struct pcnet32_rx_head) *
2104                                     lp->rx_ring_size, lp->rx_ring,
2105                                     lp->rx_ring_dma_addr);
2106                 lp->rx_ring = NULL;
2107         }
2108 }
2109
2110 static int pcnet32_open(struct net_device *dev)
2111 {
2112         struct pcnet32_private *lp = netdev_priv(dev);
2113         unsigned long ioaddr = dev->base_addr;
2114         u16 val;
2115         int i;
2116         int rc;
2117         unsigned long flags;
2118
2119         if (request_irq(dev->irq, &pcnet32_interrupt,
2120                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2121                         (void *)dev)) {
2122                 return -EAGAIN;
2123         }
2124
2125         spin_lock_irqsave(&lp->lock, flags);
2126         /* Check for a valid station address */
2127         if (!is_valid_ether_addr(dev->dev_addr)) {
2128                 rc = -EINVAL;
2129                 goto err_free_irq;
2130         }
2131
2132         /* Reset the PCNET32 */
2133         lp->a.reset(ioaddr);
2134
2135         /* switch pcnet32 to 32bit mode */
2136         lp->a.write_bcr(ioaddr, 20, 2);
2137
2138         if (netif_msg_ifup(lp))
2139                 printk(KERN_DEBUG
2140                        "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2141                        dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2142                        (u32) (lp->rx_ring_dma_addr),
2143                        (u32) (lp->init_dma_addr));
2144
2145         /* set/reset autoselect bit */
2146         val = lp->a.read_bcr(ioaddr, 2) & ~2;
2147         if (lp->options & PCNET32_PORT_ASEL)
2148                 val |= 2;
2149         lp->a.write_bcr(ioaddr, 2, val);
2150
2151         /* handle full duplex setting */
2152         if (lp->mii_if.full_duplex) {
2153                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2154                 if (lp->options & PCNET32_PORT_FD) {
2155                         val |= 1;
2156                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2157                                 val |= 2;
2158                 } else if (lp->options & PCNET32_PORT_ASEL) {
2159                         /* workaround of xSeries250, turn on for 79C975 only */
2160                         if (lp->chip_version == 0x2627)
2161                                 val |= 3;
2162                 }
2163                 lp->a.write_bcr(ioaddr, 9, val);
2164         }
2165
2166         /* set/reset GPSI bit in test register */
2167         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2168         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2169                 val |= 0x10;
2170         lp->a.write_csr(ioaddr, 124, val);
2171
2172         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2173         if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2174             (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2175              lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2176                 if (lp->options & PCNET32_PORT_ASEL) {
2177                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2178                         if (netif_msg_link(lp))
2179                                 printk(KERN_DEBUG
2180                                        "%s: Setting 100Mb-Full Duplex.\n",
2181                                        dev->name);
2182                 }
2183         }
2184         if (lp->phycount < 2) {
2185                 /*
2186                  * 24 Jun 2004 according AMD, in order to change the PHY,
2187                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2188                  * duplex, and/or enable auto negotiation, and clear DANAS
2189                  */
2190                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2191                         lp->a.write_bcr(ioaddr, 32,
2192                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
2193                         /* disable Auto Negotiation, set 10Mpbs, HD */
2194                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2195                         if (lp->options & PCNET32_PORT_FD)
2196                                 val |= 0x10;
2197                         if (lp->options & PCNET32_PORT_100)
2198                                 val |= 0x08;
2199                         lp->a.write_bcr(ioaddr, 32, val);
2200                 } else {
2201                         if (lp->options & PCNET32_PORT_ASEL) {
2202                                 lp->a.write_bcr(ioaddr, 32,
2203                                                 lp->a.read_bcr(ioaddr,
2204                                                                32) | 0x0080);
2205                                 /* enable auto negotiate, setup, disable fd */
2206                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2207                                 val |= 0x20;
2208                                 lp->a.write_bcr(ioaddr, 32, val);
2209                         }
2210                 }
2211         } else {
2212                 int first_phy = -1;
2213                 u16 bmcr;
2214                 u32 bcr9;
2215                 struct ethtool_cmd ecmd;
2216
2217                 /*
2218                  * There is really no good other way to handle multiple PHYs
2219                  * other than turning off all automatics
2220                  */
2221                 val = lp->a.read_bcr(ioaddr, 2);
2222                 lp->a.write_bcr(ioaddr, 2, val & ~2);
2223                 val = lp->a.read_bcr(ioaddr, 32);
2224                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
2225
2226                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2227                         /* setup ecmd */
2228                         ecmd.port = PORT_MII;
2229                         ecmd.transceiver = XCVR_INTERNAL;
2230                         ecmd.autoneg = AUTONEG_DISABLE;
2231                         ecmd.speed =
2232                             lp->
2233                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2234                         bcr9 = lp->a.read_bcr(ioaddr, 9);
2235
2236                         if (lp->options & PCNET32_PORT_FD) {
2237                                 ecmd.duplex = DUPLEX_FULL;
2238                                 bcr9 |= (1 << 0);
2239                         } else {
2240                                 ecmd.duplex = DUPLEX_HALF;
2241                                 bcr9 |= ~(1 << 0);
2242                         }
2243                         lp->a.write_bcr(ioaddr, 9, bcr9);
2244                 }
2245
2246                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2247                         if (lp->phymask & (1 << i)) {
2248                                 /* isolate all but the first PHY */
2249                                 bmcr = mdio_read(dev, i, MII_BMCR);
2250                                 if (first_phy == -1) {
2251                                         first_phy = i;
2252                                         mdio_write(dev, i, MII_BMCR,
2253                                                    bmcr & ~BMCR_ISOLATE);
2254                                 } else {
2255                                         mdio_write(dev, i, MII_BMCR,
2256                                                    bmcr | BMCR_ISOLATE);
2257                                 }
2258                                 /* use mii_ethtool_sset to setup PHY */
2259                                 lp->mii_if.phy_id = i;
2260                                 ecmd.phy_address = i;
2261                                 if (lp->options & PCNET32_PORT_ASEL) {
2262                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2263                                         ecmd.autoneg = AUTONEG_ENABLE;
2264                                 }
2265                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2266                         }
2267                 }
2268                 lp->mii_if.phy_id = first_phy;
2269                 if (netif_msg_link(lp))
2270                         printk(KERN_INFO "%s: Using PHY number %d.\n",
2271                                dev->name, first_phy);
2272         }
2273
2274 #ifdef DO_DXSUFLO
2275         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2276                 val = lp->a.read_csr(ioaddr, CSR3);
2277                 val |= 0x40;
2278                 lp->a.write_csr(ioaddr, CSR3, val);
2279         }
2280 #endif
2281
2282         lp->init_block->mode =
2283             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2284         pcnet32_load_multicast(dev);
2285
2286         if (pcnet32_init_ring(dev)) {
2287                 rc = -ENOMEM;
2288                 goto err_free_ring;
2289         }
2290
2291 #ifdef CONFIG_PCNET32_NAPI
2292         napi_enable(&lp->napi);
2293 #endif
2294
2295         /* Re-initialize the PCNET32, and start it when done. */
2296         lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2297         lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2298
2299         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
2300         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2301
2302         netif_start_queue(dev);
2303
2304         if (lp->chip_version >= PCNET32_79C970A) {
2305                 /* Print the link status and start the watchdog */
2306                 pcnet32_check_media(dev, 1);
2307                 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2308         }
2309
2310         i = 0;
2311         while (i++ < 100)
2312                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2313                         break;
2314         /*
2315          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2316          * reports that doing so triggers a bug in the '974.
2317          */
2318         lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2319
2320         if (netif_msg_ifup(lp))
2321                 printk(KERN_DEBUG
2322                        "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2323                        dev->name, i,
2324                        (u32) (lp->init_dma_addr),
2325                        lp->a.read_csr(ioaddr, CSR0));
2326
2327         spin_unlock_irqrestore(&lp->lock, flags);
2328
2329         return 0;               /* Always succeed */
2330
2331       err_free_ring:
2332         /* free any allocated skbuffs */
2333         pcnet32_purge_rx_ring(dev);
2334
2335         /*
2336          * Switch back to 16bit mode to avoid problems with dumb
2337          * DOS packet driver after a warm reboot
2338          */
2339         lp->a.write_bcr(ioaddr, 20, 4);
2340
2341       err_free_irq:
2342         spin_unlock_irqrestore(&lp->lock, flags);
2343         free_irq(dev->irq, dev);
2344         return rc;
2345 }
2346
2347 /*
2348  * The LANCE has been halted for one reason or another (busmaster memory
2349  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2350  * etc.).  Modern LANCE variants always reload their ring-buffer
2351  * configuration when restarted, so we must reinitialize our ring
2352  * context before restarting.  As part of this reinitialization,
2353  * find all packets still on the Tx ring and pretend that they had been
2354  * sent (in effect, drop the packets on the floor) - the higher-level
2355  * protocols will time out and retransmit.  It'd be better to shuffle
2356  * these skbs to a temp list and then actually re-Tx them after
2357  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2358  */
2359
2360 static void pcnet32_purge_tx_ring(struct net_device *dev)
2361 {
2362         struct pcnet32_private *lp = netdev_priv(dev);
2363         int i;
2364
2365         for (i = 0; i < lp->tx_ring_size; i++) {
2366                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2367                 wmb();          /* Make sure adapter sees owner change */
2368                 if (lp->tx_skbuff[i]) {
2369                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2370                                          lp->tx_skbuff[i]->len,
2371                                          PCI_DMA_TODEVICE);
2372                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2373                 }
2374                 lp->tx_skbuff[i] = NULL;
2375                 lp->tx_dma_addr[i] = 0;
2376         }
2377 }
2378
2379 /* Initialize the PCNET32 Rx and Tx rings. */
2380 static int pcnet32_init_ring(struct net_device *dev)
2381 {
2382         struct pcnet32_private *lp = netdev_priv(dev);
2383         int i;
2384
2385         lp->tx_full = 0;
2386         lp->cur_rx = lp->cur_tx = 0;
2387         lp->dirty_rx = lp->dirty_tx = 0;
2388
2389         for (i = 0; i < lp->rx_ring_size; i++) {
2390                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2391                 if (rx_skbuff == NULL) {
2392                         if (!
2393                             (rx_skbuff = lp->rx_skbuff[i] =
2394                              dev_alloc_skb(PKT_BUF_SZ))) {
2395                                 /* there is not much, we can do at this point */
2396                                 if (netif_msg_drv(lp))
2397                                         printk(KERN_ERR
2398                                                "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2399                                                dev->name);
2400                                 return -1;
2401                         }
2402                         skb_reserve(rx_skbuff, 2);
2403                 }
2404
2405                 rmb();
2406                 if (lp->rx_dma_addr[i] == 0)
2407                         lp->rx_dma_addr[i] =
2408                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2409                                            PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2410                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2411                 lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
2412                 wmb();          /* Make sure owner changes after all others are visible */
2413                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2414         }
2415         /* The Tx buffer address is filled in as needed, but we do need to clear
2416          * the upper ownership bit. */
2417         for (i = 0; i < lp->tx_ring_size; i++) {
2418                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2419                 wmb();          /* Make sure adapter sees owner change */
2420                 lp->tx_ring[i].base = 0;
2421                 lp->tx_dma_addr[i] = 0;
2422         }
2423
2424         lp->init_block->tlen_rlen =
2425             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2426         for (i = 0; i < 6; i++)
2427                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2428         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2429         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2430         wmb();                  /* Make sure all changes are visible */
2431         return 0;
2432 }
2433
2434 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2435  * then flush the pending transmit operations, re-initialize the ring,
2436  * and tell the chip to initialize.
2437  */
2438 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2439 {
2440         struct pcnet32_private *lp = netdev_priv(dev);
2441         unsigned long ioaddr = dev->base_addr;
2442         int i;
2443
2444         /* wait for stop */
2445         for (i = 0; i < 100; i++)
2446                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2447                         break;
2448
2449         if (i >= 100 && netif_msg_drv(lp))
2450                 printk(KERN_ERR
2451                        "%s: pcnet32_restart timed out waiting for stop.\n",
2452                        dev->name);
2453
2454         pcnet32_purge_tx_ring(dev);
2455         if (pcnet32_init_ring(dev))
2456                 return;
2457
2458         /* ReInit Ring */
2459         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2460         i = 0;
2461         while (i++ < 1000)
2462                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2463                         break;
2464
2465         lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2466 }
2467
2468 static void pcnet32_tx_timeout(struct net_device *dev)
2469 {
2470         struct pcnet32_private *lp = netdev_priv(dev);
2471         unsigned long ioaddr = dev->base_addr, flags;
2472
2473         spin_lock_irqsave(&lp->lock, flags);
2474         /* Transmitter timeout, serious problems. */
2475         if (pcnet32_debug & NETIF_MSG_DRV)
2476                 printk(KERN_ERR
2477                        "%s: transmit timed out, status %4.4x, resetting.\n",
2478                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2479         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2480         dev->stats.tx_errors++;
2481         if (netif_msg_tx_err(lp)) {
2482                 int i;
2483                 printk(KERN_DEBUG
2484                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2485                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2486                        lp->cur_rx);
2487                 for (i = 0; i < lp->rx_ring_size; i++)
2488                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2489                                le32_to_cpu(lp->rx_ring[i].base),
2490                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2491                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2492                                le16_to_cpu(lp->rx_ring[i].status));
2493                 for (i = 0; i < lp->tx_ring_size; i++)
2494                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2495                                le32_to_cpu(lp->tx_ring[i].base),
2496                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2497                                le32_to_cpu(lp->tx_ring[i].misc),
2498                                le16_to_cpu(lp->tx_ring[i].status));
2499                 printk("\n");
2500         }
2501         pcnet32_restart(dev, CSR0_NORMAL);
2502
2503         dev->trans_start = jiffies;
2504         netif_wake_queue(dev);
2505
2506         spin_unlock_irqrestore(&lp->lock, flags);
2507 }
2508
2509 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2510 {
2511         struct pcnet32_private *lp = netdev_priv(dev);
2512         unsigned long ioaddr = dev->base_addr;
2513         u16 status;
2514         int entry;
2515         unsigned long flags;
2516
2517         spin_lock_irqsave(&lp->lock, flags);
2518
2519         if (netif_msg_tx_queued(lp)) {
2520                 printk(KERN_DEBUG
2521                        "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2522                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2523         }
2524
2525         /* Default status -- will not enable Successful-TxDone
2526          * interrupt when that option is available to us.
2527          */
2528         status = 0x8300;
2529
2530         /* Fill in a Tx ring entry */
2531
2532         /* Mask to ring buffer boundary. */
2533         entry = lp->cur_tx & lp->tx_mod_mask;
2534
2535         /* Caution: the write order is important here, set the status
2536          * with the "ownership" bits last. */
2537
2538         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2539
2540         lp->tx_ring[entry].misc = 0x00000000;
2541
2542         lp->tx_skbuff[entry] = skb;
2543         lp->tx_dma_addr[entry] =
2544             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2545         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2546         wmb();                  /* Make sure owner changes after all others are visible */
2547         lp->tx_ring[entry].status = cpu_to_le16(status);
2548
2549         lp->cur_tx++;
2550         dev->stats.tx_bytes += skb->len;
2551
2552         /* Trigger an immediate send poll. */
2553         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2554
2555         dev->trans_start = jiffies;
2556
2557         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2558                 lp->tx_full = 1;
2559                 netif_stop_queue(dev);
2560         }
2561         spin_unlock_irqrestore(&lp->lock, flags);
2562         return 0;
2563 }
2564
2565 /* The PCNET32 interrupt handler. */
2566 static irqreturn_t
2567 pcnet32_interrupt(int irq, void *dev_id)
2568 {
2569         struct net_device *dev = dev_id;
2570         struct pcnet32_private *lp;
2571         unsigned long ioaddr;
2572         u16 csr0;
2573         int boguscnt = max_interrupt_work;
2574
2575         ioaddr = dev->base_addr;
2576         lp = netdev_priv(dev);
2577
2578         spin_lock(&lp->lock);
2579
2580         csr0 = lp->a.read_csr(ioaddr, CSR0);
2581         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2582                 if (csr0 == 0xffff) {
2583                         break;  /* PCMCIA remove happened */
2584                 }
2585                 /* Acknowledge all of the current interrupt sources ASAP. */
2586                 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2587
2588                 if (netif_msg_intr(lp))
2589                         printk(KERN_DEBUG
2590                                "%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
2591                                dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2592
2593                 /* Log misc errors. */
2594                 if (csr0 & 0x4000)
2595                         dev->stats.tx_errors++; /* Tx babble. */
2596                 if (csr0 & 0x1000) {
2597                         /*
2598                          * This happens when our receive ring is full. This
2599                          * shouldn't be a problem as we will see normal rx
2600                          * interrupts for the frames in the receive ring.  But
2601                          * there are some PCI chipsets (I can reproduce this
2602                          * on SP3G with Intel saturn chipset) which have
2603                          * sometimes problems and will fill up the receive
2604                          * ring with error descriptors.  In this situation we
2605                          * don't get a rx interrupt, but a missed frame
2606                          * interrupt sooner or later.
2607                          */
2608                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2609                 }
2610                 if (csr0 & 0x0800) {
2611                         if (netif_msg_drv(lp))
2612                                 printk(KERN_ERR
2613                                        "%s: Bus master arbitration failure, status %4.4x.\n",
2614                                        dev->name, csr0);
2615                         /* unlike for the lance, there is no restart needed */
2616                 }
2617 #ifdef CONFIG_PCNET32_NAPI
2618                 if (netif_rx_schedule_prep(dev, &lp->napi)) {
2619                         u16 val;
2620                         /* set interrupt masks */
2621                         val = lp->a.read_csr(ioaddr, CSR3);
2622                         val |= 0x5f00;
2623                         lp->a.write_csr(ioaddr, CSR3, val);
2624                         mmiowb();
2625                         __netif_rx_schedule(dev, &lp->napi);
2626                         break;
2627                 }
2628 #else
2629                 pcnet32_rx(dev, lp->napi.weight);
2630                 if (pcnet32_tx(dev)) {
2631                         /* reset the chip to clear the error condition, then restart */
2632                         lp->a.reset(ioaddr);
2633                         lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2634                         pcnet32_restart(dev, CSR0_START);
2635                         netif_wake_queue(dev);
2636                 }
2637 #endif
2638                 csr0 = lp->a.read_csr(ioaddr, CSR0);
2639         }
2640
2641 #ifndef CONFIG_PCNET32_NAPI
2642         /* Set interrupt enable. */
2643         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2644 #endif
2645
2646         if (netif_msg_intr(lp))
2647                 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2648                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2649
2650         spin_unlock(&lp->lock);
2651
2652         return IRQ_HANDLED;
2653 }
2654
2655 static int pcnet32_close(struct net_device *dev)
2656 {
2657         unsigned long ioaddr = dev->base_addr;
2658         struct pcnet32_private *lp = netdev_priv(dev);
2659         unsigned long flags;
2660
2661         del_timer_sync(&lp->watchdog_timer);
2662
2663         netif_stop_queue(dev);
2664 #ifdef CONFIG_PCNET32_NAPI
2665         napi_disable(&lp->napi);
2666 #endif
2667
2668         spin_lock_irqsave(&lp->lock, flags);
2669
2670         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2671
2672         if (netif_msg_ifdown(lp))
2673                 printk(KERN_DEBUG
2674                        "%s: Shutting down ethercard, status was %2.2x.\n",
2675                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2676
2677         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2678         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2679
2680         /*
2681          * Switch back to 16bit mode to avoid problems with dumb
2682          * DOS packet driver after a warm reboot
2683          */
2684         lp->a.write_bcr(ioaddr, 20, 4);
2685
2686         spin_unlock_irqrestore(&lp->lock, flags);
2687
2688         free_irq(dev->irq, dev);
2689
2690         spin_lock_irqsave(&lp->lock, flags);
2691
2692         pcnet32_purge_rx_ring(dev);
2693         pcnet32_purge_tx_ring(dev);
2694
2695         spin_unlock_irqrestore(&lp->lock, flags);
2696
2697         return 0;
2698 }
2699
2700 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2701 {
2702         struct pcnet32_private *lp = netdev_priv(dev);
2703         unsigned long ioaddr = dev->base_addr;
2704         unsigned long flags;
2705
2706         spin_lock_irqsave(&lp->lock, flags);
2707         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2708         spin_unlock_irqrestore(&lp->lock, flags);
2709
2710         return &dev->stats;
2711 }
2712
2713 /* taken from the sunlance driver, which it took from the depca driver */
2714 static void pcnet32_load_multicast(struct net_device *dev)
2715 {
2716         struct pcnet32_private *lp = netdev_priv(dev);
2717         volatile struct pcnet32_init_block *ib = lp->init_block;
2718         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2719         struct dev_mc_list *dmi = dev->mc_list;
2720         unsigned long ioaddr = dev->base_addr;
2721         char *addrs;
2722         int i;
2723         u32 crc;
2724
2725         /* set all multicast bits */
2726         if (dev->flags & IFF_ALLMULTI) {
2727                 ib->filter[0] = cpu_to_le32(~0U);
2728                 ib->filter[1] = cpu_to_le32(~0U);
2729                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2730                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2731                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2732                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2733                 return;
2734         }
2735         /* clear the multicast filter */
2736         ib->filter[0] = 0;
2737         ib->filter[1] = 0;
2738
2739         /* Add addresses */
2740         for (i = 0; i < dev->mc_count; i++) {
2741                 addrs = dmi->dmi_addr;
2742                 dmi = dmi->next;
2743
2744                 /* multicast address? */
2745                 if (!(*addrs & 1))
2746                         continue;
2747
2748                 crc = ether_crc_le(6, addrs);
2749                 crc = crc >> 26;
2750                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2751         }
2752         for (i = 0; i < 4; i++)
2753                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2754                                 le16_to_cpu(mcast_table[i]));
2755         return;
2756 }
2757
2758 /*
2759  * Set or clear the multicast filter for this adaptor.
2760  */
2761 static void pcnet32_set_multicast_list(struct net_device *dev)
2762 {
2763         unsigned long ioaddr = dev->base_addr, flags;
2764         struct pcnet32_private *lp = netdev_priv(dev);
2765         int csr15, suspended;
2766
2767         spin_lock_irqsave(&lp->lock, flags);
2768         suspended = pcnet32_suspend(dev, &flags, 0);
2769         csr15 = lp->a.read_csr(ioaddr, CSR15);
2770         if (dev->flags & IFF_PROMISC) {
2771                 /* Log any net taps. */
2772                 if (netif_msg_hw(lp))
2773                         printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2774                                dev->name);
2775                 lp->init_block->mode =
2776                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2777                                 7);
2778                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2779         } else {
2780                 lp->init_block->mode =
2781                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2782                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2783                 pcnet32_load_multicast(dev);
2784         }
2785
2786         if (suspended) {
2787                 int csr5;
2788                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2789                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2790                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2791         } else {
2792                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2793                 pcnet32_restart(dev, CSR0_NORMAL);
2794                 netif_wake_queue(dev);
2795         }
2796
2797         spin_unlock_irqrestore(&lp->lock, flags);
2798 }
2799
2800 /* This routine assumes that the lp->lock is held */
2801 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2802 {
2803         struct pcnet32_private *lp = netdev_priv(dev);
2804         unsigned long ioaddr = dev->base_addr;
2805         u16 val_out;
2806
2807         if (!lp->mii)
2808                 return 0;
2809
2810         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2811         val_out = lp->a.read_bcr(ioaddr, 34);
2812
2813         return val_out;
2814 }
2815
2816 /* This routine assumes that the lp->lock is held */
2817 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2818 {
2819         struct pcnet32_private *lp = netdev_priv(dev);
2820         unsigned long ioaddr = dev->base_addr;
2821
2822         if (!lp->mii)
2823                 return;
2824
2825         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2826         lp->a.write_bcr(ioaddr, 34, val);
2827 }
2828
2829 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2830 {
2831         struct pcnet32_private *lp = netdev_priv(dev);
2832         int rc;
2833         unsigned long flags;
2834
2835         /* SIOC[GS]MIIxxx ioctls */
2836         if (lp->mii) {
2837                 spin_lock_irqsave(&lp->lock, flags);
2838                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2839                 spin_unlock_irqrestore(&lp->lock, flags);
2840         } else {
2841                 rc = -EOPNOTSUPP;
2842         }
2843
2844         return rc;
2845 }
2846
2847 static int pcnet32_check_otherphy(struct net_device *dev)
2848 {
2849         struct pcnet32_private *lp = netdev_priv(dev);
2850         struct mii_if_info mii = lp->mii_if;
2851         u16 bmcr;
2852         int i;
2853
2854         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2855                 if (i == lp->mii_if.phy_id)
2856                         continue;       /* skip active phy */
2857                 if (lp->phymask & (1 << i)) {
2858                         mii.phy_id = i;
2859                         if (mii_link_ok(&mii)) {
2860                                 /* found PHY with active link */
2861                                 if (netif_msg_link(lp))
2862                                         printk(KERN_INFO
2863                                                "%s: Using PHY number %d.\n",
2864                                                dev->name, i);
2865
2866                                 /* isolate inactive phy */
2867                                 bmcr =
2868                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2869                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2870                                            bmcr | BMCR_ISOLATE);
2871
2872                                 /* de-isolate new phy */
2873                                 bmcr = mdio_read(dev, i, MII_BMCR);
2874                                 mdio_write(dev, i, MII_BMCR,
2875                                            bmcr & ~BMCR_ISOLATE);
2876
2877                                 /* set new phy address */
2878                                 lp->mii_if.phy_id = i;
2879                                 return 1;
2880                         }
2881                 }
2882         }
2883         return 0;
2884 }
2885
2886 /*
2887  * Show the status of the media.  Similar to mii_check_media however it
2888  * correctly shows the link speed for all (tested) pcnet32 variants.
2889  * Devices with no mii just report link state without speed.
2890  *
2891  * Caller is assumed to hold and release the lp->lock.
2892  */
2893
2894 static void pcnet32_check_media(struct net_device *dev, int verbose)
2895 {
2896         struct pcnet32_private *lp = netdev_priv(dev);
2897         int curr_link;
2898         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2899         u32 bcr9;
2900
2901         if (lp->mii) {
2902                 curr_link = mii_link_ok(&lp->mii_if);
2903         } else {
2904                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2905                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2906         }
2907         if (!curr_link) {
2908                 if (prev_link || verbose) {
2909                         netif_carrier_off(dev);
2910                         if (netif_msg_link(lp))
2911                                 printk(KERN_INFO "%s: link down\n", dev->name);
2912                 }
2913                 if (lp->phycount > 1) {
2914                         curr_link = pcnet32_check_otherphy(dev);
2915                         prev_link = 0;
2916                 }
2917         } else if (verbose || !prev_link) {
2918                 netif_carrier_on(dev);
2919                 if (lp->mii) {
2920                         if (netif_msg_link(lp)) {
2921                                 struct ethtool_cmd ecmd;
2922                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2923                                 printk(KERN_INFO
2924                                        "%s: link up, %sMbps, %s-duplex\n",
2925                                        dev->name,
2926                                        (ecmd.speed == SPEED_100) ? "100" : "10",
2927                                        (ecmd.duplex ==
2928                                         DUPLEX_FULL) ? "full" : "half");
2929                         }
2930                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2931                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2932                                 if (lp->mii_if.full_duplex)
2933                                         bcr9 |= (1 << 0);
2934                                 else
2935                                         bcr9 &= ~(1 << 0);
2936                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2937                         }
2938                 } else {
2939                         if (netif_msg_link(lp))
2940                                 printk(KERN_INFO "%s: link up\n", dev->name);
2941                 }
2942         }
2943 }
2944
2945 /*
2946  * Check for loss of link and link establishment.
2947  * Can not use mii_check_media because it does nothing if mode is forced.
2948  */
2949
2950 static void pcnet32_watchdog(struct net_device *dev)
2951 {
2952         struct pcnet32_private *lp = netdev_priv(dev);
2953         unsigned long flags;
2954
2955         /* Print the link status if it has changed */
2956         spin_lock_irqsave(&lp->lock, flags);
2957         pcnet32_check_media(dev, 0);
2958         spin_unlock_irqrestore(&lp->lock, flags);
2959
2960         mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2961 }
2962
2963 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2964 {
2965         struct net_device *dev = pci_get_drvdata(pdev);
2966
2967         if (netif_running(dev)) {
2968                 netif_device_detach(dev);
2969                 pcnet32_close(dev);
2970         }
2971         pci_save_state(pdev);
2972         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2973         return 0;
2974 }
2975
2976 static int pcnet32_pm_resume(struct pci_dev *pdev)
2977 {
2978         struct net_device *dev = pci_get_drvdata(pdev);
2979
2980         pci_set_power_state(pdev, PCI_D0);
2981         pci_restore_state(pdev);
2982
2983         if (netif_running(dev)) {
2984                 pcnet32_open(dev);
2985                 netif_device_attach(dev);
2986         }
2987         return 0;
2988 }
2989
2990 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2991 {
2992         struct net_device *dev = pci_get_drvdata(pdev);
2993
2994         if (dev) {
2995                 struct pcnet32_private *lp = netdev_priv(dev);
2996
2997                 unregister_netdev(dev);
2998                 pcnet32_free_ring(dev);
2999                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
3000                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3001                                     lp->init_block, lp->init_dma_addr);
3002                 free_netdev(dev);
3003                 pci_disable_device(pdev);
3004                 pci_set_drvdata(pdev, NULL);
3005         }
3006 }
3007
3008 static struct pci_driver pcnet32_driver = {
3009         .name = DRV_NAME,
3010         .probe = pcnet32_probe_pci,
3011         .remove = __devexit_p(pcnet32_remove_one),
3012         .id_table = pcnet32_pci_tbl,
3013         .suspend = pcnet32_pm_suspend,
3014         .resume = pcnet32_pm_resume,
3015 };
3016
3017 /* An additional parameter that may be passed in... */
3018 static int debug = -1;
3019 static int tx_start_pt = -1;
3020 static int pcnet32_have_pci;
3021
3022 module_param(debug, int, 0);
3023 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
3024 module_param(max_interrupt_work, int, 0);
3025 MODULE_PARM_DESC(max_interrupt_work,
3026                  DRV_NAME " maximum events handled per interrupt");
3027 module_param(rx_copybreak, int, 0);
3028 MODULE_PARM_DESC(rx_copybreak,
3029                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
3030 module_param(tx_start_pt, int, 0);
3031 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3032 module_param(pcnet32vlb, int, 0);
3033 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3034 module_param_array(options, int, NULL, 0);
3035 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3036 module_param_array(full_duplex, int, NULL, 0);
3037 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3038 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3039 module_param_array(homepna, int, NULL, 0);
3040 MODULE_PARM_DESC(homepna,
3041                  DRV_NAME
3042                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3043
3044 MODULE_AUTHOR("Thomas Bogendoerfer");
3045 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3046 MODULE_LICENSE("GPL");
3047
3048 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3049
3050 static int __init pcnet32_init_module(void)
3051 {
3052         printk(KERN_INFO "%s", version);
3053
3054         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3055
3056         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3057                 tx_start = tx_start_pt;
3058
3059         /* find the PCI devices */
3060         if (!pci_register_driver(&pcnet32_driver))
3061                 pcnet32_have_pci = 1;
3062
3063         /* should we find any remaining VLbus devices ? */
3064         if (pcnet32vlb)
3065                 pcnet32_probe_vlbus(pcnet32_portlist);
3066
3067         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3068                 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3069
3070         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3071 }
3072
3073 static void __exit pcnet32_cleanup_module(void)
3074 {
3075         struct net_device *next_dev;
3076
3077         while (pcnet32_dev) {
3078                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3079                 next_dev = lp->next;
3080                 unregister_netdev(pcnet32_dev);
3081                 pcnet32_free_ring(pcnet32_dev);
3082                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3083                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3084                                     lp->init_block, lp->init_dma_addr);
3085                 free_netdev(pcnet32_dev);
3086                 pcnet32_dev = next_dev;
3087         }
3088
3089         if (pcnet32_have_pci)
3090                 pci_unregister_driver(&pcnet32_driver);
3091 }
3092
3093 module_init(pcnet32_init_module);
3094 module_exit(pcnet32_cleanup_module);
3095
3096 /*
3097  * Local variables:
3098  *  c-indent-level: 4
3099  *  tab-width: 8
3100  * End:
3101  */