drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define DRV_NAME        "pcnet32"
  25 #define DRV_VERSION     "1.32"
  26 #define DRV_RELDATE     "18.Mar.2006"
  27 #define PFX             DRV_NAME ": "
  28
  29 static const char *const version =
  30     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/string.h>
  35 #include <linux/errno.h>
  36 #include <linux/ioport.h>
  37 #include <linux/slab.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/init.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/mii.h>
  44 #include <linux/crc32.h>
  45 #include <linux/netdevice.h>
  46 #include <linux/etherdevice.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/moduleparam.h>
  50 #include <linux/bitops.h>
  51
  52 #include <asm/dma.h>
  53 #include <asm/io.h>
  54 #include <asm/uaccess.h>
  55 #include <asm/irq.h>
  56
  57 /*
  58  * PCI device identifiers for "new style" Linux PCI Device Drivers
  59  */
  60 static struct pci_device_id pcnet32_pci_tbl[] = {
  61         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  62         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  63
  64         /*
  65          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  66          * the incorrect vendor id.
  67          */
  68         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  69           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  70
  71         { }     /* terminate list */
  72 };
  73
  74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  75
  76 static int cards_found;
  77
  78 /*
  79  * VLB I/O addresses
  80  */
  81 static unsigned int pcnet32_portlist[] __initdata =
  82     { 0x300, 0x320, 0x340, 0x360, 0 };
  83
  84 static int pcnet32_debug = 0;
  85 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  86 static int pcnet32vlb;          /* check for VLB cards ? */
  87
  88 static struct net_device *pcnet32_dev;
  89
  90 static int max_interrupt_work = 2;
  91 static int rx_copybreak = 200;
  92
  93 #define PCNET32_PORT_AUI      0x00
  94 #define PCNET32_PORT_10BT     0x01
  95 #define PCNET32_PORT_GPSI     0x02
  96 #define PCNET32_PORT_MII      0x03
  97
  98 #define PCNET32_PORT_PORTSEL  0x03
  99 #define PCNET32_PORT_ASEL     0x04
 100 #define PCNET32_PORT_100      0x40
 101 #define PCNET32_PORT_FD       0x80
 102
 103 #define PCNET32_DMA_MASK 0xffffffff
 104
 105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 106 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 107
 108 /*
 109  * table to translate option values from tulip
 110  * to internal options
 111  */
 112 static const unsigned char options_mapping[] = {
 113         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 114         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 115         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 116         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 117         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 118         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 119         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 120         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 121         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 122         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 123         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 124         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 125         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 126         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 127                                                 /* 14 MII 100BaseTx-FD */
 128         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 129         PCNET32_PORT_ASEL                       /* 15 not supported    */
 130 };
 131
 132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 133         "Loopback test  (offline)"
 134 };
 135
 136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
 137
 138 #define PCNET32_NUM_REGS 136
 139
 140 #define MAX_UNITS 8             /* More are supported, limit only on options */
 141 static int options[MAX_UNITS];
 142 static int full_duplex[MAX_UNITS];
 143 static int homepna[MAX_UNITS];
 144
 145 /*
 146  *                              Theory of Operation
 147  *
 148  * This driver uses the same software structure as the normal lance
 149  * driver. So look for a verbose description in lance.c. The differences
 150  * to the normal lance driver is the use of the 32bit mode of PCnet32
 151  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 152  * 16MB limitation and we don't need bounce buffers.
 153  */
 154
 155 /*
 156  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 157  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 158  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 159  */
 160 #ifndef PCNET32_LOG_TX_BUFFERS
 161 #define PCNET32_LOG_TX_BUFFERS          4
 162 #define PCNET32_LOG_RX_BUFFERS          5
 163 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 164 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 165 #endif
 166
 167 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 168 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 169
 170 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 171 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 172
 173 #define PKT_BUF_SZ              1544
 174
 175 /* Offsets from base I/O address. */
 176 #define PCNET32_WIO_RDP         0x10
 177 #define PCNET32_WIO_RAP         0x12
 178 #define PCNET32_WIO_RESET       0x14
 179 #define PCNET32_WIO_BDP         0x16
 180
 181 #define PCNET32_DWIO_RDP        0x10
 182 #define PCNET32_DWIO_RAP        0x14
 183 #define PCNET32_DWIO_RESET      0x18
 184 #define PCNET32_DWIO_BDP        0x1C
 185
 186 #define PCNET32_TOTAL_SIZE      0x20
 187
 188 #define CSR0            0
 189 #define CSR0_INIT       0x1
 190 #define CSR0_START      0x2
 191 #define CSR0_STOP       0x4
 192 #define CSR0_TXPOLL     0x8
 193 #define CSR0_INTEN      0x40
 194 #define CSR0_IDON       0x0100
 195 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 196 #define PCNET32_INIT_LOW        1
 197 #define PCNET32_INIT_HIGH       2
 198 #define CSR3            3
 199 #define CSR4            4
 200 #define CSR5            5
 201 #define CSR5_SUSPEND    0x0001
 202 #define CSR15           15
 203 #define PCNET32_MC_FILTER       8
 204
 205 /* The PCNET32 Rx and Tx ring descriptors. */
 206 struct pcnet32_rx_head {
 207         u32     base;
 208         s16     buf_length;
 209         s16     status;
 210         u32     msg_length;
 211         u32     reserved;
 212 };
 213
 214 struct pcnet32_tx_head {
 215         u32     base;
 216         s16     length;
 217         s16     status;
 218         u32     misc;
 219         u32     reserved;
 220 };
 221
 222 /* The PCNET32 32-Bit initialization block, described in databook. */
 223 struct pcnet32_init_block {
 224         u16     mode;
 225         u16     tlen_rlen;
 226         u8      phys_addr[6];
 227         u16     reserved;
 228         u32     filter[2];
 229         /* Receive and transmit ring base, along with extra bits. */
 230         u32     rx_ring;
 231         u32     tx_ring;
 232 };
 233
 234 /* PCnet32 access functions */
 235 struct pcnet32_access {
 236         u16     (*read_csr) (unsigned long, int);
 237         void    (*write_csr) (unsigned long, int, u16);
 238         u16     (*read_bcr) (unsigned long, int);
 239         void    (*write_bcr) (unsigned long, int, u16);
 240         u16     (*read_rap) (unsigned long);
 241         void    (*write_rap) (unsigned long, u16);
 242         void    (*reset) (unsigned long);
 243 };
 244
 245 /*
 246  * The first field of pcnet32_private is read by the ethernet device
 247  * so the structure should be allocated using pci_alloc_consistent().
 248  */
 249 struct pcnet32_private {
 250         struct pcnet32_init_block init_block;
 251         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 252         struct pcnet32_rx_head  *rx_ring;
 253         struct pcnet32_tx_head  *tx_ring;
 254         dma_addr_t              dma_addr;/* DMA address of beginning of this
 255                                    object, returned by pci_alloc_consistent */
 256         struct pci_dev          *pci_dev;
 257         const char              *name;
 258         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 259         struct sk_buff          **tx_skbuff;
 260         struct sk_buff          **rx_skbuff;
 261         dma_addr_t              *tx_dma_addr;
 262         dma_addr_t              *rx_dma_addr;
 263         struct pcnet32_access   a;
 264         spinlock_t              lock;           /* Guard lock */
 265         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 266         unsigned int            rx_ring_size;   /* current rx ring size */
 267         unsigned int            tx_ring_size;   /* current tx ring size */
 268         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 269         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 270         unsigned short          rx_len_bits;
 271         unsigned short          tx_len_bits;
 272         dma_addr_t              rx_ring_dma_addr;
 273         dma_addr_t              tx_ring_dma_addr;
 274         unsigned int            dirty_rx,       /* ring entries to be freed. */
 275                                 dirty_tx;
 276
 277         struct net_device_stats stats;
 278         char                    tx_full;
 279         char                    phycount;       /* number of phys found */
 280         int                     options;
 281         unsigned int            shared_irq:1,   /* shared irq possible */
 282                                 dxsuflo:1,   /* disable transmit stop on uflo */
 283                                 mii:1;          /* mii port available */
 284         struct net_device       *next;
 285         struct mii_if_info      mii_if;
 286         struct timer_list       watchdog_timer;
 287         struct timer_list       blink_timer;
 288         u32                     msg_enable;     /* debug message level */
 289
 290         /* each bit indicates an available PHY */
 291         u32                     phymask;
 292 };
 293
 294 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 295 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 296 static int pcnet32_open(struct net_device *);
 297 static int pcnet32_init_ring(struct net_device *);
 298 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
 299 static int pcnet32_rx(struct net_device *);
 300 static void pcnet32_tx_timeout(struct net_device *dev);
 301 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
 302 static int pcnet32_close(struct net_device *);
 303 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 304 static void pcnet32_load_multicast(struct net_device *dev);
 305 static void pcnet32_set_multicast_list(struct net_device *);
 306 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 307 static void pcnet32_watchdog(struct net_device *);
 308 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 309 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 310                        int val);
 311 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 312 static void pcnet32_ethtool_test(struct net_device *dev,
 313                                  struct ethtool_test *eth_test, u64 * data);
 314 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 315 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 316 static void pcnet32_led_blink_callback(struct net_device *dev);
 317 static int pcnet32_get_regs_len(struct net_device *dev);
 318 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 319                              void *ptr);
 320 static void pcnet32_purge_tx_ring(struct net_device *dev);
 321 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
 322 static void pcnet32_free_ring(struct net_device *dev);
 323 static void pcnet32_check_media(struct net_device *dev, int verbose);
 324
 325 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 326 {
 327         outw(index, addr + PCNET32_WIO_RAP);
 328         return inw(addr + PCNET32_WIO_RDP);
 329 }
 330
 331 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 332 {
 333         outw(index, addr + PCNET32_WIO_RAP);
 334         outw(val, addr + PCNET32_WIO_RDP);
 335 }
 336
 337 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 338 {
 339         outw(index, addr + PCNET32_WIO_RAP);
 340         return inw(addr + PCNET32_WIO_BDP);
 341 }
 342
 343 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 344 {
 345         outw(index, addr + PCNET32_WIO_RAP);
 346         outw(val, addr + PCNET32_WIO_BDP);
 347 }
 348
 349 static u16 pcnet32_wio_read_rap(unsigned long addr)
 350 {
 351         return inw(addr + PCNET32_WIO_RAP);
 352 }
 353
 354 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 355 {
 356         outw(val, addr + PCNET32_WIO_RAP);
 357 }
 358
 359 static void pcnet32_wio_reset(unsigned long addr)
 360 {
 361         inw(addr + PCNET32_WIO_RESET);
 362 }
 363
 364 static int pcnet32_wio_check(unsigned long addr)
 365 {
 366         outw(88, addr + PCNET32_WIO_RAP);
 367         return (inw(addr + PCNET32_WIO_RAP) == 88);
 368 }
 369
 370 static struct pcnet32_access pcnet32_wio = {
 371         .read_csr = pcnet32_wio_read_csr,
 372         .write_csr = pcnet32_wio_write_csr,
 373         .read_bcr = pcnet32_wio_read_bcr,
 374         .write_bcr = pcnet32_wio_write_bcr,
 375         .read_rap = pcnet32_wio_read_rap,
 376         .write_rap = pcnet32_wio_write_rap,
 377         .reset = pcnet32_wio_reset
 378 };
 379
 380 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 381 {
 382         outl(index, addr + PCNET32_DWIO_RAP);
 383         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 384 }
 385
 386 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 387 {
 388         outl(index, addr + PCNET32_DWIO_RAP);
 389         outl(val, addr + PCNET32_DWIO_RDP);
 390 }
 391
 392 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 393 {
 394         outl(index, addr + PCNET32_DWIO_RAP);
 395         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 396 }
 397
 398 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 399 {
 400         outl(index, addr + PCNET32_DWIO_RAP);
 401         outl(val, addr + PCNET32_DWIO_BDP);
 402 }
 403
 404 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 405 {
 406         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 407 }
 408
 409 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 410 {
 411         outl(val, addr + PCNET32_DWIO_RAP);
 412 }
 413
 414 static void pcnet32_dwio_reset(unsigned long addr)
 415 {
 416         inl(addr + PCNET32_DWIO_RESET);
 417 }
 418
 419 static int pcnet32_dwio_check(unsigned long addr)
 420 {
 421         outl(88, addr + PCNET32_DWIO_RAP);
 422         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 423 }
 424
 425 static struct pcnet32_access pcnet32_dwio = {
 426         .read_csr = pcnet32_dwio_read_csr,
 427         .write_csr = pcnet32_dwio_write_csr,
 428         .read_bcr = pcnet32_dwio_read_bcr,
 429         .write_bcr = pcnet32_dwio_write_bcr,
 430         .read_rap = pcnet32_dwio_read_rap,
 431         .write_rap = pcnet32_dwio_write_rap,
 432         .reset = pcnet32_dwio_reset
 433 };
 434
 435 static void pcnet32_netif_stop(struct net_device *dev)
 436 {
 437         dev->trans_start = jiffies;
 438         netif_poll_disable(dev);
 439         netif_tx_disable(dev);
 440 }
 441
 442 static void pcnet32_netif_start(struct net_device *dev)
 443 {
 444         netif_wake_queue(dev);
 445         netif_poll_enable(dev);
 446 }
 447
 448 /*
 449  * Allocate space for the new sized tx ring.
 450  * Free old resources
 451  * Save new resources.
 452  * Any failure keeps old resources.
 453  * Must be called with lp->lock held.
 454  */
 455 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 456                                     struct pcnet32_private *lp,
 457                                     unsigned int size)
 458 {
 459         dma_addr_t new_ring_dma_addr;
 460         dma_addr_t *new_dma_addr_list;
 461         struct pcnet32_tx_head *new_tx_ring;
 462         struct sk_buff **new_skb_list;
 463
 464         pcnet32_purge_tx_ring(dev);
 465
 466         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 467                                            sizeof(struct pcnet32_tx_head) *
 468                                            (1 << size),
 469                                            &new_ring_dma_addr);
 470         if (new_tx_ring == NULL) {
 471                 if (netif_msg_drv(lp))
 472                         printk("\n" KERN_ERR
 473                                "%s: Consistent memory allocation failed.\n",
 474                                dev->name);
 475                 return;
 476         }
 477         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 478
 479         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 480                                 GFP_ATOMIC);
 481         if (!new_dma_addr_list) {
 482                 if (netif_msg_drv(lp))
 483                         printk("\n" KERN_ERR
 484                                "%s: Memory allocation failed.\n", dev->name);
 485                 goto free_new_tx_ring;
 486         }
 487
 488         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 489                                 GFP_ATOMIC);
 490         if (!new_skb_list) {
 491                 if (netif_msg_drv(lp))
 492                         printk("\n" KERN_ERR
 493                                "%s: Memory allocation failed.\n", dev->name);
 494                 goto free_new_lists;
 495         }
 496
 497         kfree(lp->tx_skbuff);
 498         kfree(lp->tx_dma_addr);
 499         pci_free_consistent(lp->pci_dev,
 500                             sizeof(struct pcnet32_tx_head) *
 501                             lp->tx_ring_size, lp->tx_ring,
 502                             lp->tx_ring_dma_addr);
 503
 504         lp->tx_ring_size = (1 << size);
 505         lp->tx_mod_mask = lp->tx_ring_size - 1;
 506         lp->tx_len_bits = (size << 12);
 507         lp->tx_ring = new_tx_ring;
 508         lp->tx_ring_dma_addr = new_ring_dma_addr;
 509         lp->tx_dma_addr = new_dma_addr_list;
 510         lp->tx_skbuff = new_skb_list;
 511         return;
 512
 513     free_new_lists:
 514         kfree(new_dma_addr_list);
 515     free_new_tx_ring:
 516         pci_free_consistent(lp->pci_dev,
 517                             sizeof(struct pcnet32_tx_head) *
 518                             (1 << size),
 519                             new_tx_ring,
 520                             new_ring_dma_addr);
 521         return;
 522 }
 523
 524 /*
 525  * Allocate space for the new sized rx ring.
 526  * Re-use old receive buffers.
 527  *   alloc extra buffers
 528  *   free unneeded buffers
 529  *   free unneeded buffers
 530  * Save new resources.
 531  * Any failure keeps old resources.
 532  * Must be called with lp->lock held.
 533  */
 534 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 535                                     struct pcnet32_private *lp,
 536                                     unsigned int size)
 537 {
 538         dma_addr_t new_ring_dma_addr;
 539         dma_addr_t *new_dma_addr_list;
 540         struct pcnet32_rx_head *new_rx_ring;
 541         struct sk_buff **new_skb_list;
 542         int new, overlap;
 543
 544         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 545                                            sizeof(struct pcnet32_rx_head) *
 546                                            (1 << size),
 547                                            &new_ring_dma_addr);
 548         if (new_rx_ring == NULL) {
 549                 if (netif_msg_drv(lp))
 550                         printk("\n" KERN_ERR
 551                                "%s: Consistent memory allocation failed.\n",
 552                                dev->name);
 553                 return;
 554         }
 555         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 556
 557         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 558                                 GFP_ATOMIC);
 559         if (!new_dma_addr_list) {
 560                 if (netif_msg_drv(lp))
 561                         printk("\n" KERN_ERR
 562                                "%s: Memory allocation failed.\n", dev->name);
 563                 goto free_new_rx_ring;
 564         }
 565
 566         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 567                                 GFP_ATOMIC);
 568         if (!new_skb_list) {
 569                 if (netif_msg_drv(lp))
 570                         printk("\n" KERN_ERR
 571                                "%s: Memory allocation failed.\n", dev->name);
 572                 goto free_new_lists;
 573         }
 574
 575         /* first copy the current receive buffers */
 576         overlap = min(size, lp->rx_ring_size);
 577         for (new = 0; new < overlap; new++) {
 578                 new_rx_ring[new] = lp->rx_ring[new];
 579                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 580                 new_skb_list[new] = lp->rx_skbuff[new];
 581         }
 582         /* now allocate any new buffers needed */
 583         for (; new < size; new++ ) {
 584                 struct sk_buff *rx_skbuff;
 585                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
 586                 if (!(rx_skbuff = new_skb_list[new])) {
 587                         /* keep the original lists and buffers */
 588                         if (netif_msg_drv(lp))
 589                                 printk(KERN_ERR
 590                                        "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
 591                                        dev->name);
 592                         goto free_all_new;
 593                 }
 594                 skb_reserve(rx_skbuff, 2);
 595
 596                 new_dma_addr_list[new] =
 597                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 598                                            PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 599                 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
 600                 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
 601                 new_rx_ring[new].status = le16_to_cpu(0x8000);
 602         }
 603         /* and free any unneeded buffers */
 604         for (; new < lp->rx_ring_size; new++) {
 605                 if (lp->rx_skbuff[new]) {
 606                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 607                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 608                         dev_kfree_skb(lp->rx_skbuff[new]);
 609                 }
 610         }
 611
 612         kfree(lp->rx_skbuff);
 613         kfree(lp->rx_dma_addr);
 614         pci_free_consistent(lp->pci_dev,
 615                             sizeof(struct pcnet32_rx_head) *
 616                             lp->rx_ring_size, lp->rx_ring,
 617                             lp->rx_ring_dma_addr);
 618
 619         lp->rx_ring_size = (1 << size);
 620         lp->rx_mod_mask = lp->rx_ring_size - 1;
 621         lp->rx_len_bits = (size << 4);
 622         lp->rx_ring = new_rx_ring;
 623         lp->rx_ring_dma_addr = new_ring_dma_addr;
 624         lp->rx_dma_addr = new_dma_addr_list;
 625         lp->rx_skbuff = new_skb_list;
 626         return;
 627
 628     free_all_new:
 629         for (; --new >= lp->rx_ring_size; ) {
 630                 if (new_skb_list[new]) {
 631                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 632                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 633                         dev_kfree_skb(new_skb_list[new]);
 634                 }
 635         }
 636         kfree(new_skb_list);
 637     free_new_lists:
 638         kfree(new_dma_addr_list);
 639     free_new_rx_ring:
 640         pci_free_consistent(lp->pci_dev,
 641                             sizeof(struct pcnet32_rx_head) *
 642                             (1 << size),
 643                             new_rx_ring,
 644                             new_ring_dma_addr);
 645         return;
 646 }
 647
 648 static void pcnet32_purge_rx_ring(struct net_device *dev)
 649 {
 650         struct pcnet32_private *lp = dev->priv;
 651         int i;
 652
 653         /* free all allocated skbuffs */
 654         for (i = 0; i < lp->rx_ring_size; i++) {
 655                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 656                 wmb();          /* Make sure adapter sees owner change */
 657                 if (lp->rx_skbuff[i]) {
 658                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 659                                          PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
 660                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 661                 }
 662                 lp->rx_skbuff[i] = NULL;
 663                 lp->rx_dma_addr[i] = 0;
 664         }
 665 }
 666
 667 #ifdef CONFIG_NET_POLL_CONTROLLER
 668 static void pcnet32_poll_controller(struct net_device *dev)
 669 {
 670         disable_irq(dev->irq);
 671         pcnet32_interrupt(0, dev, NULL);
 672         enable_irq(dev->irq);
 673 }
 674 #endif
 675
 676 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 677 {
 678         struct pcnet32_private *lp = dev->priv;
 679         unsigned long flags;
 680         int r = -EOPNOTSUPP;
 681
 682         if (lp->mii) {
 683                 spin_lock_irqsave(&lp->lock, flags);
 684                 mii_ethtool_gset(&lp->mii_if, cmd);
 685                 spin_unlock_irqrestore(&lp->lock, flags);
 686                 r = 0;
 687         }
 688         return r;
 689 }
 690
 691 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 692 {
 693         struct pcnet32_private *lp = dev->priv;
 694         unsigned long flags;
 695         int r = -EOPNOTSUPP;
 696
 697         if (lp->mii) {
 698                 spin_lock_irqsave(&lp->lock, flags);
 699                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 700                 spin_unlock_irqrestore(&lp->lock, flags);
 701         }
 702         return r;
 703 }
 704
 705 static void pcnet32_get_drvinfo(struct net_device *dev,
 706                                 struct ethtool_drvinfo *info)
 707 {
 708         struct pcnet32_private *lp = dev->priv;
 709
 710         strcpy(info->driver, DRV_NAME);
 711         strcpy(info->version, DRV_VERSION);
 712         if (lp->pci_dev)
 713                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 714         else
 715                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 716 }
 717
 718 static u32 pcnet32_get_link(struct net_device *dev)
 719 {
 720         struct pcnet32_private *lp = dev->priv;
 721         unsigned long flags;
 722         int r;
 723
 724         spin_lock_irqsave(&lp->lock, flags);
 725         if (lp->mii) {
 726                 r = mii_link_ok(&lp->mii_if);
 727         } else {
 728                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 729                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 730         }
 731         spin_unlock_irqrestore(&lp->lock, flags);
 732
 733         return r;
 734 }
 735
 736 static u32 pcnet32_get_msglevel(struct net_device *dev)
 737 {
 738         struct pcnet32_private *lp = dev->priv;
 739         return lp->msg_enable;
 740 }
 741
 742 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 743 {
 744         struct pcnet32_private *lp = dev->priv;
 745         lp->msg_enable = value;
 746 }
 747
 748 static int pcnet32_nway_reset(struct net_device *dev)
 749 {
 750         struct pcnet32_private *lp = dev->priv;
 751         unsigned long flags;
 752         int r = -EOPNOTSUPP;
 753
 754         if (lp->mii) {
 755                 spin_lock_irqsave(&lp->lock, flags);
 756                 r = mii_nway_restart(&lp->mii_if);
 757                 spin_unlock_irqrestore(&lp->lock, flags);
 758         }
 759         return r;
 760 }
 761
 762 static void pcnet32_get_ringparam(struct net_device *dev,
 763                                   struct ethtool_ringparam *ering)
 764 {
 765         struct pcnet32_private *lp = dev->priv;
 766
 767         ering->tx_max_pending = TX_MAX_RING_SIZE;
 768         ering->tx_pending = lp->tx_ring_size;
 769         ering->rx_max_pending = RX_MAX_RING_SIZE;
 770         ering->rx_pending = lp->rx_ring_size;
 771 }
 772
 773 static int pcnet32_set_ringparam(struct net_device *dev,
 774                                  struct ethtool_ringparam *ering)
 775 {
 776         struct pcnet32_private *lp = dev->priv;
 777         unsigned long flags;
 778         unsigned int size;
 779         ulong ioaddr = dev->base_addr;
 780         int i;
 781
 782         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 783                 return -EINVAL;
 784
 785         if (netif_running(dev))
 786                 pcnet32_netif_stop(dev);
 787
 788         spin_lock_irqsave(&lp->lock, flags);
 789         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 790
 791         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 792
 793         /* set the minimum ring size to 4, to allow the loopback test to work
 794          * unchanged.
 795          */
 796         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 797                 if (size <= (1 << i))
 798                         break;
 799         }
 800         if ((1 << i) != lp->tx_ring_size)
 801                 pcnet32_realloc_tx_ring(dev, lp, i);
 802
 803         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 804         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 805                 if (size <= (1 << i))
 806                         break;
 807         }
 808         if ((1 << i) != lp->rx_ring_size)
 809                 pcnet32_realloc_rx_ring(dev, lp, i);
 810
 811         dev->weight = lp->rx_ring_size / 2;
 812
 813         if (netif_running(dev)) {
 814                 pcnet32_netif_start(dev);
 815                 pcnet32_restart(dev, CSR0_NORMAL);
 816         }
 817
 818         spin_unlock_irqrestore(&lp->lock, flags);
 819
 820         if (netif_msg_drv(lp))
 821                 printk(KERN_INFO
 822                        "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
 823                        lp->rx_ring_size, lp->tx_ring_size);
 824
 825         return 0;
 826 }
 827
 828 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 829                                 u8 * data)
 830 {
 831         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 832 }
 833
 834 static int pcnet32_self_test_count(struct net_device *dev)
 835 {
 836         return PCNET32_TEST_LEN;
 837 }
 838
 839 static void pcnet32_ethtool_test(struct net_device *dev,
 840                                  struct ethtool_test *test, u64 * data)
 841 {
 842         struct pcnet32_private *lp = dev->priv;
 843         int rc;
 844
 845         if (test->flags == ETH_TEST_FL_OFFLINE) {
 846                 rc = pcnet32_loopback_test(dev, data);
 847                 if (rc) {
 848                         if (netif_msg_hw(lp))
 849                                 printk(KERN_DEBUG "%s: Loopback test failed.\n",
 850                                        dev->name);
 851                         test->flags |= ETH_TEST_FL_FAILED;
 852                 } else if (netif_msg_hw(lp))
 853                         printk(KERN_DEBUG "%s: Loopback test passed.\n",
 854                                dev->name);
 855         } else if (netif_msg_hw(lp))
 856                 printk(KERN_DEBUG
 857                        "%s: No tests to run (specify 'Offline' on ethtool).",
 858                        dev->name);
 859 }                               /* end pcnet32_ethtool_test */
 860
 861 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 862 {
 863         struct pcnet32_private *lp = dev->priv;
 864         struct pcnet32_access *a = &lp->a;      /* access to registers */
 865         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 866         struct sk_buff *skb;    /* sk buff */
 867         int x, i;               /* counters */
 868         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 869         u16 status = 0x8300;    /* TX ring status */
 870         u16 teststatus;         /* test of ring status */
 871         int rc;                 /* return code */
 872         int size;               /* size of packets */
 873         unsigned char *packet;  /* source packet data */
 874         static const int data_len = 60; /* length of source packets */
 875         unsigned long flags;
 876         unsigned long ticks;
 877
 878         rc = 1;                 /* default to fail */
 879
 880         if (netif_running(dev))
 881                 pcnet32_close(dev);
 882
 883         spin_lock_irqsave(&lp->lock, flags);
 884         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 885
 886         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 887
 888         /* Reset the PCNET32 */
 889         lp->a.reset(ioaddr);
 890         lp->a.write_csr(ioaddr, CSR4, 0x0915);
 891
 892         /* switch pcnet32 to 32bit mode */
 893         lp->a.write_bcr(ioaddr, 20, 2);
 894
 895         /* purge & init rings but don't actually restart */
 896         pcnet32_restart(dev, 0x0000);
 897
 898         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 899
 900         /* Initialize Transmit buffers. */
 901         size = data_len + 15;
 902         for (x = 0; x < numbuffs; x++) {
 903                 if (!(skb = dev_alloc_skb(size))) {
 904                         if (netif_msg_hw(lp))
 905                                 printk(KERN_DEBUG
 906                                        "%s: Cannot allocate skb at line: %d!\n",
 907                                        dev->name, __LINE__);
 908                         goto clean_up;
 909                 } else {
 910                         packet = skb->data;
 911                         skb_put(skb, size);     /* create space for data */
 912                         lp->tx_skbuff[x] = skb;
 913                         lp->tx_ring[x].length = le16_to_cpu(-skb->len);
 914                         lp->tx_ring[x].misc = 0;
 915
 916                         /* put DA and SA into the skb */
 917                         for (i = 0; i < 6; i++)
 918                                 *packet++ = dev->dev_addr[i];
 919                         for (i = 0; i < 6; i++)
 920                                 *packet++ = dev->dev_addr[i];
 921                         /* type */
 922                         *packet++ = 0x08;
 923                         *packet++ = 0x06;
 924                         /* packet number */
 925                         *packet++ = x;
 926                         /* fill packet with data */
 927                         for (i = 0; i < data_len; i++)
 928                                 *packet++ = i;
 929
 930                         lp->tx_dma_addr[x] =
 931                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 932                                            PCI_DMA_TODEVICE);
 933                         lp->tx_ring[x].base =
 934                             (u32) le32_to_cpu(lp->tx_dma_addr[x]);
 935                         wmb();  /* Make sure owner changes after all others are visible */
 936                         lp->tx_ring[x].status = le16_to_cpu(status);
 937                 }
 938         }
 939
 940         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 941         a->write_bcr(ioaddr, 32, x | 0x0002);
 942
 943         /* set int loopback in CSR15 */
 944         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 945         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 946
 947         teststatus = le16_to_cpu(0x8000);
 948         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 949
 950         /* Check status of descriptors */
 951         for (x = 0; x < numbuffs; x++) {
 952                 ticks = 0;
 953                 rmb();
 954                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 955                         spin_unlock_irqrestore(&lp->lock, flags);
 956                         msleep(1);
 957                         spin_lock_irqsave(&lp->lock, flags);
 958                         rmb();
 959                         ticks++;
 960                 }
 961                 if (ticks == 200) {
 962                         if (netif_msg_hw(lp))
 963                                 printk("%s: Desc %d failed to reset!\n",
 964                                        dev->name, x);
 965                         break;
 966                 }
 967         }
 968
 969         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 970         wmb();
 971         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 972                 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
 973
 974                 for (x = 0; x < numbuffs; x++) {
 975                         printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
 976                         skb = lp->rx_skbuff[x];
 977                         for (i = 0; i < size; i++) {
 978                                 printk("%02x ", *(skb->data + i));
 979                         }
 980                         printk("\n");
 981                 }
 982         }
 983
 984         x = 0;
 985         rc = 0;
 986         while (x < numbuffs && !rc) {
 987                 skb = lp->rx_skbuff[x];
 988                 packet = lp->tx_skbuff[x]->data;
 989                 for (i = 0; i < size; i++) {
 990                         if (*(skb->data + i) != packet[i]) {
 991                                 if (netif_msg_hw(lp))
 992                                         printk(KERN_DEBUG
 993                                                "%s: Error in compare! %2x - %02x %02x\n",
 994                                                dev->name, i, *(skb->data + i),
 995                                                packet[i]);
 996                                 rc = 1;
 997                                 break;
 998                         }
 999                 }
1000                 x++;
1001         }
1002
1003       clean_up:
1004         *data1 = rc;
1005         pcnet32_purge_tx_ring(dev);
1006
1007         x = a->read_csr(ioaddr, CSR15);
1008         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1009
1010         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1011         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1012
1013         if (netif_running(dev)) {
1014                 spin_unlock_irqrestore(&lp->lock, flags);
1015                 pcnet32_open(dev);
1016         } else {
1017                 pcnet32_purge_rx_ring(dev);
1018                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1019                 spin_unlock_irqrestore(&lp->lock, flags);
1020         }
1021
1022         return (rc);
1023 }                               /* end pcnet32_loopback_test  */
1024
1025 static void pcnet32_led_blink_callback(struct net_device *dev)
1026 {
1027         struct pcnet32_private *lp = dev->priv;
1028         struct pcnet32_access *a = &lp->a;
1029         ulong ioaddr = dev->base_addr;
1030         unsigned long flags;
1031         int i;
1032
1033         spin_lock_irqsave(&lp->lock, flags);
1034         for (i = 4; i < 8; i++) {
1035                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1036         }
1037         spin_unlock_irqrestore(&lp->lock, flags);
1038
1039         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1040 }
1041
1042 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1043 {
1044         struct pcnet32_private *lp = dev->priv;
1045         struct pcnet32_access *a = &lp->a;
1046         ulong ioaddr = dev->base_addr;
1047         unsigned long flags;
1048         int i, regs[4];
1049
1050         if (!lp->blink_timer.function) {
1051                 init_timer(&lp->blink_timer);
1052                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1053                 lp->blink_timer.data = (unsigned long)dev;
1054         }
1055
1056         /* Save the current value of the bcrs */
1057         spin_lock_irqsave(&lp->lock, flags);
1058         for (i = 4; i < 8; i++) {
1059                 regs[i - 4] = a->read_bcr(ioaddr, i);
1060         }
1061         spin_unlock_irqrestore(&lp->lock, flags);
1062
1063         mod_timer(&lp->blink_timer, jiffies);
1064         set_current_state(TASK_INTERRUPTIBLE);
1065
1066         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1067                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1068
1069         msleep_interruptible(data * 1000);
1070         del_timer_sync(&lp->blink_timer);
1071
1072         /* Restore the original value of the bcrs */
1073         spin_lock_irqsave(&lp->lock, flags);
1074         for (i = 4; i < 8; i++) {
1075                 a->write_bcr(ioaddr, i, regs[i - 4]);
1076         }
1077         spin_unlock_irqrestore(&lp->lock, flags);
1078
1079         return 0;
1080 }
1081
1082 /*
1083  * lp->lock must be held.
1084  */
1085 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1086                 int can_sleep)
1087 {
1088         int csr5;
1089         struct pcnet32_private *lp = dev->priv;
1090         struct pcnet32_access *a = &lp->a;
1091         ulong ioaddr = dev->base_addr;
1092         int ticks;
1093
1094         /* set SUSPEND (SPND) - CSR5 bit 0 */
1095         csr5 = a->read_csr(ioaddr, CSR5);
1096         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1097
1098         /* poll waiting for bit to be set */
1099         ticks = 0;
1100         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1101                 spin_unlock_irqrestore(&lp->lock, *flags);
1102                 if (can_sleep)
1103                         msleep(1);
1104                 else
1105                         mdelay(1);
1106                 spin_lock_irqsave(&lp->lock, *flags);
1107                 ticks++;
1108                 if (ticks > 200) {
1109                         if (netif_msg_hw(lp))
1110                                 printk(KERN_DEBUG
1111                                        "%s: Error getting into suspend!\n",
1112                                        dev->name);
1113                         return 0;
1114                 }
1115         }
1116         return 1;
1117 }
1118
1119 #define PCNET32_REGS_PER_PHY    32
1120 #define PCNET32_MAX_PHYS        32
1121 static int pcnet32_get_regs_len(struct net_device *dev)
1122 {
1123         struct pcnet32_private *lp = dev->priv;
1124         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1125
1126         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1127 }
1128
1129 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1130                              void *ptr)
1131 {
1132         int i, csr0;
1133         u16 *buff = ptr;
1134         struct pcnet32_private *lp = dev->priv;
1135         struct pcnet32_access *a = &lp->a;
1136         ulong ioaddr = dev->base_addr;
1137         unsigned long flags;
1138
1139         spin_lock_irqsave(&lp->lock, flags);
1140
1141         csr0 = a->read_csr(ioaddr, CSR0);
1142         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1143                 pcnet32_suspend(dev, &flags, 1);
1144
1145         /* read address PROM */
1146         for (i = 0; i < 16; i += 2)
1147                 *buff++ = inw(ioaddr + i);
1148
1149         /* read control and status registers */
1150         for (i = 0; i < 90; i++) {
1151                 *buff++ = a->read_csr(ioaddr, i);
1152         }
1153
1154         *buff++ = a->read_csr(ioaddr, 112);
1155         *buff++ = a->read_csr(ioaddr, 114);
1156
1157         /* read bus configuration registers */
1158         for (i = 0; i < 30; i++) {
1159                 *buff++ = a->read_bcr(ioaddr, i);
1160         }
1161         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1162         for (i = 31; i < 36; i++) {
1163                 *buff++ = a->read_bcr(ioaddr, i);
1164         }
1165
1166         /* read mii phy registers */
1167         if (lp->mii) {
1168                 int j;
1169                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1170                         if (lp->phymask & (1 << j)) {
1171                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1172                                         lp->a.write_bcr(ioaddr, 33,
1173                                                         (j << 5) | i);
1174                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1175                                 }
1176                         }
1177                 }
1178         }
1179
1180         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1181                 int csr5;
1182
1183                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1184                 csr5 = a->read_csr(ioaddr, CSR5);
1185                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1186         }
1187
1188         spin_unlock_irqrestore(&lp->lock, flags);
1189 }
1190
1191 static struct ethtool_ops pcnet32_ethtool_ops = {
1192         .get_settings           = pcnet32_get_settings,
1193         .set_settings           = pcnet32_set_settings,
1194         .get_drvinfo            = pcnet32_get_drvinfo,
1195         .get_msglevel           = pcnet32_get_msglevel,
1196         .set_msglevel           = pcnet32_set_msglevel,
1197         .nway_reset             = pcnet32_nway_reset,
1198         .get_link               = pcnet32_get_link,
1199         .get_ringparam          = pcnet32_get_ringparam,
1200         .set_ringparam          = pcnet32_set_ringparam,
1201         .get_tx_csum            = ethtool_op_get_tx_csum,
1202         .get_sg                 = ethtool_op_get_sg,
1203         .get_tso                = ethtool_op_get_tso,
1204         .get_strings            = pcnet32_get_strings,
1205         .self_test_count        = pcnet32_self_test_count,
1206         .self_test              = pcnet32_ethtool_test,
1207         .phys_id                = pcnet32_phys_id,
1208         .get_regs_len           = pcnet32_get_regs_len,
1209         .get_regs               = pcnet32_get_regs,
1210         .get_perm_addr          = ethtool_op_get_perm_addr,
1211 };
1212
1213 /* only probes for non-PCI devices, the rest are handled by
1214  * pci_register_driver via pcnet32_probe_pci */
1215
1216 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1217 {
1218         unsigned int *port, ioaddr;
1219
1220         /* search for PCnet32 VLB cards at known addresses */
1221         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1222                 if (request_region
1223                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1224                         /* check if there is really a pcnet chip on that ioaddr */
1225                         if ((inb(ioaddr + 14) == 0x57)
1226                             && (inb(ioaddr + 15) == 0x57)) {
1227                                 pcnet32_probe1(ioaddr, 0, NULL);
1228                         } else {
1229                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1230                         }
1231                 }
1232         }
1233 }
1234
1235 static int __devinit
1236 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1237 {
1238         unsigned long ioaddr;
1239         int err;
1240
1241         err = pci_enable_device(pdev);
1242         if (err < 0) {
1243                 if (pcnet32_debug & NETIF_MSG_PROBE)
1244                         printk(KERN_ERR PFX
1245                                "failed to enable device -- err=%d\n", err);
1246                 return err;
1247         }
1248         pci_set_master(pdev);
1249
1250         ioaddr = pci_resource_start(pdev, 0);
1251         if (!ioaddr) {
1252                 if (pcnet32_debug & NETIF_MSG_PROBE)
1253                         printk(KERN_ERR PFX
1254                                "card has no PCI IO resources, aborting\n");
1255                 return -ENODEV;
1256         }
1257
1258         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1259                 if (pcnet32_debug & NETIF_MSG_PROBE)
1260                         printk(KERN_ERR PFX
1261                                "architecture does not support 32bit PCI busmaster DMA\n");
1262                 return -ENODEV;
1263         }
1264         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1265             NULL) {
1266                 if (pcnet32_debug & NETIF_MSG_PROBE)
1267                         printk(KERN_ERR PFX
1268                                "io address range already allocated\n");
1269                 return -EBUSY;
1270         }
1271
1272         err = pcnet32_probe1(ioaddr, 1, pdev);
1273         if (err < 0) {
1274                 pci_disable_device(pdev);
1275         }
1276         return err;
1277 }
1278
1279 /* pcnet32_probe1
1280  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1281  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1282  */
1283 static int __devinit
1284 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1285 {
1286         struct pcnet32_private *lp;
1287         dma_addr_t lp_dma_addr;
1288         int i, media;
1289         int fdx, mii, fset, dxsuflo;
1290         int chip_version;
1291         char *chipname;
1292         struct net_device *dev;
1293         struct pcnet32_access *a = NULL;
1294         u8 promaddr[6];
1295         int ret = -ENODEV;
1296
1297         /* reset the chip */
1298         pcnet32_wio_reset(ioaddr);
1299
1300         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1301         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1302                 a = &pcnet32_wio;
1303         } else {
1304                 pcnet32_dwio_reset(ioaddr);
1305                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1306                     && pcnet32_dwio_check(ioaddr)) {
1307                         a = &pcnet32_dwio;
1308                 } else
1309                         goto err_release_region;
1310         }
1311
1312         chip_version =
1313             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1314         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1315                 printk(KERN_INFO "  PCnet chip version is %#x.\n",
1316                        chip_version);
1317         if ((chip_version & 0xfff) != 0x003) {
1318                 if (pcnet32_debug & NETIF_MSG_PROBE)
1319                         printk(KERN_INFO PFX "Unsupported chip version.\n");
1320                 goto err_release_region;
1321         }
1322
1323         /* initialize variables */
1324         fdx = mii = fset = dxsuflo = 0;
1325         chip_version = (chip_version >> 12) & 0xffff;
1326
1327         switch (chip_version) {
1328         case 0x2420:
1329                 chipname = "PCnet/PCI 79C970";  /* PCI */
1330                 break;
1331         case 0x2430:
1332                 if (shared)
1333                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1334                 else
1335                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1336                 break;
1337         case 0x2621:
1338                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1339                 fdx = 1;
1340                 break;
1341         case 0x2623:
1342                 chipname = "PCnet/FAST 79C971"; /* PCI */
1343                 fdx = 1;
1344                 mii = 1;
1345                 fset = 1;
1346                 break;
1347         case 0x2624:
1348                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1349                 fdx = 1;
1350                 mii = 1;
1351                 fset = 1;
1352                 break;
1353         case 0x2625:
1354                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1355                 fdx = 1;
1356                 mii = 1;
1357                 break;
1358         case 0x2626:
1359                 chipname = "PCnet/Home 79C978"; /* PCI */
1360                 fdx = 1;
1361                 /*
1362                  * This is based on specs published at www.amd.com.  This section
1363                  * assumes that a card with a 79C978 wants to go into standard
1364                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1365                  * and the module option homepna=1 can select this instead.
1366                  */
1367                 media = a->read_bcr(ioaddr, 49);
1368                 media &= ~3;    /* default to 10Mb ethernet */
1369                 if (cards_found < MAX_UNITS && homepna[cards_found])
1370                         media |= 1;     /* switch to home wiring mode */
1371                 if (pcnet32_debug & NETIF_MSG_PROBE)
1372                         printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1373                                (media & 1) ? "1" : "10");
1374                 a->write_bcr(ioaddr, 49, media);
1375                 break;
1376         case 0x2627:
1377                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1378                 fdx = 1;
1379                 mii = 1;
1380                 break;
1381         case 0x2628:
1382                 chipname = "PCnet/PRO 79C976";
1383                 fdx = 1;
1384                 mii = 1;
1385                 break;
1386         default:
1387                 if (pcnet32_debug & NETIF_MSG_PROBE)
1388                         printk(KERN_INFO PFX
1389                                "PCnet version %#x, no PCnet32 chip.\n",
1390                                chip_version);
1391                 goto err_release_region;
1392         }
1393
1394         /*
1395          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1396          *  starting until the packet is loaded. Strike one for reliability, lose
1397          *  one for latency - although on PCI this isnt a big loss. Older chips
1398          *  have FIFO's smaller than a packet, so you can't do this.
1399          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1400          */
1401
1402         if (fset) {
1403                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1404                 a->write_csr(ioaddr, 80,
1405                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1406                 dxsuflo = 1;
1407         }
1408
1409         dev = alloc_etherdev(0);
1410         if (!dev) {
1411                 if (pcnet32_debug & NETIF_MSG_PROBE)
1412                         printk(KERN_ERR PFX "Memory allocation failed.\n");
1413                 ret = -ENOMEM;
1414                 goto err_release_region;
1415         }
1416         SET_NETDEV_DEV(dev, &pdev->dev);
1417
1418         if (pcnet32_debug & NETIF_MSG_PROBE)
1419                 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1420
1421         /* In most chips, after a chip reset, the ethernet address is read from the
1422          * station address PROM at the base address and programmed into the
1423          * "Physical Address Registers" CSR12-14.
1424          * As a precautionary measure, we read the PROM values and complain if
1425          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1426          * is valid, then the PROM addr is used.
1427          */
1428         for (i = 0; i < 3; i++) {
1429                 unsigned int val;
1430                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1431                 /* There may be endianness issues here. */
1432                 dev->dev_addr[2 * i] = val & 0x0ff;
1433                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1434         }
1435
1436         /* read PROM address and compare with CSR address */
1437         for (i = 0; i < 6; i++)
1438                 promaddr[i] = inb(ioaddr + i);
1439
1440         if (memcmp(promaddr, dev->dev_addr, 6)
1441             || !is_valid_ether_addr(dev->dev_addr)) {
1442                 if (is_valid_ether_addr(promaddr)) {
1443                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1444                                 printk(" warning: CSR address invalid,\n");
1445                                 printk(KERN_INFO
1446                                        "    using instead PROM address of");
1447                         }
1448                         memcpy(dev->dev_addr, promaddr, 6);
1449                 }
1450         }
1451         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1452
1453         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1454         if (!is_valid_ether_addr(dev->perm_addr))
1455                 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1456
1457         if (pcnet32_debug & NETIF_MSG_PROBE) {
1458                 for (i = 0; i < 6; i++)
1459                         printk(" %2.2x", dev->dev_addr[i]);
1460
1461                 /* Version 0x2623 and 0x2624 */
1462                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1463                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1464                         printk("\n" KERN_INFO "    tx_start_pt(0x%04x):", i);
1465                         switch (i >> 10) {
1466                         case 0:
1467                                 printk("  20 bytes,");
1468                                 break;
1469                         case 1:
1470                                 printk("  64 bytes,");
1471                                 break;
1472                         case 2:
1473                                 printk(" 128 bytes,");
1474                                 break;
1475                         case 3:
1476                                 printk("~220 bytes,");
1477                                 break;
1478                         }
1479                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1480                         printk(" BCR18(%x):", i & 0xffff);
1481                         if (i & (1 << 5))
1482                                 printk("BurstWrEn ");
1483                         if (i & (1 << 6))
1484                                 printk("BurstRdEn ");
1485                         if (i & (1 << 7))
1486                                 printk("DWordIO ");
1487                         if (i & (1 << 11))
1488                                 printk("NoUFlow ");
1489                         i = a->read_bcr(ioaddr, 25);
1490                         printk("\n" KERN_INFO "    SRAMSIZE=0x%04x,", i << 8);
1491                         i = a->read_bcr(ioaddr, 26);
1492                         printk(" SRAM_BND=0x%04x,", i << 8);
1493                         i = a->read_bcr(ioaddr, 27);
1494                         if (i & (1 << 14))
1495                                 printk("LowLatRx");
1496                 }
1497         }
1498
1499         dev->base_addr = ioaddr;
1500         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1501         if ((lp =
1502              pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1503                 if (pcnet32_debug & NETIF_MSG_PROBE)
1504                         printk(KERN_ERR PFX
1505                                "Consistent memory allocation failed.\n");
1506                 ret = -ENOMEM;
1507                 goto err_free_netdev;
1508         }
1509
1510         memset(lp, 0, sizeof(*lp));
1511         lp->dma_addr = lp_dma_addr;
1512         lp->pci_dev = pdev;
1513
1514         spin_lock_init(&lp->lock);
1515
1516         SET_MODULE_OWNER(dev);
1517         SET_NETDEV_DEV(dev, &pdev->dev);
1518         dev->priv = lp;
1519         lp->name = chipname;
1520         lp->shared_irq = shared;
1521         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1522         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1523         lp->tx_mod_mask = lp->tx_ring_size - 1;
1524         lp->rx_mod_mask = lp->rx_ring_size - 1;
1525         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1526         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1527         lp->mii_if.full_duplex = fdx;
1528         lp->mii_if.phy_id_mask = 0x1f;
1529         lp->mii_if.reg_num_mask = 0x1f;
1530         lp->dxsuflo = dxsuflo;
1531         lp->mii = mii;
1532         lp->msg_enable = pcnet32_debug;
1533         if ((cards_found >= MAX_UNITS)
1534             || (options[cards_found] > sizeof(options_mapping)))
1535                 lp->options = PCNET32_PORT_ASEL;
1536         else
1537                 lp->options = options_mapping[options[cards_found]];
1538         lp->mii_if.dev = dev;
1539         lp->mii_if.mdio_read = mdio_read;
1540         lp->mii_if.mdio_write = mdio_write;
1541
1542         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1543             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1544                 lp->options |= PCNET32_PORT_FD;
1545
1546         if (!a) {
1547                 if (pcnet32_debug & NETIF_MSG_PROBE)
1548                         printk(KERN_ERR PFX "No access methods\n");
1549                 ret = -ENODEV;
1550                 goto err_free_consistent;
1551         }
1552         lp->a = *a;
1553
1554         /* prior to register_netdev, dev->name is not yet correct */
1555         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1556                 ret = -ENOMEM;
1557                 goto err_free_ring;
1558         }
1559         /* detect special T1/E1 WAN card by checking for MAC address */
1560         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1561             && dev->dev_addr[2] == 0x75)
1562                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1563
1564         lp->init_block.mode = le16_to_cpu(0x0003);      /* Disable Rx and Tx. */
1565         lp->init_block.tlen_rlen =
1566             le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1567         for (i = 0; i < 6; i++)
1568                 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1569         lp->init_block.filter[0] = 0x00000000;
1570         lp->init_block.filter[1] = 0x00000000;
1571         lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1572         lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1573
1574         /* switch pcnet32 to 32bit mode */
1575         a->write_bcr(ioaddr, 20, 2);
1576
1577         a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1578                                                          init_block)) & 0xffff);
1579         a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1580                                                          init_block)) >> 16);
1581
1582         if (pdev) {             /* use the IRQ provided by PCI */
1583                 dev->irq = pdev->irq;
1584                 if (pcnet32_debug & NETIF_MSG_PROBE)
1585                         printk(" assigned IRQ %d.\n", dev->irq);
1586         } else {
1587                 unsigned long irq_mask = probe_irq_on();
1588
1589                 /*
1590                  * To auto-IRQ we enable the initialization-done and DMA error
1591                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1592                  * boards will work.
1593                  */
1594                 /* Trigger an initialization just for the interrupt. */
1595                 a->write_csr(ioaddr, 0, 0x41);
1596                 mdelay(1);
1597
1598                 dev->irq = probe_irq_off(irq_mask);
1599                 if (!dev->irq) {
1600                         if (pcnet32_debug & NETIF_MSG_PROBE)
1601                                 printk(", failed to detect IRQ line.\n");
1602                         ret = -ENODEV;
1603                         goto err_free_ring;
1604                 }
1605                 if (pcnet32_debug & NETIF_MSG_PROBE)
1606                         printk(", probed IRQ %d.\n", dev->irq);
1607         }
1608
1609         /* Set the mii phy_id so that we can query the link state */
1610         if (lp->mii) {
1611                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1612
1613                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1614                 /* scan for PHYs */
1615                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1616                         unsigned short id1, id2;
1617
1618                         id1 = mdio_read(dev, i, MII_PHYSID1);
1619                         if (id1 == 0xffff)
1620                                 continue;
1621                         id2 = mdio_read(dev, i, MII_PHYSID2);
1622                         if (id2 == 0xffff)
1623                                 continue;
1624                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1625                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1626                         lp->phycount++;
1627                         lp->phymask |= (1 << i);
1628                         lp->mii_if.phy_id = i;
1629                         if (pcnet32_debug & NETIF_MSG_PROBE)
1630                                 printk(KERN_INFO PFX
1631                                        "Found PHY %04x:%04x at address %d.\n",
1632                                        id1, id2, i);
1633                 }
1634                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1635                 if (lp->phycount > 1) {
1636                         lp->options |= PCNET32_PORT_MII;
1637                 }
1638         }
1639
1640         init_timer(&lp->watchdog_timer);
1641         lp->watchdog_timer.data = (unsigned long)dev;
1642         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1643
1644         /* The PCNET32-specific entries in the device structure. */
1645         dev->open = &pcnet32_open;
1646         dev->hard_start_xmit = &pcnet32_start_xmit;
1647         dev->stop = &pcnet32_close;
1648         dev->get_stats = &pcnet32_get_stats;
1649         dev->set_multicast_list = &pcnet32_set_multicast_list;
1650         dev->do_ioctl = &pcnet32_ioctl;
1651         dev->ethtool_ops = &pcnet32_ethtool_ops;
1652         dev->tx_timeout = pcnet32_tx_timeout;
1653         dev->watchdog_timeo = (5 * HZ);
1654
1655 #ifdef CONFIG_NET_POLL_CONTROLLER
1656         dev->poll_controller = pcnet32_poll_controller;
1657 #endif
1658
1659         /* Fill in the generic fields of the device structure. */
1660         if (register_netdev(dev))
1661                 goto err_free_ring;
1662
1663         if (pdev) {
1664                 pci_set_drvdata(pdev, dev);
1665         } else {
1666                 lp->next = pcnet32_dev;
1667                 pcnet32_dev = dev;
1668         }
1669
1670         if (pcnet32_debug & NETIF_MSG_PROBE)
1671                 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1672         cards_found++;
1673
1674         /* enable LED writes */
1675         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1676
1677         return 0;
1678
1679       err_free_ring:
1680         pcnet32_free_ring(dev);
1681       err_free_consistent:
1682         pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1683       err_free_netdev:
1684         free_netdev(dev);
1685       err_release_region:
1686         release_region(ioaddr, PCNET32_TOTAL_SIZE);
1687         return ret;
1688 }
1689
1690 /* if any allocation fails, caller must also call pcnet32_free_ring */
1691 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1692 {
1693         struct pcnet32_private *lp = dev->priv;
1694
1695         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1696                                            sizeof(struct pcnet32_tx_head) *
1697                                            lp->tx_ring_size,
1698                                            &lp->tx_ring_dma_addr);
1699         if (lp->tx_ring == NULL) {
1700                 if (netif_msg_drv(lp))
1701                         printk("\n" KERN_ERR PFX
1702                                "%s: Consistent memory allocation failed.\n",
1703                                name);
1704                 return -ENOMEM;
1705         }
1706
1707         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1708                                            sizeof(struct pcnet32_rx_head) *
1709                                            lp->rx_ring_size,
1710                                            &lp->rx_ring_dma_addr);
1711         if (lp->rx_ring == NULL) {
1712                 if (netif_msg_drv(lp))
1713                         printk("\n" KERN_ERR PFX
1714                                "%s: Consistent memory allocation failed.\n",
1715                                name);
1716                 return -ENOMEM;
1717         }
1718
1719         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1720                                   GFP_ATOMIC);
1721         if (!lp->tx_dma_addr) {
1722                 if (netif_msg_drv(lp))
1723                         printk("\n" KERN_ERR PFX
1724                                "%s: Memory allocation failed.\n", name);
1725                 return -ENOMEM;
1726         }
1727
1728         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1729                                   GFP_ATOMIC);
1730         if (!lp->rx_dma_addr) {
1731                 if (netif_msg_drv(lp))
1732                         printk("\n" KERN_ERR PFX
1733                                "%s: Memory allocation failed.\n", name);
1734                 return -ENOMEM;
1735         }
1736
1737         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1738                                 GFP_ATOMIC);
1739         if (!lp->tx_skbuff) {
1740                 if (netif_msg_drv(lp))
1741                         printk("\n" KERN_ERR PFX
1742                                "%s: Memory allocation failed.\n", name);
1743                 return -ENOMEM;
1744         }
1745
1746         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1747                                 GFP_ATOMIC);
1748         if (!lp->rx_skbuff) {
1749                 if (netif_msg_drv(lp))
1750                         printk("\n" KERN_ERR PFX
1751                                "%s: Memory allocation failed.\n", name);
1752                 return -ENOMEM;
1753         }
1754
1755         return 0;
1756 }
1757
1758 static void pcnet32_free_ring(struct net_device *dev)
1759 {
1760         struct pcnet32_private *lp = dev->priv;
1761
1762         kfree(lp->tx_skbuff);
1763         lp->tx_skbuff = NULL;
1764
1765         kfree(lp->rx_skbuff);
1766         lp->rx_skbuff = NULL;
1767
1768         kfree(lp->tx_dma_addr);
1769         lp->tx_dma_addr = NULL;
1770
1771         kfree(lp->rx_dma_addr);
1772         lp->rx_dma_addr = NULL;
1773
1774         if (lp->tx_ring) {
1775                 pci_free_consistent(lp->pci_dev,
1776                                     sizeof(struct pcnet32_tx_head) *
1777                                     lp->tx_ring_size, lp->tx_ring,
1778                                     lp->tx_ring_dma_addr);
1779                 lp->tx_ring = NULL;
1780         }
1781
1782         if (lp->rx_ring) {
1783                 pci_free_consistent(lp->pci_dev,
1784                                     sizeof(struct pcnet32_rx_head) *
1785                                     lp->rx_ring_size, lp->rx_ring,
1786                                     lp->rx_ring_dma_addr);
1787                 lp->rx_ring = NULL;
1788         }
1789 }
1790
1791 static int pcnet32_open(struct net_device *dev)
1792 {
1793         struct pcnet32_private *lp = dev->priv;
1794         unsigned long ioaddr = dev->base_addr;
1795         u16 val;
1796         int i;
1797         int rc;
1798         unsigned long flags;
1799
1800         if (request_irq(dev->irq, &pcnet32_interrupt,
1801                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
1802                         (void *)dev)) {
1803                 return -EAGAIN;
1804         }
1805
1806         spin_lock_irqsave(&lp->lock, flags);
1807         /* Check for a valid station address */
1808         if (!is_valid_ether_addr(dev->dev_addr)) {
1809                 rc = -EINVAL;
1810                 goto err_free_irq;
1811         }
1812
1813         /* Reset the PCNET32 */
1814         lp->a.reset(ioaddr);
1815
1816         /* switch pcnet32 to 32bit mode */
1817         lp->a.write_bcr(ioaddr, 20, 2);
1818
1819         if (netif_msg_ifup(lp))
1820                 printk(KERN_DEBUG
1821                        "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1822                        dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
1823                        (u32) (lp->rx_ring_dma_addr),
1824                        (u32) (lp->dma_addr +
1825                               offsetof(struct pcnet32_private, init_block)));
1826
1827         /* set/reset autoselect bit */
1828         val = lp->a.read_bcr(ioaddr, 2) & ~2;
1829         if (lp->options & PCNET32_PORT_ASEL)
1830                 val |= 2;
1831         lp->a.write_bcr(ioaddr, 2, val);
1832
1833         /* handle full duplex setting */
1834         if (lp->mii_if.full_duplex) {
1835                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
1836                 if (lp->options & PCNET32_PORT_FD) {
1837                         val |= 1;
1838                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1839                                 val |= 2;
1840                 } else if (lp->options & PCNET32_PORT_ASEL) {
1841                         /* workaround of xSeries250, turn on for 79C975 only */
1842                         i = ((lp->a.read_csr(ioaddr, 88) |
1843                               (lp->a.
1844                                read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff;
1845                         if (i == 0x2627)
1846                                 val |= 3;
1847                 }
1848                 lp->a.write_bcr(ioaddr, 9, val);
1849         }
1850
1851         /* set/reset GPSI bit in test register */
1852         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
1853         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1854                 val |= 0x10;
1855         lp->a.write_csr(ioaddr, 124, val);
1856
1857         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1858         if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
1859             (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1860              lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
1861                 if (lp->options & PCNET32_PORT_ASEL) {
1862                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1863                         if (netif_msg_link(lp))
1864                                 printk(KERN_DEBUG
1865                                        "%s: Setting 100Mb-Full Duplex.\n",
1866                                        dev->name);
1867                 }
1868         }
1869         if (lp->phycount < 2) {
1870                 /*
1871                  * 24 Jun 2004 according AMD, in order to change the PHY,
1872                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
1873                  * duplex, and/or enable auto negotiation, and clear DANAS
1874                  */
1875                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1876                         lp->a.write_bcr(ioaddr, 32,
1877                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
1878                         /* disable Auto Negotiation, set 10Mpbs, HD */
1879                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1880                         if (lp->options & PCNET32_PORT_FD)
1881                                 val |= 0x10;
1882                         if (lp->options & PCNET32_PORT_100)
1883                                 val |= 0x08;
1884                         lp->a.write_bcr(ioaddr, 32, val);
1885                 } else {
1886                         if (lp->options & PCNET32_PORT_ASEL) {
1887                                 lp->a.write_bcr(ioaddr, 32,
1888                                                 lp->a.read_bcr(ioaddr,
1889                                                                32) | 0x0080);
1890                                 /* enable auto negotiate, setup, disable fd */
1891                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1892                                 val |= 0x20;
1893                                 lp->a.write_bcr(ioaddr, 32, val);
1894                         }
1895                 }
1896         } else {
1897                 int first_phy = -1;
1898                 u16 bmcr;
1899                 u32 bcr9;
1900                 struct ethtool_cmd ecmd;
1901
1902                 /*
1903                  * There is really no good other way to handle multiple PHYs
1904                  * other than turning off all automatics
1905                  */
1906                 val = lp->a.read_bcr(ioaddr, 2);
1907                 lp->a.write_bcr(ioaddr, 2, val & ~2);
1908                 val = lp->a.read_bcr(ioaddr, 32);
1909                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
1910
1911                 if (!(lp->options & PCNET32_PORT_ASEL)) {
1912                         /* setup ecmd */
1913                         ecmd.port = PORT_MII;
1914                         ecmd.transceiver = XCVR_INTERNAL;
1915                         ecmd.autoneg = AUTONEG_DISABLE;
1916                         ecmd.speed =
1917                             lp->
1918                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1919                         bcr9 = lp->a.read_bcr(ioaddr, 9);
1920
1921                         if (lp->options & PCNET32_PORT_FD) {
1922                                 ecmd.duplex = DUPLEX_FULL;
1923                                 bcr9 |= (1 << 0);
1924                         } else {
1925                                 ecmd.duplex = DUPLEX_HALF;
1926                                 bcr9 |= ~(1 << 0);
1927                         }
1928                         lp->a.write_bcr(ioaddr, 9, bcr9);
1929                 }
1930
1931                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1932                         if (lp->phymask & (1 << i)) {
1933                                 /* isolate all but the first PHY */
1934                                 bmcr = mdio_read(dev, i, MII_BMCR);
1935                                 if (first_phy == -1) {
1936                                         first_phy = i;
1937                                         mdio_write(dev, i, MII_BMCR,
1938                                                    bmcr & ~BMCR_ISOLATE);
1939                                 } else {
1940                                         mdio_write(dev, i, MII_BMCR,
1941                                                    bmcr | BMCR_ISOLATE);
1942                                 }
1943                                 /* use mii_ethtool_sset to setup PHY */
1944                                 lp->mii_if.phy_id = i;
1945                                 ecmd.phy_address = i;
1946                                 if (lp->options & PCNET32_PORT_ASEL) {
1947                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
1948                                         ecmd.autoneg = AUTONEG_ENABLE;
1949                                 }
1950                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
1951                         }
1952                 }
1953                 lp->mii_if.phy_id = first_phy;
1954                 if (netif_msg_link(lp))
1955                         printk(KERN_INFO "%s: Using PHY number %d.\n",
1956                                dev->name, first_phy);
1957         }
1958
1959 #ifdef DO_DXSUFLO
1960         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
1961                 val = lp->a.read_csr(ioaddr, 3);
1962                 val |= 0x40;
1963                 lp->a.write_csr(ioaddr, 3, val);
1964         }
1965 #endif
1966
1967         lp->init_block.mode =
1968             le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1969         pcnet32_load_multicast(dev);
1970
1971         if (pcnet32_init_ring(dev)) {
1972                 rc = -ENOMEM;
1973                 goto err_free_ring;
1974         }
1975
1976         /* Re-initialize the PCNET32, and start it when done. */
1977         lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
1978                                     offsetof(struct pcnet32_private,
1979                                              init_block)) & 0xffff);
1980         lp->a.write_csr(ioaddr, 2,
1981                         (lp->dma_addr +
1982                          offsetof(struct pcnet32_private, init_block)) >> 16);
1983
1984         lp->a.write_csr(ioaddr, 4, 0x0915);
1985         lp->a.write_csr(ioaddr, 0, 0x0001);
1986
1987         netif_start_queue(dev);
1988
1989         /* Print the link status and start the watchdog */
1990         pcnet32_check_media(dev, 1);
1991         mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1992
1993         i = 0;
1994         while (i++ < 100)
1995                 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
1996                         break;
1997         /*
1998          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1999          * reports that doing so triggers a bug in the '974.
2000          */
2001         lp->a.write_csr(ioaddr, 0, 0x0042);
2002
2003         if (netif_msg_ifup(lp))
2004                 printk(KERN_DEBUG
2005                        "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2006                        dev->name, i,
2007                        (u32) (lp->dma_addr +
2008                               offsetof(struct pcnet32_private, init_block)),
2009                        lp->a.read_csr(ioaddr, 0));
2010
2011         spin_unlock_irqrestore(&lp->lock, flags);
2012
2013         return 0;               /* Always succeed */
2014
2015       err_free_ring:
2016         /* free any allocated skbuffs */
2017         pcnet32_purge_rx_ring(dev);
2018
2019         /*
2020          * Switch back to 16bit mode to avoid problems with dumb
2021          * DOS packet driver after a warm reboot
2022          */
2023         lp->a.write_bcr(ioaddr, 20, 4);
2024
2025       err_free_irq:
2026         spin_unlock_irqrestore(&lp->lock, flags);
2027         free_irq(dev->irq, dev);
2028         return rc;
2029 }
2030
2031 /*
2032  * The LANCE has been halted for one reason or another (busmaster memory
2033  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2034  * etc.).  Modern LANCE variants always reload their ring-buffer
2035  * configuration when restarted, so we must reinitialize our ring
2036  * context before restarting.  As part of this reinitialization,
2037  * find all packets still on the Tx ring and pretend that they had been
2038  * sent (in effect, drop the packets on the floor) - the higher-level
2039  * protocols will time out and retransmit.  It'd be better to shuffle
2040  * these skbs to a temp list and then actually re-Tx them after
2041  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2042  */
2043
2044 static void pcnet32_purge_tx_ring(struct net_device *dev)
2045 {
2046         struct pcnet32_private *lp = dev->priv;
2047         int i;
2048
2049         for (i = 0; i < lp->tx_ring_size; i++) {
2050                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2051                 wmb();          /* Make sure adapter sees owner change */
2052                 if (lp->tx_skbuff[i]) {
2053                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2054                                          lp->tx_skbuff[i]->len,
2055                                          PCI_DMA_TODEVICE);
2056                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2057                 }
2058                 lp->tx_skbuff[i] = NULL;
2059                 lp->tx_dma_addr[i] = 0;
2060         }
2061 }
2062
2063 /* Initialize the PCNET32 Rx and Tx rings. */
2064 static int pcnet32_init_ring(struct net_device *dev)
2065 {
2066         struct pcnet32_private *lp = dev->priv;
2067         int i;
2068
2069         lp->tx_full = 0;
2070         lp->cur_rx = lp->cur_tx = 0;
2071         lp->dirty_rx = lp->dirty_tx = 0;
2072
2073         for (i = 0; i < lp->rx_ring_size; i++) {
2074                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2075                 if (rx_skbuff == NULL) {
2076                         if (!
2077                             (rx_skbuff = lp->rx_skbuff[i] =
2078                              dev_alloc_skb(PKT_BUF_SZ))) {
2079                                 /* there is not much, we can do at this point */
2080                                 if (pcnet32_debug & NETIF_MSG_DRV)
2081                                         printk(KERN_ERR
2082                                                "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2083                                                dev->name);
2084                                 return -1;
2085                         }
2086                         skb_reserve(rx_skbuff, 2);
2087                 }
2088
2089                 rmb();
2090                 if (lp->rx_dma_addr[i] == 0)
2091                         lp->rx_dma_addr[i] =
2092                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2093                                            PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2094                 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2095                 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2096                 wmb();          /* Make sure owner changes after all others are visible */
2097                 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2098         }
2099         /* The Tx buffer address is filled in as needed, but we do need to clear
2100          * the upper ownership bit. */
2101         for (i = 0; i < lp->tx_ring_size; i++) {
2102                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2103                 wmb();          /* Make sure adapter sees owner change */
2104                 lp->tx_ring[i].base = 0;
2105                 lp->tx_dma_addr[i] = 0;
2106         }
2107
2108         lp->init_block.tlen_rlen =
2109             le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2110         for (i = 0; i < 6; i++)
2111                 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2112         lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2113         lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2114         wmb();                  /* Make sure all changes are visible */
2115         return 0;
2116 }
2117
2118 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2119  * then flush the pending transmit operations, re-initialize the ring,
2120  * and tell the chip to initialize.
2121  */
2122 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2123 {
2124         struct pcnet32_private *lp = dev->priv;
2125         unsigned long ioaddr = dev->base_addr;
2126         int i;
2127
2128         /* wait for stop */
2129         for (i = 0; i < 100; i++)
2130                 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
2131                         break;
2132
2133         if (i >= 100 && netif_msg_drv(lp))
2134                 printk(KERN_ERR
2135                        "%s: pcnet32_restart timed out waiting for stop.\n",
2136                        dev->name);
2137
2138         pcnet32_purge_tx_ring(dev);
2139         if (pcnet32_init_ring(dev))
2140                 return;
2141
2142         /* ReInit Ring */
2143         lp->a.write_csr(ioaddr, 0, 1);
2144         i = 0;
2145         while (i++ < 1000)
2146                 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
2147                         break;
2148
2149         lp->a.write_csr(ioaddr, 0, csr0_bits);
2150 }
2151
2152 static void pcnet32_tx_timeout(struct net_device *dev)
2153 {
2154         struct pcnet32_private *lp = dev->priv;
2155         unsigned long ioaddr = dev->base_addr, flags;
2156
2157         spin_lock_irqsave(&lp->lock, flags);
2158         /* Transmitter timeout, serious problems. */
2159         if (pcnet32_debug & NETIF_MSG_DRV)
2160                 printk(KERN_ERR
2161                        "%s: transmit timed out, status %4.4x, resetting.\n",
2162                        dev->name, lp->a.read_csr(ioaddr, 0));
2163         lp->a.write_csr(ioaddr, 0, 0x0004);
2164         lp->stats.tx_errors++;
2165         if (netif_msg_tx_err(lp)) {
2166                 int i;
2167                 printk(KERN_DEBUG
2168                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2169                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2170                        lp->cur_rx);
2171                 for (i = 0; i < lp->rx_ring_size; i++)
2172                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2173                                le32_to_cpu(lp->rx_ring[i].base),
2174                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2175                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2176                                le16_to_cpu(lp->rx_ring[i].status));
2177                 for (i = 0; i < lp->tx_ring_size; i++)
2178                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2179                                le32_to_cpu(lp->tx_ring[i].base),
2180                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2181                                le32_to_cpu(lp->tx_ring[i].misc),
2182                                le16_to_cpu(lp->tx_ring[i].status));
2183                 printk("\n");
2184         }
2185         pcnet32_restart(dev, 0x0042);
2186
2187         dev->trans_start = jiffies;
2188         netif_wake_queue(dev);
2189
2190         spin_unlock_irqrestore(&lp->lock, flags);
2191 }
2192
2193 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2194 {
2195         struct pcnet32_private *lp = dev->priv;
2196         unsigned long ioaddr = dev->base_addr;
2197         u16 status;
2198         int entry;
2199         unsigned long flags;
2200
2201         spin_lock_irqsave(&lp->lock, flags);
2202
2203         if (netif_msg_tx_queued(lp)) {
2204                 printk(KERN_DEBUG
2205                        "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2206                        dev->name, lp->a.read_csr(ioaddr, 0));
2207         }
2208
2209         /* Default status -- will not enable Successful-TxDone
2210          * interrupt when that option is available to us.
2211          */
2212         status = 0x8300;
2213
2214         /* Fill in a Tx ring entry */
2215
2216         /* Mask to ring buffer boundary. */
2217         entry = lp->cur_tx & lp->tx_mod_mask;
2218
2219         /* Caution: the write order is important here, set the status
2220          * with the "ownership" bits last. */
2221
2222         lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2223
2224         lp->tx_ring[entry].misc = 0x00000000;
2225
2226         lp->tx_skbuff[entry] = skb;
2227         lp->tx_dma_addr[entry] =
2228             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2229         lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2230         wmb();                  /* Make sure owner changes after all others are visible */
2231         lp->tx_ring[entry].status = le16_to_cpu(status);
2232
2233         lp->cur_tx++;
2234         lp->stats.tx_bytes += skb->len;
2235
2236         /* Trigger an immediate send poll. */
2237         lp->a.write_csr(ioaddr, 0, 0x0048);
2238
2239         dev->trans_start = jiffies;
2240
2241         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2242                 lp->tx_full = 1;
2243                 netif_stop_queue(dev);
2244         }
2245         spin_unlock_irqrestore(&lp->lock, flags);
2246         return 0;
2247 }
2248
2249 /* The PCNET32 interrupt handler. */
2250 static irqreturn_t
2251 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2252 {
2253         struct net_device *dev = dev_id;
2254         struct pcnet32_private *lp;
2255         unsigned long ioaddr;
2256         u16 csr0, rap;
2257         int boguscnt = max_interrupt_work;
2258         int must_restart;
2259
2260         if (!dev) {
2261                 if (pcnet32_debug & NETIF_MSG_INTR)
2262                         printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2263                                __FUNCTION__, irq);
2264                 return IRQ_NONE;
2265         }
2266
2267         ioaddr = dev->base_addr;
2268         lp = dev->priv;
2269
2270         spin_lock(&lp->lock);
2271
2272         rap = lp->a.read_rap(ioaddr);
2273         while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2274                 if (csr0 == 0xffff) {
2275                         break;  /* PCMCIA remove happened */
2276                 }
2277                 /* Acknowledge all of the current interrupt sources ASAP. */
2278                 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2279
2280                 must_restart = 0;
2281
2282                 if (netif_msg_intr(lp))
2283                         printk(KERN_DEBUG
2284                                "%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
2285                                dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2286
2287                 if (csr0 & 0x0400)      /* Rx interrupt */
2288                         pcnet32_rx(dev);
2289
2290                 if (csr0 & 0x0200) {    /* Tx-done interrupt */
2291                         unsigned int dirty_tx = lp->dirty_tx;
2292                         int delta;
2293
2294                         while (dirty_tx != lp->cur_tx) {
2295                                 int entry = dirty_tx & lp->tx_mod_mask;
2296                                 int status =
2297                                     (short)le16_to_cpu(lp->tx_ring[entry].
2298                                                        status);
2299
2300                                 if (status < 0)
2301                                         break;  /* It still hasn't been Txed */
2302
2303                                 lp->tx_ring[entry].base = 0;
2304
2305                                 if (status & 0x4000) {
2306                                         /* There was an major error, log it. */
2307                                         int err_status =
2308                                             le32_to_cpu(lp->tx_ring[entry].
2309                                                         misc);
2310                                         lp->stats.tx_errors++;
2311                                         if (netif_msg_tx_err(lp))
2312                                                 printk(KERN_ERR
2313                                                        "%s: Tx error status=%04x err_status=%08x\n",
2314                                                        dev->name, status,
2315                                                        err_status);
2316                                         if (err_status & 0x04000000)
2317                                                 lp->stats.tx_aborted_errors++;
2318                                         if (err_status & 0x08000000)
2319                                                 lp->stats.tx_carrier_errors++;
2320                                         if (err_status & 0x10000000)
2321                                                 lp->stats.tx_window_errors++;
2322 #ifndef DO_DXSUFLO
2323                                         if (err_status & 0x40000000) {
2324                                                 lp->stats.tx_fifo_errors++;
2325                                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
2326                                                 /* Remove this verbosity later! */
2327                                                 if (netif_msg_tx_err(lp))
2328                                                         printk(KERN_ERR
2329                                                                "%s: Tx FIFO error! CSR0=%4.4x\n",
2330                                                                dev->name, csr0);
2331                                                 must_restart = 1;
2332                                         }
2333 #else
2334                                         if (err_status & 0x40000000) {
2335                                                 lp->stats.tx_fifo_errors++;
2336                                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
2337                                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
2338                                                         /* Remove this verbosity later! */
2339                                                         if (netif_msg_tx_err
2340                                                             (lp))
2341                                                                 printk(KERN_ERR
2342                                                                        "%s: Tx FIFO error! CSR0=%4.4x\n",
2343                                                                        dev->
2344                                                                        name,
2345                                                                        csr0);
2346                                                         must_restart = 1;
2347                                                 }
2348                                         }
2349 #endif
2350                                 } else {
2351                                         if (status & 0x1800)
2352                                                 lp->stats.collisions++;
2353                                         lp->stats.tx_packets++;
2354                                 }
2355
2356                                 /* We must free the original skb */
2357                                 if (lp->tx_skbuff[entry]) {
2358                                         pci_unmap_single(lp->pci_dev,
2359                                                          lp->tx_dma_addr[entry],
2360                                                          lp->tx_skbuff[entry]->
2361                                                          len, PCI_DMA_TODEVICE);
2362                                         dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2363                                         lp->tx_skbuff[entry] = NULL;
2364                                         lp->tx_dma_addr[entry] = 0;
2365                                 }
2366                                 dirty_tx++;
2367                         }
2368
2369                         delta =
2370                             (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
2371                                                        lp->tx_ring_size);
2372                         if (delta > lp->tx_ring_size) {
2373                                 if (netif_msg_drv(lp))
2374                                         printk(KERN_ERR
2375                                                "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2376                                                dev->name, dirty_tx, lp->cur_tx,
2377                                                lp->tx_full);
2378                                 dirty_tx += lp->tx_ring_size;
2379                                 delta -= lp->tx_ring_size;
2380                         }
2381
2382                         if (lp->tx_full &&
2383                             netif_queue_stopped(dev) &&
2384                             delta < lp->tx_ring_size - 2) {
2385                                 /* The ring is no longer full, clear tbusy. */
2386                                 lp->tx_full = 0;
2387                                 netif_wake_queue(dev);
2388                         }
2389                         lp->dirty_tx = dirty_tx;
2390                 }
2391
2392                 /* Log misc errors. */
2393                 if (csr0 & 0x4000)
2394                         lp->stats.tx_errors++;  /* Tx babble. */
2395                 if (csr0 & 0x1000) {
2396                         /*
2397                          * this happens when our receive ring is full. This shouldn't
2398                          * be a problem as we will see normal rx interrupts for the frames
2399                          * in the receive ring. But there are some PCI chipsets (I can
2400                          * reproduce this on SP3G with Intel saturn chipset) which have
2401                          * sometimes problems and will fill up the receive ring with
2402                          * error descriptors. In this situation we don't get a rx
2403                          * interrupt, but a missed frame interrupt sooner or later.
2404                          * So we try to clean up our receive ring here.
2405                          */
2406                         pcnet32_rx(dev);
2407                         lp->stats.rx_errors++;  /* Missed a Rx frame. */
2408                 }
2409                 if (csr0 & 0x0800) {
2410                         if (netif_msg_drv(lp))
2411                                 printk(KERN_ERR
2412                                        "%s: Bus master arbitration failure, status %4.4x.\n",
2413                                        dev->name, csr0);
2414                         /* unlike for the lance, there is no restart needed */
2415                 }
2416
2417                 if (must_restart) {
2418                         /* reset the chip to clear the error condition, then restart */
2419                         lp->a.reset(ioaddr);
2420                         lp->a.write_csr(ioaddr, 4, 0x0915);
2421                         pcnet32_restart(dev, 0x0002);
2422                         netif_wake_queue(dev);
2423                 }
2424         }
2425
2426         /* Set interrupt enable. */
2427         lp->a.write_csr(ioaddr, 0, 0x0040);
2428         lp->a.write_rap(ioaddr, rap);
2429
2430         if (netif_msg_intr(lp))
2431                 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2432                        dev->name, lp->a.read_csr(ioaddr, 0));
2433
2434         spin_unlock(&lp->lock);
2435
2436         return IRQ_HANDLED;
2437 }
2438
2439 static int pcnet32_rx(struct net_device *dev)
2440 {
2441         struct pcnet32_private *lp = dev->priv;
2442         int entry = lp->cur_rx & lp->rx_mod_mask;
2443         int boguscnt = lp->rx_ring_size / 2;
2444
2445         /* If we own the next entry, it's a new packet. Send it up. */
2446         while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2447                 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2448
2449                 if (status != 0x03) {   /* There was an error. */
2450                         /*
2451                          * There is a tricky error noted by John Murphy,
2452                          * <murf@perftech.com> to Russ Nelson: Even with full-sized
2453                          * buffers it's possible for a jabber packet to use two
2454                          * buffers, with only the last correctly noting the error.
2455                          */
2456                         if (status & 0x01)      /* Only count a general error at the */
2457                                 lp->stats.rx_errors++;  /* end of a packet. */
2458                         if (status & 0x20)
2459                                 lp->stats.rx_frame_errors++;
2460                         if (status & 0x10)
2461                                 lp->stats.rx_over_errors++;
2462                         if (status & 0x08)
2463                                 lp->stats.rx_crc_errors++;
2464                         if (status & 0x04)
2465                                 lp->stats.rx_fifo_errors++;
2466                         lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
2467                 } else {
2468                         /* Malloc up new buffer, compatible with net-2e. */
2469                         short pkt_len =
2470                             (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
2471                             - 4;
2472                         struct sk_buff *skb;
2473
2474                         /* Discard oversize frames. */
2475                         if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2476                                 if (netif_msg_drv(lp))
2477                                         printk(KERN_ERR
2478                                                "%s: Impossible packet size %d!\n",
2479                                                dev->name, pkt_len);
2480                                 lp->stats.rx_errors++;
2481                         } else if (pkt_len < 60) {
2482                                 if (netif_msg_rx_err(lp))
2483                                         printk(KERN_ERR "%s: Runt packet!\n",
2484                                                dev->name);
2485                                 lp->stats.rx_errors++;
2486                         } else {
2487                                 int rx_in_place = 0;
2488
2489                                 if (pkt_len > rx_copybreak) {
2490                                         struct sk_buff *newskb;
2491
2492                                         if ((newskb =
2493                                              dev_alloc_skb(PKT_BUF_SZ))) {
2494                                                 skb_reserve(newskb, 2);
2495                                                 skb = lp->rx_skbuff[entry];
2496                                                 pci_unmap_single(lp->pci_dev,
2497                                                                  lp->
2498                                                                  rx_dma_addr
2499                                                                  [entry],
2500                                                                  PKT_BUF_SZ - 2,
2501                                                                  PCI_DMA_FROMDEVICE);
2502                                                 skb_put(skb, pkt_len);
2503                                                 lp->rx_skbuff[entry] = newskb;
2504                                                 newskb->dev = dev;
2505                                                 lp->rx_dma_addr[entry] =
2506                                                     pci_map_single(lp->pci_dev,
2507                                                                    newskb->data,
2508                                                                    PKT_BUF_SZ -
2509                                                                    2,
2510                                                                    PCI_DMA_FROMDEVICE);
2511                                                 lp->rx_ring[entry].base =
2512                                                     le32_to_cpu(lp->
2513                                                                 rx_dma_addr
2514                                                                 [entry]);
2515                                                 rx_in_place = 1;
2516                                         } else
2517                                                 skb = NULL;
2518                                 } else {
2519                                         skb = dev_alloc_skb(pkt_len + 2);
2520                                 }
2521
2522                                 if (skb == NULL) {
2523                                         int i;
2524                                         if (netif_msg_drv(lp))
2525                                                 printk(KERN_ERR
2526                                                        "%s: Memory squeeze, deferring packet.\n",
2527                                                        dev->name);
2528                                         for (i = 0; i < lp->rx_ring_size; i++)
2529                                                 if ((short)
2530                                                     le16_to_cpu(lp->
2531                                                                 rx_ring[(entry +
2532                                                                          i)
2533                                                                         & lp->
2534                                                                         rx_mod_mask].
2535                                                                 status) < 0)
2536                                                         break;
2537
2538                                         if (i > lp->rx_ring_size - 2) {
2539                                                 lp->stats.rx_dropped++;
2540                                                 lp->rx_ring[entry].status |=
2541                                                     le16_to_cpu(0x8000);
2542                                                 wmb();  /* Make sure adapter sees owner change */
2543                                                 lp->cur_rx++;
2544                                         }
2545                                         break;
2546                                 }
2547                                 skb->dev = dev;
2548                                 if (!rx_in_place) {
2549                                         skb_reserve(skb, 2);    /* 16 byte align */
2550                                         skb_put(skb, pkt_len);  /* Make room */
2551                                         pci_dma_sync_single_for_cpu(lp->pci_dev,
2552                                                                     lp->
2553                                                                     rx_dma_addr
2554                                                                     [entry],
2555                                                                     PKT_BUF_SZ -
2556                                                                     2,
2557                                                                     PCI_DMA_FROMDEVICE);
2558                                         eth_copy_and_sum(skb,
2559                                                          (unsigned char *)(lp->
2560                                                                            rx_skbuff
2561                                                                            [entry]->
2562                                                                            data),
2563                                                          pkt_len, 0);
2564                                         pci_dma_sync_single_for_device(lp->
2565                                                                        pci_dev,
2566                                                                        lp->
2567                                                                        rx_dma_addr
2568                                                                        [entry],
2569                                                                        PKT_BUF_SZ
2570                                                                        - 2,
2571                                                                        PCI_DMA_FROMDEVICE);
2572                                 }
2573                                 lp->stats.rx_bytes += skb->len;
2574                                 skb->protocol = eth_type_trans(skb, dev);
2575                                 netif_rx(skb);
2576                                 dev->last_rx = jiffies;
2577                                 lp->stats.rx_packets++;
2578                         }
2579                 }
2580                 /*
2581                  * The docs say that the buffer length isn't touched, but Andrew Boyd
2582                  * of QNX reports that some revs of the 79C965 clear it.
2583                  */
2584                 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2585                 wmb();          /* Make sure owner changes after all others are visible */
2586                 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2587                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2588                 if (--boguscnt <= 0)
2589                         break;  /* don't stay in loop forever */
2590         }
2591
2592         return 0;
2593 }
2594
2595 static int pcnet32_close(struct net_device *dev)
2596 {
2597         unsigned long ioaddr = dev->base_addr;
2598         struct pcnet32_private *lp = dev->priv;
2599         unsigned long flags;
2600
2601         del_timer_sync(&lp->watchdog_timer);
2602
2603         netif_stop_queue(dev);
2604
2605         spin_lock_irqsave(&lp->lock, flags);
2606
2607         lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2608
2609         if (netif_msg_ifdown(lp))
2610                 printk(KERN_DEBUG
2611                        "%s: Shutting down ethercard, status was %2.2x.\n",
2612                        dev->name, lp->a.read_csr(ioaddr, 0));
2613
2614         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2615         lp->a.write_csr(ioaddr, 0, 0x0004);
2616
2617         /*
2618          * Switch back to 16bit mode to avoid problems with dumb
2619          * DOS packet driver after a warm reboot
2620          */
2621         lp->a.write_bcr(ioaddr, 20, 4);
2622
2623         spin_unlock_irqrestore(&lp->lock, flags);
2624
2625         free_irq(dev->irq, dev);
2626
2627         spin_lock_irqsave(&lp->lock, flags);
2628
2629         pcnet32_purge_rx_ring(dev);
2630         pcnet32_purge_tx_ring(dev);
2631
2632         spin_unlock_irqrestore(&lp->lock, flags);
2633
2634         return 0;
2635 }
2636
2637 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2638 {
2639         struct pcnet32_private *lp = dev->priv;
2640         unsigned long ioaddr = dev->base_addr;
2641         u16 saved_addr;
2642         unsigned long flags;
2643
2644         spin_lock_irqsave(&lp->lock, flags);
2645         saved_addr = lp->a.read_rap(ioaddr);
2646         lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2647         lp->a.write_rap(ioaddr, saved_addr);
2648         spin_unlock_irqrestore(&lp->lock, flags);
2649
2650         return &lp->stats;
2651 }
2652
2653 /* taken from the sunlance driver, which it took from the depca driver */
2654 static void pcnet32_load_multicast(struct net_device *dev)
2655 {
2656         struct pcnet32_private *lp = dev->priv;
2657         volatile struct pcnet32_init_block *ib = &lp->init_block;
2658         volatile u16 *mcast_table = (u16 *) & ib->filter;
2659         struct dev_mc_list *dmi = dev->mc_list;
2660         unsigned long ioaddr = dev->base_addr;
2661         char *addrs;
2662         int i;
2663         u32 crc;
2664
2665         /* set all multicast bits */
2666         if (dev->flags & IFF_ALLMULTI) {
2667                 ib->filter[0] = 0xffffffff;
2668                 ib->filter[1] = 0xffffffff;
2669                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2670                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2671                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2672                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2673                 return;
2674         }
2675         /* clear the multicast filter */
2676         ib->filter[0] = 0;
2677         ib->filter[1] = 0;
2678
2679         /* Add addresses */
2680         for (i = 0; i < dev->mc_count; i++) {
2681                 addrs = dmi->dmi_addr;
2682                 dmi = dmi->next;
2683
2684                 /* multicast address? */
2685                 if (!(*addrs & 1))
2686                         continue;
2687
2688                 crc = ether_crc_le(6, addrs);
2689                 crc = crc >> 26;
2690                 mcast_table[crc >> 4] =
2691                     le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2692                                 (1 << (crc & 0xf)));
2693         }
2694         for (i = 0; i < 4; i++)
2695                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2696                                 le16_to_cpu(mcast_table[i]));
2697         return;
2698 }
2699
2700 /*
2701  * Set or clear the multicast filter for this adaptor.
2702  */
2703 static void pcnet32_set_multicast_list(struct net_device *dev)
2704 {
2705         unsigned long ioaddr = dev->base_addr, flags;
2706         struct pcnet32_private *lp = dev->priv;
2707         int csr15, suspended;
2708
2709         spin_lock_irqsave(&lp->lock, flags);
2710         suspended = pcnet32_suspend(dev, &flags, 0);
2711         csr15 = lp->a.read_csr(ioaddr, CSR15);
2712         if (dev->flags & IFF_PROMISC) {
2713                 /* Log any net taps. */
2714                 if (netif_msg_hw(lp))
2715                         printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2716                                dev->name);
2717                 lp->init_block.mode =
2718                     le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2719                                 7);
2720                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2721         } else {
2722                 lp->init_block.mode =
2723                     le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2724                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2725                 pcnet32_load_multicast(dev);
2726         }
2727
2728         if (suspended) {
2729                 int csr5;
2730                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2731                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2732                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2733         } else {
2734                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2735                 pcnet32_restart(dev, CSR0_NORMAL);
2736                 netif_wake_queue(dev);
2737         }
2738
2739         spin_unlock_irqrestore(&lp->lock, flags);
2740 }
2741
2742 /* This routine assumes that the lp->lock is held */
2743 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2744 {
2745         struct pcnet32_private *lp = dev->priv;
2746         unsigned long ioaddr = dev->base_addr;
2747         u16 val_out;
2748
2749         if (!lp->mii)
2750                 return 0;
2751
2752         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2753         val_out = lp->a.read_bcr(ioaddr, 34);
2754
2755         return val_out;
2756 }
2757
2758 /* This routine assumes that the lp->lock is held */
2759 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2760 {
2761         struct pcnet32_private *lp = dev->priv;
2762         unsigned long ioaddr = dev->base_addr;
2763
2764         if (!lp->mii)
2765                 return;
2766
2767         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2768         lp->a.write_bcr(ioaddr, 34, val);
2769 }
2770
2771 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2772 {
2773         struct pcnet32_private *lp = dev->priv;
2774         int rc;
2775         unsigned long flags;
2776
2777         /* SIOC[GS]MIIxxx ioctls */
2778         if (lp->mii) {
2779                 spin_lock_irqsave(&lp->lock, flags);
2780                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2781                 spin_unlock_irqrestore(&lp->lock, flags);
2782         } else {
2783                 rc = -EOPNOTSUPP;
2784         }
2785
2786         return rc;
2787 }
2788
2789 static int pcnet32_check_otherphy(struct net_device *dev)
2790 {
2791         struct pcnet32_private *lp = dev->priv;
2792         struct mii_if_info mii = lp->mii_if;
2793         u16 bmcr;
2794         int i;
2795
2796         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2797                 if (i == lp->mii_if.phy_id)
2798                         continue;       /* skip active phy */
2799                 if (lp->phymask & (1 << i)) {
2800                         mii.phy_id = i;
2801                         if (mii_link_ok(&mii)) {
2802                                 /* found PHY with active link */
2803                                 if (netif_msg_link(lp))
2804                                         printk(KERN_INFO
2805                                                "%s: Using PHY number %d.\n",
2806                                                dev->name, i);
2807
2808                                 /* isolate inactive phy */
2809                                 bmcr =
2810                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2811                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2812                                            bmcr | BMCR_ISOLATE);
2813
2814                                 /* de-isolate new phy */
2815                                 bmcr = mdio_read(dev, i, MII_BMCR);
2816                                 mdio_write(dev, i, MII_BMCR,
2817                                            bmcr & ~BMCR_ISOLATE);
2818
2819                                 /* set new phy address */
2820                                 lp->mii_if.phy_id = i;
2821                                 return 1;
2822                         }
2823                 }
2824         }
2825         return 0;
2826 }
2827
2828 /*
2829  * Show the status of the media.  Similar to mii_check_media however it
2830  * correctly shows the link speed for all (tested) pcnet32 variants.
2831  * Devices with no mii just report link state without speed.
2832  *
2833  * Caller is assumed to hold and release the lp->lock.
2834  */
2835
2836 static void pcnet32_check_media(struct net_device *dev, int verbose)
2837 {
2838         struct pcnet32_private *lp = dev->priv;
2839         int curr_link;
2840         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2841         u32 bcr9;
2842
2843         if (lp->mii) {
2844                 curr_link = mii_link_ok(&lp->mii_if);
2845         } else {
2846                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2847                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2848         }
2849         if (!curr_link) {
2850                 if (prev_link || verbose) {
2851                         netif_carrier_off(dev);
2852                         if (netif_msg_link(lp))
2853                                 printk(KERN_INFO "%s: link down\n", dev->name);
2854                 }
2855                 if (lp->phycount > 1) {
2856                         curr_link = pcnet32_check_otherphy(dev);
2857                         prev_link = 0;
2858                 }
2859         } else if (verbose || !prev_link) {
2860                 netif_carrier_on(dev);
2861                 if (lp->mii) {
2862                         if (netif_msg_link(lp)) {
2863                                 struct ethtool_cmd ecmd;
2864                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2865                                 printk(KERN_INFO
2866                                        "%s: link up, %sMbps, %s-duplex\n",
2867                                        dev->name,
2868                                        (ecmd.speed == SPEED_100) ? "100" : "10",
2869                                        (ecmd.duplex ==
2870                                         DUPLEX_FULL) ? "full" : "half");
2871                         }
2872                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2873                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2874                                 if (lp->mii_if.full_duplex)
2875                                         bcr9 |= (1 << 0);
2876                                 else
2877                                         bcr9 &= ~(1 << 0);
2878                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2879                         }
2880                 } else {
2881                         if (netif_msg_link(lp))
2882                                 printk(KERN_INFO "%s: link up\n", dev->name);
2883                 }
2884         }
2885 }
2886
2887 /*
2888  * Check for loss of link and link establishment.
2889  * Can not use mii_check_media because it does nothing if mode is forced.
2890  */
2891
2892 static void pcnet32_watchdog(struct net_device *dev)
2893 {
2894         struct pcnet32_private *lp = dev->priv;
2895         unsigned long flags;
2896
2897         /* Print the link status if it has changed */
2898         spin_lock_irqsave(&lp->lock, flags);
2899         pcnet32_check_media(dev, 0);
2900         spin_unlock_irqrestore(&lp->lock, flags);
2901
2902         mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2903 }
2904
2905 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2906 {
2907         struct net_device *dev = pci_get_drvdata(pdev);
2908
2909         if (dev) {
2910                 struct pcnet32_private *lp = dev->priv;
2911
2912                 unregister_netdev(dev);
2913                 pcnet32_free_ring(dev);
2914                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2915                 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2916                 free_netdev(dev);
2917                 pci_disable_device(pdev);
2918                 pci_set_drvdata(pdev, NULL);
2919         }
2920 }
2921
2922 static struct pci_driver pcnet32_driver = {
2923         .name = DRV_NAME,
2924         .probe = pcnet32_probe_pci,
2925         .remove = __devexit_p(pcnet32_remove_one),
2926         .id_table = pcnet32_pci_tbl,
2927 };
2928
2929 /* An additional parameter that may be passed in... */
2930 static int debug = -1;
2931 static int tx_start_pt = -1;
2932 static int pcnet32_have_pci;
2933
2934 module_param(debug, int, 0);
2935 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2936 module_param(max_interrupt_work, int, 0);
2937 MODULE_PARM_DESC(max_interrupt_work,
2938                  DRV_NAME " maximum events handled per interrupt");
2939 module_param(rx_copybreak, int, 0);
2940 MODULE_PARM_DESC(rx_copybreak,
2941                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2942 module_param(tx_start_pt, int, 0);
2943 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2944 module_param(pcnet32vlb, int, 0);
2945 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2946 module_param_array(options, int, NULL, 0);
2947 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2948 module_param_array(full_duplex, int, NULL, 0);
2949 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2950 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2951 module_param_array(homepna, int, NULL, 0);
2952 MODULE_PARM_DESC(homepna,
2953                  DRV_NAME
2954                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2955
2956 MODULE_AUTHOR("Thomas Bogendoerfer");
2957 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2958 MODULE_LICENSE("GPL");
2959
2960 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2961
2962 static int __init pcnet32_init_module(void)
2963 {
2964         printk(KERN_INFO "%s", version);
2965
2966         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2967
2968         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2969                 tx_start = tx_start_pt;
2970
2971         /* find the PCI devices */
2972         if (!pci_module_init(&pcnet32_driver))
2973                 pcnet32_have_pci = 1;
2974
2975         /* should we find any remaining VLbus devices ? */
2976         if (pcnet32vlb)
2977                 pcnet32_probe_vlbus(pcnet32_portlist);
2978
2979         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2980                 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2981
2982         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2983 }
2984
2985 static void __exit pcnet32_cleanup_module(void)
2986 {
2987         struct net_device *next_dev;
2988
2989         while (pcnet32_dev) {
2990                 struct pcnet32_private *lp = pcnet32_dev->priv;
2991                 next_dev = lp->next;
2992                 unregister_netdev(pcnet32_dev);
2993                 pcnet32_free_ring(pcnet32_dev);
2994                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2995                 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2996                 free_netdev(pcnet32_dev);
2997                 pcnet32_dev = next_dev;
2998         }
2999
3000         if (pcnet32_have_pci)
3001                 pci_unregister_driver(&pcnet32_driver);
3002 }
3003
3004 module_init(pcnet32_init_module);
3005 module_exit(pcnet32_cleanup_module);
3006
3007 /*
3008  * Local variables:
3009  *  c-indent-level: 4
3010  *  tab-width: 8
3011  * End:
3012  */