drivers/net/pch_gbe/pch_gbe_main.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   4  *
   5  * This code was derived from the Intel e1000e Linux driver.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  19  */
  20
  21 #include "pch_gbe.h"
  22 #include "pch_gbe_api.h"
  23 #include <linux/prefetch.h>
  24
  25 #define DRV_VERSION     "1.00"
  26 const char pch_driver_version[] = DRV_VERSION;
  27
  28 #define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  29 #define PCH_GBE_MAR_ENTRIES             16
  30 #define PCH_GBE_SHORT_PKT               64
  31 #define DSC_INIT16                      0xC000
  32 #define PCH_GBE_DMA_ALIGN               0
  33 #define PCH_GBE_DMA_PADDING             2
  34 #define PCH_GBE_WATCHDOG_PERIOD         (1 * HZ)        /* watchdog time */
  35 #define PCH_GBE_COPYBREAK_DEFAULT       256
  36 #define PCH_GBE_PCI_BAR                 1
  37
  38 /* Macros for ML7223 */
  39 #define PCI_VENDOR_ID_ROHM                      0x10db
  40 #define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  41
  42 #define PCH_GBE_TX_WEIGHT         64
  43 #define PCH_GBE_RX_WEIGHT         64
  44 #define PCH_GBE_RX_BUFFER_WRITE   16
  45
  46 /* Initialize the wake-on-LAN settings */
  47 #define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  48
  49 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  50         PCH_GBE_CHIP_TYPE_INTERNAL | \
  51         PCH_GBE_RGMII_MODE_RGMII     \
  52         )
  53
  54 /* Ethertype field values */
  55 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  56 #define PCH_GBE_FRAME_SIZE_2048         2048
  57 #define PCH_GBE_FRAME_SIZE_4096         4096
  58 #define PCH_GBE_FRAME_SIZE_8192         8192
  59
  60 #define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  61 #define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  62 #define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  63 #define PCH_GBE_DESC_UNUSED(R) \
  64         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  65         (R)->next_to_clean - (R)->next_to_use - 1)
  66
  67 /* Pause packet value */
  68 #define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  69 #define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  70 #define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  71 #define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  72
  73 #define PCH_GBE_ETH_ALEN            6
  74
  75 /* This defines the bits that are set in the Interrupt Mask
  76  * Set/Read Register.  Each bit is documented below:
  77  *   o RXT0   = Receiver Timer Interrupt (ring 0)
  78  *   o TXDW   = Transmit Descriptor Written Back
  79  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  80  *   o RXSEQ  = Receive Sequence Error
  81  *   o LSC    = Link Status Change
  82  */
  83 #define PCH_GBE_INT_ENABLE_MASK ( \
  84         PCH_GBE_INT_RX_DMA_CMPLT |    \
  85         PCH_GBE_INT_RX_DSC_EMP   |    \
  86         PCH_GBE_INT_WOL_DET      |    \
  87         PCH_GBE_INT_TX_CMPLT          \
  88         )
  89
  90
  91 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
  92
  93 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
  94 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
  95                                int data);
  96
  97 inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
  98 {
  99         iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 100 }
 101
 102 /**
 103  * pch_gbe_mac_read_mac_addr - Read MAC address
 104  * @hw:             Pointer to the HW structure
 105  * Returns
 106  *      0:                      Successful.
 107  */
 108 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 109 {
 110         u32  adr1a, adr1b;
 111
 112         adr1a = ioread32(&hw->reg->mac_adr[0].high);
 113         adr1b = ioread32(&hw->reg->mac_adr[0].low);
 114
 115         hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 116         hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 117         hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 118         hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 119         hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 120         hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 121
 122         pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
 123         return 0;
 124 }
 125
 126 /**
 127  * pch_gbe_wait_clr_bit - Wait to clear a bit
 128  * @reg:        Pointer of register
 129  * @busy:       Busy bit
 130  */
 131 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 132 {
 133         u32 tmp;
 134         /* wait busy */
 135         tmp = 1000;
 136         while ((ioread32(reg) & bit) && --tmp)
 137                 cpu_relax();
 138         if (!tmp)
 139                 pr_err("Error: busy bit is not cleared\n");
 140 }
 141 /**
 142  * pch_gbe_mac_mar_set - Set MAC address register
 143  * @hw:     Pointer to the HW structure
 144  * @addr:   Pointer to the MAC address
 145  * @index:  MAC address array register
 146  */
 147 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 148 {
 149         u32 mar_low, mar_high, adrmask;
 150
 151         pr_debug("index : 0x%x\n", index);
 152
 153         /*
 154          * HW expects these in little endian so we reverse the byte order
 155          * from network order (big endian) to little endian
 156          */
 157         mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 158                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 159         mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 160         /* Stop the MAC Address of index. */
 161         adrmask = ioread32(&hw->reg->ADDR_MASK);
 162         iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 163         /* wait busy */
 164         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 165         /* Set the MAC address to the MAC address 1A/1B register */
 166         iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 167         iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 168         /* Start the MAC address of index */
 169         iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 170         /* wait busy */
 171         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 172 }
 173
 174 /**
 175  * pch_gbe_mac_reset_hw - Reset hardware
 176  * @hw: Pointer to the HW structure
 177  */
 178 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 179 {
 180         /* Read the MAC address. and store to the private data */
 181         pch_gbe_mac_read_mac_addr(hw);
 182         iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 183 #ifdef PCH_GBE_MAC_IFOP_RGMII
 184         iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 185 #endif
 186         pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 187         /* Setup the receive address */
 188         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 189         return;
 190 }
 191
 192 /**
 193  * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 194  * @hw: Pointer to the HW structure
 195  * @mar_count: Receive address registers
 196  */
 197 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 198 {
 199         u32 i;
 200
 201         /* Setup the receive address */
 202         pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 203
 204         /* Zero out the other receive addresses */
 205         for (i = 1; i < mar_count; i++) {
 206                 iowrite32(0, &hw->reg->mac_adr[i].high);
 207                 iowrite32(0, &hw->reg->mac_adr[i].low);
 208         }
 209         iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 210         /* wait busy */
 211         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 212 }
 213
 214
 215 /**
 216  * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 217  * @hw:             Pointer to the HW structure
 218  * @mc_addr_list:   Array of multicast addresses to program
 219  * @mc_addr_count:  Number of multicast addresses to program
 220  * @mar_used_count: The first MAC Address register free to program
 221  * @mar_total_num:  Total number of supported MAC Address Registers
 222  */
 223 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 224                                             u8 *mc_addr_list, u32 mc_addr_count,
 225                                             u32 mar_used_count, u32 mar_total_num)
 226 {
 227         u32 i, adrmask;
 228
 229         /* Load the first set of multicast addresses into the exact
 230          * filters (RAR).  If there are not enough to fill the RAR
 231          * array, clear the filters.
 232          */
 233         for (i = mar_used_count; i < mar_total_num; i++) {
 234                 if (mc_addr_count) {
 235                         pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 236                         mc_addr_count--;
 237                         mc_addr_list += PCH_GBE_ETH_ALEN;
 238                 } else {
 239                         /* Clear MAC address mask */
 240                         adrmask = ioread32(&hw->reg->ADDR_MASK);
 241                         iowrite32((adrmask | (0x0001 << i)),
 242                                         &hw->reg->ADDR_MASK);
 243                         /* wait busy */
 244                         pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 245                         /* Clear MAC address */
 246                         iowrite32(0, &hw->reg->mac_adr[i].high);
 247                         iowrite32(0, &hw->reg->mac_adr[i].low);
 248                 }
 249         }
 250 }
 251
 252 /**
 253  * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 254  * @hw:             Pointer to the HW structure
 255  * Returns
 256  *      0:                      Successful.
 257  *      Negative value:         Failed.
 258  */
 259 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 260 {
 261         struct pch_gbe_mac_info *mac = &hw->mac;
 262         u32 rx_fctrl;
 263
 264         pr_debug("mac->fc = %u\n", mac->fc);
 265
 266         rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 267
 268         switch (mac->fc) {
 269         case PCH_GBE_FC_NONE:
 270                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 271                 mac->tx_fc_enable = false;
 272                 break;
 273         case PCH_GBE_FC_RX_PAUSE:
 274                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 275                 mac->tx_fc_enable = false;
 276                 break;
 277         case PCH_GBE_FC_TX_PAUSE:
 278                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 279                 mac->tx_fc_enable = true;
 280                 break;
 281         case PCH_GBE_FC_FULL:
 282                 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 283                 mac->tx_fc_enable = true;
 284                 break;
 285         default:
 286                 pr_err("Flow control param set incorrectly\n");
 287                 return -EINVAL;
 288         }
 289         if (mac->link_duplex == DUPLEX_HALF)
 290                 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 291         iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 292         pr_debug("RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 293                  ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 294         return 0;
 295 }
 296
 297 /**
 298  * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 299  * @hw:     Pointer to the HW structure
 300  * @wu_evt: Wake up event
 301  */
 302 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 303 {
 304         u32 addr_mask;
 305
 306         pr_debug("wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 307                  wu_evt, ioread32(&hw->reg->ADDR_MASK));
 308
 309         if (wu_evt) {
 310                 /* Set Wake-On-Lan address mask */
 311                 addr_mask = ioread32(&hw->reg->ADDR_MASK);
 312                 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 313                 /* wait busy */
 314                 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 315                 iowrite32(0, &hw->reg->WOL_ST);
 316                 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 317                 iowrite32(0x02, &hw->reg->TCPIP_ACC);
 318                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 319         } else {
 320                 iowrite32(0, &hw->reg->WOL_CTRL);
 321                 iowrite32(0, &hw->reg->WOL_ST);
 322         }
 323         return;
 324 }
 325
 326 /**
 327  * pch_gbe_mac_ctrl_miim - Control MIIM interface
 328  * @hw:   Pointer to the HW structure
 329  * @addr: Address of PHY
 330  * @dir:  Operetion. (Write or Read)
 331  * @reg:  Access register of PHY
 332  * @data: Write data.
 333  *
 334  * Returns: Read date.
 335  */
 336 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 337                         u16 data)
 338 {
 339         u32 data_out = 0;
 340         unsigned int i;
 341         unsigned long flags;
 342
 343         spin_lock_irqsave(&hw->miim_lock, flags);
 344
 345         for (i = 100; i; --i) {
 346                 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 347                         break;
 348                 udelay(20);
 349         }
 350         if (i == 0) {
 351                 pr_err("pch-gbe.miim won't go Ready\n");
 352                 spin_unlock_irqrestore(&hw->miim_lock, flags);
 353                 return 0;       /* No way to indicate timeout error */
 354         }
 355         iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 356                   (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 357                   dir | data), &hw->reg->MIIM);
 358         for (i = 0; i < 100; i++) {
 359                 udelay(20);
 360                 data_out = ioread32(&hw->reg->MIIM);
 361                 if ((data_out & PCH_GBE_MIIM_OPER_READY))
 362                         break;
 363         }
 364         spin_unlock_irqrestore(&hw->miim_lock, flags);
 365
 366         pr_debug("PHY %s: reg=%d, data=0x%04X\n",
 367                  dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 368                  dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 369         return (u16) data_out;
 370 }
 371
 372 /**
 373  * pch_gbe_mac_set_pause_packet - Set pause packet
 374  * @hw:   Pointer to the HW structure
 375  */
 376 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 377 {
 378         unsigned long tmp2, tmp3;
 379
 380         /* Set Pause packet */
 381         tmp2 = hw->mac.addr[1];
 382         tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 383         tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 384
 385         tmp3 = hw->mac.addr[5];
 386         tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 387         tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 388         tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 389
 390         iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 391         iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 392         iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 393         iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 394         iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 395
 396         /* Transmit Pause Packet */
 397         iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 398
 399         pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 400                  ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
 401                  ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
 402                  ioread32(&hw->reg->PAUSE_PKT5));
 403
 404         return;
 405 }
 406
 407
 408 /**
 409  * pch_gbe_alloc_queues - Allocate memory for all rings
 410  * @adapter:  Board private structure to initialize
 411  * Returns
 412  *      0:      Successfully
 413  *      Negative value: Failed
 414  */
 415 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 416 {
 417         int size;
 418
 419         size = (int)sizeof(struct pch_gbe_tx_ring);
 420         adapter->tx_ring = kzalloc(size, GFP_KERNEL);
 421         if (!adapter->tx_ring)
 422                 return -ENOMEM;
 423         size = (int)sizeof(struct pch_gbe_rx_ring);
 424         adapter->rx_ring = kzalloc(size, GFP_KERNEL);
 425         if (!adapter->rx_ring) {
 426                 kfree(adapter->tx_ring);
 427                 return -ENOMEM;
 428         }
 429         return 0;
 430 }
 431
 432 /**
 433  * pch_gbe_init_stats - Initialize status
 434  * @adapter:  Board private structure to initialize
 435  */
 436 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 437 {
 438         memset(&adapter->stats, 0, sizeof(adapter->stats));
 439         return;
 440 }
 441
 442 /**
 443  * pch_gbe_init_phy - Initialize PHY
 444  * @adapter:  Board private structure to initialize
 445  * Returns
 446  *      0:      Successfully
 447  *      Negative value: Failed
 448  */
 449 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 450 {
 451         struct net_device *netdev = adapter->netdev;
 452         u32 addr;
 453         u16 bmcr, stat;
 454
 455         /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 456         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 457                 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 458                 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 459                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 460                 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 461                 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 462                         break;
 463         }
 464         adapter->hw.phy.addr = adapter->mii.phy_id;
 465         pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
 466         if (addr == 32)
 467                 return -EAGAIN;
 468         /* Selected the phy and isolate the rest */
 469         for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 470                 if (addr != adapter->mii.phy_id) {
 471                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 472                                            BMCR_ISOLATE);
 473                 } else {
 474                         bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 475                         pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 476                                            bmcr & ~BMCR_ISOLATE);
 477                 }
 478         }
 479
 480         /* MII setup */
 481         adapter->mii.phy_id_mask = 0x1F;
 482         adapter->mii.reg_num_mask = 0x1F;
 483         adapter->mii.dev = adapter->netdev;
 484         adapter->mii.mdio_read = pch_gbe_mdio_read;
 485         adapter->mii.mdio_write = pch_gbe_mdio_write;
 486         adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 487         return 0;
 488 }
 489
 490 /**
 491  * pch_gbe_mdio_read - The read function for mii
 492  * @netdev: Network interface device structure
 493  * @addr:   Phy ID
 494  * @reg:    Access location
 495  * Returns
 496  *      0:      Successfully
 497  *      Negative value: Failed
 498  */
 499 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 500 {
 501         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 502         struct pch_gbe_hw *hw = &adapter->hw;
 503
 504         return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 505                                      (u16) 0);
 506 }
 507
 508 /**
 509  * pch_gbe_mdio_write - The write function for mii
 510  * @netdev: Network interface device structure
 511  * @addr:   Phy ID (not used)
 512  * @reg:    Access location
 513  * @data:   Write data
 514  */
 515 static void pch_gbe_mdio_write(struct net_device *netdev,
 516                                int addr, int reg, int data)
 517 {
 518         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 519         struct pch_gbe_hw *hw = &adapter->hw;
 520
 521         pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 522 }
 523
 524 /**
 525  * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 526  * @work:  Pointer of board private structure
 527  */
 528 static void pch_gbe_reset_task(struct work_struct *work)
 529 {
 530         struct pch_gbe_adapter *adapter;
 531         adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 532
 533         rtnl_lock();
 534         pch_gbe_reinit_locked(adapter);
 535         rtnl_unlock();
 536 }
 537
 538 /**
 539  * pch_gbe_reinit_locked- Re-initialization
 540  * @adapter:  Board private structure
 541  */
 542 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 543 {
 544         pch_gbe_down(adapter);
 545         pch_gbe_up(adapter);
 546 }
 547
 548 /**
 549  * pch_gbe_reset - Reset GbE
 550  * @adapter:  Board private structure
 551  */
 552 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 553 {
 554         pch_gbe_mac_reset_hw(&adapter->hw);
 555         /* Setup the receive address. */
 556         pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 557         if (pch_gbe_hal_init_hw(&adapter->hw))
 558                 pr_err("Hardware Error\n");
 559 }
 560
 561 /**
 562  * pch_gbe_free_irq - Free an interrupt
 563  * @adapter:  Board private structure
 564  */
 565 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 566 {
 567         struct net_device *netdev = adapter->netdev;
 568
 569         free_irq(adapter->pdev->irq, netdev);
 570         if (adapter->have_msi) {
 571                 pci_disable_msi(adapter->pdev);
 572                 pr_debug("call pci_disable_msi\n");
 573         }
 574 }
 575
 576 /**
 577  * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 578  * @adapter:  Board private structure
 579  */
 580 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 581 {
 582         struct pch_gbe_hw *hw = &adapter->hw;
 583
 584         atomic_inc(&adapter->irq_sem);
 585         iowrite32(0, &hw->reg->INT_EN);
 586         ioread32(&hw->reg->INT_ST);
 587         synchronize_irq(adapter->pdev->irq);
 588
 589         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
 590 }
 591
 592 /**
 593  * pch_gbe_irq_enable - Enable default interrupt generation settings
 594  * @adapter:  Board private structure
 595  */
 596 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 597 {
 598         struct pch_gbe_hw *hw = &adapter->hw;
 599
 600         if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 601                 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 602         ioread32(&hw->reg->INT_ST);
 603         pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
 604 }
 605
 606
 607
 608 /**
 609  * pch_gbe_setup_tctl - configure the Transmit control registers
 610  * @adapter:  Board private structure
 611  */
 612 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 613 {
 614         struct pch_gbe_hw *hw = &adapter->hw;
 615         u32 tx_mode, tcpip;
 616
 617         tx_mode = PCH_GBE_TM_LONG_PKT |
 618                 PCH_GBE_TM_ST_AND_FD |
 619                 PCH_GBE_TM_SHORT_PKT |
 620                 PCH_GBE_TM_TH_TX_STRT_8 |
 621                 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 622
 623         iowrite32(tx_mode, &hw->reg->TX_MODE);
 624
 625         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 626         tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 627         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 628         return;
 629 }
 630
 631 /**
 632  * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 633  * @adapter:  Board private structure
 634  */
 635 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 636 {
 637         struct pch_gbe_hw *hw = &adapter->hw;
 638         u32 tdba, tdlen, dctrl;
 639
 640         pr_debug("dma addr = 0x%08llx  size = 0x%08x\n",
 641                  (unsigned long long)adapter->tx_ring->dma,
 642                  adapter->tx_ring->size);
 643
 644         /* Setup the HW Tx Head and Tail descriptor pointers */
 645         tdba = adapter->tx_ring->dma;
 646         tdlen = adapter->tx_ring->size - 0x10;
 647         iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 648         iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 649         iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 650
 651         /* Enables Transmission DMA */
 652         dctrl = ioread32(&hw->reg->DMA_CTRL);
 653         dctrl |= PCH_GBE_TX_DMA_EN;
 654         iowrite32(dctrl, &hw->reg->DMA_CTRL);
 655 }
 656
 657 /**
 658  * pch_gbe_setup_rctl - Configure the receive control registers
 659  * @adapter:  Board private structure
 660  */
 661 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 662 {
 663         struct net_device *netdev = adapter->netdev;
 664         struct pch_gbe_hw *hw = &adapter->hw;
 665         u32 rx_mode, tcpip;
 666
 667         rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 668         PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 669
 670         iowrite32(rx_mode, &hw->reg->RX_MODE);
 671
 672         tcpip = ioread32(&hw->reg->TCPIP_ACC);
 673
 674         if (netdev->features & NETIF_F_RXCSUM) {
 675                 tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF;
 676                 tcpip |= PCH_GBE_RX_TCPIPACC_EN;
 677         } else {
 678                 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 679                 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 680         }
 681         iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 682         return;
 683 }
 684
 685 /**
 686  * pch_gbe_configure_rx - Configure Receive Unit after Reset
 687  * @adapter:  Board private structure
 688  */
 689 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 690 {
 691         struct pch_gbe_hw *hw = &adapter->hw;
 692         u32 rdba, rdlen, rctl, rxdma;
 693
 694         pr_debug("dma adr = 0x%08llx  size = 0x%08x\n",
 695                  (unsigned long long)adapter->rx_ring->dma,
 696                  adapter->rx_ring->size);
 697
 698         pch_gbe_mac_force_mac_fc(hw);
 699
 700         /* Disables Receive MAC */
 701         rctl = ioread32(&hw->reg->MAC_RX_EN);
 702         iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 703
 704         /* Disables Receive DMA */
 705         rxdma = ioread32(&hw->reg->DMA_CTRL);
 706         rxdma &= ~PCH_GBE_RX_DMA_EN;
 707         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 708
 709         pr_debug("MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 710                  ioread32(&hw->reg->MAC_RX_EN),
 711                  ioread32(&hw->reg->DMA_CTRL));
 712
 713         /* Setup the HW Rx Head and Tail Descriptor Pointers and
 714          * the Base and Length of the Rx Descriptor Ring */
 715         rdba = adapter->rx_ring->dma;
 716         rdlen = adapter->rx_ring->size - 0x10;
 717         iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 718         iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 719         iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 720
 721         /* Enables Receive DMA */
 722         rxdma = ioread32(&hw->reg->DMA_CTRL);
 723         rxdma |= PCH_GBE_RX_DMA_EN;
 724         iowrite32(rxdma, &hw->reg->DMA_CTRL);
 725         /* Enables Receive */
 726         iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
 727 }
 728
 729 /**
 730  * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 731  * @adapter:     Board private structure
 732  * @buffer_info: Buffer information structure
 733  */
 734 static void pch_gbe_unmap_and_free_tx_resource(
 735         struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 736 {
 737         if (buffer_info->mapped) {
 738                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 739                                  buffer_info->length, DMA_TO_DEVICE);
 740                 buffer_info->mapped = false;
 741         }
 742         if (buffer_info->skb) {
 743                 dev_kfree_skb_any(buffer_info->skb);
 744                 buffer_info->skb = NULL;
 745         }
 746 }
 747
 748 /**
 749  * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 750  * @adapter:      Board private structure
 751  * @buffer_info:  Buffer information structure
 752  */
 753 static void pch_gbe_unmap_and_free_rx_resource(
 754                                         struct pch_gbe_adapter *adapter,
 755                                         struct pch_gbe_buffer *buffer_info)
 756 {
 757         if (buffer_info->mapped) {
 758                 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 759                                  buffer_info->length, DMA_FROM_DEVICE);
 760                 buffer_info->mapped = false;
 761         }
 762         if (buffer_info->skb) {
 763                 dev_kfree_skb_any(buffer_info->skb);
 764                 buffer_info->skb = NULL;
 765         }
 766 }
 767
 768 /**
 769  * pch_gbe_clean_tx_ring - Free Tx Buffers
 770  * @adapter:  Board private structure
 771  * @tx_ring:  Ring to be cleaned
 772  */
 773 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 774                                    struct pch_gbe_tx_ring *tx_ring)
 775 {
 776         struct pch_gbe_hw *hw = &adapter->hw;
 777         struct pch_gbe_buffer *buffer_info;
 778         unsigned long size;
 779         unsigned int i;
 780
 781         /* Free all the Tx ring sk_buffs */
 782         for (i = 0; i < tx_ring->count; i++) {
 783                 buffer_info = &tx_ring->buffer_info[i];
 784                 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 785         }
 786         pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 787
 788         size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 789         memset(tx_ring->buffer_info, 0, size);
 790
 791         /* Zero out the descriptor ring */
 792         memset(tx_ring->desc, 0, tx_ring->size);
 793         tx_ring->next_to_use = 0;
 794         tx_ring->next_to_clean = 0;
 795         iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
 796         iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
 797 }
 798
 799 /**
 800  * pch_gbe_clean_rx_ring - Free Rx Buffers
 801  * @adapter:  Board private structure
 802  * @rx_ring:  Ring to free buffers from
 803  */
 804 static void
 805 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
 806                       struct pch_gbe_rx_ring *rx_ring)
 807 {
 808         struct pch_gbe_hw *hw = &adapter->hw;
 809         struct pch_gbe_buffer *buffer_info;
 810         unsigned long size;
 811         unsigned int i;
 812
 813         /* Free all the Rx ring sk_buffs */
 814         for (i = 0; i < rx_ring->count; i++) {
 815                 buffer_info = &rx_ring->buffer_info[i];
 816                 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
 817         }
 818         pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
 819         size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
 820         memset(rx_ring->buffer_info, 0, size);
 821
 822         /* Zero out the descriptor ring */
 823         memset(rx_ring->desc, 0, rx_ring->size);
 824         rx_ring->next_to_clean = 0;
 825         rx_ring->next_to_use = 0;
 826         iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
 827         iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
 828 }
 829
 830 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
 831                                     u16 duplex)
 832 {
 833         struct pch_gbe_hw *hw = &adapter->hw;
 834         unsigned long rgmii = 0;
 835
 836         /* Set the RGMII control. */
 837 #ifdef PCH_GBE_MAC_IFOP_RGMII
 838         switch (speed) {
 839         case SPEED_10:
 840                 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
 841                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 842                 break;
 843         case SPEED_100:
 844                 rgmii = (PCH_GBE_RGMII_RATE_25M |
 845                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 846                 break;
 847         case SPEED_1000:
 848                 rgmii = (PCH_GBE_RGMII_RATE_125M |
 849                          PCH_GBE_MAC_RGMII_CTRL_SETTING);
 850                 break;
 851         }
 852         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
 853 #else   /* GMII */
 854         rgmii = 0;
 855         iowrite32(rgmii, &hw->reg->RGMII_CTRL);
 856 #endif
 857 }
 858 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
 859                               u16 duplex)
 860 {
 861         struct net_device *netdev = adapter->netdev;
 862         struct pch_gbe_hw *hw = &adapter->hw;
 863         unsigned long mode = 0;
 864
 865         /* Set the communication mode */
 866         switch (speed) {
 867         case SPEED_10:
 868                 mode = PCH_GBE_MODE_MII_ETHER;
 869                 netdev->tx_queue_len = 10;
 870                 break;
 871         case SPEED_100:
 872                 mode = PCH_GBE_MODE_MII_ETHER;
 873                 netdev->tx_queue_len = 100;
 874                 break;
 875         case SPEED_1000:
 876                 mode = PCH_GBE_MODE_GMII_ETHER;
 877                 break;
 878         }
 879         if (duplex == DUPLEX_FULL)
 880                 mode |= PCH_GBE_MODE_FULL_DUPLEX;
 881         else
 882                 mode |= PCH_GBE_MODE_HALF_DUPLEX;
 883         iowrite32(mode, &hw->reg->MODE);
 884 }
 885
 886 /**
 887  * pch_gbe_watchdog - Watchdog process
 888  * @data:  Board private structure
 889  */
 890 static void pch_gbe_watchdog(unsigned long data)
 891 {
 892         struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
 893         struct net_device *netdev = adapter->netdev;
 894         struct pch_gbe_hw *hw = &adapter->hw;
 895
 896         pr_debug("right now = %ld\n", jiffies);
 897
 898         pch_gbe_update_stats(adapter);
 899         if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
 900                 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
 901                 netdev->tx_queue_len = adapter->tx_queue_len;
 902                 /* mii library handles link maintenance tasks */
 903                 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
 904                         pr_err("ethtool get setting Error\n");
 905                         mod_timer(&adapter->watchdog_timer,
 906                                   round_jiffies(jiffies +
 907                                                 PCH_GBE_WATCHDOG_PERIOD));
 908                         return;
 909                 }
 910                 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
 911                 hw->mac.link_duplex = cmd.duplex;
 912                 /* Set the RGMII control. */
 913                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
 914                                                 hw->mac.link_duplex);
 915                 /* Set the communication mode */
 916                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
 917                                  hw->mac.link_duplex);
 918                 netdev_dbg(netdev,
 919                            "Link is Up %d Mbps %s-Duplex\n",
 920                            hw->mac.link_speed,
 921                            cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
 922                 netif_carrier_on(netdev);
 923                 netif_wake_queue(netdev);
 924         } else if ((!mii_link_ok(&adapter->mii)) &&
 925                    (netif_carrier_ok(netdev))) {
 926                 netdev_dbg(netdev, "NIC Link is Down\n");
 927                 hw->mac.link_speed = SPEED_10;
 928                 hw->mac.link_duplex = DUPLEX_HALF;
 929                 netif_carrier_off(netdev);
 930                 netif_stop_queue(netdev);
 931         }
 932         mod_timer(&adapter->watchdog_timer,
 933                   round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
 934 }
 935
 936 /**
 937  * pch_gbe_tx_queue - Carry out queuing of the transmission data
 938  * @adapter:  Board private structure
 939  * @tx_ring:  Tx descriptor ring structure
 940  * @skb:      Sockt buffer structure
 941  */
 942 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
 943                               struct pch_gbe_tx_ring *tx_ring,
 944                               struct sk_buff *skb)
 945 {
 946         struct pch_gbe_hw *hw = &adapter->hw;
 947         struct pch_gbe_tx_desc *tx_desc;
 948         struct pch_gbe_buffer *buffer_info;
 949         struct sk_buff *tmp_skb;
 950         unsigned int frame_ctrl;
 951         unsigned int ring_num;
 952         unsigned long flags;
 953
 954         /*-- Set frame control --*/
 955         frame_ctrl = 0;
 956         if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
 957                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
 958         if (skb->ip_summed == CHECKSUM_NONE)
 959                 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
 960
 961         /* Performs checksum processing */
 962         /*
 963          * It is because the hardware accelerator does not support a checksum,
 964          * when the received data size is less than 64 bytes.
 965          */
 966         if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
 967                 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
 968                               PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
 969                 if (skb->protocol == htons(ETH_P_IP)) {
 970                         struct iphdr *iph = ip_hdr(skb);
 971                         unsigned int offset;
 972                         iph->check = 0;
 973                         iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
 974                         offset = skb_transport_offset(skb);
 975                         if (iph->protocol == IPPROTO_TCP) {
 976                                 skb->csum = 0;
 977                                 tcp_hdr(skb)->check = 0;
 978                                 skb->csum = skb_checksum(skb, offset,
 979                                                          skb->len - offset, 0);
 980                                 tcp_hdr(skb)->check =
 981                                         csum_tcpudp_magic(iph->saddr,
 982                                                           iph->daddr,
 983                                                           skb->len - offset,
 984                                                           IPPROTO_TCP,
 985                                                           skb->csum);
 986                         } else if (iph->protocol == IPPROTO_UDP) {
 987                                 skb->csum = 0;
 988                                 udp_hdr(skb)->check = 0;
 989                                 skb->csum =
 990                                         skb_checksum(skb, offset,
 991                                                      skb->len - offset, 0);
 992                                 udp_hdr(skb)->check =
 993                                         csum_tcpudp_magic(iph->saddr,
 994                                                           iph->daddr,
 995                                                           skb->len - offset,
 996                                                           IPPROTO_UDP,
 997                                                           skb->csum);
 998                         }
 999                 }
1000         }
1001         spin_lock_irqsave(&tx_ring->tx_lock, flags);
1002         ring_num = tx_ring->next_to_use;
1003         if (unlikely((ring_num + 1) == tx_ring->count))
1004                 tx_ring->next_to_use = 0;
1005         else
1006                 tx_ring->next_to_use = ring_num + 1;
1007
1008         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1009         buffer_info = &tx_ring->buffer_info[ring_num];
1010         tmp_skb = buffer_info->skb;
1011
1012         /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1013         memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1014         tmp_skb->data[ETH_HLEN] = 0x00;
1015         tmp_skb->data[ETH_HLEN + 1] = 0x00;
1016         tmp_skb->len = skb->len;
1017         memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1018                (skb->len - ETH_HLEN));
1019         /*-- Set Buffer information --*/
1020         buffer_info->length = tmp_skb->len;
1021         buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1022                                           buffer_info->length,
1023                                           DMA_TO_DEVICE);
1024         if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1025                 pr_err("TX DMA map failed\n");
1026                 buffer_info->dma = 0;
1027                 buffer_info->time_stamp = 0;
1028                 tx_ring->next_to_use = ring_num;
1029                 return;
1030         }
1031         buffer_info->mapped = true;
1032         buffer_info->time_stamp = jiffies;
1033
1034         /*-- Set Tx descriptor --*/
1035         tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1036         tx_desc->buffer_addr = (buffer_info->dma);
1037         tx_desc->length = (tmp_skb->len);
1038         tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1039         tx_desc->tx_frame_ctrl = (frame_ctrl);
1040         tx_desc->gbec_status = (DSC_INIT16);
1041
1042         if (unlikely(++ring_num == tx_ring->count))
1043                 ring_num = 0;
1044
1045         /* Update software pointer of TX descriptor */
1046         iowrite32(tx_ring->dma +
1047                   (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1048                   &hw->reg->TX_DSC_SW_P);
1049         dev_kfree_skb_any(skb);
1050 }
1051
1052 /**
1053  * pch_gbe_update_stats - Update the board statistics counters
1054  * @adapter:  Board private structure
1055  */
1056 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1057 {
1058         struct net_device *netdev = adapter->netdev;
1059         struct pci_dev *pdev = adapter->pdev;
1060         struct pch_gbe_hw_stats *stats = &adapter->stats;
1061         unsigned long flags;
1062
1063         /*
1064          * Prevent stats update while adapter is being reset, or if the pci
1065          * connection is down.
1066          */
1067         if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1068                 return;
1069
1070         spin_lock_irqsave(&adapter->stats_lock, flags);
1071
1072         /* Update device status "adapter->stats" */
1073         stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1074         stats->tx_errors = stats->tx_length_errors +
1075             stats->tx_aborted_errors +
1076             stats->tx_carrier_errors + stats->tx_timeout_count;
1077
1078         /* Update network device status "adapter->net_stats" */
1079         netdev->stats.rx_packets = stats->rx_packets;
1080         netdev->stats.rx_bytes = stats->rx_bytes;
1081         netdev->stats.rx_dropped = stats->rx_dropped;
1082         netdev->stats.tx_packets = stats->tx_packets;
1083         netdev->stats.tx_bytes = stats->tx_bytes;
1084         netdev->stats.tx_dropped = stats->tx_dropped;
1085         /* Fill out the OS statistics structure */
1086         netdev->stats.multicast = stats->multicast;
1087         netdev->stats.collisions = stats->collisions;
1088         /* Rx Errors */
1089         netdev->stats.rx_errors = stats->rx_errors;
1090         netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1091         netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1092         /* Tx Errors */
1093         netdev->stats.tx_errors = stats->tx_errors;
1094         netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1095         netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1096
1097         spin_unlock_irqrestore(&adapter->stats_lock, flags);
1098 }
1099
1100 /**
1101  * pch_gbe_intr - Interrupt Handler
1102  * @irq:   Interrupt number
1103  * @data:  Pointer to a network interface device structure
1104  * Returns
1105  *      - IRQ_HANDLED:  Our interrupt
1106  *      - IRQ_NONE:     Not our interrupt
1107  */
1108 static irqreturn_t pch_gbe_intr(int irq, void *data)
1109 {
1110         struct net_device *netdev = data;
1111         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1112         struct pch_gbe_hw *hw = &adapter->hw;
1113         u32 int_st;
1114         u32 int_en;
1115
1116         /* Check request status */
1117         int_st = ioread32(&hw->reg->INT_ST);
1118         int_st = int_st & ioread32(&hw->reg->INT_EN);
1119         /* When request status is no interruption factor */
1120         if (unlikely(!int_st))
1121                 return IRQ_NONE;        /* Not our interrupt. End processing. */
1122         pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1123         if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1124                 adapter->stats.intr_rx_frame_err_count++;
1125         if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1126                 adapter->stats.intr_rx_fifo_err_count++;
1127         if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1128                 adapter->stats.intr_rx_dma_err_count++;
1129         if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1130                 adapter->stats.intr_tx_fifo_err_count++;
1131         if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1132                 adapter->stats.intr_tx_dma_err_count++;
1133         if (int_st & PCH_GBE_INT_TCPIP_ERR)
1134                 adapter->stats.intr_tcpip_err_count++;
1135         /* When Rx descriptor is empty  */
1136         if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1137                 adapter->stats.intr_rx_dsc_empty_count++;
1138                 pr_err("Rx descriptor is empty\n");
1139                 int_en = ioread32(&hw->reg->INT_EN);
1140                 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1141                 if (hw->mac.tx_fc_enable) {
1142                         /* Set Pause packet */
1143                         pch_gbe_mac_set_pause_packet(hw);
1144                 }
1145                 if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
1146                     == 0) {
1147                         return IRQ_HANDLED;
1148                 }
1149         }
1150
1151         /* When request status is Receive interruption */
1152         if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
1153                 if (likely(napi_schedule_prep(&adapter->napi))) {
1154                         /* Enable only Rx Descriptor empty */
1155                         atomic_inc(&adapter->irq_sem);
1156                         int_en = ioread32(&hw->reg->INT_EN);
1157                         int_en &=
1158                             ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1159                         iowrite32(int_en, &hw->reg->INT_EN);
1160                         /* Start polling for NAPI */
1161                         __napi_schedule(&adapter->napi);
1162                 }
1163         }
1164         pr_debug("return = 0x%08x  INT_EN reg = 0x%08x\n",
1165                  IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1166         return IRQ_HANDLED;
1167 }
1168
1169 /**
1170  * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1171  * @adapter:       Board private structure
1172  * @rx_ring:       Rx descriptor ring
1173  * @cleaned_count: Cleaned count
1174  */
1175 static void
1176 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1177                          struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1178 {
1179         struct net_device *netdev = adapter->netdev;
1180         struct pci_dev *pdev = adapter->pdev;
1181         struct pch_gbe_hw *hw = &adapter->hw;
1182         struct pch_gbe_rx_desc *rx_desc;
1183         struct pch_gbe_buffer *buffer_info;
1184         struct sk_buff *skb;
1185         unsigned int i;
1186         unsigned int bufsz;
1187
1188         bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN;
1189         i = rx_ring->next_to_use;
1190
1191         while ((cleaned_count--)) {
1192                 buffer_info = &rx_ring->buffer_info[i];
1193                 skb = buffer_info->skb;
1194                 if (skb) {
1195                         skb_trim(skb, 0);
1196                 } else {
1197                         skb = netdev_alloc_skb(netdev, bufsz);
1198                         if (unlikely(!skb)) {
1199                                 /* Better luck next round */
1200                                 adapter->stats.rx_alloc_buff_failed++;
1201                                 break;
1202                         }
1203                         /* 64byte align */
1204                         skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1205
1206                         buffer_info->skb = skb;
1207                         buffer_info->length = adapter->rx_buffer_len;
1208                 }
1209                 buffer_info->dma = dma_map_single(&pdev->dev,
1210                                                   skb->data,
1211                                                   buffer_info->length,
1212                                                   DMA_FROM_DEVICE);
1213                 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1214                         dev_kfree_skb(skb);
1215                         buffer_info->skb = NULL;
1216                         buffer_info->dma = 0;
1217                         adapter->stats.rx_alloc_buff_failed++;
1218                         break; /* while !buffer_info->skb */
1219                 }
1220                 buffer_info->mapped = true;
1221                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1222                 rx_desc->buffer_addr = (buffer_info->dma);
1223                 rx_desc->gbec_status = DSC_INIT16;
1224
1225                 pr_debug("i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1226                          i, (unsigned long long)buffer_info->dma,
1227                          buffer_info->length);
1228
1229                 if (unlikely(++i == rx_ring->count))
1230                         i = 0;
1231         }
1232         if (likely(rx_ring->next_to_use != i)) {
1233                 rx_ring->next_to_use = i;
1234                 if (unlikely(i-- == 0))
1235                         i = (rx_ring->count - 1);
1236                 iowrite32(rx_ring->dma +
1237                           (int)sizeof(struct pch_gbe_rx_desc) * i,
1238                           &hw->reg->RX_DSC_SW_P);
1239         }
1240         return;
1241 }
1242
1243 /**
1244  * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1245  * @adapter:   Board private structure
1246  * @tx_ring:   Tx descriptor ring
1247  */
1248 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1249                                         struct pch_gbe_tx_ring *tx_ring)
1250 {
1251         struct pch_gbe_buffer *buffer_info;
1252         struct sk_buff *skb;
1253         unsigned int i;
1254         unsigned int bufsz;
1255         struct pch_gbe_tx_desc *tx_desc;
1256
1257         bufsz =
1258             adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1259
1260         for (i = 0; i < tx_ring->count; i++) {
1261                 buffer_info = &tx_ring->buffer_info[i];
1262                 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1263                 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1264                 buffer_info->skb = skb;
1265                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1266                 tx_desc->gbec_status = (DSC_INIT16);
1267         }
1268         return;
1269 }
1270
1271 /**
1272  * pch_gbe_clean_tx - Reclaim resources after transmit completes
1273  * @adapter:   Board private structure
1274  * @tx_ring:   Tx descriptor ring
1275  * Returns
1276  *      true:  Cleaned the descriptor
1277  *      false: Not cleaned the descriptor
1278  */
1279 static bool
1280 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1281                  struct pch_gbe_tx_ring *tx_ring)
1282 {
1283         struct pch_gbe_tx_desc *tx_desc;
1284         struct pch_gbe_buffer *buffer_info;
1285         struct sk_buff *skb;
1286         unsigned int i;
1287         unsigned int cleaned_count = 0;
1288         bool cleaned = false;
1289
1290         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1291
1292         i = tx_ring->next_to_clean;
1293         tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1294         pr_debug("gbec_status:0x%04x  dma_status:0x%04x\n",
1295                  tx_desc->gbec_status, tx_desc->dma_status);
1296
1297         while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1298                 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1299                 cleaned = true;
1300                 buffer_info = &tx_ring->buffer_info[i];
1301                 skb = buffer_info->skb;
1302
1303                 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1304                         adapter->stats.tx_aborted_errors++;
1305                         pr_err("Transfer Abort Error\n");
1306                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1307                           ) {
1308                         adapter->stats.tx_carrier_errors++;
1309                         pr_err("Transfer Carrier Sense Error\n");
1310                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1311                           ) {
1312                         adapter->stats.tx_aborted_errors++;
1313                         pr_err("Transfer Collision Abort Error\n");
1314                 } else if ((tx_desc->gbec_status &
1315                             (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1316                              PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1317                         adapter->stats.collisions++;
1318                         adapter->stats.tx_packets++;
1319                         adapter->stats.tx_bytes += skb->len;
1320                         pr_debug("Transfer Collision\n");
1321                 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1322                           ) {
1323                         adapter->stats.tx_packets++;
1324                         adapter->stats.tx_bytes += skb->len;
1325                 }
1326                 if (buffer_info->mapped) {
1327                         pr_debug("unmap buffer_info->dma : %d\n", i);
1328                         dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1329                                          buffer_info->length, DMA_TO_DEVICE);
1330                         buffer_info->mapped = false;
1331                 }
1332                 if (buffer_info->skb) {
1333                         pr_debug("trim buffer_info->skb : %d\n", i);
1334                         skb_trim(buffer_info->skb, 0);
1335                 }
1336                 tx_desc->gbec_status = DSC_INIT16;
1337                 if (unlikely(++i == tx_ring->count))
1338                         i = 0;
1339                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1340
1341                 /* weight of a sort for tx, to avoid endless transmit cleanup */
1342                 if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
1343                         break;
1344         }
1345         pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1346                  cleaned_count);
1347         /* Recover from running out of Tx resources in xmit_frame */
1348         if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1349                 netif_wake_queue(adapter->netdev);
1350                 adapter->stats.tx_restart_count++;
1351                 pr_debug("Tx wake queue\n");
1352         }
1353         spin_lock(&adapter->tx_queue_lock);
1354         tx_ring->next_to_clean = i;
1355         spin_unlock(&adapter->tx_queue_lock);
1356         pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1357         return cleaned;
1358 }
1359
1360 /**
1361  * pch_gbe_clean_rx - Send received data up the network stack; legacy
1362  * @adapter:     Board private structure
1363  * @rx_ring:     Rx descriptor ring
1364  * @work_done:   Completed count
1365  * @work_to_do:  Request count
1366  * Returns
1367  *      true:  Cleaned the descriptor
1368  *      false: Not cleaned the descriptor
1369  */
1370 static bool
1371 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1372                  struct pch_gbe_rx_ring *rx_ring,
1373                  int *work_done, int work_to_do)
1374 {
1375         struct net_device *netdev = adapter->netdev;
1376         struct pci_dev *pdev = adapter->pdev;
1377         struct pch_gbe_buffer *buffer_info;
1378         struct pch_gbe_rx_desc *rx_desc;
1379         u32 length;
1380         unsigned int i;
1381         unsigned int cleaned_count = 0;
1382         bool cleaned = false;
1383         struct sk_buff *skb, *new_skb;
1384         u8 dma_status;
1385         u16 gbec_status;
1386         u32 tcp_ip_status;
1387
1388         i = rx_ring->next_to_clean;
1389
1390         while (*work_done < work_to_do) {
1391                 /* Check Rx descriptor status */
1392                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1393                 if (rx_desc->gbec_status == DSC_INIT16)
1394                         break;
1395                 cleaned = true;
1396                 cleaned_count++;
1397
1398                 dma_status = rx_desc->dma_status;
1399                 gbec_status = rx_desc->gbec_status;
1400                 tcp_ip_status = rx_desc->tcp_ip_status;
1401                 rx_desc->gbec_status = DSC_INIT16;
1402                 buffer_info = &rx_ring->buffer_info[i];
1403                 skb = buffer_info->skb;
1404
1405                 /* unmap dma */
1406                 dma_unmap_single(&pdev->dev, buffer_info->dma,
1407                                    buffer_info->length, DMA_FROM_DEVICE);
1408                 buffer_info->mapped = false;
1409                 /* Prefetch the packet */
1410                 prefetch(skb->data);
1411
1412                 pr_debug("RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x "
1413                          "TCP:0x%08x]  BufInf = 0x%p\n",
1414                          i, dma_status, gbec_status, tcp_ip_status,
1415                          buffer_info);
1416                 /* Error check */
1417                 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1418                         adapter->stats.rx_frame_errors++;
1419                         pr_err("Receive Not Octal Error\n");
1420                 } else if (unlikely(gbec_status &
1421                                 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1422                         adapter->stats.rx_frame_errors++;
1423                         pr_err("Receive Nibble Error\n");
1424                 } else if (unlikely(gbec_status &
1425                                 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1426                         adapter->stats.rx_crc_errors++;
1427                         pr_err("Receive CRC Error\n");
1428                 } else {
1429                         /* get receive length */
1430                         /* length convert[-3] */
1431                         length = (rx_desc->rx_words_eob) - 3;
1432
1433                         /* Decide the data conversion method */
1434                         if (!(netdev->features & NETIF_F_RXCSUM)) {
1435                                 /* [Header:14][payload] */
1436                                 if (NET_IP_ALIGN) {
1437                                         /* Because alignment differs,
1438                                          * the new_skb is newly allocated,
1439                                          * and data is copied to new_skb.*/
1440                                         new_skb = netdev_alloc_skb(netdev,
1441                                                          length + NET_IP_ALIGN);
1442                                         if (!new_skb) {
1443                                                 /* dorrop error */
1444                                                 pr_err("New skb allocation "
1445                                                         "Error\n");
1446                                                 goto dorrop;
1447                                         }
1448                                         skb_reserve(new_skb, NET_IP_ALIGN);
1449                                         memcpy(new_skb->data, skb->data,
1450                                                length);
1451                                         skb = new_skb;
1452                                 } else {
1453                                         /* DMA buffer is used as SKB as it is.*/
1454                                         buffer_info->skb = NULL;
1455                                 }
1456                         } else {
1457                                 /* [Header:14][padding:2][payload] */
1458                                 /* The length includes padding length */
1459                                 length = length - PCH_GBE_DMA_PADDING;
1460                                 if ((length < copybreak) ||
1461                                     (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) {
1462                                         /* Because alignment differs,
1463                                          * the new_skb is newly allocated,
1464                                          * and data is copied to new_skb.
1465                                          * Padding data is deleted
1466                                          * at the time of a copy.*/
1467                                         new_skb = netdev_alloc_skb(netdev,
1468                                                          length + NET_IP_ALIGN);
1469                                         if (!new_skb) {
1470                                                 /* dorrop error */
1471                                                 pr_err("New skb allocation "
1472                                                         "Error\n");
1473                                                 goto dorrop;
1474                                         }
1475                                         skb_reserve(new_skb, NET_IP_ALIGN);
1476                                         memcpy(new_skb->data, skb->data,
1477                                                ETH_HLEN);
1478                                         memcpy(&new_skb->data[ETH_HLEN],
1479                                                &skb->data[ETH_HLEN +
1480                                                PCH_GBE_DMA_PADDING],
1481                                                length - ETH_HLEN);
1482                                         skb = new_skb;
1483                                 } else {
1484                                         /* Padding data is deleted
1485                                          * by moving header data.*/
1486                                         memmove(&skb->data[PCH_GBE_DMA_PADDING],
1487                                                 &skb->data[0], ETH_HLEN);
1488                                         skb_reserve(skb, NET_IP_ALIGN);
1489                                         buffer_info->skb = NULL;
1490                                 }
1491                         }
1492                         /* The length includes FCS length */
1493                         length = length - ETH_FCS_LEN;
1494                         /* update status of driver */
1495                         adapter->stats.rx_bytes += length;
1496                         adapter->stats.rx_packets++;
1497                         if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1498                                 adapter->stats.multicast++;
1499                         /* Write meta date of skb */
1500                         skb_put(skb, length);
1501                         skb->protocol = eth_type_trans(skb, netdev);
1502                         if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1503                                 skb->ip_summed = CHECKSUM_NONE;
1504                         else
1505                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1506
1507                         napi_gro_receive(&adapter->napi, skb);
1508                         (*work_done)++;
1509                         pr_debug("Receive skb->ip_summed: %d length: %d\n",
1510                                  skb->ip_summed, length);
1511                 }
1512 dorrop:
1513                 /* return some buffers to hardware, one at a time is too slow */
1514                 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1515                         pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1516                                                  cleaned_count);
1517                         cleaned_count = 0;
1518                 }
1519                 if (++i == rx_ring->count)
1520                         i = 0;
1521         }
1522         rx_ring->next_to_clean = i;
1523         if (cleaned_count)
1524                 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1525         return cleaned;
1526 }
1527
1528 /**
1529  * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1530  * @adapter:  Board private structure
1531  * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1532  * Returns
1533  *      0:              Successfully
1534  *      Negative value: Failed
1535  */
1536 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1537                                 struct pch_gbe_tx_ring *tx_ring)
1538 {
1539         struct pci_dev *pdev = adapter->pdev;
1540         struct pch_gbe_tx_desc *tx_desc;
1541         int size;
1542         int desNo;
1543
1544         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1545         tx_ring->buffer_info = vzalloc(size);
1546         if (!tx_ring->buffer_info) {
1547                 pr_err("Unable to allocate memory for the buffer information\n");
1548                 return -ENOMEM;
1549         }
1550
1551         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1552
1553         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1554                                            &tx_ring->dma, GFP_KERNEL);
1555         if (!tx_ring->desc) {
1556                 vfree(tx_ring->buffer_info);
1557                 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1558                 return -ENOMEM;
1559         }
1560         memset(tx_ring->desc, 0, tx_ring->size);
1561
1562         tx_ring->next_to_use = 0;
1563         tx_ring->next_to_clean = 0;
1564         spin_lock_init(&tx_ring->tx_lock);
1565
1566         for (desNo = 0; desNo < tx_ring->count; desNo++) {
1567                 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1568                 tx_desc->gbec_status = DSC_INIT16;
1569         }
1570         pr_debug("tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx\n"
1571                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1572                  tx_ring->desc, (unsigned long long)tx_ring->dma,
1573                  tx_ring->next_to_clean, tx_ring->next_to_use);
1574         return 0;
1575 }
1576
1577 /**
1578  * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1579  * @adapter:  Board private structure
1580  * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1581  * Returns
1582  *      0:              Successfully
1583  *      Negative value: Failed
1584  */
1585 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1586                                 struct pch_gbe_rx_ring *rx_ring)
1587 {
1588         struct pci_dev *pdev = adapter->pdev;
1589         struct pch_gbe_rx_desc *rx_desc;
1590         int size;
1591         int desNo;
1592
1593         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1594         rx_ring->buffer_info = vzalloc(size);
1595         if (!rx_ring->buffer_info) {
1596                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1597                 return -ENOMEM;
1598         }
1599         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1600         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1601                                            &rx_ring->dma, GFP_KERNEL);
1602
1603         if (!rx_ring->desc) {
1604                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1605                 vfree(rx_ring->buffer_info);
1606                 return -ENOMEM;
1607         }
1608         memset(rx_ring->desc, 0, rx_ring->size);
1609         rx_ring->next_to_clean = 0;
1610         rx_ring->next_to_use = 0;
1611         for (desNo = 0; desNo < rx_ring->count; desNo++) {
1612                 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1613                 rx_desc->gbec_status = DSC_INIT16;
1614         }
1615         pr_debug("rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx "
1616                  "next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1617                  rx_ring->desc, (unsigned long long)rx_ring->dma,
1618                  rx_ring->next_to_clean, rx_ring->next_to_use);
1619         return 0;
1620 }
1621
1622 /**
1623  * pch_gbe_free_tx_resources - Free Tx Resources
1624  * @adapter:  Board private structure
1625  * @tx_ring:  Tx descriptor ring for a specific queue
1626  */
1627 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1628                                 struct pch_gbe_tx_ring *tx_ring)
1629 {
1630         struct pci_dev *pdev = adapter->pdev;
1631
1632         pch_gbe_clean_tx_ring(adapter, tx_ring);
1633         vfree(tx_ring->buffer_info);
1634         tx_ring->buffer_info = NULL;
1635         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1636         tx_ring->desc = NULL;
1637 }
1638
1639 /**
1640  * pch_gbe_free_rx_resources - Free Rx Resources
1641  * @adapter:  Board private structure
1642  * @rx_ring:  Ring to clean the resources from
1643  */
1644 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1645                                 struct pch_gbe_rx_ring *rx_ring)
1646 {
1647         struct pci_dev *pdev = adapter->pdev;
1648
1649         pch_gbe_clean_rx_ring(adapter, rx_ring);
1650         vfree(rx_ring->buffer_info);
1651         rx_ring->buffer_info = NULL;
1652         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1653         rx_ring->desc = NULL;
1654 }
1655
1656 /**
1657  * pch_gbe_request_irq - Allocate an interrupt line
1658  * @adapter:  Board private structure
1659  * Returns
1660  *      0:              Successfully
1661  *      Negative value: Failed
1662  */
1663 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1664 {
1665         struct net_device *netdev = adapter->netdev;
1666         int err;
1667         int flags;
1668
1669         flags = IRQF_SHARED;
1670         adapter->have_msi = false;
1671         err = pci_enable_msi(adapter->pdev);
1672         pr_debug("call pci_enable_msi\n");
1673         if (err) {
1674                 pr_debug("call pci_enable_msi - Error: %d\n", err);
1675         } else {
1676                 flags = 0;
1677                 adapter->have_msi = true;
1678         }
1679         err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1680                           flags, netdev->name, netdev);
1681         if (err)
1682                 pr_err("Unable to allocate interrupt Error: %d\n", err);
1683         pr_debug("adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1684                  adapter->have_msi, flags, err);
1685         return err;
1686 }
1687
1688
1689 static void pch_gbe_set_multi(struct net_device *netdev);
1690 /**
1691  * pch_gbe_up - Up GbE network device
1692  * @adapter:  Board private structure
1693  * Returns
1694  *      0:              Successfully
1695  *      Negative value: Failed
1696  */
1697 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1698 {
1699         struct net_device *netdev = adapter->netdev;
1700         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1701         struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1702         int err;
1703
1704         /* hardware has been reset, we need to reload some things */
1705         pch_gbe_set_multi(netdev);
1706
1707         pch_gbe_setup_tctl(adapter);
1708         pch_gbe_configure_tx(adapter);
1709         pch_gbe_setup_rctl(adapter);
1710         pch_gbe_configure_rx(adapter);
1711
1712         err = pch_gbe_request_irq(adapter);
1713         if (err) {
1714                 pr_err("Error: can't bring device up\n");
1715                 return err;
1716         }
1717         pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1718         pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1719         adapter->tx_queue_len = netdev->tx_queue_len;
1720
1721         mod_timer(&adapter->watchdog_timer, jiffies);
1722
1723         napi_enable(&adapter->napi);
1724         pch_gbe_irq_enable(adapter);
1725         netif_start_queue(adapter->netdev);
1726
1727         return 0;
1728 }
1729
1730 /**
1731  * pch_gbe_down - Down GbE network device
1732  * @adapter:  Board private structure
1733  */
1734 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1735 {
1736         struct net_device *netdev = adapter->netdev;
1737
1738         /* signal that we're down so the interrupt handler does not
1739          * reschedule our watchdog timer */
1740         napi_disable(&adapter->napi);
1741         atomic_set(&adapter->irq_sem, 0);
1742
1743         pch_gbe_irq_disable(adapter);
1744         pch_gbe_free_irq(adapter);
1745
1746         del_timer_sync(&adapter->watchdog_timer);
1747
1748         netdev->tx_queue_len = adapter->tx_queue_len;
1749         netif_carrier_off(netdev);
1750         netif_stop_queue(netdev);
1751
1752         pch_gbe_reset(adapter);
1753         pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1754         pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1755 }
1756
1757 /**
1758  * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1759  * @adapter:  Board private structure to initialize
1760  * Returns
1761  *      0:              Successfully
1762  *      Negative value: Failed
1763  */
1764 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1765 {
1766         struct pch_gbe_hw *hw = &adapter->hw;
1767         struct net_device *netdev = adapter->netdev;
1768
1769         adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1770         hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1771         hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1772
1773         /* Initialize the hardware-specific values */
1774         if (pch_gbe_hal_setup_init_funcs(hw)) {
1775                 pr_err("Hardware Initialization Failure\n");
1776                 return -EIO;
1777         }
1778         if (pch_gbe_alloc_queues(adapter)) {
1779                 pr_err("Unable to allocate memory for queues\n");
1780                 return -ENOMEM;
1781         }
1782         spin_lock_init(&adapter->hw.miim_lock);
1783         spin_lock_init(&adapter->tx_queue_lock);
1784         spin_lock_init(&adapter->stats_lock);
1785         spin_lock_init(&adapter->ethtool_lock);
1786         atomic_set(&adapter->irq_sem, 0);
1787         pch_gbe_irq_disable(adapter);
1788
1789         pch_gbe_init_stats(adapter);
1790
1791         pr_debug("rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
1792                  (u32) adapter->rx_buffer_len,
1793                  hw->mac.min_frame_size, hw->mac.max_frame_size);
1794         return 0;
1795 }
1796
1797 /**
1798  * pch_gbe_open - Called when a network interface is made active
1799  * @netdev:     Network interface device structure
1800  * Returns
1801  *      0:              Successfully
1802  *      Negative value: Failed
1803  */
1804 static int pch_gbe_open(struct net_device *netdev)
1805 {
1806         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1807         struct pch_gbe_hw *hw = &adapter->hw;
1808         int err;
1809
1810         /* allocate transmit descriptors */
1811         err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1812         if (err)
1813                 goto err_setup_tx;
1814         /* allocate receive descriptors */
1815         err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1816         if (err)
1817                 goto err_setup_rx;
1818         pch_gbe_hal_power_up_phy(hw);
1819         err = pch_gbe_up(adapter);
1820         if (err)
1821                 goto err_up;
1822         pr_debug("Success End\n");
1823         return 0;
1824
1825 err_up:
1826         if (!adapter->wake_up_evt)
1827                 pch_gbe_hal_power_down_phy(hw);
1828         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1829 err_setup_rx:
1830         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1831 err_setup_tx:
1832         pch_gbe_reset(adapter);
1833         pr_err("Error End\n");
1834         return err;
1835 }
1836
1837 /**
1838  * pch_gbe_stop - Disables a network interface
1839  * @netdev:  Network interface device structure
1840  * Returns
1841  *      0: Successfully
1842  */
1843 static int pch_gbe_stop(struct net_device *netdev)
1844 {
1845         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1846         struct pch_gbe_hw *hw = &adapter->hw;
1847
1848         pch_gbe_down(adapter);
1849         if (!adapter->wake_up_evt)
1850                 pch_gbe_hal_power_down_phy(hw);
1851         pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1852         pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1853         return 0;
1854 }
1855
1856 /**
1857  * pch_gbe_xmit_frame - Packet transmitting start
1858  * @skb:     Socket buffer structure
1859  * @netdev:  Network interface device structure
1860  * Returns
1861  *      - NETDEV_TX_OK:   Normal end
1862  *      - NETDEV_TX_BUSY: Error end
1863  */
1864 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1865 {
1866         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1867         struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1868         unsigned long flags;
1869
1870         if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1871                 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1872                        skb->len, adapter->hw.mac.max_frame_size);
1873                 dev_kfree_skb_any(skb);
1874                 adapter->stats.tx_length_errors++;
1875                 return NETDEV_TX_OK;
1876         }
1877         if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1878                 /* Collision - tell upper layer to requeue */
1879                 return NETDEV_TX_LOCKED;
1880         }
1881         if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1882                 netif_stop_queue(netdev);
1883                 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1884                 pr_debug("Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
1885                          tx_ring->next_to_use, tx_ring->next_to_clean);
1886                 return NETDEV_TX_BUSY;
1887         }
1888         spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1889
1890         /* CRC,ITAG no support */
1891         pch_gbe_tx_queue(adapter, tx_ring, skb);
1892         return NETDEV_TX_OK;
1893 }
1894
1895 /**
1896  * pch_gbe_get_stats - Get System Network Statistics
1897  * @netdev:  Network interface device structure
1898  * Returns:  The current stats
1899  */
1900 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1901 {
1902         /* only return the current stats */
1903         return &netdev->stats;
1904 }
1905
1906 /**
1907  * pch_gbe_set_multi - Multicast and Promiscuous mode set
1908  * @netdev:   Network interface device structure
1909  */
1910 static void pch_gbe_set_multi(struct net_device *netdev)
1911 {
1912         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1913         struct pch_gbe_hw *hw = &adapter->hw;
1914         struct netdev_hw_addr *ha;
1915         u8 *mta_list;
1916         u32 rctl;
1917         int i;
1918         int mc_count;
1919
1920         pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1921
1922         /* Check for Promiscuous and All Multicast modes */
1923         rctl = ioread32(&hw->reg->RX_MODE);
1924         mc_count = netdev_mc_count(netdev);
1925         if ((netdev->flags & IFF_PROMISC)) {
1926                 rctl &= ~PCH_GBE_ADD_FIL_EN;
1927                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1928         } else if ((netdev->flags & IFF_ALLMULTI)) {
1929                 /* all the multicasting receive permissions */
1930                 rctl |= PCH_GBE_ADD_FIL_EN;
1931                 rctl &= ~PCH_GBE_MLT_FIL_EN;
1932         } else {
1933                 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1934                         /* all the multicasting receive permissions */
1935                         rctl |= PCH_GBE_ADD_FIL_EN;
1936                         rctl &= ~PCH_GBE_MLT_FIL_EN;
1937                 } else {
1938                         rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1939                 }
1940         }
1941         iowrite32(rctl, &hw->reg->RX_MODE);
1942
1943         if (mc_count >= PCH_GBE_MAR_ENTRIES)
1944                 return;
1945         mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
1946         if (!mta_list)
1947                 return;
1948
1949         /* The shared function expects a packed array of only addresses. */
1950         i = 0;
1951         netdev_for_each_mc_addr(ha, netdev) {
1952                 if (i == mc_count)
1953                         break;
1954                 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
1955         }
1956         pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
1957                                         PCH_GBE_MAR_ENTRIES);
1958         kfree(mta_list);
1959
1960         pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
1961                  ioread32(&hw->reg->RX_MODE), mc_count);
1962 }
1963
1964 /**
1965  * pch_gbe_set_mac - Change the Ethernet Address of the NIC
1966  * @netdev: Network interface device structure
1967  * @addr:   Pointer to an address structure
1968  * Returns
1969  *      0:              Successfully
1970  *      -EADDRNOTAVAIL: Failed
1971  */
1972 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
1973 {
1974         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1975         struct sockaddr *skaddr = addr;
1976         int ret_val;
1977
1978         if (!is_valid_ether_addr(skaddr->sa_data)) {
1979                 ret_val = -EADDRNOTAVAIL;
1980         } else {
1981                 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
1982                 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
1983                 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1984                 ret_val = 0;
1985         }
1986         pr_debug("ret_val : 0x%08x\n", ret_val);
1987         pr_debug("dev_addr : %pM\n", netdev->dev_addr);
1988         pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
1989         pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
1990                  ioread32(&adapter->hw.reg->mac_adr[0].high),
1991                  ioread32(&adapter->hw.reg->mac_adr[0].low));
1992         return ret_val;
1993 }
1994
1995 /**
1996  * pch_gbe_change_mtu - Change the Maximum Transfer Unit
1997  * @netdev:   Network interface device structure
1998  * @new_mtu:  New value for maximum frame size
1999  * Returns
2000  *      0:              Successfully
2001  *      -EINVAL:        Failed
2002  */
2003 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2004 {
2005         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2006         int max_frame;
2007
2008         max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2009         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2010                 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2011                 pr_err("Invalid MTU setting\n");
2012                 return -EINVAL;
2013         }
2014         if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2015                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2016         else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2017                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2018         else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2019                 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2020         else
2021                 adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE;
2022         netdev->mtu = new_mtu;
2023         adapter->hw.mac.max_frame_size = max_frame;
2024
2025         if (netif_running(netdev))
2026                 pch_gbe_reinit_locked(adapter);
2027         else
2028                 pch_gbe_reset(adapter);
2029
2030         pr_debug("max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2031                  max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2032                  adapter->hw.mac.max_frame_size);
2033         return 0;
2034 }
2035
2036 /**
2037  * pch_gbe_set_features - Reset device after features changed
2038  * @netdev:   Network interface device structure
2039  * @features:  New features
2040  * Returns
2041  *      0:              HW state updated successfully
2042  */
2043 static int pch_gbe_set_features(struct net_device *netdev, u32 features)
2044 {
2045         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2046         u32 changed = features ^ netdev->features;
2047
2048         if (!(changed & NETIF_F_RXCSUM))
2049                 return 0;
2050
2051         if (netif_running(netdev))
2052                 pch_gbe_reinit_locked(adapter);
2053         else
2054                 pch_gbe_reset(adapter);
2055
2056         return 0;
2057 }
2058
2059 /**
2060  * pch_gbe_ioctl - Controls register through a MII interface
2061  * @netdev:   Network interface device structure
2062  * @ifr:      Pointer to ifr structure
2063  * @cmd:      Control command
2064  * Returns
2065  *      0:      Successfully
2066  *      Negative value: Failed
2067  */
2068 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2069 {
2070         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2071
2072         pr_debug("cmd : 0x%04x\n", cmd);
2073
2074         return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2075 }
2076
2077 /**
2078  * pch_gbe_tx_timeout - Respond to a Tx Hang
2079  * @netdev:   Network interface device structure
2080  */
2081 static void pch_gbe_tx_timeout(struct net_device *netdev)
2082 {
2083         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2084
2085         /* Do the reset outside of interrupt context */
2086         adapter->stats.tx_timeout_count++;
2087         schedule_work(&adapter->reset_task);
2088 }
2089
2090 /**
2091  * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2092  * @napi:    Pointer of polling device struct
2093  * @budget:  The maximum number of a packet
2094  * Returns
2095  *      false:  Exit the polling mode
2096  *      true:   Continue the polling mode
2097  */
2098 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2099 {
2100         struct pch_gbe_adapter *adapter =
2101             container_of(napi, struct pch_gbe_adapter, napi);
2102         struct net_device *netdev = adapter->netdev;
2103         int work_done = 0;
2104         bool poll_end_flag = false;
2105         bool cleaned = false;
2106
2107         pr_debug("budget : %d\n", budget);
2108
2109         /* Keep link state information with original netdev */
2110         if (!netif_carrier_ok(netdev)) {
2111                 poll_end_flag = true;
2112         } else {
2113                 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2114                 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2115
2116                 if (cleaned)
2117                         work_done = budget;
2118                 /* If no Tx and not enough Rx work done,
2119                  * exit the polling mode
2120                  */
2121                 if ((work_done < budget) || !netif_running(netdev))
2122                         poll_end_flag = true;
2123         }
2124
2125         if (poll_end_flag) {
2126                 napi_complete(napi);
2127                 pch_gbe_irq_enable(adapter);
2128         }
2129
2130         pr_debug("poll_end_flag : %d  work_done : %d  budget : %d\n",
2131                  poll_end_flag, work_done, budget);
2132
2133         return work_done;
2134 }
2135
2136 #ifdef CONFIG_NET_POLL_CONTROLLER
2137 /**
2138  * pch_gbe_netpoll - Used by things like netconsole to send skbs
2139  * @netdev:  Network interface device structure
2140  */
2141 static void pch_gbe_netpoll(struct net_device *netdev)
2142 {
2143         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2144
2145         disable_irq(adapter->pdev->irq);
2146         pch_gbe_intr(adapter->pdev->irq, netdev);
2147         enable_irq(adapter->pdev->irq);
2148 }
2149 #endif
2150
2151 static const struct net_device_ops pch_gbe_netdev_ops = {
2152         .ndo_open = pch_gbe_open,
2153         .ndo_stop = pch_gbe_stop,
2154         .ndo_start_xmit = pch_gbe_xmit_frame,
2155         .ndo_get_stats = pch_gbe_get_stats,
2156         .ndo_set_mac_address = pch_gbe_set_mac,
2157         .ndo_tx_timeout = pch_gbe_tx_timeout,
2158         .ndo_change_mtu = pch_gbe_change_mtu,
2159         .ndo_set_features = pch_gbe_set_features,
2160         .ndo_do_ioctl = pch_gbe_ioctl,
2161         .ndo_set_multicast_list = &pch_gbe_set_multi,
2162 #ifdef CONFIG_NET_POLL_CONTROLLER
2163         .ndo_poll_controller = pch_gbe_netpoll,
2164 #endif
2165 };
2166
2167 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2168                                                 pci_channel_state_t state)
2169 {
2170         struct net_device *netdev = pci_get_drvdata(pdev);
2171         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2172
2173         netif_device_detach(netdev);
2174         if (netif_running(netdev))
2175                 pch_gbe_down(adapter);
2176         pci_disable_device(pdev);
2177         /* Request a slot slot reset. */
2178         return PCI_ERS_RESULT_NEED_RESET;
2179 }
2180
2181 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2182 {
2183         struct net_device *netdev = pci_get_drvdata(pdev);
2184         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2185         struct pch_gbe_hw *hw = &adapter->hw;
2186
2187         if (pci_enable_device(pdev)) {
2188                 pr_err("Cannot re-enable PCI device after reset\n");
2189                 return PCI_ERS_RESULT_DISCONNECT;
2190         }
2191         pci_set_master(pdev);
2192         pci_enable_wake(pdev, PCI_D0, 0);
2193         pch_gbe_hal_power_up_phy(hw);
2194         pch_gbe_reset(adapter);
2195         /* Clear wake up status */
2196         pch_gbe_mac_set_wol_event(hw, 0);
2197
2198         return PCI_ERS_RESULT_RECOVERED;
2199 }
2200
2201 static void pch_gbe_io_resume(struct pci_dev *pdev)
2202 {
2203         struct net_device *netdev = pci_get_drvdata(pdev);
2204         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2205
2206         if (netif_running(netdev)) {
2207                 if (pch_gbe_up(adapter)) {
2208                         pr_debug("can't bring device back up after reset\n");
2209                         return;
2210                 }
2211         }
2212         netif_device_attach(netdev);
2213 }
2214
2215 static int __pch_gbe_suspend(struct pci_dev *pdev)
2216 {
2217         struct net_device *netdev = pci_get_drvdata(pdev);
2218         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2219         struct pch_gbe_hw *hw = &adapter->hw;
2220         u32 wufc = adapter->wake_up_evt;
2221         int retval = 0;
2222
2223         netif_device_detach(netdev);
2224         if (netif_running(netdev))
2225                 pch_gbe_down(adapter);
2226         if (wufc) {
2227                 pch_gbe_set_multi(netdev);
2228                 pch_gbe_setup_rctl(adapter);
2229                 pch_gbe_configure_rx(adapter);
2230                 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2231                                         hw->mac.link_duplex);
2232                 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2233                                         hw->mac.link_duplex);
2234                 pch_gbe_mac_set_wol_event(hw, wufc);
2235                 pci_disable_device(pdev);
2236         } else {
2237                 pch_gbe_hal_power_down_phy(hw);
2238                 pch_gbe_mac_set_wol_event(hw, wufc);
2239                 pci_disable_device(pdev);
2240         }
2241         return retval;
2242 }
2243
2244 #ifdef CONFIG_PM
2245 static int pch_gbe_suspend(struct device *device)
2246 {
2247         struct pci_dev *pdev = to_pci_dev(device);
2248
2249         return __pch_gbe_suspend(pdev);
2250 }
2251
2252 static int pch_gbe_resume(struct device *device)
2253 {
2254         struct pci_dev *pdev = to_pci_dev(device);
2255         struct net_device *netdev = pci_get_drvdata(pdev);
2256         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2257         struct pch_gbe_hw *hw = &adapter->hw;
2258         u32 err;
2259
2260         err = pci_enable_device(pdev);
2261         if (err) {
2262                 pr_err("Cannot enable PCI device from suspend\n");
2263                 return err;
2264         }
2265         pci_set_master(pdev);
2266         pch_gbe_hal_power_up_phy(hw);
2267         pch_gbe_reset(adapter);
2268         /* Clear wake on lan control and status */
2269         pch_gbe_mac_set_wol_event(hw, 0);
2270
2271         if (netif_running(netdev))
2272                 pch_gbe_up(adapter);
2273         netif_device_attach(netdev);
2274
2275         return 0;
2276 }
2277 #endif /* CONFIG_PM */
2278
2279 static void pch_gbe_shutdown(struct pci_dev *pdev)
2280 {
2281         __pch_gbe_suspend(pdev);
2282         if (system_state == SYSTEM_POWER_OFF) {
2283                 pci_wake_from_d3(pdev, true);
2284                 pci_set_power_state(pdev, PCI_D3hot);
2285         }
2286 }
2287
2288 static void pch_gbe_remove(struct pci_dev *pdev)
2289 {
2290         struct net_device *netdev = pci_get_drvdata(pdev);
2291         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2292
2293         cancel_work_sync(&adapter->reset_task);
2294         unregister_netdev(netdev);
2295
2296         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2297
2298         kfree(adapter->tx_ring);
2299         kfree(adapter->rx_ring);
2300
2301         iounmap(adapter->hw.reg);
2302         pci_release_regions(pdev);
2303         free_netdev(netdev);
2304         pci_disable_device(pdev);
2305 }
2306
2307 static int pch_gbe_probe(struct pci_dev *pdev,
2308                           const struct pci_device_id *pci_id)
2309 {
2310         struct net_device *netdev;
2311         struct pch_gbe_adapter *adapter;
2312         int ret;
2313
2314         ret = pci_enable_device(pdev);
2315         if (ret)
2316                 return ret;
2317
2318         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2319                 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2320                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2321                 if (ret) {
2322                         ret = pci_set_consistent_dma_mask(pdev,
2323                                                           DMA_BIT_MASK(32));
2324                         if (ret) {
2325                                 dev_err(&pdev->dev, "ERR: No usable DMA "
2326                                         "configuration, aborting\n");
2327                                 goto err_disable_device;
2328                         }
2329                 }
2330         }
2331
2332         ret = pci_request_regions(pdev, KBUILD_MODNAME);
2333         if (ret) {
2334                 dev_err(&pdev->dev,
2335                         "ERR: Can't reserve PCI I/O and memory resources\n");
2336                 goto err_disable_device;
2337         }
2338         pci_set_master(pdev);
2339
2340         netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2341         if (!netdev) {
2342                 ret = -ENOMEM;
2343                 dev_err(&pdev->dev,
2344                         "ERR: Can't allocate and set up an Ethernet device\n");
2345                 goto err_release_pci;
2346         }
2347         SET_NETDEV_DEV(netdev, &pdev->dev);
2348
2349         pci_set_drvdata(pdev, netdev);
2350         adapter = netdev_priv(netdev);
2351         adapter->netdev = netdev;
2352         adapter->pdev = pdev;
2353         adapter->hw.back = adapter;
2354         adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2355         if (!adapter->hw.reg) {
2356                 ret = -EIO;
2357                 dev_err(&pdev->dev, "Can't ioremap\n");
2358                 goto err_free_netdev;
2359         }
2360
2361         netdev->netdev_ops = &pch_gbe_netdev_ops;
2362         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2363         netif_napi_add(netdev, &adapter->napi,
2364                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2365         netdev->hw_features = NETIF_F_RXCSUM |
2366                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2367         netdev->features = netdev->hw_features;
2368         pch_gbe_set_ethtool_ops(netdev);
2369
2370         pch_gbe_mac_load_mac_addr(&adapter->hw);
2371         pch_gbe_mac_reset_hw(&adapter->hw);
2372
2373         /* setup the private structure */
2374         ret = pch_gbe_sw_init(adapter);
2375         if (ret)
2376                 goto err_iounmap;
2377
2378         /* Initialize PHY */
2379         ret = pch_gbe_init_phy(adapter);
2380         if (ret) {
2381                 dev_err(&pdev->dev, "PHY initialize error\n");
2382                 goto err_free_adapter;
2383         }
2384         pch_gbe_hal_get_bus_info(&adapter->hw);
2385
2386         /* Read the MAC address. and store to the private data */
2387         ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2388         if (ret) {
2389                 dev_err(&pdev->dev, "MAC address Read Error\n");
2390                 goto err_free_adapter;
2391         }
2392
2393         memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2394         if (!is_valid_ether_addr(netdev->dev_addr)) {
2395                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2396                 ret = -EIO;
2397                 goto err_free_adapter;
2398         }
2399         setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2400                     (unsigned long)adapter);
2401
2402         INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2403
2404         pch_gbe_check_options(adapter);
2405
2406         /* initialize the wol settings based on the eeprom settings */
2407         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2408         dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2409
2410         /* reset the hardware with the new settings */
2411         pch_gbe_reset(adapter);
2412
2413         ret = register_netdev(netdev);
2414         if (ret)
2415                 goto err_free_adapter;
2416         /* tell the stack to leave us alone until pch_gbe_open() is called */
2417         netif_carrier_off(netdev);
2418         netif_stop_queue(netdev);
2419
2420         dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2421
2422         device_set_wakeup_enable(&pdev->dev, 1);
2423         return 0;
2424
2425 err_free_adapter:
2426         pch_gbe_hal_phy_hw_reset(&adapter->hw);
2427         kfree(adapter->tx_ring);
2428         kfree(adapter->rx_ring);
2429 err_iounmap:
2430         iounmap(adapter->hw.reg);
2431 err_free_netdev:
2432         free_netdev(netdev);
2433 err_release_pci:
2434         pci_release_regions(pdev);
2435 err_disable_device:
2436         pci_disable_device(pdev);
2437         return ret;
2438 }
2439
2440 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2441         {.vendor = PCI_VENDOR_ID_INTEL,
2442          .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2443          .subvendor = PCI_ANY_ID,
2444          .subdevice = PCI_ANY_ID,
2445          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2446          .class_mask = (0xFFFF00)
2447          },
2448         {.vendor = PCI_VENDOR_ID_ROHM,
2449          .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2450          .subvendor = PCI_ANY_ID,
2451          .subdevice = PCI_ANY_ID,
2452          .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2453          .class_mask = (0xFFFF00)
2454          },
2455         /* required last entry */
2456         {0}
2457 };
2458
2459 #ifdef CONFIG_PM
2460 static const struct dev_pm_ops pch_gbe_pm_ops = {
2461         .suspend = pch_gbe_suspend,
2462         .resume = pch_gbe_resume,
2463         .freeze = pch_gbe_suspend,
2464         .thaw = pch_gbe_resume,
2465         .poweroff = pch_gbe_suspend,
2466         .restore = pch_gbe_resume,
2467 };
2468 #endif
2469
2470 static struct pci_error_handlers pch_gbe_err_handler = {
2471         .error_detected = pch_gbe_io_error_detected,
2472         .slot_reset = pch_gbe_io_slot_reset,
2473         .resume = pch_gbe_io_resume
2474 };
2475
2476 static struct pci_driver pch_gbe_driver = {
2477         .name = KBUILD_MODNAME,
2478         .id_table = pch_gbe_pcidev_id,
2479         .probe = pch_gbe_probe,
2480         .remove = pch_gbe_remove,
2481 #ifdef CONFIG_PM
2482         .driver.pm = &pch_gbe_pm_ops,
2483 #endif
2484         .shutdown = pch_gbe_shutdown,
2485         .err_handler = &pch_gbe_err_handler
2486 };
2487
2488
2489 static int __init pch_gbe_init_module(void)
2490 {
2491         int ret;
2492
2493         ret = pci_register_driver(&pch_gbe_driver);
2494         if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2495                 if (copybreak == 0) {
2496                         pr_info("copybreak disabled\n");
2497                 } else {
2498                         pr_info("copybreak enabled for packets <= %u bytes\n",
2499                                 copybreak);
2500                 }
2501         }
2502         return ret;
2503 }
2504
2505 static void __exit pch_gbe_exit_module(void)
2506 {
2507         pci_unregister_driver(&pch_gbe_driver);
2508 }
2509
2510 module_init(pch_gbe_init_module);
2511 module_exit(pch_gbe_exit_module);
2512
2513 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2514 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2515 MODULE_LICENSE("GPL");
2516 MODULE_VERSION(DRV_VERSION);
2517 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2518
2519 module_param(copybreak, uint, 0644);
2520 MODULE_PARM_DESC(copybreak,
2521         "Maximum size of packet that is copied to a new buffer on receive");
2522
2523 /* pch_gbe_main.c */