2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48 #include <linux/version.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
58 #include <asm/system.h>
60 #include <asm/byteorder.h>
61 #include <asm/uaccess.h>
62 #include <asm/pgtable.h>
64 #include "netxen_nic_hw.h"
66 #define _NETXEN_NIC_LINUX_MAJOR 3
67 #define _NETXEN_NIC_LINUX_MINOR 4
68 #define _NETXEN_NIC_LINUX_SUBVERSION 18
69 #define NETXEN_NIC_LINUX_VERSIONID "3.4.18"
71 #define NETXEN_NUM_FLASH_SECTORS (64)
72 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
73 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
74 * NETXEN_FLASH_SECTOR_SIZE)
76 #define PHAN_VENDOR_ID 0x4040
78 #define RCV_DESC_RINGSIZE \
79 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
80 #define STATUS_DESC_RINGSIZE \
81 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
82 #define LRO_DESC_RINGSIZE \
83 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
85 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
86 #define RCV_BUFFSIZE \
87 (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
90 #define NETXEN_NETDEV_STATUS 0x1
91 #define NETXEN_RCV_PRODUCER_OFFSET 0
92 #define NETXEN_RCV_PEG_DB_ID 2
93 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
94 #define FLASH_SUCCESS 0
96 #define ADDR_IN_WINDOW1(off) \
97 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
100 * normalize a 64MB crb address to 32MB PCI window
101 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
103 #define NETXEN_CRB_NORMAL(reg) \
104 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
106 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
107 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
109 #define DB_NORMALIZE(adapter, off) \
110 (adapter->ahw.db_base + (off))
112 #define NX_P2_C0 0x24
113 #define NX_P2_C1 0x25
114 #define NX_P3_A0 0x30
115 #define NX_P3_A2 0x30
116 #define NX_P3_B0 0x40
117 #define NX_P3_B1 0x41
119 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
120 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
122 #define FIRST_PAGE_GROUP_START 0
123 #define FIRST_PAGE_GROUP_END 0x100000
125 #define SECOND_PAGE_GROUP_START 0x6000000
126 #define SECOND_PAGE_GROUP_END 0x68BC000
128 #define THIRD_PAGE_GROUP_START 0x70E4000
129 #define THIRD_PAGE_GROUP_END 0x8000000
131 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
132 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
133 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
135 #define P2_MAX_MTU (8000)
136 #define P3_MAX_MTU (9600)
137 #define NX_ETHERMTU 1500
138 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
140 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
141 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
142 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
144 #define MAX_RX_BUFFER_LENGTH 1760
145 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
146 #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
147 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
148 #define RX_JUMBO_DMA_MAP_LEN \
149 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
150 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
153 * Maximum number of ring contexts
155 #define MAX_RING_CTX 1
157 /* Opcodes to be used with the commands */
158 #define TX_ETHER_PKT 0x01
159 #define TX_TCP_PKT 0x02
160 #define TX_UDP_PKT 0x03
161 #define TX_IP_PKT 0x04
162 #define TX_TCP_LSO 0x05
163 #define TX_TCP_LSO6 0x06
164 #define TX_IPSEC 0x07
165 #define TX_IPSEC_CMD 0x0a
166 #define TX_TCPV6_PKT 0x0b
167 #define TX_UDPV6_PKT 0x0c
169 /* The following opcodes are for internal consumption. */
170 #define NETXEN_CONTROL_OP 0x10
171 #define PEGNET_REQUEST 0x11
173 #define MAX_NUM_CARDS 4
175 #define MAX_BUFFERS_PER_CMD 32
178 * Following are the states of the Phantom. Phantom will set them and
179 * Host will read to check if the fields are correct.
181 #define PHAN_INITIALIZE_START 0xff00
182 #define PHAN_INITIALIZE_FAILED 0xffff
183 #define PHAN_INITIALIZE_COMPLETE 0xff01
185 /* Host writes the following to notify that it has done the init-handshake */
186 #define PHAN_INITIALIZE_ACK 0xf00f
188 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
190 /* descriptor types */
191 #define RCV_DESC_NORMAL 0x01
192 #define RCV_DESC_JUMBO 0x02
193 #define RCV_DESC_LRO 0x04
194 #define RCV_DESC_NORMAL_CTXID 0
195 #define RCV_DESC_JUMBO_CTXID 1
196 #define RCV_DESC_LRO_CTXID 2
198 #define RCV_DESC_TYPE(ID) \
199 ((ID == RCV_DESC_JUMBO_CTXID) \
201 : ((ID == RCV_DESC_LRO_CTXID) \
205 #define MAX_CMD_DESCRIPTORS 4096
206 #define MAX_RCV_DESCRIPTORS 16384
207 #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
208 #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
209 #define MAX_RCV_DESCRIPTORS_10G 8192
210 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
211 #define MAX_LRO_RCV_DESCRIPTORS 64
212 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
213 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
214 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
215 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
216 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
217 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
218 MAX_LRO_RCV_DESCRIPTORS)
219 #define MIN_TX_COUNT 4096
220 #define MIN_RX_COUNT 4096
221 #define NETXEN_CTX_SIGNATURE 0xdee0
222 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
223 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
225 #define PHAN_PEG_RCV_INITIALIZED 0xff01
226 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
228 #define get_next_index(index, length) \
229 (((index) + 1) & ((length) - 1))
231 #define get_index_range(index,length,count) \
232 (((index) + (count)) & ((length) - 1))
234 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
235 #define MPORT_MULTI_FUNCTION_MODE 0x2222
237 #include "netxen_nic_phan_reg.h"
240 * NetXen host-peg signal message structure
242 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
243 * Bit 2 : priv_id => must be 1
244 * Bit 3-17 : count => for doorbell
245 * Bit 18-27 : ctx_id => Context id
249 typedef u32 netxen_ctx_msg;
251 #define netxen_set_msg_peg_id(config_word, val) \
252 ((config_word) &= ~3, (config_word) |= val & 3)
253 #define netxen_set_msg_privid(config_word) \
254 ((config_word) |= 1 << 2)
255 #define netxen_set_msg_count(config_word, val) \
256 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
257 #define netxen_set_msg_ctxid(config_word, val) \
258 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
259 #define netxen_set_msg_opcode(config_word, val) \
260 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
262 struct netxen_rcv_context {
263 __le64 rcv_ring_addr;
264 __le32 rcv_ring_size;
268 struct netxen_ring_ctx {
270 /* one command ring */
271 __le64 cmd_consumer_offset;
272 __le64 cmd_ring_addr;
273 __le32 cmd_ring_size;
276 /* three receive rings */
277 struct netxen_rcv_context rcv_ctx[3];
279 /* one status ring */
280 __le64 sts_ring_addr;
281 __le32 sts_ring_size;
284 } __attribute__ ((aligned(64)));
287 * Following data structures describe the descriptors that will be used.
288 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
289 * we are doing LSO (above the 1500 size packet) only.
293 * The size of reference handle been changed to 16 bits to pass the MSS fields
297 #define FLAGS_CHECKSUM_ENABLED 0x01
298 #define FLAGS_LSO_ENABLED 0x02
299 #define FLAGS_IPSEC_SA_ADD 0x04
300 #define FLAGS_IPSEC_SA_DELETE 0x08
301 #define FLAGS_VLAN_TAGGED 0x10
303 #define netxen_set_cmd_desc_port(cmd_desc, var) \
304 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
305 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
306 ((cmd_desc)->port_ctxid |= ((var) & 0xF0))
308 #define netxen_set_cmd_desc_flags(cmd_desc, val) \
309 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
310 ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
311 #define netxen_set_cmd_desc_opcode(cmd_desc, val) \
312 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
313 ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
315 #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
316 (cmd_desc)->num_of_buffers_total_length = \
317 ((cmd_desc)->num_of_buffers_total_length & \
318 ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
319 #define netxen_set_cmd_desc_totallength(cmd_desc, val) \
320 (cmd_desc)->num_of_buffers_total_length = \
321 ((cmd_desc)->num_of_buffers_total_length & \
322 ~cpu_to_le32((u32)0xffffff << 8)) | \
323 cpu_to_le32(((val) & 0xffffff) << 8)
325 #define netxen_get_cmd_desc_opcode(cmd_desc) \
326 ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
327 #define netxen_get_cmd_desc_totallength(cmd_desc) \
328 ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
330 struct cmd_desc_type0 {
331 u8 tcp_hdr_offset; /* For LSO only */
332 u8 ip_hdr_offset; /* For LSO only */
333 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
335 /* Bit pattern: 0-7 total number of segments,
336 8-31 Total size of the packet */
337 __le32 num_of_buffers_total_length;
340 __le32 addr_low_part2;
341 __le32 addr_high_part2;
346 __le16 reference_handle; /* changed to u16 to add mss */
347 __le16 mss; /* passed by NDIS_PACKET for LSO */
348 /* Bit pattern 0-3 port, 0-3 ctx id */
350 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
351 __le16 conn_id; /* IPSec offoad only */
355 __le32 addr_low_part3;
356 __le32 addr_high_part3;
362 __le32 addr_low_part1;
363 __le32 addr_high_part1;
368 __le16 buffer1_length;
369 __le16 buffer2_length;
370 __le16 buffer3_length;
371 __le16 buffer4_length;
375 __le32 addr_low_part4;
376 __le32 addr_high_part4;
383 } __attribute__ ((aligned(64)));
385 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
387 __le16 reference_handle;
389 __le32 buffer_length; /* allocated buffer length (usually 2K) */
393 /* opcode field in status_desc */
394 #define RCV_NIC_PKT (0xA)
395 #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
397 /* for status field in status_desc */
398 #define STATUS_NEED_CKSUM (1)
399 #define STATUS_CKSUM_OK (2)
401 /* owner bits of status_desc */
402 #define STATUS_OWNER_HOST (0x1)
403 #define STATUS_OWNER_PHANTOM (0x2)
405 #define NETXEN_PROT_IP (1)
406 #define NETXEN_PROT_UNKNOWN (0)
408 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
410 #define netxen_get_sts_desc_lro_cnt(status_desc) \
411 ((status_desc)->lro & 0x7F)
412 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
413 (((status_desc)->lro & 0x80) >> 7)
415 #define netxen_get_sts_port(sts_data) \
417 #define netxen_get_sts_status(sts_data) \
418 (((sts_data) >> 4) & 0x0F)
419 #define netxen_get_sts_type(sts_data) \
420 (((sts_data) >> 8) & 0x0F)
421 #define netxen_get_sts_totallength(sts_data) \
422 (((sts_data) >> 12) & 0xFFFF)
423 #define netxen_get_sts_refhandle(sts_data) \
424 (((sts_data) >> 28) & 0xFFFF)
425 #define netxen_get_sts_prot(sts_data) \
426 (((sts_data) >> 44) & 0x0F)
427 #define netxen_get_sts_opcode(sts_data) \
428 (((sts_data) >> 58) & 0x03F)
430 #define netxen_get_sts_owner(status_desc) \
431 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
432 #define netxen_set_sts_owner(status_desc, val) { \
433 (status_desc)->status_desc_data = \
434 ((status_desc)->status_desc_data & \
435 ~cpu_to_le64(0x3ULL << 56)) | \
436 cpu_to_le64((u64)((val) & 0x3) << 56); \
440 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
441 28-43 reference_handle, 44-47 protocol, 48-52 unused
442 53-55 desc_cnt, 56-57 owner, 58-63 opcode
444 __le64 status_desc_data;
449 /* Bit pattern: 0-6 lro_count indicates frag sequence,
450 7 last_frag indicates last frag */
452 } __attribute__ ((aligned(16)));
455 NETXEN_RCV_PEG_0 = 0,
458 /* The version of the main data structure */
459 #define NETXEN_BDINFO_VERSION 1
461 /* Magic number to let user know flash is programmed */
462 #define NETXEN_BDINFO_MAGIC 0x12345678
464 /* Max number of Gig ports on a Phantom board */
465 #define NETXEN_MAX_PORTS 4
468 NETXEN_BRDTYPE_P1_BD = 0x0000,
469 NETXEN_BRDTYPE_P1_SB = 0x0001,
470 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
471 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
473 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
474 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
475 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
476 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
477 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
479 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
480 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
481 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
483 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
484 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
485 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
486 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
487 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
488 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
489 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
490 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
491 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
492 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
493 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032
498 NETXEN_BRDMFG_INVENTEC = 1
502 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
503 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
504 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
505 MEM_ORG_256Mbx4 = 0x3,
506 MEM_ORG_256Mbx8 = 0x4,
507 MEM_ORG_256Mbx16 = 0x5,
508 MEM_ORG_512Mbx4 = 0x6,
509 MEM_ORG_512Mbx8 = 0x7,
510 MEM_ORG_512Mbx16 = 0x8,
513 MEM_ORG_1Gbx16 = 0xb,
516 MEM_ORG_2Gbx16 = 0xe,
517 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
518 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
519 } netxen_mn_mem_org_t;
522 MEM_ORG_512Kx36 = 0x0,
525 } netxen_sn_mem_org_t;
530 MEM_DEPTH_16MB = 0x3,
531 MEM_DEPTH_32MB = 0x4,
532 MEM_DEPTH_64MB = 0x5,
533 MEM_DEPTH_128MB = 0x6,
534 MEM_DEPTH_256MB = 0x7,
535 MEM_DEPTH_512MB = 0x8,
540 MEM_DEPTH_16GB = 0xd,
542 } netxen_mem_depth_t;
544 struct netxen_board_info {
556 u32 port_mask; /* available niu ports */
557 u32 peg_mask; /* available pegs */
558 u32 icache_ok; /* can we run with icache? */
559 u32 dcache_ok; /* can we run with dcache? */
567 /* MN-related config */
568 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
569 u32 mn_sync_shift_cclk;
570 u32 mn_sync_shift_mclk;
572 u32 mn_crystal_freq; /* in MHz */
573 u32 mn_speed; /* in MHz */
576 u32 mn_ranks_0; /* ranks per slot */
577 u32 mn_ranks_1; /* ranks per slot */
588 u32 mn_mode_reg; /* MIU DDR Mode Register */
589 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
590 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
591 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
592 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
594 /* SN-related config */
595 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
596 u32 sn_pt_mode; /* pass through mode */
611 u32 magic; /* indicates flash has been initialized */
618 #define FLASH_NUM_PORTS (4)
620 struct netxen_flash_mac_addr {
624 struct netxen_user_old_info {
636 /* primary image status */
638 u32 secondary_present;
640 /* MAC address , 4 ports */
641 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
643 #define FLASH_NUM_MAC_PER_PORT 32
644 struct netxen_user_info {
645 u8 flash_md5[16 * 64];
652 /* primary image status */
654 u32 secondary_present;
656 /* MAC address , 4 ports, 32 address per port */
657 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
661 /* Any user defined data */
665 * Flash Layout - new format.
667 struct netxen_new_user_info {
668 u8 flash_md5[16 * 64];
675 /* primary image status */
677 u32 secondary_present;
679 /* MAC address , 4 ports, 32 address per port */
680 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
684 /* Any user defined data */
687 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
688 #define SECONDARY_IMAGE_ABSENT 0xffffffff
689 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
690 #define PRIMARY_IMAGE_BAD 0xffffffff
692 /* Flash memory map */
694 NETXEN_CRBINIT_START = 0, /* Crbinit section */
695 NETXEN_BRDCFG_START = 0x4000, /* board config */
696 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
697 NETXEN_BOOTLD_START = 0x10000, /* bootld */
698 NETXEN_IMAGE_START = 0x43000, /* compressed image */
699 NETXEN_SECONDARY_START = 0x200000, /* backup images */
700 NETXEN_PXE_START = 0x3E0000, /* user defined region */
701 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
702 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
703 } netxen_flash_map_t;
705 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
707 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
708 #define NETXEN_INIT_SECTOR (0)
709 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
710 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
711 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
712 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
713 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
714 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
715 #define NETXEN_NUM_CONFIG_SECTORS (1)
716 #define PFX "NetXen: "
717 extern char netxen_nic_driver_name[];
719 /* Note: Make sure to not call this before adapter->port is valid */
720 #if !defined(NETXEN_DEBUG)
721 #define DPRINTK(klevel, fmt, args...) do { \
724 #define DPRINTK(klevel, fmt, args...) do { \
725 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
726 (adapter != NULL && adapter->netdev != NULL) ? \
727 adapter->netdev->name : NULL, \
731 /* Number of status descriptors to handle per interrupt */
732 #define MAX_STATUS_HANDLE (128)
735 * netxen_skb_frag{} is to contain mapping info for each SG list. This
736 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
738 struct netxen_skb_frag {
743 #define _netxen_set_bits(config_word, start, bits, val) {\
744 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
745 unsigned long long __tvalue = (val); \
746 (config_word) &= ~__tmask; \
747 (config_word) |= (((__tvalue) << (start)) & __tmask); \
750 #define _netxen_clear_bits(config_word, start, bits) {\
751 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
752 (config_word) &= ~__tmask; \
755 /* Following defines are for the state of the buffers */
756 #define NETXEN_BUFFER_FREE 0
757 #define NETXEN_BUFFER_BUSY 1
760 * There will be one netxen_buffer per skb packet. These will be
761 * used to save the dma info for pci_unmap_page()
763 struct netxen_cmd_buffer {
765 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
771 unsigned long time_stamp;
775 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
776 struct netxen_rx_buffer {
781 u32 lro_expected_frags;
782 u32 lro_current_frags;
787 #define NETXEN_NIC_GBE 0x01
788 #define NETXEN_NIC_XGBE 0x02
791 * One hardware_context{} per adapter
792 * contains interrupt info as well shared hardware info.
794 struct netxen_hardware_context {
795 void __iomem *pci_base0;
796 void __iomem *pci_base1;
797 void __iomem *pci_base2;
798 unsigned long first_page_group_end;
799 unsigned long first_page_group_start;
800 void __iomem *db_base;
801 unsigned long db_len;
805 struct netxen_board_info boardcfg;
808 /* Address of cmd ring in Phantom */
809 struct cmd_desc_type0 *cmd_desc_head;
810 dma_addr_t cmd_desc_phys_addr;
811 struct netxen_adapter *adapter;
815 #define RCV_RING_LRO RCV_DESC_LRO
817 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
818 #define ETHERNET_FCS_SIZE 4
820 struct netxen_adapter_stats {
838 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
839 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
841 struct netxen_rcv_desc_ctx {
844 dma_addr_t phys_addr;
845 u32 crb_rcv_producer; /* reg offset */
846 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
847 u32 max_rx_desc_count;
850 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
855 * Receive context. There is one such structure per instance of the
856 * receive processing. Any state information that is relevant to
857 * the receive, and is must be in this structure. The global data may be
860 struct netxen_recv_context {
861 struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
862 u32 status_rx_consumer;
863 u32 crb_sts_consumer; /* reg offset */
864 dma_addr_t rcv_status_desc_phys_addr;
865 struct status_desc *rcv_status_desc_head;
868 #define NETXEN_NIC_MSI_ENABLED 0x02
869 #define NETXEN_DMA_MASK 0xfffffffe
870 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
872 struct netxen_dummy_dma {
874 dma_addr_t phys_addr;
877 struct netxen_adapter {
878 struct netxen_hardware_context ahw;
880 struct net_device *netdev;
881 struct pci_dev *pdev;
882 struct napi_struct napi;
883 struct net_device_stats net_stats;
884 unsigned char mac_addr[ETH_ALEN];
890 uint8_t max_mc_count;
892 struct work_struct watchdog_task;
893 struct timer_list watchdog_timer;
894 struct work_struct tx_timeout_task;
899 __le32 *cmd_consumer;
900 u32 last_cmd_consumer;
901 u32 crb_addr_cmd_producer;
902 u32 crb_addr_cmd_consumer;
904 u32 max_tx_desc_count;
905 u32 max_rx_desc_count;
906 u32 max_jumbo_rx_desc_count;
907 u32 max_lro_rx_desc_count;
914 struct netxen_adapter_stats stats;
923 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
926 * Receive instances. These can be either one per port,
927 * or one per peg, etc.
929 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
932 struct netxen_dummy_dma dummy_dma;
934 /* Context interface shared between card and host */
935 struct netxen_ring_ctx *ctx_desc;
936 dma_addr_t ctx_desc_phys_addr;
939 int (*enable_phy_interrupts) (struct netxen_adapter *);
940 int (*disable_phy_interrupts) (struct netxen_adapter *);
941 void (*handle_phy_intr) (struct netxen_adapter *);
942 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
943 int (*set_mtu) (struct netxen_adapter *, int);
944 int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
945 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
946 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
947 int (*init_port) (struct netxen_adapter *, int);
948 void (*init_niu) (struct netxen_adapter *);
949 int (*stop_port) (struct netxen_adapter *);
950 }; /* netxen_adapter structure */
953 * NetXen dma watchdog control structure
955 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
956 * Bit 1 : disable_request => 1 req disable dma watchdog
957 * Bit 2 : enable_request => 1 req enable dma watchdog
961 #define netxen_set_dma_watchdog_disable_req(config_word) \
962 _netxen_set_bits(config_word, 1, 1, 1)
963 #define netxen_set_dma_watchdog_enable_req(config_word) \
964 _netxen_set_bits(config_word, 2, 1, 1)
965 #define netxen_get_dma_watchdog_enabled(config_word) \
966 ((config_word) & 0x1)
967 #define netxen_get_dma_watchdog_disabled(config_word) \
968 (((config_word) >> 1) & 0x1)
970 /* Max number of xmit producer threads that can run simultaneously */
971 #define MAX_XMIT_PRODUCERS 16
973 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
974 ((adapter)->ahw.pci_base0 + (off))
975 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
976 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
977 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
978 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
980 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
983 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
984 return (adapter->ahw.pci_base0 + off);
985 } else if ((off < SECOND_PAGE_GROUP_END) &&
986 (off >= SECOND_PAGE_GROUP_START)) {
987 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
988 } else if ((off < THIRD_PAGE_GROUP_END) &&
989 (off >= THIRD_PAGE_GROUP_START)) {
990 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
995 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
998 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
999 return adapter->ahw.pci_base0;
1000 } else if ((off < SECOND_PAGE_GROUP_END) &&
1001 (off >= SECOND_PAGE_GROUP_START)) {
1002 return adapter->ahw.pci_base1;
1003 } else if ((off < THIRD_PAGE_GROUP_END) &&
1004 (off >= THIRD_PAGE_GROUP_START)) {
1005 return adapter->ahw.pci_base2;
1010 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1011 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1012 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1013 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1014 void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
1015 void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
1016 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1018 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1019 long reg, __u32 val);
1021 /* Functions available from netxen_nic_hw.c */
1022 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1023 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1024 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
1025 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
1026 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1027 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1028 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1029 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
1031 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1032 int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
1034 int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
1036 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1037 unsigned long off, int data);
1039 /* Functions from netxen_nic_init.c */
1040 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1041 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1042 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1043 int netxen_load_firmware(struct netxen_adapter *adapter);
1044 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1045 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1046 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1047 u8 *bytes, size_t size);
1048 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1049 u8 *bytes, size_t size);
1050 int netxen_flash_unlock(struct netxen_adapter *adapter);
1051 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1052 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1053 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1054 void netxen_halt_pegs(struct netxen_adapter *adapter);
1056 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1058 /* Functions from netxen_nic_isr.c */
1059 void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
1060 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1061 int netxen_init_firmware(struct netxen_adapter *adapter);
1062 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1063 void netxen_tso_check(struct netxen_adapter *adapter,
1064 struct cmd_desc_type0 *desc, struct sk_buff *skb);
1065 int netxen_nic_hw_resources(struct netxen_adapter *adapter);
1066 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1067 void netxen_watchdog_task(struct work_struct *work);
1068 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1070 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1071 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1072 void netxen_nic_set_multi(struct net_device *netdev);
1073 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1074 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1075 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1079 * NetXen Board information
1082 #define NETXEN_MAX_SHORT_NAME 32
1083 struct netxen_brdinfo {
1084 netxen_brdtype_t brdtype; /* type of board */
1085 long ports; /* max no of physical ports */
1086 char short_name[NETXEN_MAX_SHORT_NAME];
1089 static const struct netxen_brdinfo netxen_boards[] = {
1090 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1091 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1092 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1093 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1094 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1095 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1096 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1097 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1098 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1099 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1100 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1101 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1102 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1103 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1104 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "Quad GB - March Madness"},
1105 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1106 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1109 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1111 static inline void get_brd_name_by_type(u32 type, char *name)
1114 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1115 if (netxen_boards[i].brdtype == type) {
1116 strcpy(name, netxen_boards[i].short_name);
1127 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1131 /* check if already inactive */
1132 if (netxen_nic_hw_read_wx(adapter,
1133 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1134 printk(KERN_ERR "failed to read dma watchdog status\n");
1136 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1139 /* Send the disable request */
1140 netxen_set_dma_watchdog_disable_req(ctrl);
1141 netxen_crb_writelit_adapter(adapter,
1142 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1148 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1152 if (netxen_nic_hw_read_wx(adapter,
1153 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1154 printk(KERN_ERR "failed to read dma watchdog status\n");
1156 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1160 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1164 if (netxen_nic_hw_read_wx(adapter,
1165 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1166 printk(KERN_ERR "failed to read dma watchdog status\n");
1168 if (netxen_get_dma_watchdog_enabled(ctrl))
1171 /* send the wakeup request */
1172 netxen_set_dma_watchdog_enable_req(ctrl);
1174 netxen_crb_writelit_adapter(adapter,
1175 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1181 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1182 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]);
1183 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1184 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1187 extern struct ethtool_ops netxen_nic_ethtool_ops;
1189 #endif /* __NETXEN_NIC_H_ */