drivers/net/myri10ge/myri10ge.c

   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2009 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42
  43 #include <linux/tcp.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/string.h>
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/if_ether.h>
  52 #include <linux/if_vlan.h>
  53 #include <linux/inet_lro.h>
  54 #include <linux/dca.h>
  55 #include <linux/ip.h>
  56 #include <linux/inet.h>
  57 #include <linux/in.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/firmware.h>
  60 #include <linux/delay.h>
  61 #include <linux/timer.h>
  62 #include <linux/vmalloc.h>
  63 #include <linux/crc32.h>
  64 #include <linux/moduleparam.h>
  65 #include <linux/io.h>
  66 #include <linux/log2.h>
  67 #include <linux/slab.h>
  68 #include <linux/prefetch.h>
  69 #include <net/checksum.h>
  70 #include <net/ip.h>
  71 #include <net/tcp.h>
  72 #include <asm/byteorder.h>
  73 #include <asm/io.h>
  74 #include <asm/processor.h>
  75 #ifdef CONFIG_MTRR
  76 #include <asm/mtrr.h>
  77 #endif
  78
  79 #include "myri10ge_mcp.h"
  80 #include "myri10ge_mcp_gen_header.h"
  81
  82 #define MYRI10GE_VERSION_STR "1.5.2-1.459"
  83
  84 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  85 MODULE_AUTHOR("Maintainer: help@myri.com");
  86 MODULE_VERSION(MYRI10GE_VERSION_STR);
  87 MODULE_LICENSE("Dual BSD/GPL");
  88
  89 #define MYRI10GE_MAX_ETHER_MTU 9014
  90
  91 #define MYRI10GE_ETH_STOPPED 0
  92 #define MYRI10GE_ETH_STOPPING 1
  93 #define MYRI10GE_ETH_STARTING 2
  94 #define MYRI10GE_ETH_RUNNING 3
  95 #define MYRI10GE_ETH_OPEN_FAILED 4
  96
  97 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  98 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  99 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
 100 #define MYRI10GE_LRO_MAX_PKTS 64
 101
 102 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 103 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 104
 105 #define MYRI10GE_ALLOC_ORDER 0
 106 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 107 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 108
 109 #define MYRI10GE_MAX_SLICES 32
 110
 111 struct myri10ge_rx_buffer_state {
 112         struct page *page;
 113         int page_offset;
 114         DEFINE_DMA_UNMAP_ADDR(bus);
 115         DEFINE_DMA_UNMAP_LEN(len);
 116 };
 117
 118 struct myri10ge_tx_buffer_state {
 119         struct sk_buff *skb;
 120         int last;
 121         DEFINE_DMA_UNMAP_ADDR(bus);
 122         DEFINE_DMA_UNMAP_LEN(len);
 123 };
 124
 125 struct myri10ge_cmd {
 126         u32 data0;
 127         u32 data1;
 128         u32 data2;
 129 };
 130
 131 struct myri10ge_rx_buf {
 132         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 133         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 134         struct myri10ge_rx_buffer_state *info;
 135         struct page *page;
 136         dma_addr_t bus;
 137         int page_offset;
 138         int cnt;
 139         int fill_cnt;
 140         int alloc_fail;
 141         int mask;               /* number of rx slots -1 */
 142         int watchdog_needed;
 143 };
 144
 145 struct myri10ge_tx_buf {
 146         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 147         __be32 __iomem *send_go;        /* "go" doorbell ptr */
 148         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
 149         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 150         char *req_bytes;
 151         struct myri10ge_tx_buffer_state *info;
 152         int mask;               /* number of transmit slots -1  */
 153         int req ____cacheline_aligned;  /* transmit slots submitted     */
 154         int pkt_start;          /* packets started */
 155         int stop_queue;
 156         int linearized;
 157         int done ____cacheline_aligned; /* transmit slots completed     */
 158         int pkt_done;           /* packets completed */
 159         int wake_queue;
 160         int queue_active;
 161 };
 162
 163 struct myri10ge_rx_done {
 164         struct mcp_slot *entry;
 165         dma_addr_t bus;
 166         int cnt;
 167         int idx;
 168         struct net_lro_mgr lro_mgr;
 169         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 170 };
 171
 172 struct myri10ge_slice_netstats {
 173         unsigned long rx_packets;
 174         unsigned long tx_packets;
 175         unsigned long rx_bytes;
 176         unsigned long tx_bytes;
 177         unsigned long rx_dropped;
 178         unsigned long tx_dropped;
 179 };
 180
 181 struct myri10ge_slice_state {
 182         struct myri10ge_tx_buf tx;      /* transmit ring        */
 183         struct myri10ge_rx_buf rx_small;
 184         struct myri10ge_rx_buf rx_big;
 185         struct myri10ge_rx_done rx_done;
 186         struct net_device *dev;
 187         struct napi_struct napi;
 188         struct myri10ge_priv *mgp;
 189         struct myri10ge_slice_netstats stats;
 190         __be32 __iomem *irq_claim;
 191         struct mcp_irq_data *fw_stats;
 192         dma_addr_t fw_stats_bus;
 193         int watchdog_tx_done;
 194         int watchdog_tx_req;
 195         int watchdog_rx_done;
 196 #ifdef CONFIG_MYRI10GE_DCA
 197         int cached_dca_tag;
 198         int cpu;
 199         __be32 __iomem *dca_tag;
 200 #endif
 201         char irq_desc[32];
 202 };
 203
 204 struct myri10ge_priv {
 205         struct myri10ge_slice_state *ss;
 206         int tx_boundary;        /* boundary transmits cannot cross */
 207         int num_slices;
 208         int running;            /* running?             */
 209         int small_bytes;
 210         int big_bytes;
 211         int max_intr_slots;
 212         struct net_device *dev;
 213         spinlock_t stats_lock;
 214         u8 __iomem *sram;
 215         int sram_size;
 216         unsigned long board_span;
 217         unsigned long iomem_base;
 218         __be32 __iomem *irq_deassert;
 219         char *mac_addr_string;
 220         struct mcp_cmd_response *cmd;
 221         dma_addr_t cmd_bus;
 222         struct pci_dev *pdev;
 223         int msi_enabled;
 224         int msix_enabled;
 225         struct msix_entry *msix_vectors;
 226 #ifdef CONFIG_MYRI10GE_DCA
 227         int dca_enabled;
 228         int relaxed_order;
 229 #endif
 230         u32 link_state;
 231         unsigned int rdma_tags_available;
 232         int intr_coal_delay;
 233         __be32 __iomem *intr_coal_delay_ptr;
 234         int mtrr;
 235         int wc_enabled;
 236         int down_cnt;
 237         wait_queue_head_t down_wq;
 238         struct work_struct watchdog_work;
 239         struct timer_list watchdog_timer;
 240         int watchdog_resets;
 241         int watchdog_pause;
 242         int pause;
 243         bool fw_name_allocated;
 244         char *fw_name;
 245         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 246         char *product_code_string;
 247         char fw_version[128];
 248         int fw_ver_major;
 249         int fw_ver_minor;
 250         int fw_ver_tiny;
 251         int adopted_rx_filter_bug;
 252         u8 mac_addr[6];         /* eeprom mac address */
 253         unsigned long serial_number;
 254         int vendor_specific_offset;
 255         int fw_multicast_support;
 256         u32 features;
 257         u32 max_tso6;
 258         u32 read_dma;
 259         u32 write_dma;
 260         u32 read_write_dma;
 261         u32 link_changes;
 262         u32 msg_enable;
 263         unsigned int board_number;
 264         int rebooted;
 265 };
 266
 267 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 268 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 269 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 270 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 271 MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
 272 MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
 273 MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
 274 MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
 275
 276 /* Careful: must be accessed under kparam_block_sysfs_write */
 277 static char *myri10ge_fw_name = NULL;
 278 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 279 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 280
 281 #define MYRI10GE_MAX_BOARDS 8
 282 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
 283     {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
 284 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
 285                          0444);
 286 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
 287
 288 static int myri10ge_ecrc_enable = 1;
 289 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 290 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 291
 292 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 293 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 294 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 295
 296 static int myri10ge_msi = 1;    /* enable msi by default */
 297 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 298 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 299
 300 static int myri10ge_intr_coal_delay = 75;
 301 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 302 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 303
 304 static int myri10ge_flow_control = 1;
 305 module_param(myri10ge_flow_control, int, S_IRUGO);
 306 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 307
 308 static int myri10ge_deassert_wait = 1;
 309 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 310 MODULE_PARM_DESC(myri10ge_deassert_wait,
 311                  "Wait when deasserting legacy interrupts");
 312
 313 static int myri10ge_force_firmware = 0;
 314 module_param(myri10ge_force_firmware, int, S_IRUGO);
 315 MODULE_PARM_DESC(myri10ge_force_firmware,
 316                  "Force firmware to assume aligned completions");
 317
 318 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 319 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 320 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 321
 322 static int myri10ge_napi_weight = 64;
 323 module_param(myri10ge_napi_weight, int, S_IRUGO);
 324 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 325
 326 static int myri10ge_watchdog_timeout = 1;
 327 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 328 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 329
 330 static int myri10ge_max_irq_loops = 1048576;
 331 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 332 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 333                  "Set stuck legacy IRQ detection threshold");
 334
 335 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 336
 337 static int myri10ge_debug = -1; /* defaults above */
 338 module_param(myri10ge_debug, int, 0);
 339 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 340
 341 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 342 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 343 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 344                  "Number of LRO packets to be aggregated");
 345
 346 static int myri10ge_fill_thresh = 256;
 347 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 348 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 349
 350 static int myri10ge_reset_recover = 1;
 351
 352 static int myri10ge_max_slices = 1;
 353 module_param(myri10ge_max_slices, int, S_IRUGO);
 354 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 355
 356 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
 357 module_param(myri10ge_rss_hash, int, S_IRUGO);
 358 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 359
 360 static int myri10ge_dca = 1;
 361 module_param(myri10ge_dca, int, S_IRUGO);
 362 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 363
 364 #define MYRI10GE_FW_OFFSET 1024*1024
 365 #define MYRI10GE_HIGHPART_TO_U32(X) \
 366 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 367 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 368
 369 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 370
 371 static void myri10ge_set_multicast_list(struct net_device *dev);
 372 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
 373                                          struct net_device *dev);
 374
 375 static inline void put_be32(__be32 val, __be32 __iomem * p)
 376 {
 377         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 378 }
 379
 380 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
 381
 382 static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
 383 {
 384         if (mgp->fw_name_allocated)
 385                 kfree(mgp->fw_name);
 386         mgp->fw_name = name;
 387         mgp->fw_name_allocated = allocated;
 388 }
 389
 390 static int
 391 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 392                   struct myri10ge_cmd *data, int atomic)
 393 {
 394         struct mcp_cmd *buf;
 395         char buf_bytes[sizeof(*buf) + 8];
 396         struct mcp_cmd_response *response = mgp->cmd;
 397         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 398         u32 dma_low, dma_high, result, value;
 399         int sleep_total = 0;
 400
 401         /* ensure buf is aligned to 8 bytes */
 402         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 403
 404         buf->data0 = htonl(data->data0);
 405         buf->data1 = htonl(data->data1);
 406         buf->data2 = htonl(data->data2);
 407         buf->cmd = htonl(cmd);
 408         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 409         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 410
 411         buf->response_addr.low = htonl(dma_low);
 412         buf->response_addr.high = htonl(dma_high);
 413         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 414         mb();
 415         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 416
 417         /* wait up to 15ms. Longest command is the DMA benchmark,
 418          * which is capped at 5ms, but runs from a timeout handler
 419          * that runs every 7.8ms. So a 15ms timeout leaves us with
 420          * a 2.2ms margin
 421          */
 422         if (atomic) {
 423                 /* if atomic is set, do not sleep,
 424                  * and try to get the completion quickly
 425                  * (1ms will be enough for those commands) */
 426                 for (sleep_total = 0;
 427                      sleep_total < 1000 &&
 428                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 429                      sleep_total += 10) {
 430                         udelay(10);
 431                         mb();
 432                 }
 433         } else {
 434                 /* use msleep for most command */
 435                 for (sleep_total = 0;
 436                      sleep_total < 15 &&
 437                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 438                      sleep_total++)
 439                         msleep(1);
 440         }
 441
 442         result = ntohl(response->result);
 443         value = ntohl(response->data);
 444         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 445                 if (result == 0) {
 446                         data->data0 = value;
 447                         return 0;
 448                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 449                         return -ENOSYS;
 450                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 451                         return -E2BIG;
 452                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
 453                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
 454                            (data->
 455                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
 456                            0) {
 457                         return -ERANGE;
 458                 } else {
 459                         dev_err(&mgp->pdev->dev,
 460                                 "command %d failed, result = %d\n",
 461                                 cmd, result);
 462                         return -ENXIO;
 463                 }
 464         }
 465
 466         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 467                 cmd, result);
 468         return -EAGAIN;
 469 }
 470
 471 /*
 472  * The eeprom strings on the lanaiX have the format
 473  * SN=x\0
 474  * MAC=x:x:x:x:x:x\0
 475  * PT:ddd mmm xx xx:xx:xx xx\0
 476  * PV:ddd mmm xx xx:xx:xx xx\0
 477  */
 478 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 479 {
 480         char *ptr, *limit;
 481         int i;
 482
 483         ptr = mgp->eeprom_strings;
 484         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 485
 486         while (*ptr != '\0' && ptr < limit) {
 487                 if (memcmp(ptr, "MAC=", 4) == 0) {
 488                         ptr += 4;
 489                         mgp->mac_addr_string = ptr;
 490                         for (i = 0; i < 6; i++) {
 491                                 if ((ptr + 2) > limit)
 492                                         goto abort;
 493                                 mgp->mac_addr[i] =
 494                                     simple_strtoul(ptr, &ptr, 16);
 495                                 ptr += 1;
 496                         }
 497                 }
 498                 if (memcmp(ptr, "PC=", 3) == 0) {
 499                         ptr += 3;
 500                         mgp->product_code_string = ptr;
 501                 }
 502                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 503                         ptr += 3;
 504                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 505                 }
 506                 while (ptr < limit && *ptr++) ;
 507         }
 508
 509         return 0;
 510
 511 abort:
 512         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 513         return -ENXIO;
 514 }
 515
 516 /*
 517  * Enable or disable periodic RDMAs from the host to make certain
 518  * chipsets resend dropped PCIe messages
 519  */
 520
 521 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 522 {
 523         char __iomem *submit;
 524         __be32 buf[16] __attribute__ ((__aligned__(8)));
 525         u32 dma_low, dma_high;
 526         int i;
 527
 528         /* clear confirmation addr */
 529         mgp->cmd->data = 0;
 530         mb();
 531
 532         /* send a rdma command to the PCIe engine, and wait for the
 533          * response in the confirmation address.  The firmware should
 534          * write a -1 there to indicate it is alive and well
 535          */
 536         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 537         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 538
 539         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 540         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 541         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 542         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 543         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 544         buf[5] = htonl(enable); /* enable? */
 545
 546         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 547
 548         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 549         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 550                 msleep(1);
 551         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 552                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 553                         (enable ? "enable" : "disable"));
 554 }
 555
 556 static int
 557 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 558                            struct mcp_gen_header *hdr)
 559 {
 560         struct device *dev = &mgp->pdev->dev;
 561
 562         /* check firmware type */
 563         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 564                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 565                 return -EINVAL;
 566         }
 567
 568         /* save firmware version for ethtool */
 569         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 570
 571         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 572                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 573
 574         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
 575               mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 576                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 577                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 578                         MXGEFW_VERSION_MINOR);
 579                 return -EINVAL;
 580         }
 581         return 0;
 582 }
 583
 584 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 585 {
 586         unsigned crc, reread_crc;
 587         const struct firmware *fw;
 588         struct device *dev = &mgp->pdev->dev;
 589         unsigned char *fw_readback;
 590         struct mcp_gen_header *hdr;
 591         size_t hdr_offset;
 592         int status;
 593         unsigned i;
 594
 595         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 596                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 597                         mgp->fw_name);
 598                 status = -EINVAL;
 599                 goto abort_with_nothing;
 600         }
 601
 602         /* check size */
 603
 604         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 605             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 606                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 607                 status = -EINVAL;
 608                 goto abort_with_fw;
 609         }
 610
 611         /* check id */
 612         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 613         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 614                 dev_err(dev, "Bad firmware file\n");
 615                 status = -EINVAL;
 616                 goto abort_with_fw;
 617         }
 618         hdr = (void *)(fw->data + hdr_offset);
 619
 620         status = myri10ge_validate_firmware(mgp, hdr);
 621         if (status != 0)
 622                 goto abort_with_fw;
 623
 624         crc = crc32(~0, fw->data, fw->size);
 625         for (i = 0; i < fw->size; i += 256) {
 626                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 627                                   fw->data + i,
 628                                   min(256U, (unsigned)(fw->size - i)));
 629                 mb();
 630                 readb(mgp->sram);
 631         }
 632         fw_readback = vmalloc(fw->size);
 633         if (!fw_readback) {
 634                 status = -ENOMEM;
 635                 goto abort_with_fw;
 636         }
 637         /* corruption checking is good for parity recovery and buggy chipset */
 638         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 639         reread_crc = crc32(~0, fw_readback, fw->size);
 640         vfree(fw_readback);
 641         if (crc != reread_crc) {
 642                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 643                         (unsigned)fw->size, reread_crc, crc);
 644                 status = -EIO;
 645                 goto abort_with_fw;
 646         }
 647         *size = (u32) fw->size;
 648
 649 abort_with_fw:
 650         release_firmware(fw);
 651
 652 abort_with_nothing:
 653         return status;
 654 }
 655
 656 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 657 {
 658         struct mcp_gen_header *hdr;
 659         struct device *dev = &mgp->pdev->dev;
 660         const size_t bytes = sizeof(struct mcp_gen_header);
 661         size_t hdr_offset;
 662         int status;
 663
 664         /* find running firmware header */
 665         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 666
 667         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 668                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 669                         (int)hdr_offset);
 670                 return -EIO;
 671         }
 672
 673         /* copy header of running firmware from SRAM to host memory to
 674          * validate firmware */
 675         hdr = kmalloc(bytes, GFP_KERNEL);
 676         if (hdr == NULL) {
 677                 dev_err(dev, "could not malloc firmware hdr\n");
 678                 return -ENOMEM;
 679         }
 680         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 681         status = myri10ge_validate_firmware(mgp, hdr);
 682         kfree(hdr);
 683
 684         /* check to see if adopted firmware has bug where adopting
 685          * it will cause broadcasts to be filtered unless the NIC
 686          * is kept in ALLMULTI mode */
 687         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 688             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 689                 mgp->adopted_rx_filter_bug = 1;
 690                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 691                          "working around rx filter bug\n",
 692                          mgp->fw_ver_major, mgp->fw_ver_minor,
 693                          mgp->fw_ver_tiny);
 694         }
 695         return status;
 696 }
 697
 698 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 699 {
 700         struct myri10ge_cmd cmd;
 701         int status;
 702
 703         /* probe for IPv6 TSO support */
 704         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 705         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 706                                    &cmd, 0);
 707         if (status == 0) {
 708                 mgp->max_tso6 = cmd.data0;
 709                 mgp->features |= NETIF_F_TSO6;
 710         }
 711
 712         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 713         if (status != 0) {
 714                 dev_err(&mgp->pdev->dev,
 715                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 716                 return -ENXIO;
 717         }
 718
 719         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 720
 721         return 0;
 722 }
 723
 724 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 725 {
 726         char __iomem *submit;
 727         __be32 buf[16] __attribute__ ((__aligned__(8)));
 728         u32 dma_low, dma_high, size;
 729         int status, i;
 730
 731         size = 0;
 732         status = myri10ge_load_hotplug_firmware(mgp, &size);
 733         if (status) {
 734                 if (!adopt)
 735                         return status;
 736                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 737
 738                 /* Do not attempt to adopt firmware if there
 739                  * was a bad crc */
 740                 if (status == -EIO)
 741                         return status;
 742
 743                 status = myri10ge_adopt_running_firmware(mgp);
 744                 if (status != 0) {
 745                         dev_err(&mgp->pdev->dev,
 746                                 "failed to adopt running firmware\n");
 747                         return status;
 748                 }
 749                 dev_info(&mgp->pdev->dev,
 750                          "Successfully adopted running firmware\n");
 751                 if (mgp->tx_boundary == 4096) {
 752                         dev_warn(&mgp->pdev->dev,
 753                                  "Using firmware currently running on NIC"
 754                                  ".  For optimal\n");
 755                         dev_warn(&mgp->pdev->dev,
 756                                  "performance consider loading optimized "
 757                                  "firmware\n");
 758                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 759                 }
 760
 761                 set_fw_name(mgp, "adopted", false);
 762                 mgp->tx_boundary = 2048;
 763                 myri10ge_dummy_rdma(mgp, 1);
 764                 status = myri10ge_get_firmware_capabilities(mgp);
 765                 return status;
 766         }
 767
 768         /* clear confirmation addr */
 769         mgp->cmd->data = 0;
 770         mb();
 771
 772         /* send a reload command to the bootstrap MCP, and wait for the
 773          *  response in the confirmation address.  The firmware should
 774          * write a -1 there to indicate it is alive and well
 775          */
 776         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 777         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 778
 779         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 780         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 781         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 782
 783         /* FIX: All newest firmware should un-protect the bottom of
 784          * the sram before handoff. However, the very first interfaces
 785          * do not. Therefore the handoff copy must skip the first 8 bytes
 786          */
 787         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 788         buf[4] = htonl(size - 8);       /* length of code */
 789         buf[5] = htonl(8);      /* where to copy to */
 790         buf[6] = htonl(0);      /* where to jump to */
 791
 792         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 793
 794         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 795         mb();
 796         msleep(1);
 797         mb();
 798         i = 0;
 799         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 800                 msleep(1 << i);
 801                 i++;
 802         }
 803         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 804                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 805                 return -ENXIO;
 806         }
 807         myri10ge_dummy_rdma(mgp, 1);
 808         status = myri10ge_get_firmware_capabilities(mgp);
 809
 810         return status;
 811 }
 812
 813 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 814 {
 815         struct myri10ge_cmd cmd;
 816         int status;
 817
 818         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 819                      | (addr[2] << 8) | addr[3]);
 820
 821         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 822
 823         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 824         return status;
 825 }
 826
 827 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 828 {
 829         struct myri10ge_cmd cmd;
 830         int status, ctl;
 831
 832         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 833         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 834
 835         if (status) {
 836                 netdev_err(mgp->dev, "Failed to set flow control mode\n");
 837                 return status;
 838         }
 839         mgp->pause = pause;
 840         return 0;
 841 }
 842
 843 static void
 844 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 845 {
 846         struct myri10ge_cmd cmd;
 847         int status, ctl;
 848
 849         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 850         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 851         if (status)
 852                 netdev_err(mgp->dev, "Failed to set promisc mode\n");
 853 }
 854
 855 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 856 {
 857         struct myri10ge_cmd cmd;
 858         int status;
 859         u32 len;
 860         struct page *dmatest_page;
 861         dma_addr_t dmatest_bus;
 862         char *test = " ";
 863
 864         dmatest_page = alloc_page(GFP_KERNEL);
 865         if (!dmatest_page)
 866                 return -ENOMEM;
 867         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 868                                    DMA_BIDIRECTIONAL);
 869
 870         /* Run a small DMA test.
 871          * The magic multipliers to the length tell the firmware
 872          * to do DMA read, write, or read+write tests.  The
 873          * results are returned in cmd.data0.  The upper 16
 874          * bits or the return is the number of transfers completed.
 875          * The lower 16 bits is the time in 0.5us ticks that the
 876          * transfers took to complete.
 877          */
 878
 879         len = mgp->tx_boundary;
 880
 881         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 882         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 883         cmd.data2 = len * 0x10000;
 884         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 885         if (status != 0) {
 886                 test = "read";
 887                 goto abort;
 888         }
 889         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 890         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 891         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 892         cmd.data2 = len * 0x1;
 893         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 894         if (status != 0) {
 895                 test = "write";
 896                 goto abort;
 897         }
 898         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 899
 900         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 901         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 902         cmd.data2 = len * 0x10001;
 903         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 904         if (status != 0) {
 905                 test = "read/write";
 906                 goto abort;
 907         }
 908         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 909             (cmd.data0 & 0xffff);
 910
 911 abort:
 912         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 913         put_page(dmatest_page);
 914
 915         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 916                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 917                          test, status);
 918
 919         return status;
 920 }
 921
 922 static int myri10ge_reset(struct myri10ge_priv *mgp)
 923 {
 924         struct myri10ge_cmd cmd;
 925         struct myri10ge_slice_state *ss;
 926         int i, status;
 927         size_t bytes;
 928 #ifdef CONFIG_MYRI10GE_DCA
 929         unsigned long dca_tag_off;
 930 #endif
 931
 932         /* try to send a reset command to the card to see if it
 933          * is alive */
 934         memset(&cmd, 0, sizeof(cmd));
 935         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 936         if (status != 0) {
 937                 dev_err(&mgp->pdev->dev, "failed reset\n");
 938                 return -ENXIO;
 939         }
 940
 941         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 942         /*
 943          * Use non-ndis mcp_slot (eg, 4 bytes total,
 944          * no toeplitz hash value returned.  Older firmware will
 945          * not understand this command, but will use the correct
 946          * sized mcp_slot, so we ignore error returns
 947          */
 948         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 949         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 950
 951         /* Now exchange information about interrupts  */
 952
 953         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 954         cmd.data0 = (u32) bytes;
 955         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 956
 957         /*
 958          * Even though we already know how many slices are supported
 959          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 960          * has magic side effects, and must be called after a reset.
 961          * It must be called prior to calling any RSS related cmds,
 962          * including assigning an interrupt queue for anything but
 963          * slice 0.  It must also be called *after*
 964          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 965          * the firmware to compute offsets.
 966          */
 967
 968         if (mgp->num_slices > 1) {
 969
 970                 /* ask the maximum number of slices it supports */
 971                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 972                                            &cmd, 0);
 973                 if (status != 0) {
 974                         dev_err(&mgp->pdev->dev,
 975                                 "failed to get number of slices\n");
 976                 }
 977
 978                 /*
 979                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 980                  * to setting up the interrupt queue DMA
 981                  */
 982
 983                 cmd.data0 = mgp->num_slices;
 984                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 985                 if (mgp->dev->real_num_tx_queues > 1)
 986                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
 987                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 988                                            &cmd, 0);
 989
 990                 /* Firmware older than 1.4.32 only supports multiple
 991                  * RX queues, so if we get an error, first retry using a
 992                  * single TX queue before giving up */
 993                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
 994                         netif_set_real_num_tx_queues(mgp->dev, 1);
 995                         cmd.data0 = mgp->num_slices;
 996                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 997                         status = myri10ge_send_cmd(mgp,
 998                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
 999                                                    &cmd, 0);
1000                 }
1001
1002                 if (status != 0) {
1003                         dev_err(&mgp->pdev->dev,
1004                                 "failed to set number of slices\n");
1005
1006                         return status;
1007                 }
1008         }
1009         for (i = 0; i < mgp->num_slices; i++) {
1010                 ss = &mgp->ss[i];
1011                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1012                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1013                 cmd.data2 = i;
1014                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1015                                             &cmd, 0);
1016         };
1017
1018         status |=
1019             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1020         for (i = 0; i < mgp->num_slices; i++) {
1021                 ss = &mgp->ss[i];
1022                 ss->irq_claim =
1023                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1024         }
1025         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1026                                     &cmd, 0);
1027         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1028
1029         status |= myri10ge_send_cmd
1030             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1031         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1032         if (status != 0) {
1033                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1034                 return status;
1035         }
1036         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1037
1038 #ifdef CONFIG_MYRI10GE_DCA
1039         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1040         dca_tag_off = cmd.data0;
1041         for (i = 0; i < mgp->num_slices; i++) {
1042                 ss = &mgp->ss[i];
1043                 if (status == 0) {
1044                         ss->dca_tag = (__iomem __be32 *)
1045                             (mgp->sram + dca_tag_off + 4 * i);
1046                 } else {
1047                         ss->dca_tag = NULL;
1048                 }
1049         }
1050 #endif                          /* CONFIG_MYRI10GE_DCA */
1051
1052         /* reset mcp/driver shared state back to 0 */
1053
1054         mgp->link_changes = 0;
1055         for (i = 0; i < mgp->num_slices; i++) {
1056                 ss = &mgp->ss[i];
1057
1058                 memset(ss->rx_done.entry, 0, bytes);
1059                 ss->tx.req = 0;
1060                 ss->tx.done = 0;
1061                 ss->tx.pkt_start = 0;
1062                 ss->tx.pkt_done = 0;
1063                 ss->rx_big.cnt = 0;
1064                 ss->rx_small.cnt = 0;
1065                 ss->rx_done.idx = 0;
1066                 ss->rx_done.cnt = 0;
1067                 ss->tx.wake_queue = 0;
1068                 ss->tx.stop_queue = 0;
1069         }
1070
1071         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1072         myri10ge_change_pause(mgp, mgp->pause);
1073         myri10ge_set_multicast_list(mgp->dev);
1074         return status;
1075 }
1076
1077 #ifdef CONFIG_MYRI10GE_DCA
1078 static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1079 {
1080         int ret, cap, err;
1081         u16 ctl;
1082
1083         cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1084         if (!cap)
1085                 return 0;
1086
1087         err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1088         ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1089         if (ret != on) {
1090                 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1091                 ctl |= (on << 4);
1092                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1093         }
1094         return ret;
1095 }
1096
1097 static void
1098 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1099 {
1100         ss->cached_dca_tag = tag;
1101         put_be32(htonl(tag), ss->dca_tag);
1102 }
1103
1104 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1105 {
1106         int cpu = get_cpu();
1107         int tag;
1108
1109         if (cpu != ss->cpu) {
1110                 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
1111                 if (ss->cached_dca_tag != tag)
1112                         myri10ge_write_dca(ss, cpu, tag);
1113                 ss->cpu = cpu;
1114         }
1115         put_cpu();
1116 }
1117
1118 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1119 {
1120         int err, i;
1121         struct pci_dev *pdev = mgp->pdev;
1122
1123         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1124                 return;
1125         if (!myri10ge_dca) {
1126                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1127                 return;
1128         }
1129         err = dca_add_requester(&pdev->dev);
1130         if (err) {
1131                 if (err != -ENODEV)
1132                         dev_err(&pdev->dev,
1133                                 "dca_add_requester() failed, err=%d\n", err);
1134                 return;
1135         }
1136         mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
1137         mgp->dca_enabled = 1;
1138         for (i = 0; i < mgp->num_slices; i++) {
1139                 mgp->ss[i].cpu = -1;
1140                 mgp->ss[i].cached_dca_tag = -1;
1141                 myri10ge_update_dca(&mgp->ss[i]);
1142          }
1143 }
1144
1145 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1146 {
1147         struct pci_dev *pdev = mgp->pdev;
1148         int err;
1149
1150         if (!mgp->dca_enabled)
1151                 return;
1152         mgp->dca_enabled = 0;
1153         if (mgp->relaxed_order)
1154                 myri10ge_toggle_relaxed(pdev, 1);
1155         err = dca_remove_requester(&pdev->dev);
1156 }
1157
1158 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1159 {
1160         struct myri10ge_priv *mgp;
1161         unsigned long event;
1162
1163         mgp = dev_get_drvdata(dev);
1164         event = *(unsigned long *)data;
1165
1166         if (event == DCA_PROVIDER_ADD)
1167                 myri10ge_setup_dca(mgp);
1168         else if (event == DCA_PROVIDER_REMOVE)
1169                 myri10ge_teardown_dca(mgp);
1170         return 0;
1171 }
1172 #endif                          /* CONFIG_MYRI10GE_DCA */
1173
1174 static inline void
1175 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1176                     struct mcp_kreq_ether_recv *src)
1177 {
1178         __be32 low;
1179
1180         low = src->addr_low;
1181         src->addr_low = htonl(DMA_BIT_MASK(32));
1182         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1183         mb();
1184         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1185         mb();
1186         src->addr_low = low;
1187         put_be32(low, &dst->addr_low);
1188         mb();
1189 }
1190
1191 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1192 {
1193         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1194
1195         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1196             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1197              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1198                 skb->csum = hw_csum;
1199                 skb->ip_summed = CHECKSUM_COMPLETE;
1200         }
1201 }
1202
1203 static inline void
1204 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1205                       struct skb_frag_struct *rx_frags, int len, int hlen)
1206 {
1207         struct skb_frag_struct *skb_frags;
1208
1209         skb->len = skb->data_len = len;
1210         skb->truesize = len + sizeof(struct sk_buff);
1211         /* attach the page(s) */
1212
1213         skb_frags = skb_shinfo(skb)->frags;
1214         while (len > 0) {
1215                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1216                 len -= rx_frags->size;
1217                 skb_frags++;
1218                 rx_frags++;
1219                 skb_shinfo(skb)->nr_frags++;
1220         }
1221
1222         /* pskb_may_pull is not available in irq context, but
1223          * skb_pull() (for ether_pad and eth_type_trans()) requires
1224          * the beginning of the packet in skb_headlen(), move it
1225          * manually */
1226         skb_copy_to_linear_data(skb, va, hlen);
1227         skb_shinfo(skb)->frags[0].page_offset += hlen;
1228         skb_shinfo(skb)->frags[0].size -= hlen;
1229         skb->data_len -= hlen;
1230         skb->tail += hlen;
1231         skb_pull(skb, MXGEFW_PAD);
1232 }
1233
1234 static void
1235 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1236                         int bytes, int watchdog)
1237 {
1238         struct page *page;
1239         int idx;
1240 #if MYRI10GE_ALLOC_SIZE > 4096
1241         int end_offset;
1242 #endif
1243
1244         if (unlikely(rx->watchdog_needed && !watchdog))
1245                 return;
1246
1247         /* try to refill entire ring */
1248         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1249                 idx = rx->fill_cnt & rx->mask;
1250                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1251                         /* we can use part of previous page */
1252                         get_page(rx->page);
1253                 } else {
1254                         /* we need a new page */
1255                         page =
1256                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1257                                         MYRI10GE_ALLOC_ORDER);
1258                         if (unlikely(page == NULL)) {
1259                                 if (rx->fill_cnt - rx->cnt < 16)
1260                                         rx->watchdog_needed = 1;
1261                                 return;
1262                         }
1263                         rx->page = page;
1264                         rx->page_offset = 0;
1265                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1266                                                MYRI10GE_ALLOC_SIZE,
1267                                                PCI_DMA_FROMDEVICE);
1268                 }
1269                 rx->info[idx].page = rx->page;
1270                 rx->info[idx].page_offset = rx->page_offset;
1271                 /* note that this is the address of the start of the
1272                  * page */
1273                 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1274                 rx->shadow[idx].addr_low =
1275                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1276                 rx->shadow[idx].addr_high =
1277                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1278
1279                 /* start next packet on a cacheline boundary */
1280                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1281
1282 #if MYRI10GE_ALLOC_SIZE > 4096
1283                 /* don't cross a 4KB boundary */
1284                 end_offset = rx->page_offset + bytes - 1;
1285                 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1286                         rx->page_offset = end_offset & ~4095;
1287 #endif
1288                 rx->fill_cnt++;
1289
1290                 /* copy 8 descriptors to the firmware at a time */
1291                 if ((idx & 7) == 7) {
1292                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1293                                             &rx->shadow[idx - 7]);
1294                 }
1295         }
1296 }
1297
1298 static inline void
1299 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1300                        struct myri10ge_rx_buffer_state *info, int bytes)
1301 {
1302         /* unmap the recvd page if we're the only or last user of it */
1303         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1304             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1305                 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
1306                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1307                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1308         }
1309 }
1310
1311 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1312                                  * page into an skb */
1313
1314 static inline int
1315 myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
1316                  int lro_enabled)
1317 {
1318         struct myri10ge_priv *mgp = ss->mgp;
1319         struct sk_buff *skb;
1320         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1321         struct myri10ge_rx_buf *rx;
1322         int i, idx, hlen, remainder, bytes;
1323         struct pci_dev *pdev = mgp->pdev;
1324         struct net_device *dev = mgp->dev;
1325         u8 *va;
1326
1327         if (len <= mgp->small_bytes) {
1328                 rx = &ss->rx_small;
1329                 bytes = mgp->small_bytes;
1330         } else {
1331                 rx = &ss->rx_big;
1332                 bytes = mgp->big_bytes;
1333         }
1334
1335         len += MXGEFW_PAD;
1336         idx = rx->cnt & rx->mask;
1337         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1338         prefetch(va);
1339         /* Fill skb_frag_struct(s) with data from our receive */
1340         for (i = 0, remainder = len; remainder > 0; i++) {
1341                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1342                 rx_frags[i].page = rx->info[idx].page;
1343                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1344                 if (remainder < MYRI10GE_ALLOC_SIZE)
1345                         rx_frags[i].size = remainder;
1346                 else
1347                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1348                 rx->cnt++;
1349                 idx = rx->cnt & rx->mask;
1350                 remainder -= MYRI10GE_ALLOC_SIZE;
1351         }
1352
1353         if (lro_enabled) {
1354                 rx_frags[0].page_offset += MXGEFW_PAD;
1355                 rx_frags[0].size -= MXGEFW_PAD;
1356                 len -= MXGEFW_PAD;
1357                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1358                                   /* opaque, will come back in get_frag_header */
1359                                   len, len,
1360                                   (void *)(__force unsigned long)csum, csum);
1361
1362                 return 1;
1363         }
1364
1365         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1366
1367         /* allocate an skb to attach the page(s) to. This is done
1368          * after trying LRO, so as to avoid skb allocation overheads */
1369
1370         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1371         if (unlikely(skb == NULL)) {
1372                 ss->stats.rx_dropped++;
1373                 do {
1374                         i--;
1375                         put_page(rx_frags[i].page);
1376                 } while (i != 0);
1377                 return 0;
1378         }
1379
1380         /* Attach the pages to the skb, and trim off any padding */
1381         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1382         if (skb_shinfo(skb)->frags[0].size <= 0) {
1383                 put_page(skb_shinfo(skb)->frags[0].page);
1384                 skb_shinfo(skb)->nr_frags = 0;
1385         }
1386         skb->protocol = eth_type_trans(skb, dev);
1387         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1388
1389         if (dev->features & NETIF_F_RXCSUM) {
1390                 if ((skb->protocol == htons(ETH_P_IP)) ||
1391                     (skb->protocol == htons(ETH_P_IPV6))) {
1392                         skb->csum = csum;
1393                         skb->ip_summed = CHECKSUM_COMPLETE;
1394                 } else
1395                         myri10ge_vlan_ip_csum(skb, csum);
1396         }
1397         netif_receive_skb(skb);
1398         return 1;
1399 }
1400
1401 static inline void
1402 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1403 {
1404         struct pci_dev *pdev = ss->mgp->pdev;
1405         struct myri10ge_tx_buf *tx = &ss->tx;
1406         struct netdev_queue *dev_queue;
1407         struct sk_buff *skb;
1408         int idx, len;
1409
1410         while (tx->pkt_done != mcp_index) {
1411                 idx = tx->done & tx->mask;
1412                 skb = tx->info[idx].skb;
1413
1414                 /* Mark as free */
1415                 tx->info[idx].skb = NULL;
1416                 if (tx->info[idx].last) {
1417                         tx->pkt_done++;
1418                         tx->info[idx].last = 0;
1419                 }
1420                 tx->done++;
1421                 len = dma_unmap_len(&tx->info[idx], len);
1422                 dma_unmap_len_set(&tx->info[idx], len, 0);
1423                 if (skb) {
1424                         ss->stats.tx_bytes += skb->len;
1425                         ss->stats.tx_packets++;
1426                         dev_kfree_skb_irq(skb);
1427                         if (len)
1428                                 pci_unmap_single(pdev,
1429                                                  dma_unmap_addr(&tx->info[idx],
1430                                                                 bus), len,
1431                                                  PCI_DMA_TODEVICE);
1432                 } else {
1433                         if (len)
1434                                 pci_unmap_page(pdev,
1435                                                dma_unmap_addr(&tx->info[idx],
1436                                                               bus), len,
1437                                                PCI_DMA_TODEVICE);
1438                 }
1439         }
1440
1441         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1442         /*
1443          * Make a minimal effort to prevent the NIC from polling an
1444          * idle tx queue.  If we can't get the lock we leave the queue
1445          * active. In this case, either a thread was about to start
1446          * using the queue anyway, or we lost a race and the NIC will
1447          * waste some of its resources polling an inactive queue for a
1448          * while.
1449          */
1450
1451         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1452             __netif_tx_trylock(dev_queue)) {
1453                 if (tx->req == tx->done) {
1454                         tx->queue_active = 0;
1455                         put_be32(htonl(1), tx->send_stop);
1456                         mb();
1457                         mmiowb();
1458                 }
1459                 __netif_tx_unlock(dev_queue);
1460         }
1461
1462         /* start the queue if we've stopped it */
1463         if (netif_tx_queue_stopped(dev_queue) &&
1464             tx->req - tx->done < (tx->mask >> 1)) {
1465                 tx->wake_queue++;
1466                 netif_tx_wake_queue(dev_queue);
1467         }
1468 }
1469
1470 static inline int
1471 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1472 {
1473         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1474         struct myri10ge_priv *mgp = ss->mgp;
1475
1476         unsigned long rx_bytes = 0;
1477         unsigned long rx_packets = 0;
1478         unsigned long rx_ok;
1479
1480         int idx = rx_done->idx;
1481         int cnt = rx_done->cnt;
1482         int work_done = 0;
1483         u16 length;
1484         __wsum checksum;
1485
1486         /*
1487          * Prevent compiler from generating more than one ->features memory
1488          * access to avoid theoretical race condition with functions that
1489          * change NETIF_F_LRO flag at runtime.
1490          */
1491         bool lro_enabled = ACCESS_ONCE(mgp->dev->features) & NETIF_F_LRO;
1492
1493         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1494                 length = ntohs(rx_done->entry[idx].length);
1495                 rx_done->entry[idx].length = 0;
1496                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1497                 rx_ok = myri10ge_rx_done(ss, length, checksum, lro_enabled);
1498                 rx_packets += rx_ok;
1499                 rx_bytes += rx_ok * (unsigned long)length;
1500                 cnt++;
1501                 idx = cnt & (mgp->max_intr_slots - 1);
1502                 work_done++;
1503         }
1504         rx_done->idx = idx;
1505         rx_done->cnt = cnt;
1506         ss->stats.rx_packets += rx_packets;
1507         ss->stats.rx_bytes += rx_bytes;
1508
1509         if (lro_enabled)
1510                 lro_flush_all(&rx_done->lro_mgr);
1511
1512         /* restock receive rings if needed */
1513         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1514                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1515                                         mgp->small_bytes + MXGEFW_PAD, 0);
1516         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1517                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1518
1519         return work_done;
1520 }
1521
1522 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1523 {
1524         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1525
1526         if (unlikely(stats->stats_updated)) {
1527                 unsigned link_up = ntohl(stats->link_up);
1528                 if (mgp->link_state != link_up) {
1529                         mgp->link_state = link_up;
1530
1531                         if (mgp->link_state == MXGEFW_LINK_UP) {
1532                                 if (netif_msg_link(mgp))
1533                                         netdev_info(mgp->dev, "link up\n");
1534                                 netif_carrier_on(mgp->dev);
1535                                 mgp->link_changes++;
1536                         } else {
1537                                 if (netif_msg_link(mgp))
1538                                         netdev_info(mgp->dev, "link %s\n",
1539                                             link_up == MXGEFW_LINK_MYRINET ?
1540                                             "mismatch (Myrinet detected)" :
1541                                             "down");
1542                                 netif_carrier_off(mgp->dev);
1543                                 mgp->link_changes++;
1544                         }
1545                 }
1546                 if (mgp->rdma_tags_available !=
1547                     ntohl(stats->rdma_tags_available)) {
1548                         mgp->rdma_tags_available =
1549                             ntohl(stats->rdma_tags_available);
1550                         netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1551                                     mgp->rdma_tags_available);
1552                 }
1553                 mgp->down_cnt += stats->link_down;
1554                 if (stats->link_down)
1555                         wake_up(&mgp->down_wq);
1556         }
1557 }
1558
1559 static int myri10ge_poll(struct napi_struct *napi, int budget)
1560 {
1561         struct myri10ge_slice_state *ss =
1562             container_of(napi, struct myri10ge_slice_state, napi);
1563         int work_done;
1564
1565 #ifdef CONFIG_MYRI10GE_DCA
1566         if (ss->mgp->dca_enabled)
1567                 myri10ge_update_dca(ss);
1568 #endif
1569
1570         /* process as many rx events as NAPI will allow */
1571         work_done = myri10ge_clean_rx_done(ss, budget);
1572
1573         if (work_done < budget) {
1574                 napi_complete(napi);
1575                 put_be32(htonl(3), ss->irq_claim);
1576         }
1577         return work_done;
1578 }
1579
1580 static irqreturn_t myri10ge_intr(int irq, void *arg)
1581 {
1582         struct myri10ge_slice_state *ss = arg;
1583         struct myri10ge_priv *mgp = ss->mgp;
1584         struct mcp_irq_data *stats = ss->fw_stats;
1585         struct myri10ge_tx_buf *tx = &ss->tx;
1586         u32 send_done_count;
1587         int i;
1588
1589         /* an interrupt on a non-zero receive-only slice is implicitly
1590          * valid  since MSI-X irqs are not shared */
1591         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1592                 napi_schedule(&ss->napi);
1593                 return IRQ_HANDLED;
1594         }
1595
1596         /* make sure it is our IRQ, and that the DMA has finished */
1597         if (unlikely(!stats->valid))
1598                 return IRQ_NONE;
1599
1600         /* low bit indicates receives are present, so schedule
1601          * napi poll handler */
1602         if (stats->valid & 1)
1603                 napi_schedule(&ss->napi);
1604
1605         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1606                 put_be32(0, mgp->irq_deassert);
1607                 if (!myri10ge_deassert_wait)
1608                         stats->valid = 0;
1609                 mb();
1610         } else
1611                 stats->valid = 0;
1612
1613         /* Wait for IRQ line to go low, if using INTx */
1614         i = 0;
1615         while (1) {
1616                 i++;
1617                 /* check for transmit completes and receives */
1618                 send_done_count = ntohl(stats->send_done_count);
1619                 if (send_done_count != tx->pkt_done)
1620                         myri10ge_tx_done(ss, (int)send_done_count);
1621                 if (unlikely(i > myri10ge_max_irq_loops)) {
1622                         netdev_err(mgp->dev, "irq stuck?\n");
1623                         stats->valid = 0;
1624                         schedule_work(&mgp->watchdog_work);
1625                 }
1626                 if (likely(stats->valid == 0))
1627                         break;
1628                 cpu_relax();
1629                 barrier();
1630         }
1631
1632         /* Only slice 0 updates stats */
1633         if (ss == mgp->ss)
1634                 myri10ge_check_statblock(mgp);
1635
1636         put_be32(htonl(3), ss->irq_claim + 1);
1637         return IRQ_HANDLED;
1638 }
1639
1640 static int
1641 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1642 {
1643         struct myri10ge_priv *mgp = netdev_priv(netdev);
1644         char *ptr;
1645         int i;
1646
1647         cmd->autoneg = AUTONEG_DISABLE;
1648         ethtool_cmd_speed_set(cmd, SPEED_10000);
1649         cmd->duplex = DUPLEX_FULL;
1650
1651         /*
1652          * parse the product code to deterimine the interface type
1653          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1654          * after the 3rd dash in the driver's cached copy of the
1655          * EEPROM's product code string.
1656          */
1657         ptr = mgp->product_code_string;
1658         if (ptr == NULL) {
1659                 netdev_err(netdev, "Missing product code\n");
1660                 return 0;
1661         }
1662         for (i = 0; i < 3; i++, ptr++) {
1663                 ptr = strchr(ptr, '-');
1664                 if (ptr == NULL) {
1665                         netdev_err(netdev, "Invalid product code %s\n",
1666                                    mgp->product_code_string);
1667                         return 0;
1668                 }
1669         }
1670         if (*ptr == '2')
1671                 ptr++;
1672         if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1673                 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
1674                 cmd->port = PORT_FIBRE;
1675                 cmd->supported |= SUPPORTED_FIBRE;
1676                 cmd->advertising |= ADVERTISED_FIBRE;
1677         } else {
1678                 cmd->port = PORT_OTHER;
1679         }
1680         if (*ptr == 'R' || *ptr == 'S')
1681                 cmd->transceiver = XCVR_EXTERNAL;
1682         else
1683                 cmd->transceiver = XCVR_INTERNAL;
1684
1685         return 0;
1686 }
1687
1688 static void
1689 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1690 {
1691         struct myri10ge_priv *mgp = netdev_priv(netdev);
1692
1693         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1694         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1695         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1696         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1697 }
1698
1699 static int
1700 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1701 {
1702         struct myri10ge_priv *mgp = netdev_priv(netdev);
1703
1704         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1705         return 0;
1706 }
1707
1708 static int
1709 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1710 {
1711         struct myri10ge_priv *mgp = netdev_priv(netdev);
1712
1713         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1714         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1715         return 0;
1716 }
1717
1718 static void
1719 myri10ge_get_pauseparam(struct net_device *netdev,
1720                         struct ethtool_pauseparam *pause)
1721 {
1722         struct myri10ge_priv *mgp = netdev_priv(netdev);
1723
1724         pause->autoneg = 0;
1725         pause->rx_pause = mgp->pause;
1726         pause->tx_pause = mgp->pause;
1727 }
1728
1729 static int
1730 myri10ge_set_pauseparam(struct net_device *netdev,
1731                         struct ethtool_pauseparam *pause)
1732 {
1733         struct myri10ge_priv *mgp = netdev_priv(netdev);
1734
1735         if (pause->tx_pause != mgp->pause)
1736                 return myri10ge_change_pause(mgp, pause->tx_pause);
1737         if (pause->rx_pause != mgp->pause)
1738                 return myri10ge_change_pause(mgp, pause->rx_pause);
1739         if (pause->autoneg != 0)
1740                 return -EINVAL;
1741         return 0;
1742 }
1743
1744 static void
1745 myri10ge_get_ringparam(struct net_device *netdev,
1746                        struct ethtool_ringparam *ring)
1747 {
1748         struct myri10ge_priv *mgp = netdev_priv(netdev);
1749
1750         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1751         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1752         ring->rx_jumbo_max_pending = 0;
1753         ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1754         ring->rx_mini_pending = ring->rx_mini_max_pending;
1755         ring->rx_pending = ring->rx_max_pending;
1756         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1757         ring->tx_pending = ring->tx_max_pending;
1758 }
1759
1760 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1761         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1762         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1763         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1764         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1765         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1766         "tx_heartbeat_errors", "tx_window_errors",
1767         /* device-specific stats */
1768         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1769         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1770         "serial_number", "watchdog_resets",
1771 #ifdef CONFIG_MYRI10GE_DCA
1772         "dca_capable_firmware", "dca_device_present",
1773 #endif
1774         "link_changes", "link_up", "dropped_link_overflow",
1775         "dropped_link_error_or_filtered",
1776         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1777         "dropped_unicast_filtered", "dropped_multicast_filtered",
1778         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1779         "dropped_no_big_buffer"
1780 };
1781
1782 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1783         "----------- slice ---------",
1784         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1785         "rx_small_cnt", "rx_big_cnt",
1786         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1787             "LRO flushed",
1788         "LRO avg aggr", "LRO no_desc"
1789 };
1790
1791 #define MYRI10GE_NET_STATS_LEN      21
1792 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1793 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1794
1795 static void
1796 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1797 {
1798         struct myri10ge_priv *mgp = netdev_priv(netdev);
1799         int i;
1800
1801         switch (stringset) {
1802         case ETH_SS_STATS:
1803                 memcpy(data, *myri10ge_gstrings_main_stats,
1804                        sizeof(myri10ge_gstrings_main_stats));
1805                 data += sizeof(myri10ge_gstrings_main_stats);
1806                 for (i = 0; i < mgp->num_slices; i++) {
1807                         memcpy(data, *myri10ge_gstrings_slice_stats,
1808                                sizeof(myri10ge_gstrings_slice_stats));
1809                         data += sizeof(myri10ge_gstrings_slice_stats);
1810                 }
1811                 break;
1812         }
1813 }
1814
1815 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1816 {
1817         struct myri10ge_priv *mgp = netdev_priv(netdev);
1818
1819         switch (sset) {
1820         case ETH_SS_STATS:
1821                 return MYRI10GE_MAIN_STATS_LEN +
1822                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1823         default:
1824                 return -EOPNOTSUPP;
1825         }
1826 }
1827
1828 static void
1829 myri10ge_get_ethtool_stats(struct net_device *netdev,
1830                            struct ethtool_stats *stats, u64 * data)
1831 {
1832         struct myri10ge_priv *mgp = netdev_priv(netdev);
1833         struct myri10ge_slice_state *ss;
1834         int slice;
1835         int i;
1836
1837         /* force stats update */
1838         (void)myri10ge_get_stats(netdev);
1839         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1840                 data[i] = ((unsigned long *)&netdev->stats)[i];
1841
1842         data[i++] = (unsigned int)mgp->tx_boundary;
1843         data[i++] = (unsigned int)mgp->wc_enabled;
1844         data[i++] = (unsigned int)mgp->pdev->irq;
1845         data[i++] = (unsigned int)mgp->msi_enabled;
1846         data[i++] = (unsigned int)mgp->msix_enabled;
1847         data[i++] = (unsigned int)mgp->read_dma;
1848         data[i++] = (unsigned int)mgp->write_dma;
1849         data[i++] = (unsigned int)mgp->read_write_dma;
1850         data[i++] = (unsigned int)mgp->serial_number;
1851         data[i++] = (unsigned int)mgp->watchdog_resets;
1852 #ifdef CONFIG_MYRI10GE_DCA
1853         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1854         data[i++] = (unsigned int)(mgp->dca_enabled);
1855 #endif
1856         data[i++] = (unsigned int)mgp->link_changes;
1857
1858         /* firmware stats are useful only in the first slice */
1859         ss = &mgp->ss[0];
1860         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1861         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1862         data[i++] =
1863             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1864         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1865         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1866         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1867         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1868         data[i++] =
1869             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1870         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1871         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1872         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1873         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1874
1875         for (slice = 0; slice < mgp->num_slices; slice++) {
1876                 ss = &mgp->ss[slice];
1877                 data[i++] = slice;
1878                 data[i++] = (unsigned int)ss->tx.pkt_start;
1879                 data[i++] = (unsigned int)ss->tx.pkt_done;
1880                 data[i++] = (unsigned int)ss->tx.req;
1881                 data[i++] = (unsigned int)ss->tx.done;
1882                 data[i++] = (unsigned int)ss->rx_small.cnt;
1883                 data[i++] = (unsigned int)ss->rx_big.cnt;
1884                 data[i++] = (unsigned int)ss->tx.wake_queue;
1885                 data[i++] = (unsigned int)ss->tx.stop_queue;
1886                 data[i++] = (unsigned int)ss->tx.linearized;
1887                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1888                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1889                 if (ss->rx_done.lro_mgr.stats.flushed)
1890                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1891                             ss->rx_done.lro_mgr.stats.flushed;
1892                 else
1893                         data[i++] = 0;
1894                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1895         }
1896 }
1897
1898 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1899 {
1900         struct myri10ge_priv *mgp = netdev_priv(netdev);
1901         mgp->msg_enable = value;
1902 }
1903
1904 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1905 {
1906         struct myri10ge_priv *mgp = netdev_priv(netdev);
1907         return mgp->msg_enable;
1908 }
1909
1910 static const struct ethtool_ops myri10ge_ethtool_ops = {
1911         .get_settings = myri10ge_get_settings,
1912         .get_drvinfo = myri10ge_get_drvinfo,
1913         .get_coalesce = myri10ge_get_coalesce,
1914         .set_coalesce = myri10ge_set_coalesce,
1915         .get_pauseparam = myri10ge_get_pauseparam,
1916         .set_pauseparam = myri10ge_set_pauseparam,
1917         .get_ringparam = myri10ge_get_ringparam,
1918         .get_link = ethtool_op_get_link,
1919         .get_strings = myri10ge_get_strings,
1920         .get_sset_count = myri10ge_get_sset_count,
1921         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1922         .set_msglevel = myri10ge_set_msglevel,
1923         .get_msglevel = myri10ge_get_msglevel,
1924 };
1925
1926 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1927 {
1928         struct myri10ge_priv *mgp = ss->mgp;
1929         struct myri10ge_cmd cmd;
1930         struct net_device *dev = mgp->dev;
1931         int tx_ring_size, rx_ring_size;
1932         int tx_ring_entries, rx_ring_entries;
1933         int i, slice, status;
1934         size_t bytes;
1935
1936         /* get ring sizes */
1937         slice = ss - mgp->ss;
1938         cmd.data0 = slice;
1939         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1940         tx_ring_size = cmd.data0;
1941         cmd.data0 = slice;
1942         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1943         if (status != 0)
1944                 return status;
1945         rx_ring_size = cmd.data0;
1946
1947         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1948         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1949         ss->tx.mask = tx_ring_entries - 1;
1950         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1951
1952         status = -ENOMEM;
1953
1954         /* allocate the host shadow rings */
1955
1956         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1957             * sizeof(*ss->tx.req_list);
1958         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1959         if (ss->tx.req_bytes == NULL)
1960                 goto abort_with_nothing;
1961
1962         /* ensure req_list entries are aligned to 8 bytes */
1963         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1964             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1965         ss->tx.queue_active = 0;
1966
1967         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1968         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1969         if (ss->rx_small.shadow == NULL)
1970                 goto abort_with_tx_req_bytes;
1971
1972         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1973         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1974         if (ss->rx_big.shadow == NULL)
1975                 goto abort_with_rx_small_shadow;
1976
1977         /* allocate the host info rings */
1978
1979         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1980         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1981         if (ss->tx.info == NULL)
1982                 goto abort_with_rx_big_shadow;
1983
1984         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1985         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1986         if (ss->rx_small.info == NULL)
1987                 goto abort_with_tx_info;
1988
1989         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1990         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1991         if (ss->rx_big.info == NULL)
1992                 goto abort_with_rx_small_info;
1993
1994         /* Fill the receive rings */
1995         ss->rx_big.cnt = 0;
1996         ss->rx_small.cnt = 0;
1997         ss->rx_big.fill_cnt = 0;
1998         ss->rx_small.fill_cnt = 0;
1999         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2000         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2001         ss->rx_small.watchdog_needed = 0;
2002         ss->rx_big.watchdog_needed = 0;
2003         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2004                                 mgp->small_bytes + MXGEFW_PAD, 0);
2005
2006         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
2007                 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2008                            slice, ss->rx_small.fill_cnt);
2009                 goto abort_with_rx_small_ring;
2010         }
2011
2012         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2013         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2014                 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2015                            slice, ss->rx_big.fill_cnt);
2016                 goto abort_with_rx_big_ring;
2017         }
2018
2019         return 0;
2020
2021 abort_with_rx_big_ring:
2022         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2023                 int idx = i & ss->rx_big.mask;
2024                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2025                                        mgp->big_bytes);
2026                 put_page(ss->rx_big.info[idx].page);
2027         }
2028
2029 abort_with_rx_small_ring:
2030         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2031                 int idx = i & ss->rx_small.mask;
2032                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2033                                        mgp->small_bytes + MXGEFW_PAD);
2034                 put_page(ss->rx_small.info[idx].page);
2035         }
2036
2037         kfree(ss->rx_big.info);
2038
2039 abort_with_rx_small_info:
2040         kfree(ss->rx_small.info);
2041
2042 abort_with_tx_info:
2043         kfree(ss->tx.info);
2044
2045 abort_with_rx_big_shadow:
2046         kfree(ss->rx_big.shadow);
2047
2048 abort_with_rx_small_shadow:
2049         kfree(ss->rx_small.shadow);
2050
2051 abort_with_tx_req_bytes:
2052         kfree(ss->tx.req_bytes);
2053         ss->tx.req_bytes = NULL;
2054         ss->tx.req_list = NULL;
2055
2056 abort_with_nothing:
2057         return status;
2058 }
2059
2060 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2061 {
2062         struct myri10ge_priv *mgp = ss->mgp;
2063         struct sk_buff *skb;
2064         struct myri10ge_tx_buf *tx;
2065         int i, len, idx;
2066
2067         /* If not allocated, skip it */
2068         if (ss->tx.req_list == NULL)
2069                 return;
2070
2071         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2072                 idx = i & ss->rx_big.mask;
2073                 if (i == ss->rx_big.fill_cnt - 1)
2074                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2075                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2076                                        mgp->big_bytes);
2077                 put_page(ss->rx_big.info[idx].page);
2078         }
2079
2080         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2081                 idx = i & ss->rx_small.mask;
2082                 if (i == ss->rx_small.fill_cnt - 1)
2083                         ss->rx_small.info[idx].page_offset =
2084                             MYRI10GE_ALLOC_SIZE;
2085                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2086                                        mgp->small_bytes + MXGEFW_PAD);
2087                 put_page(ss->rx_small.info[idx].page);
2088         }
2089         tx = &ss->tx;
2090         while (tx->done != tx->req) {
2091                 idx = tx->done & tx->mask;
2092                 skb = tx->info[idx].skb;
2093
2094                 /* Mark as free */
2095                 tx->info[idx].skb = NULL;
2096                 tx->done++;
2097                 len = dma_unmap_len(&tx->info[idx], len);
2098                 dma_unmap_len_set(&tx->info[idx], len, 0);
2099                 if (skb) {
2100                         ss->stats.tx_dropped++;
2101                         dev_kfree_skb_any(skb);
2102                         if (len)
2103                                 pci_unmap_single(mgp->pdev,
2104                                                  dma_unmap_addr(&tx->info[idx],
2105                                                                 bus), len,
2106                                                  PCI_DMA_TODEVICE);
2107                 } else {
2108                         if (len)
2109                                 pci_unmap_page(mgp->pdev,
2110                                                dma_unmap_addr(&tx->info[idx],
2111                                                               bus), len,
2112                                                PCI_DMA_TODEVICE);
2113                 }
2114         }
2115         kfree(ss->rx_big.info);
2116
2117         kfree(ss->rx_small.info);
2118
2119         kfree(ss->tx.info);
2120
2121         kfree(ss->rx_big.shadow);
2122
2123         kfree(ss->rx_small.shadow);
2124
2125         kfree(ss->tx.req_bytes);
2126         ss->tx.req_bytes = NULL;
2127         ss->tx.req_list = NULL;
2128 }
2129
2130 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2131 {
2132         struct pci_dev *pdev = mgp->pdev;
2133         struct myri10ge_slice_state *ss;
2134         struct net_device *netdev = mgp->dev;
2135         int i;
2136         int status;
2137
2138         mgp->msi_enabled = 0;
2139         mgp->msix_enabled = 0;
2140         status = 0;
2141         if (myri10ge_msi) {
2142                 if (mgp->num_slices > 1) {
2143                         status =
2144                             pci_enable_msix(pdev, mgp->msix_vectors,
2145                                             mgp->num_slices);
2146                         if (status == 0) {
2147                                 mgp->msix_enabled = 1;
2148                         } else {
2149                                 dev_err(&pdev->dev,
2150                                         "Error %d setting up MSI-X\n", status);
2151                                 return status;
2152                         }
2153                 }
2154                 if (mgp->msix_enabled == 0) {
2155                         status = pci_enable_msi(pdev);
2156                         if (status != 0) {
2157                                 dev_err(&pdev->dev,
2158                                         "Error %d setting up MSI; falling back to xPIC\n",
2159                                         status);
2160                         } else {
2161                                 mgp->msi_enabled = 1;
2162                         }
2163                 }
2164         }
2165         if (mgp->msix_enabled) {
2166                 for (i = 0; i < mgp->num_slices; i++) {
2167                         ss = &mgp->ss[i];
2168                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2169                                  "%s:slice-%d", netdev->name, i);
2170                         status = request_irq(mgp->msix_vectors[i].vector,
2171                                              myri10ge_intr, 0, ss->irq_desc,
2172                                              ss);
2173                         if (status != 0) {
2174                                 dev_err(&pdev->dev,
2175                                         "slice %d failed to allocate IRQ\n", i);
2176                                 i--;
2177                                 while (i >= 0) {
2178                                         free_irq(mgp->msix_vectors[i].vector,
2179                                                  &mgp->ss[i]);
2180                                         i--;
2181                                 }
2182                                 pci_disable_msix(pdev);
2183                                 return status;
2184                         }
2185                 }
2186         } else {
2187                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2188                                      mgp->dev->name, &mgp->ss[0]);
2189                 if (status != 0) {
2190                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2191                         if (mgp->msi_enabled)
2192                                 pci_disable_msi(pdev);
2193                 }
2194         }
2195         return status;
2196 }
2197
2198 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2199 {
2200         struct pci_dev *pdev = mgp->pdev;
2201         int i;
2202
2203         if (mgp->msix_enabled) {
2204                 for (i = 0; i < mgp->num_slices; i++)
2205                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2206         } else {
2207                 free_irq(pdev->irq, &mgp->ss[0]);
2208         }
2209         if (mgp->msi_enabled)
2210                 pci_disable_msi(pdev);
2211         if (mgp->msix_enabled)
2212                 pci_disable_msix(pdev);
2213 }
2214
2215 static int
2216 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2217                          void **ip_hdr, void **tcpudp_hdr,
2218                          u64 * hdr_flags, void *priv)
2219 {
2220         struct ethhdr *eh;
2221         struct vlan_ethhdr *veh;
2222         struct iphdr *iph;
2223         u8 *va = page_address(frag->page) + frag->page_offset;
2224         unsigned long ll_hlen;
2225         /* passed opaque through lro_receive_frags() */
2226         __wsum csum = (__force __wsum) (unsigned long)priv;
2227
2228         /* find the mac header, aborting if not IPv4 */
2229
2230         eh = (struct ethhdr *)va;
2231         *mac_hdr = eh;
2232         ll_hlen = ETH_HLEN;
2233         if (eh->h_proto != htons(ETH_P_IP)) {
2234                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2235                         veh = (struct vlan_ethhdr *)va;
2236                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2237                                 return -1;
2238
2239                         ll_hlen += VLAN_HLEN;
2240
2241                         /*
2242                          *  HW checksum starts ETH_HLEN bytes into
2243                          *  frame, so we must subtract off the VLAN
2244                          *  header's checksum before csum can be used
2245                          */
2246                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2247                                                            VLAN_HLEN, 0));
2248                 } else {
2249                         return -1;
2250                 }
2251         }
2252         *hdr_flags = LRO_IPV4;
2253
2254         iph = (struct iphdr *)(va + ll_hlen);
2255         *ip_hdr = iph;
2256         if (iph->protocol != IPPROTO_TCP)
2257                 return -1;
2258         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2259                 return -1;
2260         *hdr_flags |= LRO_TCP;
2261         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2262
2263         /* verify the IP checksum */
2264         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2265                 return -1;
2266
2267         /* verify the  checksum */
2268         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2269                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2270                                        IPPROTO_TCP, csum)))
2271                 return -1;
2272
2273         return 0;
2274 }
2275
2276 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2277 {
2278         struct myri10ge_cmd cmd;
2279         struct myri10ge_slice_state *ss;
2280         int status;
2281
2282         ss = &mgp->ss[slice];
2283         status = 0;
2284         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2285                 cmd.data0 = slice;
2286                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2287                                            &cmd, 0);
2288                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2289                     (mgp->sram + cmd.data0);
2290         }
2291         cmd.data0 = slice;
2292         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2293                                     &cmd, 0);
2294         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2295             (mgp->sram + cmd.data0);
2296
2297         cmd.data0 = slice;
2298         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2299         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2300             (mgp->sram + cmd.data0);
2301
2302         ss->tx.send_go = (__iomem __be32 *)
2303             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2304         ss->tx.send_stop = (__iomem __be32 *)
2305             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2306         return status;
2307
2308 }
2309
2310 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2311 {
2312         struct myri10ge_cmd cmd;
2313         struct myri10ge_slice_state *ss;
2314         int status;
2315
2316         ss = &mgp->ss[slice];
2317         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2318         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2319         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2320         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2321         if (status == -ENOSYS) {
2322                 dma_addr_t bus = ss->fw_stats_bus;
2323                 if (slice != 0)
2324                         return -EINVAL;
2325                 bus += offsetof(struct mcp_irq_data, send_done_count);
2326                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2327                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2328                 status = myri10ge_send_cmd(mgp,
2329                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2330                                            &cmd, 0);
2331                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2332                 mgp->fw_multicast_support = 0;
2333         } else {
2334                 mgp->fw_multicast_support = 1;
2335         }
2336         return 0;
2337 }
2338
2339 static int myri10ge_open(struct net_device *dev)
2340 {
2341         struct myri10ge_slice_state *ss;
2342         struct myri10ge_priv *mgp = netdev_priv(dev);
2343         struct myri10ge_cmd cmd;
2344         int i, status, big_pow2, slice;
2345         u8 *itable;
2346         struct net_lro_mgr *lro_mgr;
2347
2348         if (mgp->running != MYRI10GE_ETH_STOPPED)
2349                 return -EBUSY;
2350
2351         mgp->running = MYRI10GE_ETH_STARTING;
2352         status = myri10ge_reset(mgp);
2353         if (status != 0) {
2354                 netdev_err(dev, "failed reset\n");
2355                 goto abort_with_nothing;
2356         }
2357
2358         if (mgp->num_slices > 1) {
2359                 cmd.data0 = mgp->num_slices;
2360                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2361                 if (mgp->dev->real_num_tx_queues > 1)
2362                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2363                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2364                                            &cmd, 0);
2365                 if (status != 0) {
2366                         netdev_err(dev, "failed to set number of slices\n");
2367                         goto abort_with_nothing;
2368                 }
2369                 /* setup the indirection table */
2370                 cmd.data0 = mgp->num_slices;
2371                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2372                                            &cmd, 0);
2373
2374                 status |= myri10ge_send_cmd(mgp,
2375                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2376                                             &cmd, 0);
2377                 if (status != 0) {
2378                         netdev_err(dev, "failed to setup rss tables\n");
2379                         goto abort_with_nothing;
2380                 }
2381
2382                 /* just enable an identity mapping */
2383                 itable = mgp->sram + cmd.data0;
2384                 for (i = 0; i < mgp->num_slices; i++)
2385                         __raw_writeb(i, &itable[i]);
2386
2387                 cmd.data0 = 1;
2388                 cmd.data1 = myri10ge_rss_hash;
2389                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2390                                            &cmd, 0);
2391                 if (status != 0) {
2392                         netdev_err(dev, "failed to enable slices\n");
2393                         goto abort_with_nothing;
2394                 }
2395         }
2396
2397         status = myri10ge_request_irq(mgp);
2398         if (status != 0)
2399                 goto abort_with_nothing;
2400
2401         /* decide what small buffer size to use.  For good TCP rx
2402          * performance, it is important to not receive 1514 byte
2403          * frames into jumbo buffers, as it confuses the socket buffer
2404          * accounting code, leading to drops and erratic performance.
2405          */
2406
2407         if (dev->mtu <= ETH_DATA_LEN)
2408                 /* enough for a TCP header */
2409                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2410                     ? (128 - MXGEFW_PAD)
2411                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2412         else
2413                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2414                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2415
2416         /* Override the small buffer size? */
2417         if (myri10ge_small_bytes > 0)
2418                 mgp->small_bytes = myri10ge_small_bytes;
2419
2420         /* Firmware needs the big buff size as a power of 2.  Lie and
2421          * tell him the buffer is larger, because we only use 1
2422          * buffer/pkt, and the mtu will prevent overruns.
2423          */
2424         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2425         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2426                 while (!is_power_of_2(big_pow2))
2427                         big_pow2++;
2428                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2429         } else {
2430                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2431                 mgp->big_bytes = big_pow2;
2432         }
2433
2434         /* setup the per-slice data structures */
2435         for (slice = 0; slice < mgp->num_slices; slice++) {
2436                 ss = &mgp->ss[slice];
2437
2438                 status = myri10ge_get_txrx(mgp, slice);
2439                 if (status != 0) {
2440                         netdev_err(dev, "failed to get ring sizes or locations\n");
2441                         goto abort_with_rings;
2442                 }
2443                 status = myri10ge_allocate_rings(ss);
2444                 if (status != 0)
2445                         goto abort_with_rings;
2446
2447                 /* only firmware which supports multiple TX queues
2448                  * supports setting up the tx stats on non-zero
2449                  * slices */
2450                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2451                         status = myri10ge_set_stats(mgp, slice);
2452                 if (status) {
2453                         netdev_err(dev, "Couldn't set stats DMA\n");
2454                         goto abort_with_rings;
2455                 }
2456
2457                 lro_mgr = &ss->rx_done.lro_mgr;
2458                 lro_mgr->dev = dev;
2459                 lro_mgr->features = LRO_F_NAPI;
2460                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2461                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2462                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2463                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2464                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2465                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2466                 lro_mgr->frag_align_pad = 2;
2467                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2468                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2469
2470                 /* must happen prior to any irq */
2471                 napi_enable(&(ss)->napi);
2472         }
2473
2474         /* now give firmware buffers sizes, and MTU */
2475         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2476         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2477         cmd.data0 = mgp->small_bytes;
2478         status |=
2479             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2480         cmd.data0 = big_pow2;
2481         status |=
2482             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2483         if (status) {
2484                 netdev_err(dev, "Couldn't set buffer sizes\n");
2485                 goto abort_with_rings;
2486         }
2487
2488         /*
2489          * Set Linux style TSO mode; this is needed only on newer
2490          *  firmware versions.  Older versions default to Linux
2491          *  style TSO
2492          */
2493         cmd.data0 = 0;
2494         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2495         if (status && status != -ENOSYS) {
2496                 netdev_err(dev, "Couldn't set TSO mode\n");
2497                 goto abort_with_rings;
2498         }
2499
2500         mgp->link_state = ~0U;
2501         mgp->rdma_tags_available = 15;
2502
2503         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2504         if (status) {
2505                 netdev_err(dev, "Couldn't bring up link\n");
2506                 goto abort_with_rings;
2507         }
2508
2509         mgp->running = MYRI10GE_ETH_RUNNING;
2510         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2511         add_timer(&mgp->watchdog_timer);
2512         netif_tx_wake_all_queues(dev);
2513
2514         return 0;
2515
2516 abort_with_rings:
2517         while (slice) {
2518                 slice--;
2519                 napi_disable(&mgp->ss[slice].napi);
2520         }
2521         for (i = 0; i < mgp->num_slices; i++)
2522                 myri10ge_free_rings(&mgp->ss[i]);
2523
2524         myri10ge_free_irq(mgp);
2525
2526 abort_with_nothing:
2527         mgp->running = MYRI10GE_ETH_STOPPED;
2528         return -ENOMEM;
2529 }
2530
2531 static int myri10ge_close(struct net_device *dev)
2532 {
2533         struct myri10ge_priv *mgp = netdev_priv(dev);
2534         struct myri10ge_cmd cmd;
2535         int status, old_down_cnt;
2536         int i;
2537
2538         if (mgp->running != MYRI10GE_ETH_RUNNING)
2539                 return 0;
2540
2541         if (mgp->ss[0].tx.req_bytes == NULL)
2542                 return 0;
2543
2544         del_timer_sync(&mgp->watchdog_timer);
2545         mgp->running = MYRI10GE_ETH_STOPPING;
2546         for (i = 0; i < mgp->num_slices; i++) {
2547                 napi_disable(&mgp->ss[i].napi);
2548         }
2549         netif_carrier_off(dev);
2550
2551         netif_tx_stop_all_queues(dev);
2552         if (mgp->rebooted == 0) {
2553                 old_down_cnt = mgp->down_cnt;
2554                 mb();
2555                 status =
2556                     myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2557                 if (status)
2558                         netdev_err(dev, "Couldn't bring down link\n");
2559
2560                 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2561                                    HZ);
2562                 if (old_down_cnt == mgp->down_cnt)
2563                         netdev_err(dev, "never got down irq\n");
2564         }
2565         netif_tx_disable(dev);
2566         myri10ge_free_irq(mgp);
2567         for (i = 0; i < mgp->num_slices; i++)
2568                 myri10ge_free_rings(&mgp->ss[i]);
2569
2570         mgp->running = MYRI10GE_ETH_STOPPED;
2571         return 0;
2572 }
2573
2574 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2575  * backwards one at a time and handle ring wraps */
2576
2577 static inline void
2578 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2579                               struct mcp_kreq_ether_send *src, int cnt)
2580 {
2581         int idx, starting_slot;
2582         starting_slot = tx->req;
2583         while (cnt > 1) {
2584                 cnt--;
2585                 idx = (starting_slot + cnt) & tx->mask;
2586                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2587                 mb();
2588         }
2589 }
2590
2591 /*
2592  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2593  * at most 32 bytes at a time, so as to avoid involving the software
2594  * pio handler in the nic.   We re-write the first segment's flags
2595  * to mark them valid only after writing the entire chain.
2596  */
2597
2598 static inline void
2599 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2600                     int cnt)
2601 {
2602         int idx, i;
2603         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2604         struct mcp_kreq_ether_send *srcp;
2605         u8 last_flags;
2606
2607         idx = tx->req & tx->mask;
2608
2609         last_flags = src->flags;
2610         src->flags = 0;
2611         mb();
2612         dst = dstp = &tx->lanai[idx];
2613         srcp = src;
2614
2615         if ((idx + cnt) < tx->mask) {
2616                 for (i = 0; i < (cnt - 1); i += 2) {
2617                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2618                         mb();   /* force write every 32 bytes */
2619                         srcp += 2;
2620                         dstp += 2;
2621                 }
2622         } else {
2623                 /* submit all but the first request, and ensure
2624                  * that it is submitted below */
2625                 myri10ge_submit_req_backwards(tx, src, cnt);
2626                 i = 0;
2627         }
2628         if (i < cnt) {
2629                 /* submit the first request */
2630                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2631                 mb();           /* barrier before setting valid flag */
2632         }
2633
2634         /* re-write the last 32-bits with the valid flags */
2635         src->flags = last_flags;
2636         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2637         tx->req += cnt;
2638         mb();
2639 }
2640
2641 /*
2642  * Transmit a packet.  We need to split the packet so that a single
2643  * segment does not cross myri10ge->tx_boundary, so this makes segment
2644  * counting tricky.  So rather than try to count segments up front, we
2645  * just give up if there are too few segments to hold a reasonably
2646  * fragmented packet currently available.  If we run
2647  * out of segments while preparing a packet for DMA, we just linearize
2648  * it and try again.
2649  */
2650
2651 static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2652                                        struct net_device *dev)
2653 {
2654         struct myri10ge_priv *mgp = netdev_priv(dev);
2655         struct myri10ge_slice_state *ss;
2656         struct mcp_kreq_ether_send *req;
2657         struct myri10ge_tx_buf *tx;
2658         struct skb_frag_struct *frag;
2659         struct netdev_queue *netdev_queue;
2660         dma_addr_t bus;
2661         u32 low;
2662         __be32 high_swapped;
2663         unsigned int len;
2664         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2665         u16 pseudo_hdr_offset, cksum_offset, queue;
2666         int cum_len, seglen, boundary, rdma_count;
2667         u8 flags, odd_flag;
2668
2669         queue = skb_get_queue_mapping(skb);
2670         ss = &mgp->ss[queue];
2671         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2672         tx = &ss->tx;
2673
2674 again:
2675         req = tx->req_list;
2676         avail = tx->mask - 1 - (tx->req - tx->done);
2677
2678         mss = 0;
2679         max_segments = MXGEFW_MAX_SEND_DESC;
2680
2681         if (skb_is_gso(skb)) {
2682                 mss = skb_shinfo(skb)->gso_size;
2683                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2684         }
2685
2686         if ((unlikely(avail < max_segments))) {
2687                 /* we are out of transmit resources */
2688                 tx->stop_queue++;
2689                 netif_tx_stop_queue(netdev_queue);
2690                 return NETDEV_TX_BUSY;
2691         }
2692
2693         /* Setup checksum offloading, if needed */
2694         cksum_offset = 0;
2695         pseudo_hdr_offset = 0;
2696         odd_flag = 0;
2697         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2698         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2699                 cksum_offset = skb_checksum_start_offset(skb);
2700                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2701                 /* If the headers are excessively large, then we must
2702                  * fall back to a software checksum */
2703                 if (unlikely(!mss && (cksum_offset > 255 ||
2704                                       pseudo_hdr_offset > 127))) {
2705                         if (skb_checksum_help(skb))
2706                                 goto drop;
2707                         cksum_offset = 0;
2708                         pseudo_hdr_offset = 0;
2709                 } else {
2710                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2711                         flags |= MXGEFW_FLAGS_CKSUM;
2712                 }
2713         }
2714
2715         cum_len = 0;
2716
2717         if (mss) {              /* TSO */
2718                 /* this removes any CKSUM flag from before */
2719                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2720
2721                 /* negative cum_len signifies to the
2722                  * send loop that we are still in the
2723                  * header portion of the TSO packet.
2724                  * TSO header can be at most 1KB long */
2725                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2726
2727                 /* for IPv6 TSO, the checksum offset stores the
2728                  * TCP header length, to save the firmware from
2729                  * the need to parse the headers */
2730                 if (skb_is_gso_v6(skb)) {
2731                         cksum_offset = tcp_hdrlen(skb);
2732                         /* Can only handle headers <= max_tso6 long */
2733                         if (unlikely(-cum_len > mgp->max_tso6))
2734                                 return myri10ge_sw_tso(skb, dev);
2735                 }
2736                 /* for TSO, pseudo_hdr_offset holds mss.
2737                  * The firmware figures out where to put
2738                  * the checksum by parsing the header. */
2739                 pseudo_hdr_offset = mss;
2740         } else
2741                 /* Mark small packets, and pad out tiny packets */
2742         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2743                 flags |= MXGEFW_FLAGS_SMALL;
2744
2745                 /* pad frames to at least ETH_ZLEN bytes */
2746                 if (unlikely(skb->len < ETH_ZLEN)) {
2747                         if (skb_padto(skb, ETH_ZLEN)) {
2748                                 /* The packet is gone, so we must
2749                                  * return 0 */
2750                                 ss->stats.tx_dropped += 1;
2751                                 return NETDEV_TX_OK;
2752                         }
2753                         /* adjust the len to account for the zero pad
2754                          * so that the nic can know how long it is */
2755                         skb->len = ETH_ZLEN;
2756                 }
2757         }
2758
2759         /* map the skb for DMA */
2760         len = skb_headlen(skb);
2761         idx = tx->req & tx->mask;
2762         tx->info[idx].skb = skb;
2763         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2764         dma_unmap_addr_set(&tx->info[idx], bus, bus);
2765         dma_unmap_len_set(&tx->info[idx], len, len);
2766
2767         frag_cnt = skb_shinfo(skb)->nr_frags;
2768         frag_idx = 0;
2769         count = 0;
2770         rdma_count = 0;
2771
2772         /* "rdma_count" is the number of RDMAs belonging to the
2773          * current packet BEFORE the current send request. For
2774          * non-TSO packets, this is equal to "count".
2775          * For TSO packets, rdma_count needs to be reset
2776          * to 0 after a segment cut.
2777          *
2778          * The rdma_count field of the send request is
2779          * the number of RDMAs of the packet starting at
2780          * that request. For TSO send requests with one ore more cuts
2781          * in the middle, this is the number of RDMAs starting
2782          * after the last cut in the request. All previous
2783          * segments before the last cut implicitly have 1 RDMA.
2784          *
2785          * Since the number of RDMAs is not known beforehand,
2786          * it must be filled-in retroactively - after each
2787          * segmentation cut or at the end of the entire packet.
2788          */
2789
2790         while (1) {
2791                 /* Break the SKB or Fragment up into pieces which
2792                  * do not cross mgp->tx_boundary */
2793                 low = MYRI10GE_LOWPART_TO_U32(bus);
2794                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2795                 while (len) {
2796                         u8 flags_next;
2797                         int cum_len_next;
2798
2799                         if (unlikely(count == max_segments))
2800                                 goto abort_linearize;
2801
2802                         boundary =
2803                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2804                         seglen = boundary - low;
2805                         if (seglen > len)
2806                                 seglen = len;
2807                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2808                         cum_len_next = cum_len + seglen;
2809                         if (mss) {      /* TSO */
2810                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2811
2812                                 if (likely(cum_len >= 0)) {     /* payload */
2813                                         int next_is_first, chop;
2814
2815                                         chop = (cum_len_next > mss);
2816                                         cum_len_next = cum_len_next % mss;
2817                                         next_is_first = (cum_len_next == 0);
2818                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2819                                         flags_next |= next_is_first *
2820                                             MXGEFW_FLAGS_FIRST;
2821                                         rdma_count |= -(chop | next_is_first);
2822                                         rdma_count += chop & !next_is_first;
2823                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2824                                         int small;
2825
2826                                         rdma_count = -1;
2827                                         cum_len_next = 0;
2828                                         seglen = -cum_len;
2829                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2830                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2831                                             MXGEFW_FLAGS_FIRST |
2832                                             (small * MXGEFW_FLAGS_SMALL);
2833                                 }
2834                         }
2835                         req->addr_high = high_swapped;
2836                         req->addr_low = htonl(low);
2837                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2838                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2839                         req->rdma_count = 1;
2840                         req->length = htons(seglen);
2841                         req->cksum_offset = cksum_offset;
2842                         req->flags = flags | ((cum_len & 1) * odd_flag);
2843
2844                         low += seglen;
2845                         len -= seglen;
2846                         cum_len = cum_len_next;
2847                         flags = flags_next;
2848                         req++;
2849                         count++;
2850                         rdma_count++;
2851                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2852                                 if (unlikely(cksum_offset > seglen))
2853                                         cksum_offset -= seglen;
2854                                 else
2855                                         cksum_offset = 0;
2856                         }
2857                 }
2858                 if (frag_idx == frag_cnt)
2859                         break;
2860
2861                 /* map next fragment for DMA */
2862                 idx = (count + tx->req) & tx->mask;
2863                 frag = &skb_shinfo(skb)->frags[frag_idx];
2864                 frag_idx++;
2865                 len = frag->size;
2866                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2867                                    len, PCI_DMA_TODEVICE);
2868                 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2869                 dma_unmap_len_set(&tx->info[idx], len, len);
2870         }
2871
2872         (req - rdma_count)->rdma_count = rdma_count;
2873         if (mss)
2874                 do {
2875                         req--;
2876                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2877                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2878                                          MXGEFW_FLAGS_FIRST)));
2879         idx = ((count - 1) + tx->req) & tx->mask;
2880         tx->info[idx].last = 1;
2881         myri10ge_submit_req(tx, tx->req_list, count);
2882         /* if using multiple tx queues, make sure NIC polls the
2883          * current slice */
2884         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2885                 tx->queue_active = 1;
2886                 put_be32(htonl(1), tx->send_go);
2887                 mb();
2888                 mmiowb();
2889         }
2890         tx->pkt_start++;
2891         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2892                 tx->stop_queue++;
2893                 netif_tx_stop_queue(netdev_queue);
2894         }
2895         return NETDEV_TX_OK;
2896
2897 abort_linearize:
2898         /* Free any DMA resources we've alloced and clear out the skb
2899          * slot so as to not trip up assertions, and to avoid a
2900          * double-free if linearizing fails */
2901
2902         last_idx = (idx + 1) & tx->mask;
2903         idx = tx->req & tx->mask;
2904         tx->info[idx].skb = NULL;
2905         do {
2906                 len = dma_unmap_len(&tx->info[idx], len);
2907                 if (len) {
2908                         if (tx->info[idx].skb != NULL)
2909                                 pci_unmap_single(mgp->pdev,
2910                                                  dma_unmap_addr(&tx->info[idx],
2911                                                                 bus), len,
2912                                                  PCI_DMA_TODEVICE);
2913                         else
2914                                 pci_unmap_page(mgp->pdev,
2915                                                dma_unmap_addr(&tx->info[idx],
2916                                                               bus), len,
2917                                                PCI_DMA_TODEVICE);
2918                         dma_unmap_len_set(&tx->info[idx], len, 0);
2919                         tx->info[idx].skb = NULL;
2920                 }
2921                 idx = (idx + 1) & tx->mask;
2922         } while (idx != last_idx);
2923         if (skb_is_gso(skb)) {
2924                 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2925                 goto drop;
2926         }
2927
2928         if (skb_linearize(skb))
2929                 goto drop;
2930
2931         tx->linearized++;
2932         goto again;
2933
2934 drop:
2935         dev_kfree_skb_any(skb);
2936         ss->stats.tx_dropped += 1;
2937         return NETDEV_TX_OK;
2938
2939 }
2940
2941 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2942                                          struct net_device *dev)
2943 {
2944         struct sk_buff *segs, *curr;
2945         struct myri10ge_priv *mgp = netdev_priv(dev);
2946         struct myri10ge_slice_state *ss;
2947         netdev_tx_t status;
2948
2949         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2950         if (IS_ERR(segs))
2951                 goto drop;
2952
2953         while (segs) {
2954                 curr = segs;
2955                 segs = segs->next;
2956                 curr->next = NULL;
2957                 status = myri10ge_xmit(curr, dev);
2958                 if (status != 0) {
2959                         dev_kfree_skb_any(curr);
2960                         if (segs != NULL) {
2961                                 curr = segs;
2962                                 segs = segs->next;
2963                                 curr->next = NULL;
2964                                 dev_kfree_skb_any(segs);
2965                         }
2966                         goto drop;
2967                 }
2968         }
2969         dev_kfree_skb_any(skb);
2970         return NETDEV_TX_OK;
2971
2972 drop:
2973         ss = &mgp->ss[skb_get_queue_mapping(skb)];
2974         dev_kfree_skb_any(skb);
2975         ss->stats.tx_dropped += 1;
2976         return NETDEV_TX_OK;
2977 }
2978
2979 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2980 {
2981         struct myri10ge_priv *mgp = netdev_priv(dev);
2982         struct myri10ge_slice_netstats *slice_stats;
2983         struct net_device_stats *stats = &dev->stats;
2984         int i;
2985
2986         spin_lock(&mgp->stats_lock);
2987         memset(stats, 0, sizeof(*stats));
2988         for (i = 0; i < mgp->num_slices; i++) {
2989                 slice_stats = &mgp->ss[i].stats;
2990                 stats->rx_packets += slice_stats->rx_packets;
2991                 stats->tx_packets += slice_stats->tx_packets;
2992                 stats->rx_bytes += slice_stats->rx_bytes;
2993                 stats->tx_bytes += slice_stats->tx_bytes;
2994                 stats->rx_dropped += slice_stats->rx_dropped;
2995                 stats->tx_dropped += slice_stats->tx_dropped;
2996         }
2997         spin_unlock(&mgp->stats_lock);
2998         return stats;
2999 }
3000
3001 static void myri10ge_set_multicast_list(struct net_device *dev)
3002 {
3003         struct myri10ge_priv *mgp = netdev_priv(dev);
3004         struct myri10ge_cmd cmd;
3005         struct netdev_hw_addr *ha;
3006         __be32 data[2] = { 0, 0 };
3007         int err;
3008
3009         /* can be called from atomic contexts,
3010          * pass 1 to force atomicity in myri10ge_send_cmd() */
3011         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3012
3013         /* This firmware is known to not support multicast */
3014         if (!mgp->fw_multicast_support)
3015                 return;
3016
3017         /* Disable multicast filtering */
3018
3019         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3020         if (err != 0) {
3021                 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3022                            err);
3023                 goto abort;
3024         }
3025
3026         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3027                 /* request to disable multicast filtering, so quit here */
3028                 return;
3029         }
3030
3031         /* Flush the filters */
3032
3033         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3034                                 &cmd, 1);
3035         if (err != 0) {
3036                 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3037                            err);
3038                 goto abort;
3039         }
3040
3041         /* Walk the multicast list, and add each address */
3042         netdev_for_each_mc_addr(ha, dev) {
3043                 memcpy(data, &ha->addr, 6);
3044                 cmd.data0 = ntohl(data[0]);
3045                 cmd.data1 = ntohl(data[1]);
3046                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3047                                         &cmd, 1);
3048
3049                 if (err != 0) {
3050                         netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
3051                                    err, ha->addr);
3052                         goto abort;
3053                 }
3054         }
3055         /* Enable multicast filtering */
3056         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3057         if (err != 0) {
3058                 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3059                            err);
3060                 goto abort;
3061         }
3062
3063         return;
3064
3065 abort:
3066         return;
3067 }
3068
3069 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3070 {
3071         struct sockaddr *sa = addr;
3072         struct myri10ge_priv *mgp = netdev_priv(dev);
3073         int status;
3074
3075         if (!is_valid_ether_addr(sa->sa_data))
3076                 return -EADDRNOTAVAIL;
3077
3078         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3079         if (status != 0) {
3080                 netdev_err(dev, "changing mac address failed with %d\n",
3081                            status);
3082                 return status;
3083         }
3084
3085         /* change the dev structure */
3086         memcpy(dev->dev_addr, sa->sa_data, 6);
3087         return 0;
3088 }
3089
3090 static u32 myri10ge_fix_features(struct net_device *dev, u32 features)
3091 {
3092         if (!(features & NETIF_F_RXCSUM))
3093                 features &= ~NETIF_F_LRO;
3094
3095         return features;
3096 }
3097
3098 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3099 {
3100         struct myri10ge_priv *mgp = netdev_priv(dev);
3101         int error = 0;
3102
3103         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3104                 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
3105                 return -EINVAL;
3106         }
3107         netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
3108         if (mgp->running) {
3109                 /* if we change the mtu on an active device, we must
3110                  * reset the device so the firmware sees the change */
3111                 myri10ge_close(dev);
3112                 dev->mtu = new_mtu;
3113                 myri10ge_open(dev);
3114         } else
3115                 dev->mtu = new_mtu;
3116
3117         return error;
3118 }
3119
3120 /*
3121  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3122  * Only do it if the bridge is a root port since we don't want to disturb
3123  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3124  */
3125
3126 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3127 {
3128         struct pci_dev *bridge = mgp->pdev->bus->self;
3129         struct device *dev = &mgp->pdev->dev;
3130         unsigned cap;
3131         unsigned err_cap;
3132         u16 val;
3133         u8 ext_type;
3134         int ret;
3135
3136         if (!myri10ge_ecrc_enable || !bridge)
3137                 return;
3138
3139         /* check that the bridge is a root port */
3140         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3141         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3142         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3143         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3144                 if (myri10ge_ecrc_enable > 1) {
3145                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3146
3147                         /* Walk the hierarchy up to the root port
3148                          * where ECRC has to be enabled */
3149                         do {
3150                                 prev_bridge = bridge;
3151                                 bridge = bridge->bus->self;
3152                                 if (!bridge || prev_bridge == bridge) {
3153                                         dev_err(dev,
3154                                                 "Failed to find root port"
3155                                                 " to force ECRC\n");
3156                                         return;
3157                                 }
3158                                 cap =
3159                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3160                                 pci_read_config_word(bridge,
3161                                                      cap + PCI_CAP_FLAGS, &val);
3162                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3163                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3164
3165                         dev_info(dev,
3166                                  "Forcing ECRC on non-root port %s"
3167                                  " (enabling on root port %s)\n",
3168                                  pci_name(old_bridge), pci_name(bridge));
3169                 } else {
3170                         dev_err(dev,
3171                                 "Not enabling ECRC on non-root port %s\n",
3172                                 pci_name(bridge));
3173                         return;
3174                 }
3175         }
3176
3177         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3178         if (!cap)
3179                 return;
3180
3181         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3182         if (ret) {
3183                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3184                         pci_name(bridge));
3185                 dev_err(dev, "\t pci=nommconf in use? "
3186                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3187                 return;
3188         }
3189         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3190                 return;
3191
3192         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3193         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3194         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3195 }
3196
3197 /*
3198  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3199  * when the PCI-E Completion packets are aligned on an 8-byte
3200  * boundary.  Some PCI-E chip sets always align Completion packets; on
3201  * the ones that do not, the alignment can be enforced by enabling
3202  * ECRC generation (if supported).
3203  *
3204  * When PCI-E Completion packets are not aligned, it is actually more
3205  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3206  *
3207  * If the driver can neither enable ECRC nor verify that it has
3208  * already been enabled, then it must use a firmware image which works
3209  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3210  * should also ensure that it never gives the device a Read-DMA which is
3211  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3212  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3213  * firmware image, and set tx_boundary to 4KB.
3214  */
3215
3216 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3217 {
3218         struct pci_dev *pdev = mgp->pdev;
3219         struct device *dev = &pdev->dev;
3220         int status;
3221
3222         mgp->tx_boundary = 4096;
3223         /*
3224          * Verify the max read request size was set to 4KB
3225          * before trying the test with 4KB.
3226          */
3227         status = pcie_get_readrq(pdev);
3228         if (status < 0) {
3229                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3230                 goto abort;
3231         }
3232         if (status != 4096) {
3233                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3234                 mgp->tx_boundary = 2048;
3235         }
3236         /*
3237          * load the optimized firmware (which assumes aligned PCIe
3238          * completions) in order to see if it works on this host.
3239          */
3240         set_fw_name(mgp, myri10ge_fw_aligned, false);
3241         status = myri10ge_load_firmware(mgp, 1);
3242         if (status != 0) {
3243                 goto abort;
3244         }
3245
3246         /*
3247          * Enable ECRC if possible
3248          */
3249         myri10ge_enable_ecrc(mgp);
3250
3251         /*
3252          * Run a DMA test which watches for unaligned completions and
3253          * aborts on the first one seen.
3254          */
3255
3256         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3257         if (status == 0)
3258                 return;         /* keep the aligned firmware */
3259
3260         if (status != -E2BIG)
3261                 dev_warn(dev, "DMA test failed: %d\n", status);
3262         if (status == -ENOSYS)
3263                 dev_warn(dev, "Falling back to ethp! "
3264                          "Please install up to date fw\n");
3265 abort:
3266         /* fall back to using the unaligned firmware */
3267         mgp->tx_boundary = 2048;
3268         set_fw_name(mgp, myri10ge_fw_unaligned, false);
3269
3270 }
3271
3272 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3273 {
3274         int overridden = 0;
3275
3276         if (myri10ge_force_firmware == 0) {
3277                 int link_width, exp_cap;
3278                 u16 lnk;
3279
3280                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3281                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3282                 link_width = (lnk >> 4) & 0x3f;
3283
3284                 /* Check to see if Link is less than 8 or if the
3285                  * upstream bridge is known to provide aligned
3286                  * completions */
3287                 if (link_width < 8) {
3288                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3289                                  link_width);
3290                         mgp->tx_boundary = 4096;
3291                         set_fw_name(mgp, myri10ge_fw_aligned, false);
3292                 } else {
3293                         myri10ge_firmware_probe(mgp);
3294                 }
3295         } else {
3296                 if (myri10ge_force_firmware == 1) {
3297                         dev_info(&mgp->pdev->dev,
3298                                  "Assuming aligned completions (forced)\n");
3299                         mgp->tx_boundary = 4096;
3300                         set_fw_name(mgp, myri10ge_fw_aligned, false);
3301                 } else {
3302                         dev_info(&mgp->pdev->dev,
3303                                  "Assuming unaligned completions (forced)\n");
3304                         mgp->tx_boundary = 2048;
3305                         set_fw_name(mgp, myri10ge_fw_unaligned, false);
3306                 }
3307         }
3308
3309         kparam_block_sysfs_write(myri10ge_fw_name);
3310         if (myri10ge_fw_name != NULL) {
3311                 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3312                 if (fw_name) {
3313                         overridden = 1;
3314                         set_fw_name(mgp, fw_name, true);
3315                 }
3316         }
3317         kparam_unblock_sysfs_write(myri10ge_fw_name);
3318
3319         if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3320             myri10ge_fw_names[mgp->board_number] != NULL &&
3321             strlen(myri10ge_fw_names[mgp->board_number])) {
3322                 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
3323                 overridden = 1;
3324         }
3325         if (overridden)
3326                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3327                          mgp->fw_name);
3328 }
3329
3330 #ifdef CONFIG_PM
3331 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3332 {
3333         struct myri10ge_priv *mgp;
3334         struct net_device *netdev;
3335
3336         mgp = pci_get_drvdata(pdev);
3337         if (mgp == NULL)
3338                 return -EINVAL;
3339         netdev = mgp->dev;
3340
3341         netif_device_detach(netdev);
3342         if (netif_running(netdev)) {
3343                 netdev_info(netdev, "closing\n");
3344                 rtnl_lock();
3345                 myri10ge_close(netdev);
3346                 rtnl_unlock();
3347         }
3348         myri10ge_dummy_rdma(mgp, 0);
3349         pci_save_state(pdev);
3350         pci_disable_device(pdev);
3351
3352         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3353 }
3354
3355 static int myri10ge_resume(struct pci_dev *pdev)
3356 {
3357         struct myri10ge_priv *mgp;
3358         struct net_device *netdev;
3359         int status;
3360         u16 vendor;
3361
3362         mgp = pci_get_drvdata(pdev);
3363         if (mgp == NULL)
3364                 return -EINVAL;
3365         netdev = mgp->dev;
3366         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3367         msleep(5);              /* give card time to respond */
3368         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3369         if (vendor == 0xffff) {
3370                 netdev_err(mgp->dev, "device disappeared!\n");
3371                 return -EIO;
3372         }
3373
3374         pci_restore_state(pdev);
3375
3376         status = pci_enable_device(pdev);
3377         if (status) {
3378                 dev_err(&pdev->dev, "failed to enable device\n");
3379                 return status;
3380         }
3381
3382         pci_set_master(pdev);
3383
3384         myri10ge_reset(mgp);
3385         myri10ge_dummy_rdma(mgp, 1);
3386
3387         /* Save configuration space to be restored if the
3388          * nic resets due to a parity error */
3389         pci_save_state(pdev);
3390
3391         if (netif_running(netdev)) {
3392                 rtnl_lock();
3393                 status = myri10ge_open(netdev);
3394                 rtnl_unlock();
3395                 if (status != 0)
3396                         goto abort_with_enabled;
3397
3398         }
3399         netif_device_attach(netdev);
3400
3401         return 0;
3402
3403 abort_with_enabled:
3404         pci_disable_device(pdev);
3405         return -EIO;
3406
3407 }
3408 #endif                          /* CONFIG_PM */
3409
3410 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3411 {
3412         struct pci_dev *pdev = mgp->pdev;
3413         int vs = mgp->vendor_specific_offset;
3414         u32 reboot;
3415
3416         /*enter read32 mode */
3417         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3418
3419         /*read REBOOT_STATUS (0xfffffff0) */
3420         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3421         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3422         return reboot;
3423 }
3424
3425 /*
3426  * This watchdog is used to check whether the board has suffered
3427  * from a parity error and needs to be recovered.
3428  */
3429 static void myri10ge_watchdog(struct work_struct *work)
3430 {
3431         struct myri10ge_priv *mgp =
3432             container_of(work, struct myri10ge_priv, watchdog_work);
3433         struct myri10ge_tx_buf *tx;
3434         u32 reboot;
3435         int status, rebooted;
3436         int i;
3437         u16 cmd, vendor;
3438
3439         mgp->watchdog_resets++;
3440         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3441         rebooted = 0;
3442         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3443                 /* Bus master DMA disabled?  Check to see
3444                  * if the card rebooted due to a parity error
3445                  * For now, just report it */
3446                 reboot = myri10ge_read_reboot(mgp);
3447                 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3448                            reboot,
3449                            myri10ge_reset_recover ? "" : " not");
3450                 if (myri10ge_reset_recover == 0)
3451                         return;
3452                 rtnl_lock();
3453                 mgp->rebooted = 1;
3454                 rebooted = 1;
3455                 myri10ge_close(mgp->dev);
3456                 myri10ge_reset_recover--;
3457                 mgp->rebooted = 0;
3458                 /*
3459                  * A rebooted nic will come back with config space as
3460                  * it was after power was applied to PCIe bus.
3461                  * Attempt to restore config space which was saved
3462                  * when the driver was loaded, or the last time the
3463                  * nic was resumed from power saving mode.
3464                  */
3465                 pci_restore_state(mgp->pdev);
3466
3467                 /* save state again for accounting reasons */
3468                 pci_save_state(mgp->pdev);
3469
3470         } else {
3471                 /* if we get back -1's from our slot, perhaps somebody
3472                  * powered off our card.  Don't try to reset it in
3473                  * this case */
3474                 if (cmd == 0xffff) {
3475                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3476                         if (vendor == 0xffff) {
3477                                 netdev_err(mgp->dev, "device disappeared!\n");
3478                                 return;
3479                         }
3480                 }
3481                 /* Perhaps it is a software error.  Try to reset */
3482
3483                 netdev_err(mgp->dev, "device timeout, resetting\n");
3484                 for (i = 0; i < mgp->num_slices; i++) {
3485                         tx = &mgp->ss[i].tx;
3486                         netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3487                                    i, tx->queue_active, tx->req,
3488                                    tx->done, tx->pkt_start, tx->pkt_done,
3489                                    (int)ntohl(mgp->ss[i].fw_stats->
3490                                               send_done_count));
3491                         msleep(2000);
3492                         netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3493                                     i, tx->queue_active, tx->req,
3494                                     tx->done, tx->pkt_start, tx->pkt_done,
3495                                     (int)ntohl(mgp->ss[i].fw_stats->
3496                                                send_done_count));
3497                 }
3498         }
3499
3500         if (!rebooted) {
3501                 rtnl_lock();
3502                 myri10ge_close(mgp->dev);
3503         }
3504         status = myri10ge_load_firmware(mgp, 1);
3505         if (status != 0)
3506                 netdev_err(mgp->dev, "failed to load firmware\n");
3507         else
3508                 myri10ge_open(mgp->dev);
3509         rtnl_unlock();
3510 }
3511
3512 /*
3513  * We use our own timer routine rather than relying upon
3514  * netdev->tx_timeout because we have a very large hardware transmit
3515  * queue.  Due to the large queue, the netdev->tx_timeout function
3516  * cannot detect a NIC with a parity error in a timely fashion if the
3517  * NIC is lightly loaded.
3518  */
3519 static void myri10ge_watchdog_timer(unsigned long arg)
3520 {
3521         struct myri10ge_priv *mgp;
3522         struct myri10ge_slice_state *ss;
3523         int i, reset_needed, busy_slice_cnt;
3524         u32 rx_pause_cnt;
3525         u16 cmd;
3526
3527         mgp = (struct myri10ge_priv *)arg;
3528
3529         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3530         busy_slice_cnt = 0;
3531         for (i = 0, reset_needed = 0;
3532              i < mgp->num_slices && reset_needed == 0; ++i) {
3533
3534                 ss = &mgp->ss[i];
3535                 if (ss->rx_small.watchdog_needed) {
3536                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3537                                                 mgp->small_bytes + MXGEFW_PAD,
3538                                                 1);
3539                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3540                             myri10ge_fill_thresh)
3541                                 ss->rx_small.watchdog_needed = 0;
3542                 }
3543                 if (ss->rx_big.watchdog_needed) {
3544                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3545                                                 mgp->big_bytes, 1);
3546                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3547                             myri10ge_fill_thresh)
3548                                 ss->rx_big.watchdog_needed = 0;
3549                 }
3550
3551                 if (ss->tx.req != ss->tx.done &&
3552                     ss->tx.done == ss->watchdog_tx_done &&
3553                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3554                         /* nic seems like it might be stuck.. */
3555                         if (rx_pause_cnt != mgp->watchdog_pause) {
3556                                 if (net_ratelimit())
3557                                         netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3558                                                    i);
3559                         } else {
3560                                 netdev_warn(mgp->dev, "slice %d stuck:", i);
3561                                 reset_needed = 1;
3562                         }
3563                 }
3564                 if (ss->watchdog_tx_done != ss->tx.done ||
3565                     ss->watchdog_rx_done != ss->rx_done.cnt) {
3566                         busy_slice_cnt++;
3567                 }
3568                 ss->watchdog_tx_done = ss->tx.done;
3569                 ss->watchdog_tx_req = ss->tx.req;
3570                 ss->watchdog_rx_done = ss->rx_done.cnt;
3571         }
3572         /* if we've sent or received no traffic, poll the NIC to
3573          * ensure it is still there.  Otherwise, we risk not noticing
3574          * an error in a timely fashion */
3575         if (busy_slice_cnt == 0) {
3576                 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3577                 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3578                         reset_needed = 1;
3579                 }
3580         }
3581         mgp->watchdog_pause = rx_pause_cnt;
3582
3583         if (reset_needed) {
3584                 schedule_work(&mgp->watchdog_work);
3585         } else {
3586                 /* rearm timer */
3587                 mod_timer(&mgp->watchdog_timer,
3588                           jiffies + myri10ge_watchdog_timeout * HZ);
3589         }
3590 }
3591
3592 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3593 {
3594         struct myri10ge_slice_state *ss;
3595         struct pci_dev *pdev = mgp->pdev;
3596         size_t bytes;
3597         int i;
3598
3599         if (mgp->ss == NULL)
3600                 return;
3601
3602         for (i = 0; i < mgp->num_slices; i++) {
3603                 ss = &mgp->ss[i];
3604                 if (ss->rx_done.entry != NULL) {
3605                         bytes = mgp->max_intr_slots *
3606                             sizeof(*ss->rx_done.entry);
3607                         dma_free_coherent(&pdev->dev, bytes,
3608                                           ss->rx_done.entry, ss->rx_done.bus);
3609                         ss->rx_done.entry = NULL;
3610                 }
3611                 if (ss->fw_stats != NULL) {
3612                         bytes = sizeof(*ss->fw_stats);
3613                         dma_free_coherent(&pdev->dev, bytes,
3614                                           ss->fw_stats, ss->fw_stats_bus);
3615                         ss->fw_stats = NULL;
3616                         netif_napi_del(&ss->napi);
3617                 }
3618         }
3619         kfree(mgp->ss);
3620         mgp->ss = NULL;
3621 }
3622
3623 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3624 {
3625         struct myri10ge_slice_state *ss;
3626         struct pci_dev *pdev = mgp->pdev;
3627         size_t bytes;
3628         int i;
3629
3630         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3631         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3632         if (mgp->ss == NULL) {
3633                 return -ENOMEM;
3634         }
3635
3636         for (i = 0; i < mgp->num_slices; i++) {
3637                 ss = &mgp->ss[i];
3638                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3639                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3640                                                        &ss->rx_done.bus,
3641                                                        GFP_KERNEL);
3642                 if (ss->rx_done.entry == NULL)
3643                         goto abort;
3644                 memset(ss->rx_done.entry, 0, bytes);
3645                 bytes = sizeof(*ss->fw_stats);
3646                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3647                                                   &ss->fw_stats_bus,
3648                                                   GFP_KERNEL);
3649                 if (ss->fw_stats == NULL)
3650                         goto abort;
3651                 ss->mgp = mgp;
3652                 ss->dev = mgp->dev;
3653                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3654                                myri10ge_napi_weight);
3655         }
3656         return 0;
3657 abort:
3658         myri10ge_free_slices(mgp);
3659         return -ENOMEM;
3660 }
3661
3662 /*
3663  * This function determines the number of slices supported.
3664  * The number slices is the minimum of the number of CPUS,
3665  * the number of MSI-X irqs supported, the number of slices
3666  * supported by the firmware
3667  */
3668 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3669 {
3670         struct myri10ge_cmd cmd;
3671         struct pci_dev *pdev = mgp->pdev;
3672         char *old_fw;
3673         bool old_allocated;
3674         int i, status, ncpus, msix_cap;
3675
3676         mgp->num_slices = 1;
3677         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3678         ncpus = num_online_cpus();
3679
3680         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3681             (myri10ge_max_slices == -1 && ncpus < 2))
3682                 return;
3683
3684         /* try to load the slice aware rss firmware */
3685         old_fw = mgp->fw_name;
3686         old_allocated = mgp->fw_name_allocated;
3687         /* don't free old_fw if we override it. */
3688         mgp->fw_name_allocated = false;
3689
3690         if (myri10ge_fw_name != NULL) {
3691                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3692                          myri10ge_fw_name);
3693                 set_fw_name(mgp, myri10ge_fw_name, false);
3694         } else if (old_fw == myri10ge_fw_aligned)
3695                 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
3696         else
3697                 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
3698         status = myri10ge_load_firmware(mgp, 0);
3699         if (status != 0) {
3700                 dev_info(&pdev->dev, "Rss firmware not found\n");
3701                 if (old_allocated)
3702                         kfree(old_fw);
3703                 return;
3704         }
3705
3706         /* hit the board with a reset to ensure it is alive */
3707         memset(&cmd, 0, sizeof(cmd));
3708         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3709         if (status != 0) {
3710                 dev_err(&mgp->pdev->dev, "failed reset\n");
3711                 goto abort_with_fw;
3712         }
3713
3714         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3715
3716         /* tell it the size of the interrupt queues */
3717         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3718         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3719         if (status != 0) {
3720                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3721                 goto abort_with_fw;
3722         }
3723
3724         /* ask the maximum number of slices it supports */
3725         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3726         if (status != 0)
3727                 goto abort_with_fw;
3728         else
3729                 mgp->num_slices = cmd.data0;
3730
3731         /* Only allow multiple slices if MSI-X is usable */
3732         if (!myri10ge_msi) {
3733                 goto abort_with_fw;
3734         }
3735
3736         /* if the admin did not specify a limit to how many
3737          * slices we should use, cap it automatically to the
3738          * number of CPUs currently online */
3739         if (myri10ge_max_slices == -1)
3740                 myri10ge_max_slices = ncpus;
3741
3742         if (mgp->num_slices > myri10ge_max_slices)
3743                 mgp->num_slices = myri10ge_max_slices;
3744
3745         /* Now try to allocate as many MSI-X vectors as we have
3746          * slices. We give up on MSI-X if we can only get a single
3747          * vector. */
3748
3749         mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3750                                     GFP_KERNEL);
3751         if (mgp->msix_vectors == NULL)
3752                 goto disable_msix;
3753         for (i = 0; i < mgp->num_slices; i++) {
3754                 mgp->msix_vectors[i].entry = i;
3755         }
3756
3757         while (mgp->num_slices > 1) {
3758                 /* make sure it is a power of two */
3759                 while (!is_power_of_2(mgp->num_slices))
3760                         mgp->num_slices--;
3761                 if (mgp->num_slices == 1)
3762                         goto disable_msix;
3763                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3764                                          mgp->num_slices);
3765                 if (status == 0) {
3766                         pci_disable_msix(pdev);
3767                         if (old_allocated)
3768                                 kfree(old_fw);
3769                         return;
3770                 }
3771                 if (status > 0)
3772                         mgp->num_slices = status;
3773                 else
3774                         goto disable_msix;
3775         }
3776
3777 disable_msix:
3778         if (mgp->msix_vectors != NULL) {
3779                 kfree(mgp->msix_vectors);
3780                 mgp->msix_vectors = NULL;
3781         }
3782
3783 abort_with_fw:
3784         mgp->num_slices = 1;
3785         set_fw_name(mgp, old_fw, old_allocated);
3786         myri10ge_load_firmware(mgp, 0);
3787 }
3788
3789 static const struct net_device_ops myri10ge_netdev_ops = {
3790         .ndo_open               = myri10ge_open,
3791         .ndo_stop               = myri10ge_close,
3792         .ndo_start_xmit         = myri10ge_xmit,
3793         .ndo_get_stats          = myri10ge_get_stats,
3794         .ndo_validate_addr      = eth_validate_addr,
3795         .ndo_change_mtu         = myri10ge_change_mtu,
3796         .ndo_fix_features       = myri10ge_fix_features,
3797         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3798         .ndo_set_mac_address    = myri10ge_set_mac_address,
3799 };
3800
3801 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3802 {
3803         struct net_device *netdev;
3804         struct myri10ge_priv *mgp;
3805         struct device *dev = &pdev->dev;
3806         int i;
3807         int status = -ENXIO;
3808         int dac_enabled;
3809         unsigned hdr_offset, ss_offset;
3810         static int board_number;
3811
3812         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3813         if (netdev == NULL) {
3814                 dev_err(dev, "Could not allocate ethernet device\n");
3815                 return -ENOMEM;
3816         }
3817
3818         SET_NETDEV_DEV(netdev, &pdev->dev);
3819
3820         mgp = netdev_priv(netdev);
3821         mgp->dev = netdev;
3822         mgp->pdev = pdev;
3823         mgp->pause = myri10ge_flow_control;
3824         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3825         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3826         mgp->board_number = board_number;
3827         init_waitqueue_head(&mgp->down_wq);
3828
3829         if (pci_enable_device(pdev)) {
3830                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3831                 status = -ENODEV;
3832                 goto abort_with_netdev;
3833         }
3834
3835         /* Find the vendor-specific cap so we can check
3836          * the reboot register later on */
3837         mgp->vendor_specific_offset
3838             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3839
3840         /* Set our max read request to 4KB */
3841         status = pcie_set_readrq(pdev, 4096);
3842         if (status != 0) {
3843                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3844                         status);
3845                 goto abort_with_enabled;
3846         }
3847
3848         pci_set_master(pdev);
3849         dac_enabled = 1;
3850         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3851         if (status != 0) {
3852                 dac_enabled = 0;
3853                 dev_err(&pdev->dev,
3854                         "64-bit pci address mask was refused, "
3855                         "trying 32-bit\n");
3856                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3857         }
3858         if (status != 0) {
3859                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3860                 goto abort_with_enabled;
3861         }
3862         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3863         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3864                                       &mgp->cmd_bus, GFP_KERNEL);
3865         if (mgp->cmd == NULL)
3866                 goto abort_with_enabled;
3867
3868         mgp->board_span = pci_resource_len(pdev, 0);
3869         mgp->iomem_base = pci_resource_start(pdev, 0);
3870         mgp->mtrr = -1;
3871         mgp->wc_enabled = 0;
3872 #ifdef CONFIG_MTRR
3873         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3874                              MTRR_TYPE_WRCOMB, 1);
3875         if (mgp->mtrr >= 0)
3876                 mgp->wc_enabled = 1;
3877 #endif
3878         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3879         if (mgp->sram == NULL) {
3880                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3881                         mgp->board_span, mgp->iomem_base);
3882                 status = -ENXIO;
3883                 goto abort_with_mtrr;
3884         }
3885         hdr_offset =
3886             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3887         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3888         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3889         if (mgp->sram_size > mgp->board_span ||
3890             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3891                 dev_err(&pdev->dev,
3892                         "invalid sram_size %dB or board span %ldB\n",
3893                         mgp->sram_size, mgp->board_span);
3894                 goto abort_with_ioremap;
3895         }
3896         memcpy_fromio(mgp->eeprom_strings,
3897                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3898         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3899         status = myri10ge_read_mac_addr(mgp);
3900         if (status)
3901                 goto abort_with_ioremap;
3902
3903         for (i = 0; i < ETH_ALEN; i++)
3904                 netdev->dev_addr[i] = mgp->mac_addr[i];
3905
3906         myri10ge_select_firmware(mgp);
3907
3908         status = myri10ge_load_firmware(mgp, 1);
3909         if (status != 0) {
3910                 dev_err(&pdev->dev, "failed to load firmware\n");
3911                 goto abort_with_ioremap;
3912         }
3913         myri10ge_probe_slices(mgp);
3914         status = myri10ge_alloc_slices(mgp);
3915         if (status != 0) {
3916                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3917                 goto abort_with_firmware;
3918         }
3919         netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3920         netif_set_real_num_rx_queues(netdev, mgp->num_slices);
3921         status = myri10ge_reset(mgp);
3922         if (status != 0) {
3923                 dev_err(&pdev->dev, "failed reset\n");
3924                 goto abort_with_slices;
3925         }
3926 #ifdef CONFIG_MYRI10GE_DCA
3927         myri10ge_setup_dca(mgp);
3928 #endif
3929         pci_set_drvdata(pdev, mgp);
3930         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3931                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3932         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3933                 myri10ge_initial_mtu = 68;
3934
3935         netdev->netdev_ops = &myri10ge_netdev_ops;
3936         netdev->mtu = myri10ge_initial_mtu;
3937         netdev->base_addr = mgp->iomem_base;
3938         netdev->hw_features = mgp->features | NETIF_F_LRO | NETIF_F_RXCSUM;
3939         netdev->features = netdev->hw_features;
3940
3941         if (dac_enabled)
3942                 netdev->features |= NETIF_F_HIGHDMA;
3943
3944         netdev->vlan_features |= mgp->features;
3945         if (mgp->fw_ver_tiny < 37)
3946                 netdev->vlan_features &= ~NETIF_F_TSO6;
3947         if (mgp->fw_ver_tiny < 32)
3948                 netdev->vlan_features &= ~NETIF_F_TSO;
3949
3950         /* make sure we can get an irq, and that MSI can be
3951          * setup (if available).  Also ensure netdev->irq
3952          * is set to correct value if MSI is enabled */
3953         status = myri10ge_request_irq(mgp);
3954         if (status != 0)
3955                 goto abort_with_firmware;
3956         netdev->irq = pdev->irq;
3957         myri10ge_free_irq(mgp);
3958
3959         /* Save configuration space to be restored if the
3960          * nic resets due to a parity error */
3961         pci_save_state(pdev);
3962
3963         /* Setup the watchdog timer */
3964         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3965                     (unsigned long)mgp);
3966
3967         spin_lock_init(&mgp->stats_lock);
3968         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3969         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3970         status = register_netdev(netdev);
3971         if (status != 0) {
3972                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3973                 goto abort_with_state;
3974         }
3975         if (mgp->msix_enabled)
3976                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3977                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3978                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3979         else
3980                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3981                          mgp->msi_enabled ? "MSI" : "xPIC",
3982                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3983                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3984
3985         board_number++;
3986         return 0;
3987
3988 abort_with_state:
3989         pci_restore_state(pdev);
3990
3991 abort_with_slices:
3992         myri10ge_free_slices(mgp);
3993
3994 abort_with_firmware:
3995         myri10ge_dummy_rdma(mgp, 0);
3996
3997 abort_with_ioremap:
3998         if (mgp->mac_addr_string != NULL)
3999                 dev_err(&pdev->dev,
4000                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4001                         mgp->mac_addr_string, mgp->serial_number);
4002         iounmap(mgp->sram);
4003
4004 abort_with_mtrr:
4005 #ifdef CONFIG_MTRR
4006         if (mgp->mtrr >= 0)
4007                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4008 #endif
4009         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4010                           mgp->cmd, mgp->cmd_bus);
4011
4012 abort_with_enabled:
4013         pci_disable_device(pdev);
4014
4015 abort_with_netdev:
4016         set_fw_name(mgp, NULL, false);
4017         free_netdev(netdev);
4018         return status;
4019 }
4020
4021 /*
4022  * myri10ge_remove
4023  *
4024  * Does what is necessary to shutdown one Myrinet device. Called
4025  *   once for each Myrinet card by the kernel when a module is
4026  *   unloaded.
4027  */
4028 static void myri10ge_remove(struct pci_dev *pdev)
4029 {
4030         struct myri10ge_priv *mgp;
4031         struct net_device *netdev;
4032
4033         mgp = pci_get_drvdata(pdev);
4034         if (mgp == NULL)
4035                 return;
4036
4037         cancel_work_sync(&mgp->watchdog_work);
4038         netdev = mgp->dev;
4039         unregister_netdev(netdev);
4040
4041 #ifdef CONFIG_MYRI10GE_DCA
4042         myri10ge_teardown_dca(mgp);
4043 #endif
4044         myri10ge_dummy_rdma(mgp, 0);
4045
4046         /* avoid a memory leak */
4047         pci_restore_state(pdev);
4048
4049         iounmap(mgp->sram);
4050
4051 #ifdef CONFIG_MTRR
4052         if (mgp->mtrr >= 0)
4053                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4054 #endif
4055         myri10ge_free_slices(mgp);
4056         if (mgp->msix_vectors != NULL)
4057                 kfree(mgp->msix_vectors);
4058         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4059                           mgp->cmd, mgp->cmd_bus);
4060
4061         set_fw_name(mgp, NULL, false);
4062         free_netdev(netdev);
4063         pci_disable_device(pdev);
4064         pci_set_drvdata(pdev, NULL);
4065 }
4066
4067 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4068 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4069
4070 static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
4071         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4072         {PCI_DEVICE
4073          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4074         {0},
4075 };
4076
4077 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4078
4079 static struct pci_driver myri10ge_driver = {
4080         .name = "myri10ge",
4081         .probe = myri10ge_probe,
4082         .remove = myri10ge_remove,
4083         .id_table = myri10ge_pci_tbl,
4084 #ifdef CONFIG_PM
4085         .suspend = myri10ge_suspend,
4086         .resume = myri10ge_resume,
4087 #endif
4088 };
4089
4090 #ifdef CONFIG_MYRI10GE_DCA
4091 static int
4092 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4093 {
4094         int err = driver_for_each_device(&myri10ge_driver.driver,
4095                                          NULL, &event,
4096                                          myri10ge_notify_dca_device);
4097
4098         if (err)
4099                 return NOTIFY_BAD;
4100         return NOTIFY_DONE;
4101 }
4102
4103 static struct notifier_block myri10ge_dca_notifier = {
4104         .notifier_call = myri10ge_notify_dca,
4105         .next = NULL,
4106         .priority = 0,
4107 };
4108 #endif                          /* CONFIG_MYRI10GE_DCA */
4109
4110 static __init int myri10ge_init_module(void)
4111 {
4112         pr_info("Version %s\n", MYRI10GE_VERSION_STR);
4113
4114         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4115                 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4116                        myri10ge_rss_hash);
4117                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4118         }
4119 #ifdef CONFIG_MYRI10GE_DCA
4120         dca_register_notify(&myri10ge_dca_notifier);
4121 #endif
4122         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4123                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4124
4125         return pci_register_driver(&myri10ge_driver);
4126 }
4127
4128 module_init(myri10ge_init_module);
4129
4130 static __exit void myri10ge_cleanup_module(void)
4131 {
4132 #ifdef CONFIG_MYRI10GE_DCA
4133         dca_unregister_notify(&myri10ge_dca_notifier);
4134 #endif
4135         pci_unregister_driver(&myri10ge_driver);
4136 }
4137
4138 module_exit(myri10ge_cleanup_module);