2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_RX 0x00000804
100 #define INT_EXT 0x00000002
101 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
102 #define INT_EXT_LINK 0x00100000
103 #define INT_EXT_PHY 0x00010000
104 #define INT_EXT_TX_ERROR_0 0x00000100
105 #define INT_EXT_TX_0 0x00000001
106 #define INT_EXT_TX 0x00000101
107 #define INT_MASK(p) (0x0468 + ((p) << 10))
108 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
109 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
110 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
111 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
112 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
113 #define TXQ_BW_TOKENS(p) (0x0700 + ((p) << 10))
114 #define TXQ_BW_CONF(p) (0x0704 + ((p) << 10))
115 #define TXQ_BW_WRR_CONF(p) (0x0708 + ((p) << 10))
116 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
123 * SDMA configuration register.
125 #define RX_BURST_SIZE_4_64BIT (2 << 1)
126 #define BLM_RX_NO_SWAP (1 << 4)
127 #define BLM_TX_NO_SWAP (1 << 5)
128 #define TX_BURST_SIZE_4_64BIT (2 << 22)
130 #if defined(__BIG_ENDIAN)
131 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
133 TX_BURST_SIZE_4_64BIT
134 #elif defined(__LITTLE_ENDIAN)
135 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
139 TX_BURST_SIZE_4_64BIT
141 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
146 * Port serial control register.
148 #define SET_MII_SPEED_TO_100 (1 << 24)
149 #define SET_GMII_SPEED_TO_1000 (1 << 23)
150 #define SET_FULL_DUPLEX_MODE (1 << 21)
151 #define MAX_RX_PACKET_1522BYTE (1 << 17)
152 #define MAX_RX_PACKET_9700BYTE (5 << 17)
153 #define MAX_RX_PACKET_MASK (7 << 17)
154 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159 #define FORCE_LINK_PASS (1 << 1)
160 #define SERIAL_PORT_ENABLE (1 << 0)
162 #define DEFAULT_RX_QUEUE_SIZE 400
163 #define DEFAULT_TX_QUEUE_SIZE 800
169 #if defined(__BIG_ENDIAN)
171 u16 byte_cnt; /* Descriptor buffer byte count */
172 u16 buf_size; /* Buffer size */
173 u32 cmd_sts; /* Descriptor command status */
174 u32 next_desc_ptr; /* Next descriptor pointer */
175 u32 buf_ptr; /* Descriptor buffer pointer */
179 u16 byte_cnt; /* buffer byte count */
180 u16 l4i_chk; /* CPU provided TCP checksum */
181 u32 cmd_sts; /* Command/status field */
182 u32 next_desc_ptr; /* Pointer to next descriptor */
183 u32 buf_ptr; /* pointer to buffer for this descriptor*/
185 #elif defined(__LITTLE_ENDIAN)
187 u32 cmd_sts; /* Descriptor command status */
188 u16 buf_size; /* Buffer size */
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 u32 next_desc_ptr; /* Next descriptor pointer */
195 u32 cmd_sts; /* Command/status field */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u16 byte_cnt; /* buffer byte count */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 u32 next_desc_ptr; /* Pointer to next descriptor */
202 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
205 /* RX & TX descriptor command */
206 #define BUFFER_OWNED_BY_DMA 0x80000000
208 /* RX & TX descriptor status */
209 #define ERROR_SUMMARY 0x00000001
211 /* RX descriptor status */
212 #define LAYER_4_CHECKSUM_OK 0x40000000
213 #define RX_ENABLE_INTERRUPT 0x20000000
214 #define RX_FIRST_DESC 0x08000000
215 #define RX_LAST_DESC 0x04000000
217 /* TX descriptor command */
218 #define TX_ENABLE_INTERRUPT 0x00800000
219 #define GEN_CRC 0x00400000
220 #define TX_FIRST_DESC 0x00200000
221 #define TX_LAST_DESC 0x00100000
222 #define ZERO_PADDING 0x00080000
223 #define GEN_IP_V4_CHECKSUM 0x00040000
224 #define GEN_TCP_UDP_CHECKSUM 0x00020000
225 #define UDP_FRAME 0x00010000
227 #define TX_IHL_SHIFT 11
230 /* global *******************************************************************/
231 struct mv643xx_eth_shared_private {
233 * Ethernet controller base address.
238 * Protects access to SMI_REG, which is shared between ports.
243 * Per-port MBUS window access register value.
248 * Hardware-specific parameters.
254 /* per-port *****************************************************************/
255 struct mib_counters {
256 u64 good_octets_received;
257 u32 bad_octets_received;
258 u32 internal_mac_transmit_err;
259 u32 good_frames_received;
260 u32 bad_frames_received;
261 u32 broadcast_frames_received;
262 u32 multicast_frames_received;
263 u32 frames_64_octets;
264 u32 frames_65_to_127_octets;
265 u32 frames_128_to_255_octets;
266 u32 frames_256_to_511_octets;
267 u32 frames_512_to_1023_octets;
268 u32 frames_1024_to_max_octets;
269 u64 good_octets_sent;
270 u32 good_frames_sent;
271 u32 excessive_collision;
272 u32 multicast_frames_sent;
273 u32 broadcast_frames_sent;
274 u32 unrec_mac_control_received;
276 u32 good_fc_received;
278 u32 undersize_received;
279 u32 fragments_received;
280 u32 oversize_received;
282 u32 mac_receive_error;
295 struct rx_desc *rx_desc_area;
296 dma_addr_t rx_desc_dma;
297 int rx_desc_area_size;
298 struct sk_buff **rx_skb;
300 struct timer_list rx_oom;
310 struct tx_desc *tx_desc_area;
311 dma_addr_t tx_desc_dma;
312 int tx_desc_area_size;
313 struct sk_buff **tx_skb;
316 struct mv643xx_eth_private {
317 struct mv643xx_eth_shared_private *shared;
320 struct net_device *dev;
322 struct mv643xx_eth_shared_private *shared_smi;
327 struct mib_counters mib_counters;
328 struct work_struct tx_timeout_task;
329 struct mii_if_info mii;
334 int default_rx_ring_size;
335 unsigned long rx_desc_sram_addr;
336 int rx_desc_sram_size;
337 struct napi_struct napi;
338 struct rx_queue rxq[1];
343 int default_tx_ring_size;
344 unsigned long tx_desc_sram_addr;
345 int tx_desc_sram_size;
346 struct tx_queue txq[1];
347 #ifdef MV643XX_ETH_TX_FAST_REFILL
348 int tx_clean_threshold;
353 /* port register accessors **************************************************/
354 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
356 return readl(mp->shared->base + offset);
359 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
361 writel(data, mp->shared->base + offset);
365 /* rxq/txq helper functions *************************************************/
366 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
368 return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
371 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
373 return container_of(txq, struct mv643xx_eth_private, txq[0]);
376 static void rxq_enable(struct rx_queue *rxq)
378 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
379 wrl(mp, RXQ_COMMAND(mp->port_num), 1);
382 static void rxq_disable(struct rx_queue *rxq)
384 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
387 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
388 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
392 static void txq_enable(struct tx_queue *txq)
394 struct mv643xx_eth_private *mp = txq_to_mp(txq);
395 wrl(mp, TXQ_COMMAND(mp->port_num), 1);
398 static void txq_disable(struct tx_queue *txq)
400 struct mv643xx_eth_private *mp = txq_to_mp(txq);
403 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
408 static void __txq_maybe_wake(struct tx_queue *txq)
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
412 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
413 netif_wake_queue(mp->dev);
417 /* rx ***********************************************************************/
418 static void txq_reclaim(struct tx_queue *txq, int force);
420 static void rxq_refill(struct rx_queue *rxq)
422 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
425 spin_lock_irqsave(&mp->lock, flags);
427 while (rxq->rx_desc_count < rxq->rx_ring_size) {
434 * Reserve 2+14 bytes for an ethernet header (the
435 * hardware automatically prepends 2 bytes of dummy
436 * data to each received packet), 4 bytes for a VLAN
437 * header, and 4 bytes for the trailing FCS -- 24
440 skb_size = mp->dev->mtu + 24;
442 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
446 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
448 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
450 rxq->rx_desc_count++;
451 rx = rxq->rx_used_desc;
452 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
454 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
455 skb_size, DMA_FROM_DEVICE);
456 rxq->rx_desc_area[rx].buf_size = skb_size;
457 rxq->rx_skb[rx] = skb;
459 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
464 * The hardware automatically prepends 2 bytes of
465 * dummy data to each received packet, so that the
466 * IP header ends up 16-byte aligned.
471 if (rxq->rx_desc_count == 0) {
472 rxq->rx_oom.expires = jiffies + (HZ / 10);
473 add_timer(&rxq->rx_oom);
476 spin_unlock_irqrestore(&mp->lock, flags);
479 static inline void rxq_refill_timer_wrapper(unsigned long data)
481 rxq_refill((struct rx_queue *)data);
484 static int rxq_process(struct rx_queue *rxq, int budget)
486 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
487 struct net_device_stats *stats = &mp->dev->stats;
491 while (rx < budget) {
492 struct rx_desc *rx_desc;
493 unsigned int cmd_sts;
497 spin_lock_irqsave(&mp->lock, flags);
499 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
501 cmd_sts = rx_desc->cmd_sts;
502 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
503 spin_unlock_irqrestore(&mp->lock, flags);
508 skb = rxq->rx_skb[rxq->rx_curr_desc];
509 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
511 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
513 spin_unlock_irqrestore(&mp->lock, flags);
515 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
516 mp->dev->mtu + 24, DMA_FROM_DEVICE);
517 rxq->rx_desc_count--;
523 * Note that the descriptor byte count includes 2 dummy
524 * bytes automatically inserted by the hardware at the
525 * start of the packet (which we don't count), and a 4
526 * byte CRC at the end of the packet (which we do count).
529 stats->rx_bytes += rx_desc->byte_cnt - 2;
532 * In case we received a packet without first / last bits
533 * on, or the error summary bit is set, the packet needs
536 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
537 (RX_FIRST_DESC | RX_LAST_DESC))
538 || (cmd_sts & ERROR_SUMMARY)) {
541 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
542 (RX_FIRST_DESC | RX_LAST_DESC)) {
544 dev_printk(KERN_ERR, &mp->dev->dev,
545 "received packet spanning "
546 "multiple descriptors\n");
549 if (cmd_sts & ERROR_SUMMARY)
552 dev_kfree_skb_irq(skb);
555 * The -4 is for the CRC in the trailer of the
558 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
560 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
563 (cmd_sts & 0x0007fff8) >> 3);
565 skb->protocol = eth_type_trans(skb, mp->dev);
566 #ifdef MV643XX_ETH_NAPI
567 netif_receive_skb(skb);
573 mp->dev->last_rx = jiffies;
581 #ifdef MV643XX_ETH_NAPI
582 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
584 struct mv643xx_eth_private *mp;
587 mp = container_of(napi, struct mv643xx_eth_private, napi);
589 #ifdef MV643XX_ETH_TX_FAST_REFILL
590 if (++mp->tx_clean_threshold > 5) {
591 txq_reclaim(mp->txq, 0);
592 mp->tx_clean_threshold = 0;
596 rx = rxq_process(mp->rxq, budget);
599 netif_rx_complete(mp->dev, napi);
600 wrl(mp, INT_CAUSE(mp->port_num), 0);
601 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
602 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
610 /* tx ***********************************************************************/
611 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
615 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
616 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
617 if (fragp->size <= 8 && fragp->page_offset & 7)
624 static int txq_alloc_desc_index(struct tx_queue *txq)
628 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
630 tx_desc_curr = txq->tx_curr_desc;
631 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
633 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
638 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
640 int nr_frags = skb_shinfo(skb)->nr_frags;
643 for (frag = 0; frag < nr_frags; frag++) {
644 skb_frag_t *this_frag;
646 struct tx_desc *desc;
648 this_frag = &skb_shinfo(skb)->frags[frag];
649 tx_index = txq_alloc_desc_index(txq);
650 desc = &txq->tx_desc_area[tx_index];
653 * The last fragment will generate an interrupt
654 * which will free the skb on TX completion.
656 if (frag == nr_frags - 1) {
657 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
658 ZERO_PADDING | TX_LAST_DESC |
660 txq->tx_skb[tx_index] = skb;
662 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
663 txq->tx_skb[tx_index] = NULL;
667 desc->byte_cnt = this_frag->size;
668 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
669 this_frag->page_offset,
675 static inline __be16 sum16_as_be(__sum16 sum)
677 return (__force __be16)sum;
680 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
682 int nr_frags = skb_shinfo(skb)->nr_frags;
684 struct tx_desc *desc;
688 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
690 tx_index = txq_alloc_desc_index(txq);
691 desc = &txq->tx_desc_area[tx_index];
694 txq_submit_frag_skb(txq, skb);
696 length = skb_headlen(skb);
697 txq->tx_skb[tx_index] = NULL;
699 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
701 txq->tx_skb[tx_index] = skb;
704 desc->byte_cnt = length;
705 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
707 if (skb->ip_summed == CHECKSUM_PARTIAL) {
708 BUG_ON(skb->protocol != htons(ETH_P_IP));
710 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
712 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
714 switch (ip_hdr(skb)->protocol) {
716 cmd_sts |= UDP_FRAME;
717 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
720 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
726 /* Errata BTS #50, IHL must be 5 if no HW checksum */
727 cmd_sts |= 5 << TX_IHL_SHIFT;
731 /* ensure all other descriptors are written before first cmd_sts */
733 desc->cmd_sts = cmd_sts;
735 /* ensure all descriptors are written before poking hardware */
739 txq->tx_desc_count += nr_frags + 1;
742 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
744 struct mv643xx_eth_private *mp = netdev_priv(dev);
745 struct net_device_stats *stats = &dev->stats;
746 struct tx_queue *txq;
749 BUG_ON(netif_queue_stopped(dev));
751 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
753 dev_printk(KERN_DEBUG, &dev->dev,
754 "failed to linearize skb with tiny "
755 "unaligned fragment\n");
756 return NETDEV_TX_BUSY;
759 spin_lock_irqsave(&mp->lock, flags);
763 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
764 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
765 netif_stop_queue(dev);
766 spin_unlock_irqrestore(&mp->lock, flags);
767 return NETDEV_TX_BUSY;
770 txq_submit_skb(txq, skb);
771 stats->tx_bytes += skb->len;
773 dev->trans_start = jiffies;
775 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB)
776 netif_stop_queue(dev);
778 spin_unlock_irqrestore(&mp->lock, flags);
784 /* tx rate control **********************************************************/
786 * Set total maximum TX rate (shared by all TX queues for this port)
787 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
789 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
795 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
796 if (token_rate > 1023)
799 mtu = (mp->dev->mtu + 255) >> 8;
803 bucket_size = (burst + 255) >> 8;
804 if (bucket_size > 65535)
807 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
808 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
809 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
812 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
814 struct mv643xx_eth_private *mp = txq_to_mp(txq);
818 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
819 if (token_rate > 1023)
822 bucket_size = (burst + 255) >> 8;
823 if (bucket_size > 65535)
826 wrl(mp, TXQ_BW_TOKENS(mp->port_num), token_rate << 14);
827 wrl(mp, TXQ_BW_CONF(mp->port_num),
828 (bucket_size << 10) | token_rate);
831 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
833 struct mv643xx_eth_private *mp = txq_to_mp(txq);
838 * Turn on fixed priority mode.
840 off = TXQ_FIX_PRIO_CONF(mp->port_num);
847 static void txq_set_wrr(struct tx_queue *txq, int weight)
849 struct mv643xx_eth_private *mp = txq_to_mp(txq);
854 * Turn off fixed priority mode.
856 off = TXQ_FIX_PRIO_CONF(mp->port_num);
863 * Configure WRR weight for this queue.
865 off = TXQ_BW_WRR_CONF(mp->port_num);
868 val = (val & ~0xff) | (weight & 0xff);
873 /* mii management interface *************************************************/
874 #define SMI_BUSY 0x10000000
875 #define SMI_READ_VALID 0x08000000
876 #define SMI_OPCODE_READ 0x04000000
877 #define SMI_OPCODE_WRITE 0x00000000
879 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
880 unsigned int reg, unsigned int *value)
882 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
886 /* the SMI register is a shared resource */
887 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
889 /* wait for the SMI register to become available */
890 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
892 printk("%s: PHY busy timeout\n", mp->dev->name);
898 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
900 /* now wait for the data to be valid */
901 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
903 printk("%s: PHY read timeout\n", mp->dev->name);
909 *value = readl(smi_reg) & 0xffff;
911 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
914 static void smi_reg_write(struct mv643xx_eth_private *mp,
916 unsigned int reg, unsigned int value)
918 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
922 /* the SMI register is a shared resource */
923 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
925 /* wait for the SMI register to become available */
926 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
928 printk("%s: PHY busy timeout\n", mp->dev->name);
934 writel(SMI_OPCODE_WRITE | (reg << 21) |
935 (addr << 16) | (value & 0xffff), smi_reg);
937 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
941 /* mib counters *************************************************************/
942 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
944 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
947 static void mib_counters_clear(struct mv643xx_eth_private *mp)
951 for (i = 0; i < 0x80; i += 4)
955 static void mib_counters_update(struct mv643xx_eth_private *mp)
957 struct mib_counters *p = &mp->mib_counters;
959 p->good_octets_received += mib_read(mp, 0x00);
960 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
961 p->bad_octets_received += mib_read(mp, 0x08);
962 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
963 p->good_frames_received += mib_read(mp, 0x10);
964 p->bad_frames_received += mib_read(mp, 0x14);
965 p->broadcast_frames_received += mib_read(mp, 0x18);
966 p->multicast_frames_received += mib_read(mp, 0x1c);
967 p->frames_64_octets += mib_read(mp, 0x20);
968 p->frames_65_to_127_octets += mib_read(mp, 0x24);
969 p->frames_128_to_255_octets += mib_read(mp, 0x28);
970 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
971 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
972 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
973 p->good_octets_sent += mib_read(mp, 0x38);
974 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
975 p->good_frames_sent += mib_read(mp, 0x40);
976 p->excessive_collision += mib_read(mp, 0x44);
977 p->multicast_frames_sent += mib_read(mp, 0x48);
978 p->broadcast_frames_sent += mib_read(mp, 0x4c);
979 p->unrec_mac_control_received += mib_read(mp, 0x50);
980 p->fc_sent += mib_read(mp, 0x54);
981 p->good_fc_received += mib_read(mp, 0x58);
982 p->bad_fc_received += mib_read(mp, 0x5c);
983 p->undersize_received += mib_read(mp, 0x60);
984 p->fragments_received += mib_read(mp, 0x64);
985 p->oversize_received += mib_read(mp, 0x68);
986 p->jabber_received += mib_read(mp, 0x6c);
987 p->mac_receive_error += mib_read(mp, 0x70);
988 p->bad_crc_event += mib_read(mp, 0x74);
989 p->collision += mib_read(mp, 0x78);
990 p->late_collision += mib_read(mp, 0x7c);
994 /* ethtool ******************************************************************/
995 struct mv643xx_eth_stats {
996 char stat_string[ETH_GSTRING_LEN];
1003 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1004 offsetof(struct net_device, stats.m), -1 }
1006 #define MIBSTAT(m) \
1007 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1008 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1010 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1019 MIBSTAT(good_octets_received),
1020 MIBSTAT(bad_octets_received),
1021 MIBSTAT(internal_mac_transmit_err),
1022 MIBSTAT(good_frames_received),
1023 MIBSTAT(bad_frames_received),
1024 MIBSTAT(broadcast_frames_received),
1025 MIBSTAT(multicast_frames_received),
1026 MIBSTAT(frames_64_octets),
1027 MIBSTAT(frames_65_to_127_octets),
1028 MIBSTAT(frames_128_to_255_octets),
1029 MIBSTAT(frames_256_to_511_octets),
1030 MIBSTAT(frames_512_to_1023_octets),
1031 MIBSTAT(frames_1024_to_max_octets),
1032 MIBSTAT(good_octets_sent),
1033 MIBSTAT(good_frames_sent),
1034 MIBSTAT(excessive_collision),
1035 MIBSTAT(multicast_frames_sent),
1036 MIBSTAT(broadcast_frames_sent),
1037 MIBSTAT(unrec_mac_control_received),
1039 MIBSTAT(good_fc_received),
1040 MIBSTAT(bad_fc_received),
1041 MIBSTAT(undersize_received),
1042 MIBSTAT(fragments_received),
1043 MIBSTAT(oversize_received),
1044 MIBSTAT(jabber_received),
1045 MIBSTAT(mac_receive_error),
1046 MIBSTAT(bad_crc_event),
1048 MIBSTAT(late_collision),
1051 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1053 struct mv643xx_eth_private *mp = netdev_priv(dev);
1056 spin_lock_irq(&mp->lock);
1057 err = mii_ethtool_gset(&mp->mii, cmd);
1058 spin_unlock_irq(&mp->lock);
1061 * The MAC does not support 1000baseT_Half.
1063 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1064 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1069 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1071 struct mv643xx_eth_private *mp = netdev_priv(dev);
1075 * The MAC does not support 1000baseT_Half.
1077 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1079 spin_lock_irq(&mp->lock);
1080 err = mii_ethtool_sset(&mp->mii, cmd);
1081 spin_unlock_irq(&mp->lock);
1086 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1087 struct ethtool_drvinfo *drvinfo)
1089 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1090 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1091 strncpy(drvinfo->fw_version, "N/A", 32);
1092 strncpy(drvinfo->bus_info, "platform", 32);
1093 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1096 static int mv643xx_eth_nway_reset(struct net_device *dev)
1098 struct mv643xx_eth_private *mp = netdev_priv(dev);
1100 return mii_nway_restart(&mp->mii);
1103 static u32 mv643xx_eth_get_link(struct net_device *dev)
1105 struct mv643xx_eth_private *mp = netdev_priv(dev);
1107 return mii_link_ok(&mp->mii);
1110 static void mv643xx_eth_get_strings(struct net_device *dev,
1111 uint32_t stringset, uint8_t *data)
1115 if (stringset == ETH_SS_STATS) {
1116 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1117 memcpy(data + i * ETH_GSTRING_LEN,
1118 mv643xx_eth_stats[i].stat_string,
1124 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1125 struct ethtool_stats *stats,
1128 struct mv643xx_eth_private *mp = dev->priv;
1131 mib_counters_update(mp);
1133 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1134 const struct mv643xx_eth_stats *stat;
1137 stat = mv643xx_eth_stats + i;
1139 if (stat->netdev_off >= 0)
1140 p = ((void *)mp->dev) + stat->netdev_off;
1142 p = ((void *)mp) + stat->mp_off;
1144 data[i] = (stat->sizeof_stat == 8) ?
1145 *(uint64_t *)p : *(uint32_t *)p;
1149 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1151 if (sset == ETH_SS_STATS)
1152 return ARRAY_SIZE(mv643xx_eth_stats);
1157 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1158 .get_settings = mv643xx_eth_get_settings,
1159 .set_settings = mv643xx_eth_set_settings,
1160 .get_drvinfo = mv643xx_eth_get_drvinfo,
1161 .nway_reset = mv643xx_eth_nway_reset,
1162 .get_link = mv643xx_eth_get_link,
1163 .set_sg = ethtool_op_set_sg,
1164 .get_strings = mv643xx_eth_get_strings,
1165 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1166 .get_sset_count = mv643xx_eth_get_sset_count,
1170 /* address handling *********************************************************/
1171 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1176 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1177 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1179 addr[0] = (mac_h >> 24) & 0xff;
1180 addr[1] = (mac_h >> 16) & 0xff;
1181 addr[2] = (mac_h >> 8) & 0xff;
1182 addr[3] = mac_h & 0xff;
1183 addr[4] = (mac_l >> 8) & 0xff;
1184 addr[5] = mac_l & 0xff;
1187 static void init_mac_tables(struct mv643xx_eth_private *mp)
1191 for (i = 0; i < 0x100; i += 4) {
1192 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1193 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1196 for (i = 0; i < 0x10; i += 4)
1197 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1200 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1201 int table, unsigned char entry)
1203 unsigned int table_reg;
1205 /* Set "accepts frame bit" at specified table entry */
1206 table_reg = rdl(mp, table + (entry & 0xfc));
1207 table_reg |= 0x01 << (8 * (entry & 3));
1208 wrl(mp, table + (entry & 0xfc), table_reg);
1211 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1217 mac_l = (addr[4] << 8) | addr[5];
1218 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1220 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1221 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1223 table = UNICAST_TABLE(mp->port_num);
1224 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1227 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1229 struct mv643xx_eth_private *mp = netdev_priv(dev);
1231 /* +2 is for the offset of the HW addr type */
1232 memcpy(dev->dev_addr, addr + 2, 6);
1234 init_mac_tables(mp);
1235 uc_addr_set(mp, dev->dev_addr);
1240 static int addr_crc(unsigned char *addr)
1245 for (i = 0; i < 6; i++) {
1248 crc = (crc ^ addr[i]) << 8;
1249 for (j = 7; j >= 0; j--) {
1250 if (crc & (0x100 << j))
1258 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1260 struct mv643xx_eth_private *mp = netdev_priv(dev);
1262 struct dev_addr_list *addr;
1265 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1266 if (dev->flags & IFF_PROMISC)
1267 port_config |= UNICAST_PROMISCUOUS_MODE;
1269 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1270 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1272 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1273 int port_num = mp->port_num;
1274 u32 accept = 0x01010101;
1276 for (i = 0; i < 0x100; i += 4) {
1277 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1278 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1283 for (i = 0; i < 0x100; i += 4) {
1284 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1285 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1288 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1289 u8 *a = addr->da_addr;
1292 if (addr->da_addrlen != 6)
1295 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1296 table = SPECIAL_MCAST_TABLE(mp->port_num);
1297 set_filter_table_entry(mp, table, a[5]);
1299 int crc = addr_crc(a);
1301 table = OTHER_MCAST_TABLE(mp->port_num);
1302 set_filter_table_entry(mp, table, crc);
1308 /* rx/tx queue initialisation ***********************************************/
1309 static int rxq_init(struct mv643xx_eth_private *mp)
1311 struct rx_queue *rxq = mp->rxq;
1312 struct rx_desc *rx_desc;
1316 rxq->rx_ring_size = mp->default_rx_ring_size;
1318 rxq->rx_desc_count = 0;
1319 rxq->rx_curr_desc = 0;
1320 rxq->rx_used_desc = 0;
1322 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1324 if (size <= mp->rx_desc_sram_size) {
1325 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1326 mp->rx_desc_sram_size);
1327 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1329 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1334 if (rxq->rx_desc_area == NULL) {
1335 dev_printk(KERN_ERR, &mp->dev->dev,
1336 "can't allocate rx ring (%d bytes)\n", size);
1339 memset(rxq->rx_desc_area, 0, size);
1341 rxq->rx_desc_area_size = size;
1342 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1344 if (rxq->rx_skb == NULL) {
1345 dev_printk(KERN_ERR, &mp->dev->dev,
1346 "can't allocate rx skb ring\n");
1350 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1351 for (i = 0; i < rxq->rx_ring_size; i++) {
1352 int nexti = (i + 1) % rxq->rx_ring_size;
1353 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1354 nexti * sizeof(struct rx_desc);
1357 init_timer(&rxq->rx_oom);
1358 rxq->rx_oom.data = (unsigned long)rxq;
1359 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1365 if (size <= mp->rx_desc_sram_size)
1366 iounmap(rxq->rx_desc_area);
1368 dma_free_coherent(NULL, size,
1376 static void rxq_deinit(struct rx_queue *rxq)
1378 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1383 del_timer_sync(&rxq->rx_oom);
1385 for (i = 0; i < rxq->rx_ring_size; i++) {
1386 if (rxq->rx_skb[i]) {
1387 dev_kfree_skb(rxq->rx_skb[i]);
1388 rxq->rx_desc_count--;
1392 if (rxq->rx_desc_count) {
1393 dev_printk(KERN_ERR, &mp->dev->dev,
1394 "error freeing rx ring -- %d skbs stuck\n",
1395 rxq->rx_desc_count);
1398 if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1399 iounmap(rxq->rx_desc_area);
1401 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1402 rxq->rx_desc_area, rxq->rx_desc_dma);
1407 static int txq_init(struct mv643xx_eth_private *mp)
1409 struct tx_queue *txq = mp->txq;
1410 struct tx_desc *tx_desc;
1414 txq->tx_ring_size = mp->default_tx_ring_size;
1416 txq->tx_desc_count = 0;
1417 txq->tx_curr_desc = 0;
1418 txq->tx_used_desc = 0;
1420 size = txq->tx_ring_size * sizeof(struct tx_desc);
1422 if (size <= mp->tx_desc_sram_size) {
1423 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1424 mp->tx_desc_sram_size);
1425 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1427 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1432 if (txq->tx_desc_area == NULL) {
1433 dev_printk(KERN_ERR, &mp->dev->dev,
1434 "can't allocate tx ring (%d bytes)\n", size);
1437 memset(txq->tx_desc_area, 0, size);
1439 txq->tx_desc_area_size = size;
1440 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1442 if (txq->tx_skb == NULL) {
1443 dev_printk(KERN_ERR, &mp->dev->dev,
1444 "can't allocate tx skb ring\n");
1448 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1449 for (i = 0; i < txq->tx_ring_size; i++) {
1450 int nexti = (i + 1) % txq->tx_ring_size;
1451 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1452 nexti * sizeof(struct tx_desc);
1459 if (size <= mp->tx_desc_sram_size)
1460 iounmap(txq->tx_desc_area);
1462 dma_free_coherent(NULL, size,
1470 static void txq_reclaim(struct tx_queue *txq, int force)
1472 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1473 unsigned long flags;
1475 spin_lock_irqsave(&mp->lock, flags);
1476 while (txq->tx_desc_count > 0) {
1478 struct tx_desc *desc;
1480 struct sk_buff *skb;
1484 tx_index = txq->tx_used_desc;
1485 desc = &txq->tx_desc_area[tx_index];
1486 cmd_sts = desc->cmd_sts;
1488 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1491 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1492 txq->tx_desc_count--;
1494 addr = desc->buf_ptr;
1495 count = desc->byte_cnt;
1496 skb = txq->tx_skb[tx_index];
1497 txq->tx_skb[tx_index] = NULL;
1499 if (cmd_sts & ERROR_SUMMARY) {
1500 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1501 mp->dev->stats.tx_errors++;
1505 * Drop mp->lock while we free the skb.
1507 spin_unlock_irqrestore(&mp->lock, flags);
1509 if (cmd_sts & TX_FIRST_DESC)
1510 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1512 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1515 dev_kfree_skb_irq(skb);
1517 spin_lock_irqsave(&mp->lock, flags);
1519 spin_unlock_irqrestore(&mp->lock, flags);
1522 static void txq_deinit(struct tx_queue *txq)
1524 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1527 txq_reclaim(txq, 1);
1529 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1531 if (txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1532 iounmap(txq->tx_desc_area);
1534 dma_free_coherent(NULL, txq->tx_desc_area_size,
1535 txq->tx_desc_area, txq->tx_desc_dma);
1541 /* netdev ops and related ***************************************************/
1542 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1547 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1549 /* clear speed, duplex and rx buffer size fields */
1550 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1551 SET_GMII_SPEED_TO_1000 |
1552 SET_FULL_DUPLEX_MODE |
1553 MAX_RX_PACKET_MASK);
1555 if (speed == SPEED_1000) {
1556 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1558 if (speed == SPEED_100)
1559 pscr_n |= SET_MII_SPEED_TO_100;
1560 pscr_n |= MAX_RX_PACKET_1522BYTE;
1563 if (duplex == DUPLEX_FULL)
1564 pscr_n |= SET_FULL_DUPLEX_MODE;
1566 if (pscr_n != pscr_o) {
1567 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1568 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1570 txq_disable(mp->txq);
1571 pscr_o &= ~SERIAL_PORT_ENABLE;
1572 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1573 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1574 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1575 txq_enable(mp->txq);
1580 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1582 struct net_device *dev = (struct net_device *)dev_id;
1583 struct mv643xx_eth_private *mp = netdev_priv(dev);
1587 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
1592 if (int_cause & INT_EXT) {
1593 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1594 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1595 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1598 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1599 if (mii_link_ok(&mp->mii)) {
1600 struct ethtool_cmd cmd;
1602 mii_ethtool_gset(&mp->mii, &cmd);
1603 update_pscr(mp, cmd.speed, cmd.duplex);
1604 txq_enable(mp->txq);
1605 if (!netif_carrier_ok(dev)) {
1606 netif_carrier_on(dev);
1607 __txq_maybe_wake(mp->txq);
1609 } else if (netif_carrier_ok(dev)) {
1610 netif_stop_queue(dev);
1611 netif_carrier_off(dev);
1615 #ifdef MV643XX_ETH_NAPI
1616 if (int_cause & INT_RX) {
1617 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1618 rdl(mp, INT_MASK(mp->port_num));
1620 netif_rx_schedule(dev, &mp->napi);
1623 if (int_cause & INT_RX)
1624 rxq_process(mp->rxq, INT_MAX);
1627 if (int_cause_ext & INT_EXT_TX) {
1628 txq_reclaim(mp->txq, 0);
1629 __txq_maybe_wake(mp->txq);
1635 static void phy_reset(struct mv643xx_eth_private *mp)
1639 smi_reg_read(mp, mp->phy_addr, 0, &data);
1641 smi_reg_write(mp, mp->phy_addr, 0, data);
1645 smi_reg_read(mp, mp->phy_addr, 0, &data);
1646 } while (data & 0x8000);
1649 static void port_start(struct mv643xx_eth_private *mp)
1652 struct ethtool_cmd ethtool_cmd;
1656 * Configure basic link parameters.
1658 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1659 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1660 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1661 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1662 DISABLE_AUTO_NEG_SPEED_GMII |
1663 DISABLE_AUTO_NEG_FOR_DUPLEX |
1664 DO_NOT_FORCE_LINK_FAIL |
1665 SERIAL_PORT_CONTROL_RESERVED;
1666 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1667 pscr |= SERIAL_PORT_ENABLE;
1668 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1670 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1672 mv643xx_eth_get_settings(mp->dev, ðtool_cmd);
1674 mv643xx_eth_set_settings(mp->dev, ðtool_cmd);
1677 * Configure TX path and queues.
1679 tx_set_rate(mp, 1000000000, 16777216);
1680 for (i = 0; i < 1; i++) {
1681 struct tx_queue *txq = mp->txq;
1682 int off = TXQ_CURRENT_DESC_PTR(mp->port_num);
1685 addr = (u32)txq->tx_desc_dma;
1686 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1689 txq_set_rate(txq, 1000000000, 16777216);
1690 txq_set_fixed_prio_mode(txq);
1694 * Add configured unicast address to address filter table.
1696 uc_addr_set(mp, mp->dev->dev_addr);
1699 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1700 * frames to RX queue #0.
1702 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1705 * Treat BPDUs as normal multicasts, and disable partition mode.
1707 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1710 * Enable the receive queue.
1712 for (i = 0; i < 1; i++) {
1713 struct rx_queue *rxq = mp->rxq;
1714 int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
1717 addr = (u32)rxq->rx_desc_dma;
1718 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1725 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1727 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1732 wrl(mp, SDMA_CONFIG(mp->port_num),
1733 ((coal & 0x3fff) << 8) |
1734 (rdl(mp, SDMA_CONFIG(mp->port_num))
1738 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1740 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1744 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1747 static int mv643xx_eth_open(struct net_device *dev)
1749 struct mv643xx_eth_private *mp = netdev_priv(dev);
1752 wrl(mp, INT_CAUSE(mp->port_num), 0);
1753 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1754 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1756 err = request_irq(dev->irq, mv643xx_eth_irq,
1757 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1760 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1764 init_mac_tables(mp);
1769 rxq_refill(mp->rxq);
1775 #ifdef MV643XX_ETH_NAPI
1776 napi_enable(&mp->napi);
1784 wrl(mp, INT_MASK_EXT(mp->port_num),
1785 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1787 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
1793 rxq_deinit(mp->rxq);
1795 free_irq(dev->irq, dev);
1800 static void port_reset(struct mv643xx_eth_private *mp)
1804 txq_disable(mp->txq);
1805 rxq_disable(mp->rxq);
1806 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1809 /* Reset the Enable bit in the Configuration Register */
1810 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1811 data &= ~(SERIAL_PORT_ENABLE |
1812 DO_NOT_FORCE_LINK_FAIL |
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1817 static int mv643xx_eth_stop(struct net_device *dev)
1819 struct mv643xx_eth_private *mp = netdev_priv(dev);
1821 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1822 rdl(mp, INT_MASK(mp->port_num));
1824 #ifdef MV643XX_ETH_NAPI
1825 napi_disable(&mp->napi);
1827 netif_carrier_off(dev);
1828 netif_stop_queue(dev);
1830 free_irq(dev->irq, dev);
1833 mib_counters_update(mp);
1835 txq_deinit(mp->txq);
1836 rxq_deinit(mp->rxq);
1841 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1843 struct mv643xx_eth_private *mp = netdev_priv(dev);
1845 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1848 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1850 struct mv643xx_eth_private *mp = netdev_priv(dev);
1852 if (new_mtu < 64 || new_mtu > 9500)
1856 tx_set_rate(mp, 1000000000, 16777216);
1858 if (!netif_running(dev))
1862 * Stop and then re-open the interface. This will allocate RX
1863 * skbs of the new MTU.
1864 * There is a possible danger that the open will not succeed,
1865 * due to memory being full.
1867 mv643xx_eth_stop(dev);
1868 if (mv643xx_eth_open(dev)) {
1869 dev_printk(KERN_ERR, &dev->dev,
1870 "fatal error on re-opening device after "
1877 static void tx_timeout_task(struct work_struct *ugly)
1879 struct mv643xx_eth_private *mp;
1881 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1882 if (netif_running(mp->dev)) {
1883 netif_stop_queue(mp->dev);
1888 __txq_maybe_wake(mp->txq);
1892 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1894 struct mv643xx_eth_private *mp = netdev_priv(dev);
1896 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
1898 schedule_work(&mp->tx_timeout_task);
1901 #ifdef CONFIG_NET_POLL_CONTROLLER
1902 static void mv643xx_eth_netpoll(struct net_device *dev)
1904 struct mv643xx_eth_private *mp = netdev_priv(dev);
1906 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1907 rdl(mp, INT_MASK(mp->port_num));
1909 mv643xx_eth_irq(dev->irq, dev);
1911 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
1915 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
1917 struct mv643xx_eth_private *mp = netdev_priv(dev);
1920 smi_reg_read(mp, addr, reg, &val);
1925 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
1927 struct mv643xx_eth_private *mp = netdev_priv(dev);
1928 smi_reg_write(mp, addr, reg, val);
1932 /* platform glue ************************************************************/
1934 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1935 struct mbus_dram_target_info *dram)
1937 void __iomem *base = msp->base;
1942 for (i = 0; i < 6; i++) {
1943 writel(0, base + WINDOW_BASE(i));
1944 writel(0, base + WINDOW_SIZE(i));
1946 writel(0, base + WINDOW_REMAP_HIGH(i));
1952 for (i = 0; i < dram->num_cs; i++) {
1953 struct mbus_dram_window *cs = dram->cs + i;
1955 writel((cs->base & 0xffff0000) |
1956 (cs->mbus_attr << 8) |
1957 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1958 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1960 win_enable &= ~(1 << i);
1961 win_protect |= 3 << (2 * i);
1964 writel(win_enable, base + WINDOW_BAR_ENABLE);
1965 msp->win_protect = win_protect;
1968 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1970 static int mv643xx_eth_version_printed = 0;
1971 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
1972 struct mv643xx_eth_shared_private *msp;
1973 struct resource *res;
1976 if (!mv643xx_eth_version_printed++)
1977 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1985 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
1988 memset(msp, 0, sizeof(*msp));
1990 msp->base = ioremap(res->start, res->end - res->start + 1);
1991 if (msp->base == NULL)
1994 spin_lock_init(&msp->phy_lock);
1997 * (Re-)program MBUS remapping windows if we are asked to.
1999 if (pd != NULL && pd->dram != NULL)
2000 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2003 * Detect hardware parameters.
2005 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2007 platform_set_drvdata(pdev, msp);
2017 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2019 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2027 static struct platform_driver mv643xx_eth_shared_driver = {
2028 .probe = mv643xx_eth_shared_probe,
2029 .remove = mv643xx_eth_shared_remove,
2031 .name = MV643XX_ETH_SHARED_NAME,
2032 .owner = THIS_MODULE,
2036 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2038 int addr_shift = 5 * mp->port_num;
2041 data = rdl(mp, PHY_ADDR);
2042 data &= ~(0x1f << addr_shift);
2043 data |= (phy_addr & 0x1f) << addr_shift;
2044 wrl(mp, PHY_ADDR, data);
2047 static int phy_addr_get(struct mv643xx_eth_private *mp)
2051 data = rdl(mp, PHY_ADDR);
2053 return (data >> (5 * mp->port_num)) & 0x1f;
2056 static void set_params(struct mv643xx_eth_private *mp,
2057 struct mv643xx_eth_platform_data *pd)
2059 struct net_device *dev = mp->dev;
2061 if (is_valid_ether_addr(pd->mac_addr))
2062 memcpy(dev->dev_addr, pd->mac_addr, 6);
2064 uc_addr_get(mp, dev->dev_addr);
2066 if (pd->phy_addr == -1) {
2067 mp->shared_smi = NULL;
2070 mp->shared_smi = mp->shared;
2071 if (pd->shared_smi != NULL)
2072 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2074 if (pd->force_phy_addr || pd->phy_addr) {
2075 mp->phy_addr = pd->phy_addr & 0x3f;
2076 phy_addr_set(mp, mp->phy_addr);
2078 mp->phy_addr = phy_addr_get(mp);
2082 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2083 if (pd->rx_queue_size)
2084 mp->default_rx_ring_size = pd->rx_queue_size;
2085 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2086 mp->rx_desc_sram_size = pd->rx_sram_size;
2088 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2089 if (pd->tx_queue_size)
2090 mp->default_tx_ring_size = pd->tx_queue_size;
2091 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2092 mp->tx_desc_sram_size = pd->tx_sram_size;
2095 static int phy_detect(struct mv643xx_eth_private *mp)
2100 smi_reg_read(mp, mp->phy_addr, 0, &data);
2101 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2103 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2104 if (((data ^ data2) & 0x1000) == 0)
2107 smi_reg_write(mp, mp->phy_addr, 0, data);
2112 static int phy_init(struct mv643xx_eth_private *mp,
2113 struct mv643xx_eth_platform_data *pd)
2115 struct ethtool_cmd cmd;
2118 err = phy_detect(mp);
2120 dev_printk(KERN_INFO, &mp->dev->dev,
2121 "no PHY detected at addr %d\n", mp->phy_addr);
2126 mp->mii.phy_id = mp->phy_addr;
2127 mp->mii.phy_id_mask = 0x3f;
2128 mp->mii.reg_num_mask = 0x1f;
2129 mp->mii.dev = mp->dev;
2130 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2131 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2133 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2135 memset(&cmd, 0, sizeof(cmd));
2137 cmd.port = PORT_MII;
2138 cmd.transceiver = XCVR_INTERNAL;
2139 cmd.phy_address = mp->phy_addr;
2140 if (pd->speed == 0) {
2141 cmd.autoneg = AUTONEG_ENABLE;
2142 cmd.speed = SPEED_100;
2143 cmd.advertising = ADVERTISED_10baseT_Half |
2144 ADVERTISED_10baseT_Full |
2145 ADVERTISED_100baseT_Half |
2146 ADVERTISED_100baseT_Full;
2147 if (mp->mii.supports_gmii)
2148 cmd.advertising |= ADVERTISED_1000baseT_Full;
2150 cmd.autoneg = AUTONEG_DISABLE;
2151 cmd.speed = pd->speed;
2152 cmd.duplex = pd->duplex;
2155 update_pscr(mp, cmd.speed, cmd.duplex);
2156 mv643xx_eth_set_settings(mp->dev, &cmd);
2161 static int mv643xx_eth_probe(struct platform_device *pdev)
2163 struct mv643xx_eth_platform_data *pd;
2164 struct mv643xx_eth_private *mp;
2165 struct net_device *dev;
2166 struct resource *res;
2167 DECLARE_MAC_BUF(mac);
2170 pd = pdev->dev.platform_data;
2172 dev_printk(KERN_ERR, &pdev->dev,
2173 "no mv643xx_eth_platform_data\n");
2177 if (pd->shared == NULL) {
2178 dev_printk(KERN_ERR, &pdev->dev,
2179 "no mv643xx_eth_platform_data->shared\n");
2183 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2187 mp = netdev_priv(dev);
2188 platform_set_drvdata(pdev, mp);
2190 mp->shared = platform_get_drvdata(pd->shared);
2191 mp->port_num = pd->port_number;
2194 #ifdef MV643XX_ETH_NAPI
2195 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2200 spin_lock_init(&mp->lock);
2202 mib_counters_clear(mp);
2203 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2205 err = phy_init(mp, pd);
2208 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2211 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2213 dev->irq = res->start;
2215 dev->hard_start_xmit = mv643xx_eth_xmit;
2216 dev->open = mv643xx_eth_open;
2217 dev->stop = mv643xx_eth_stop;
2218 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2219 dev->set_mac_address = mv643xx_eth_set_mac_address;
2220 dev->do_ioctl = mv643xx_eth_ioctl;
2221 dev->change_mtu = mv643xx_eth_change_mtu;
2222 dev->tx_timeout = mv643xx_eth_tx_timeout;
2223 #ifdef CONFIG_NET_POLL_CONTROLLER
2224 dev->poll_controller = mv643xx_eth_netpoll;
2226 dev->watchdog_timeo = 2 * HZ;
2229 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2231 * Zero copy can only work if we use Discovery II memory. Else, we will
2232 * have to map the buffers to ISA memory which is only 16 MB
2234 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2237 SET_NETDEV_DEV(dev, &pdev->dev);
2239 if (mp->shared->win_protect)
2240 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2242 err = register_netdev(dev);
2246 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2247 mp->port_num, print_mac(mac, dev->dev_addr));
2249 if (dev->features & NETIF_F_SG)
2250 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2252 if (dev->features & NETIF_F_IP_CSUM)
2253 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2255 #ifdef MV643XX_ETH_NAPI
2256 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2259 if (mp->tx_desc_sram_size > 0)
2260 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2270 static int mv643xx_eth_remove(struct platform_device *pdev)
2272 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2274 unregister_netdev(mp->dev);
2275 flush_scheduled_work();
2276 free_netdev(mp->dev);
2278 platform_set_drvdata(pdev, NULL);
2283 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2285 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2287 /* Mask all interrupts on ethernet port */
2288 wrl(mp, INT_MASK(mp->port_num), 0);
2289 rdl(mp, INT_MASK(mp->port_num));
2291 if (netif_running(mp->dev))
2295 static struct platform_driver mv643xx_eth_driver = {
2296 .probe = mv643xx_eth_probe,
2297 .remove = mv643xx_eth_remove,
2298 .shutdown = mv643xx_eth_shutdown,
2300 .name = MV643XX_ETH_NAME,
2301 .owner = THIS_MODULE,
2305 static int __init mv643xx_eth_init_module(void)
2309 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2311 rc = platform_driver_register(&mv643xx_eth_driver);
2313 platform_driver_unregister(&mv643xx_eth_shared_driver);
2318 module_init(mv643xx_eth_init_module);
2320 static void __exit mv643xx_eth_cleanup_module(void)
2322 platform_driver_unregister(&mv643xx_eth_driver);
2323 platform_driver_unregister(&mv643xx_eth_shared_driver);
2325 module_exit(mv643xx_eth_cleanup_module);
2327 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2328 "and Dale Farnsworth");
2329 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2330 MODULE_LICENSE("GPL");
2331 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2332 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);