2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63 #undef MV643XX_ETH_COAL
65 #define MV643XX_ETH_TX_COAL 100
66 #ifdef MV643XX_ETH_COAL
67 #define MV643XX_ETH_RX_COAL 100
70 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TX_FIFO_EMPTY 0x00000400
107 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
109 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
110 #define INT_RX 0x00000804
111 #define INT_EXT 0x00000002
112 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
113 #define INT_EXT_LINK 0x00100000
114 #define INT_EXT_PHY 0x00010000
115 #define INT_EXT_TX_ERROR_0 0x00000100
116 #define INT_EXT_TX_0 0x00000001
117 #define INT_EXT_TX 0x00000101
118 #define INT_MASK(p) (0x0468 + ((p) << 10))
119 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
120 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
121 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
122 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
123 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_4_64BIT (2 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_4_64BIT (2 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_4_64BIT | \
141 TX_BURST_SIZE_4_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_4_64BIT | \
147 TX_BURST_SIZE_4_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_1522BYTE (1 << 17)
160 #define MAX_RX_PACKET_9700BYTE (5 << 17)
161 #define MAX_RX_PACKET_MASK (7 << 17)
162 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167 #define FORCE_LINK_PASS (1 << 1)
168 #define SERIAL_PORT_ENABLE (1 << 0)
170 #define DEFAULT_RX_QUEUE_SIZE 400
171 #define DEFAULT_TX_QUEUE_SIZE 800
174 #define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
175 #define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
176 #define SMI_OPCODE_WRITE 0 /* Completion of Read */
177 #define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
183 #if defined(__BIG_ENDIAN)
185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 #elif defined(__LITTLE_ENDIAN)
201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
216 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219 /* RX & TX descriptor command */
220 #define BUFFER_OWNED_BY_DMA 0x80000000
222 /* RX & TX descriptor status */
223 #define ERROR_SUMMARY 0x00000001
225 /* RX descriptor status */
226 #define LAYER_4_CHECKSUM_OK 0x40000000
227 #define RX_ENABLE_INTERRUPT 0x20000000
228 #define RX_FIRST_DESC 0x08000000
229 #define RX_LAST_DESC 0x04000000
231 /* TX descriptor command */
232 #define TX_ENABLE_INTERRUPT 0x00800000
233 #define GEN_CRC 0x00400000
234 #define TX_FIRST_DESC 0x00200000
235 #define TX_LAST_DESC 0x00100000
236 #define ZERO_PADDING 0x00080000
237 #define GEN_IP_V4_CHECKSUM 0x00040000
238 #define GEN_TCP_UDP_CHECKSUM 0x00020000
239 #define UDP_FRAME 0x00010000
241 #define TX_IHL_SHIFT 11
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
248 /* used to protect SMI_REG, which is shared across ports */
257 /* per-port *****************************************************************/
258 struct mib_counters {
259 u64 good_octets_received;
260 u32 bad_octets_received;
261 u32 internal_mac_transmit_err;
262 u32 good_frames_received;
263 u32 bad_frames_received;
264 u32 broadcast_frames_received;
265 u32 multicast_frames_received;
266 u32 frames_64_octets;
267 u32 frames_65_to_127_octets;
268 u32 frames_128_to_255_octets;
269 u32 frames_256_to_511_octets;
270 u32 frames_512_to_1023_octets;
271 u32 frames_1024_to_max_octets;
272 u64 good_octets_sent;
273 u32 good_frames_sent;
274 u32 excessive_collision;
275 u32 multicast_frames_sent;
276 u32 broadcast_frames_sent;
277 u32 unrec_mac_control_received;
279 u32 good_fc_received;
281 u32 undersize_received;
282 u32 fragments_received;
283 u32 oversize_received;
285 u32 mac_receive_error;
291 struct mv643xx_eth_private {
292 struct mv643xx_eth_shared_private *shared;
293 int port_num; /* User Ethernet port number */
295 struct mv643xx_eth_shared_private *shared_smi;
297 u32 rx_sram_addr; /* Base address of rx sram area */
298 u32 rx_sram_size; /* Size of rx sram area */
299 u32 tx_sram_addr; /* Base address of tx sram area */
300 u32 tx_sram_size; /* Size of tx sram area */
302 /* Tx/Rx rings managment indexes fields. For driver use */
304 /* Next available and first returning Rx resource */
305 int rx_curr_desc, rx_used_desc;
307 /* Next available and first returning Tx resource */
308 int tx_curr_desc, tx_used_desc;
310 #ifdef MV643XX_ETH_TX_FAST_REFILL
311 u32 tx_clean_threshold;
314 struct rx_desc *rx_desc_area;
315 dma_addr_t rx_desc_dma;
316 int rx_desc_area_size;
317 struct sk_buff **rx_skb;
319 struct tx_desc *tx_desc_area;
320 dma_addr_t tx_desc_dma;
321 int tx_desc_area_size;
322 struct sk_buff **tx_skb;
324 struct work_struct tx_timeout_task;
326 struct net_device *dev;
327 struct napi_struct napi;
328 struct mib_counters mib_counters;
330 /* Size of Tx Ring per queue */
332 /* Number of tx descriptors in use */
334 /* Size of Rx Ring per queue */
336 /* Number of rx descriptors in use */
340 * Used in case RX Ring is empty, which can be caused when
341 * system does not have resources (skb's)
343 struct timer_list timeout;
347 struct mii_if_info mii;
351 /* port register accessors **************************************************/
352 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
354 return readl(mp->shared->base + offset);
357 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
359 writel(data, mp->shared->base + offset);
363 /* rxq/txq helper functions *************************************************/
364 static void mv643xx_eth_port_enable_rx(struct mv643xx_eth_private *mp,
367 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
370 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_eth_private *mp)
372 unsigned int port_num = mp->port_num;
375 /* Stop Rx port activity. Check port Rx activity. */
376 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
378 /* Issue stop command for active queues only */
379 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
381 /* Wait for all Rx activity to terminate. */
382 /* Check port cause register that all Rx queues are stopped */
383 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
390 static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
393 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
396 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
398 unsigned int port_num = mp->port_num;
401 /* Stop Tx port activity. Check port Tx activity. */
402 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
404 /* Issue stop command for active queues only */
405 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
407 /* Wait for all Tx activity to terminate. */
408 /* Check port cause register that all Tx queues are stopped */
409 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
412 /* Wait for Tx FIFO to empty */
413 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
421 /* rx ***********************************************************************/
422 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
424 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
426 struct mv643xx_eth_private *mp = netdev_priv(dev);
429 spin_lock_irqsave(&mp->lock, flags);
431 while (mp->rx_desc_count < mp->rx_ring_size) {
436 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
440 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
442 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
445 rx = mp->rx_used_desc;
446 mp->rx_used_desc = (rx + 1) % mp->rx_ring_size;
448 mp->rx_desc_area[rx].buf_ptr = dma_map_single(NULL,
452 mp->rx_desc_area[rx].buf_size = ETH_RX_SKB_SIZE;
453 mp->rx_skb[rx] = skb;
455 mp->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
459 skb_reserve(skb, ETH_HW_IP_ALIGN);
462 if (mp->rx_desc_count == 0) {
463 mp->timeout.expires = jiffies + (HZ / 10);
464 add_timer(&mp->timeout);
467 spin_unlock_irqrestore(&mp->lock, flags);
470 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
472 mv643xx_eth_rx_refill_descs((struct net_device *)data);
475 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
477 struct mv643xx_eth_private *mp = netdev_priv(dev);
478 struct net_device_stats *stats = &dev->stats;
479 unsigned int received_packets = 0;
481 while (budget-- > 0) {
483 volatile struct rx_desc *rx_desc;
484 unsigned int cmd_sts;
487 spin_lock_irqsave(&mp->lock, flags);
489 rx_desc = &mp->rx_desc_area[mp->rx_curr_desc];
491 cmd_sts = rx_desc->cmd_sts;
492 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
493 spin_unlock_irqrestore(&mp->lock, flags);
498 skb = mp->rx_skb[mp->rx_curr_desc];
499 mp->rx_skb[mp->rx_curr_desc] = NULL;
501 mp->rx_curr_desc = (mp->rx_curr_desc + 1) % mp->rx_ring_size;
503 spin_unlock_irqrestore(&mp->lock, flags);
505 dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
506 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
512 * Note byte count includes 4 byte CRC count
515 stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
518 * In case received a packet without first / last bits on OR
519 * the error summary bit is on, the packets needs to be dropeed.
521 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
522 (RX_FIRST_DESC | RX_LAST_DESC))
523 || (cmd_sts & ERROR_SUMMARY)) {
525 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
526 (RX_FIRST_DESC | RX_LAST_DESC)) {
529 "%s: Received packet spread "
530 "on multiple descriptors\n",
533 if (cmd_sts & ERROR_SUMMARY)
536 dev_kfree_skb_irq(skb);
539 * The -4 is for the CRC in the trailer of the
542 skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
544 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
545 skb->ip_summed = CHECKSUM_UNNECESSARY;
547 (cmd_sts & 0x0007fff8) >> 3);
549 skb->protocol = eth_type_trans(skb, dev);
550 #ifdef MV643XX_ETH_NAPI
551 netif_receive_skb(skb);
556 dev->last_rx = jiffies;
558 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
560 return received_packets;
563 #ifdef MV643XX_ETH_NAPI
564 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
566 struct mv643xx_eth_private *mp = container_of(napi, struct mv643xx_eth_private, napi);
567 struct net_device *dev = mp->dev;
568 unsigned int port_num = mp->port_num;
571 #ifdef MV643XX_ETH_TX_FAST_REFILL
572 if (++mp->tx_clean_threshold > 5) {
573 mv643xx_eth_free_completed_tx_descs(dev);
574 mp->tx_clean_threshold = 0;
579 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
580 != (u32) mp->rx_used_desc)
581 work_done = mv643xx_eth_receive_queue(dev, budget);
583 if (work_done < budget) {
584 netif_rx_complete(dev, napi);
585 wrl(mp, INT_CAUSE(port_num), 0);
586 wrl(mp, INT_CAUSE_EXT(port_num), 0);
587 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
595 /* tx ***********************************************************************/
596 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
601 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
602 fragp = &skb_shinfo(skb)->frags[frag];
603 if (fragp->size <= 8 && fragp->page_offset & 0x7)
609 static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
613 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
615 tx_desc_curr = mp->tx_curr_desc;
616 mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
618 BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
623 static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
628 struct tx_desc *desc;
630 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
631 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
633 tx_index = alloc_tx_desc_index(mp);
634 desc = &mp->tx_desc_area[tx_index];
636 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
637 /* Last Frag enables interrupt and frees the skb */
638 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
639 desc->cmd_sts |= ZERO_PADDING |
642 mp->tx_skb[tx_index] = skb;
644 mp->tx_skb[tx_index] = NULL;
646 desc = &mp->tx_desc_area[tx_index];
648 desc->byte_cnt = this_frag->size;
649 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
650 this_frag->page_offset,
656 static inline __be16 sum16_as_be(__sum16 sum)
658 return (__force __be16)sum;
661 static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
665 struct tx_desc *desc;
668 int nr_frags = skb_shinfo(skb)->nr_frags;
670 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
672 tx_index = alloc_tx_desc_index(mp);
673 desc = &mp->tx_desc_area[tx_index];
676 tx_fill_frag_descs(mp, skb);
678 length = skb_headlen(skb);
679 mp->tx_skb[tx_index] = NULL;
681 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
683 mp->tx_skb[tx_index] = skb;
686 desc->byte_cnt = length;
687 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
689 if (skb->ip_summed == CHECKSUM_PARTIAL) {
690 BUG_ON(skb->protocol != htons(ETH_P_IP));
692 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
694 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
696 switch (ip_hdr(skb)->protocol) {
698 cmd_sts |= UDP_FRAME;
699 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
702 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
708 /* Errata BTS #50, IHL must be 5 if no HW checksum */
709 cmd_sts |= 5 << TX_IHL_SHIFT;
713 /* ensure all other descriptors are written before first cmd_sts */
715 desc->cmd_sts = cmd_sts;
717 /* ensure all descriptors are written before poking hardware */
719 mv643xx_eth_port_enable_tx(mp, 1);
721 mp->tx_desc_count += nr_frags + 1;
724 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
726 struct mv643xx_eth_private *mp = netdev_priv(dev);
727 struct net_device_stats *stats = &dev->stats;
730 BUG_ON(netif_queue_stopped(dev));
732 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
734 printk(KERN_DEBUG "%s: failed to linearize tiny "
735 "unaligned fragment\n", dev->name);
736 return NETDEV_TX_BUSY;
739 spin_lock_irqsave(&mp->lock, flags);
741 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
742 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
743 netif_stop_queue(dev);
744 spin_unlock_irqrestore(&mp->lock, flags);
745 return NETDEV_TX_BUSY;
748 tx_submit_descs_for_skb(mp, skb);
749 stats->tx_bytes += skb->len;
751 dev->trans_start = jiffies;
753 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
754 netif_stop_queue(dev);
756 spin_unlock_irqrestore(&mp->lock, flags);
762 /* mii management interface *************************************************/
763 static int phy_addr_get(struct mv643xx_eth_private *mp);
765 static void read_smi_reg(struct mv643xx_eth_private *mp,
766 unsigned int phy_reg, unsigned int *value)
768 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
769 int phy_addr = phy_addr_get(mp);
773 /* the SMI register is a shared resource */
774 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
776 /* wait for the SMI register to become available */
777 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
779 printk("%s: PHY busy timeout\n", mp->dev->name);
785 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
787 /* now wait for the data to be valid */
788 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
790 printk("%s: PHY read timeout\n", mp->dev->name);
796 *value = readl(smi_reg) & 0xffff;
798 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
801 static void write_smi_reg(struct mv643xx_eth_private *mp,
802 unsigned int phy_reg, unsigned int value)
804 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
805 int phy_addr = phy_addr_get(mp);
809 /* the SMI register is a shared resource */
810 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
812 /* wait for the SMI register to become available */
813 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
815 printk("%s: PHY busy timeout\n", mp->dev->name);
821 writel((phy_addr << 16) | (phy_reg << 21) |
822 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
824 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
828 /* mib counters *************************************************************/
829 static void clear_mib_counters(struct mv643xx_eth_private *mp)
831 unsigned int port_num = mp->port_num;
834 /* Perform dummy reads from MIB counters */
835 for (i = 0; i < 0x80; i += 4)
836 rdl(mp, MIB_COUNTERS(port_num) + i);
839 static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
841 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
844 static void update_mib_counters(struct mv643xx_eth_private *mp)
846 struct mib_counters *p = &mp->mib_counters;
848 p->good_octets_received += read_mib(mp, 0x00);
849 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
850 p->bad_octets_received += read_mib(mp, 0x08);
851 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
852 p->good_frames_received += read_mib(mp, 0x10);
853 p->bad_frames_received += read_mib(mp, 0x14);
854 p->broadcast_frames_received += read_mib(mp, 0x18);
855 p->multicast_frames_received += read_mib(mp, 0x1c);
856 p->frames_64_octets += read_mib(mp, 0x20);
857 p->frames_65_to_127_octets += read_mib(mp, 0x24);
858 p->frames_128_to_255_octets += read_mib(mp, 0x28);
859 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
860 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
861 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
862 p->good_octets_sent += read_mib(mp, 0x38);
863 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
864 p->good_frames_sent += read_mib(mp, 0x40);
865 p->excessive_collision += read_mib(mp, 0x44);
866 p->multicast_frames_sent += read_mib(mp, 0x48);
867 p->broadcast_frames_sent += read_mib(mp, 0x4c);
868 p->unrec_mac_control_received += read_mib(mp, 0x50);
869 p->fc_sent += read_mib(mp, 0x54);
870 p->good_fc_received += read_mib(mp, 0x58);
871 p->bad_fc_received += read_mib(mp, 0x5c);
872 p->undersize_received += read_mib(mp, 0x60);
873 p->fragments_received += read_mib(mp, 0x64);
874 p->oversize_received += read_mib(mp, 0x68);
875 p->jabber_received += read_mib(mp, 0x6c);
876 p->mac_receive_error += read_mib(mp, 0x70);
877 p->bad_crc_event += read_mib(mp, 0x74);
878 p->collision += read_mib(mp, 0x78);
879 p->late_collision += read_mib(mp, 0x7c);
883 /* ethtool ******************************************************************/
884 struct mv643xx_eth_stats {
885 char stat_string[ETH_GSTRING_LEN];
892 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
893 offsetof(struct net_device, stats.m), -1 }
896 { #m, FIELD_SIZEOF(struct mib_counters, m), \
897 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
899 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
908 MIBSTAT(good_octets_received),
909 MIBSTAT(bad_octets_received),
910 MIBSTAT(internal_mac_transmit_err),
911 MIBSTAT(good_frames_received),
912 MIBSTAT(bad_frames_received),
913 MIBSTAT(broadcast_frames_received),
914 MIBSTAT(multicast_frames_received),
915 MIBSTAT(frames_64_octets),
916 MIBSTAT(frames_65_to_127_octets),
917 MIBSTAT(frames_128_to_255_octets),
918 MIBSTAT(frames_256_to_511_octets),
919 MIBSTAT(frames_512_to_1023_octets),
920 MIBSTAT(frames_1024_to_max_octets),
921 MIBSTAT(good_octets_sent),
922 MIBSTAT(good_frames_sent),
923 MIBSTAT(excessive_collision),
924 MIBSTAT(multicast_frames_sent),
925 MIBSTAT(broadcast_frames_sent),
926 MIBSTAT(unrec_mac_control_received),
928 MIBSTAT(good_fc_received),
929 MIBSTAT(bad_fc_received),
930 MIBSTAT(undersize_received),
931 MIBSTAT(fragments_received),
932 MIBSTAT(oversize_received),
933 MIBSTAT(jabber_received),
934 MIBSTAT(mac_receive_error),
935 MIBSTAT(bad_crc_event),
937 MIBSTAT(late_collision),
940 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
942 struct mv643xx_eth_private *mp = netdev_priv(dev);
945 spin_lock_irq(&mp->lock);
946 err = mii_ethtool_gset(&mp->mii, cmd);
947 spin_unlock_irq(&mp->lock);
949 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
950 cmd->supported &= ~SUPPORTED_1000baseT_Half;
951 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
956 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
958 struct mv643xx_eth_private *mp = netdev_priv(dev);
961 spin_lock_irq(&mp->lock);
962 err = mii_ethtool_sset(&mp->mii, cmd);
963 spin_unlock_irq(&mp->lock);
968 static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
969 struct ethtool_drvinfo *drvinfo)
971 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
972 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
973 strncpy(drvinfo->fw_version, "N/A", 32);
974 strncpy(drvinfo->bus_info, "mv643xx", 32);
975 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
978 static int mv643xx_eth_nway_restart(struct net_device *dev)
980 struct mv643xx_eth_private *mp = netdev_priv(dev);
982 return mii_nway_restart(&mp->mii);
985 static u32 mv643xx_eth_get_link(struct net_device *dev)
987 struct mv643xx_eth_private *mp = netdev_priv(dev);
989 return mii_link_ok(&mp->mii);
992 static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
999 for (i=0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1000 memcpy(data + i * ETH_GSTRING_LEN,
1001 mv643xx_eth_stats[i].stat_string,
1008 static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
1009 struct ethtool_stats *stats, uint64_t *data)
1011 struct mv643xx_eth_private *mp = netdev->priv;
1014 update_mib_counters(mp);
1016 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1017 const struct mv643xx_eth_stats *stat;
1020 stat = mv643xx_eth_stats + i;
1022 if (stat->netdev_off >= 0)
1023 p = ((void *)mp->dev) + stat->netdev_off;
1025 p = ((void *)mp) + stat->mp_off;
1027 data[i] = (stat->sizeof_stat == 8) ?
1028 *(uint64_t *)p : *(uint32_t *)p;
1032 static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
1036 return ARRAY_SIZE(mv643xx_eth_stats);
1042 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1043 .get_settings = mv643xx_eth_get_settings,
1044 .set_settings = mv643xx_eth_set_settings,
1045 .get_drvinfo = mv643xx_eth_get_drvinfo,
1046 .get_link = mv643xx_eth_get_link,
1047 .set_sg = ethtool_op_set_sg,
1048 .get_sset_count = mv643xx_eth_get_sset_count,
1049 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1050 .get_strings = mv643xx_eth_get_strings,
1051 .nway_reset = mv643xx_eth_nway_restart,
1055 /* address handling *********************************************************/
1056 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1058 unsigned int port_num = mp->port_num;
1062 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1063 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1065 addr[0] = (mac_h >> 24) & 0xff;
1066 addr[1] = (mac_h >> 16) & 0xff;
1067 addr[2] = (mac_h >> 8) & 0xff;
1068 addr[3] = mac_h & 0xff;
1069 addr[4] = (mac_l >> 8) & 0xff;
1070 addr[5] = mac_l & 0xff;
1073 static void init_mac_tables(struct mv643xx_eth_private *mp)
1075 unsigned int port_num = mp->port_num;
1078 /* Clear DA filter unicast table (Ex_dFUT) */
1079 for (table_index = 0; table_index <= 0xC; table_index += 4)
1080 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1082 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1083 /* Clear DA filter special multicast table (Ex_dFSMT) */
1084 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1085 /* Clear DA filter other multicast table (Ex_dFOMT) */
1086 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1090 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1091 int table, unsigned char entry)
1093 unsigned int table_reg;
1094 unsigned int tbl_offset;
1095 unsigned int reg_offset;
1097 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1098 reg_offset = entry % 4; /* Entry offset within the register */
1100 /* Set "accepts frame bit" at specified table entry */
1101 table_reg = rdl(mp, table + tbl_offset);
1102 table_reg |= 0x01 << (8 * reg_offset);
1103 wrl(mp, table + tbl_offset, table_reg);
1106 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1108 unsigned int port_num = mp->port_num;
1113 mac_l = (addr[4] << 8) | (addr[5]);
1114 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1117 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1118 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1120 /* Accept frames with this address */
1121 table = UNICAST_TABLE(port_num);
1122 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1125 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1127 struct mv643xx_eth_private *mp = netdev_priv(dev);
1129 init_mac_tables(mp);
1130 uc_addr_set(mp, dev->dev_addr);
1133 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1137 for (i = 0; i < 6; i++)
1138 /* +2 is for the offset of the HW addr type */
1139 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1140 mv643xx_eth_update_mac_address(dev);
1144 static int addr_crc(unsigned char *addr)
1149 for (i = 0; i < 6; i++) {
1152 crc = (crc ^ addr[i]) << 8;
1153 for (j = 7; j >= 0; j--) {
1154 if (crc & (0x100 << j))
1162 static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
1164 unsigned int port_num = mp->port_num;
1168 if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
1169 (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
1170 table = SPECIAL_MCAST_TABLE(port_num);
1171 set_filter_table_entry(mp, table, addr[5]);
1175 crc = addr_crc(addr);
1177 table = OTHER_MCAST_TABLE(port_num);
1178 set_filter_table_entry(mp, table, crc);
1181 static void set_multicast_list(struct net_device *dev)
1184 struct dev_mc_list *mc_list;
1187 struct mv643xx_eth_private *mp = netdev_priv(dev);
1188 unsigned int port_num = mp->port_num;
1190 /* If the device is in promiscuous mode or in all multicast mode,
1191 * we will fully populate both multicast tables with accept.
1192 * This is guaranteed to yield a match on all multicast addresses...
1194 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1195 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1196 /* Set all entries in DA filter special multicast
1198 * Set for ETH_Q0 for now
1200 * 0 Accept=1, Drop=0
1201 * 3-1 Queue ETH_Q0=0
1204 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
1206 /* Set all entries in DA filter other multicast
1208 * Set for ETH_Q0 for now
1210 * 0 Accept=1, Drop=0
1211 * 3-1 Queue ETH_Q0=0
1214 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
1219 /* We will clear out multicast tables every time we get the list.
1220 * Then add the entire new list...
1222 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1223 /* Clear DA filter special multicast table (Ex_dFSMT) */
1224 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1226 /* Clear DA filter other multicast table (Ex_dFOMT) */
1227 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1230 /* Get pointer to net_device multicast list and add each one... */
1231 for (i = 0, mc_list = dev->mc_list;
1232 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1233 i++, mc_list = mc_list->next)
1234 if (mc_list->dmi_addrlen == 6)
1235 mc_addr(mp, mc_list->dmi_addr);
1238 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1240 struct mv643xx_eth_private *mp = netdev_priv(dev);
1243 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1244 if (dev->flags & IFF_PROMISC)
1245 config_reg |= UNICAST_PROMISCUOUS_MODE;
1247 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1248 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1250 set_multicast_list(dev);
1254 /* rx/tx queue initialisation ***********************************************/
1255 static void ether_init_rx_desc_ring(struct mv643xx_eth_private *mp)
1257 volatile struct rx_desc *p_rx_desc;
1258 int rx_desc_num = mp->rx_ring_size;
1261 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1262 p_rx_desc = (struct rx_desc *)mp->rx_desc_area;
1263 for (i = 0; i < rx_desc_num; i++) {
1264 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1265 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1268 /* Save Rx desc pointer to driver struct. */
1269 mp->rx_curr_desc = 0;
1270 mp->rx_used_desc = 0;
1272 mp->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1275 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1277 struct mv643xx_eth_private *mp = netdev_priv(dev);
1280 /* Stop RX Queues */
1281 mv643xx_eth_port_disable_rx(mp);
1283 /* Free preallocated skb's on RX rings */
1284 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1285 if (mp->rx_skb[curr]) {
1286 dev_kfree_skb(mp->rx_skb[curr]);
1287 mp->rx_desc_count--;
1291 if (mp->rx_desc_count)
1293 "%s: Error in freeing Rx Ring. %d skb's still"
1294 " stuck in RX Ring - ignoring them\n", dev->name,
1297 if (mp->rx_sram_size)
1298 iounmap(mp->rx_desc_area);
1300 dma_free_coherent(NULL, mp->rx_desc_area_size,
1301 mp->rx_desc_area, mp->rx_desc_dma);
1304 static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
1306 int tx_desc_num = mp->tx_ring_size;
1307 struct tx_desc *p_tx_desc;
1310 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1311 p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
1312 for (i = 0; i < tx_desc_num; i++) {
1313 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1314 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1317 mp->tx_curr_desc = 0;
1318 mp->tx_used_desc = 0;
1320 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1323 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1325 struct mv643xx_eth_private *mp = netdev_priv(dev);
1326 struct tx_desc *desc;
1328 struct sk_buff *skb;
1329 unsigned long flags;
1335 while (mp->tx_desc_count > 0) {
1336 spin_lock_irqsave(&mp->lock, flags);
1338 /* tx_desc_count might have changed before acquiring the lock */
1339 if (mp->tx_desc_count <= 0) {
1340 spin_unlock_irqrestore(&mp->lock, flags);
1344 tx_index = mp->tx_used_desc;
1345 desc = &mp->tx_desc_area[tx_index];
1346 cmd_sts = desc->cmd_sts;
1348 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
1349 spin_unlock_irqrestore(&mp->lock, flags);
1353 mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
1354 mp->tx_desc_count--;
1356 addr = desc->buf_ptr;
1357 count = desc->byte_cnt;
1358 skb = mp->tx_skb[tx_index];
1360 mp->tx_skb[tx_index] = NULL;
1362 if (cmd_sts & ERROR_SUMMARY) {
1363 printk("%s: Error in TX\n", dev->name);
1364 dev->stats.tx_errors++;
1367 spin_unlock_irqrestore(&mp->lock, flags);
1369 if (cmd_sts & TX_FIRST_DESC)
1370 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1372 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1375 dev_kfree_skb_irq(skb);
1383 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1385 struct mv643xx_eth_private *mp = netdev_priv(dev);
1387 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1388 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1389 netif_wake_queue(dev);
1392 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1394 mv643xx_eth_free_tx_descs(dev, 1);
1397 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1399 struct mv643xx_eth_private *mp = netdev_priv(dev);
1401 /* Stop Tx Queues */
1402 mv643xx_eth_port_disable_tx(mp);
1404 /* Free outstanding skb's on TX ring */
1405 mv643xx_eth_free_all_tx_descs(dev);
1407 BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
1410 if (mp->tx_sram_size)
1411 iounmap(mp->tx_desc_area);
1413 dma_free_coherent(NULL, mp->tx_desc_area_size,
1414 mp->tx_desc_area, mp->tx_desc_dma);
1418 /* netdev ops and related ***************************************************/
1419 static void port_reset(struct mv643xx_eth_private *mp);
1421 static void mv643xx_eth_update_pscr(struct net_device *dev,
1422 struct ethtool_cmd *ecmd)
1424 struct mv643xx_eth_private *mp = netdev_priv(dev);
1425 int port_num = mp->port_num;
1427 unsigned int queues;
1429 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1432 /* clear speed, duplex and rx buffer size fields */
1433 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1434 SET_GMII_SPEED_TO_1000 |
1435 SET_FULL_DUPLEX_MODE |
1436 MAX_RX_PACKET_MASK);
1438 if (ecmd->duplex == DUPLEX_FULL)
1439 n_pscr |= SET_FULL_DUPLEX_MODE;
1441 if (ecmd->speed == SPEED_1000)
1442 n_pscr |= SET_GMII_SPEED_TO_1000 |
1443 MAX_RX_PACKET_9700BYTE;
1445 if (ecmd->speed == SPEED_100)
1446 n_pscr |= SET_MII_SPEED_TO_100;
1447 n_pscr |= MAX_RX_PACKET_1522BYTE;
1450 if (n_pscr != o_pscr) {
1451 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1452 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1454 queues = mv643xx_eth_port_disable_tx(mp);
1456 o_pscr &= ~SERIAL_PORT_ENABLE;
1457 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1458 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1459 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1461 mv643xx_eth_port_enable_tx(mp, queues);
1466 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1468 struct net_device *dev = (struct net_device *)dev_id;
1469 struct mv643xx_eth_private *mp = netdev_priv(dev);
1470 u32 int_cause, int_cause_ext = 0;
1471 unsigned int port_num = mp->port_num;
1473 /* Read interrupt cause registers */
1474 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1475 if (int_cause & INT_EXT) {
1476 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1477 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1478 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
1481 /* PHY status changed */
1482 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1483 struct ethtool_cmd cmd;
1485 if (mii_link_ok(&mp->mii)) {
1486 mii_ethtool_gset(&mp->mii, &cmd);
1487 mv643xx_eth_update_pscr(dev, &cmd);
1488 mv643xx_eth_port_enable_tx(mp, 1);
1489 if (!netif_carrier_ok(dev)) {
1490 netif_carrier_on(dev);
1491 if (mp->tx_ring_size - mp->tx_desc_count >=
1493 netif_wake_queue(dev);
1495 } else if (netif_carrier_ok(dev)) {
1496 netif_stop_queue(dev);
1497 netif_carrier_off(dev);
1501 #ifdef MV643XX_ETH_NAPI
1502 if (int_cause & INT_RX) {
1503 /* schedule the NAPI poll routine to maintain port */
1504 wrl(mp, INT_MASK(port_num), 0x00000000);
1506 /* wait for previous write to complete */
1507 rdl(mp, INT_MASK(port_num));
1509 netif_rx_schedule(dev, &mp->napi);
1512 if (int_cause & INT_RX)
1513 mv643xx_eth_receive_queue(dev, INT_MAX);
1515 if (int_cause_ext & INT_EXT_TX)
1516 mv643xx_eth_free_completed_tx_descs(dev);
1519 * If no real interrupt occured, exit.
1520 * This can happen when using gigE interrupt coalescing mechanism.
1522 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
1528 static void phy_reset(struct mv643xx_eth_private *mp)
1530 unsigned int phy_reg_data;
1533 read_smi_reg(mp, 0, &phy_reg_data);
1534 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
1535 write_smi_reg(mp, 0, phy_reg_data);
1537 /* wait for PHY to come out of reset */
1540 read_smi_reg(mp, 0, &phy_reg_data);
1541 } while (phy_reg_data & 0x8000);
1544 static void port_start(struct net_device *dev)
1546 struct mv643xx_eth_private *mp = netdev_priv(dev);
1547 unsigned int port_num = mp->port_num;
1548 int tx_curr_desc, rx_curr_desc;
1550 struct ethtool_cmd ethtool_cmd;
1552 /* Assignment of Tx CTRP of given queue */
1553 tx_curr_desc = mp->tx_curr_desc;
1554 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
1555 (u32)((struct tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1557 /* Assignment of Rx CRDP of given queue */
1558 rx_curr_desc = mp->rx_curr_desc;
1559 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
1560 (u32)((struct rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1562 /* Add the assigned Ethernet address to the port's address table */
1563 uc_addr_set(mp, dev->dev_addr);
1566 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1567 * frames to RX queue #0.
1569 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
1572 * Treat BPDUs as normal multicasts, and disable partition mode.
1574 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
1576 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1578 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1579 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1581 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1582 DISABLE_AUTO_NEG_SPEED_GMII |
1583 DISABLE_AUTO_NEG_FOR_DUPLEX |
1584 DO_NOT_FORCE_LINK_FAIL |
1585 SERIAL_PORT_CONTROL_RESERVED;
1587 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1589 pscr |= SERIAL_PORT_ENABLE;
1590 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1592 /* Assign port SDMA configuration */
1593 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1595 /* Enable port Rx. */
1596 mv643xx_eth_port_enable_rx(mp, 1);
1598 /* Disable port bandwidth limits by clearing MTU register */
1599 wrl(mp, TX_BW_MTU(port_num), 0);
1601 /* save phy settings across reset */
1602 mv643xx_eth_get_settings(dev, ðtool_cmd);
1604 mv643xx_eth_set_settings(dev, ðtool_cmd);
1607 #ifdef MV643XX_ETH_COAL
1608 static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
1611 unsigned int port_num = mp->port_num;
1612 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1614 /* Set RX Coalescing mechanism */
1615 wrl(mp, SDMA_CONFIG(port_num),
1616 ((coal & 0x3fff) << 8) |
1617 (rdl(mp, SDMA_CONFIG(port_num))
1624 static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
1627 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1629 /* Set TX Coalescing mechanism */
1630 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1635 static void port_init(struct mv643xx_eth_private *mp)
1639 init_mac_tables(mp);
1642 static int mv643xx_eth_open(struct net_device *dev)
1644 struct mv643xx_eth_private *mp = netdev_priv(dev);
1645 unsigned int port_num = mp->port_num;
1649 /* Clear any pending ethernet port interrupts */
1650 wrl(mp, INT_CAUSE(port_num), 0);
1651 wrl(mp, INT_CAUSE_EXT(port_num), 0);
1652 /* wait for previous write to complete */
1653 rdl(mp, INT_CAUSE_EXT(port_num));
1655 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1656 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1658 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1664 memset(&mp->timeout, 0, sizeof(struct timer_list));
1665 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1666 mp->timeout.data = (unsigned long)dev;
1668 /* Allocate RX and TX skb rings */
1669 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1672 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1676 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1679 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1681 goto out_free_rx_skb;
1684 /* Allocate TX ring */
1685 mp->tx_desc_count = 0;
1686 size = mp->tx_ring_size * sizeof(struct tx_desc);
1687 mp->tx_desc_area_size = size;
1689 if (mp->tx_sram_size) {
1690 mp->tx_desc_area = ioremap(mp->tx_sram_addr,
1692 mp->tx_desc_dma = mp->tx_sram_addr;
1694 mp->tx_desc_area = dma_alloc_coherent(NULL, size,
1698 if (!mp->tx_desc_area) {
1699 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1702 goto out_free_tx_skb;
1704 BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
1705 memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
1707 ether_init_tx_desc_ring(mp);
1709 /* Allocate RX ring */
1710 mp->rx_desc_count = 0;
1711 size = mp->rx_ring_size * sizeof(struct rx_desc);
1712 mp->rx_desc_area_size = size;
1714 if (mp->rx_sram_size) {
1715 mp->rx_desc_area = ioremap(mp->rx_sram_addr,
1717 mp->rx_desc_dma = mp->rx_sram_addr;
1719 mp->rx_desc_area = dma_alloc_coherent(NULL, size,
1723 if (!mp->rx_desc_area) {
1724 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1726 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1728 if (mp->rx_sram_size)
1729 iounmap(mp->tx_desc_area);
1731 dma_free_coherent(NULL, mp->tx_desc_area_size,
1732 mp->tx_desc_area, mp->tx_desc_dma);
1734 goto out_free_tx_skb;
1736 memset((void *)mp->rx_desc_area, 0, size);
1738 ether_init_rx_desc_ring(mp);
1740 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1742 #ifdef MV643XX_ETH_NAPI
1743 napi_enable(&mp->napi);
1748 /* Interrupt Coalescing */
1750 #ifdef MV643XX_ETH_COAL
1751 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
1754 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
1756 /* Unmask phy and link status changes interrupts */
1757 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1759 /* Unmask RX buffer and TX end interrupt */
1760 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
1769 free_irq(dev->irq, dev);
1774 static void port_reset(struct mv643xx_eth_private *mp)
1776 unsigned int port_num = mp->port_num;
1777 unsigned int reg_data;
1779 mv643xx_eth_port_disable_tx(mp);
1780 mv643xx_eth_port_disable_rx(mp);
1782 /* Clear all MIB counters */
1783 clear_mib_counters(mp);
1785 /* Reset the Enable bit in the Configuration Register */
1786 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1787 reg_data &= ~(SERIAL_PORT_ENABLE |
1788 DO_NOT_FORCE_LINK_FAIL |
1790 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1793 static int mv643xx_eth_stop(struct net_device *dev)
1795 struct mv643xx_eth_private *mp = netdev_priv(dev);
1796 unsigned int port_num = mp->port_num;
1798 /* Mask all interrupts on ethernet port */
1799 wrl(mp, INT_MASK(port_num), 0x00000000);
1800 /* wait for previous write to complete */
1801 rdl(mp, INT_MASK(port_num));
1803 #ifdef MV643XX_ETH_NAPI
1804 napi_disable(&mp->napi);
1806 netif_carrier_off(dev);
1807 netif_stop_queue(dev);
1811 mv643xx_eth_free_tx_rings(dev);
1812 mv643xx_eth_free_rx_rings(dev);
1814 free_irq(dev->irq, dev);
1819 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1821 struct mv643xx_eth_private *mp = netdev_priv(dev);
1823 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1826 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1828 if ((new_mtu > 9500) || (new_mtu < 64))
1832 if (!netif_running(dev))
1836 * Stop and then re-open the interface. This will allocate RX
1837 * skbs of the new MTU.
1838 * There is a possible danger that the open will not succeed,
1839 * due to memory being full, which might fail the open function.
1841 mv643xx_eth_stop(dev);
1842 if (mv643xx_eth_open(dev)) {
1843 printk(KERN_ERR "%s: Fatal error on opening device\n",
1850 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1852 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
1854 struct net_device *dev = mp->dev;
1856 if (!netif_running(dev))
1859 netif_stop_queue(dev);
1864 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1865 netif_wake_queue(dev);
1868 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1870 struct mv643xx_eth_private *mp = netdev_priv(dev);
1872 printk(KERN_INFO "%s: TX timeout ", dev->name);
1874 /* Do the reset outside of interrupt context */
1875 schedule_work(&mp->tx_timeout_task);
1878 #ifdef CONFIG_NET_POLL_CONTROLLER
1879 static void mv643xx_eth_netpoll(struct net_device *netdev)
1881 struct mv643xx_eth_private *mp = netdev_priv(netdev);
1882 int port_num = mp->port_num;
1884 wrl(mp, INT_MASK(port_num), 0x00000000);
1885 /* wait for previous write to complete */
1886 rdl(mp, INT_MASK(port_num));
1888 mv643xx_eth_int_handler(netdev->irq, netdev);
1890 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
1894 static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
1896 struct mv643xx_eth_private *mp = netdev_priv(dev);
1899 read_smi_reg(mp, location, &val);
1903 static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
1905 struct mv643xx_eth_private *mp = netdev_priv(dev);
1906 write_smi_reg(mp, location, val);
1910 /* platform glue ************************************************************/
1912 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1913 struct mbus_dram_target_info *dram)
1915 void __iomem *base = msp->base;
1920 for (i = 0; i < 6; i++) {
1921 writel(0, base + WINDOW_BASE(i));
1922 writel(0, base + WINDOW_SIZE(i));
1924 writel(0, base + WINDOW_REMAP_HIGH(i));
1930 for (i = 0; i < dram->num_cs; i++) {
1931 struct mbus_dram_window *cs = dram->cs + i;
1933 writel((cs->base & 0xffff0000) |
1934 (cs->mbus_attr << 8) |
1935 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1936 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1938 win_enable &= ~(1 << i);
1939 win_protect |= 3 << (2 * i);
1942 writel(win_enable, base + WINDOW_BAR_ENABLE);
1943 msp->win_protect = win_protect;
1946 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1948 static int mv643xx_eth_version_printed = 0;
1949 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
1950 struct mv643xx_eth_shared_private *msp;
1951 struct resource *res;
1954 if (!mv643xx_eth_version_printed++)
1955 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1958 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1963 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
1966 memset(msp, 0, sizeof(*msp));
1968 msp->base = ioremap(res->start, res->end - res->start + 1);
1969 if (msp->base == NULL)
1972 spin_lock_init(&msp->phy_lock);
1973 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
1975 platform_set_drvdata(pdev, msp);
1978 * (Re-)program MBUS remapping windows if we are asked to.
1980 if (pd != NULL && pd->dram != NULL)
1981 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
1991 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1993 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2001 static struct platform_driver mv643xx_eth_shared_driver = {
2002 .probe = mv643xx_eth_shared_probe,
2003 .remove = mv643xx_eth_shared_remove,
2005 .name = MV643XX_ETH_SHARED_NAME,
2006 .owner = THIS_MODULE,
2010 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2013 int addr_shift = 5 * mp->port_num;
2015 reg_data = rdl(mp, PHY_ADDR);
2016 reg_data &= ~(0x1f << addr_shift);
2017 reg_data |= (phy_addr & 0x1f) << addr_shift;
2018 wrl(mp, PHY_ADDR, reg_data);
2021 static int phy_addr_get(struct mv643xx_eth_private *mp)
2023 unsigned int reg_data;
2025 reg_data = rdl(mp, PHY_ADDR);
2027 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2030 static int phy_detect(struct mv643xx_eth_private *mp)
2032 unsigned int phy_reg_data0;
2035 read_smi_reg(mp, 0, &phy_reg_data0);
2036 auto_neg = phy_reg_data0 & 0x1000;
2037 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2038 write_smi_reg(mp, 0, phy_reg_data0);
2040 read_smi_reg(mp, 0, &phy_reg_data0);
2041 if ((phy_reg_data0 & 0x1000) == auto_neg)
2042 return -ENODEV; /* change didn't take */
2044 phy_reg_data0 ^= 0x1000;
2045 write_smi_reg(mp, 0, phy_reg_data0);
2049 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2050 int speed, int duplex,
2051 struct ethtool_cmd *cmd)
2053 struct mv643xx_eth_private *mp = netdev_priv(dev);
2055 memset(cmd, 0, sizeof(*cmd));
2057 cmd->port = PORT_MII;
2058 cmd->transceiver = XCVR_INTERNAL;
2059 cmd->phy_address = phy_address;
2062 cmd->autoneg = AUTONEG_ENABLE;
2063 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2064 cmd->speed = SPEED_100;
2065 cmd->advertising = ADVERTISED_10baseT_Half |
2066 ADVERTISED_10baseT_Full |
2067 ADVERTISED_100baseT_Half |
2068 ADVERTISED_100baseT_Full;
2069 if (mp->mii.supports_gmii)
2070 cmd->advertising |= ADVERTISED_1000baseT_Full;
2072 cmd->autoneg = AUTONEG_DISABLE;
2074 cmd->duplex = duplex;
2078 static int mv643xx_eth_probe(struct platform_device *pdev)
2080 struct mv643xx_eth_platform_data *pd;
2082 struct mv643xx_eth_private *mp;
2083 struct net_device *dev;
2085 struct resource *res;
2087 struct ethtool_cmd cmd;
2088 int duplex = DUPLEX_HALF;
2089 int speed = 0; /* default to auto-negotiation */
2090 DECLARE_MAC_BUF(mac);
2092 pd = pdev->dev.platform_data;
2094 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2098 if (pd->shared == NULL) {
2099 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2103 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2107 platform_set_drvdata(pdev, dev);
2109 mp = netdev_priv(dev);
2111 #ifdef MV643XX_ETH_NAPI
2112 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2115 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2117 dev->irq = res->start;
2119 dev->open = mv643xx_eth_open;
2120 dev->stop = mv643xx_eth_stop;
2121 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2122 dev->set_mac_address = mv643xx_eth_set_mac_address;
2123 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2125 /* No need to Tx Timeout */
2126 dev->tx_timeout = mv643xx_eth_tx_timeout;
2128 #ifdef CONFIG_NET_POLL_CONTROLLER
2129 dev->poll_controller = mv643xx_eth_netpoll;
2132 dev->watchdog_timeo = 2 * HZ;
2134 dev->change_mtu = mv643xx_eth_change_mtu;
2135 dev->do_ioctl = mv643xx_eth_do_ioctl;
2136 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2138 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2139 #ifdef MAX_SKB_FRAGS
2141 * Zero copy can only work if we use Discovery II memory. Else, we will
2142 * have to map the buffers to ISA memory which is only 16 MB
2144 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2148 /* Configure the timeout task */
2149 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2151 spin_lock_init(&mp->lock);
2153 mp->shared = platform_get_drvdata(pd->shared);
2154 port_num = mp->port_num = pd->port_number;
2156 if (mp->shared->win_protect)
2157 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2159 mp->shared_smi = mp->shared;
2160 if (pd->shared_smi != NULL)
2161 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2163 /* set default config values */
2164 uc_addr_get(mp, dev->dev_addr);
2165 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2166 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2168 if (is_valid_ether_addr(pd->mac_addr))
2169 memcpy(dev->dev_addr, pd->mac_addr, 6);
2171 if (pd->phy_addr || pd->force_phy_addr)
2172 phy_addr_set(mp, pd->phy_addr);
2174 if (pd->rx_queue_size)
2175 mp->rx_ring_size = pd->rx_queue_size;
2177 if (pd->tx_queue_size)
2178 mp->tx_ring_size = pd->tx_queue_size;
2180 if (pd->tx_sram_size) {
2181 mp->tx_sram_size = pd->tx_sram_size;
2182 mp->tx_sram_addr = pd->tx_sram_addr;
2185 if (pd->rx_sram_size) {
2186 mp->rx_sram_size = pd->rx_sram_size;
2187 mp->rx_sram_addr = pd->rx_sram_addr;
2190 duplex = pd->duplex;
2193 /* Hook up MII support for ethtool */
2195 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2196 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2197 mp->mii.phy_id = phy_addr_get(mp);
2198 mp->mii.phy_id_mask = 0x3f;
2199 mp->mii.reg_num_mask = 0x1f;
2201 err = phy_detect(mp);
2203 pr_debug("%s: No PHY detected at addr %d\n",
2204 dev->name, phy_addr_get(mp));
2209 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2210 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2211 mv643xx_eth_update_pscr(dev, &cmd);
2212 mv643xx_eth_set_settings(dev, &cmd);
2214 SET_NETDEV_DEV(dev, &pdev->dev);
2215 err = register_netdev(dev);
2221 "%s: port %d with MAC address %s\n",
2222 dev->name, port_num, print_mac(mac, p));
2224 if (dev->features & NETIF_F_SG)
2225 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2227 if (dev->features & NETIF_F_IP_CSUM)
2228 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2231 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2232 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2235 #ifdef MV643XX_ETH_COAL
2236 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2240 #ifdef MV643XX_ETH_NAPI
2241 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2244 if (mp->tx_sram_size > 0)
2245 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2255 static int mv643xx_eth_remove(struct platform_device *pdev)
2257 struct net_device *dev = platform_get_drvdata(pdev);
2259 unregister_netdev(dev);
2260 flush_scheduled_work();
2263 platform_set_drvdata(pdev, NULL);
2267 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2269 struct net_device *dev = platform_get_drvdata(pdev);
2270 struct mv643xx_eth_private *mp = netdev_priv(dev);
2271 unsigned int port_num = mp->port_num;
2273 /* Mask all interrupts on ethernet port */
2274 wrl(mp, INT_MASK(port_num), 0);
2275 rdl(mp, INT_MASK(port_num));
2280 static struct platform_driver mv643xx_eth_driver = {
2281 .probe = mv643xx_eth_probe,
2282 .remove = mv643xx_eth_remove,
2283 .shutdown = mv643xx_eth_shutdown,
2285 .name = MV643XX_ETH_NAME,
2286 .owner = THIS_MODULE,
2290 static int __init mv643xx_eth_init_module(void)
2294 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2296 rc = platform_driver_register(&mv643xx_eth_driver);
2298 platform_driver_unregister(&mv643xx_eth_shared_driver);
2303 static void __exit mv643xx_eth_cleanup_module(void)
2305 platform_driver_unregister(&mv643xx_eth_driver);
2306 platform_driver_unregister(&mv643xx_eth_shared_driver);
2309 module_init(mv643xx_eth_init_module);
2310 module_exit(mv643xx_eth_cleanup_module);
2312 MODULE_LICENSE("GPL");
2313 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2314 " and Dale Farnsworth");
2315 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2316 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2317 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);