2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_driver_name[] = "mv643xx_eth";
58 static char mv643xx_driver_version[] = "1.0";
60 #define MV643XX_CHECKSUM_OFFLOAD_TX
62 #define MV643XX_TX_FAST_REFILL
65 #define MV643XX_TX_COAL 100
67 #define MV643XX_RX_COAL 100
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
107 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
108 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
109 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
110 #define INT_MASK(p) (0x0468 + ((p) << 10))
111 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
112 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
113 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
114 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
115 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
116 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
121 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
122 #define CLASSIFY_EN (1 << 0)
123 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
124 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
125 #define PARTITION_DISABLE (0 << 2)
126 #define PARTITION_ENABLE (1 << 2)
128 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
129 SPAN_BPDU_PACKETS_AS_NORMAL | \
132 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
133 #define RIFB (1 << 0)
134 #define RX_BURST_SIZE_1_64BIT (0 << 1)
135 #define RX_BURST_SIZE_2_64BIT (1 << 1)
136 #define RX_BURST_SIZE_4_64BIT (2 << 1)
137 #define RX_BURST_SIZE_8_64BIT (3 << 1)
138 #define RX_BURST_SIZE_16_64BIT (4 << 1)
139 #define BLM_RX_NO_SWAP (1 << 4)
140 #define BLM_RX_BYTE_SWAP (0 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define BLM_TX_BYTE_SWAP (0 << 5)
143 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
144 #define DESCRIPTORS_NO_SWAP (0 << 6)
145 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
146 #define TX_BURST_SIZE_1_64BIT (0 << 22)
147 #define TX_BURST_SIZE_2_64BIT (1 << 22)
148 #define TX_BURST_SIZE_4_64BIT (2 << 22)
149 #define TX_BURST_SIZE_8_64BIT (3 << 22)
150 #define TX_BURST_SIZE_16_64BIT (4 << 22)
152 #if defined(__BIG_ENDIAN)
153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
154 RX_BURST_SIZE_4_64BIT | \
156 TX_BURST_SIZE_4_64BIT
157 #elif defined(__LITTLE_ENDIAN)
158 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
159 RX_BURST_SIZE_4_64BIT | \
163 TX_BURST_SIZE_4_64BIT
165 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
168 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
169 #define SERIAL_PORT_DISABLE (0 << 0)
170 #define SERIAL_PORT_ENABLE (1 << 0)
171 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
172 #define FORCE_LINK_PASS (1 << 1)
173 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
174 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
175 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
176 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
177 #define ADV_NO_FLOW_CTRL (0 << 4)
178 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
179 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
180 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
181 #define FORCE_BP_MODE_NO_JAM (0 << 7)
182 #define FORCE_BP_MODE_JAM_TX (1 << 7)
183 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
184 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
185 #define FORCE_LINK_FAIL (0 << 10)
186 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
187 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
188 #define RETRANSMIT_FOREVER (1 << 11)
189 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
190 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
191 #define DTE_ADV_0 (0 << 14)
192 #define DTE_ADV_1 (1 << 14)
193 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
194 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
195 #define AUTO_NEG_NO_CHANGE (0 << 16)
196 #define RESTART_AUTO_NEG (1 << 16)
197 #define MAX_RX_PACKET_1518BYTE (0 << 17)
198 #define MAX_RX_PACKET_1522BYTE (1 << 17)
199 #define MAX_RX_PACKET_1552BYTE (2 << 17)
200 #define MAX_RX_PACKET_9022BYTE (3 << 17)
201 #define MAX_RX_PACKET_9192BYTE (4 << 17)
202 #define MAX_RX_PACKET_9700BYTE (5 << 17)
203 #define MAX_RX_PACKET_MASK (7 << 17)
204 #define CLR_EXT_LOOPBACK (0 << 20)
205 #define SET_EXT_LOOPBACK (1 << 20)
206 #define SET_HALF_DUPLEX_MODE (0 << 21)
207 #define SET_FULL_DUPLEX_MODE (1 << 21)
208 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
209 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
210 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
211 #define SET_GMII_SPEED_TO_1000 (1 << 23)
212 #define SET_MII_SPEED_TO_10 (0 << 24)
213 #define SET_MII_SPEED_TO_100 (1 << 24)
215 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
216 DO_NOT_FORCE_LINK_PASS | \
217 ENABLE_AUTO_NEG_FOR_DUPLX | \
218 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
219 ADV_SYMMETRIC_FLOW_CTRL | \
220 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
221 FORCE_BP_MODE_NO_JAM | \
222 (1 << 9) /* reserved */ | \
223 DO_NOT_FORCE_LINK_FAIL | \
224 RETRANSMIT_16_ATTEMPTS | \
225 ENABLE_AUTO_NEG_SPEED_GMII | \
227 DISABLE_AUTO_NEG_BYPASS | \
228 AUTO_NEG_NO_CHANGE | \
229 MAX_RX_PACKET_9700BYTE | \
231 SET_FULL_DUPLEX_MODE | \
232 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
234 /* These macros describe Ethernet Serial Status reg (PSR) bits */
235 #define PORT_STATUS_MODE_10_BIT (1 << 0)
236 #define PORT_STATUS_LINK_UP (1 << 1)
237 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
238 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
239 #define PORT_STATUS_GMII_1000 (1 << 4)
240 #define PORT_STATUS_MII_100 (1 << 5)
241 /* PSR bit 6 is undocumented */
242 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
243 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
244 #define PORT_STATUS_PARTITION (1 << 9)
245 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
246 /* PSR bits 11-31 are reserved */
248 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
249 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
253 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
254 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
256 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
257 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
258 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
259 #define ETH_INT_CAUSE_EXT 0x00000002
260 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
262 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
263 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
264 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
265 #define ETH_INT_CAUSE_PHY 0x00010000
266 #define ETH_INT_CAUSE_STATE 0x00100000
267 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
270 #define ETH_INT_MASK_ALL 0x00000000
271 #define ETH_INT_MASK_ALL_EXT 0x00000000
273 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
274 #define PHY_WAIT_MICRO_SECONDS 10
276 /* Buffer offset from buffer pointer */
277 #define RX_BUF_OFFSET 0x2
279 /* Gigabit Ethernet Unit Global Registers */
281 /* MIB Counters register definitions */
282 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
283 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
284 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
285 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
286 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
287 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
288 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
289 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
290 #define ETH_MIB_FRAMES_64_OCTETS 0x20
291 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
292 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
293 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
294 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
295 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
296 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
297 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
298 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
299 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
300 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
301 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
302 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
303 #define ETH_MIB_FC_SENT 0x54
304 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
305 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
306 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
307 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
308 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
309 #define ETH_MIB_JABBER_RECEIVED 0x6c
310 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
311 #define ETH_MIB_BAD_CRC_EVENT 0x74
312 #define ETH_MIB_COLLISION 0x78
313 #define ETH_MIB_LATE_COLLISION 0x7c
315 /* Port serial status reg (PSR) */
316 #define ETH_INTERFACE_PCM 0x00000001
317 #define ETH_LINK_IS_UP 0x00000002
318 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
319 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
320 #define ETH_GMII_SPEED_1000 0x00000010
321 #define ETH_MII_SPEED_100 0x00000020
322 #define ETH_TX_IN_PROGRESS 0x00000080
323 #define ETH_BYPASS_ACTIVE 0x00000100
324 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
325 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
328 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
329 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
330 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
331 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
333 /* Interrupt Cause Register Bit Definitions */
335 /* SDMA command status fields macros */
337 /* Tx & Rx descriptors status */
338 #define ETH_ERROR_SUMMARY 0x00000001
340 /* Tx & Rx descriptors command */
341 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
343 /* Tx descriptors status */
344 #define ETH_LC_ERROR 0
345 #define ETH_UR_ERROR 0x00000002
346 #define ETH_RL_ERROR 0x00000004
347 #define ETH_LLC_SNAP_FORMAT 0x00000200
349 /* Rx descriptors status */
350 #define ETH_OVERRUN_ERROR 0x00000002
351 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
352 #define ETH_RESOURCE_ERROR 0x00000006
353 #define ETH_VLAN_TAGGED 0x00080000
354 #define ETH_BPDU_FRAME 0x00100000
355 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
356 #define ETH_OTHER_FRAME_TYPE 0x00400000
357 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
358 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
359 #define ETH_FRAME_HEADER_OK 0x02000000
360 #define ETH_RX_LAST_DESC 0x04000000
361 #define ETH_RX_FIRST_DESC 0x08000000
362 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
363 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
364 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
366 /* Rx descriptors byte count */
367 #define ETH_FRAME_FRAGMENTED 0x00000004
369 /* Tx descriptors command */
370 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
371 #define ETH_FRAME_SET_TO_VLAN 0x00008000
372 #define ETH_UDP_FRAME 0x00010000
373 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
374 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
375 #define ETH_ZERO_PADDING 0x00080000
376 #define ETH_TX_LAST_DESC 0x00100000
377 #define ETH_TX_FIRST_DESC 0x00200000
378 #define ETH_GEN_CRC 0x00400000
379 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
380 #define ETH_AUTO_MODE 0x40000000
382 #define ETH_TX_IHL_SHIFT 11
386 typedef enum _eth_func_ret_status {
387 ETH_OK, /* Returned as expected. */
388 ETH_ERROR, /* Fundamental error. */
389 ETH_RETRY, /* Could not process request. Try later.*/
390 ETH_END_OF_JOB, /* Ring has nothing to process. */
391 ETH_QUEUE_FULL, /* Ring resource error. */
392 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
393 } ETH_FUNC_RET_STATUS;
395 /* These are for big-endian machines. Little endian needs different
398 #if defined(__BIG_ENDIAN)
400 u16 byte_cnt; /* Descriptor buffer byte count */
401 u16 buf_size; /* Buffer size */
402 u32 cmd_sts; /* Descriptor command status */
403 u32 next_desc_ptr; /* Next descriptor pointer */
404 u32 buf_ptr; /* Descriptor buffer pointer */
408 u16 byte_cnt; /* buffer byte count */
409 u16 l4i_chk; /* CPU provided TCP checksum */
410 u32 cmd_sts; /* Command/status field */
411 u32 next_desc_ptr; /* Pointer to next descriptor */
412 u32 buf_ptr; /* pointer to buffer for this descriptor*/
414 #elif defined(__LITTLE_ENDIAN)
416 u32 cmd_sts; /* Descriptor command status */
417 u16 buf_size; /* Buffer size */
418 u16 byte_cnt; /* Descriptor buffer byte count */
419 u32 buf_ptr; /* Descriptor buffer pointer */
420 u32 next_desc_ptr; /* Next descriptor pointer */
424 u32 cmd_sts; /* Command/status field */
425 u16 l4i_chk; /* CPU provided TCP checksum */
426 u16 byte_cnt; /* buffer byte count */
427 u32 buf_ptr; /* pointer to buffer for this descriptor*/
428 u32 next_desc_ptr; /* Pointer to next descriptor */
431 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
434 /* Unified struct for Rx and Tx operations. The user is not required to */
435 /* be familier with neither Tx nor Rx descriptors. */
437 unsigned short byte_cnt; /* Descriptor buffer byte count */
438 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
439 unsigned int cmd_sts; /* Descriptor command status */
440 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
441 struct sk_buff *return_info; /* User resource return information */
445 /* global *******************************************************************/
446 struct mv643xx_shared_private {
447 void __iomem *eth_base;
449 /* used to protect SMI_REG, which is shared across ports */
458 /* per-port *****************************************************************/
459 struct mv643xx_mib_counters {
460 u64 good_octets_received;
461 u32 bad_octets_received;
462 u32 internal_mac_transmit_err;
463 u32 good_frames_received;
464 u32 bad_frames_received;
465 u32 broadcast_frames_received;
466 u32 multicast_frames_received;
467 u32 frames_64_octets;
468 u32 frames_65_to_127_octets;
469 u32 frames_128_to_255_octets;
470 u32 frames_256_to_511_octets;
471 u32 frames_512_to_1023_octets;
472 u32 frames_1024_to_max_octets;
473 u64 good_octets_sent;
474 u32 good_frames_sent;
475 u32 excessive_collision;
476 u32 multicast_frames_sent;
477 u32 broadcast_frames_sent;
478 u32 unrec_mac_control_received;
480 u32 good_fc_received;
482 u32 undersize_received;
483 u32 fragments_received;
484 u32 oversize_received;
486 u32 mac_receive_error;
492 struct mv643xx_private {
493 struct mv643xx_shared_private *shared;
494 int port_num; /* User Ethernet port number */
496 struct mv643xx_shared_private *shared_smi;
498 u32 rx_sram_addr; /* Base address of rx sram area */
499 u32 rx_sram_size; /* Size of rx sram area */
500 u32 tx_sram_addr; /* Base address of tx sram area */
501 u32 tx_sram_size; /* Size of tx sram area */
503 int rx_resource_err; /* Rx ring resource error flag */
505 /* Tx/Rx rings managment indexes fields. For driver use */
507 /* Next available and first returning Rx resource */
508 int rx_curr_desc_q, rx_used_desc_q;
510 /* Next available and first returning Tx resource */
511 int tx_curr_desc_q, tx_used_desc_q;
513 #ifdef MV643XX_TX_FAST_REFILL
514 u32 tx_clean_threshold;
517 struct eth_rx_desc *p_rx_desc_area;
518 dma_addr_t rx_desc_dma;
519 int rx_desc_area_size;
520 struct sk_buff **rx_skb;
522 struct eth_tx_desc *p_tx_desc_area;
523 dma_addr_t tx_desc_dma;
524 int tx_desc_area_size;
525 struct sk_buff **tx_skb;
527 struct work_struct tx_timeout_task;
529 struct net_device *dev;
530 struct napi_struct napi;
531 struct net_device_stats stats;
532 struct mv643xx_mib_counters mib_counters;
534 /* Size of Tx Ring per queue */
536 /* Number of tx descriptors in use */
538 /* Size of Rx Ring per queue */
540 /* Number of rx descriptors in use */
544 * Used in case RX Ring is empty, which can be caused when
545 * system does not have resources (skb's)
547 struct timer_list timeout;
551 struct mii_if_info mii;
555 /* port register accessors **************************************************/
556 static inline u32 rdl(struct mv643xx_private *mp, int offset)
558 return readl(mp->shared->eth_base + offset);
561 static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
563 writel(data, mp->shared->eth_base + offset);
567 /* rxq/txq helper functions *************************************************/
568 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
571 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
574 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
576 unsigned int port_num = mp->port_num;
579 /* Stop Rx port activity. Check port Rx activity. */
580 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
582 /* Issue stop command for active queues only */
583 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
585 /* Wait for all Rx activity to terminate. */
586 /* Check port cause register that all Rx queues are stopped */
587 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
588 udelay(PHY_WAIT_MICRO_SECONDS);
594 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
597 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
600 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
602 unsigned int port_num = mp->port_num;
605 /* Stop Tx port activity. Check port Tx activity. */
606 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
608 /* Issue stop command for active queues only */
609 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
611 /* Wait for all Tx activity to terminate. */
612 /* Check port cause register that all Tx queues are stopped */
613 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
614 udelay(PHY_WAIT_MICRO_SECONDS);
616 /* Wait for Tx FIFO to empty */
617 while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
618 udelay(PHY_WAIT_MICRO_SECONDS);
625 /* rx ***********************************************************************/
626 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
629 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
632 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
633 * next 'used' descriptor and attached the returned buffer to it.
634 * In case the Rx ring was in "resource error" condition, where there are
635 * no available Rx resources, the function resets the resource error flag.
638 * struct mv643xx_private *mp Ethernet Port Control srtuct.
639 * struct pkt_info *p_pkt_info Information on returned buffer.
642 * New available Rx resource in Rx descriptor ring.
645 * ETH_ERROR in case the routine can not access Rx desc ring.
648 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
649 struct pkt_info *p_pkt_info)
651 int used_rx_desc; /* Where to return Rx resource */
652 volatile struct eth_rx_desc *p_used_rx_desc;
655 spin_lock_irqsave(&mp->lock, flags);
657 /* Get 'used' Rx descriptor */
658 used_rx_desc = mp->rx_used_desc_q;
659 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
661 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
662 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
663 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
665 /* Flush the write pipe */
667 /* Return the descriptor to DMA ownership */
669 p_used_rx_desc->cmd_sts =
670 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
673 /* Move the used descriptor pointer to the next descriptor */
674 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
676 /* Any Rx return cancels the Rx resource error status */
677 mp->rx_resource_err = 0;
679 spin_unlock_irqrestore(&mp->lock, flags);
685 * mv643xx_eth_rx_refill_descs
687 * Fills / refills RX queue on a certain gigabit ethernet port
689 * Input : pointer to ethernet interface network device structure
692 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
694 struct mv643xx_private *mp = netdev_priv(dev);
695 struct pkt_info pkt_info;
699 while (mp->rx_desc_count < mp->rx_ring_size) {
700 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
704 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
706 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
707 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
708 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
709 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
710 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
711 pkt_info.return_info = skb;
712 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
714 "%s: Error allocating RX Ring\n", dev->name);
717 skb_reserve(skb, ETH_HW_IP_ALIGN);
720 * If RX ring is empty of SKB, set a timer to try allocating
721 * again at a later time.
723 if (mp->rx_desc_count == 0) {
724 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
725 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
726 add_timer(&mp->timeout);
731 * mv643xx_eth_rx_refill_descs_timer_wrapper
733 * Timer routine to wake up RX queue filling task. This function is
734 * used only in case the RX queue is empty, and all alloc_skb has
735 * failed (due to out of memory event).
737 * Input : pointer to ethernet interface network device structure
740 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
742 mv643xx_eth_rx_refill_descs((struct net_device *)data);
746 * eth_port_receive - Get received information from Rx ring.
749 * This routine returns the received data to the caller. There is no
750 * data copying during routine operation. All information is returned
751 * using pointer to packet information struct passed from the caller.
752 * If the routine exhausts Rx ring resources then the resource error flag
756 * struct mv643xx_private *mp Ethernet Port Control srtuct.
757 * struct pkt_info *p_pkt_info User packet buffer.
760 * Rx ring current and used indexes are updated.
763 * ETH_ERROR in case the routine can not access Rx desc ring.
764 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
765 * ETH_END_OF_JOB if there is no received data.
768 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
769 struct pkt_info *p_pkt_info)
771 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
772 volatile struct eth_rx_desc *p_rx_desc;
773 unsigned int command_status;
776 /* Do not process Rx ring in case of Rx ring resource error */
777 if (mp->rx_resource_err)
778 return ETH_QUEUE_FULL;
780 spin_lock_irqsave(&mp->lock, flags);
782 /* Get the Rx Desc ring 'curr and 'used' indexes */
783 rx_curr_desc = mp->rx_curr_desc_q;
784 rx_used_desc = mp->rx_used_desc_q;
786 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
788 /* The following parameters are used to save readings from memory */
789 command_status = p_rx_desc->cmd_sts;
792 /* Nothing to receive... */
793 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
794 spin_unlock_irqrestore(&mp->lock, flags);
795 return ETH_END_OF_JOB;
798 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
799 p_pkt_info->cmd_sts = command_status;
800 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
801 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
802 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
805 * Clean the return info field to indicate that the
806 * packet has been moved to the upper layers
808 mp->rx_skb[rx_curr_desc] = NULL;
810 /* Update current index in data structure */
811 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
812 mp->rx_curr_desc_q = rx_next_curr_desc;
814 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
815 if (rx_next_curr_desc == rx_used_desc)
816 mp->rx_resource_err = 1;
818 spin_unlock_irqrestore(&mp->lock, flags);
824 * mv643xx_eth_receive
826 * This function is forward packets that are received from the port's
827 * queues toward kernel core or FastRoute them to another interface.
829 * Input : dev - a pointer to the required interface
830 * max - maximum number to receive (0 means unlimted)
832 * Output : number of served packets
834 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
836 struct mv643xx_private *mp = netdev_priv(dev);
837 struct net_device_stats *stats = &dev->stats;
838 unsigned int received_packets = 0;
840 struct pkt_info pkt_info;
842 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
843 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
850 * Note byte count includes 4 byte CRC count
853 stats->rx_bytes += pkt_info.byte_cnt;
854 skb = pkt_info.return_info;
856 * In case received a packet without first / last bits on OR
857 * the error summary bit is on, the packets needs to be dropeed.
859 if (((pkt_info.cmd_sts
860 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
861 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
862 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
864 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
865 ETH_RX_LAST_DESC)) !=
866 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
869 "%s: Received packet spread "
870 "on multiple descriptors\n",
873 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
876 dev_kfree_skb_irq(skb);
879 * The -4 is for the CRC in the trailer of the
882 skb_put(skb, pkt_info.byte_cnt - 4);
884 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
885 skb->ip_summed = CHECKSUM_UNNECESSARY;
887 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
889 skb->protocol = eth_type_trans(skb, dev);
891 netif_receive_skb(skb);
896 dev->last_rx = jiffies;
898 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
900 return received_packets;
907 * This function is used in case of NAPI
909 static int mv643xx_poll(struct napi_struct *napi, int budget)
911 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
912 struct net_device *dev = mp->dev;
913 unsigned int port_num = mp->port_num;
916 #ifdef MV643XX_TX_FAST_REFILL
917 if (++mp->tx_clean_threshold > 5) {
918 mv643xx_eth_free_completed_tx_descs(dev);
919 mp->tx_clean_threshold = 0;
924 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
925 != (u32) mp->rx_used_desc_q)
926 work_done = mv643xx_eth_receive_queue(dev, budget);
928 if (work_done < budget) {
929 netif_rx_complete(dev, napi);
930 wrl(mp, INT_CAUSE(port_num), 0);
931 wrl(mp, INT_CAUSE_EXT(port_num), 0);
932 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
940 /* tx ***********************************************************************/
942 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
944 * Hardware can't handle unaligned fragments smaller than 9 bytes.
945 * This helper function detects that case.
948 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
953 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
954 fragp = &skb_shinfo(skb)->frags[frag];
955 if (fragp->size <= 8 && fragp->page_offset & 0x7)
962 * eth_alloc_tx_desc_index - return the index of the next available tx desc
964 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
968 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
970 tx_desc_curr = mp->tx_curr_desc_q;
971 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
973 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
979 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
981 * Ensure the data for each fragment to be transmitted is mapped properly,
982 * then fill in descriptors in the tx hw queue.
984 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
989 struct eth_tx_desc *desc;
991 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
992 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
994 tx_index = eth_alloc_tx_desc_index(mp);
995 desc = &mp->p_tx_desc_area[tx_index];
997 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
998 /* Last Frag enables interrupt and frees the skb */
999 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1000 desc->cmd_sts |= ETH_ZERO_PADDING |
1002 ETH_TX_ENABLE_INTERRUPT;
1003 mp->tx_skb[tx_index] = skb;
1005 mp->tx_skb[tx_index] = NULL;
1007 desc = &mp->p_tx_desc_area[tx_index];
1009 desc->byte_cnt = this_frag->size;
1010 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1011 this_frag->page_offset,
1017 static inline __be16 sum16_as_be(__sum16 sum)
1019 return (__force __be16)sum;
1023 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1025 * Ensure the data for an skb to be transmitted is mapped properly,
1026 * then fill in descriptors in the tx hw queue and start the hardware.
1028 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1029 struct sk_buff *skb)
1032 struct eth_tx_desc *desc;
1035 int nr_frags = skb_shinfo(skb)->nr_frags;
1037 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1039 tx_index = eth_alloc_tx_desc_index(mp);
1040 desc = &mp->p_tx_desc_area[tx_index];
1043 eth_tx_fill_frag_descs(mp, skb);
1045 length = skb_headlen(skb);
1046 mp->tx_skb[tx_index] = NULL;
1048 cmd_sts |= ETH_ZERO_PADDING |
1050 ETH_TX_ENABLE_INTERRUPT;
1052 mp->tx_skb[tx_index] = skb;
1055 desc->byte_cnt = length;
1056 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1058 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1059 BUG_ON(skb->protocol != htons(ETH_P_IP));
1061 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1062 ETH_GEN_IP_V_4_CHECKSUM |
1063 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1065 switch (ip_hdr(skb)->protocol) {
1067 cmd_sts |= ETH_UDP_FRAME;
1068 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1071 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
1077 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1078 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1082 /* ensure all other descriptors are written before first cmd_sts */
1084 desc->cmd_sts = cmd_sts;
1086 /* ensure all descriptors are written before poking hardware */
1088 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1090 mp->tx_desc_count += nr_frags + 1;
1094 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1097 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1099 struct mv643xx_private *mp = netdev_priv(dev);
1100 struct net_device_stats *stats = &dev->stats;
1101 unsigned long flags;
1103 BUG_ON(netif_queue_stopped(dev));
1105 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1106 stats->tx_dropped++;
1107 printk(KERN_DEBUG "%s: failed to linearize tiny "
1108 "unaligned fragment\n", dev->name);
1109 return NETDEV_TX_BUSY;
1112 spin_lock_irqsave(&mp->lock, flags);
1114 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1115 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1116 netif_stop_queue(dev);
1117 spin_unlock_irqrestore(&mp->lock, flags);
1118 return NETDEV_TX_BUSY;
1121 eth_tx_submit_descs_for_skb(mp, skb);
1122 stats->tx_bytes += skb->len;
1123 stats->tx_packets++;
1124 dev->trans_start = jiffies;
1126 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1127 netif_stop_queue(dev);
1129 spin_unlock_irqrestore(&mp->lock, flags);
1131 return NETDEV_TX_OK;
1135 /* mii management interface *************************************************/
1136 static int ethernet_phy_get(struct mv643xx_private *mp);
1139 * eth_port_read_smi_reg - Read PHY registers
1142 * This routine utilize the SMI interface to interact with the PHY in
1143 * order to perform PHY register read.
1146 * struct mv643xx_private *mp Ethernet Port.
1147 * unsigned int phy_reg PHY register address offset.
1148 * unsigned int *value Register value buffer.
1151 * Write the value of a specified PHY register into given buffer.
1154 * false if the PHY is busy or read data is not in valid state.
1158 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
1159 unsigned int phy_reg, unsigned int *value)
1161 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1162 int phy_addr = ethernet_phy_get(mp);
1163 unsigned long flags;
1166 /* the SMI register is a shared resource */
1167 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1169 /* wait for the SMI register to become available */
1170 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1171 if (i == PHY_WAIT_ITERATIONS) {
1172 printk("%s: PHY busy timeout\n", mp->dev->name);
1175 udelay(PHY_WAIT_MICRO_SECONDS);
1178 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
1181 /* now wait for the data to be valid */
1182 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
1183 if (i == PHY_WAIT_ITERATIONS) {
1184 printk("%s: PHY read timeout\n", mp->dev->name);
1187 udelay(PHY_WAIT_MICRO_SECONDS);
1190 *value = readl(smi_reg) & 0xffff;
1192 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1196 * eth_port_write_smi_reg - Write to PHY registers
1199 * This routine utilize the SMI interface to interact with the PHY in
1200 * order to perform writes to PHY registers.
1203 * struct mv643xx_private *mp Ethernet Port.
1204 * unsigned int phy_reg PHY register address offset.
1205 * unsigned int value Register value.
1208 * Write the given value to the specified PHY register.
1211 * false if the PHY is busy.
1215 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
1216 unsigned int phy_reg, unsigned int value)
1218 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1219 int phy_addr = ethernet_phy_get(mp);
1220 unsigned long flags;
1223 /* the SMI register is a shared resource */
1224 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1226 /* wait for the SMI register to become available */
1227 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1228 if (i == PHY_WAIT_ITERATIONS) {
1229 printk("%s: PHY busy timeout\n", mp->dev->name);
1232 udelay(PHY_WAIT_MICRO_SECONDS);
1235 writel((phy_addr << 16) | (phy_reg << 21) |
1236 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
1238 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1242 /* mib counters *************************************************************/
1244 * eth_clear_mib_counters - Clear all MIB counters
1247 * This function clears all MIB counters of a specific ethernet port.
1248 * A read from the MIB counter will reset the counter.
1251 * struct mv643xx_private *mp Ethernet Port.
1254 * After reading all MIB counters, the counters resets.
1257 * MIB counter value.
1260 static void eth_clear_mib_counters(struct mv643xx_private *mp)
1262 unsigned int port_num = mp->port_num;
1265 /* Perform dummy reads from MIB counters */
1266 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
1268 rdl(mp, MIB_COUNTERS(port_num) + i);
1271 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
1273 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1276 static void eth_update_mib_counters(struct mv643xx_private *mp)
1278 struct mv643xx_mib_counters *p = &mp->mib_counters;
1281 p->good_octets_received +=
1282 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
1283 p->good_octets_received +=
1284 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
1286 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
1287 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
1289 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1291 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
1292 p->good_octets_sent +=
1293 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
1295 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
1296 offset <= ETH_MIB_LATE_COLLISION;
1298 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1302 /* ethtool ******************************************************************/
1303 struct mv643xx_stats {
1304 char stat_string[ETH_GSTRING_LEN];
1309 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
1310 offsetof(struct mv643xx_private, m)
1312 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
1313 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
1314 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
1315 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
1316 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
1317 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
1318 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
1319 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
1320 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
1321 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
1322 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
1323 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
1324 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
1325 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
1326 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
1327 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
1328 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
1329 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
1330 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
1331 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
1332 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
1333 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
1334 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
1335 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
1336 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
1337 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
1338 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
1339 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
1340 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
1341 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
1342 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
1343 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
1344 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
1345 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
1346 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
1347 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
1348 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
1349 { "collision", MV643XX_STAT(mib_counters.collision) },
1350 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
1353 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
1355 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1357 struct mv643xx_private *mp = netdev_priv(dev);
1360 spin_lock_irq(&mp->lock);
1361 err = mii_ethtool_gset(&mp->mii, cmd);
1362 spin_unlock_irq(&mp->lock);
1364 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1365 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1366 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1371 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 struct mv643xx_private *mp = netdev_priv(dev);
1376 spin_lock_irq(&mp->lock);
1377 err = mii_ethtool_sset(&mp->mii, cmd);
1378 spin_unlock_irq(&mp->lock);
1383 static void mv643xx_get_drvinfo(struct net_device *netdev,
1384 struct ethtool_drvinfo *drvinfo)
1386 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
1387 strncpy(drvinfo->version, mv643xx_driver_version, 32);
1388 strncpy(drvinfo->fw_version, "N/A", 32);
1389 strncpy(drvinfo->bus_info, "mv643xx", 32);
1390 drvinfo->n_stats = MV643XX_STATS_LEN;
1393 static int mv643xx_eth_nway_restart(struct net_device *dev)
1395 struct mv643xx_private *mp = netdev_priv(dev);
1397 return mii_nway_restart(&mp->mii);
1400 static u32 mv643xx_eth_get_link(struct net_device *dev)
1402 struct mv643xx_private *mp = netdev_priv(dev);
1404 return mii_link_ok(&mp->mii);
1407 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
1414 for (i=0; i < MV643XX_STATS_LEN; i++) {
1415 memcpy(data + i * ETH_GSTRING_LEN,
1416 mv643xx_gstrings_stats[i].stat_string,
1423 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
1424 struct ethtool_stats *stats, uint64_t *data)
1426 struct mv643xx_private *mp = netdev->priv;
1429 eth_update_mib_counters(mp);
1431 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1432 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
1433 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1434 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1438 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
1442 return MV643XX_STATS_LEN;
1448 static const struct ethtool_ops mv643xx_ethtool_ops = {
1449 .get_settings = mv643xx_get_settings,
1450 .set_settings = mv643xx_set_settings,
1451 .get_drvinfo = mv643xx_get_drvinfo,
1452 .get_link = mv643xx_eth_get_link,
1453 .set_sg = ethtool_op_set_sg,
1454 .get_sset_count = mv643xx_get_sset_count,
1455 .get_ethtool_stats = mv643xx_get_ethtool_stats,
1456 .get_strings = mv643xx_get_strings,
1457 .nway_reset = mv643xx_eth_nway_restart,
1461 /* address handling *********************************************************/
1463 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1465 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
1466 unsigned char *p_addr)
1468 unsigned int port_num = mp->port_num;
1472 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1473 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1475 p_addr[0] = (mac_h >> 24) & 0xff;
1476 p_addr[1] = (mac_h >> 16) & 0xff;
1477 p_addr[2] = (mac_h >> 8) & 0xff;
1478 p_addr[3] = mac_h & 0xff;
1479 p_addr[4] = (mac_l >> 8) & 0xff;
1480 p_addr[5] = mac_l & 0xff;
1484 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1487 * Go through all the DA filter tables (Unicast, Special Multicast &
1488 * Other Multicast) and set each entry to 0.
1491 * struct mv643xx_private *mp Ethernet Port.
1494 * Multicast and Unicast packets are rejected.
1499 static void eth_port_init_mac_tables(struct mv643xx_private *mp)
1501 unsigned int port_num = mp->port_num;
1504 /* Clear DA filter unicast table (Ex_dFUT) */
1505 for (table_index = 0; table_index <= 0xC; table_index += 4)
1506 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1508 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1509 /* Clear DA filter special multicast table (Ex_dFSMT) */
1510 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1511 /* Clear DA filter other multicast table (Ex_dFOMT) */
1512 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1517 * The entries in each table are indexed by a hash of a packet's MAC
1518 * address. One bit in each entry determines whether the packet is
1519 * accepted. There are 4 entries (each 8 bits wide) in each register
1520 * of the table. The bits in each entry are defined as follows:
1521 * 0 Accept=1, Drop=0
1522 * 3-1 Queue (ETH_Q0=0)
1525 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
1526 int table, unsigned char entry)
1528 unsigned int table_reg;
1529 unsigned int tbl_offset;
1530 unsigned int reg_offset;
1532 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1533 reg_offset = entry % 4; /* Entry offset within the register */
1535 /* Set "accepts frame bit" at specified table entry */
1536 table_reg = rdl(mp, table + tbl_offset);
1537 table_reg |= 0x01 << (8 * reg_offset);
1538 wrl(mp, table + tbl_offset, table_reg);
1542 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1544 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
1545 unsigned char *p_addr)
1547 unsigned int port_num = mp->port_num;
1552 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1553 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1556 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1557 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1559 /* Accept frames with this address */
1560 table = UNICAST_TABLE(port_num);
1561 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
1565 * mv643xx_eth_update_mac_address
1567 * Update the MAC address of the port in the address table
1569 * Input : pointer to ethernet interface network device structure
1572 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1574 struct mv643xx_private *mp = netdev_priv(dev);
1576 eth_port_init_mac_tables(mp);
1577 eth_port_uc_addr_set(mp, dev->dev_addr);
1581 * mv643xx_eth_set_mac_address
1583 * Change the interface's mac address.
1584 * No special hardware thing should be done because interface is always
1585 * put in promiscuous mode.
1587 * Input : pointer to ethernet interface network device structure and
1588 * a pointer to the designated entry to be added to the cache.
1589 * Output : zero upon success, negative upon failure
1591 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1595 for (i = 0; i < 6; i++)
1596 /* +2 is for the offset of the HW addr type */
1597 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1598 mv643xx_eth_update_mac_address(dev);
1603 * eth_port_mc_addr - Multicast address settings.
1605 * The MV device supports multicast using two tables:
1606 * 1) Special Multicast Table for MAC addresses of the form
1607 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1608 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1609 * Table entries in the DA-Filter table.
1610 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1611 * is used as an index to the Other Multicast Table entries in the
1612 * DA-Filter table. This function calculates the CRC-8bit value.
1613 * In either case, eth_port_set_filter_table_entry() is then called
1614 * to set to set the actual table entry.
1616 static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
1618 unsigned int port_num = mp->port_num;
1621 unsigned char crc_result = 0;
1627 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1628 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1629 table = SPECIAL_MCAST_TABLE(port_num);
1630 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
1634 /* Calculate CRC-8 out of the given address */
1635 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1636 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1637 (p_addr[4] << 8) | (p_addr[5] << 0);
1639 for (i = 0; i < 32; i++)
1640 mac_array[i] = (mac_l >> i) & 0x1;
1641 for (i = 32; i < 48; i++)
1642 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1644 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1645 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1646 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1647 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1648 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1650 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1651 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1652 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1653 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1654 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1655 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1656 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1658 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1659 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1660 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1661 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1662 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1663 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1665 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1666 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1667 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1668 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1669 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1670 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1672 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1673 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1674 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1675 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1676 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1677 mac_array[3] ^ mac_array[2];
1679 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1680 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1681 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1682 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1683 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1684 mac_array[4] ^ mac_array[3];
1686 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1687 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1688 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1689 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1690 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1693 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1694 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1695 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1696 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1697 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1699 for (i = 0; i < 8; i++)
1700 crc_result = crc_result | (crc[i] << i);
1702 table = OTHER_MCAST_TABLE(port_num);
1703 eth_port_set_filter_table_entry(mp, table, crc_result);
1707 * Set the entire multicast list based on dev->mc_list.
1709 static void eth_port_set_multicast_list(struct net_device *dev)
1712 struct dev_mc_list *mc_list;
1715 struct mv643xx_private *mp = netdev_priv(dev);
1716 unsigned int eth_port_num = mp->port_num;
1718 /* If the device is in promiscuous mode or in all multicast mode,
1719 * we will fully populate both multicast tables with accept.
1720 * This is guaranteed to yield a match on all multicast addresses...
1722 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1723 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1724 /* Set all entries in DA filter special multicast
1726 * Set for ETH_Q0 for now
1728 * 0 Accept=1, Drop=0
1729 * 3-1 Queue ETH_Q0=0
1732 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1734 /* Set all entries in DA filter other multicast
1736 * Set for ETH_Q0 for now
1738 * 0 Accept=1, Drop=0
1739 * 3-1 Queue ETH_Q0=0
1742 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1747 /* We will clear out multicast tables every time we get the list.
1748 * Then add the entire new list...
1750 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1751 /* Clear DA filter special multicast table (Ex_dFSMT) */
1752 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0);
1754 /* Clear DA filter other multicast table (Ex_dFOMT) */
1755 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0);
1758 /* Get pointer to net_device multicast list and add each one... */
1759 for (i = 0, mc_list = dev->mc_list;
1760 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1761 i++, mc_list = mc_list->next)
1762 if (mc_list->dmi_addrlen == 6)
1763 eth_port_mc_addr(mp, mc_list->dmi_addr);
1767 * mv643xx_eth_set_rx_mode
1769 * Change from promiscuos to regular rx mode
1771 * Input : pointer to ethernet interface network device structure
1774 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1776 struct mv643xx_private *mp = netdev_priv(dev);
1779 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1780 if (dev->flags & IFF_PROMISC)
1781 config_reg |= UNICAST_PROMISCUOUS_MODE;
1783 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1784 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1786 eth_port_set_multicast_list(dev);
1790 /* rx/tx queue initialisation ***********************************************/
1792 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1795 * This function prepares a Rx chained list of descriptors and packet
1796 * buffers in a form of a ring. The routine must be called after port
1797 * initialization routine and before port start routine.
1798 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1799 * devices in the system (i.e. DRAM). This function uses the ethernet
1800 * struct 'virtual to physical' routine (set by the user) to set the ring
1801 * with physical addresses.
1804 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1807 * The routine updates the Ethernet port control struct with information
1808 * regarding the Rx descriptors and buffers.
1813 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1815 volatile struct eth_rx_desc *p_rx_desc;
1816 int rx_desc_num = mp->rx_ring_size;
1819 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1820 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1821 for (i = 0; i < rx_desc_num; i++) {
1822 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1823 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1826 /* Save Rx desc pointer to driver struct. */
1827 mp->rx_curr_desc_q = 0;
1828 mp->rx_used_desc_q = 0;
1830 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1833 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1835 struct mv643xx_private *mp = netdev_priv(dev);
1838 /* Stop RX Queues */
1839 mv643xx_eth_port_disable_rx(mp);
1841 /* Free preallocated skb's on RX rings */
1842 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1843 if (mp->rx_skb[curr]) {
1844 dev_kfree_skb(mp->rx_skb[curr]);
1845 mp->rx_desc_count--;
1849 if (mp->rx_desc_count)
1851 "%s: Error in freeing Rx Ring. %d skb's still"
1852 " stuck in RX Ring - ignoring them\n", dev->name,
1855 if (mp->rx_sram_size)
1856 iounmap(mp->p_rx_desc_area);
1858 dma_free_coherent(NULL, mp->rx_desc_area_size,
1859 mp->p_rx_desc_area, mp->rx_desc_dma);
1863 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1866 * This function prepares a Tx chained list of descriptors and packet
1867 * buffers in a form of a ring. The routine must be called after port
1868 * initialization routine and before port start routine.
1869 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1870 * devices in the system (i.e. DRAM). This function uses the ethernet
1871 * struct 'virtual to physical' routine (set by the user) to set the ring
1872 * with physical addresses.
1875 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1878 * The routine updates the Ethernet port control struct with information
1879 * regarding the Tx descriptors and buffers.
1884 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1886 int tx_desc_num = mp->tx_ring_size;
1887 struct eth_tx_desc *p_tx_desc;
1890 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1891 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1892 for (i = 0; i < tx_desc_num; i++) {
1893 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1894 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1897 mp->tx_curr_desc_q = 0;
1898 mp->tx_used_desc_q = 0;
1900 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1904 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1906 * If force is non-zero, frees uncompleted descriptors as well
1908 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1910 struct mv643xx_private *mp = netdev_priv(dev);
1911 struct eth_tx_desc *desc;
1913 struct sk_buff *skb;
1914 unsigned long flags;
1920 while (mp->tx_desc_count > 0) {
1921 spin_lock_irqsave(&mp->lock, flags);
1923 /* tx_desc_count might have changed before acquiring the lock */
1924 if (mp->tx_desc_count <= 0) {
1925 spin_unlock_irqrestore(&mp->lock, flags);
1929 tx_index = mp->tx_used_desc_q;
1930 desc = &mp->p_tx_desc_area[tx_index];
1931 cmd_sts = desc->cmd_sts;
1933 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
1934 spin_unlock_irqrestore(&mp->lock, flags);
1938 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
1939 mp->tx_desc_count--;
1941 addr = desc->buf_ptr;
1942 count = desc->byte_cnt;
1943 skb = mp->tx_skb[tx_index];
1945 mp->tx_skb[tx_index] = NULL;
1947 if (cmd_sts & ETH_ERROR_SUMMARY) {
1948 printk("%s: Error in TX\n", dev->name);
1949 dev->stats.tx_errors++;
1952 spin_unlock_irqrestore(&mp->lock, flags);
1954 if (cmd_sts & ETH_TX_FIRST_DESC)
1955 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1957 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1960 dev_kfree_skb_irq(skb);
1968 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1970 struct mv643xx_private *mp = netdev_priv(dev);
1972 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1973 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1974 netif_wake_queue(dev);
1977 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1979 mv643xx_eth_free_tx_descs(dev, 1);
1982 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1984 struct mv643xx_private *mp = netdev_priv(dev);
1986 /* Stop Tx Queues */
1987 mv643xx_eth_port_disable_tx(mp);
1989 /* Free outstanding skb's on TX ring */
1990 mv643xx_eth_free_all_tx_descs(dev);
1992 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1995 if (mp->tx_sram_size)
1996 iounmap(mp->p_tx_desc_area);
1998 dma_free_coherent(NULL, mp->tx_desc_area_size,
1999 mp->p_tx_desc_area, mp->tx_desc_dma);
2003 /* netdev ops and related ***************************************************/
2004 static void eth_port_reset(struct mv643xx_private *mp);
2006 /* Set the mv643xx port configuration register for the speed/duplex mode. */
2007 static void mv643xx_eth_update_pscr(struct net_device *dev,
2008 struct ethtool_cmd *ecmd)
2010 struct mv643xx_private *mp = netdev_priv(dev);
2011 int port_num = mp->port_num;
2013 unsigned int queues;
2015 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2018 /* clear speed, duplex and rx buffer size fields */
2019 n_pscr &= ~(SET_MII_SPEED_TO_100 |
2020 SET_GMII_SPEED_TO_1000 |
2021 SET_FULL_DUPLEX_MODE |
2022 MAX_RX_PACKET_MASK);
2024 if (ecmd->duplex == DUPLEX_FULL)
2025 n_pscr |= SET_FULL_DUPLEX_MODE;
2027 if (ecmd->speed == SPEED_1000)
2028 n_pscr |= SET_GMII_SPEED_TO_1000 |
2029 MAX_RX_PACKET_9700BYTE;
2031 if (ecmd->speed == SPEED_100)
2032 n_pscr |= SET_MII_SPEED_TO_100;
2033 n_pscr |= MAX_RX_PACKET_1522BYTE;
2036 if (n_pscr != o_pscr) {
2037 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
2038 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
2040 queues = mv643xx_eth_port_disable_tx(mp);
2042 o_pscr &= ~SERIAL_PORT_ENABLE;
2043 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
2044 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
2045 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
2047 mv643xx_eth_port_enable_tx(mp, queues);
2053 * mv643xx_eth_int_handler
2055 * Main interrupt handler for the gigbit ethernet ports
2057 * Input : irq - irq number (not used)
2058 * dev_id - a pointer to the required interface's data structure
2063 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
2065 struct net_device *dev = (struct net_device *)dev_id;
2066 struct mv643xx_private *mp = netdev_priv(dev);
2067 u32 eth_int_cause, eth_int_cause_ext = 0;
2068 unsigned int port_num = mp->port_num;
2070 /* Read interrupt cause registers */
2071 eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & ETH_INT_UNMASK_ALL;
2072 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
2073 eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
2074 & ETH_INT_UNMASK_ALL_EXT;
2075 wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext);
2078 /* PHY status changed */
2079 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
2080 struct ethtool_cmd cmd;
2082 if (mii_link_ok(&mp->mii)) {
2083 mii_ethtool_gset(&mp->mii, &cmd);
2084 mv643xx_eth_update_pscr(dev, &cmd);
2085 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
2086 if (!netif_carrier_ok(dev)) {
2087 netif_carrier_on(dev);
2088 if (mp->tx_ring_size - mp->tx_desc_count >=
2090 netif_wake_queue(dev);
2092 } else if (netif_carrier_ok(dev)) {
2093 netif_stop_queue(dev);
2094 netif_carrier_off(dev);
2099 if (eth_int_cause & ETH_INT_CAUSE_RX) {
2100 /* schedule the NAPI poll routine to maintain port */
2101 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2103 /* wait for previous write to complete */
2104 rdl(mp, INT_MASK(port_num));
2106 netif_rx_schedule(dev, &mp->napi);
2109 if (eth_int_cause & ETH_INT_CAUSE_RX)
2110 mv643xx_eth_receive_queue(dev, INT_MAX);
2112 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
2113 mv643xx_eth_free_completed_tx_descs(dev);
2116 * If no real interrupt occured, exit.
2117 * This can happen when using gigE interrupt coalescing mechanism.
2119 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
2126 * ethernet_phy_reset - Reset Ethernet port PHY.
2129 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2132 * struct mv643xx_private *mp Ethernet Port.
2141 static void ethernet_phy_reset(struct mv643xx_private *mp)
2143 unsigned int phy_reg_data;
2146 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2147 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2148 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2150 /* wait for PHY to come out of reset */
2153 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2154 } while (phy_reg_data & 0x8000);
2158 * eth_port_start - Start the Ethernet port activity.
2161 * This routine prepares the Ethernet port for Rx and Tx activity:
2162 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2163 * has been initialized a descriptor's ring (using
2164 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2165 * 2. Initialize and enable the Ethernet configuration port by writing to
2166 * the port's configuration and command registers.
2167 * 3. Initialize and enable the SDMA by writing to the SDMA's
2168 * configuration and command registers. After completing these steps,
2169 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2171 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2172 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2173 * and ether_init_rx_desc_ring for Rx queues).
2176 * dev - a pointer to the required interface
2179 * Ethernet port is ready to receive and transmit.
2184 static void eth_port_start(struct net_device *dev)
2186 struct mv643xx_private *mp = netdev_priv(dev);
2187 unsigned int port_num = mp->port_num;
2188 int tx_curr_desc, rx_curr_desc;
2190 struct ethtool_cmd ethtool_cmd;
2192 /* Assignment of Tx CTRP of given queue */
2193 tx_curr_desc = mp->tx_curr_desc_q;
2194 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
2195 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2197 /* Assignment of Rx CRDP of given queue */
2198 rx_curr_desc = mp->rx_curr_desc_q;
2199 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
2200 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2202 /* Add the assigned Ethernet address to the port's address table */
2203 eth_port_uc_addr_set(mp, dev->dev_addr);
2206 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2207 * frames to RX queue #0.
2209 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
2211 wrl(mp, PORT_CONFIG_EXT(port_num), PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2213 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2215 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2216 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2218 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2219 DISABLE_AUTO_NEG_SPEED_GMII |
2220 DISABLE_AUTO_NEG_FOR_DUPLX |
2221 DO_NOT_FORCE_LINK_FAIL |
2222 SERIAL_PORT_CONTROL_RESERVED;
2224 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2226 pscr |= SERIAL_PORT_ENABLE;
2227 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2229 /* Assign port SDMA configuration */
2230 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2232 /* Enable port Rx. */
2233 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
2235 /* Disable port bandwidth limits by clearing MTU register */
2236 wrl(mp, TX_BW_MTU(port_num), 0);
2238 /* save phy settings across reset */
2239 mv643xx_get_settings(dev, ðtool_cmd);
2240 ethernet_phy_reset(mp);
2241 mv643xx_set_settings(dev, ðtool_cmd);
2247 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
2250 * This routine sets the RX coalescing interrupt mechanism parameter.
2251 * This parameter is a timeout counter, that counts in 64 t_clk
2252 * chunks ; that when timeout event occurs a maskable interrupt
2254 * The parameter is calculated using the tClk of the MV-643xx chip
2255 * , and the required delay of the interrupt in usec.
2258 * struct mv643xx_private *mp Ethernet port
2259 * unsigned int delay Delay in usec
2262 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2265 * The interrupt coalescing value set in the gigE port.
2268 static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
2271 unsigned int port_num = mp->port_num;
2272 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2274 /* Set RX Coalescing mechanism */
2275 wrl(mp, SDMA_CONFIG(port_num),
2276 ((coal & 0x3fff) << 8) |
2277 (rdl(mp, SDMA_CONFIG(port_num))
2285 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
2288 * This routine sets the TX coalescing interrupt mechanism parameter.
2289 * This parameter is a timeout counter, that counts in 64 t_clk
2290 * chunks ; that when timeout event occurs a maskable interrupt
2292 * The parameter is calculated using the t_cLK frequency of the
2293 * MV-643xx chip and the required delay in the interrupt in uSec
2296 * struct mv643xx_private *mp Ethernet port
2297 * unsigned int delay Delay in uSeconds
2300 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2303 * The interrupt coalescing value set in the gigE port.
2306 static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
2309 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2311 /* Set TX Coalescing mechanism */
2312 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
2318 * eth_port_init - Initialize the Ethernet port driver
2321 * This function prepares the ethernet port to start its activity:
2322 * 1) Completes the ethernet port driver struct initialization toward port
2324 * 2) Resets the device to a quiescent state in case of warm reboot.
2325 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2326 * 4) Clean MAC tables. The reset status of those tables is unknown.
2327 * 5) Set PHY address.
2328 * Note: Call this routine prior to eth_port_start routine and after
2329 * setting user values in the user fields of Ethernet port control
2333 * struct mv643xx_private *mp Ethernet port control struct
2341 static void eth_port_init(struct mv643xx_private *mp)
2343 mp->rx_resource_err = 0;
2347 eth_port_init_mac_tables(mp);
2353 * This function is called when openning the network device. The function
2354 * should initialize all the hardware, initialize cyclic Rx/Tx
2355 * descriptors chain and buffers and allocate an IRQ to the network
2358 * Input : a pointer to the network device structure
2360 * Output : zero of success , nonzero if fails.
2363 static int mv643xx_eth_open(struct net_device *dev)
2365 struct mv643xx_private *mp = netdev_priv(dev);
2366 unsigned int port_num = mp->port_num;
2370 /* Clear any pending ethernet port interrupts */
2371 wrl(mp, INT_CAUSE(port_num), 0);
2372 wrl(mp, INT_CAUSE_EXT(port_num), 0);
2373 /* wait for previous write to complete */
2374 rdl(mp, INT_CAUSE_EXT(port_num));
2376 err = request_irq(dev->irq, mv643xx_eth_int_handler,
2377 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
2379 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
2385 memset(&mp->timeout, 0, sizeof(struct timer_list));
2386 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
2387 mp->timeout.data = (unsigned long)dev;
2389 /* Allocate RX and TX skb rings */
2390 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
2393 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
2397 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
2400 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
2402 goto out_free_rx_skb;
2405 /* Allocate TX ring */
2406 mp->tx_desc_count = 0;
2407 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
2408 mp->tx_desc_area_size = size;
2410 if (mp->tx_sram_size) {
2411 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
2413 mp->tx_desc_dma = mp->tx_sram_addr;
2415 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
2419 if (!mp->p_tx_desc_area) {
2420 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
2423 goto out_free_tx_skb;
2425 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
2426 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
2428 ether_init_tx_desc_ring(mp);
2430 /* Allocate RX ring */
2431 mp->rx_desc_count = 0;
2432 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
2433 mp->rx_desc_area_size = size;
2435 if (mp->rx_sram_size) {
2436 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
2438 mp->rx_desc_dma = mp->rx_sram_addr;
2440 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
2444 if (!mp->p_rx_desc_area) {
2445 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
2447 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
2449 if (mp->rx_sram_size)
2450 iounmap(mp->p_tx_desc_area);
2452 dma_free_coherent(NULL, mp->tx_desc_area_size,
2453 mp->p_tx_desc_area, mp->tx_desc_dma);
2455 goto out_free_tx_skb;
2457 memset((void *)mp->p_rx_desc_area, 0, size);
2459 ether_init_rx_desc_ring(mp);
2461 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
2464 napi_enable(&mp->napi);
2467 eth_port_start(dev);
2469 /* Interrupt Coalescing */
2473 eth_port_set_rx_coal(mp, MV643XX_RX_COAL);
2477 eth_port_set_tx_coal(mp, MV643XX_TX_COAL);
2479 /* Unmask phy and link status changes interrupts */
2480 wrl(mp, INT_MASK_EXT(port_num), ETH_INT_UNMASK_ALL_EXT);
2482 /* Unmask RX buffer and TX end interrupt */
2483 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
2492 free_irq(dev->irq, dev);
2498 * eth_port_reset - Reset Ethernet port
2501 * This routine resets the chip by aborting any SDMA engine activity and
2502 * clearing the MIB counters. The Receiver and the Transmit unit are in
2503 * idle state after this command is performed and the port is disabled.
2506 * struct mv643xx_private *mp Ethernet Port.
2509 * Channel activity is halted.
2515 static void eth_port_reset(struct mv643xx_private *mp)
2517 unsigned int port_num = mp->port_num;
2518 unsigned int reg_data;
2520 mv643xx_eth_port_disable_tx(mp);
2521 mv643xx_eth_port_disable_rx(mp);
2523 /* Clear all MIB counters */
2524 eth_clear_mib_counters(mp);
2526 /* Reset the Enable bit in the Configuration Register */
2527 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2528 reg_data &= ~(SERIAL_PORT_ENABLE |
2529 DO_NOT_FORCE_LINK_FAIL |
2531 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
2537 * This function is used when closing the network device.
2538 * It updates the hardware,
2539 * release all memory that holds buffers and descriptors and release the IRQ.
2540 * Input : a pointer to the device structure
2541 * Output : zero if success , nonzero if fails
2544 static int mv643xx_eth_stop(struct net_device *dev)
2546 struct mv643xx_private *mp = netdev_priv(dev);
2547 unsigned int port_num = mp->port_num;
2549 /* Mask all interrupts on ethernet port */
2550 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2551 /* wait for previous write to complete */
2552 rdl(mp, INT_MASK(port_num));
2555 napi_disable(&mp->napi);
2557 netif_carrier_off(dev);
2558 netif_stop_queue(dev);
2562 mv643xx_eth_free_tx_rings(dev);
2563 mv643xx_eth_free_rx_rings(dev);
2565 free_irq(dev->irq, dev);
2570 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2572 struct mv643xx_private *mp = netdev_priv(dev);
2574 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2578 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
2580 * Input : pointer to ethernet interface network device structure
2582 * Output : 0 upon success, -EINVAL upon failure
2584 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2586 if ((new_mtu > 9500) || (new_mtu < 64))
2590 if (!netif_running(dev))
2594 * Stop and then re-open the interface. This will allocate RX
2595 * skbs of the new MTU.
2596 * There is a possible danger that the open will not succeed,
2597 * due to memory being full, which might fail the open function.
2599 mv643xx_eth_stop(dev);
2600 if (mv643xx_eth_open(dev)) {
2601 printk(KERN_ERR "%s: Fatal error on opening device\n",
2609 * mv643xx_eth_tx_timeout_task
2611 * Actual routine to reset the adapter when a timeout on Tx has occurred
2613 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
2615 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
2617 struct net_device *dev = mp->dev;
2619 if (!netif_running(dev))
2622 netif_stop_queue(dev);
2625 eth_port_start(dev);
2627 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
2628 netif_wake_queue(dev);
2632 * mv643xx_eth_tx_timeout
2634 * Called upon a timeout on transmitting a packet
2636 * Input : pointer to ethernet interface network device structure.
2639 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2641 struct mv643xx_private *mp = netdev_priv(dev);
2643 printk(KERN_INFO "%s: TX timeout ", dev->name);
2645 /* Do the reset outside of interrupt context */
2646 schedule_work(&mp->tx_timeout_task);
2649 #ifdef CONFIG_NET_POLL_CONTROLLER
2650 static void mv643xx_netpoll(struct net_device *netdev)
2652 struct mv643xx_private *mp = netdev_priv(netdev);
2653 int port_num = mp->port_num;
2655 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2656 /* wait for previous write to complete */
2657 rdl(mp, INT_MASK(port_num));
2659 mv643xx_eth_int_handler(netdev->irq, netdev);
2661 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
2666 * Wrappers for MII support library.
2668 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2670 struct mv643xx_private *mp = netdev_priv(dev);
2673 eth_port_read_smi_reg(mp, location, &val);
2677 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2679 struct mv643xx_private *mp = netdev_priv(dev);
2680 eth_port_write_smi_reg(mp, location, val);
2684 /* platform glue ************************************************************/
2685 static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
2686 struct mbus_dram_target_info *dram)
2688 void __iomem *base = msp->eth_base;
2693 for (i = 0; i < 6; i++) {
2694 writel(0, base + WINDOW_BASE(i));
2695 writel(0, base + WINDOW_SIZE(i));
2697 writel(0, base + WINDOW_REMAP_HIGH(i));
2703 for (i = 0; i < dram->num_cs; i++) {
2704 struct mbus_dram_window *cs = dram->cs + i;
2706 writel((cs->base & 0xffff0000) |
2707 (cs->mbus_attr << 8) |
2708 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2709 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2711 win_enable &= ~(1 << i);
2712 win_protect |= 3 << (2 * i);
2715 writel(win_enable, base + WINDOW_BAR_ENABLE);
2716 msp->win_protect = win_protect;
2719 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2721 static int mv643xx_version_printed = 0;
2722 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2723 struct mv643xx_shared_private *msp;
2724 struct resource *res;
2727 if (!mv643xx_version_printed++)
2728 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2731 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2736 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2739 memset(msp, 0, sizeof(*msp));
2741 msp->eth_base = ioremap(res->start, res->end - res->start + 1);
2742 if (msp->eth_base == NULL)
2745 spin_lock_init(&msp->phy_lock);
2746 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2748 platform_set_drvdata(pdev, msp);
2751 * (Re-)program MBUS remapping windows if we are asked to.
2753 if (pd != NULL && pd->dram != NULL)
2754 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2764 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2766 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2768 iounmap(msp->eth_base);
2774 static struct platform_driver mv643xx_eth_shared_driver = {
2775 .probe = mv643xx_eth_shared_probe,
2776 .remove = mv643xx_eth_shared_remove,
2778 .name = MV643XX_ETH_SHARED_NAME,
2779 .owner = THIS_MODULE,
2784 * ethernet_phy_set - Set the ethernet port PHY address.
2787 * This routine sets the given ethernet port PHY address.
2790 * struct mv643xx_private *mp Ethernet Port.
2791 * int phy_addr PHY address.
2800 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2803 int addr_shift = 5 * mp->port_num;
2805 reg_data = rdl(mp, PHY_ADDR);
2806 reg_data &= ~(0x1f << addr_shift);
2807 reg_data |= (phy_addr & 0x1f) << addr_shift;
2808 wrl(mp, PHY_ADDR, reg_data);
2812 * ethernet_phy_get - Get the ethernet port PHY address.
2815 * This routine returns the given ethernet port PHY address.
2818 * struct mv643xx_private *mp Ethernet Port.
2827 static int ethernet_phy_get(struct mv643xx_private *mp)
2829 unsigned int reg_data;
2831 reg_data = rdl(mp, PHY_ADDR);
2833 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2837 * ethernet_phy_detect - Detect whether a phy is present
2840 * This function tests whether there is a PHY present on
2841 * the specified port.
2844 * struct mv643xx_private *mp Ethernet Port.
2851 * -ENODEV on failure
2854 static int ethernet_phy_detect(struct mv643xx_private *mp)
2856 unsigned int phy_reg_data0;
2859 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2860 auto_neg = phy_reg_data0 & 0x1000;
2861 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2862 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2864 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2865 if ((phy_reg_data0 & 0x1000) == auto_neg)
2866 return -ENODEV; /* change didn't take */
2868 phy_reg_data0 ^= 0x1000;
2869 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2873 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2874 int speed, int duplex,
2875 struct ethtool_cmd *cmd)
2877 struct mv643xx_private *mp = netdev_priv(dev);
2879 memset(cmd, 0, sizeof(*cmd));
2881 cmd->port = PORT_MII;
2882 cmd->transceiver = XCVR_INTERNAL;
2883 cmd->phy_address = phy_address;
2886 cmd->autoneg = AUTONEG_ENABLE;
2887 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2888 cmd->speed = SPEED_100;
2889 cmd->advertising = ADVERTISED_10baseT_Half |
2890 ADVERTISED_10baseT_Full |
2891 ADVERTISED_100baseT_Half |
2892 ADVERTISED_100baseT_Full;
2893 if (mp->mii.supports_gmii)
2894 cmd->advertising |= ADVERTISED_1000baseT_Full;
2896 cmd->autoneg = AUTONEG_DISABLE;
2898 cmd->duplex = duplex;
2905 * First function called after registering the network device.
2906 * It's purpose is to initialize the device as an ethernet device,
2907 * fill the ethernet device structure with pointers * to functions,
2908 * and set the MAC address of the interface
2910 * Input : struct device *
2911 * Output : -ENOMEM if failed , 0 if success
2913 static int mv643xx_eth_probe(struct platform_device *pdev)
2915 struct mv643xx_eth_platform_data *pd;
2917 struct mv643xx_private *mp;
2918 struct net_device *dev;
2920 struct resource *res;
2922 struct ethtool_cmd cmd;
2923 int duplex = DUPLEX_HALF;
2924 int speed = 0; /* default to auto-negotiation */
2925 DECLARE_MAC_BUF(mac);
2927 pd = pdev->dev.platform_data;
2929 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2933 if (pd->shared == NULL) {
2934 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2938 dev = alloc_etherdev(sizeof(struct mv643xx_private));
2942 platform_set_drvdata(pdev, dev);
2944 mp = netdev_priv(dev);
2947 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
2950 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2952 dev->irq = res->start;
2954 dev->open = mv643xx_eth_open;
2955 dev->stop = mv643xx_eth_stop;
2956 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2957 dev->set_mac_address = mv643xx_eth_set_mac_address;
2958 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2960 /* No need to Tx Timeout */
2961 dev->tx_timeout = mv643xx_eth_tx_timeout;
2963 #ifdef CONFIG_NET_POLL_CONTROLLER
2964 dev->poll_controller = mv643xx_netpoll;
2967 dev->watchdog_timeo = 2 * HZ;
2969 dev->change_mtu = mv643xx_eth_change_mtu;
2970 dev->do_ioctl = mv643xx_eth_do_ioctl;
2971 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
2973 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2974 #ifdef MAX_SKB_FRAGS
2976 * Zero copy can only work if we use Discovery II memory. Else, we will
2977 * have to map the buffers to ISA memory which is only 16 MB
2979 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2983 /* Configure the timeout task */
2984 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2986 spin_lock_init(&mp->lock);
2988 mp->shared = platform_get_drvdata(pd->shared);
2989 port_num = mp->port_num = pd->port_number;
2991 if (mp->shared->win_protect)
2992 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2994 mp->shared_smi = mp->shared;
2995 if (pd->shared_smi != NULL)
2996 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2998 /* set default config values */
2999 eth_port_uc_addr_get(mp, dev->dev_addr);
3000 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
3001 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
3003 if (is_valid_ether_addr(pd->mac_addr))
3004 memcpy(dev->dev_addr, pd->mac_addr, 6);
3006 if (pd->phy_addr || pd->force_phy_addr)
3007 ethernet_phy_set(mp, pd->phy_addr);
3009 if (pd->rx_queue_size)
3010 mp->rx_ring_size = pd->rx_queue_size;
3012 if (pd->tx_queue_size)
3013 mp->tx_ring_size = pd->tx_queue_size;
3015 if (pd->tx_sram_size) {
3016 mp->tx_sram_size = pd->tx_sram_size;
3017 mp->tx_sram_addr = pd->tx_sram_addr;
3020 if (pd->rx_sram_size) {
3021 mp->rx_sram_size = pd->rx_sram_size;
3022 mp->rx_sram_addr = pd->rx_sram_addr;
3025 duplex = pd->duplex;
3028 /* Hook up MII support for ethtool */
3030 mp->mii.mdio_read = mv643xx_mdio_read;
3031 mp->mii.mdio_write = mv643xx_mdio_write;
3032 mp->mii.phy_id = ethernet_phy_get(mp);
3033 mp->mii.phy_id_mask = 0x3f;
3034 mp->mii.reg_num_mask = 0x1f;
3036 err = ethernet_phy_detect(mp);
3038 pr_debug("%s: No PHY detected at addr %d\n",
3039 dev->name, ethernet_phy_get(mp));
3043 ethernet_phy_reset(mp);
3044 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
3045 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
3046 mv643xx_eth_update_pscr(dev, &cmd);
3047 mv643xx_set_settings(dev, &cmd);
3049 SET_NETDEV_DEV(dev, &pdev->dev);
3050 err = register_netdev(dev);
3056 "%s: port %d with MAC address %s\n",
3057 dev->name, port_num, print_mac(mac, p));
3059 if (dev->features & NETIF_F_SG)
3060 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
3062 if (dev->features & NETIF_F_IP_CSUM)
3063 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
3066 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
3067 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
3071 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
3076 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
3079 if (mp->tx_sram_size > 0)
3080 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
3090 static int mv643xx_eth_remove(struct platform_device *pdev)
3092 struct net_device *dev = platform_get_drvdata(pdev);
3094 unregister_netdev(dev);
3095 flush_scheduled_work();
3098 platform_set_drvdata(pdev, NULL);
3102 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3104 struct net_device *dev = platform_get_drvdata(pdev);
3105 struct mv643xx_private *mp = netdev_priv(dev);
3106 unsigned int port_num = mp->port_num;
3108 /* Mask all interrupts on ethernet port */
3109 wrl(mp, INT_MASK(port_num), 0);
3110 rdl(mp, INT_MASK(port_num));
3115 static struct platform_driver mv643xx_eth_driver = {
3116 .probe = mv643xx_eth_probe,
3117 .remove = mv643xx_eth_remove,
3118 .shutdown = mv643xx_eth_shutdown,
3120 .name = MV643XX_ETH_NAME,
3121 .owner = THIS_MODULE,
3126 * mv643xx_init_module
3128 * Registers the network drivers into the Linux kernel
3134 static int __init mv643xx_init_module(void)
3138 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3140 rc = platform_driver_register(&mv643xx_eth_driver);
3142 platform_driver_unregister(&mv643xx_eth_shared_driver);
3148 * mv643xx_cleanup_module
3150 * Registers the network drivers into the Linux kernel
3156 static void __exit mv643xx_cleanup_module(void)
3158 platform_driver_unregister(&mv643xx_eth_driver);
3159 platform_driver_unregister(&mv643xx_eth_shared_driver);
3162 module_init(mv643xx_init_module);
3163 module_exit(mv643xx_cleanup_module);
3165 MODULE_LICENSE("GPL");
3166 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
3167 " and Dale Farnsworth");
3168 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3169 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3170 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);