drivers/net/mlx4/profile.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include "mlx4.h"
  38 #include "fw.h"
  39
  40 enum {
  41         MLX4_RES_QP,
  42         MLX4_RES_RDMARC,
  43         MLX4_RES_ALTC,
  44         MLX4_RES_AUXC,
  45         MLX4_RES_SRQ,
  46         MLX4_RES_CQ,
  47         MLX4_RES_EQ,
  48         MLX4_RES_DMPT,
  49         MLX4_RES_CMPT,
  50         MLX4_RES_MTT,
  51         MLX4_RES_MCG,
  52         MLX4_RES_NUM
  53 };
  54
  55 static const char *res_name[] = {
  56         [MLX4_RES_QP]           = "QP",
  57         [MLX4_RES_RDMARC]       = "RDMARC",
  58         [MLX4_RES_ALTC]         = "ALTC",
  59         [MLX4_RES_AUXC]         = "AUXC",
  60         [MLX4_RES_SRQ]          = "SRQ",
  61         [MLX4_RES_CQ]           = "CQ",
  62         [MLX4_RES_EQ]           = "EQ",
  63         [MLX4_RES_DMPT]         = "DMPT",
  64         [MLX4_RES_CMPT]         = "CMPT",
  65         [MLX4_RES_MTT]          = "MTT",
  66         [MLX4_RES_MCG]          = "MCG",
  67 };
  68
  69 u64 mlx4_make_profile(struct mlx4_dev *dev,
  70                       struct mlx4_profile *request,
  71                       struct mlx4_dev_cap *dev_cap,
  72                       struct mlx4_init_hca_param *init_hca)
  73 {
  74         struct mlx4_priv *priv = mlx4_priv(dev);
  75         struct mlx4_resource {
  76                 u64 size;
  77                 u64 start;
  78                 int type;
  79                 int num;
  80                 int log_num;
  81         };
  82
  83         u64 total_size = 0;
  84         struct mlx4_resource *profile;
  85         struct mlx4_resource tmp;
  86         int i, j;
  87
  88         profile = kzalloc(MLX4_RES_NUM * sizeof *profile, GFP_KERNEL);
  89         if (!profile)
  90                 return -ENOMEM;
  91
  92         profile[MLX4_RES_QP].size     = dev_cap->qpc_entry_sz;
  93         profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
  94         profile[MLX4_RES_ALTC].size   = dev_cap->altc_entry_sz;
  95         profile[MLX4_RES_AUXC].size   = dev_cap->aux_entry_sz;
  96         profile[MLX4_RES_SRQ].size    = dev_cap->srq_entry_sz;
  97         profile[MLX4_RES_CQ].size     = dev_cap->cqc_entry_sz;
  98         profile[MLX4_RES_EQ].size     = dev_cap->eqc_entry_sz;
  99         profile[MLX4_RES_DMPT].size   = dev_cap->dmpt_entry_sz;
 100         profile[MLX4_RES_CMPT].size   = dev_cap->cmpt_entry_sz;
 101         profile[MLX4_RES_MTT].size    = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
 102         profile[MLX4_RES_MCG].size    = MLX4_MGM_ENTRY_SIZE;
 103
 104         profile[MLX4_RES_QP].num      = request->num_qp;
 105         profile[MLX4_RES_RDMARC].num  = request->num_qp * request->rdmarc_per_qp;
 106         profile[MLX4_RES_ALTC].num    = request->num_qp;
 107         profile[MLX4_RES_AUXC].num    = request->num_qp;
 108         profile[MLX4_RES_SRQ].num     = request->num_srq;
 109         profile[MLX4_RES_CQ].num      = request->num_cq;
 110         profile[MLX4_RES_EQ].num      = min(dev_cap->max_eqs,
 111                                             dev_cap->reserved_eqs +
 112                                             num_possible_cpus() + 1);
 113         profile[MLX4_RES_DMPT].num    = request->num_mpt;
 114         profile[MLX4_RES_CMPT].num    = MLX4_NUM_CMPTS;
 115         profile[MLX4_RES_MTT].num     = request->num_mtt;
 116         profile[MLX4_RES_MCG].num     = request->num_mcg;
 117
 118         for (i = 0; i < MLX4_RES_NUM; ++i) {
 119                 profile[i].type     = i;
 120                 profile[i].num      = roundup_pow_of_two(profile[i].num);
 121                 profile[i].log_num  = ilog2(profile[i].num);
 122                 profile[i].size    *= profile[i].num;
 123                 profile[i].size     = max(profile[i].size, (u64) PAGE_SIZE);
 124         }
 125
 126         /*
 127          * Sort the resources in decreasing order of size.  Since they
 128          * all have sizes that are powers of 2, we'll be able to keep
 129          * resources aligned to their size and pack them without gaps
 130          * using the sorted order.
 131          */
 132         for (i = MLX4_RES_NUM; i > 0; --i)
 133                 for (j = 1; j < i; ++j) {
 134                         if (profile[j].size > profile[j - 1].size) {
 135                                 tmp            = profile[j];
 136                                 profile[j]     = profile[j - 1];
 137                                 profile[j - 1] = tmp;
 138                         }
 139                 }
 140
 141         for (i = 0; i < MLX4_RES_NUM; ++i) {
 142                 if (profile[i].size) {
 143                         profile[i].start = total_size;
 144                         total_size      += profile[i].size;
 145                 }
 146
 147                 if (total_size > dev_cap->max_icm_sz) {
 148                         mlx4_err(dev, "Profile requires 0x%llx bytes; "
 149                                   "won't fit in 0x%llx bytes of context memory.\n",
 150                                   (unsigned long long) total_size,
 151                                   (unsigned long long) dev_cap->max_icm_sz);
 152                         kfree(profile);
 153                         return -ENOMEM;
 154                 }
 155
 156                 if (profile[i].size)
 157                         mlx4_dbg(dev, "  profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, "
 158                                   "size 0x%10llx\n",
 159                                  i, res_name[profile[i].type], profile[i].log_num,
 160                                  (unsigned long long) profile[i].start,
 161                                  (unsigned long long) profile[i].size);
 162         }
 163
 164         mlx4_dbg(dev, "HCA context memory: reserving %d KB\n",
 165                  (int) (total_size >> 10));
 166
 167         for (i = 0; i < MLX4_RES_NUM; ++i) {
 168                 switch (profile[i].type) {
 169                 case MLX4_RES_QP:
 170                         dev->caps.num_qps     = profile[i].num;
 171                         init_hca->qpc_base    = profile[i].start;
 172                         init_hca->log_num_qps = profile[i].log_num;
 173                         break;
 174                 case MLX4_RES_RDMARC:
 175                         for (priv->qp_table.rdmarc_shift = 0;
 176                              request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num;
 177                              ++priv->qp_table.rdmarc_shift)
 178                                 ; /* nothing */
 179                         dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift;
 180                         priv->qp_table.rdmarc_base   = (u32) profile[i].start;
 181                         init_hca->rdmarc_base        = profile[i].start;
 182                         init_hca->log_rd_per_qp      = priv->qp_table.rdmarc_shift;
 183                         break;
 184                 case MLX4_RES_ALTC:
 185                         init_hca->altc_base = profile[i].start;
 186                         break;
 187                 case MLX4_RES_AUXC:
 188                         init_hca->auxc_base = profile[i].start;
 189                         break;
 190                 case MLX4_RES_SRQ:
 191                         dev->caps.num_srqs     = profile[i].num;
 192                         init_hca->srqc_base    = profile[i].start;
 193                         init_hca->log_num_srqs = profile[i].log_num;
 194                         break;
 195                 case MLX4_RES_CQ:
 196                         dev->caps.num_cqs     = profile[i].num;
 197                         init_hca->cqc_base    = profile[i].start;
 198                         init_hca->log_num_cqs = profile[i].log_num;
 199                         break;
 200                 case MLX4_RES_EQ:
 201                         dev->caps.num_eqs     = profile[i].num;
 202                         init_hca->eqc_base    = profile[i].start;
 203                         init_hca->log_num_eqs = profile[i].log_num;
 204                         break;
 205                 case MLX4_RES_DMPT:
 206                         dev->caps.num_mpts      = profile[i].num;
 207                         priv->mr_table.mpt_base = profile[i].start;
 208                         init_hca->dmpt_base     = profile[i].start;
 209                         init_hca->log_mpt_sz    = profile[i].log_num;
 210                         break;
 211                 case MLX4_RES_CMPT:
 212                         init_hca->cmpt_base      = profile[i].start;
 213                         break;
 214                 case MLX4_RES_MTT:
 215                         dev->caps.num_mtt_segs   = profile[i].num;
 216                         priv->mr_table.mtt_base  = profile[i].start;
 217                         init_hca->mtt_base       = profile[i].start;
 218                         break;
 219                 case MLX4_RES_MCG:
 220                         dev->caps.num_mgms        = profile[i].num >> 1;
 221                         dev->caps.num_amgms       = profile[i].num >> 1;
 222                         init_hca->mc_base         = profile[i].start;
 223                         init_hca->log_mc_entry_sz = ilog2(MLX4_MGM_ENTRY_SIZE);
 224                         init_hca->log_mc_table_sz = profile[i].log_num;
 225                         init_hca->log_mc_hash_sz  = profile[i].log_num - 1;
 226                         break;
 227                 default:
 228                         break;
 229                 }
 230         }
 231
 232         /*
 233          * PDs don't take any HCA memory, but we assign them as part
 234          * of the HCA profile anyway.
 235          */
 236         dev->caps.num_pds = MLX4_NUM_PDS;
 237
 238         kfree(profile);
 239         return total_size;
 240 }