drivers/net/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34 //#include "ixgbe_mbx.h"
  35
  36 #define IXGBE_X540_MAX_TX_QUEUES 128
  37 #define IXGBE_X540_MAX_RX_QUEUES 128
  38 #define IXGBE_X540_RAR_ENTRIES   128
  39 #define IXGBE_X540_MC_TBL_SIZE   128
  40 #define IXGBE_X540_VFT_TBL_SIZE  128
  41
  42 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  43 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  44 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  48
  49 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
  50 {
  51         return ixgbe_media_type_copper;
  52 }
  53
  54 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
  55 {
  56         struct ixgbe_mac_info *mac = &hw->mac;
  57
  58         /* Call PHY identify routine to get the phy type */
  59         ixgbe_identify_phy_generic(hw);
  60
  61         mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
  62         mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
  63         mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
  64         mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
  65         mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
  66         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
  73  *  @hw: pointer to hardware structure
  74  *  @speed: new link speed
  75  *  @autoneg: true if autonegotiation enabled
  76  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  77  **/
  78 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
  79                                      ixgbe_link_speed speed, bool autoneg,
  80                                      bool autoneg_wait_to_complete)
  81 {
  82         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
  83                                             autoneg_wait_to_complete);
  84 }
  85
  86 /**
  87  *  ixgbe_reset_hw_X540 - Perform hardware reset
  88  *  @hw: pointer to hardware structure
  89  *
  90  *  Resets the hardware by resetting the transmit and receive units, masks
  91  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  92  *  reset.
  93  **/
  94 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
  95 {
  96         ixgbe_link_speed link_speed;
  97         s32 status = 0;
  98         u32 ctrl;
  99         u32 ctrl_ext;
 100         u32 reset_bit;
 101         u32 i;
 102         u32 autoc;
 103         u32 autoc2;
 104         bool link_up = false;
 105
 106         /* Call adapter stop to disable tx/rx and clear interrupts */
 107         hw->mac.ops.stop_adapter(hw);
 108
 109         /*
 110          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 111          * access and verify no pending requests before reset
 112          */
 113         status = ixgbe_disable_pcie_master(hw);
 114         if (status != 0) {
 115                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 116                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 117         }
 118
 119         /*
 120          * Issue global reset to the MAC.  Needs to be SW reset if link is up.
 121          * If link reset is used when link is up, it might reset the PHY when
 122          * mng is using it.  If link is down or the flag to force full link
 123          * reset is set, then perform link reset.
 124          */
 125         if (hw->force_full_reset) {
 126                 reset_bit = IXGBE_CTRL_LNK_RST;
 127         } else {
 128                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 129                 if (!link_up)
 130                         reset_bit = IXGBE_CTRL_LNK_RST;
 131                 else
 132                         reset_bit = IXGBE_CTRL_RST;
 133         }
 134
 135         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 136         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | reset_bit));
 137         IXGBE_WRITE_FLUSH(hw);
 138
 139         /* Poll for reset bit to self-clear indicating reset is complete */
 140         for (i = 0; i < 10; i++) {
 141                 udelay(1);
 142                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 143                 if (!(ctrl & reset_bit))
 144                         break;
 145         }
 146         if (ctrl & reset_bit) {
 147                 status = IXGBE_ERR_RESET_FAILED;
 148                 hw_dbg(hw, "Reset polling failed to complete.\n");
 149         }
 150
 151         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 152         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 153         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 154         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 155
 156         msleep(50);
 157
 158         /* Set the Rx packet buffer size. */
 159         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 160
 161         /* Store the permanent mac address */
 162         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 163
 164         /*
 165          * Store the original AUTOC/AUTOC2 values if they have not been
 166          * stored off yet.  Otherwise restore the stored original
 167          * values since the reset operation sets back to defaults.
 168          */
 169         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 170         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 171         if (hw->mac.orig_link_settings_stored == false) {
 172                 hw->mac.orig_autoc = autoc;
 173                 hw->mac.orig_autoc2 = autoc2;
 174                 hw->mac.orig_link_settings_stored = true;
 175         } else {
 176                 if (autoc != hw->mac.orig_autoc)
 177                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 178                                         IXGBE_AUTOC_AN_RESTART));
 179
 180                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 181                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 182                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 183                         autoc2 |= (hw->mac.orig_autoc2 &
 184                                    IXGBE_AUTOC2_UPPER_MASK);
 185                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 186                 }
 187         }
 188
 189         /*
 190          * Store MAC address from RAR0, clear receive address registers, and
 191          * clear the multicast table.  Also reset num_rar_entries to 128,
 192          * since we modify this value when programming the SAN MAC address.
 193          */
 194         hw->mac.num_rar_entries = 128;
 195         hw->mac.ops.init_rx_addrs(hw);
 196
 197         /* Store the permanent mac address */
 198         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 199
 200         /* Store the permanent SAN mac address */
 201         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 202
 203         /* Add the SAN MAC address to the RAR only if it's a valid address */
 204         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 205                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 206                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 207
 208                 /* Reserve the last RAR for the SAN MAC address */
 209                 hw->mac.num_rar_entries--;
 210         }
 211
 212         /* Store the alternative WWNN/WWPN prefix */
 213         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 214                                    &hw->mac.wwpn_prefix);
 215
 216         return status;
 217 }
 218
 219 /**
 220  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 221  *  @hw: pointer to hardware structure
 222  *
 223  *  Determines physical layer capabilities of the current configuration.
 224  **/
 225 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 226 {
 227         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 228         u16 ext_ability = 0;
 229
 230         hw->phy.ops.identify(hw);
 231
 232         hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
 233                              &ext_ability);
 234         if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
 235                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 236         if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
 237                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 238         if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
 239                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 240
 241         return physical_layer;
 242 }
 243
 244 /**
 245  * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 246  * @hw: pointer to hardware structure
 247  **/
 248 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 249 {
 250         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 251         u32 eec;
 252         u16 eeprom_size;
 253
 254         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 255                 eeprom->semaphore_delay = 10;
 256                 eeprom->type = ixgbe_flash;
 257
 258                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 259                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 260                                     IXGBE_EEC_SIZE_SHIFT);
 261                 eeprom->word_size = 1 << (eeprom_size +
 262                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 263
 264                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 265                         eeprom->type, eeprom->word_size);
 266         }
 267
 268         return 0;
 269 }
 270
 271 /**
 272  * ixgbe_read_eerd_X540 - Read EEPROM word using EERD
 273  * @hw: pointer to hardware structure
 274  * @offset: offset of word in the EEPROM to read
 275  * @data: word read from the EERPOM
 276  **/
 277 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 278 {
 279         s32 status;
 280
 281         if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0)
 282                 status = ixgbe_read_eerd_generic(hw, offset, data);
 283         else
 284                 status = IXGBE_ERR_SWFW_SYNC;
 285
 286         ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM);
 287         return status;
 288 }
 289
 290 /**
 291  * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 292  * @hw: pointer to hardware structure
 293  * @offset: offset of  word in the EEPROM to write
 294  * @data: word write to the EEPROM
 295  *
 296  * Write a 16 bit word to the EEPROM using the EEWR register.
 297  **/
 298 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 299 {
 300         u32 eewr;
 301         s32 status;
 302
 303         hw->eeprom.ops.init_params(hw);
 304
 305         if (offset >= hw->eeprom.word_size) {
 306                 status = IXGBE_ERR_EEPROM;
 307                 goto out;
 308         }
 309
 310         eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
 311                (data << IXGBE_EEPROM_RW_REG_DATA) |
 312                IXGBE_EEPROM_RW_REG_START;
 313
 314         if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0) {
 315                 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
 316                 if (status != 0) {
 317                         hw_dbg(hw, "Eeprom write EEWR timed out\n");
 318                         goto out;
 319                 }
 320
 321                 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
 322
 323                 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
 324                 if (status != 0) {
 325                         hw_dbg(hw, "Eeprom write EEWR timed out\n");
 326                         goto out;
 327                 }
 328         } else {
 329                 status = IXGBE_ERR_SWFW_SYNC;
 330         }
 331
 332 out:
 333         ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM);
 334         return status;
 335 }
 336
 337 /**
 338  * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 339  * @hw: pointer to hardware structure
 340  **/
 341 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 342 {
 343         u16 i;
 344         u16 j;
 345         u16 checksum = 0;
 346         u16 length = 0;
 347         u16 pointer = 0;
 348         u16 word = 0;
 349
 350         /* Include 0x0-0x3F in the checksum */
 351         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 352                 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
 353                         hw_dbg(hw, "EEPROM read failed\n");
 354                         break;
 355                 }
 356                 checksum += word;
 357         }
 358
 359         /*
 360          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 361          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 362          */
 363         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 364                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 365                         continue;
 366
 367                 if (hw->eeprom.ops.read(hw, i, &pointer) != 0) {
 368                         hw_dbg(hw, "EEPROM read failed\n");
 369                         break;
 370                 }
 371
 372                 /* Skip pointer section if the pointer is invalid. */
 373                 if (pointer == 0xFFFF || pointer == 0 ||
 374                     pointer >= hw->eeprom.word_size)
 375                         continue;
 376
 377                 if (hw->eeprom.ops.read(hw, pointer, &length) != 0) {
 378                         hw_dbg(hw, "EEPROM read failed\n");
 379                         break;
 380                 }
 381
 382                 /* Skip pointer section if length is invalid. */
 383                 if (length == 0xFFFF || length == 0 ||
 384                     (pointer + length) >= hw->eeprom.word_size)
 385                         continue;
 386
 387                 for (j = pointer+1; j <= pointer+length; j++) {
 388                         if (hw->eeprom.ops.read(hw, j, &word) != 0) {
 389                                 hw_dbg(hw, "EEPROM read failed\n");
 390                                 break;
 391                         }
 392                         checksum += word;
 393                 }
 394         }
 395
 396         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 397
 398         return checksum;
 399 }
 400
 401 /**
 402  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 403  * @hw: pointer to hardware structure
 404  *
 405  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 406  * checksum and updates the EEPROM and instructs the hardware to update
 407  * the flash.
 408  **/
 409 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 410 {
 411         s32 status;
 412
 413         status = ixgbe_update_eeprom_checksum_generic(hw);
 414
 415         if (status)
 416                 status = ixgbe_update_flash_X540(hw);
 417
 418         return status;
 419 }
 420
 421 /**
 422  * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 423  * @hw: pointer to hardware structure
 424  *
 425  * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 426  * EEPROM from shadow RAM to the flash device.
 427  **/
 428 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 429 {
 430         u32 flup;
 431         s32 status = IXGBE_ERR_EEPROM;
 432
 433         status = ixgbe_poll_flash_update_done_X540(hw);
 434         if (status == IXGBE_ERR_EEPROM) {
 435                 hw_dbg(hw, "Flash update time out\n");
 436                 goto out;
 437         }
 438
 439         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 440         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 441
 442         status = ixgbe_poll_flash_update_done_X540(hw);
 443         if (status)
 444                 hw_dbg(hw, "Flash update complete\n");
 445         else
 446                 hw_dbg(hw, "Flash update time out\n");
 447
 448         if (hw->revision_id == 0) {
 449                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 450
 451                 if (flup & IXGBE_EEC_SEC1VAL) {
 452                         flup |= IXGBE_EEC_FLUP;
 453                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 454                 }
 455
 456                 status = ixgbe_poll_flash_update_done_X540(hw);
 457                 if (status)
 458                         hw_dbg(hw, "Flash update complete\n");
 459                 else
 460                         hw_dbg(hw, "Flash update time out\n");
 461
 462         }
 463 out:
 464         return status;
 465 }
 466
 467 /**
 468  * ixgbe_poll_flash_update_done_X540 - Poll flash update status
 469  * @hw: pointer to hardware structure
 470  *
 471  * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 472  * flash update is done.
 473  **/
 474 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 475 {
 476         u32 i;
 477         u32 reg;
 478         s32 status = IXGBE_ERR_EEPROM;
 479
 480         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 481                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 482                 if (reg & IXGBE_EEC_FLUDONE) {
 483                         status = 0;
 484                         break;
 485                 }
 486                 udelay(5);
 487         }
 488         return status;
 489 }
 490
 491 /**
 492  * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 493  * @hw: pointer to hardware structure
 494  * @mask: Mask to specify which semaphore to acquire
 495  *
 496  * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 497  * the specified function (CSR, PHY0, PHY1, NVM, Flash)
 498  **/
 499 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 500 {
 501         u32 swfw_sync;
 502         u32 swmask = mask;
 503         u32 fwmask = mask << 5;
 504         u32 hwmask = 0;
 505         u32 timeout = 200;
 506         u32 i;
 507
 508         if (swmask == IXGBE_GSSR_EEP_SM)
 509                 hwmask = IXGBE_GSSR_FLASH_SM;
 510
 511         for (i = 0; i < timeout; i++) {
 512                 /*
 513                  * SW NVM semaphore bit is used for access to all
 514                  * SW_FW_SYNC bits (not just NVM)
 515                  */
 516                 if (ixgbe_get_swfw_sync_semaphore(hw))
 517                         return IXGBE_ERR_SWFW_SYNC;
 518
 519                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 520                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 521                         swfw_sync |= swmask;
 522                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 523                         ixgbe_release_swfw_sync_semaphore(hw);
 524                         break;
 525                 } else {
 526                         /*
 527                          * Firmware currently using resource (fwmask),
 528                          * hardware currently using resource (hwmask),
 529                          * or other software thread currently using
 530                          * resource (swmask)
 531                          */
 532                         ixgbe_release_swfw_sync_semaphore(hw);
 533                         msleep(5);
 534                 }
 535         }
 536
 537         /*
 538          * If the resource is not released by the FW/HW the SW can assume that
 539          * the FW/HW malfunctions. In that case the SW should sets the
 540          * SW bit(s) of the requested resource(s) while ignoring the
 541          * corresponding FW/HW bits in the SW_FW_SYNC register.
 542          */
 543         if (i >= timeout) {
 544                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 545                 if (swfw_sync & (fwmask | hwmask)) {
 546                         if (ixgbe_get_swfw_sync_semaphore(hw))
 547                                 return IXGBE_ERR_SWFW_SYNC;
 548
 549                         swfw_sync |= swmask;
 550                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 551                         ixgbe_release_swfw_sync_semaphore(hw);
 552                 }
 553         }
 554
 555         msleep(5);
 556         return 0;
 557 }
 558
 559 /**
 560  * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 561  * @hw: pointer to hardware structure
 562  * @mask: Mask to specify which semaphore to release
 563  *
 564  * Releases the SWFW semaphore throught the SW_FW_SYNC register
 565  * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 566  **/
 567 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 568 {
 569         u32 swfw_sync;
 570         u32 swmask = mask;
 571
 572         ixgbe_get_swfw_sync_semaphore(hw);
 573
 574         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 575         swfw_sync &= ~swmask;
 576         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 577
 578         ixgbe_release_swfw_sync_semaphore(hw);
 579         msleep(5);
 580 }
 581
 582 /**
 583  * ixgbe_get_nvm_semaphore - Get hardware semaphore
 584  * @hw: pointer to hardware structure
 585  *
 586  * Sets the hardware semaphores so SW/FW can gain control of shared resources
 587  **/
 588 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 589 {
 590         s32 status = IXGBE_ERR_EEPROM;
 591         u32 timeout = 2000;
 592         u32 i;
 593         u32 swsm;
 594
 595         /* Get SMBI software semaphore between device drivers first */
 596         for (i = 0; i < timeout; i++) {
 597                 /*
 598                  * If the SMBI bit is 0 when we read it, then the bit will be
 599                  * set and we have the semaphore
 600                  */
 601                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 602                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 603                         status = 0;
 604                         break;
 605                 }
 606                 udelay(50);
 607         }
 608
 609         /* Now get the semaphore between SW/FW through the REGSMP bit */
 610         if (status) {
 611                 for (i = 0; i < timeout; i++) {
 612                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 613                         if (!(swsm & IXGBE_SWFW_REGSMP))
 614                                 break;
 615
 616                         udelay(50);
 617                 }
 618         } else {
 619                 hw_dbg(hw, "Software semaphore SMBI between device drivers "
 620                            "not granted.\n");
 621         }
 622
 623         return status;
 624 }
 625
 626 /**
 627  * ixgbe_release_nvm_semaphore - Release hardware semaphore
 628  * @hw: pointer to hardware structure
 629  *
 630  * This function clears hardware semaphore bits.
 631  **/
 632 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 633 {
 634          u32 swsm;
 635
 636         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 637
 638         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 639         swsm &= ~IXGBE_SWSM_SMBI;
 640         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 641
 642         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 643         swsm &= ~IXGBE_SWFW_REGSMP;
 644         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 645
 646         IXGBE_WRITE_FLUSH(hw);
 647 }
 648
 649 static struct ixgbe_mac_operations mac_ops_X540 = {
 650         .init_hw                = &ixgbe_init_hw_generic,
 651         .reset_hw               = &ixgbe_reset_hw_X540,
 652         .start_hw               = &ixgbe_start_hw_generic,
 653         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
 654         .get_media_type         = &ixgbe_get_media_type_X540,
 655         .get_supported_physical_layer =
 656                                   &ixgbe_get_supported_physical_layer_X540,
 657         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
 658         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
 659         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
 660         .get_device_caps        = NULL,
 661         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
 662         .stop_adapter           = &ixgbe_stop_adapter_generic,
 663         .get_bus_info           = &ixgbe_get_bus_info_generic,
 664         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
 665         .read_analog_reg8       = NULL,
 666         .write_analog_reg8      = NULL,
 667         .setup_link             = &ixgbe_setup_mac_link_X540,
 668         .check_link             = &ixgbe_check_mac_link_generic,
 669         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
 670         .led_on                 = &ixgbe_led_on_generic,
 671         .led_off                = &ixgbe_led_off_generic,
 672         .blink_led_start        = &ixgbe_blink_led_start_generic,
 673         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
 674         .set_rar                = &ixgbe_set_rar_generic,
 675         .clear_rar              = &ixgbe_clear_rar_generic,
 676         .set_vmdq               = &ixgbe_set_vmdq_generic,
 677         .clear_vmdq             = &ixgbe_clear_vmdq_generic,
 678         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
 679         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
 680         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
 681         .enable_mc              = &ixgbe_enable_mc_generic,
 682         .disable_mc             = &ixgbe_disable_mc_generic,
 683         .clear_vfta             = &ixgbe_clear_vfta_generic,
 684         .set_vfta               = &ixgbe_set_vfta_generic,
 685         .fc_enable              = &ixgbe_fc_enable_generic,
 686         .init_uta_tables        = &ixgbe_init_uta_tables_generic,
 687         .setup_sfp              = NULL,
 688         .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
 689         .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 690 };
 691
 692 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
 693         .init_params            = &ixgbe_init_eeprom_params_X540,
 694         .read                   = &ixgbe_read_eerd_X540,
 695         .write                  = &ixgbe_write_eewr_X540,
 696         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X540,
 697         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
 698         .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
 699 };
 700
 701 static struct ixgbe_phy_operations phy_ops_X540 = {
 702         .identify               = &ixgbe_identify_phy_generic,
 703         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
 704         .init                   = NULL,
 705         .reset                  = &ixgbe_reset_phy_generic,
 706         .read_reg               = &ixgbe_read_phy_reg_generic,
 707         .write_reg              = &ixgbe_write_phy_reg_generic,
 708         .setup_link             = &ixgbe_setup_phy_link_generic,
 709         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
 710         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
 711         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
 712         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
 713         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
 714         .check_overtemp         = &ixgbe_tn_check_overtemp,
 715 };
 716
 717 struct ixgbe_info ixgbe_X540_info = {
 718         .mac                    = ixgbe_mac_X540,
 719         .get_invariants         = &ixgbe_get_invariants_X540,
 720         .mac_ops                = &mac_ops_X540,
 721         .eeprom_ops             = &eeprom_ops_X540,
 722         .phy_ops                = &phy_ops_X540,
 723         .mbx_ops                = &mbx_ops_generic,
 724 };