drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 108          board_82599 },
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 126 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 127 MODULE_LICENSE("GPL");
 128 MODULE_VERSION(DRV_VERSION);
 129
 130 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 131
 132 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware take over control of h/w */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 143 {
 144         u32 ctrl_ext;
 145
 146         /* Let firmware know the driver has taken over */
 147         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 148         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 149                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 150 }
 151
 152 /*
 153  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 154  * @adapter: pointer to adapter struct
 155  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 156  * @queue: queue to map the corresponding interrupt to
 157  * @msix_vector: the vector to map to the corresponding queue
 158  *
 159  */
 160 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 161                            u8 queue, u8 msix_vector)
 162 {
 163         u32 ivar, index;
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         switch (hw->mac.type) {
 166         case ixgbe_mac_82598EB:
 167                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                 if (direction == -1)
 169                         direction = 0;
 170                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 171                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 172                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 173                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 174                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 175                 break;
 176         case ixgbe_mac_82599EB:
 177                 if (direction == -1) {
 178                         /* other causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((queue & 1) * 8);
 181                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 185                         break;
 186                 } else {
 187                         /* tx or rx causes */
 188                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 189                         index = ((16 * (queue & 1)) + (8 * direction));
 190                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 191                         ivar &= ~(0xFF << index);
 192                         ivar |= (msix_vector << index);
 193                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 194                         break;
 195                 }
 196         default:
 197                 break;
 198         }
 199 }
 200
 201 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 202                                           u64 qmask)
 203 {
 204         u32 mask;
 205
 206         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 207                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 209         } else {
 210                 mask = (qmask & 0xFFFFFFFF);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 212                 mask = (qmask >> 32);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 214         }
 215 }
 216
 217 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 218                                              struct ixgbe_tx_buffer
 219                                              *tx_buffer_info)
 220 {
 221         tx_buffer_info->dma = 0;
 222         if (tx_buffer_info->skb) {
 223                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 224                               DMA_TO_DEVICE);
 225                 dev_kfree_skb_any(tx_buffer_info->skb);
 226                 tx_buffer_info->skb = NULL;
 227         }
 228         tx_buffer_info->time_stamp = 0;
 229         /* tx_buffer_info must be completely set up in the transmit path */
 230 }
 231
 232 /**
 233  * ixgbe_tx_is_paused - check if the tx ring is paused
 234  * @adapter: the ixgbe adapter
 235  * @tx_ring: the corresponding tx_ring
 236  *
 237  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 238  * corresponding TC of this tx_ring when checking TFCS.
 239  *
 240  * Returns : true if paused
 241  */
 242 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 243                                       struct ixgbe_ring *tx_ring)
 244 {
 245         int tc;
 246         u32 txoff = IXGBE_TFCS_TXOFF;
 247
 248 #ifdef CONFIG_IXGBE_DCB
 249         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 250                 int reg_idx = tx_ring->reg_idx;
 251                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 252
 253                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 254                         tc = reg_idx >> 2;
 255                         txoff = IXGBE_TFCS_TXOFF0;
 256                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 257                         tc = 0;
 258                         txoff = IXGBE_TFCS_TXOFF;
 259                         if (dcb_i == 8) {
 260                                 /* TC0, TC1 */
 261                                 tc = reg_idx >> 5;
 262                                 if (tc == 2) /* TC2, TC3 */
 263                                         tc += (reg_idx - 64) >> 4;
 264                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 265                                         tc += 1 + ((reg_idx - 96) >> 3);
 266                         } else if (dcb_i == 4) {
 267                                 /* TC0, TC1 */
 268                                 tc = reg_idx >> 6;
 269                                 if (tc == 1) {
 270                                         tc += (reg_idx - 64) >> 5;
 271                                         if (tc == 2) /* TC2, TC3 */
 272                                                 tc += (reg_idx - 96) >> 4;
 273                                 }
 274                         }
 275                 }
 276                 txoff <<= tc;
 277         }
 278 #endif
 279         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 280 }
 281
 282 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 283                                        struct ixgbe_ring *tx_ring,
 284                                        unsigned int eop)
 285 {
 286         struct ixgbe_hw *hw = &adapter->hw;
 287
 288         /* Detect a transmit hang in hardware, this serializes the
 289          * check with the clearing of time_stamp and movement of eop */
 290         adapter->detect_tx_hung = false;
 291         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 292             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 293             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 294                 /* detected Tx unit hang */
 295                 union ixgbe_adv_tx_desc *tx_desc;
 296                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 297                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 298                         "  Tx Queue             <%d>\n"
 299                         "  TDH, TDT             <%x>, <%x>\n"
 300                         "  next_to_use          <%x>\n"
 301                         "  next_to_clean        <%x>\n"
 302                         "tx_buffer_info[next_to_clean]\n"
 303                         "  time_stamp           <%lx>\n"
 304                         "  jiffies              <%lx>\n",
 305                         tx_ring->queue_index,
 306                         IXGBE_READ_REG(hw, tx_ring->head),
 307                         IXGBE_READ_REG(hw, tx_ring->tail),
 308                         tx_ring->next_to_use, eop,
 309                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 310                 return true;
 311         }
 312
 313         return false;
 314 }
 315
 316 #define IXGBE_MAX_TXD_PWR       14
 317 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 318
 319 /* Tx Descriptors needed, worst case */
 320 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 321                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 322 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 323         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 324
 325 static void ixgbe_tx_timeout(struct net_device *netdev);
 326
 327 /**
 328  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 329  * @q_vector: structure containing interrupt and ring information
 330  * @tx_ring: tx ring to clean
 331  **/
 332 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 333                                struct ixgbe_ring *tx_ring)
 334 {
 335         struct ixgbe_adapter *adapter = q_vector->adapter;
 336         struct net_device *netdev = adapter->netdev;
 337         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 338         struct ixgbe_tx_buffer *tx_buffer_info;
 339         unsigned int i, eop, count = 0;
 340         unsigned int total_bytes = 0, total_packets = 0;
 341
 342         i = tx_ring->next_to_clean;
 343         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 344         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 345
 346         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 347                (count < tx_ring->work_limit)) {
 348                 bool cleaned = false;
 349                 for ( ; !cleaned; count++) {
 350                         struct sk_buff *skb;
 351                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 352                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 353                         cleaned = (i == eop);
 354                         skb = tx_buffer_info->skb;
 355
 356                         if (cleaned && skb) {
 357                                 unsigned int segs, bytecount;
 358                                 unsigned int hlen = skb_headlen(skb);
 359
 360                                 /* gso_segs is currently only valid for tcp */
 361                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 362 #ifdef IXGBE_FCOE
 363                                 /* adjust for FCoE Sequence Offload */
 364                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 365                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 366                                     skb_is_gso(skb)) {
 367                                         hlen = skb_transport_offset(skb) +
 368                                                 sizeof(struct fc_frame_header) +
 369                                                 sizeof(struct fcoe_crc_eof);
 370                                         segs = DIV_ROUND_UP(skb->len - hlen,
 371                                                 skb_shinfo(skb)->gso_size);
 372                                 }
 373 #endif /* IXGBE_FCOE */
 374                                 /* multiply data chunks by size of headers */
 375                                 bytecount = ((segs - 1) * hlen) + skb->len;
 376                                 total_packets += segs;
 377                                 total_bytes += bytecount;
 378                         }
 379
 380                         ixgbe_unmap_and_free_tx_resource(adapter,
 381                                                          tx_buffer_info);
 382
 383                         tx_desc->wb.status = 0;
 384
 385                         i++;
 386                         if (i == tx_ring->count)
 387                                 i = 0;
 388                 }
 389
 390                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 391                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 392         }
 393
 394         tx_ring->next_to_clean = i;
 395
 396 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 397         if (unlikely(count && netif_carrier_ok(netdev) &&
 398                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 399                 /* Make sure that anybody stopping the queue after this
 400                  * sees the new next_to_clean.
 401                  */
 402                 smp_mb();
 403                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 404                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 405                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 406                         ++adapter->restart_queue;
 407                 }
 408         }
 409
 410         if (adapter->detect_tx_hung) {
 411                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 412                         /* schedule immediate reset if we believe we hung */
 413                         DPRINTK(PROBE, INFO,
 414                                 "tx hang %d detected, resetting adapter\n",
 415                                 adapter->tx_timeout_count + 1);
 416                         ixgbe_tx_timeout(adapter->netdev);
 417                 }
 418         }
 419
 420         /* re-arm the interrupt */
 421         if (count >= tx_ring->work_limit)
 422                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 423
 424         tx_ring->total_bytes += total_bytes;
 425         tx_ring->total_packets += total_packets;
 426         tx_ring->stats.packets += total_packets;
 427         tx_ring->stats.bytes += total_bytes;
 428         netdev->stats.tx_bytes += total_bytes;
 429         netdev->stats.tx_packets += total_packets;
 430         return (count < tx_ring->work_limit);
 431 }
 432
 433 #ifdef CONFIG_IXGBE_DCA
 434 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 435                                 struct ixgbe_ring *rx_ring)
 436 {
 437         u32 rxctrl;
 438         int cpu = get_cpu();
 439         int q = rx_ring - adapter->rx_ring;
 440
 441         if (rx_ring->cpu != cpu) {
 442                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 443                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 444                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 445                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 446                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 447                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 448                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 449                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 450                 }
 451                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 452                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 453                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 454                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 455                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 456                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 457                 rx_ring->cpu = cpu;
 458         }
 459         put_cpu();
 460 }
 461
 462 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 463                                 struct ixgbe_ring *tx_ring)
 464 {
 465         u32 txctrl;
 466         int cpu = get_cpu();
 467         int q = tx_ring - adapter->tx_ring;
 468         struct ixgbe_hw *hw = &adapter->hw;
 469
 470         if (tx_ring->cpu != cpu) {
 471                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 472                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 473                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 474                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 475                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 476                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 477                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 478                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 479                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 480                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 481                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 482                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 483                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 484                 }
 485                 tx_ring->cpu = cpu;
 486         }
 487         put_cpu();
 488 }
 489
 490 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 491 {
 492         int i;
 493
 494         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 495                 return;
 496
 497         /* always use CB2 mode, difference is masked in the CB driver */
 498         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 499
 500         for (i = 0; i < adapter->num_tx_queues; i++) {
 501                 adapter->tx_ring[i].cpu = -1;
 502                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 503         }
 504         for (i = 0; i < adapter->num_rx_queues; i++) {
 505                 adapter->rx_ring[i].cpu = -1;
 506                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 507         }
 508 }
 509
 510 static int __ixgbe_notify_dca(struct device *dev, void *data)
 511 {
 512         struct net_device *netdev = dev_get_drvdata(dev);
 513         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 514         unsigned long event = *(unsigned long *)data;
 515
 516         switch (event) {
 517         case DCA_PROVIDER_ADD:
 518                 /* if we're already enabled, don't do it again */
 519                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 520                         break;
 521                 if (dca_add_requester(dev) == 0) {
 522                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 523                         ixgbe_setup_dca(adapter);
 524                         break;
 525                 }
 526                 /* Fall Through since DCA is disabled. */
 527         case DCA_PROVIDER_REMOVE:
 528                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 529                         dca_remove_requester(dev);
 530                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 531                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 532                 }
 533                 break;
 534         }
 535
 536         return 0;
 537 }
 538
 539 #endif /* CONFIG_IXGBE_DCA */
 540 /**
 541  * ixgbe_receive_skb - Send a completed packet up the stack
 542  * @adapter: board private structure
 543  * @skb: packet to send up
 544  * @status: hardware indication of status of receive
 545  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 546  * @rx_desc: rx descriptor
 547  **/
 548 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 549                               struct sk_buff *skb, u8 status,
 550                               struct ixgbe_ring *ring,
 551                               union ixgbe_adv_rx_desc *rx_desc)
 552 {
 553         struct ixgbe_adapter *adapter = q_vector->adapter;
 554         struct napi_struct *napi = &q_vector->napi;
 555         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 556         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 557
 558         skb_record_rx_queue(skb, ring->queue_index);
 559         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 560                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 561                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 562                 else
 563                         napi_gro_receive(napi, skb);
 564         } else {
 565                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 566                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 567                 else
 568                         netif_rx(skb);
 569         }
 570 }
 571
 572 /**
 573  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 574  * @adapter: address of board private structure
 575  * @status_err: hardware indication of status of receive
 576  * @skb: skb currently being received and modified
 577  **/
 578 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 579                                      union ixgbe_adv_rx_desc *rx_desc,
 580                                      struct sk_buff *skb)
 581 {
 582         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 583
 584         skb->ip_summed = CHECKSUM_NONE;
 585
 586         /* Rx csum disabled */
 587         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 588                 return;
 589
 590         /* if IP and error */
 591         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 592             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 593                 adapter->hw_csum_rx_error++;
 594                 return;
 595         }
 596
 597         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 598                 return;
 599
 600         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 601                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 602
 603                 /*
 604                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 605                  * checksum errors.
 606                  */
 607                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 608                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 609                         return;
 610
 611                 adapter->hw_csum_rx_error++;
 612                 return;
 613         }
 614
 615         /* It must be a TCP or UDP packet with a valid checksum */
 616         skb->ip_summed = CHECKSUM_UNNECESSARY;
 617         adapter->hw_csum_rx_good++;
 618 }
 619
 620 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 621                                          struct ixgbe_ring *rx_ring, u32 val)
 622 {
 623         /*
 624          * Force memory writes to complete before letting h/w
 625          * know there are new descriptors to fetch.  (Only
 626          * applicable for weak-ordered memory model archs,
 627          * such as IA-64).
 628          */
 629         wmb();
 630         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 631 }
 632
 633 /**
 634  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 635  * @adapter: address of board private structure
 636  **/
 637 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 638                                    struct ixgbe_ring *rx_ring,
 639                                    int cleaned_count)
 640 {
 641         struct pci_dev *pdev = adapter->pdev;
 642         union ixgbe_adv_rx_desc *rx_desc;
 643         struct ixgbe_rx_buffer *bi;
 644         unsigned int i;
 645
 646         i = rx_ring->next_to_use;
 647         bi = &rx_ring->rx_buffer_info[i];
 648
 649         while (cleaned_count--) {
 650                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 651
 652                 if (!bi->page_dma &&
 653                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 654                         if (!bi->page) {
 655                                 bi->page = alloc_page(GFP_ATOMIC);
 656                                 if (!bi->page) {
 657                                         adapter->alloc_rx_page_failed++;
 658                                         goto no_buffers;
 659                                 }
 660                                 bi->page_offset = 0;
 661                         } else {
 662                                 /* use a half page if we're re-using */
 663                                 bi->page_offset ^= (PAGE_SIZE / 2);
 664                         }
 665
 666                         bi->page_dma = pci_map_page(pdev, bi->page,
 667                                                     bi->page_offset,
 668                                                     (PAGE_SIZE / 2),
 669                                                     PCI_DMA_FROMDEVICE);
 670                 }
 671
 672                 if (!bi->skb) {
 673                         struct sk_buff *skb;
 674                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 675                                                         rx_ring->rx_buf_len);
 676
 677                         if (!skb) {
 678                                 adapter->alloc_rx_buff_failed++;
 679                                 goto no_buffers;
 680                         }
 681
 682                         bi->skb = skb;
 683                         bi->dma = pci_map_single(pdev, skb->data,
 684                                                  rx_ring->rx_buf_len,
 685                                                  PCI_DMA_FROMDEVICE);
 686                 }
 687                 /* Refresh the desc even if buffer_addrs didn't change because
 688                  * each write-back erases this info. */
 689                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 690                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 691                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 692                 } else {
 693                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 694                 }
 695
 696                 i++;
 697                 if (i == rx_ring->count)
 698                         i = 0;
 699                 bi = &rx_ring->rx_buffer_info[i];
 700         }
 701
 702 no_buffers:
 703         if (rx_ring->next_to_use != i) {
 704                 rx_ring->next_to_use = i;
 705                 if (i-- == 0)
 706                         i = (rx_ring->count - 1);
 707
 708                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 709         }
 710 }
 711
 712 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 713 {
 714         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 715 }
 716
 717 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 718 {
 719         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 720 }
 721
 722 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 725                 IXGBE_RXDADV_RSCCNT_MASK) >>
 726                 IXGBE_RXDADV_RSCCNT_SHIFT;
 727 }
 728
 729 /**
 730  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 731  * @skb: pointer to the last skb in the rsc queue
 732  * @count: pointer to number of packets coalesced in this context
 733  *
 734  * This function changes a queue full of hw rsc buffers into a completed
 735  * packet.  It uses the ->prev pointers to find the first packet and then
 736  * turns it into the frag list owner.
 737  **/
 738 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
 739                                                         u64 *count)
 740 {
 741         unsigned int frag_list_size = 0;
 742
 743         while (skb->prev) {
 744                 struct sk_buff *prev = skb->prev;
 745                 frag_list_size += skb->len;
 746                 skb->prev = NULL;
 747                 skb = prev;
 748                 *count += 1;
 749         }
 750
 751         skb_shinfo(skb)->frag_list = skb->next;
 752         skb->next = NULL;
 753         skb->len += frag_list_size;
 754         skb->data_len += frag_list_size;
 755         skb->truesize += frag_list_size;
 756         return skb;
 757 }
 758
 759 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 760                                struct ixgbe_ring *rx_ring,
 761                                int *work_done, int work_to_do)
 762 {
 763         struct ixgbe_adapter *adapter = q_vector->adapter;
 764         struct net_device *netdev = adapter->netdev;
 765         struct pci_dev *pdev = adapter->pdev;
 766         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 767         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 768         struct sk_buff *skb;
 769         unsigned int i, rsc_count = 0;
 770         u32 len, staterr;
 771         u16 hdr_info;
 772         bool cleaned = false;
 773         int cleaned_count = 0;
 774         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 775 #ifdef IXGBE_FCOE
 776         int ddp_bytes = 0;
 777 #endif /* IXGBE_FCOE */
 778
 779         i = rx_ring->next_to_clean;
 780         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 781         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 782         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 783
 784         while (staterr & IXGBE_RXD_STAT_DD) {
 785                 u32 upper_len = 0;
 786                 if (*work_done >= work_to_do)
 787                         break;
 788                 (*work_done)++;
 789
 790                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 791                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 792                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 793                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 794                         if (hdr_info & IXGBE_RXDADV_SPH)
 795                                 adapter->rx_hdr_split++;
 796                         if (len > IXGBE_RX_HDR_SIZE)
 797                                 len = IXGBE_RX_HDR_SIZE;
 798                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 799                 } else {
 800                         len = le16_to_cpu(rx_desc->wb.upper.length);
 801                 }
 802
 803                 cleaned = true;
 804                 skb = rx_buffer_info->skb;
 805                 prefetch(skb->data - NET_IP_ALIGN);
 806                 rx_buffer_info->skb = NULL;
 807
 808                 if (rx_buffer_info->dma) {
 809                         pci_unmap_single(pdev, rx_buffer_info->dma,
 810                                          rx_ring->rx_buf_len,
 811                                          PCI_DMA_FROMDEVICE);
 812                         rx_buffer_info->dma = 0;
 813                         skb_put(skb, len);
 814                 }
 815
 816                 if (upper_len) {
 817                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 818                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 819                         rx_buffer_info->page_dma = 0;
 820                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 821                                            rx_buffer_info->page,
 822                                            rx_buffer_info->page_offset,
 823                                            upper_len);
 824
 825                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 826                             (page_count(rx_buffer_info->page) != 1))
 827                                 rx_buffer_info->page = NULL;
 828                         else
 829                                 get_page(rx_buffer_info->page);
 830
 831                         skb->len += upper_len;
 832                         skb->data_len += upper_len;
 833                         skb->truesize += upper_len;
 834                 }
 835
 836                 i++;
 837                 if (i == rx_ring->count)
 838                         i = 0;
 839
 840                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 841                 prefetch(next_rxd);
 842                 cleaned_count++;
 843
 844                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 845                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 846
 847                 if (rsc_count) {
 848                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 849                                      IXGBE_RXDADV_NEXTP_SHIFT;
 850                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 851                 } else {
 852                         next_buffer = &rx_ring->rx_buffer_info[i];
 853                 }
 854
 855                 if (staterr & IXGBE_RXD_STAT_EOP) {
 856                         if (skb->prev)
 857                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
 858                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
 859                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
 860                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
 861                                 else
 862                                         rx_ring->rsc_count++;
 863                                 rx_ring->rsc_flush++;
 864                         }
 865                         rx_ring->stats.packets++;
 866                         rx_ring->stats.bytes += skb->len;
 867                 } else {
 868                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 869                                 rx_buffer_info->skb = next_buffer->skb;
 870                                 rx_buffer_info->dma = next_buffer->dma;
 871                                 next_buffer->skb = skb;
 872                                 next_buffer->dma = 0;
 873                         } else {
 874                                 skb->next = next_buffer->skb;
 875                                 skb->next->prev = skb;
 876                         }
 877                         adapter->non_eop_descs++;
 878                         goto next_desc;
 879                 }
 880
 881                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 882                         dev_kfree_skb_irq(skb);
 883                         goto next_desc;
 884                 }
 885
 886                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 887
 888                 /* probably a little skewed due to removing CRC */
 889                 total_rx_bytes += skb->len;
 890                 total_rx_packets++;
 891
 892                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 893 #ifdef IXGBE_FCOE
 894                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 895                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 896                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 897                         if (!ddp_bytes)
 898                                 goto next_desc;
 899                 }
 900 #endif /* IXGBE_FCOE */
 901                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 902
 903 next_desc:
 904                 rx_desc->wb.upper.status_error = 0;
 905
 906                 /* return some buffers to hardware, one at a time is too slow */
 907                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 908                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 909                         cleaned_count = 0;
 910                 }
 911
 912                 /* use prefetched values */
 913                 rx_desc = next_rxd;
 914                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 915
 916                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 917         }
 918
 919         rx_ring->next_to_clean = i;
 920         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 921
 922         if (cleaned_count)
 923                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 924
 925 #ifdef IXGBE_FCOE
 926         /* include DDPed FCoE data */
 927         if (ddp_bytes > 0) {
 928                 unsigned int mss;
 929
 930                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 931                         sizeof(struct fc_frame_header) -
 932                         sizeof(struct fcoe_crc_eof);
 933                 if (mss > 512)
 934                         mss &= ~511;
 935                 total_rx_bytes += ddp_bytes;
 936                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 937         }
 938 #endif /* IXGBE_FCOE */
 939
 940         rx_ring->total_packets += total_rx_packets;
 941         rx_ring->total_bytes += total_rx_bytes;
 942         netdev->stats.rx_bytes += total_rx_bytes;
 943         netdev->stats.rx_packets += total_rx_packets;
 944
 945         return cleaned;
 946 }
 947
 948 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 949 /**
 950  * ixgbe_configure_msix - Configure MSI-X hardware
 951  * @adapter: board private structure
 952  *
 953  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 954  * interrupts.
 955  **/
 956 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 957 {
 958         struct ixgbe_q_vector *q_vector;
 959         int i, j, q_vectors, v_idx, r_idx;
 960         u32 mask;
 961
 962         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 963
 964         /*
 965          * Populate the IVAR table and set the ITR values to the
 966          * corresponding register.
 967          */
 968         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 969                 q_vector = adapter->q_vector[v_idx];
 970                 /* XXX for_each_bit(...) */
 971                 r_idx = find_first_bit(q_vector->rxr_idx,
 972                                        adapter->num_rx_queues);
 973
 974                 for (i = 0; i < q_vector->rxr_count; i++) {
 975                         j = adapter->rx_ring[r_idx].reg_idx;
 976                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 977                         r_idx = find_next_bit(q_vector->rxr_idx,
 978                                               adapter->num_rx_queues,
 979                                               r_idx + 1);
 980                 }
 981                 r_idx = find_first_bit(q_vector->txr_idx,
 982                                        adapter->num_tx_queues);
 983
 984                 for (i = 0; i < q_vector->txr_count; i++) {
 985                         j = adapter->tx_ring[r_idx].reg_idx;
 986                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 987                         r_idx = find_next_bit(q_vector->txr_idx,
 988                                               adapter->num_tx_queues,
 989                                               r_idx + 1);
 990                 }
 991
 992                 if (q_vector->txr_count && !q_vector->rxr_count)
 993                         /* tx only */
 994                         q_vector->eitr = adapter->tx_eitr_param;
 995                 else if (q_vector->rxr_count)
 996                         /* rx or mixed */
 997                         q_vector->eitr = adapter->rx_eitr_param;
 998
 999                 ixgbe_write_eitr(q_vector);
1000         }
1001
1002         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1003                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1004                                v_idx);
1005         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1006                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1007         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1008
1009         /* set up to autoclear timer, and the vectors */
1010         mask = IXGBE_EIMS_ENABLE_MASK;
1011         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1012         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1013 }
1014
1015 enum latency_range {
1016         lowest_latency = 0,
1017         low_latency = 1,
1018         bulk_latency = 2,
1019         latency_invalid = 255
1020 };
1021
1022 /**
1023  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1024  * @adapter: pointer to adapter
1025  * @eitr: eitr setting (ints per sec) to give last timeslice
1026  * @itr_setting: current throttle rate in ints/second
1027  * @packets: the number of packets during this measurement interval
1028  * @bytes: the number of bytes during this measurement interval
1029  *
1030  *      Stores a new ITR value based on packets and byte
1031  *      counts during the last interrupt.  The advantage of per interrupt
1032  *      computation is faster updates and more accurate ITR for the current
1033  *      traffic pattern.  Constants in this function were computed
1034  *      based on theoretical maximum wire speed and thresholds were set based
1035  *      on testing data as well as attempting to minimize response time
1036  *      while increasing bulk throughput.
1037  *      this functionality is controlled by the InterruptThrottleRate module
1038  *      parameter (see ixgbe_param.c)
1039  **/
1040 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1041                            u32 eitr, u8 itr_setting,
1042                            int packets, int bytes)
1043 {
1044         unsigned int retval = itr_setting;
1045         u32 timepassed_us;
1046         u64 bytes_perint;
1047
1048         if (packets == 0)
1049                 goto update_itr_done;
1050
1051
1052         /* simple throttlerate management
1053          *    0-20MB/s lowest (100000 ints/s)
1054          *   20-100MB/s low   (20000 ints/s)
1055          *  100-1249MB/s bulk (8000 ints/s)
1056          */
1057         /* what was last interrupt timeslice? */
1058         timepassed_us = 1000000/eitr;
1059         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1060
1061         switch (itr_setting) {
1062         case lowest_latency:
1063                 if (bytes_perint > adapter->eitr_low)
1064                         retval = low_latency;
1065                 break;
1066         case low_latency:
1067                 if (bytes_perint > adapter->eitr_high)
1068                         retval = bulk_latency;
1069                 else if (bytes_perint <= adapter->eitr_low)
1070                         retval = lowest_latency;
1071                 break;
1072         case bulk_latency:
1073                 if (bytes_perint <= adapter->eitr_high)
1074                         retval = low_latency;
1075                 break;
1076         }
1077
1078 update_itr_done:
1079         return retval;
1080 }
1081
1082 /**
1083  * ixgbe_write_eitr - write EITR register in hardware specific way
1084  * @q_vector: structure containing interrupt and ring information
1085  *
1086  * This function is made to be called by ethtool and by the driver
1087  * when it needs to update EITR registers at runtime.  Hardware
1088  * specific quirks/differences are taken care of here.
1089  */
1090 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1091 {
1092         struct ixgbe_adapter *adapter = q_vector->adapter;
1093         struct ixgbe_hw *hw = &adapter->hw;
1094         int v_idx = q_vector->v_idx;
1095         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1096
1097         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1098                 /* must write high and low 16 bits to reset counter */
1099                 itr_reg |= (itr_reg << 16);
1100         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1101                 /*
1102                  * set the WDIS bit to not clear the timer bits and cause an
1103                  * immediate assertion of the interrupt
1104                  */
1105                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1106         }
1107         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1108 }
1109
1110 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1111 {
1112         struct ixgbe_adapter *adapter = q_vector->adapter;
1113         u32 new_itr;
1114         u8 current_itr, ret_itr;
1115         int i, r_idx;
1116         struct ixgbe_ring *rx_ring, *tx_ring;
1117
1118         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1119         for (i = 0; i < q_vector->txr_count; i++) {
1120                 tx_ring = &(adapter->tx_ring[r_idx]);
1121                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1122                                            q_vector->tx_itr,
1123                                            tx_ring->total_packets,
1124                                            tx_ring->total_bytes);
1125                 /* if the result for this queue would decrease interrupt
1126                  * rate for this vector then use that result */
1127                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1128                                     q_vector->tx_itr - 1 : ret_itr);
1129                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1130                                       r_idx + 1);
1131         }
1132
1133         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1134         for (i = 0; i < q_vector->rxr_count; i++) {
1135                 rx_ring = &(adapter->rx_ring[r_idx]);
1136                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1137                                            q_vector->rx_itr,
1138                                            rx_ring->total_packets,
1139                                            rx_ring->total_bytes);
1140                 /* if the result for this queue would decrease interrupt
1141                  * rate for this vector then use that result */
1142                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1143                                     q_vector->rx_itr - 1 : ret_itr);
1144                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1145                                       r_idx + 1);
1146         }
1147
1148         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1149
1150         switch (current_itr) {
1151         /* counts and packets in update_itr are dependent on these numbers */
1152         case lowest_latency:
1153                 new_itr = 100000;
1154                 break;
1155         case low_latency:
1156                 new_itr = 20000; /* aka hwitr = ~200 */
1157                 break;
1158         case bulk_latency:
1159         default:
1160                 new_itr = 8000;
1161                 break;
1162         }
1163
1164         if (new_itr != q_vector->eitr) {
1165                 /* do an exponential smoothing */
1166                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1167
1168                 /* save the algorithm value here, not the smoothed one */
1169                 q_vector->eitr = new_itr;
1170
1171                 ixgbe_write_eitr(q_vector);
1172         }
1173
1174         return;
1175 }
1176
1177 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1178 {
1179         struct ixgbe_hw *hw = &adapter->hw;
1180
1181         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1182             (eicr & IXGBE_EICR_GPI_SDP1)) {
1183                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1184                 /* write to clear the interrupt */
1185                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1186         }
1187 }
1188
1189 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1190 {
1191         struct ixgbe_hw *hw = &adapter->hw;
1192
1193         if (eicr & IXGBE_EICR_GPI_SDP1) {
1194                 /* Clear the interrupt */
1195                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1196                 schedule_work(&adapter->multispeed_fiber_task);
1197         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1198                 /* Clear the interrupt */
1199                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1200                 schedule_work(&adapter->sfp_config_module_task);
1201         } else {
1202                 /* Interrupt isn't for us... */
1203                 return;
1204         }
1205 }
1206
1207 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1208 {
1209         struct ixgbe_hw *hw = &adapter->hw;
1210
1211         adapter->lsc_int++;
1212         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1213         adapter->link_check_timeout = jiffies;
1214         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1215                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1216                 IXGBE_WRITE_FLUSH(hw);
1217                 schedule_work(&adapter->watchdog_task);
1218         }
1219 }
1220
1221 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1222 {
1223         struct net_device *netdev = data;
1224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1225         struct ixgbe_hw *hw = &adapter->hw;
1226         u32 eicr;
1227
1228         /*
1229          * Workaround for Silicon errata.  Use clear-by-write instead
1230          * of clear-by-read.  Reading with EICS will return the
1231          * interrupt causes without clearing, which later be done
1232          * with the write to EICR.
1233          */
1234         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1235         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1236
1237         if (eicr & IXGBE_EICR_LSC)
1238                 ixgbe_check_lsc(adapter);
1239
1240         if (hw->mac.type == ixgbe_mac_82598EB)
1241                 ixgbe_check_fan_failure(adapter, eicr);
1242
1243         if (hw->mac.type == ixgbe_mac_82599EB) {
1244                 ixgbe_check_sfp_event(adapter, eicr);
1245
1246                 /* Handle Flow Director Full threshold interrupt */
1247                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1248                         int i;
1249                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1250                         /* Disable transmits before FDIR Re-initialization */
1251                         netif_tx_stop_all_queues(netdev);
1252                         for (i = 0; i < adapter->num_tx_queues; i++) {
1253                                 struct ixgbe_ring *tx_ring =
1254                                                            &adapter->tx_ring[i];
1255                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1256                                                        &tx_ring->reinit_state))
1257                                         schedule_work(&adapter->fdir_reinit_task);
1258                         }
1259                 }
1260         }
1261         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1262                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1268                                            u64 qmask)
1269 {
1270         u32 mask;
1271
1272         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1273                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1274                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1275         } else {
1276                 mask = (qmask & 0xFFFFFFFF);
1277                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1278                 mask = (qmask >> 32);
1279                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1280         }
1281         /* skip the flush */
1282 }
1283
1284 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1285                                             u64 qmask)
1286 {
1287         u32 mask;
1288
1289         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1290                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1292         } else {
1293                 mask = (qmask & 0xFFFFFFFF);
1294                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1295                 mask = (qmask >> 32);
1296                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1297         }
1298         /* skip the flush */
1299 }
1300
1301 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1302 {
1303         struct ixgbe_q_vector *q_vector = data;
1304         struct ixgbe_adapter  *adapter = q_vector->adapter;
1305         struct ixgbe_ring     *tx_ring;
1306         int i, r_idx;
1307
1308         if (!q_vector->txr_count)
1309                 return IRQ_HANDLED;
1310
1311         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1312         for (i = 0; i < q_vector->txr_count; i++) {
1313                 tx_ring = &(adapter->tx_ring[r_idx]);
1314                 tx_ring->total_bytes = 0;
1315                 tx_ring->total_packets = 0;
1316                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1317                                       r_idx + 1);
1318         }
1319
1320         /* disable interrupts on this vector only */
1321         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1322         napi_schedule(&q_vector->napi);
1323
1324         return IRQ_HANDLED;
1325 }
1326
1327 /**
1328  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1329  * @irq: unused
1330  * @data: pointer to our q_vector struct for this interrupt vector
1331  **/
1332 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1333 {
1334         struct ixgbe_q_vector *q_vector = data;
1335         struct ixgbe_adapter  *adapter = q_vector->adapter;
1336         struct ixgbe_ring  *rx_ring;
1337         int r_idx;
1338         int i;
1339
1340         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1341         for (i = 0;  i < q_vector->rxr_count; i++) {
1342                 rx_ring = &(adapter->rx_ring[r_idx]);
1343                 rx_ring->total_bytes = 0;
1344                 rx_ring->total_packets = 0;
1345                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1346                                       r_idx + 1);
1347         }
1348
1349         if (!q_vector->rxr_count)
1350                 return IRQ_HANDLED;
1351
1352         /* disable interrupts on this vector only */
1353         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1354         napi_schedule(&q_vector->napi);
1355
1356         return IRQ_HANDLED;
1357 }
1358
1359 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1360 {
1361         struct ixgbe_q_vector *q_vector = data;
1362         struct ixgbe_adapter  *adapter = q_vector->adapter;
1363         struct ixgbe_ring  *ring;
1364         int r_idx;
1365         int i;
1366
1367         if (!q_vector->txr_count && !q_vector->rxr_count)
1368                 return IRQ_HANDLED;
1369
1370         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1371         for (i = 0; i < q_vector->txr_count; i++) {
1372                 ring = &(adapter->tx_ring[r_idx]);
1373                 ring->total_bytes = 0;
1374                 ring->total_packets = 0;
1375                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1376                                       r_idx + 1);
1377         }
1378
1379         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1380         for (i = 0; i < q_vector->rxr_count; i++) {
1381                 ring = &(adapter->rx_ring[r_idx]);
1382                 ring->total_bytes = 0;
1383                 ring->total_packets = 0;
1384                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1385                                       r_idx + 1);
1386         }
1387
1388         /* disable interrupts on this vector only */
1389         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1390         napi_schedule(&q_vector->napi);
1391
1392         return IRQ_HANDLED;
1393 }
1394
1395 /**
1396  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1397  * @napi: napi struct with our devices info in it
1398  * @budget: amount of work driver is allowed to do this pass, in packets
1399  *
1400  * This function is optimized for cleaning one queue only on a single
1401  * q_vector!!!
1402  **/
1403 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1404 {
1405         struct ixgbe_q_vector *q_vector =
1406                                container_of(napi, struct ixgbe_q_vector, napi);
1407         struct ixgbe_adapter *adapter = q_vector->adapter;
1408         struct ixgbe_ring *rx_ring = NULL;
1409         int work_done = 0;
1410         long r_idx;
1411
1412         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1413         rx_ring = &(adapter->rx_ring[r_idx]);
1414 #ifdef CONFIG_IXGBE_DCA
1415         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1416                 ixgbe_update_rx_dca(adapter, rx_ring);
1417 #endif
1418
1419         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1420
1421         /* If all Rx work done, exit the polling mode */
1422         if (work_done < budget) {
1423                 napi_complete(napi);
1424                 if (adapter->rx_itr_setting & 1)
1425                         ixgbe_set_itr_msix(q_vector);
1426                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1427                         ixgbe_irq_enable_queues(adapter,
1428                                                 ((u64)1 << q_vector->v_idx));
1429         }
1430
1431         return work_done;
1432 }
1433
1434 /**
1435  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1436  * @napi: napi struct with our devices info in it
1437  * @budget: amount of work driver is allowed to do this pass, in packets
1438  *
1439  * This function will clean more than one rx queue associated with a
1440  * q_vector.
1441  **/
1442 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1443 {
1444         struct ixgbe_q_vector *q_vector =
1445                                container_of(napi, struct ixgbe_q_vector, napi);
1446         struct ixgbe_adapter *adapter = q_vector->adapter;
1447         struct ixgbe_ring *ring = NULL;
1448         int work_done = 0, i;
1449         long r_idx;
1450         bool tx_clean_complete = true;
1451
1452         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1453         for (i = 0; i < q_vector->txr_count; i++) {
1454                 ring = &(adapter->tx_ring[r_idx]);
1455 #ifdef CONFIG_IXGBE_DCA
1456                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1457                         ixgbe_update_tx_dca(adapter, ring);
1458 #endif
1459                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1460                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1461                                       r_idx + 1);
1462         }
1463
1464         /* attempt to distribute budget to each queue fairly, but don't allow
1465          * the budget to go below 1 because we'll exit polling */
1466         budget /= (q_vector->rxr_count ?: 1);
1467         budget = max(budget, 1);
1468         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1469         for (i = 0; i < q_vector->rxr_count; i++) {
1470                 ring = &(adapter->rx_ring[r_idx]);
1471 #ifdef CONFIG_IXGBE_DCA
1472                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1473                         ixgbe_update_rx_dca(adapter, ring);
1474 #endif
1475                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1476                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1477                                       r_idx + 1);
1478         }
1479
1480         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1481         ring = &(adapter->rx_ring[r_idx]);
1482         /* If all Rx work done, exit the polling mode */
1483         if (work_done < budget) {
1484                 napi_complete(napi);
1485                 if (adapter->rx_itr_setting & 1)
1486                         ixgbe_set_itr_msix(q_vector);
1487                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1488                         ixgbe_irq_enable_queues(adapter,
1489                                                 ((u64)1 << q_vector->v_idx));
1490                 return 0;
1491         }
1492
1493         return work_done;
1494 }
1495
1496 /**
1497  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1498  * @napi: napi struct with our devices info in it
1499  * @budget: amount of work driver is allowed to do this pass, in packets
1500  *
1501  * This function is optimized for cleaning one queue only on a single
1502  * q_vector!!!
1503  **/
1504 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1505 {
1506         struct ixgbe_q_vector *q_vector =
1507                                container_of(napi, struct ixgbe_q_vector, napi);
1508         struct ixgbe_adapter *adapter = q_vector->adapter;
1509         struct ixgbe_ring *tx_ring = NULL;
1510         int work_done = 0;
1511         long r_idx;
1512
1513         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1514         tx_ring = &(adapter->tx_ring[r_idx]);
1515 #ifdef CONFIG_IXGBE_DCA
1516         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1517                 ixgbe_update_tx_dca(adapter, tx_ring);
1518 #endif
1519
1520         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1521                 work_done = budget;
1522
1523         /* If all Tx work done, exit the polling mode */
1524         if (work_done < budget) {
1525                 napi_complete(napi);
1526                 if (adapter->tx_itr_setting & 1)
1527                         ixgbe_set_itr_msix(q_vector);
1528                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1529                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1530         }
1531
1532         return work_done;
1533 }
1534
1535 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1536                                      int r_idx)
1537 {
1538         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1539
1540         set_bit(r_idx, q_vector->rxr_idx);
1541         q_vector->rxr_count++;
1542 }
1543
1544 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1545                                      int t_idx)
1546 {
1547         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1548
1549         set_bit(t_idx, q_vector->txr_idx);
1550         q_vector->txr_count++;
1551 }
1552
1553 /**
1554  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1555  * @adapter: board private structure to initialize
1556  * @vectors: allotted vector count for descriptor rings
1557  *
1558  * This function maps descriptor rings to the queue-specific vectors
1559  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1560  * one vector per ring/queue, but on a constrained vector budget, we
1561  * group the rings as "efficiently" as possible.  You would add new
1562  * mapping configurations in here.
1563  **/
1564 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1565                                       int vectors)
1566 {
1567         int v_start = 0;
1568         int rxr_idx = 0, txr_idx = 0;
1569         int rxr_remaining = adapter->num_rx_queues;
1570         int txr_remaining = adapter->num_tx_queues;
1571         int i, j;
1572         int rqpv, tqpv;
1573         int err = 0;
1574
1575         /* No mapping required if MSI-X is disabled. */
1576         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1577                 goto out;
1578
1579         /*
1580          * The ideal configuration...
1581          * We have enough vectors to map one per queue.
1582          */
1583         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1584                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1585                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1586
1587                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1588                         map_vector_to_txq(adapter, v_start, txr_idx);
1589
1590                 goto out;
1591         }
1592
1593         /*
1594          * If we don't have enough vectors for a 1-to-1
1595          * mapping, we'll have to group them so there are
1596          * multiple queues per vector.
1597          */
1598         /* Re-adjusting *qpv takes care of the remainder. */
1599         for (i = v_start; i < vectors; i++) {
1600                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1601                 for (j = 0; j < rqpv; j++) {
1602                         map_vector_to_rxq(adapter, i, rxr_idx);
1603                         rxr_idx++;
1604                         rxr_remaining--;
1605                 }
1606         }
1607         for (i = v_start; i < vectors; i++) {
1608                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1609                 for (j = 0; j < tqpv; j++) {
1610                         map_vector_to_txq(adapter, i, txr_idx);
1611                         txr_idx++;
1612                         txr_remaining--;
1613                 }
1614         }
1615
1616 out:
1617         return err;
1618 }
1619
1620 /**
1621  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1622  * @adapter: board private structure
1623  *
1624  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1625  * interrupts from the kernel.
1626  **/
1627 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1628 {
1629         struct net_device *netdev = adapter->netdev;
1630         irqreturn_t (*handler)(int, void *);
1631         int i, vector, q_vectors, err;
1632         int ri=0, ti=0;
1633
1634         /* Decrement for Other and TCP Timer vectors */
1635         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1636
1637         /* Map the Tx/Rx rings to the vectors we were allotted. */
1638         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1639         if (err)
1640                 goto out;
1641
1642 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1643                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1644                          &ixgbe_msix_clean_many)
1645         for (vector = 0; vector < q_vectors; vector++) {
1646                 handler = SET_HANDLER(adapter->q_vector[vector]);
1647
1648                 if(handler == &ixgbe_msix_clean_rx) {
1649                         sprintf(adapter->name[vector], "%s-%s-%d",
1650                                 netdev->name, "rx", ri++);
1651                 }
1652                 else if(handler == &ixgbe_msix_clean_tx) {
1653                         sprintf(adapter->name[vector], "%s-%s-%d",
1654                                 netdev->name, "tx", ti++);
1655                 }
1656                 else
1657                         sprintf(adapter->name[vector], "%s-%s-%d",
1658                                 netdev->name, "TxRx", vector);
1659
1660                 err = request_irq(adapter->msix_entries[vector].vector,
1661                                   handler, 0, adapter->name[vector],
1662                                   adapter->q_vector[vector]);
1663                 if (err) {
1664                         DPRINTK(PROBE, ERR,
1665                                 "request_irq failed for MSIX interrupt "
1666                                 "Error: %d\n", err);
1667                         goto free_queue_irqs;
1668                 }
1669         }
1670
1671         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1672         err = request_irq(adapter->msix_entries[vector].vector,
1673                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1674         if (err) {
1675                 DPRINTK(PROBE, ERR,
1676                         "request_irq for msix_lsc failed: %d\n", err);
1677                 goto free_queue_irqs;
1678         }
1679
1680         return 0;
1681
1682 free_queue_irqs:
1683         for (i = vector - 1; i >= 0; i--)
1684                 free_irq(adapter->msix_entries[--vector].vector,
1685                          adapter->q_vector[i]);
1686         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1687         pci_disable_msix(adapter->pdev);
1688         kfree(adapter->msix_entries);
1689         adapter->msix_entries = NULL;
1690 out:
1691         return err;
1692 }
1693
1694 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1695 {
1696         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1697         u8 current_itr;
1698         u32 new_itr = q_vector->eitr;
1699         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1700         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1701
1702         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1703                                             q_vector->tx_itr,
1704                                             tx_ring->total_packets,
1705                                             tx_ring->total_bytes);
1706         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1707                                             q_vector->rx_itr,
1708                                             rx_ring->total_packets,
1709                                             rx_ring->total_bytes);
1710
1711         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1712
1713         switch (current_itr) {
1714         /* counts and packets in update_itr are dependent on these numbers */
1715         case lowest_latency:
1716                 new_itr = 100000;
1717                 break;
1718         case low_latency:
1719                 new_itr = 20000; /* aka hwitr = ~200 */
1720                 break;
1721         case bulk_latency:
1722                 new_itr = 8000;
1723                 break;
1724         default:
1725                 break;
1726         }
1727
1728         if (new_itr != q_vector->eitr) {
1729                 /* do an exponential smoothing */
1730                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1731
1732                 /* save the algorithm value here, not the smoothed one */
1733                 q_vector->eitr = new_itr;
1734
1735                 ixgbe_write_eitr(q_vector);
1736         }
1737
1738         return;
1739 }
1740
1741 /**
1742  * ixgbe_irq_enable - Enable default interrupt generation settings
1743  * @adapter: board private structure
1744  **/
1745 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1746 {
1747         u32 mask;
1748
1749         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1750         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1751                 mask |= IXGBE_EIMS_GPI_SDP1;
1752         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1753                 mask |= IXGBE_EIMS_ECC;
1754                 mask |= IXGBE_EIMS_GPI_SDP1;
1755                 mask |= IXGBE_EIMS_GPI_SDP2;
1756         }
1757         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1758             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1759                 mask |= IXGBE_EIMS_FLOW_DIR;
1760
1761         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1762         ixgbe_irq_enable_queues(adapter, ~0);
1763         IXGBE_WRITE_FLUSH(&adapter->hw);
1764 }
1765
1766 /**
1767  * ixgbe_intr - legacy mode Interrupt Handler
1768  * @irq: interrupt number
1769  * @data: pointer to a network interface device structure
1770  **/
1771 static irqreturn_t ixgbe_intr(int irq, void *data)
1772 {
1773         struct net_device *netdev = data;
1774         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1775         struct ixgbe_hw *hw = &adapter->hw;
1776         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1777         u32 eicr;
1778
1779         /*
1780          * Workaround for silicon errata.  Mask the interrupts
1781          * before the read of EICR.
1782          */
1783         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1784
1785         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1786          * therefore no explict interrupt disable is necessary */
1787         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1788         if (!eicr) {
1789                 /* shared interrupt alert!
1790                  * make sure interrupts are enabled because the read will
1791                  * have disabled interrupts due to EIAM */
1792                 ixgbe_irq_enable(adapter);
1793                 return IRQ_NONE;        /* Not our interrupt */
1794         }
1795
1796         if (eicr & IXGBE_EICR_LSC)
1797                 ixgbe_check_lsc(adapter);
1798
1799         if (hw->mac.type == ixgbe_mac_82599EB)
1800                 ixgbe_check_sfp_event(adapter, eicr);
1801
1802         ixgbe_check_fan_failure(adapter, eicr);
1803
1804         if (napi_schedule_prep(&(q_vector->napi))) {
1805                 adapter->tx_ring[0].total_packets = 0;
1806                 adapter->tx_ring[0].total_bytes = 0;
1807                 adapter->rx_ring[0].total_packets = 0;
1808                 adapter->rx_ring[0].total_bytes = 0;
1809                 /* would disable interrupts here but EIAM disabled it */
1810                 __napi_schedule(&(q_vector->napi));
1811         }
1812
1813         return IRQ_HANDLED;
1814 }
1815
1816 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1817 {
1818         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1819
1820         for (i = 0; i < q_vectors; i++) {
1821                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1822                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1823                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1824                 q_vector->rxr_count = 0;
1825                 q_vector->txr_count = 0;
1826         }
1827 }
1828
1829 /**
1830  * ixgbe_request_irq - initialize interrupts
1831  * @adapter: board private structure
1832  *
1833  * Attempts to configure interrupts using the best available
1834  * capabilities of the hardware and kernel.
1835  **/
1836 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1837 {
1838         struct net_device *netdev = adapter->netdev;
1839         int err;
1840
1841         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1842                 err = ixgbe_request_msix_irqs(adapter);
1843         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1844                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1845                                   netdev->name, netdev);
1846         } else {
1847                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1848                                   netdev->name, netdev);
1849         }
1850
1851         if (err)
1852                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1853
1854         return err;
1855 }
1856
1857 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1858 {
1859         struct net_device *netdev = adapter->netdev;
1860
1861         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1862                 int i, q_vectors;
1863
1864                 q_vectors = adapter->num_msix_vectors;
1865
1866                 i = q_vectors - 1;
1867                 free_irq(adapter->msix_entries[i].vector, netdev);
1868
1869                 i--;
1870                 for (; i >= 0; i--) {
1871                         free_irq(adapter->msix_entries[i].vector,
1872                                  adapter->q_vector[i]);
1873                 }
1874
1875                 ixgbe_reset_q_vectors(adapter);
1876         } else {
1877                 free_irq(adapter->pdev->irq, netdev);
1878         }
1879 }
1880
1881 /**
1882  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1883  * @adapter: board private structure
1884  **/
1885 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1886 {
1887         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1888                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1889         } else {
1890                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1891                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1892                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1893         }
1894         IXGBE_WRITE_FLUSH(&adapter->hw);
1895         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1896                 int i;
1897                 for (i = 0; i < adapter->num_msix_vectors; i++)
1898                         synchronize_irq(adapter->msix_entries[i].vector);
1899         } else {
1900                 synchronize_irq(adapter->pdev->irq);
1901         }
1902 }
1903
1904 /**
1905  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1906  *
1907  **/
1908 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1909 {
1910         struct ixgbe_hw *hw = &adapter->hw;
1911
1912         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1913                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1914
1915         ixgbe_set_ivar(adapter, 0, 0, 0);
1916         ixgbe_set_ivar(adapter, 1, 0, 0);
1917
1918         map_vector_to_rxq(adapter, 0, 0);
1919         map_vector_to_txq(adapter, 0, 0);
1920
1921         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1922 }
1923
1924 /**
1925  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1926  * @adapter: board private structure
1927  *
1928  * Configure the Tx unit of the MAC after a reset.
1929  **/
1930 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1931 {
1932         u64 tdba;
1933         struct ixgbe_hw *hw = &adapter->hw;
1934         u32 i, j, tdlen, txctrl;
1935
1936         /* Setup the HW Tx Head and Tail descriptor pointers */
1937         for (i = 0; i < adapter->num_tx_queues; i++) {
1938                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1939                 j = ring->reg_idx;
1940                 tdba = ring->dma;
1941                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1942                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1943                                 (tdba & DMA_BIT_MASK(32)));
1944                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1945                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1946                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1947                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1948                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1949                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1950                 /*
1951                  * Disable Tx Head Writeback RO bit, since this hoses
1952                  * bookkeeping if things aren't delivered in order.
1953                  */
1954                 switch (hw->mac.type) {
1955                 case ixgbe_mac_82598EB:
1956                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1957                         break;
1958                 case ixgbe_mac_82599EB:
1959                 default:
1960                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1961                         break;
1962                 }
1963                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1964                 switch (hw->mac.type) {
1965                 case ixgbe_mac_82598EB:
1966                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1967                         break;
1968                 case ixgbe_mac_82599EB:
1969                 default:
1970                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1971                         break;
1972                 }
1973         }
1974
1975         if (hw->mac.type == ixgbe_mac_82599EB) {
1976                 u32 rttdcs;
1977
1978                 /* disable the arbiter while setting MTQC */
1979                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1980                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1981                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1982
1983                 /* We enable 8 traffic classes, DCB only */
1984                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1985                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1986                                         IXGBE_MTQC_8TC_8TQ));
1987                 else
1988                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1989
1990                 /* re-eable the arbiter */
1991                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1992                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1993         }
1994 }
1995
1996 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1997
1998 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1999                                    struct ixgbe_ring *rx_ring)
2000 {
2001         u32 srrctl;
2002         int index;
2003         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2004
2005         index = rx_ring->reg_idx;
2006         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2007                 unsigned long mask;
2008                 mask = (unsigned long) feature[RING_F_RSS].mask;
2009                 index = index & mask;
2010         }
2011         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2012
2013         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2014         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2015
2016         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2017                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2018
2019         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2020 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2021                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2022 #else
2023                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2024 #endif
2025                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2026         } else {
2027                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2028                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2029                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2030         }
2031
2032         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2033 }
2034
2035 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2036 {
2037         u32 mrqc = 0;
2038         int mask;
2039
2040         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2041                 return mrqc;
2042
2043         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2044 #ifdef CONFIG_IXGBE_DCB
2045                                  | IXGBE_FLAG_DCB_ENABLED
2046 #endif
2047                                 );
2048
2049         switch (mask) {
2050         case (IXGBE_FLAG_RSS_ENABLED):
2051                 mrqc = IXGBE_MRQC_RSSEN;
2052                 break;
2053 #ifdef CONFIG_IXGBE_DCB
2054         case (IXGBE_FLAG_DCB_ENABLED):
2055                 mrqc = IXGBE_MRQC_RT8TCEN;
2056                 break;
2057 #endif /* CONFIG_IXGBE_DCB */
2058         default:
2059                 break;
2060         }
2061
2062         return mrqc;
2063 }
2064
2065 /**
2066  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2067  * @adapter:    address of board private structure
2068  * @index:      index of ring to set
2069  * @rx_buf_len: rx buffer length
2070  **/
2071 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2072                                    int rx_buf_len)
2073 {
2074         struct ixgbe_ring *rx_ring;
2075         struct ixgbe_hw *hw = &adapter->hw;
2076         int j;
2077         u32 rscctrl;
2078
2079         rx_ring = &adapter->rx_ring[index];
2080         j = rx_ring->reg_idx;
2081         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2082         rscctrl |= IXGBE_RSCCTL_RSCEN;
2083         /*
2084          * we must limit the number of descriptors so that the
2085          * total size of max desc * buf_len is not greater
2086          * than 65535
2087          */
2088         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2089 #if (MAX_SKB_FRAGS > 16)
2090                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2091 #elif (MAX_SKB_FRAGS > 8)
2092                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2093 #elif (MAX_SKB_FRAGS > 4)
2094                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2095 #else
2096                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2097 #endif
2098         } else {
2099                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2100                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2101                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2102                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2103                 else
2104                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2105         }
2106         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2107 }
2108
2109 /**
2110  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2111  * @adapter: board private structure
2112  *
2113  * Configure the Rx unit of the MAC after a reset.
2114  **/
2115 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2116 {
2117         u64 rdba;
2118         struct ixgbe_hw *hw = &adapter->hw;
2119         struct ixgbe_ring *rx_ring;
2120         struct net_device *netdev = adapter->netdev;
2121         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2122         int i, j;
2123         u32 rdlen, rxctrl, rxcsum;
2124         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2125                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2126                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2127         u32 fctrl, hlreg0;
2128         u32 reta = 0, mrqc = 0;
2129         u32 rdrxctl;
2130         int rx_buf_len;
2131
2132         /* Decide whether to use packet split mode or not */
2133         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2134
2135         /* Set the RX buffer length according to the mode */
2136         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2137                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2138                 if (hw->mac.type == ixgbe_mac_82599EB) {
2139                         /* PSRTYPE must be initialized in 82599 */
2140                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2141                                       IXGBE_PSRTYPE_UDPHDR |
2142                                       IXGBE_PSRTYPE_IPV4HDR |
2143                                       IXGBE_PSRTYPE_IPV6HDR |
2144                                       IXGBE_PSRTYPE_L2HDR;
2145                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2146                 }
2147         } else {
2148                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2149                     (netdev->mtu <= ETH_DATA_LEN))
2150                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2151                 else
2152                         rx_buf_len = ALIGN(max_frame, 1024);
2153         }
2154
2155         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2156         fctrl |= IXGBE_FCTRL_BAM;
2157         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2158         fctrl |= IXGBE_FCTRL_PMCF;
2159         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2160
2161         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2162         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2163                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2164         else
2165                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2166 #ifdef IXGBE_FCOE
2167         if (netdev->features & NETIF_F_FCOE_MTU)
2168                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2169 #endif
2170         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2171
2172         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2173         /* disable receives while setting up the descriptors */
2174         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2175         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2176
2177         /*
2178          * Setup the HW Rx Head and Tail Descriptor Pointers and
2179          * the Base and Length of the Rx Descriptor Ring
2180          */
2181         for (i = 0; i < adapter->num_rx_queues; i++) {
2182                 rx_ring = &adapter->rx_ring[i];
2183                 rdba = rx_ring->dma;
2184                 j = rx_ring->reg_idx;
2185                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2186                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2187                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2188                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2189                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2190                 rx_ring->head = IXGBE_RDH(j);
2191                 rx_ring->tail = IXGBE_RDT(j);
2192                 rx_ring->rx_buf_len = rx_buf_len;
2193
2194                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2195                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2196                 else
2197                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2198
2199 #ifdef IXGBE_FCOE
2200                 if (netdev->features & NETIF_F_FCOE_MTU) {
2201                         struct ixgbe_ring_feature *f;
2202                         f = &adapter->ring_feature[RING_F_FCOE];
2203                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2204                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2205                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2206                                         rx_ring->rx_buf_len =
2207                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2208                         }
2209                 }
2210
2211 #endif /* IXGBE_FCOE */
2212                 ixgbe_configure_srrctl(adapter, rx_ring);
2213         }
2214
2215         if (hw->mac.type == ixgbe_mac_82598EB) {
2216                 /*
2217                  * For VMDq support of different descriptor types or
2218                  * buffer sizes through the use of multiple SRRCTL
2219                  * registers, RDRXCTL.MVMEN must be set to 1
2220                  *
2221                  * also, the manual doesn't mention it clearly but DCA hints
2222                  * will only use queue 0's tags unless this bit is set.  Side
2223                  * effects of setting this bit are only that SRRCTL must be
2224                  * fully programmed [0..15]
2225                  */
2226                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2227                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2228                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2229         }
2230
2231         /* Program MRQC for the distribution of queues */
2232         mrqc = ixgbe_setup_mrqc(adapter);
2233
2234         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2235                 /* Fill out redirection table */
2236                 for (i = 0, j = 0; i < 128; i++, j++) {
2237                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2238                                 j = 0;
2239                         /* reta = 4-byte sliding window of
2240                          * 0x00..(indices-1)(indices-1)00..etc. */
2241                         reta = (reta << 8) | (j * 0x11);
2242                         if ((i & 3) == 3)
2243                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2244                 }
2245
2246                 /* Fill out hash function seeds */
2247                 for (i = 0; i < 10; i++)
2248                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2249
2250                 if (hw->mac.type == ixgbe_mac_82598EB)
2251                         mrqc |= IXGBE_MRQC_RSSEN;
2252                     /* Perform hash on these packet types */
2253                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2254                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2255                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2256                       | IXGBE_MRQC_RSS_FIELD_IPV6
2257                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2258                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2259         }
2260         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2261
2262         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2263
2264         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2265             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2266                 /* Disable indicating checksum in descriptor, enables
2267                  * RSS hash */
2268                 rxcsum |= IXGBE_RXCSUM_PCSD;
2269         }
2270         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2271                 /* Enable IPv4 payload checksum for UDP fragments
2272                  * if PCSD is not set */
2273                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2274         }
2275
2276         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2277
2278         if (hw->mac.type == ixgbe_mac_82599EB) {
2279                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2280                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2281                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2282                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2283         }
2284
2285         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2286                 /* Enable 82599 HW-RSC */
2287                 for (i = 0; i < adapter->num_rx_queues; i++)
2288                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2289
2290                 /* Disable RSC for ACK packets */
2291                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2292                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2293         }
2294 }
2295
2296 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2297 {
2298         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2299         struct ixgbe_hw *hw = &adapter->hw;
2300
2301         /* add VID to filter table */
2302         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2303 }
2304
2305 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2306 {
2307         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2308         struct ixgbe_hw *hw = &adapter->hw;
2309
2310         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2311                 ixgbe_irq_disable(adapter);
2312
2313         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2314
2315         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2316                 ixgbe_irq_enable(adapter);
2317
2318         /* remove VID from filter table */
2319         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2320 }
2321
2322 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2323                                    struct vlan_group *grp)
2324 {
2325         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2326         u32 ctrl;
2327         int i, j;
2328
2329         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2330                 ixgbe_irq_disable(adapter);
2331         adapter->vlgrp = grp;
2332
2333         /*
2334          * For a DCB driver, always enable VLAN tag stripping so we can
2335          * still receive traffic from a DCB-enabled host even if we're
2336          * not in DCB mode.
2337          */
2338         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2339         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2340                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2341                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2342                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2343         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2344                 ctrl |= IXGBE_VLNCTRL_VFE;
2345                 /* enable VLAN tag insert/strip */
2346                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2347                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2348                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2349                 for (i = 0; i < adapter->num_rx_queues; i++) {
2350                         j = adapter->rx_ring[i].reg_idx;
2351                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2352                         ctrl |= IXGBE_RXDCTL_VME;
2353                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2354                 }
2355         }
2356         ixgbe_vlan_rx_add_vid(netdev, 0);
2357
2358         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2359                 ixgbe_irq_enable(adapter);
2360 }
2361
2362 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2363 {
2364         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2365
2366         if (adapter->vlgrp) {
2367                 u16 vid;
2368                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2369                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2370                                 continue;
2371                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2372                 }
2373         }
2374 }
2375
2376 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2377 {
2378         struct dev_mc_list *mc_ptr;
2379         u8 *addr = *mc_addr_ptr;
2380         *vmdq = 0;
2381
2382         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2383         if (mc_ptr->next)
2384                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2385         else
2386                 *mc_addr_ptr = NULL;
2387
2388         return addr;
2389 }
2390
2391 /**
2392  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2393  * @netdev: network interface device structure
2394  *
2395  * The set_rx_method entry point is called whenever the unicast/multicast
2396  * address list or the network interface flags are updated.  This routine is
2397  * responsible for configuring the hardware for proper unicast, multicast and
2398  * promiscuous mode.
2399  **/
2400 static void ixgbe_set_rx_mode(struct net_device *netdev)
2401 {
2402         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2403         struct ixgbe_hw *hw = &adapter->hw;
2404         u32 fctrl, vlnctrl;
2405         u8 *addr_list = NULL;
2406         int addr_count = 0;
2407
2408         /* Check for Promiscuous and All Multicast modes */
2409
2410         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2411         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2412
2413         if (netdev->flags & IFF_PROMISC) {
2414                 hw->addr_ctrl.user_set_promisc = 1;
2415                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2416                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2417         } else {
2418                 if (netdev->flags & IFF_ALLMULTI) {
2419                         fctrl |= IXGBE_FCTRL_MPE;
2420                         fctrl &= ~IXGBE_FCTRL_UPE;
2421                 } else {
2422                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2423                 }
2424                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2425                 hw->addr_ctrl.user_set_promisc = 0;
2426         }
2427
2428         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2429         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2430
2431         /* reprogram secondary unicast list */
2432         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2433
2434         /* reprogram multicast list */
2435         addr_count = netdev->mc_count;
2436         if (addr_count)
2437                 addr_list = netdev->mc_list->dmi_addr;
2438         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2439                                         ixgbe_addr_list_itr);
2440 }
2441
2442 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2443 {
2444         int q_idx;
2445         struct ixgbe_q_vector *q_vector;
2446         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2447
2448         /* legacy and MSI only use one vector */
2449         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2450                 q_vectors = 1;
2451
2452         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2453                 struct napi_struct *napi;
2454                 q_vector = adapter->q_vector[q_idx];
2455                 napi = &q_vector->napi;
2456                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2457                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2458                                 if (q_vector->txr_count == 1)
2459                                         napi->poll = &ixgbe_clean_txonly;
2460                                 else if (q_vector->rxr_count == 1)
2461                                         napi->poll = &ixgbe_clean_rxonly;
2462                         }
2463                 }
2464
2465                 napi_enable(napi);
2466         }
2467 }
2468
2469 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2470 {
2471         int q_idx;
2472         struct ixgbe_q_vector *q_vector;
2473         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2474
2475         /* legacy and MSI only use one vector */
2476         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2477                 q_vectors = 1;
2478
2479         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2480                 q_vector = adapter->q_vector[q_idx];
2481                 napi_disable(&q_vector->napi);
2482         }
2483 }
2484
2485 #ifdef CONFIG_IXGBE_DCB
2486 /*
2487  * ixgbe_configure_dcb - Configure DCB hardware
2488  * @adapter: ixgbe adapter struct
2489  *
2490  * This is called by the driver on open to configure the DCB hardware.
2491  * This is also called by the gennetlink interface when reconfiguring
2492  * the DCB state.
2493  */
2494 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2495 {
2496         struct ixgbe_hw *hw = &adapter->hw;
2497         u32 txdctl, vlnctrl;
2498         int i, j;
2499
2500         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2501         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2502         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2503
2504         /* reconfigure the hardware */
2505         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2506
2507         for (i = 0; i < adapter->num_tx_queues; i++) {
2508                 j = adapter->tx_ring[i].reg_idx;
2509                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2510                 /* PThresh workaround for Tx hang with DFP enabled. */
2511                 txdctl |= 32;
2512                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2513         }
2514         /* Enable VLAN tag insert/strip */
2515         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2516         if (hw->mac.type == ixgbe_mac_82598EB) {
2517                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2518                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2519                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2520         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2521                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2522                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2523                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2524                 for (i = 0; i < adapter->num_rx_queues; i++) {
2525                         j = adapter->rx_ring[i].reg_idx;
2526                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2527                         vlnctrl |= IXGBE_RXDCTL_VME;
2528                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2529                 }
2530         }
2531         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2532 }
2533
2534 #endif
2535 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2536 {
2537         struct net_device *netdev = adapter->netdev;
2538         struct ixgbe_hw *hw = &adapter->hw;
2539         int i;
2540
2541         ixgbe_set_rx_mode(netdev);
2542
2543         ixgbe_restore_vlan(adapter);
2544 #ifdef CONFIG_IXGBE_DCB
2545         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2546                 if (hw->mac.type == ixgbe_mac_82598EB)
2547                         netif_set_gso_max_size(netdev, 32768);
2548                 else
2549                         netif_set_gso_max_size(netdev, 65536);
2550                 ixgbe_configure_dcb(adapter);
2551         } else {
2552                 netif_set_gso_max_size(netdev, 65536);
2553         }
2554 #else
2555         netif_set_gso_max_size(netdev, 65536);
2556 #endif
2557
2558 #ifdef IXGBE_FCOE
2559         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2560                 ixgbe_configure_fcoe(adapter);
2561
2562 #endif /* IXGBE_FCOE */
2563         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2564                 for (i = 0; i < adapter->num_tx_queues; i++)
2565                         adapter->tx_ring[i].atr_sample_rate =
2566                                                        adapter->atr_sample_rate;
2567                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2568         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2569                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2570         }
2571
2572         ixgbe_configure_tx(adapter);
2573         ixgbe_configure_rx(adapter);
2574         for (i = 0; i < adapter->num_rx_queues; i++)
2575                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2576                                        (adapter->rx_ring[i].count - 1));
2577 }
2578
2579 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2580 {
2581         switch (hw->phy.type) {
2582         case ixgbe_phy_sfp_avago:
2583         case ixgbe_phy_sfp_ftl:
2584         case ixgbe_phy_sfp_intel:
2585         case ixgbe_phy_sfp_unknown:
2586         case ixgbe_phy_tw_tyco:
2587         case ixgbe_phy_tw_unknown:
2588                 return true;
2589         default:
2590                 return false;
2591         }
2592 }
2593
2594 /**
2595  * ixgbe_sfp_link_config - set up SFP+ link
2596  * @adapter: pointer to private adapter struct
2597  **/
2598 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2599 {
2600         struct ixgbe_hw *hw = &adapter->hw;
2601
2602                 if (hw->phy.multispeed_fiber) {
2603                         /*
2604                          * In multispeed fiber setups, the device may not have
2605                          * had a physical connection when the driver loaded.
2606                          * If that's the case, the initial link configuration
2607                          * couldn't get the MAC into 10G or 1G mode, so we'll
2608                          * never have a link status change interrupt fire.
2609                          * We need to try and force an autonegotiation
2610                          * session, then bring up link.
2611                          */
2612                         hw->mac.ops.setup_sfp(hw);
2613                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2614                                 schedule_work(&adapter->multispeed_fiber_task);
2615                 } else {
2616                         /*
2617                          * Direct Attach Cu and non-multispeed fiber modules
2618                          * still need to be configured properly prior to
2619                          * attempting link.
2620                          */
2621                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2622                                 schedule_work(&adapter->sfp_config_module_task);
2623                 }
2624 }
2625
2626 /**
2627  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2628  * @hw: pointer to private hardware struct
2629  *
2630  * Returns 0 on success, negative on failure
2631  **/
2632 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2633 {
2634         u32 autoneg;
2635         bool negotiation, link_up = false;
2636         u32 ret = IXGBE_ERR_LINK_SETUP;
2637
2638         if (hw->mac.ops.check_link)
2639                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2640
2641         if (ret)
2642                 goto link_cfg_out;
2643
2644         if (hw->mac.ops.get_link_capabilities)
2645                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2646         if (ret)
2647                 goto link_cfg_out;
2648
2649         if (hw->mac.ops.setup_link)
2650                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2651 link_cfg_out:
2652         return ret;
2653 }
2654
2655 #define IXGBE_MAX_RX_DESC_POLL 10
2656 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2657                                               int rxr)
2658 {
2659         int j = adapter->rx_ring[rxr].reg_idx;
2660         int k;
2661
2662         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2663                 if (IXGBE_READ_REG(&adapter->hw,
2664                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2665                         break;
2666                 else
2667                         msleep(1);
2668         }
2669         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2670                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2671                         "not set within the polling period\n", rxr);
2672         }
2673         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2674                               (adapter->rx_ring[rxr].count - 1));
2675 }
2676
2677 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2678 {
2679         struct net_device *netdev = adapter->netdev;
2680         struct ixgbe_hw *hw = &adapter->hw;
2681         int i, j = 0;
2682         int num_rx_rings = adapter->num_rx_queues;
2683         int err;
2684         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2685         u32 txdctl, rxdctl, mhadd;
2686         u32 dmatxctl;
2687         u32 gpie;
2688
2689         ixgbe_get_hw_control(adapter);
2690
2691         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2692             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2693                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2694                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2695                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2696                 } else {
2697                         /* MSI only */
2698                         gpie = 0;
2699                 }
2700                 /* XXX: to interrupt immediately for EICS writes, enable this */
2701                 /* gpie |= IXGBE_GPIE_EIMEN; */
2702                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2703         }
2704
2705         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2706                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2707                  * specifically only auto mask tx and rx interrupts */
2708                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2709         }
2710
2711         /* Enable fan failure interrupt if media type is copper */
2712         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2713                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2714                 gpie |= IXGBE_SDP1_GPIEN;
2715                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2716         }
2717
2718         if (hw->mac.type == ixgbe_mac_82599EB) {
2719                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2720                 gpie |= IXGBE_SDP1_GPIEN;
2721                 gpie |= IXGBE_SDP2_GPIEN;
2722                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2723         }
2724
2725 #ifdef IXGBE_FCOE
2726         /* adjust max frame to be able to do baby jumbo for FCoE */
2727         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2728             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2729                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2730
2731 #endif /* IXGBE_FCOE */
2732         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2733         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2734                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2735                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2736
2737                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2738         }
2739
2740         for (i = 0; i < adapter->num_tx_queues; i++) {
2741                 j = adapter->tx_ring[i].reg_idx;
2742                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2743                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2744                 txdctl |= (8 << 16);
2745                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2746         }
2747
2748         if (hw->mac.type == ixgbe_mac_82599EB) {
2749                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2750                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2751                 dmatxctl |= IXGBE_DMATXCTL_TE;
2752                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2753         }
2754         for (i = 0; i < adapter->num_tx_queues; i++) {
2755                 j = adapter->tx_ring[i].reg_idx;
2756                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2757                 txdctl |= IXGBE_TXDCTL_ENABLE;
2758                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2759         }
2760
2761         for (i = 0; i < num_rx_rings; i++) {
2762                 j = adapter->rx_ring[i].reg_idx;
2763                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2764                 /* enable PTHRESH=32 descriptors (half the internal cache)
2765                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2766                  * this also removes a pesky rx_no_buffer_count increment */
2767                 rxdctl |= 0x0020;
2768                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2769                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2770                 if (hw->mac.type == ixgbe_mac_82599EB)
2771                         ixgbe_rx_desc_queue_enable(adapter, i);
2772         }
2773         /* enable all receives */
2774         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2775         if (hw->mac.type == ixgbe_mac_82598EB)
2776                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2777         else
2778                 rxdctl |= IXGBE_RXCTRL_RXEN;
2779         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2780
2781         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2782                 ixgbe_configure_msix(adapter);
2783         else
2784                 ixgbe_configure_msi_and_legacy(adapter);
2785
2786         clear_bit(__IXGBE_DOWN, &adapter->state);
2787         ixgbe_napi_enable_all(adapter);
2788
2789         /* clear any pending interrupts, may auto mask */
2790         IXGBE_READ_REG(hw, IXGBE_EICR);
2791
2792         ixgbe_irq_enable(adapter);
2793
2794         /*
2795          * If this adapter has a fan, check to see if we had a failure
2796          * before we enabled the interrupt.
2797          */
2798         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2799                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2800                 if (esdp & IXGBE_ESDP_SDP1)
2801                         DPRINTK(DRV, CRIT,
2802                                 "Fan has stopped, replace the adapter\n");
2803         }
2804
2805         /*
2806          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2807          * arrived before interrupts were enabled but after probe.  Such
2808          * devices wouldn't have their type identified yet. We need to
2809          * kick off the SFP+ module setup first, then try to bring up link.
2810          * If we're not hot-pluggable SFP+, we just need to configure link
2811          * and bring it up.
2812          */
2813         if (hw->phy.type == ixgbe_phy_unknown) {
2814                 err = hw->phy.ops.identify(hw);
2815                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2816                         /*
2817                          * Take the device down and schedule the sfp tasklet
2818                          * which will unregister_netdev and log it.
2819                          */
2820                         ixgbe_down(adapter);
2821                         schedule_work(&adapter->sfp_config_module_task);
2822                         return err;
2823                 }
2824         }
2825
2826         if (ixgbe_is_sfp(hw)) {
2827                 ixgbe_sfp_link_config(adapter);
2828         } else {
2829                 err = ixgbe_non_sfp_link_config(hw);
2830                 if (err)
2831                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2832         }
2833
2834         for (i = 0; i < adapter->num_tx_queues; i++)
2835                 set_bit(__IXGBE_FDIR_INIT_DONE,
2836                         &(adapter->tx_ring[i].reinit_state));
2837
2838         /* enable transmits */
2839         netif_tx_start_all_queues(netdev);
2840
2841         /* bring the link up in the watchdog, this could race with our first
2842          * link up interrupt but shouldn't be a problem */
2843         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2844         adapter->link_check_timeout = jiffies;
2845         mod_timer(&adapter->watchdog_timer, jiffies);
2846         return 0;
2847 }
2848
2849 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2850 {
2851         WARN_ON(in_interrupt());
2852         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2853                 msleep(1);
2854         ixgbe_down(adapter);
2855         ixgbe_up(adapter);
2856         clear_bit(__IXGBE_RESETTING, &adapter->state);
2857 }
2858
2859 int ixgbe_up(struct ixgbe_adapter *adapter)
2860 {
2861         /* hardware has been reset, we need to reload some things */
2862         ixgbe_configure(adapter);
2863
2864         return ixgbe_up_complete(adapter);
2865 }
2866
2867 void ixgbe_reset(struct ixgbe_adapter *adapter)
2868 {
2869         struct ixgbe_hw *hw = &adapter->hw;
2870         int err;
2871
2872         err = hw->mac.ops.init_hw(hw);
2873         switch (err) {
2874         case 0:
2875         case IXGBE_ERR_SFP_NOT_PRESENT:
2876                 break;
2877         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2878                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2879                 break;
2880         case IXGBE_ERR_EEPROM_VERSION:
2881                 /* We are running on a pre-production device, log a warning */
2882                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2883                          "adapter/LOM.  Please be aware there may be issues "
2884                          "associated with your hardware.  If you are "
2885                          "experiencing problems please contact your Intel or "
2886                          "hardware representative who provided you with this "
2887                          "hardware.\n");
2888                 break;
2889         default:
2890                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2891         }
2892
2893         /* reprogram the RAR[0] in case user changed it. */
2894         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2895 }
2896
2897 /**
2898  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2899  * @adapter: board private structure
2900  * @rx_ring: ring to free buffers from
2901  **/
2902 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2903                                 struct ixgbe_ring *rx_ring)
2904 {
2905         struct pci_dev *pdev = adapter->pdev;
2906         unsigned long size;
2907         unsigned int i;
2908
2909         /* Free all the Rx ring sk_buffs */
2910
2911         for (i = 0; i < rx_ring->count; i++) {
2912                 struct ixgbe_rx_buffer *rx_buffer_info;
2913
2914                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2915                 if (rx_buffer_info->dma) {
2916                         pci_unmap_single(pdev, rx_buffer_info->dma,
2917                                          rx_ring->rx_buf_len,
2918                                          PCI_DMA_FROMDEVICE);
2919                         rx_buffer_info->dma = 0;
2920                 }
2921                 if (rx_buffer_info->skb) {
2922                         struct sk_buff *skb = rx_buffer_info->skb;
2923                         rx_buffer_info->skb = NULL;
2924                         do {
2925                                 struct sk_buff *this = skb;
2926                                 skb = skb->prev;
2927                                 dev_kfree_skb(this);
2928                         } while (skb);
2929                 }
2930                 if (!rx_buffer_info->page)
2931                         continue;
2932                 if (rx_buffer_info->page_dma) {
2933                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2934                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2935                         rx_buffer_info->page_dma = 0;
2936                 }
2937                 put_page(rx_buffer_info->page);
2938                 rx_buffer_info->page = NULL;
2939                 rx_buffer_info->page_offset = 0;
2940         }
2941
2942         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2943         memset(rx_ring->rx_buffer_info, 0, size);
2944
2945         /* Zero out the descriptor ring */
2946         memset(rx_ring->desc, 0, rx_ring->size);
2947
2948         rx_ring->next_to_clean = 0;
2949         rx_ring->next_to_use = 0;
2950
2951         if (rx_ring->head)
2952                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2953         if (rx_ring->tail)
2954                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2955 }
2956
2957 /**
2958  * ixgbe_clean_tx_ring - Free Tx Buffers
2959  * @adapter: board private structure
2960  * @tx_ring: ring to be cleaned
2961  **/
2962 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2963                                 struct ixgbe_ring *tx_ring)
2964 {
2965         struct ixgbe_tx_buffer *tx_buffer_info;
2966         unsigned long size;
2967         unsigned int i;
2968
2969         /* Free all the Tx ring sk_buffs */
2970
2971         for (i = 0; i < tx_ring->count; i++) {
2972                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2973                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2974         }
2975
2976         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2977         memset(tx_ring->tx_buffer_info, 0, size);
2978
2979         /* Zero out the descriptor ring */
2980         memset(tx_ring->desc, 0, tx_ring->size);
2981
2982         tx_ring->next_to_use = 0;
2983         tx_ring->next_to_clean = 0;
2984
2985         if (tx_ring->head)
2986                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2987         if (tx_ring->tail)
2988                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2989 }
2990
2991 /**
2992  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2993  * @adapter: board private structure
2994  **/
2995 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2996 {
2997         int i;
2998
2999         for (i = 0; i < adapter->num_rx_queues; i++)
3000                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3001 }
3002
3003 /**
3004  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3005  * @adapter: board private structure
3006  **/
3007 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3008 {
3009         int i;
3010
3011         for (i = 0; i < adapter->num_tx_queues; i++)
3012                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3013 }
3014
3015 void ixgbe_down(struct ixgbe_adapter *adapter)
3016 {
3017         struct net_device *netdev = adapter->netdev;
3018         struct ixgbe_hw *hw = &adapter->hw;
3019         u32 rxctrl;
3020         u32 txdctl;
3021         int i, j;
3022
3023         /* signal that we are down to the interrupt handler */
3024         set_bit(__IXGBE_DOWN, &adapter->state);
3025
3026         /* disable receives */
3027         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3028         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3029
3030         netif_tx_disable(netdev);
3031
3032         IXGBE_WRITE_FLUSH(hw);
3033         msleep(10);
3034
3035         netif_tx_stop_all_queues(netdev);
3036
3037         ixgbe_irq_disable(adapter);
3038
3039         ixgbe_napi_disable_all(adapter);
3040
3041         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3042         del_timer_sync(&adapter->sfp_timer);
3043         del_timer_sync(&adapter->watchdog_timer);
3044         cancel_work_sync(&adapter->watchdog_task);
3045
3046         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3047             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3048                 cancel_work_sync(&adapter->fdir_reinit_task);
3049
3050         /* disable transmits in the hardware now that interrupts are off */
3051         for (i = 0; i < adapter->num_tx_queues; i++) {
3052                 j = adapter->tx_ring[i].reg_idx;
3053                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3054                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3055                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3056         }
3057         /* Disable the Tx DMA engine on 82599 */
3058         if (hw->mac.type == ixgbe_mac_82599EB)
3059                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3060                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3061                                  ~IXGBE_DMATXCTL_TE));
3062
3063         netif_carrier_off(netdev);
3064
3065         if (!pci_channel_offline(adapter->pdev))
3066                 ixgbe_reset(adapter);
3067         ixgbe_clean_all_tx_rings(adapter);
3068         ixgbe_clean_all_rx_rings(adapter);
3069
3070 #ifdef CONFIG_IXGBE_DCA
3071         /* since we reset the hardware DCA settings were cleared */
3072         ixgbe_setup_dca(adapter);
3073 #endif
3074 }
3075
3076 /**
3077  * ixgbe_poll - NAPI Rx polling callback
3078  * @napi: structure for representing this polling device
3079  * @budget: how many packets driver is allowed to clean
3080  *
3081  * This function is used for legacy and MSI, NAPI mode
3082  **/
3083 static int ixgbe_poll(struct napi_struct *napi, int budget)
3084 {
3085         struct ixgbe_q_vector *q_vector =
3086                                 container_of(napi, struct ixgbe_q_vector, napi);
3087         struct ixgbe_adapter *adapter = q_vector->adapter;
3088         int tx_clean_complete, work_done = 0;
3089
3090 #ifdef CONFIG_IXGBE_DCA
3091         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3092                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3093                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3094         }
3095 #endif
3096
3097         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3098         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3099
3100         if (!tx_clean_complete)
3101                 work_done = budget;
3102
3103         /* If budget not fully consumed, exit the polling mode */
3104         if (work_done < budget) {
3105                 napi_complete(napi);
3106                 if (adapter->rx_itr_setting & 1)
3107                         ixgbe_set_itr(adapter);
3108                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3109                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3110         }
3111         return work_done;
3112 }
3113
3114 /**
3115  * ixgbe_tx_timeout - Respond to a Tx Hang
3116  * @netdev: network interface device structure
3117  **/
3118 static void ixgbe_tx_timeout(struct net_device *netdev)
3119 {
3120         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3121
3122         /* Do the reset outside of interrupt context */
3123         schedule_work(&adapter->reset_task);
3124 }
3125
3126 static void ixgbe_reset_task(struct work_struct *work)
3127 {
3128         struct ixgbe_adapter *adapter;
3129         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3130
3131         /* If we're already down or resetting, just bail */
3132         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3133             test_bit(__IXGBE_RESETTING, &adapter->state))
3134                 return;
3135
3136         adapter->tx_timeout_count++;
3137
3138         ixgbe_reinit_locked(adapter);
3139 }
3140
3141 #ifdef CONFIG_IXGBE_DCB
3142 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3143 {
3144         bool ret = false;
3145         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3146
3147         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3148                 return ret;
3149
3150         f->mask = 0x7 << 3;
3151         adapter->num_rx_queues = f->indices;
3152         adapter->num_tx_queues = f->indices;
3153         ret = true;
3154
3155         return ret;
3156 }
3157 #endif
3158
3159 /**
3160  * ixgbe_set_rss_queues: Allocate queues for RSS
3161  * @adapter: board private structure to initialize
3162  *
3163  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3164  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3165  *
3166  **/
3167 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3168 {
3169         bool ret = false;
3170         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3171
3172         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3173                 f->mask = 0xF;
3174                 adapter->num_rx_queues = f->indices;
3175                 adapter->num_tx_queues = f->indices;
3176                 ret = true;
3177         } else {
3178                 ret = false;
3179         }
3180
3181         return ret;
3182 }
3183
3184 /**
3185  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3186  * @adapter: board private structure to initialize
3187  *
3188  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3189  * to the original CPU that initiated the Tx session.  This runs in addition
3190  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3191  * Rx load across CPUs using RSS.
3192  *
3193  **/
3194 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3195 {
3196         bool ret = false;
3197         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3198
3199         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3200         f_fdir->mask = 0;
3201
3202         /* Flow Director must have RSS enabled */
3203         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3204             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3205              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3206                 adapter->num_tx_queues = f_fdir->indices;
3207                 adapter->num_rx_queues = f_fdir->indices;
3208                 ret = true;
3209         } else {
3210                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3211                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3212         }
3213         return ret;
3214 }
3215
3216 #ifdef IXGBE_FCOE
3217 /**
3218  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3219  * @adapter: board private structure to initialize
3220  *
3221  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3222  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3223  * rx queues out of the max number of rx queues, instead, it is used as the
3224  * index of the first rx queue used by FCoE.
3225  *
3226  **/
3227 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3228 {
3229         bool ret = false;
3230         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3231
3232         f->indices = min((int)num_online_cpus(), f->indices);
3233         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3234                 adapter->num_rx_queues = 1;
3235                 adapter->num_tx_queues = 1;
3236 #ifdef CONFIG_IXGBE_DCB
3237                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3238                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3239                         ixgbe_set_dcb_queues(adapter);
3240                 }
3241 #endif
3242                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3243                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3244                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3245                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3246                                 ixgbe_set_fdir_queues(adapter);
3247                         else
3248                                 ixgbe_set_rss_queues(adapter);
3249                 }
3250                 /* adding FCoE rx rings to the end */
3251                 f->mask = adapter->num_rx_queues;
3252                 adapter->num_rx_queues += f->indices;
3253                 adapter->num_tx_queues += f->indices;
3254
3255                 ret = true;
3256         }
3257
3258         return ret;
3259 }
3260
3261 #endif /* IXGBE_FCOE */
3262 /*
3263  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3264  * @adapter: board private structure to initialize
3265  *
3266  * This is the top level queue allocation routine.  The order here is very
3267  * important, starting with the "most" number of features turned on at once,
3268  * and ending with the smallest set of features.  This way large combinations
3269  * can be allocated if they're turned on, and smaller combinations are the
3270  * fallthrough conditions.
3271  *
3272  **/
3273 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3274 {
3275 #ifdef IXGBE_FCOE
3276         if (ixgbe_set_fcoe_queues(adapter))
3277                 goto done;
3278
3279 #endif /* IXGBE_FCOE */
3280 #ifdef CONFIG_IXGBE_DCB
3281         if (ixgbe_set_dcb_queues(adapter))
3282                 goto done;
3283
3284 #endif
3285         if (ixgbe_set_fdir_queues(adapter))
3286                 goto done;
3287
3288         if (ixgbe_set_rss_queues(adapter))
3289                 goto done;
3290
3291         /* fallback to base case */
3292         adapter->num_rx_queues = 1;
3293         adapter->num_tx_queues = 1;
3294
3295 done:
3296         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3297         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3298 }
3299
3300 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3301                                        int vectors)
3302 {
3303         int err, vector_threshold;
3304
3305         /* We'll want at least 3 (vector_threshold):
3306          * 1) TxQ[0] Cleanup
3307          * 2) RxQ[0] Cleanup
3308          * 3) Other (Link Status Change, etc.)
3309          * 4) TCP Timer (optional)
3310          */
3311         vector_threshold = MIN_MSIX_COUNT;
3312
3313         /* The more we get, the more we will assign to Tx/Rx Cleanup
3314          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3315          * Right now, we simply care about how many we'll get; we'll
3316          * set them up later while requesting irq's.
3317          */
3318         while (vectors >= vector_threshold) {
3319                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3320                                       vectors);
3321                 if (!err) /* Success in acquiring all requested vectors. */
3322                         break;
3323                 else if (err < 0)
3324                         vectors = 0; /* Nasty failure, quit now */
3325                 else /* err == number of vectors we should try again with */
3326                         vectors = err;
3327         }
3328
3329         if (vectors < vector_threshold) {
3330                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3331                  * This just means we'll go with either a single MSI
3332                  * vector or fall back to legacy interrupts.
3333                  */
3334                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3335                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3336                 kfree(adapter->msix_entries);
3337                 adapter->msix_entries = NULL;
3338         } else {
3339                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3340                 /*
3341                  * Adjust for only the vectors we'll use, which is minimum
3342                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3343                  * vectors we were allocated.
3344                  */
3345                 adapter->num_msix_vectors = min(vectors,
3346                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3347         }
3348 }
3349
3350 /**
3351  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3352  * @adapter: board private structure to initialize
3353  *
3354  * Cache the descriptor ring offsets for RSS to the assigned rings.
3355  *
3356  **/
3357 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3358 {
3359         int i;
3360         bool ret = false;
3361
3362         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3363                 for (i = 0; i < adapter->num_rx_queues; i++)
3364                         adapter->rx_ring[i].reg_idx = i;
3365                 for (i = 0; i < adapter->num_tx_queues; i++)
3366                         adapter->tx_ring[i].reg_idx = i;
3367                 ret = true;
3368         } else {
3369                 ret = false;
3370         }
3371
3372         return ret;
3373 }
3374
3375 #ifdef CONFIG_IXGBE_DCB
3376 /**
3377  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3378  * @adapter: board private structure to initialize
3379  *
3380  * Cache the descriptor ring offsets for DCB to the assigned rings.
3381  *
3382  **/
3383 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3384 {
3385         int i;
3386         bool ret = false;
3387         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3388
3389         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3390                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3391                         /* the number of queues is assumed to be symmetric */
3392                         for (i = 0; i < dcb_i; i++) {
3393                                 adapter->rx_ring[i].reg_idx = i << 3;
3394                                 adapter->tx_ring[i].reg_idx = i << 2;
3395                         }
3396                         ret = true;
3397                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3398                         if (dcb_i == 8) {
3399                                 /*
3400                                  * Tx TC0 starts at: descriptor queue 0
3401                                  * Tx TC1 starts at: descriptor queue 32
3402                                  * Tx TC2 starts at: descriptor queue 64
3403                                  * Tx TC3 starts at: descriptor queue 80
3404                                  * Tx TC4 starts at: descriptor queue 96
3405                                  * Tx TC5 starts at: descriptor queue 104
3406                                  * Tx TC6 starts at: descriptor queue 112
3407                                  * Tx TC7 starts at: descriptor queue 120
3408                                  *
3409                                  * Rx TC0-TC7 are offset by 16 queues each
3410                                  */
3411                                 for (i = 0; i < 3; i++) {
3412                                         adapter->tx_ring[i].reg_idx = i << 5;
3413                                         adapter->rx_ring[i].reg_idx = i << 4;
3414                                 }
3415                                 for ( ; i < 5; i++) {
3416                                         adapter->tx_ring[i].reg_idx =
3417                                                                  ((i + 2) << 4);
3418                                         adapter->rx_ring[i].reg_idx = i << 4;
3419                                 }
3420                                 for ( ; i < dcb_i; i++) {
3421                                         adapter->tx_ring[i].reg_idx =
3422                                                                  ((i + 8) << 3);
3423                                         adapter->rx_ring[i].reg_idx = i << 4;
3424                                 }
3425
3426                                 ret = true;
3427                         } else if (dcb_i == 4) {
3428                                 /*
3429                                  * Tx TC0 starts at: descriptor queue 0
3430                                  * Tx TC1 starts at: descriptor queue 64
3431                                  * Tx TC2 starts at: descriptor queue 96
3432                                  * Tx TC3 starts at: descriptor queue 112
3433                                  *
3434                                  * Rx TC0-TC3 are offset by 32 queues each
3435                                  */
3436                                 adapter->tx_ring[0].reg_idx = 0;
3437                                 adapter->tx_ring[1].reg_idx = 64;
3438                                 adapter->tx_ring[2].reg_idx = 96;
3439                                 adapter->tx_ring[3].reg_idx = 112;
3440                                 for (i = 0 ; i < dcb_i; i++)
3441                                         adapter->rx_ring[i].reg_idx = i << 5;
3442
3443                                 ret = true;
3444                         } else {
3445                                 ret = false;
3446                         }
3447                 } else {
3448                         ret = false;
3449                 }
3450         } else {
3451                 ret = false;
3452         }
3453
3454         return ret;
3455 }
3456 #endif
3457
3458 /**
3459  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3460  * @adapter: board private structure to initialize
3461  *
3462  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3463  *
3464  **/
3465 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3466 {
3467         int i;
3468         bool ret = false;
3469
3470         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3471             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3472              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3473                 for (i = 0; i < adapter->num_rx_queues; i++)
3474                         adapter->rx_ring[i].reg_idx = i;
3475                 for (i = 0; i < adapter->num_tx_queues; i++)
3476                         adapter->tx_ring[i].reg_idx = i;
3477                 ret = true;
3478         }
3479
3480         return ret;
3481 }
3482
3483 #ifdef IXGBE_FCOE
3484 /**
3485  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3486  * @adapter: board private structure to initialize
3487  *
3488  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3489  *
3490  */
3491 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3492 {
3493         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3494         bool ret = false;
3495         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3496
3497         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3498 #ifdef CONFIG_IXGBE_DCB
3499                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3500                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3501
3502                         ixgbe_cache_ring_dcb(adapter);
3503                         /* find out queues in TC for FCoE */
3504                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3505                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3506                         /*
3507                          * In 82599, the number of Tx queues for each traffic
3508                          * class for both 8-TC and 4-TC modes are:
3509                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3510                          * 8 TCs:  32  32  16  16   8   8   8   8
3511                          * 4 TCs:  64  64  32  32
3512                          * We have max 8 queues for FCoE, where 8 the is
3513                          * FCoE redirection table size. If TC for FCoE is
3514                          * less than or equal to TC3, we have enough queues
3515                          * to add max of 8 queues for FCoE, so we start FCoE
3516                          * tx descriptor from the next one, i.e., reg_idx + 1.
3517                          * If TC for FCoE is above TC3, implying 8 TC mode,
3518                          * and we need 8 for FCoE, we have to take all queues
3519                          * in that traffic class for FCoE.
3520                          */
3521                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3522                                 fcoe_tx_i--;
3523                 }
3524 #endif /* CONFIG_IXGBE_DCB */
3525                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3526                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3527                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3528                                 ixgbe_cache_ring_fdir(adapter);
3529                         else
3530                                 ixgbe_cache_ring_rss(adapter);
3531
3532                         fcoe_rx_i = f->mask;
3533                         fcoe_tx_i = f->mask;
3534                 }
3535                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3536                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3537                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3538                 }
3539                 ret = true;
3540         }
3541         return ret;
3542 }
3543
3544 #endif /* IXGBE_FCOE */
3545 /**
3546  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3547  * @adapter: board private structure to initialize
3548  *
3549  * Once we know the feature-set enabled for the device, we'll cache
3550  * the register offset the descriptor ring is assigned to.
3551  *
3552  * Note, the order the various feature calls is important.  It must start with
3553  * the "most" features enabled at the same time, then trickle down to the
3554  * least amount of features turned on at once.
3555  **/
3556 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3557 {
3558         /* start with default case */
3559         adapter->rx_ring[0].reg_idx = 0;
3560         adapter->tx_ring[0].reg_idx = 0;
3561
3562 #ifdef IXGBE_FCOE
3563         if (ixgbe_cache_ring_fcoe(adapter))
3564                 return;
3565
3566 #endif /* IXGBE_FCOE */
3567 #ifdef CONFIG_IXGBE_DCB
3568         if (ixgbe_cache_ring_dcb(adapter))
3569                 return;
3570
3571 #endif
3572         if (ixgbe_cache_ring_fdir(adapter))
3573                 return;
3574
3575         if (ixgbe_cache_ring_rss(adapter))
3576                 return;
3577 }
3578
3579 /**
3580  * ixgbe_alloc_queues - Allocate memory for all rings
3581  * @adapter: board private structure to initialize
3582  *
3583  * We allocate one ring per queue at run-time since we don't know the
3584  * number of queues at compile-time.  The polling_netdev array is
3585  * intended for Multiqueue, but should work fine with a single queue.
3586  **/
3587 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3588 {
3589         int i;
3590
3591         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3592                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3593         if (!adapter->tx_ring)
3594                 goto err_tx_ring_allocation;
3595
3596         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3597                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3598         if (!adapter->rx_ring)
3599                 goto err_rx_ring_allocation;
3600
3601         for (i = 0; i < adapter->num_tx_queues; i++) {
3602                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3603                 adapter->tx_ring[i].queue_index = i;
3604         }
3605
3606         for (i = 0; i < adapter->num_rx_queues; i++) {
3607                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3608                 adapter->rx_ring[i].queue_index = i;
3609         }
3610
3611         ixgbe_cache_ring_register(adapter);
3612
3613         return 0;
3614
3615 err_rx_ring_allocation:
3616         kfree(adapter->tx_ring);
3617 err_tx_ring_allocation:
3618         return -ENOMEM;
3619 }
3620
3621 /**
3622  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3623  * @adapter: board private structure to initialize
3624  *
3625  * Attempt to configure the interrupts using the best available
3626  * capabilities of the hardware and the kernel.
3627  **/
3628 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3629 {
3630         struct ixgbe_hw *hw = &adapter->hw;
3631         int err = 0;
3632         int vector, v_budget;
3633
3634         /*
3635          * It's easy to be greedy for MSI-X vectors, but it really
3636          * doesn't do us much good if we have a lot more vectors
3637          * than CPU's.  So let's be conservative and only ask for
3638          * (roughly) the same number of vectors as there are CPU's.
3639          */
3640         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3641                        (int)num_online_cpus()) + NON_Q_VECTORS;
3642
3643         /*
3644          * At the same time, hardware can only support a maximum of
3645          * hw.mac->max_msix_vectors vectors.  With features
3646          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3647          * descriptor queues supported by our device.  Thus, we cap it off in
3648          * those rare cases where the cpu count also exceeds our vector limit.
3649          */
3650         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3651
3652         /* A failure in MSI-X entry allocation isn't fatal, but it does
3653          * mean we disable MSI-X capabilities of the adapter. */
3654         adapter->msix_entries = kcalloc(v_budget,
3655                                         sizeof(struct msix_entry), GFP_KERNEL);
3656         if (adapter->msix_entries) {
3657                 for (vector = 0; vector < v_budget; vector++)
3658                         adapter->msix_entries[vector].entry = vector;
3659
3660                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3661
3662                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3663                         goto out;
3664         }
3665
3666         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3667         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3668         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3669         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3670         adapter->atr_sample_rate = 0;
3671         ixgbe_set_num_queues(adapter);
3672
3673         err = pci_enable_msi(adapter->pdev);
3674         if (!err) {
3675                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3676         } else {
3677                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3678                         "falling back to legacy.  Error: %d\n", err);
3679                 /* reset err */
3680                 err = 0;
3681         }
3682
3683 out:
3684         return err;
3685 }
3686
3687 /**
3688  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3689  * @adapter: board private structure to initialize
3690  *
3691  * We allocate one q_vector per queue interrupt.  If allocation fails we
3692  * return -ENOMEM.
3693  **/
3694 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3695 {
3696         int q_idx, num_q_vectors;
3697         struct ixgbe_q_vector *q_vector;
3698         int napi_vectors;
3699         int (*poll)(struct napi_struct *, int);
3700
3701         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3702                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3703                 napi_vectors = adapter->num_rx_queues;
3704                 poll = &ixgbe_clean_rxtx_many;
3705         } else {
3706                 num_q_vectors = 1;
3707                 napi_vectors = 1;
3708                 poll = &ixgbe_poll;
3709         }
3710
3711         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3712                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3713                 if (!q_vector)
3714                         goto err_out;
3715                 q_vector->adapter = adapter;
3716                 if (q_vector->txr_count && !q_vector->rxr_count)
3717                         q_vector->eitr = adapter->tx_eitr_param;
3718                 else
3719                         q_vector->eitr = adapter->rx_eitr_param;
3720                 q_vector->v_idx = q_idx;
3721                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3722                 adapter->q_vector[q_idx] = q_vector;
3723         }
3724
3725         return 0;
3726
3727 err_out:
3728         while (q_idx) {
3729                 q_idx--;
3730                 q_vector = adapter->q_vector[q_idx];
3731                 netif_napi_del(&q_vector->napi);
3732                 kfree(q_vector);
3733                 adapter->q_vector[q_idx] = NULL;
3734         }
3735         return -ENOMEM;
3736 }
3737
3738 /**
3739  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3740  * @adapter: board private structure to initialize
3741  *
3742  * This function frees the memory allocated to the q_vectors.  In addition if
3743  * NAPI is enabled it will delete any references to the NAPI struct prior
3744  * to freeing the q_vector.
3745  **/
3746 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3747 {
3748         int q_idx, num_q_vectors;
3749
3750         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3751                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3752         else
3753                 num_q_vectors = 1;
3754
3755         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3756                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3757                 adapter->q_vector[q_idx] = NULL;
3758                 netif_napi_del(&q_vector->napi);
3759                 kfree(q_vector);
3760         }
3761 }
3762
3763 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3764 {
3765         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3766                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3767                 pci_disable_msix(adapter->pdev);
3768                 kfree(adapter->msix_entries);
3769                 adapter->msix_entries = NULL;
3770         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3771                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3772                 pci_disable_msi(adapter->pdev);
3773         }
3774         return;
3775 }
3776
3777 /**
3778  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3779  * @adapter: board private structure to initialize
3780  *
3781  * We determine which interrupt scheme to use based on...
3782  * - Kernel support (MSI, MSI-X)
3783  *   - which can be user-defined (via MODULE_PARAM)
3784  * - Hardware queue count (num_*_queues)
3785  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3786  **/
3787 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3788 {
3789         int err;
3790
3791         /* Number of supported queues */
3792         ixgbe_set_num_queues(adapter);
3793
3794         err = ixgbe_set_interrupt_capability(adapter);
3795         if (err) {
3796                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3797                 goto err_set_interrupt;
3798         }
3799
3800         err = ixgbe_alloc_q_vectors(adapter);
3801         if (err) {
3802                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3803                         "vectors\n");
3804                 goto err_alloc_q_vectors;
3805         }
3806
3807         err = ixgbe_alloc_queues(adapter);
3808         if (err) {
3809                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3810                 goto err_alloc_queues;
3811         }
3812
3813         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3814                 "Tx Queue count = %u\n",
3815                 (adapter->num_rx_queues > 1) ? "Enabled" :
3816                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3817
3818         set_bit(__IXGBE_DOWN, &adapter->state);
3819
3820         return 0;
3821
3822 err_alloc_queues:
3823         ixgbe_free_q_vectors(adapter);
3824 err_alloc_q_vectors:
3825         ixgbe_reset_interrupt_capability(adapter);
3826 err_set_interrupt:
3827         return err;
3828 }
3829
3830 /**
3831  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3832  * @adapter: board private structure to clear interrupt scheme on
3833  *
3834  * We go through and clear interrupt specific resources and reset the structure
3835  * to pre-load conditions
3836  **/
3837 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3838 {
3839         kfree(adapter->tx_ring);
3840         kfree(adapter->rx_ring);
3841         adapter->tx_ring = NULL;
3842         adapter->rx_ring = NULL;
3843
3844         ixgbe_free_q_vectors(adapter);
3845         ixgbe_reset_interrupt_capability(adapter);
3846 }
3847
3848 /**
3849  * ixgbe_sfp_timer - worker thread to find a missing module
3850  * @data: pointer to our adapter struct
3851  **/
3852 static void ixgbe_sfp_timer(unsigned long data)
3853 {
3854         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3855
3856         /*
3857          * Do the sfp_timer outside of interrupt context due to the
3858          * delays that sfp+ detection requires
3859          */
3860         schedule_work(&adapter->sfp_task);
3861 }
3862
3863 /**
3864  * ixgbe_sfp_task - worker thread to find a missing module
3865  * @work: pointer to work_struct containing our data
3866  **/
3867 static void ixgbe_sfp_task(struct work_struct *work)
3868 {
3869         struct ixgbe_adapter *adapter = container_of(work,
3870                                                      struct ixgbe_adapter,
3871                                                      sfp_task);
3872         struct ixgbe_hw *hw = &adapter->hw;
3873
3874         if ((hw->phy.type == ixgbe_phy_nl) &&
3875             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3876                 s32 ret = hw->phy.ops.identify_sfp(hw);
3877                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3878                         goto reschedule;
3879                 ret = hw->phy.ops.reset(hw);
3880                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3881                         dev_err(&adapter->pdev->dev, "failed to initialize "
3882                                 "because an unsupported SFP+ module type "
3883                                 "was detected.\n"
3884                                 "Reload the driver after installing a "
3885                                 "supported module.\n");
3886                         unregister_netdev(adapter->netdev);
3887                 } else {
3888                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3889                                 hw->phy.sfp_type);
3890                 }
3891                 /* don't need this routine any more */
3892                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3893         }
3894         return;
3895 reschedule:
3896         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3897                 mod_timer(&adapter->sfp_timer,
3898                           round_jiffies(jiffies + (2 * HZ)));
3899 }
3900
3901 /**
3902  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3903  * @adapter: board private structure to initialize
3904  *
3905  * ixgbe_sw_init initializes the Adapter private data structure.
3906  * Fields are initialized based on PCI device information and
3907  * OS network device settings (MTU size).
3908  **/
3909 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3910 {
3911         struct ixgbe_hw *hw = &adapter->hw;
3912         struct pci_dev *pdev = adapter->pdev;
3913         unsigned int rss;
3914 #ifdef CONFIG_IXGBE_DCB
3915         int j;
3916         struct tc_configuration *tc;
3917 #endif
3918
3919         /* PCI config space info */
3920
3921         hw->vendor_id = pdev->vendor;
3922         hw->device_id = pdev->device;
3923         hw->revision_id = pdev->revision;
3924         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3925         hw->subsystem_device_id = pdev->subsystem_device;
3926
3927         /* Set capability flags */
3928         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3929         adapter->ring_feature[RING_F_RSS].indices = rss;
3930         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3931         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3932         if (hw->mac.type == ixgbe_mac_82598EB) {
3933                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3934                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3935                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3936         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3937                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3938                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3939                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3940                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3941                 adapter->ring_feature[RING_F_FDIR].indices =
3942                                                          IXGBE_MAX_FDIR_INDICES;
3943                 adapter->atr_sample_rate = 20;
3944                 adapter->fdir_pballoc = 0;
3945 #ifdef IXGBE_FCOE
3946                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3947                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3948                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3949                 /* Default traffic class to use for FCoE */
3950                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3951 #endif /* IXGBE_FCOE */
3952         }
3953
3954 #ifdef CONFIG_IXGBE_DCB
3955         /* Configure DCB traffic classes */
3956         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3957                 tc = &adapter->dcb_cfg.tc_config[j];
3958                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3959                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3960                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3961                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3962                 tc->dcb_pfc = pfc_disabled;
3963         }
3964         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3965         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3966         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3967         adapter->dcb_cfg.pfc_mode_enable = false;
3968         adapter->dcb_cfg.round_robin_enable = false;
3969         adapter->dcb_set_bitmap = 0x00;
3970         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3971                            adapter->ring_feature[RING_F_DCB].indices);
3972
3973 #endif
3974
3975         /* default flow control settings */
3976         hw->fc.requested_mode = ixgbe_fc_full;
3977         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3978 #ifdef CONFIG_DCB
3979         adapter->last_lfc_mode = hw->fc.current_mode;
3980 #endif
3981         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3982         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3983         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3984         hw->fc.send_xon = true;
3985         hw->fc.disable_fc_autoneg = false;
3986
3987         /* enable itr by default in dynamic mode */
3988         adapter->rx_itr_setting = 1;
3989         adapter->rx_eitr_param = 20000;
3990         adapter->tx_itr_setting = 1;
3991         adapter->tx_eitr_param = 10000;
3992
3993         /* set defaults for eitr in MegaBytes */
3994         adapter->eitr_low = 10;
3995         adapter->eitr_high = 20;
3996
3997         /* set default ring sizes */
3998         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3999         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4000
4001         /* initialize eeprom parameters */
4002         if (ixgbe_init_eeprom_params_generic(hw)) {
4003                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4004                 return -EIO;
4005         }
4006
4007         /* enable rx csum by default */
4008         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4009
4010         set_bit(__IXGBE_DOWN, &adapter->state);
4011
4012         return 0;
4013 }
4014
4015 /**
4016  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4017  * @adapter: board private structure
4018  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4019  *
4020  * Return 0 on success, negative on failure
4021  **/
4022 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4023                              struct ixgbe_ring *tx_ring)
4024 {
4025         struct pci_dev *pdev = adapter->pdev;
4026         int size;
4027
4028         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4029         tx_ring->tx_buffer_info = vmalloc(size);
4030         if (!tx_ring->tx_buffer_info)
4031                 goto err;
4032         memset(tx_ring->tx_buffer_info, 0, size);
4033
4034         /* round up to nearest 4K */
4035         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4036         tx_ring->size = ALIGN(tx_ring->size, 4096);
4037
4038         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4039                                              &tx_ring->dma);
4040         if (!tx_ring->desc)
4041                 goto err;
4042
4043         tx_ring->next_to_use = 0;
4044         tx_ring->next_to_clean = 0;
4045         tx_ring->work_limit = tx_ring->count;
4046         return 0;
4047
4048 err:
4049         vfree(tx_ring->tx_buffer_info);
4050         tx_ring->tx_buffer_info = NULL;
4051         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4052                             "descriptor ring\n");
4053         return -ENOMEM;
4054 }
4055
4056 /**
4057  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4058  * @adapter: board private structure
4059  *
4060  * If this function returns with an error, then it's possible one or
4061  * more of the rings is populated (while the rest are not).  It is the
4062  * callers duty to clean those orphaned rings.
4063  *
4064  * Return 0 on success, negative on failure
4065  **/
4066 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4067 {
4068         int i, err = 0;
4069
4070         for (i = 0; i < adapter->num_tx_queues; i++) {
4071                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4072                 if (!err)
4073                         continue;
4074                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4075                 break;
4076         }
4077
4078         return err;
4079 }
4080
4081 /**
4082  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4083  * @adapter: board private structure
4084  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4085  *
4086  * Returns 0 on success, negative on failure
4087  **/
4088 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4089                              struct ixgbe_ring *rx_ring)
4090 {
4091         struct pci_dev *pdev = adapter->pdev;
4092         int size;
4093
4094         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4095         rx_ring->rx_buffer_info = vmalloc(size);
4096         if (!rx_ring->rx_buffer_info) {
4097                 DPRINTK(PROBE, ERR,
4098                         "vmalloc allocation failed for the rx desc ring\n");
4099                 goto alloc_failed;
4100         }
4101         memset(rx_ring->rx_buffer_info, 0, size);
4102
4103         /* Round up to nearest 4K */
4104         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4105         rx_ring->size = ALIGN(rx_ring->size, 4096);
4106
4107         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4108
4109         if (!rx_ring->desc) {
4110                 DPRINTK(PROBE, ERR,
4111                         "Memory allocation failed for the rx desc ring\n");
4112                 vfree(rx_ring->rx_buffer_info);
4113                 goto alloc_failed;
4114         }
4115
4116         rx_ring->next_to_clean = 0;
4117         rx_ring->next_to_use = 0;
4118
4119         return 0;
4120
4121 alloc_failed:
4122         return -ENOMEM;
4123 }
4124
4125 /**
4126  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4127  * @adapter: board private structure
4128  *
4129  * If this function returns with an error, then it's possible one or
4130  * more of the rings is populated (while the rest are not).  It is the
4131  * callers duty to clean those orphaned rings.
4132  *
4133  * Return 0 on success, negative on failure
4134  **/
4135
4136 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4137 {
4138         int i, err = 0;
4139
4140         for (i = 0; i < adapter->num_rx_queues; i++) {
4141                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4142                 if (!err)
4143                         continue;
4144                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4145                 break;
4146         }
4147
4148         return err;
4149 }
4150
4151 /**
4152  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4153  * @adapter: board private structure
4154  * @tx_ring: Tx descriptor ring for a specific queue
4155  *
4156  * Free all transmit software resources
4157  **/
4158 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4159                              struct ixgbe_ring *tx_ring)
4160 {
4161         struct pci_dev *pdev = adapter->pdev;
4162
4163         ixgbe_clean_tx_ring(adapter, tx_ring);
4164
4165         vfree(tx_ring->tx_buffer_info);
4166         tx_ring->tx_buffer_info = NULL;
4167
4168         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4169
4170         tx_ring->desc = NULL;
4171 }
4172
4173 /**
4174  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4175  * @adapter: board private structure
4176  *
4177  * Free all transmit software resources
4178  **/
4179 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4180 {
4181         int i;
4182
4183         for (i = 0; i < adapter->num_tx_queues; i++)
4184                 if (adapter->tx_ring[i].desc)
4185                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4186 }
4187
4188 /**
4189  * ixgbe_free_rx_resources - Free Rx Resources
4190  * @adapter: board private structure
4191  * @rx_ring: ring to clean the resources from
4192  *
4193  * Free all receive software resources
4194  **/
4195 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4196                              struct ixgbe_ring *rx_ring)
4197 {
4198         struct pci_dev *pdev = adapter->pdev;
4199
4200         ixgbe_clean_rx_ring(adapter, rx_ring);
4201
4202         vfree(rx_ring->rx_buffer_info);
4203         rx_ring->rx_buffer_info = NULL;
4204
4205         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4206
4207         rx_ring->desc = NULL;
4208 }
4209
4210 /**
4211  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4212  * @adapter: board private structure
4213  *
4214  * Free all receive software resources
4215  **/
4216 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4217 {
4218         int i;
4219
4220         for (i = 0; i < adapter->num_rx_queues; i++)
4221                 if (adapter->rx_ring[i].desc)
4222                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4223 }
4224
4225 /**
4226  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4227  * @netdev: network interface device structure
4228  * @new_mtu: new value for maximum frame size
4229  *
4230  * Returns 0 on success, negative on failure
4231  **/
4232 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4233 {
4234         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4235         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4236
4237         /* MTU < 68 is an error and causes problems on some kernels */
4238         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4239                 return -EINVAL;
4240
4241         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4242                 netdev->mtu, new_mtu);
4243         /* must set new MTU before calling down or up */
4244         netdev->mtu = new_mtu;
4245
4246         if (netif_running(netdev))
4247                 ixgbe_reinit_locked(adapter);
4248
4249         return 0;
4250 }
4251
4252 /**
4253  * ixgbe_open - Called when a network interface is made active
4254  * @netdev: network interface device structure
4255  *
4256  * Returns 0 on success, negative value on failure
4257  *
4258  * The open entry point is called when a network interface is made
4259  * active by the system (IFF_UP).  At this point all resources needed
4260  * for transmit and receive operations are allocated, the interrupt
4261  * handler is registered with the OS, the watchdog timer is started,
4262  * and the stack is notified that the interface is ready.
4263  **/
4264 static int ixgbe_open(struct net_device *netdev)
4265 {
4266         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4267         int err;
4268
4269         /* disallow open during test */
4270         if (test_bit(__IXGBE_TESTING, &adapter->state))
4271                 return -EBUSY;
4272
4273         netif_carrier_off(netdev);
4274
4275         /* allocate transmit descriptors */
4276         err = ixgbe_setup_all_tx_resources(adapter);
4277         if (err)
4278                 goto err_setup_tx;
4279
4280         /* allocate receive descriptors */
4281         err = ixgbe_setup_all_rx_resources(adapter);
4282         if (err)
4283                 goto err_setup_rx;
4284
4285         ixgbe_configure(adapter);
4286
4287         err = ixgbe_request_irq(adapter);
4288         if (err)
4289                 goto err_req_irq;
4290
4291         err = ixgbe_up_complete(adapter);
4292         if (err)
4293                 goto err_up;
4294
4295         netif_tx_start_all_queues(netdev);
4296
4297         return 0;
4298
4299 err_up:
4300         ixgbe_release_hw_control(adapter);
4301         ixgbe_free_irq(adapter);
4302 err_req_irq:
4303 err_setup_rx:
4304         ixgbe_free_all_rx_resources(adapter);
4305 err_setup_tx:
4306         ixgbe_free_all_tx_resources(adapter);
4307         ixgbe_reset(adapter);
4308
4309         return err;
4310 }
4311
4312 /**
4313  * ixgbe_close - Disables a network interface
4314  * @netdev: network interface device structure
4315  *
4316  * Returns 0, this is not allowed to fail
4317  *
4318  * The close entry point is called when an interface is de-activated
4319  * by the OS.  The hardware is still under the drivers control, but
4320  * needs to be disabled.  A global MAC reset is issued to stop the
4321  * hardware, and all transmit and receive resources are freed.
4322  **/
4323 static int ixgbe_close(struct net_device *netdev)
4324 {
4325         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4326
4327         ixgbe_down(adapter);
4328         ixgbe_free_irq(adapter);
4329
4330         ixgbe_free_all_tx_resources(adapter);
4331         ixgbe_free_all_rx_resources(adapter);
4332
4333         ixgbe_release_hw_control(adapter);
4334
4335         return 0;
4336 }
4337
4338 #ifdef CONFIG_PM
4339 static int ixgbe_resume(struct pci_dev *pdev)
4340 {
4341         struct net_device *netdev = pci_get_drvdata(pdev);
4342         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4343         u32 err;
4344
4345         pci_set_power_state(pdev, PCI_D0);
4346         pci_restore_state(pdev);
4347
4348         err = pci_enable_device_mem(pdev);
4349         if (err) {
4350                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4351                                 "suspend\n");
4352                 return err;
4353         }
4354         pci_set_master(pdev);
4355
4356         pci_wake_from_d3(pdev, false);
4357
4358         err = ixgbe_init_interrupt_scheme(adapter);
4359         if (err) {
4360                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4361                                 "device\n");
4362                 return err;
4363         }
4364
4365         ixgbe_reset(adapter);
4366
4367         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4368
4369         if (netif_running(netdev)) {
4370                 err = ixgbe_open(adapter->netdev);
4371                 if (err)
4372                         return err;
4373         }
4374
4375         netif_device_attach(netdev);
4376
4377         return 0;
4378 }
4379 #endif /* CONFIG_PM */
4380
4381 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4382 {
4383         struct net_device *netdev = pci_get_drvdata(pdev);
4384         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4385         struct ixgbe_hw *hw = &adapter->hw;
4386         u32 ctrl, fctrl;
4387         u32 wufc = adapter->wol;
4388 #ifdef CONFIG_PM
4389         int retval = 0;
4390 #endif
4391
4392         netif_device_detach(netdev);
4393
4394         if (netif_running(netdev)) {
4395                 ixgbe_down(adapter);
4396                 ixgbe_free_irq(adapter);
4397                 ixgbe_free_all_tx_resources(adapter);
4398                 ixgbe_free_all_rx_resources(adapter);
4399         }
4400         ixgbe_clear_interrupt_scheme(adapter);
4401
4402 #ifdef CONFIG_PM
4403         retval = pci_save_state(pdev);
4404         if (retval)
4405                 return retval;
4406
4407 #endif
4408         if (wufc) {
4409                 ixgbe_set_rx_mode(netdev);
4410
4411                 /* turn on all-multi mode if wake on multicast is enabled */
4412                 if (wufc & IXGBE_WUFC_MC) {
4413                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4414                         fctrl |= IXGBE_FCTRL_MPE;
4415                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4416                 }
4417
4418                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4419                 ctrl |= IXGBE_CTRL_GIO_DIS;
4420                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4421
4422                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4423         } else {
4424                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4425                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4426         }
4427
4428         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4429                 pci_wake_from_d3(pdev, true);
4430         else
4431                 pci_wake_from_d3(pdev, false);
4432
4433         *enable_wake = !!wufc;
4434
4435         ixgbe_release_hw_control(adapter);
4436
4437         pci_disable_device(pdev);
4438
4439         return 0;
4440 }
4441
4442 #ifdef CONFIG_PM
4443 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4444 {
4445         int retval;
4446         bool wake;
4447
4448         retval = __ixgbe_shutdown(pdev, &wake);
4449         if (retval)
4450                 return retval;
4451
4452         if (wake) {
4453                 pci_prepare_to_sleep(pdev);
4454         } else {
4455                 pci_wake_from_d3(pdev, false);
4456                 pci_set_power_state(pdev, PCI_D3hot);
4457         }
4458
4459         return 0;
4460 }
4461 #endif /* CONFIG_PM */
4462
4463 static void ixgbe_shutdown(struct pci_dev *pdev)
4464 {
4465         bool wake;
4466
4467         __ixgbe_shutdown(pdev, &wake);
4468
4469         if (system_state == SYSTEM_POWER_OFF) {
4470                 pci_wake_from_d3(pdev, wake);
4471                 pci_set_power_state(pdev, PCI_D3hot);
4472         }
4473 }
4474
4475 /**
4476  * ixgbe_update_stats - Update the board statistics counters.
4477  * @adapter: board private structure
4478  **/
4479 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4480 {
4481         struct net_device *netdev = adapter->netdev;
4482         struct ixgbe_hw *hw = &adapter->hw;
4483         u64 total_mpc = 0;
4484         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4485
4486         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4487                 u64 rsc_count = 0;
4488                 u64 rsc_flush = 0;
4489                 for (i = 0; i < 16; i++)
4490                         adapter->hw_rx_no_dma_resources +=
4491                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4492                 for (i = 0; i < adapter->num_rx_queues; i++) {
4493                         rsc_count += adapter->rx_ring[i].rsc_count;
4494                         rsc_flush += adapter->rx_ring[i].rsc_flush;
4495                 }
4496                 adapter->rsc_total_count = rsc_count;
4497                 adapter->rsc_total_flush = rsc_flush;
4498         }
4499
4500         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4501         for (i = 0; i < 8; i++) {
4502                 /* for packet buffers not used, the register should read 0 */
4503                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4504                 missed_rx += mpc;
4505                 adapter->stats.mpc[i] += mpc;
4506                 total_mpc += adapter->stats.mpc[i];
4507                 if (hw->mac.type == ixgbe_mac_82598EB)
4508                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4509                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4510                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4511                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4512                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4513                 if (hw->mac.type == ixgbe_mac_82599EB) {
4514                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4515                                                             IXGBE_PXONRXCNT(i));
4516                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4517                                                            IXGBE_PXOFFRXCNT(i));
4518                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4519                 } else {
4520                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4521                                                               IXGBE_PXONRXC(i));
4522                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4523                                                              IXGBE_PXOFFRXC(i));
4524                 }
4525                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4526                                                             IXGBE_PXONTXC(i));
4527                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4528                                                              IXGBE_PXOFFTXC(i));
4529         }
4530         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4531         /* work around hardware counting issue */
4532         adapter->stats.gprc -= missed_rx;
4533
4534         /* 82598 hardware only has a 32 bit counter in the high register */
4535         if (hw->mac.type == ixgbe_mac_82599EB) {
4536                 u64 tmp;
4537                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4538                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4539                 adapter->stats.gorc += (tmp << 32);
4540                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4541                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4542                 adapter->stats.gotc += (tmp << 32);
4543                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4544                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4545                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4546                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4547                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4548                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4549 #ifdef IXGBE_FCOE
4550                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4551                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4552                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4553                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4554                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4555                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4556 #endif /* IXGBE_FCOE */
4557         } else {
4558                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4559                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4560                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4561                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4562                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4563         }
4564         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4565         adapter->stats.bprc += bprc;
4566         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4567         if (hw->mac.type == ixgbe_mac_82598EB)
4568                 adapter->stats.mprc -= bprc;
4569         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4570         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4571         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4572         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4573         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4574         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4575         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4576         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4577         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4578         adapter->stats.lxontxc += lxon;
4579         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4580         adapter->stats.lxofftxc += lxoff;
4581         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4582         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4583         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4584         /*
4585          * 82598 errata - tx of flow control packets is included in tx counters
4586          */
4587         xon_off_tot = lxon + lxoff;
4588         adapter->stats.gptc -= xon_off_tot;
4589         adapter->stats.mptc -= xon_off_tot;
4590         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4591         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4592         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4593         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4594         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4595         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4596         adapter->stats.ptc64 -= xon_off_tot;
4597         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4598         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4599         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4600         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4601         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4602         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4603
4604         /* Fill out the OS statistics structure */
4605         netdev->stats.multicast = adapter->stats.mprc;
4606
4607         /* Rx Errors */
4608         netdev->stats.rx_errors = adapter->stats.crcerrs +
4609                                        adapter->stats.rlec;
4610         netdev->stats.rx_dropped = 0;
4611         netdev->stats.rx_length_errors = adapter->stats.rlec;
4612         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4613         netdev->stats.rx_missed_errors = total_mpc;
4614 }
4615
4616 /**
4617  * ixgbe_watchdog - Timer Call-back
4618  * @data: pointer to adapter cast into an unsigned long
4619  **/
4620 static void ixgbe_watchdog(unsigned long data)
4621 {
4622         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4623         struct ixgbe_hw *hw = &adapter->hw;
4624         u64 eics = 0;
4625         int i;
4626
4627         /*
4628          *  Do the watchdog outside of interrupt context due to the lovely
4629          * delays that some of the newer hardware requires
4630          */
4631
4632         if (test_bit(__IXGBE_DOWN, &adapter->state))
4633                 goto watchdog_short_circuit;
4634
4635         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4636                 /*
4637                  * for legacy and MSI interrupts don't set any bits
4638                  * that are enabled for EIAM, because this operation
4639                  * would set *both* EIMS and EICS for any bit in EIAM
4640                  */
4641                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4642                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4643                 goto watchdog_reschedule;
4644         }
4645
4646         /* get one bit for every active tx/rx interrupt vector */
4647         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4648                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4649                 if (qv->rxr_count || qv->txr_count)
4650                         eics |= ((u64)1 << i);
4651         }
4652
4653         /* Cause software interrupt to ensure rx rings are cleaned */
4654         ixgbe_irq_rearm_queues(adapter, eics);
4655
4656 watchdog_reschedule:
4657         /* Reset the timer */
4658         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4659
4660 watchdog_short_circuit:
4661         schedule_work(&adapter->watchdog_task);
4662 }
4663
4664 /**
4665  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4666  * @work: pointer to work_struct containing our data
4667  **/
4668 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4669 {
4670         struct ixgbe_adapter *adapter = container_of(work,
4671                                                      struct ixgbe_adapter,
4672                                                      multispeed_fiber_task);
4673         struct ixgbe_hw *hw = &adapter->hw;
4674         u32 autoneg;
4675         bool negotiation;
4676
4677         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4678         autoneg = hw->phy.autoneg_advertised;
4679         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4680                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4681         if (hw->mac.ops.setup_link)
4682                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4683         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4684         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4685 }
4686
4687 /**
4688  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4689  * @work: pointer to work_struct containing our data
4690  **/
4691 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4692 {
4693         struct ixgbe_adapter *adapter = container_of(work,
4694                                                      struct ixgbe_adapter,
4695                                                      sfp_config_module_task);
4696         struct ixgbe_hw *hw = &adapter->hw;
4697         u32 err;
4698
4699         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4700
4701         /* Time for electrical oscillations to settle down */
4702         msleep(100);
4703         err = hw->phy.ops.identify_sfp(hw);
4704
4705         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4706                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4707                         "an unsupported SFP+ module type was detected.\n"
4708                         "Reload the driver after installing a supported "
4709                         "module.\n");
4710                 unregister_netdev(adapter->netdev);
4711                 return;
4712         }
4713         hw->mac.ops.setup_sfp(hw);
4714
4715         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4716                 /* This will also work for DA Twinax connections */
4717                 schedule_work(&adapter->multispeed_fiber_task);
4718         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4719 }
4720
4721 /**
4722  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4723  * @work: pointer to work_struct containing our data
4724  **/
4725 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4726 {
4727         struct ixgbe_adapter *adapter = container_of(work,
4728                                                      struct ixgbe_adapter,
4729                                                      fdir_reinit_task);
4730         struct ixgbe_hw *hw = &adapter->hw;
4731         int i;
4732
4733         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4734                 for (i = 0; i < adapter->num_tx_queues; i++)
4735                         set_bit(__IXGBE_FDIR_INIT_DONE,
4736                                 &(adapter->tx_ring[i].reinit_state));
4737         } else {
4738                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4739                         "ignored adding FDIR ATR filters \n");
4740         }
4741         /* Done FDIR Re-initialization, enable transmits */
4742         netif_tx_start_all_queues(adapter->netdev);
4743 }
4744
4745 /**
4746  * ixgbe_watchdog_task - worker thread to bring link up
4747  * @work: pointer to work_struct containing our data
4748  **/
4749 static void ixgbe_watchdog_task(struct work_struct *work)
4750 {
4751         struct ixgbe_adapter *adapter = container_of(work,
4752                                                      struct ixgbe_adapter,
4753                                                      watchdog_task);
4754         struct net_device *netdev = adapter->netdev;
4755         struct ixgbe_hw *hw = &adapter->hw;
4756         u32 link_speed = adapter->link_speed;
4757         bool link_up = adapter->link_up;
4758         int i;
4759         struct ixgbe_ring *tx_ring;
4760         int some_tx_pending = 0;
4761
4762         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4763
4764         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4765                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4766                 if (link_up) {
4767 #ifdef CONFIG_DCB
4768                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4769                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4770                                         hw->mac.ops.fc_enable(hw, i);
4771                         } else {
4772                                 hw->mac.ops.fc_enable(hw, 0);
4773                         }
4774 #else
4775                         hw->mac.ops.fc_enable(hw, 0);
4776 #endif
4777                 }
4778
4779                 if (link_up ||
4780                     time_after(jiffies, (adapter->link_check_timeout +
4781                                          IXGBE_TRY_LINK_TIMEOUT))) {
4782                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4783                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4784                 }
4785                 adapter->link_up = link_up;
4786                 adapter->link_speed = link_speed;
4787         }
4788
4789         if (link_up) {
4790                 if (!netif_carrier_ok(netdev)) {
4791                         bool flow_rx, flow_tx;
4792
4793                         if (hw->mac.type == ixgbe_mac_82599EB) {
4794                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4795                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4796                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4797                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4798                         } else {
4799                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4800                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4801                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4802                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4803                         }
4804
4805                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4806                                "Flow Control: %s\n",
4807                                netdev->name,
4808                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4809                                 "10 Gbps" :
4810                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4811                                  "1 Gbps" : "unknown speed")),
4812                                ((flow_rx && flow_tx) ? "RX/TX" :
4813                                 (flow_rx ? "RX" :
4814                                 (flow_tx ? "TX" : "None"))));
4815
4816                         netif_carrier_on(netdev);
4817                 } else {
4818                         /* Force detection of hung controller */
4819                         adapter->detect_tx_hung = true;
4820                 }
4821         } else {
4822                 adapter->link_up = false;
4823                 adapter->link_speed = 0;
4824                 if (netif_carrier_ok(netdev)) {
4825                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4826                                netdev->name);
4827                         netif_carrier_off(netdev);
4828                 }
4829         }
4830
4831         if (!netif_carrier_ok(netdev)) {
4832                 for (i = 0; i < adapter->num_tx_queues; i++) {
4833                         tx_ring = &adapter->tx_ring[i];
4834                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4835                                 some_tx_pending = 1;
4836                                 break;
4837                         }
4838                 }
4839
4840                 if (some_tx_pending) {
4841                         /* We've lost link, so the controller stops DMA,
4842                          * but we've got queued Tx work that's never going
4843                          * to get done, so reset controller to flush Tx.
4844                          * (Do the reset outside of interrupt context).
4845                          */
4846                          schedule_work(&adapter->reset_task);
4847                 }
4848         }
4849
4850         ixgbe_update_stats(adapter);
4851         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4852 }
4853
4854 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4855                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4856                      u32 tx_flags, u8 *hdr_len)
4857 {
4858         struct ixgbe_adv_tx_context_desc *context_desc;
4859         unsigned int i;
4860         int err;
4861         struct ixgbe_tx_buffer *tx_buffer_info;
4862         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4863         u32 mss_l4len_idx, l4len;
4864
4865         if (skb_is_gso(skb)) {
4866                 if (skb_header_cloned(skb)) {
4867                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4868                         if (err)
4869                                 return err;
4870                 }
4871                 l4len = tcp_hdrlen(skb);
4872                 *hdr_len += l4len;
4873
4874                 if (skb->protocol == htons(ETH_P_IP)) {
4875                         struct iphdr *iph = ip_hdr(skb);
4876                         iph->tot_len = 0;
4877                         iph->check = 0;
4878                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4879                                                                  iph->daddr, 0,
4880                                                                  IPPROTO_TCP,
4881                                                                  0);
4882                         adapter->hw_tso_ctxt++;
4883                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4884                         ipv6_hdr(skb)->payload_len = 0;
4885                         tcp_hdr(skb)->check =
4886                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4887                                              &ipv6_hdr(skb)->daddr,
4888                                              0, IPPROTO_TCP, 0);
4889                         adapter->hw_tso6_ctxt++;
4890                 }
4891
4892                 i = tx_ring->next_to_use;
4893
4894                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4895                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4896
4897                 /* VLAN MACLEN IPLEN */
4898                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4899                         vlan_macip_lens |=
4900                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4901                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4902                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4903                 *hdr_len += skb_network_offset(skb);
4904                 vlan_macip_lens |=
4905                     (skb_transport_header(skb) - skb_network_header(skb));
4906                 *hdr_len +=
4907                     (skb_transport_header(skb) - skb_network_header(skb));
4908                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4909                 context_desc->seqnum_seed = 0;
4910
4911                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4912                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4913                                    IXGBE_ADVTXD_DTYP_CTXT);
4914
4915                 if (skb->protocol == htons(ETH_P_IP))
4916                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4917                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4918                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4919
4920                 /* MSS L4LEN IDX */
4921                 mss_l4len_idx =
4922                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4923                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4924                 /* use index 1 for TSO */
4925                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4926                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4927
4928                 tx_buffer_info->time_stamp = jiffies;
4929                 tx_buffer_info->next_to_watch = i;
4930
4931                 i++;
4932                 if (i == tx_ring->count)
4933                         i = 0;
4934                 tx_ring->next_to_use = i;
4935
4936                 return true;
4937         }
4938         return false;
4939 }
4940
4941 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4942                           struct ixgbe_ring *tx_ring,
4943                           struct sk_buff *skb, u32 tx_flags)
4944 {
4945         struct ixgbe_adv_tx_context_desc *context_desc;
4946         unsigned int i;
4947         struct ixgbe_tx_buffer *tx_buffer_info;
4948         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4949
4950         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4951             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4952                 i = tx_ring->next_to_use;
4953                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4954                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4955
4956                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4957                         vlan_macip_lens |=
4958                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4959                 vlan_macip_lens |= (skb_network_offset(skb) <<
4960                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4961                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4962                         vlan_macip_lens |= (skb_transport_header(skb) -
4963                                             skb_network_header(skb));
4964
4965                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4966                 context_desc->seqnum_seed = 0;
4967
4968                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4969                                     IXGBE_ADVTXD_DTYP_CTXT);
4970
4971                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4972                         switch (skb->protocol) {
4973                         case cpu_to_be16(ETH_P_IP):
4974                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4975                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4976                                         type_tucmd_mlhl |=
4977                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4978                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4979                                         type_tucmd_mlhl |=
4980                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4981                                 break;
4982                         case cpu_to_be16(ETH_P_IPV6):
4983                                 /* XXX what about other V6 headers?? */
4984                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4985                                         type_tucmd_mlhl |=
4986                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4987                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4988                                         type_tucmd_mlhl |=
4989                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4990                                 break;
4991                         default:
4992                                 if (unlikely(net_ratelimit())) {
4993                                         DPRINTK(PROBE, WARNING,
4994                                          "partial checksum but proto=%x!\n",
4995                                          skb->protocol);
4996                                 }
4997                                 break;
4998                         }
4999                 }
5000
5001                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5002                 /* use index zero for tx checksum offload */
5003                 context_desc->mss_l4len_idx = 0;
5004
5005                 tx_buffer_info->time_stamp = jiffies;
5006                 tx_buffer_info->next_to_watch = i;
5007
5008                 adapter->hw_csum_tx_good++;
5009                 i++;
5010                 if (i == tx_ring->count)
5011                         i = 0;
5012                 tx_ring->next_to_use = i;
5013
5014                 return true;
5015         }
5016
5017         return false;
5018 }
5019
5020 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5021                         struct ixgbe_ring *tx_ring,
5022                         struct sk_buff *skb, u32 tx_flags,
5023                         unsigned int first)
5024 {
5025         struct ixgbe_tx_buffer *tx_buffer_info;
5026         unsigned int len;
5027         unsigned int total = skb->len;
5028         unsigned int offset = 0, size, count = 0, i;
5029         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5030         unsigned int f;
5031         dma_addr_t *map;
5032
5033         i = tx_ring->next_to_use;
5034
5035         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5036                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5037                 return 0;
5038         }
5039
5040         map = skb_shinfo(skb)->dma_maps;
5041
5042         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5043                 /* excluding fcoe_crc_eof for FCoE */
5044                 total -= sizeof(struct fcoe_crc_eof);
5045
5046         len = min(skb_headlen(skb), total);
5047         while (len) {
5048                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5049                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5050
5051                 tx_buffer_info->length = size;
5052                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5053                 tx_buffer_info->time_stamp = jiffies;
5054                 tx_buffer_info->next_to_watch = i;
5055
5056                 len -= size;
5057                 total -= size;
5058                 offset += size;
5059                 count++;
5060
5061                 if (len) {
5062                         i++;
5063                         if (i == tx_ring->count)
5064                                 i = 0;
5065                 }
5066         }
5067
5068         for (f = 0; f < nr_frags; f++) {
5069                 struct skb_frag_struct *frag;
5070
5071                 frag = &skb_shinfo(skb)->frags[f];
5072                 len = min((unsigned int)frag->size, total);
5073                 offset = 0;
5074
5075                 while (len) {
5076                         i++;
5077                         if (i == tx_ring->count)
5078                                 i = 0;
5079
5080                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5081                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5082
5083                         tx_buffer_info->length = size;
5084                         tx_buffer_info->dma = map[f] + offset;
5085                         tx_buffer_info->time_stamp = jiffies;
5086                         tx_buffer_info->next_to_watch = i;
5087
5088                         len -= size;
5089                         total -= size;
5090                         offset += size;
5091                         count++;
5092                 }
5093                 if (total == 0)
5094                         break;
5095         }
5096
5097         tx_ring->tx_buffer_info[i].skb = skb;
5098         tx_ring->tx_buffer_info[first].next_to_watch = i;
5099
5100         return count;
5101 }
5102
5103 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5104                            struct ixgbe_ring *tx_ring,
5105                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5106 {
5107         union ixgbe_adv_tx_desc *tx_desc = NULL;
5108         struct ixgbe_tx_buffer *tx_buffer_info;
5109         u32 olinfo_status = 0, cmd_type_len = 0;
5110         unsigned int i;
5111         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5112
5113         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5114
5115         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5116
5117         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5118                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5119
5120         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5121                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5122
5123                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5124                                  IXGBE_ADVTXD_POPTS_SHIFT;
5125
5126                 /* use index 1 context for tso */
5127                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5128                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5129                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5130                                          IXGBE_ADVTXD_POPTS_SHIFT;
5131
5132         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5133                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5134                                  IXGBE_ADVTXD_POPTS_SHIFT;
5135
5136         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5137                 olinfo_status |= IXGBE_ADVTXD_CC;
5138                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5139                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5140                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5141         }
5142
5143         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5144
5145         i = tx_ring->next_to_use;
5146         while (count--) {
5147                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5148                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5149                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5150                 tx_desc->read.cmd_type_len =
5151                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5152                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5153                 i++;
5154                 if (i == tx_ring->count)
5155                         i = 0;
5156         }
5157
5158         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5159
5160         /*
5161          * Force memory writes to complete before letting h/w
5162          * know there are new descriptors to fetch.  (Only
5163          * applicable for weak-ordered memory model archs,
5164          * such as IA-64).
5165          */
5166         wmb();
5167
5168         tx_ring->next_to_use = i;
5169         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5170 }
5171
5172 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5173                       int queue, u32 tx_flags)
5174 {
5175         /* Right now, we support IPv4 only */
5176         struct ixgbe_atr_input atr_input;
5177         struct tcphdr *th;
5178         struct iphdr *iph = ip_hdr(skb);
5179         struct ethhdr *eth = (struct ethhdr *)skb->data;
5180         u16 vlan_id, src_port, dst_port, flex_bytes;
5181         u32 src_ipv4_addr, dst_ipv4_addr;
5182         u8 l4type = 0;
5183
5184         /* check if we're UDP or TCP */
5185         if (iph->protocol == IPPROTO_TCP) {
5186                 th = tcp_hdr(skb);
5187                 src_port = th->source;
5188                 dst_port = th->dest;
5189                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5190                 /* l4type IPv4 type is 0, no need to assign */
5191         } else {
5192                 /* Unsupported L4 header, just bail here */
5193                 return;
5194         }
5195
5196         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5197
5198         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5199                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5200         src_ipv4_addr = iph->saddr;
5201         dst_ipv4_addr = iph->daddr;
5202         flex_bytes = eth->h_proto;
5203
5204         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5205         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5206         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5207         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5208         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5209         /* src and dst are inverted, think how the receiver sees them */
5210         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5211         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5212
5213         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5214         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5215 }
5216
5217 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5218                                  struct ixgbe_ring *tx_ring, int size)
5219 {
5220         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5221
5222         netif_stop_subqueue(netdev, tx_ring->queue_index);
5223         /* Herbert's original patch had:
5224          *  smp_mb__after_netif_stop_queue();
5225          * but since that doesn't exist yet, just open code it. */
5226         smp_mb();
5227
5228         /* We need to check again in a case another CPU has just
5229          * made room available. */
5230         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5231                 return -EBUSY;
5232
5233         /* A reprieve! - use start_queue because it doesn't call schedule */
5234         netif_start_subqueue(netdev, tx_ring->queue_index);
5235         ++adapter->restart_queue;
5236         return 0;
5237 }
5238
5239 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5240                               struct ixgbe_ring *tx_ring, int size)
5241 {
5242         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5243                 return 0;
5244         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5245 }
5246
5247 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5248 {
5249         struct ixgbe_adapter *adapter = netdev_priv(dev);
5250
5251         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5252                 return smp_processor_id();
5253
5254         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5255                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5256
5257         return skb_tx_hash(dev, skb);
5258 }
5259
5260 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5261                                     struct net_device *netdev)
5262 {
5263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5264         struct ixgbe_ring *tx_ring;
5265         unsigned int first;
5266         unsigned int tx_flags = 0;
5267         u8 hdr_len = 0;
5268         int r_idx = 0, tso;
5269         int count = 0;
5270         unsigned int f;
5271
5272         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5273                 tx_flags |= vlan_tx_tag_get(skb);
5274                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5275                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5276                         tx_flags |= (skb->queue_mapping << 13);
5277                 }
5278                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5279                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5280         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5281                 if (skb->priority != TC_PRIO_CONTROL) {
5282                         tx_flags |= (skb->queue_mapping << 13);
5283                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5284                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5285                 } else {
5286                         skb->queue_mapping =
5287                                 adapter->ring_feature[RING_F_DCB].indices-1;
5288                 }
5289         }
5290
5291         r_idx = skb->queue_mapping;
5292         tx_ring = &adapter->tx_ring[r_idx];
5293
5294         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5295             (skb->protocol == htons(ETH_P_FCOE))) {
5296                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5297 #ifdef IXGBE_FCOE
5298                 r_idx = smp_processor_id();
5299                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5300                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5301                 tx_ring = &adapter->tx_ring[r_idx];
5302 #endif
5303         }
5304         /* four things can cause us to need a context descriptor */
5305         if (skb_is_gso(skb) ||
5306             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5307             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5308             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5309                 count++;
5310
5311         count += TXD_USE_COUNT(skb_headlen(skb));
5312         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5313                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5314
5315         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5316                 adapter->tx_busy++;
5317                 return NETDEV_TX_BUSY;
5318         }
5319
5320         first = tx_ring->next_to_use;
5321         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5322 #ifdef IXGBE_FCOE
5323                 /* setup tx offload for FCoE */
5324                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5325                 if (tso < 0) {
5326                         dev_kfree_skb_any(skb);
5327                         return NETDEV_TX_OK;
5328                 }
5329                 if (tso)
5330                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5331 #endif /* IXGBE_FCOE */
5332         } else {
5333                 if (skb->protocol == htons(ETH_P_IP))
5334                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5335                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5336                 if (tso < 0) {
5337                         dev_kfree_skb_any(skb);
5338                         return NETDEV_TX_OK;
5339                 }
5340
5341                 if (tso)
5342                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5343                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5344                          (skb->ip_summed == CHECKSUM_PARTIAL))
5345                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5346         }
5347
5348         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5349         if (count) {
5350                 /* add the ATR filter if ATR is on */
5351                 if (tx_ring->atr_sample_rate) {
5352                         ++tx_ring->atr_count;
5353                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5354                              test_bit(__IXGBE_FDIR_INIT_DONE,
5355                                       &tx_ring->reinit_state)) {
5356                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5357                                           tx_flags);
5358                                 tx_ring->atr_count = 0;
5359                         }
5360                 }
5361                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5362                                hdr_len);
5363                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5364
5365         } else {
5366                 dev_kfree_skb_any(skb);
5367                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5368                 tx_ring->next_to_use = first;
5369         }
5370
5371         return NETDEV_TX_OK;
5372 }
5373
5374 /**
5375  * ixgbe_get_stats - Get System Network Statistics
5376  * @netdev: network interface device structure
5377  *
5378  * Returns the address of the device statistics structure.
5379  * The statistics are actually updated from the timer callback.
5380  **/
5381 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5382 {
5383         /* only return the current stats */
5384         return &netdev->stats;
5385 }
5386
5387 /**
5388  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5389  * @netdev: network interface device structure
5390  * @p: pointer to an address structure
5391  *
5392  * Returns 0 on success, negative on failure
5393  **/
5394 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5395 {
5396         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5397         struct ixgbe_hw *hw = &adapter->hw;
5398         struct sockaddr *addr = p;
5399
5400         if (!is_valid_ether_addr(addr->sa_data))
5401                 return -EADDRNOTAVAIL;
5402
5403         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5404         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5405
5406         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5407
5408         return 0;
5409 }
5410
5411 static int
5412 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5413 {
5414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5415         struct ixgbe_hw *hw = &adapter->hw;
5416         u16 value;
5417         int rc;
5418
5419         if (prtad != hw->phy.mdio.prtad)
5420                 return -EINVAL;
5421         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5422         if (!rc)
5423                 rc = value;
5424         return rc;
5425 }
5426
5427 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5428                             u16 addr, u16 value)
5429 {
5430         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5431         struct ixgbe_hw *hw = &adapter->hw;
5432
5433         if (prtad != hw->phy.mdio.prtad)
5434                 return -EINVAL;
5435         return hw->phy.ops.write_reg(hw, addr, devad, value);
5436 }
5437
5438 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5439 {
5440         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5441
5442         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5443 }
5444
5445 /**
5446  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5447  * netdev->dev_addrs
5448  * @netdev: network interface device structure
5449  *
5450  * Returns non-zero on failure
5451  **/
5452 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5453 {
5454         int err = 0;
5455         struct ixgbe_adapter *adapter = netdev_priv(dev);
5456         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5457
5458         if (is_valid_ether_addr(mac->san_addr)) {
5459                 rtnl_lock();
5460                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5461                 rtnl_unlock();
5462         }
5463         return err;
5464 }
5465
5466 /**
5467  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5468  * netdev->dev_addrs
5469  * @netdev: network interface device structure
5470  *
5471  * Returns non-zero on failure
5472  **/
5473 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5474 {
5475         int err = 0;
5476         struct ixgbe_adapter *adapter = netdev_priv(dev);
5477         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5478
5479         if (is_valid_ether_addr(mac->san_addr)) {
5480                 rtnl_lock();
5481                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5482                 rtnl_unlock();
5483         }
5484         return err;
5485 }
5486
5487 #ifdef CONFIG_NET_POLL_CONTROLLER
5488 /*
5489  * Polling 'interrupt' - used by things like netconsole to send skbs
5490  * without having to re-enable interrupts. It's not called while
5491  * the interrupt routine is executing.
5492  */
5493 static void ixgbe_netpoll(struct net_device *netdev)
5494 {
5495         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5496         int i;
5497
5498         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5499         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5500                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5501                 for (i = 0; i < num_q_vectors; i++) {
5502                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5503                         ixgbe_msix_clean_many(0, q_vector);
5504                 }
5505         } else {
5506                 ixgbe_intr(adapter->pdev->irq, netdev);
5507         }
5508         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5509 }
5510 #endif
5511
5512 static const struct net_device_ops ixgbe_netdev_ops = {
5513         .ndo_open               = ixgbe_open,
5514         .ndo_stop               = ixgbe_close,
5515         .ndo_start_xmit         = ixgbe_xmit_frame,
5516         .ndo_select_queue       = ixgbe_select_queue,
5517         .ndo_get_stats          = ixgbe_get_stats,
5518         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5519         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5520         .ndo_validate_addr      = eth_validate_addr,
5521         .ndo_set_mac_address    = ixgbe_set_mac,
5522         .ndo_change_mtu         = ixgbe_change_mtu,
5523         .ndo_tx_timeout         = ixgbe_tx_timeout,
5524         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5525         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5526         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5527         .ndo_do_ioctl           = ixgbe_ioctl,
5528 #ifdef CONFIG_NET_POLL_CONTROLLER
5529         .ndo_poll_controller    = ixgbe_netpoll,
5530 #endif
5531 #ifdef IXGBE_FCOE
5532         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5533         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5534         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5535         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5536         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5537 #endif /* IXGBE_FCOE */
5538 };
5539
5540 /**
5541  * ixgbe_probe - Device Initialization Routine
5542  * @pdev: PCI device information struct
5543  * @ent: entry in ixgbe_pci_tbl
5544  *
5545  * Returns 0 on success, negative on failure
5546  *
5547  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5548  * The OS initialization, configuring of the adapter private structure,
5549  * and a hardware reset occur.
5550  **/
5551 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5552                                  const struct pci_device_id *ent)
5553 {
5554         struct net_device *netdev;
5555         struct ixgbe_adapter *adapter = NULL;
5556         struct ixgbe_hw *hw;
5557         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5558         static int cards_found;
5559         int i, err, pci_using_dac;
5560 #ifdef IXGBE_FCOE
5561         u16 device_caps;
5562 #endif
5563         u32 part_num, eec;
5564
5565         err = pci_enable_device_mem(pdev);
5566         if (err)
5567                 return err;
5568
5569         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5570             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5571                 pci_using_dac = 1;
5572         } else {
5573                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5574                 if (err) {
5575                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5576                         if (err) {
5577                                 dev_err(&pdev->dev, "No usable DMA "
5578                                         "configuration, aborting\n");
5579                                 goto err_dma;
5580                         }
5581                 }
5582                 pci_using_dac = 0;
5583         }
5584
5585         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5586                                            IORESOURCE_MEM), ixgbe_driver_name);
5587         if (err) {
5588                 dev_err(&pdev->dev,
5589                         "pci_request_selected_regions failed 0x%x\n", err);
5590                 goto err_pci_reg;
5591         }
5592
5593         pci_enable_pcie_error_reporting(pdev);
5594
5595         pci_set_master(pdev);
5596         pci_save_state(pdev);
5597
5598         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5599         if (!netdev) {
5600                 err = -ENOMEM;
5601                 goto err_alloc_etherdev;
5602         }
5603
5604         SET_NETDEV_DEV(netdev, &pdev->dev);
5605
5606         pci_set_drvdata(pdev, netdev);
5607         adapter = netdev_priv(netdev);
5608
5609         adapter->netdev = netdev;
5610         adapter->pdev = pdev;
5611         hw = &adapter->hw;
5612         hw->back = adapter;
5613         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5614
5615         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5616                               pci_resource_len(pdev, 0));
5617         if (!hw->hw_addr) {
5618                 err = -EIO;
5619                 goto err_ioremap;
5620         }
5621
5622         for (i = 1; i <= 5; i++) {
5623                 if (pci_resource_len(pdev, i) == 0)
5624                         continue;
5625         }
5626
5627         netdev->netdev_ops = &ixgbe_netdev_ops;
5628         ixgbe_set_ethtool_ops(netdev);
5629         netdev->watchdog_timeo = 5 * HZ;
5630         strcpy(netdev->name, pci_name(pdev));
5631
5632         adapter->bd_number = cards_found;
5633
5634         /* Setup hw api */
5635         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5636         hw->mac.type  = ii->mac;
5637
5638         /* EEPROM */
5639         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5640         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5641         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5642         if (!(eec & (1 << 8)))
5643                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5644
5645         /* PHY */
5646         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5647         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5648         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5649         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5650         hw->phy.mdio.mmds = 0;
5651         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5652         hw->phy.mdio.dev = netdev;
5653         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5654         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5655
5656         /* set up this timer and work struct before calling get_invariants
5657          * which might start the timer
5658          */
5659         init_timer(&adapter->sfp_timer);
5660         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5661         adapter->sfp_timer.data = (unsigned long) adapter;
5662
5663         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5664
5665         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5666         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5667
5668         /* a new SFP+ module arrival, called from GPI SDP2 context */
5669         INIT_WORK(&adapter->sfp_config_module_task,
5670                   ixgbe_sfp_config_module_task);
5671
5672         ii->get_invariants(hw);
5673
5674         /* setup the private structure */
5675         err = ixgbe_sw_init(adapter);
5676         if (err)
5677                 goto err_sw_init;
5678
5679         /*
5680          * If there is a fan on this device and it has failed log the
5681          * failure.
5682          */
5683         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5684                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5685                 if (esdp & IXGBE_ESDP_SDP1)
5686                         DPRINTK(PROBE, CRIT,
5687                                 "Fan has stopped, replace the adapter\n");
5688         }
5689
5690         /* reset_hw fills in the perm_addr as well */
5691         err = hw->mac.ops.reset_hw(hw);
5692         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5693             hw->mac.type == ixgbe_mac_82598EB) {
5694                 /*
5695                  * Start a kernel thread to watch for a module to arrive.
5696                  * Only do this for 82598, since 82599 will generate
5697                  * interrupts on module arrival.
5698                  */
5699                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5700                 mod_timer(&adapter->sfp_timer,
5701                           round_jiffies(jiffies + (2 * HZ)));
5702                 err = 0;
5703         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5704                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5705                         "an unsupported SFP+ module type was detected.\n"
5706                         "Reload the driver after installing a supported "
5707                         "module.\n");
5708                 goto err_sw_init;
5709         } else if (err) {
5710                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5711                 goto err_sw_init;
5712         }
5713
5714         netdev->features = NETIF_F_SG |
5715                            NETIF_F_IP_CSUM |
5716                            NETIF_F_HW_VLAN_TX |
5717                            NETIF_F_HW_VLAN_RX |
5718                            NETIF_F_HW_VLAN_FILTER;
5719
5720         netdev->features |= NETIF_F_IPV6_CSUM;
5721         netdev->features |= NETIF_F_TSO;
5722         netdev->features |= NETIF_F_TSO6;
5723         netdev->features |= NETIF_F_GRO;
5724
5725         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5726                 netdev->features |= NETIF_F_SCTP_CSUM;
5727
5728         netdev->vlan_features |= NETIF_F_TSO;
5729         netdev->vlan_features |= NETIF_F_TSO6;
5730         netdev->vlan_features |= NETIF_F_IP_CSUM;
5731         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5732         netdev->vlan_features |= NETIF_F_SG;
5733
5734         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5735                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5736
5737 #ifdef CONFIG_IXGBE_DCB
5738         netdev->dcbnl_ops = &dcbnl_ops;
5739 #endif
5740
5741 #ifdef IXGBE_FCOE
5742         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5743                 if (hw->mac.ops.get_device_caps) {
5744                         hw->mac.ops.get_device_caps(hw, &device_caps);
5745                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5746                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5747                 }
5748         }
5749 #endif /* IXGBE_FCOE */
5750         if (pci_using_dac)
5751                 netdev->features |= NETIF_F_HIGHDMA;
5752
5753         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5754                 netdev->features |= NETIF_F_LRO;
5755
5756         /* make sure the EEPROM is good */
5757         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5758                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5759                 err = -EIO;
5760                 goto err_eeprom;
5761         }
5762
5763         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5764         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5765
5766         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5767                 dev_err(&pdev->dev, "invalid MAC address\n");
5768                 err = -EIO;
5769                 goto err_eeprom;
5770         }
5771
5772         init_timer(&adapter->watchdog_timer);
5773         adapter->watchdog_timer.function = &ixgbe_watchdog;
5774         adapter->watchdog_timer.data = (unsigned long)adapter;
5775
5776         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5777         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5778
5779         err = ixgbe_init_interrupt_scheme(adapter);
5780         if (err)
5781                 goto err_sw_init;
5782
5783         switch (pdev->device) {
5784         case IXGBE_DEV_ID_82599_KX4:
5785                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5786                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5787                 /* Enable ACPI wakeup in GRC */
5788                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5789                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5790                 break;
5791         default:
5792                 adapter->wol = 0;
5793                 break;
5794         }
5795         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5796
5797         /* pick up the PCI bus settings for reporting later */
5798         hw->mac.ops.get_bus_info(hw);
5799
5800         /* print bus type/speed/width info */
5801         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5802                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5803                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5804                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5805                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5806                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5807                  "Unknown"),
5808                 netdev->dev_addr);
5809         ixgbe_read_pba_num_generic(hw, &part_num);
5810         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5811                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5812                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5813                          (part_num >> 8), (part_num & 0xff));
5814         else
5815                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5816                          hw->mac.type, hw->phy.type,
5817                          (part_num >> 8), (part_num & 0xff));
5818
5819         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5820                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5821                          "this card is not sufficient for optimal "
5822                          "performance.\n");
5823                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5824                          "PCI-Express slot is required.\n");
5825         }
5826
5827         /* save off EEPROM version number */
5828         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5829
5830         /* reset the hardware with the new settings */
5831         err = hw->mac.ops.start_hw(hw);
5832
5833         if (err == IXGBE_ERR_EEPROM_VERSION) {
5834                 /* We are running on a pre-production device, log a warning */
5835                 dev_warn(&pdev->dev, "This device is a pre-production "
5836                          "adapter/LOM.  Please be aware there may be issues "
5837                          "associated with your hardware.  If you are "
5838                          "experiencing problems please contact your Intel or "
5839                          "hardware representative who provided you with this "
5840                          "hardware.\n");
5841         }
5842         strcpy(netdev->name, "eth%d");
5843         err = register_netdev(netdev);
5844         if (err)
5845                 goto err_register;
5846
5847         /* carrier off reporting is important to ethtool even BEFORE open */
5848         netif_carrier_off(netdev);
5849
5850         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5851             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5852                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5853
5854 #ifdef CONFIG_IXGBE_DCA
5855         if (dca_add_requester(&pdev->dev) == 0) {
5856                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5857                 ixgbe_setup_dca(adapter);
5858         }
5859 #endif
5860         /* add san mac addr to netdev */
5861         ixgbe_add_sanmac_netdev(netdev);
5862
5863         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5864         cards_found++;
5865         return 0;
5866
5867 err_register:
5868         ixgbe_release_hw_control(adapter);
5869         ixgbe_clear_interrupt_scheme(adapter);
5870 err_sw_init:
5871 err_eeprom:
5872         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5873         del_timer_sync(&adapter->sfp_timer);
5874         cancel_work_sync(&adapter->sfp_task);
5875         cancel_work_sync(&adapter->multispeed_fiber_task);
5876         cancel_work_sync(&adapter->sfp_config_module_task);
5877         iounmap(hw->hw_addr);
5878 err_ioremap:
5879         free_netdev(netdev);
5880 err_alloc_etherdev:
5881         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5882                                      IORESOURCE_MEM));
5883 err_pci_reg:
5884 err_dma:
5885         pci_disable_device(pdev);
5886         return err;
5887 }
5888
5889 /**
5890  * ixgbe_remove - Device Removal Routine
5891  * @pdev: PCI device information struct
5892  *
5893  * ixgbe_remove is called by the PCI subsystem to alert the driver
5894  * that it should release a PCI device.  The could be caused by a
5895  * Hot-Plug event, or because the driver is going to be removed from
5896  * memory.
5897  **/
5898 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5899 {
5900         struct net_device *netdev = pci_get_drvdata(pdev);
5901         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5902
5903         set_bit(__IXGBE_DOWN, &adapter->state);
5904         /* clear the module not found bit to make sure the worker won't
5905          * reschedule
5906          */
5907         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5908         del_timer_sync(&adapter->watchdog_timer);
5909
5910         del_timer_sync(&adapter->sfp_timer);
5911         cancel_work_sync(&adapter->watchdog_task);
5912         cancel_work_sync(&adapter->sfp_task);
5913         cancel_work_sync(&adapter->multispeed_fiber_task);
5914         cancel_work_sync(&adapter->sfp_config_module_task);
5915         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5916             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5917                 cancel_work_sync(&adapter->fdir_reinit_task);
5918         flush_scheduled_work();
5919
5920 #ifdef CONFIG_IXGBE_DCA
5921         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5922                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5923                 dca_remove_requester(&pdev->dev);
5924                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5925         }
5926
5927 #endif
5928 #ifdef IXGBE_FCOE
5929         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5930                 ixgbe_cleanup_fcoe(adapter);
5931
5932 #endif /* IXGBE_FCOE */
5933
5934         /* remove the added san mac */
5935         ixgbe_del_sanmac_netdev(netdev);
5936
5937         if (netdev->reg_state == NETREG_REGISTERED)
5938                 unregister_netdev(netdev);
5939
5940         ixgbe_clear_interrupt_scheme(adapter);
5941
5942         ixgbe_release_hw_control(adapter);
5943
5944         iounmap(adapter->hw.hw_addr);
5945         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5946                                      IORESOURCE_MEM));
5947
5948         DPRINTK(PROBE, INFO, "complete\n");
5949
5950         free_netdev(netdev);
5951
5952         pci_disable_pcie_error_reporting(pdev);
5953
5954         pci_disable_device(pdev);
5955 }
5956
5957 /**
5958  * ixgbe_io_error_detected - called when PCI error is detected
5959  * @pdev: Pointer to PCI device
5960  * @state: The current pci connection state
5961  *
5962  * This function is called after a PCI bus error affecting
5963  * this device has been detected.
5964  */
5965 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5966                                                 pci_channel_state_t state)
5967 {
5968         struct net_device *netdev = pci_get_drvdata(pdev);
5969         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5970
5971         netif_device_detach(netdev);
5972
5973         if (state == pci_channel_io_perm_failure)
5974                 return PCI_ERS_RESULT_DISCONNECT;
5975
5976         if (netif_running(netdev))
5977                 ixgbe_down(adapter);
5978         pci_disable_device(pdev);
5979
5980         /* Request a slot reset. */
5981         return PCI_ERS_RESULT_NEED_RESET;
5982 }
5983
5984 /**
5985  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5986  * @pdev: Pointer to PCI device
5987  *
5988  * Restart the card from scratch, as if from a cold-boot.
5989  */
5990 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5991 {
5992         struct net_device *netdev = pci_get_drvdata(pdev);
5993         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5994         pci_ers_result_t result;
5995         int err;
5996
5997         if (pci_enable_device_mem(pdev)) {
5998                 DPRINTK(PROBE, ERR,
5999                         "Cannot re-enable PCI device after reset.\n");
6000                 result = PCI_ERS_RESULT_DISCONNECT;
6001         } else {
6002                 pci_set_master(pdev);
6003                 pci_restore_state(pdev);
6004                 pci_save_state(pdev);
6005
6006                 pci_wake_from_d3(pdev, false);
6007
6008                 ixgbe_reset(adapter);
6009                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6010                 result = PCI_ERS_RESULT_RECOVERED;
6011         }
6012
6013         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6014         if (err) {
6015                 dev_err(&pdev->dev,
6016                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6017                 /* non-fatal, continue */
6018         }
6019
6020         return result;
6021 }
6022
6023 /**
6024  * ixgbe_io_resume - called when traffic can start flowing again.
6025  * @pdev: Pointer to PCI device
6026  *
6027  * This callback is called when the error recovery driver tells us that
6028  * its OK to resume normal operation.
6029  */
6030 static void ixgbe_io_resume(struct pci_dev *pdev)
6031 {
6032         struct net_device *netdev = pci_get_drvdata(pdev);
6033         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6034
6035         if (netif_running(netdev)) {
6036                 if (ixgbe_up(adapter)) {
6037                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6038                         return;
6039                 }
6040         }
6041
6042         netif_device_attach(netdev);
6043 }
6044
6045 static struct pci_error_handlers ixgbe_err_handler = {
6046         .error_detected = ixgbe_io_error_detected,
6047         .slot_reset = ixgbe_io_slot_reset,
6048         .resume = ixgbe_io_resume,
6049 };
6050
6051 static struct pci_driver ixgbe_driver = {
6052         .name     = ixgbe_driver_name,
6053         .id_table = ixgbe_pci_tbl,
6054         .probe    = ixgbe_probe,
6055         .remove   = __devexit_p(ixgbe_remove),
6056 #ifdef CONFIG_PM
6057         .suspend  = ixgbe_suspend,
6058         .resume   = ixgbe_resume,
6059 #endif
6060         .shutdown = ixgbe_shutdown,
6061         .err_handler = &ixgbe_err_handler
6062 };
6063
6064 /**
6065  * ixgbe_init_module - Driver Registration Routine
6066  *
6067  * ixgbe_init_module is the first routine called when the driver is
6068  * loaded. All it does is register with the PCI subsystem.
6069  **/
6070 static int __init ixgbe_init_module(void)
6071 {
6072         int ret;
6073         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6074                ixgbe_driver_string, ixgbe_driver_version);
6075
6076         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6077
6078 #ifdef CONFIG_IXGBE_DCA
6079         dca_register_notify(&dca_notifier);
6080 #endif
6081
6082         ret = pci_register_driver(&ixgbe_driver);
6083         return ret;
6084 }
6085
6086 module_init(ixgbe_init_module);
6087
6088 /**
6089  * ixgbe_exit_module - Driver Exit Cleanup Routine
6090  *
6091  * ixgbe_exit_module is called just before the driver is removed
6092  * from memory.
6093  **/
6094 static void __exit ixgbe_exit_module(void)
6095 {
6096 #ifdef CONFIG_IXGBE_DCA
6097         dca_unregister_notify(&dca_notifier);
6098 #endif
6099         pci_unregister_driver(&ixgbe_driver);
6100 }
6101
6102 #ifdef CONFIG_IXGBE_DCA
6103 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6104                             void *p)
6105 {
6106         int ret_val;
6107
6108         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6109                                          __ixgbe_notify_dca);
6110
6111         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6112 }
6113
6114 #endif /* CONFIG_IXGBE_DCA */
6115 #ifdef DEBUG
6116 /**
6117  * ixgbe_get_hw_dev_name - return device name string
6118  * used by hardware layer to print debugging information
6119  **/
6120 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6121 {
6122         struct ixgbe_adapter *adapter = hw->back;
6123         return adapter->netdev->name;
6124 }
6125
6126 #endif
6127 module_exit(ixgbe_exit_module);
6128
6129 /* ixgbe_main.c */