1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "3.2.9-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
60 static const struct ixgbe_info *ixgbe_info_tbl[] = {
61 [board_82598] = &ixgbe_82598_info,
62 [board_82599] = &ixgbe_82599_info,
63 [board_X540] = &ixgbe_X540_info,
66 /* ixgbe_pci_tbl - PCI Device ID Table
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
74 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
124 /* required last entry */
127 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
129 #ifdef CONFIG_IXGBE_DCA
130 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
132 static struct notifier_block dca_notifier = {
133 .notifier_call = ixgbe_notify_dca,
139 #ifdef CONFIG_PCI_IOV
140 static unsigned int max_vfs;
141 module_param(max_vfs, uint, 0);
142 MODULE_PARM_DESC(max_vfs,
143 "Maximum number of virtual functions to allocate per physical function");
144 #endif /* CONFIG_PCI_IOV */
146 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_VERSION);
151 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
153 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
155 struct ixgbe_hw *hw = &adapter->hw;
160 #ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter->pdev);
165 /* turn off device IOV mode */
166 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
167 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
169 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
170 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
173 /* set default pool back to 0 */
174 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
175 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
178 /* take a breather then clean up driver data */
181 kfree(adapter->vfinfo);
182 adapter->vfinfo = NULL;
184 adapter->num_vfs = 0;
185 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
188 struct ixgbe_reg_info {
193 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
195 /* General Registers */
196 {IXGBE_CTRL, "CTRL"},
197 {IXGBE_STATUS, "STATUS"},
198 {IXGBE_CTRL_EXT, "CTRL_EXT"},
200 /* Interrupt Registers */
201 {IXGBE_EICR, "EICR"},
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
221 /* List Terminator */
227 * ixgbe_regdump - register printout routine
229 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
235 switch (reginfo->ofs) {
236 case IXGBE_SRRCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
240 case IXGBE_DCA_RXCTRL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
256 case IXGBE_RXDCTL(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
288 case IXGBE_TXDCTL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
293 pr_info("%-15s %08x\n", reginfo->name,
294 IXGBE_READ_REG(hw, reginfo->ofs));
298 for (i = 0; i < 8; i++) {
299 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
300 pr_err("%-15s", rname);
301 for (j = 0; j < 8; j++)
302 pr_cont(" %08x", regs[i*8+j]);
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
311 static void ixgbe_dump(struct ixgbe_adapter *adapter)
313 struct net_device *netdev = adapter->netdev;
314 struct ixgbe_hw *hw = &adapter->hw;
315 struct ixgbe_reg_info *reginfo;
317 struct ixgbe_ring *tx_ring;
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 union ixgbe_adv_tx_desc *tx_desc;
320 struct my_u0 { u64 a; u64 b; } *u0;
321 struct ixgbe_ring *rx_ring;
322 union ixgbe_adv_rx_desc *rx_desc;
323 struct ixgbe_rx_buffer *rx_buffer_info;
327 if (!netif_msg_hw(adapter))
330 /* Print netdevice Info */
332 dev_info(&adapter->pdev->dev, "Net device Info\n");
333 pr_info("Device Name state "
334 "trans_start last_rx\n");
335 pr_info("%-15s %016lX %016lX %016lX\n",
342 /* Print Registers */
343 dev_info(&adapter->pdev->dev, "Register Dump\n");
344 pr_info(" Register Name Value\n");
345 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
346 reginfo->name; reginfo++) {
347 ixgbe_regdump(hw, reginfo);
350 /* Print TX Ring Summary */
351 if (!netdev || !netif_running(netdev))
354 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
356 for (n = 0; n < adapter->num_tx_queues; n++) {
357 tx_ring = adapter->tx_ring[n];
359 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
361 n, tx_ring->next_to_use, tx_ring->next_to_clean,
362 (u64)tx_buffer_info->dma,
363 tx_buffer_info->length,
364 tx_buffer_info->next_to_watch,
365 (u64)tx_buffer_info->time_stamp);
369 if (!netif_msg_tx_done(adapter))
370 goto rx_ring_summary;
372 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
374 /* Transmit Descriptor Formats
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
385 for (n = 0; n < adapter->num_tx_queues; n++) {
386 tx_ring = adapter->tx_ring[n];
387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
397 u0 = (struct my_u0 *)tx_desc;
398 pr_info("T [0x%03X] %016llX %016llX %016llX"
399 " %04X %3X %016llX %p", i,
402 (u64)tx_buffer_info->dma,
403 tx_buffer_info->length,
404 tx_buffer_info->next_to_watch,
405 (u64)tx_buffer_info->time_stamp,
406 tx_buffer_info->skb);
407 if (i == tx_ring->next_to_use &&
408 i == tx_ring->next_to_clean)
410 else if (i == tx_ring->next_to_use)
412 else if (i == tx_ring->next_to_clean)
417 if (netif_msg_pktdata(adapter) &&
418 tx_buffer_info->dma != 0)
419 print_hex_dump(KERN_INFO, "",
420 DUMP_PREFIX_ADDRESS, 16, 1,
421 phys_to_virt(tx_buffer_info->dma),
422 tx_buffer_info->length, true);
426 /* Print RX Rings Summary */
428 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
429 pr_info("Queue [NTU] [NTC]\n");
430 for (n = 0; n < adapter->num_rx_queues; n++) {
431 rx_ring = adapter->rx_ring[n];
432 pr_info("%5d %5X %5X\n",
433 n, rx_ring->next_to_use, rx_ring->next_to_clean);
437 if (!netif_msg_rx_status(adapter))
440 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
442 /* Advanced Receive Descriptor (Read) Format
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
451 * Advanced Receive Descriptor (Write-Back) Format
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
462 for (n = 0; n < adapter->num_rx_queues; n++) {
463 rx_ring = adapter->rx_ring[n];
464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
474 for (i = 0; i < rx_ring->count; i++) {
475 rx_buffer_info = &rx_ring->rx_buffer_info[i];
476 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
477 u0 = (struct my_u0 *)rx_desc;
478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
479 if (staterr & IXGBE_RXD_STAT_DD) {
480 /* Descriptor Done */
481 pr_info("RWB[0x%03X] %016llX "
482 "%016llX ---------------- %p", i,
485 rx_buffer_info->skb);
487 pr_info("R [0x%03X] %016llX "
488 "%016llX %016llX %p", i,
491 (u64)rx_buffer_info->dma,
492 rx_buffer_info->skb);
494 if (netif_msg_pktdata(adapter)) {
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(rx_buffer_info->dma),
498 rx_ring->rx_buf_len, true);
500 if (rx_ring->rx_buf_len
501 < IXGBE_RXBUFFER_2048)
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS, 16, 1,
505 rx_buffer_info->page_dma +
506 rx_buffer_info->page_offset
512 if (i == rx_ring->next_to_use)
514 else if (i == rx_ring->next_to_clean)
526 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
530 /* Let firmware take over control of h/w */
531 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
533 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
536 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
540 /* Let firmware know the driver has taken over */
541 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
543 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
554 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
555 u8 queue, u8 msix_vector)
558 struct ixgbe_hw *hw = &adapter->hw;
559 switch (hw->mac.type) {
560 case ixgbe_mac_82598EB:
561 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
564 index = (((direction * 64) + queue) >> 2) & 0x1F;
565 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
566 ivar &= ~(0xFF << (8 * (queue & 0x3)));
567 ivar |= (msix_vector << (8 * (queue & 0x3)));
568 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
570 case ixgbe_mac_82599EB:
572 if (direction == -1) {
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((queue & 1) * 8);
576 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
582 /* tx or rx causes */
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 index = ((16 * (queue & 1)) + (8 * direction));
585 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
586 ivar &= ~(0xFF << index);
587 ivar |= (msix_vector << index);
588 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
596 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
601 switch (adapter->hw.mac.type) {
602 case ixgbe_mac_82598EB:
603 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
606 case ixgbe_mac_82599EB:
608 mask = (qmask & 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
610 mask = (qmask >> 32);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
618 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
619 struct ixgbe_tx_buffer *tx_buffer_info)
621 if (tx_buffer_info->dma) {
622 if (tx_buffer_info->mapped_as_page)
623 dma_unmap_page(tx_ring->dev,
625 tx_buffer_info->length,
628 dma_unmap_single(tx_ring->dev,
630 tx_buffer_info->length,
632 tx_buffer_info->dma = 0;
634 if (tx_buffer_info->skb) {
635 dev_kfree_skb_any(tx_buffer_info->skb);
636 tx_buffer_info->skb = NULL;
638 tx_buffer_info->time_stamp = 0;
639 /* tx_buffer_info must be completely set up in the transmit path */
643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
647 * Helper function to determine the traffic index for a paticular
650 * Returns : a tc index for use in range 0-7, or 0-3
652 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
655 int dcb_i = netdev_get_num_tc(adapter->netdev);
657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
661 /* check valid range */
662 if (reg_idx >= adapter->hw.mac.max_tx_queues)
665 switch (adapter->hw.mac.type) {
666 case ixgbe_mac_82598EB:
670 if (dcb_i != 4 && dcb_i != 8)
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
675 IXGBE_FLAG_VMDQ_ENABLED)) {
676 tc = reg_idx & (dcb_i - 1);
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
691 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
692 tc >>= 9 - (reg_idx >> 5);
698 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
700 struct ixgbe_hw *hw = &adapter->hw;
701 struct ixgbe_hw_stats *hwstats = &adapter->stats;
706 if ((hw->fc.current_mode == ixgbe_fc_full) ||
707 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
708 switch (hw->mac.type) {
709 case ixgbe_mac_82598EB:
710 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
713 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
715 hwstats->lxoffrxc += data;
717 /* refill credits (no tx hang) if we received xoff */
721 for (i = 0; i < adapter->num_tx_queues; i++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED,
723 &adapter->tx_ring[i]->state);
725 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
735 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
737 hwstats->pxoffrxc[i] += xoff[i];
740 /* disarm tx queues that have received xoff frames */
741 for (i = 0; i < adapter->num_tx_queues; i++) {
742 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
743 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
746 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
750 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
752 return ring->tx_stats.completed;
755 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
757 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
758 struct ixgbe_hw *hw = &adapter->hw;
760 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
761 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
764 return (head < tail) ?
765 tail - head : (tail + ring->count - head);
770 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
772 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
773 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
774 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
777 clear_check_for_tx_hang(tx_ring);
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
791 if ((tx_done_old == tx_done) && tx_pending) {
792 /* make sure it is true for two checks in a row */
793 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
796 /* update completed stats and continue */
797 tx_ring->tx_stats.tx_done_old = tx_done;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
805 #define IXGBE_MAX_TXD_PWR 14
806 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
808 /* Tx Descriptors needed, worst case */
809 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
814 static void ixgbe_tx_timeout(struct net_device *netdev);
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
818 * @q_vector: structure containing interrupt and ring information
819 * @tx_ring: tx ring to clean
821 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
822 struct ixgbe_ring *tx_ring)
824 struct ixgbe_adapter *adapter = q_vector->adapter;
825 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
826 struct ixgbe_tx_buffer *tx_buffer_info;
827 unsigned int total_bytes = 0, total_packets = 0;
828 u16 i, eop, count = 0;
830 i = tx_ring->next_to_clean;
831 eop = tx_ring->tx_buffer_info[i].next_to_watch;
832 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
834 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
835 (count < tx_ring->work_limit)) {
836 bool cleaned = false;
837 rmb(); /* read buffer_info after eop_desc */
838 for ( ; !cleaned; count++) {
839 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
840 tx_buffer_info = &tx_ring->tx_buffer_info[i];
842 tx_desc->wb.status = 0;
843 cleaned = (i == eop);
846 if (i == tx_ring->count)
849 if (cleaned && tx_buffer_info->skb) {
850 total_bytes += tx_buffer_info->bytecount;
851 total_packets += tx_buffer_info->gso_segs;
854 ixgbe_unmap_and_free_tx_resource(tx_ring,
858 tx_ring->tx_stats.completed++;
859 eop = tx_ring->tx_buffer_info[i].next_to_watch;
860 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
863 tx_ring->next_to_clean = i;
864 tx_ring->total_bytes += total_bytes;
865 tx_ring->total_packets += total_packets;
866 u64_stats_update_begin(&tx_ring->syncp);
867 tx_ring->stats.packets += total_packets;
868 tx_ring->stats.bytes += total_bytes;
869 u64_stats_update_end(&tx_ring->syncp);
871 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw *hw = &adapter->hw;
874 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
875 e_err(drv, "Detected Tx Unit Hang\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
883 tx_ring->queue_index,
884 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
885 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
886 tx_ring->next_to_use, eop,
887 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
889 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter->tx_timeout_count + 1, tx_ring->queue_index);
895 /* schedule immediate reset if we believe we hung */
896 ixgbe_tx_timeout(adapter->netdev);
898 /* the adapter is about to reset, no point in enabling stuff */
902 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
903 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
904 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
909 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
910 !test_bit(__IXGBE_DOWN, &adapter->state)) {
911 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
912 ++tx_ring->tx_stats.restart_queue;
916 return count < tx_ring->work_limit;
919 #ifdef CONFIG_IXGBE_DCA
920 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
921 struct ixgbe_ring *rx_ring,
924 struct ixgbe_hw *hw = &adapter->hw;
926 u8 reg_idx = rx_ring->reg_idx;
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
929 switch (hw->mac.type) {
930 case ixgbe_mac_82598EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
932 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
934 case ixgbe_mac_82599EB:
936 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
937 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
943 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
944 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
946 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
951 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
952 struct ixgbe_ring *tx_ring,
955 struct ixgbe_hw *hw = &adapter->hw;
957 u8 reg_idx = tx_ring->reg_idx;
959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
961 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
962 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
963 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
964 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
965 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
966 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
968 case ixgbe_mac_82599EB:
970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
971 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
972 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
974 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
983 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
985 struct ixgbe_adapter *adapter = q_vector->adapter;
990 if (q_vector->cpu == cpu)
993 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
994 for (i = 0; i < q_vector->txr_count; i++) {
995 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
996 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1007 q_vector->cpu = cpu;
1012 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1024 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1028 for (i = 0; i < num_q_vectors; i++) {
1029 adapter->q_vector[i]->cpu = -1;
1030 ixgbe_update_dca(adapter->q_vector[i]);
1034 static int __ixgbe_notify_dca(struct device *dev, void *data)
1036 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1037 unsigned long event = *(unsigned long *)data;
1039 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1043 case DCA_PROVIDER_ADD:
1044 /* if we're already enabled, don't do it again */
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1047 if (dca_add_requester(dev) == 0) {
1048 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1049 ixgbe_setup_dca(adapter);
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE:
1054 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1055 dca_remove_requester(dev);
1056 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1065 #endif /* CONFIG_IXGBE_DCA */
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
1074 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1075 struct sk_buff *skb, u8 status,
1076 struct ixgbe_ring *ring,
1077 union ixgbe_adv_rx_desc *rx_desc)
1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct napi_struct *napi = &q_vector->napi;
1081 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1082 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1084 if (is_vlan && (tag & VLAN_VID_MASK))
1085 __vlan_hwaccel_put_tag(skb, tag);
1087 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1088 napi_gro_receive(napi, skb);
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1099 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1100 union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
1103 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1105 skb_checksum_none_assert(skb);
1107 /* Rx csum disabled */
1108 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1111 /* if IP and error */
1112 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1113 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1114 adapter->hw_csum_rx_error++;
1118 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1121 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1122 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1128 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1129 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1132 adapter->hw_csum_rx_error++;
1136 /* It must be a TCP or UDP packet with a valid checksum */
1137 skb->ip_summed = CHECKSUM_UNNECESSARY;
1140 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1149 writel(val, rx_ring->tail);
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
1157 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1159 union ixgbe_adv_rx_desc *rx_desc;
1160 struct ixgbe_rx_buffer *bi;
1161 struct sk_buff *skb;
1162 u16 i = rx_ring->next_to_use;
1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring->netdev)
1168 while (cleaned_count--) {
1169 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1170 bi = &rx_ring->rx_buffer_info[i];
1174 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1175 rx_ring->rx_buf_len);
1177 rx_ring->rx_stats.alloc_rx_buff_failed++;
1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb, rx_ring->queue_index);
1186 bi->dma = dma_map_single(rx_ring->dev,
1188 rx_ring->rx_buf_len,
1190 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1191 rx_ring->rx_stats.alloc_rx_buff_failed++;
1197 if (ring_is_ps_enabled(rx_ring)) {
1199 bi->page = netdev_alloc_page(rx_ring->netdev);
1201 rx_ring->rx_stats.alloc_rx_page_failed++;
1206 if (!bi->page_dma) {
1207 /* use a half page if we're re-using */
1208 bi->page_offset ^= PAGE_SIZE / 2;
1209 bi->page_dma = dma_map_page(rx_ring->dev,
1214 if (dma_mapping_error(rx_ring->dev,
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
1224 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1225 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1227 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1228 rx_desc->read.hdr_addr = 0;
1232 if (i == rx_ring->count)
1237 if (rx_ring->next_to_use != i) {
1238 rx_ring->next_to_use = i;
1239 ixgbe_release_rx_desc(rx_ring, i);
1243 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1249 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1250 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1252 if (hlen > IXGBE_RX_HDR_SIZE)
1253 hlen = IXGBE_RX_HDR_SIZE;
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1265 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1267 unsigned int frag_list_size = 0;
1268 unsigned int skb_cnt = 1;
1271 struct sk_buff *prev = skb->prev;
1272 frag_list_size += skb->len;
1278 skb_shinfo(skb)->frag_list = skb->next;
1280 skb->len += frag_list_size;
1281 skb->data_len += frag_list_size;
1282 skb->truesize += frag_list_size;
1283 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1288 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1290 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1291 IXGBE_RXDADV_RSCCNT_MASK);
1294 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1295 struct ixgbe_ring *rx_ring,
1296 int *work_done, int work_to_do)
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1300 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1301 struct sk_buff *skb;
1302 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1303 const int current_node = numa_node_id();
1306 #endif /* IXGBE_FCOE */
1309 u16 cleaned_count = 0;
1310 bool pkt_is_rsc = false;
1312 i = rx_ring->next_to_clean;
1313 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1316 while (staterr & IXGBE_RXD_STAT_DD) {
1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
1321 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1323 skb = rx_buffer_info->skb;
1324 rx_buffer_info->skb = NULL;
1325 prefetch(skb->data);
1327 if (ring_is_rsc_enabled(rx_ring))
1328 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1330 /* if this is a skb from previous receive DMA will be 0 */
1331 if (rx_buffer_info->dma) {
1334 !(staterr & IXGBE_RXD_STAT_EOP) &&
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1343 IXGBE_RSC_CB(skb)->delay_unmap = true;
1344 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1346 dma_unmap_single(rx_ring->dev,
1347 rx_buffer_info->dma,
1348 rx_ring->rx_buf_len,
1351 rx_buffer_info->dma = 0;
1353 if (ring_is_ps_enabled(rx_ring)) {
1354 hlen = ixgbe_get_hlen(rx_desc);
1355 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1357 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1362 /* assume packet split since header is unmapped */
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1367 dma_unmap_page(rx_ring->dev,
1368 rx_buffer_info->page_dma,
1371 rx_buffer_info->page_dma = 0;
1372 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1373 rx_buffer_info->page,
1374 rx_buffer_info->page_offset,
1377 if ((page_count(rx_buffer_info->page) == 1) &&
1378 (page_to_nid(rx_buffer_info->page) == current_node))
1379 get_page(rx_buffer_info->page);
1381 rx_buffer_info->page = NULL;
1383 skb->len += upper_len;
1384 skb->data_len += upper_len;
1385 skb->truesize += upper_len;
1389 if (i == rx_ring->count)
1392 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1397 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT;
1399 next_buffer = &rx_ring->rx_buffer_info[nextp];
1401 next_buffer = &rx_ring->rx_buffer_info[i];
1404 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1405 if (ring_is_ps_enabled(rx_ring)) {
1406 rx_buffer_info->skb = next_buffer->skb;
1407 rx_buffer_info->dma = next_buffer->dma;
1408 next_buffer->skb = skb;
1409 next_buffer->dma = 0;
1411 skb->next = next_buffer->skb;
1412 skb->next->prev = skb;
1414 rx_ring->rx_stats.non_eop_descs++;
1419 skb = ixgbe_transform_rsc_queue(skb);
1420 /* if we got here without RSC the packet is invalid */
1422 __pskb_trim(skb, 0);
1423 rx_buffer_info->skb = skb;
1428 if (ring_is_rsc_enabled(rx_ring)) {
1429 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1430 dma_unmap_single(rx_ring->dev,
1431 IXGBE_RSC_CB(skb)->dma,
1432 rx_ring->rx_buf_len,
1434 IXGBE_RSC_CB(skb)->dma = 0;
1435 IXGBE_RSC_CB(skb)->delay_unmap = false;
1439 if (ring_is_ps_enabled(rx_ring))
1440 rx_ring->rx_stats.rsc_count +=
1441 skb_shinfo(skb)->nr_frags;
1443 rx_ring->rx_stats.rsc_count +=
1444 IXGBE_RSC_CB(skb)->skb_cnt;
1445 rx_ring->rx_stats.rsc_flush++;
1448 /* ERR_MASK will only have valid bits if EOP set */
1449 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb, 0);
1452 rx_buffer_info->skb = skb;
1456 ixgbe_rx_checksum(adapter, rx_desc, skb);
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes += skb->len;
1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1465 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1466 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1470 #endif /* IXGBE_FCOE */
1471 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1474 rx_desc->wb.upper.status_error = 0;
1477 if (*work_done >= work_to_do)
1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1482 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1486 /* use prefetched values */
1488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1491 rx_ring->next_to_clean = i;
1492 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1495 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes > 0) {
1502 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1503 sizeof(struct fc_frame_header) -
1504 sizeof(struct fcoe_crc_eof);
1507 total_rx_bytes += ddp_bytes;
1508 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1510 #endif /* IXGBE_FCOE */
1512 rx_ring->total_packets += total_rx_packets;
1513 rx_ring->total_bytes += total_rx_bytes;
1514 u64_stats_update_begin(&rx_ring->syncp);
1515 rx_ring->stats.packets += total_rx_packets;
1516 rx_ring->stats.bytes += total_rx_bytes;
1517 u64_stats_update_end(&rx_ring->syncp);
1520 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1528 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1530 struct ixgbe_q_vector *q_vector;
1531 int i, q_vectors, v_idx, r_idx;
1534 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1537 * Populate the IVAR table and set the ITR values to the
1538 * corresponding register.
1540 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1541 q_vector = adapter->q_vector[v_idx];
1542 /* XXX for_each_set_bit(...) */
1543 r_idx = find_first_bit(q_vector->rxr_idx,
1544 adapter->num_rx_queues);
1546 for (i = 0; i < q_vector->rxr_count; i++) {
1547 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1548 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1549 r_idx = find_next_bit(q_vector->rxr_idx,
1550 adapter->num_rx_queues,
1553 r_idx = find_first_bit(q_vector->txr_idx,
1554 adapter->num_tx_queues);
1556 for (i = 0; i < q_vector->txr_count; i++) {
1557 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1559 r_idx = find_next_bit(q_vector->txr_idx,
1560 adapter->num_tx_queues,
1564 if (q_vector->txr_count && !q_vector->rxr_count)
1566 q_vector->eitr = adapter->tx_eitr_param;
1567 else if (q_vector->rxr_count)
1569 q_vector->eitr = adapter->rx_eitr_param;
1571 ixgbe_write_eitr(q_vector);
1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1574 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1580 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1583 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1584 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1585 q_vector->affinity_mask);
1589 switch (adapter->hw.mac.type) {
1590 case ixgbe_mac_82598EB:
1591 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1594 case ixgbe_mac_82599EB:
1595 case ixgbe_mac_X540:
1596 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1604 /* set up to autoclear timer, and the vectors */
1605 mask = IXGBE_EIMS_ENABLE_MASK;
1606 if (adapter->num_vfs)
1607 mask &= ~(IXGBE_EIMS_OTHER |
1608 IXGBE_EIMS_MAILBOX |
1611 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1615 enum latency_range {
1619 latency_invalid = 255
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1640 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1641 u32 eitr, u8 itr_setting,
1642 int packets, int bytes)
1644 unsigned int retval = itr_setting;
1649 goto update_itr_done;
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1657 /* what was last interrupt timeslice? */
1658 timepassed_us = 1000000/eitr;
1659 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1661 switch (itr_setting) {
1662 case lowest_latency:
1663 if (bytes_perint > adapter->eitr_low)
1664 retval = low_latency;
1667 if (bytes_perint > adapter->eitr_high)
1668 retval = bulk_latency;
1669 else if (bytes_perint <= adapter->eitr_low)
1670 retval = lowest_latency;
1673 if (bytes_perint <= adapter->eitr_high)
1674 retval = low_latency;
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
1684 * @q_vector: structure containing interrupt and ring information
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1690 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1692 struct ixgbe_adapter *adapter = q_vector->adapter;
1693 struct ixgbe_hw *hw = &adapter->hw;
1694 int v_idx = q_vector->v_idx;
1695 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1697 switch (adapter->hw.mac.type) {
1698 case ixgbe_mac_82598EB:
1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg |= (itr_reg << 16);
1702 case ixgbe_mac_82599EB:
1703 case ixgbe_mac_X540:
1705 * 82599 and X540 can support a value of zero, so allow it for
1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1710 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1717 itr_reg |= IXGBE_EITR_CNT_WDIS;
1722 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1725 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1727 struct ixgbe_adapter *adapter = q_vector->adapter;
1730 u8 current_itr, ret_itr;
1732 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1733 for (i = 0; i < q_vector->txr_count; i++) {
1734 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1735 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1737 tx_ring->total_packets,
1738 tx_ring->total_bytes);
1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
1741 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1742 q_vector->tx_itr - 1 : ret_itr);
1743 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1747 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1748 for (i = 0; i < q_vector->rxr_count; i++) {
1749 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1750 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1752 rx_ring->total_packets,
1753 rx_ring->total_bytes);
1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
1756 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1757 q_vector->rx_itr - 1 : ret_itr);
1758 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1762 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1764 switch (current_itr) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency:
1770 new_itr = 20000; /* aka hwitr = ~200 */
1778 if (new_itr != q_vector->eitr) {
1779 /* do an exponential smoothing */
1780 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector->eitr = new_itr;
1785 ixgbe_write_eitr(q_vector);
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1793 static void ixgbe_check_overtemp_task(struct work_struct *work)
1795 struct ixgbe_adapter *adapter = container_of(work,
1796 struct ixgbe_adapter,
1797 check_overtemp_task);
1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 eicr = adapter->interrupt_event;
1801 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1804 switch (hw->device_id) {
1805 case IXGBE_DEV_ID_82599_T3_LOM: {
1807 bool link_up = false;
1809 if (hw->mac.ops.check_link)
1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1812 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1813 (eicr & IXGBE_EICR_LSC))
1814 /* Check if this is due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1832 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1834 struct ixgbe_hw *hw = &adapter->hw;
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1844 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1846 struct ixgbe_hw *hw = &adapter->hw;
1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1852 schedule_work(&adapter->sfp_config_module_task);
1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1858 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1859 schedule_work(&adapter->multispeed_fiber_task);
1863 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1865 struct ixgbe_hw *hw = &adapter->hw;
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1869 adapter->link_check_timeout = jiffies;
1870 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1872 IXGBE_WRITE_FLUSH(hw);
1873 schedule_work(&adapter->watchdog_task);
1877 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1879 struct net_device *netdev = data;
1880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1881 struct ixgbe_hw *hw = &adapter->hw;
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1890 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1893 if (eicr & IXGBE_EICR_LSC)
1894 ixgbe_check_lsc(adapter);
1896 if (eicr & IXGBE_EICR_MAILBOX)
1897 ixgbe_msg_task(adapter);
1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82599EB:
1901 ixgbe_check_sfp_event(adapter, eicr);
1902 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904 adapter->interrupt_event = eicr;
1905 schedule_work(&adapter->check_overtemp_task);
1907 /* now fallthrough to handle Flow Director */
1908 case ixgbe_mac_X540:
1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1912 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 struct ixgbe_ring *tx_ring =
1917 adapter->tx_ring[i];
1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1920 schedule_work(&adapter->fdir_reinit_task);
1928 ixgbe_check_fan_failure(adapter, eicr);
1930 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1936 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1940 struct ixgbe_hw *hw = &adapter->hw;
1942 switch (hw->mac.type) {
1943 case ixgbe_mac_82598EB:
1944 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1947 case ixgbe_mac_82599EB:
1948 case ixgbe_mac_X540:
1949 mask = (qmask & 0xFFFFFFFF);
1951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1952 mask = (qmask >> 32);
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1959 /* skip the flush */
1962 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1966 struct ixgbe_hw *hw = &adapter->hw;
1968 switch (hw->mac.type) {
1969 case ixgbe_mac_82598EB:
1970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1973 case ixgbe_mac_82599EB:
1974 case ixgbe_mac_X540:
1975 mask = (qmask & 0xFFFFFFFF);
1977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1978 mask = (qmask >> 32);
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1985 /* skip the flush */
1988 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1990 struct ixgbe_q_vector *q_vector = data;
1991 struct ixgbe_adapter *adapter = q_vector->adapter;
1992 struct ixgbe_ring *tx_ring;
1995 if (!q_vector->txr_count)
1998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999 for (i = 0; i < q_vector->txr_count; i++) {
2000 tx_ring = adapter->tx_ring[r_idx];
2001 tx_ring->total_bytes = 0;
2002 tx_ring->total_packets = 0;
2003 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2007 /* EIAM disabled interrupts (on this vector) for us */
2008 napi_schedule(&q_vector->napi);
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2016 * @data: pointer to our q_vector struct for this interrupt vector
2018 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2020 struct ixgbe_q_vector *q_vector = data;
2021 struct ixgbe_adapter *adapter = q_vector->adapter;
2022 struct ixgbe_ring *rx_ring;
2026 #ifdef CONFIG_IXGBE_DCA
2027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2028 ixgbe_update_dca(q_vector);
2031 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2032 for (i = 0; i < q_vector->rxr_count; i++) {
2033 rx_ring = adapter->rx_ring[r_idx];
2034 rx_ring->total_bytes = 0;
2035 rx_ring->total_packets = 0;
2036 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2040 if (!q_vector->rxr_count)
2043 /* EIAM disabled interrupts (on this vector) for us */
2044 napi_schedule(&q_vector->napi);
2049 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2051 struct ixgbe_q_vector *q_vector = data;
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 struct ixgbe_ring *ring;
2057 if (!q_vector->txr_count && !q_vector->rxr_count)
2060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2061 for (i = 0; i < q_vector->txr_count; i++) {
2062 ring = adapter->tx_ring[r_idx];
2063 ring->total_bytes = 0;
2064 ring->total_packets = 0;
2065 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2069 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2070 for (i = 0; i < q_vector->rxr_count; i++) {
2071 ring = adapter->rx_ring[r_idx];
2072 ring->total_bytes = 0;
2073 ring->total_packets = 0;
2074 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2078 /* EIAM disabled interrupts (on this vector) for us */
2079 napi_schedule(&q_vector->napi);
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2089 * This function is optimized for cleaning one queue only on a single
2092 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2094 struct ixgbe_q_vector *q_vector =
2095 container_of(napi, struct ixgbe_q_vector, napi);
2096 struct ixgbe_adapter *adapter = q_vector->adapter;
2097 struct ixgbe_ring *rx_ring = NULL;
2101 #ifdef CONFIG_IXGBE_DCA
2102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2103 ixgbe_update_dca(q_vector);
2106 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2107 rx_ring = adapter->rx_ring[r_idx];
2109 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done < budget) {
2113 napi_complete(napi);
2114 if (adapter->rx_itr_setting & 1)
2115 ixgbe_set_itr_msix(q_vector);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2117 ixgbe_irq_enable_queues(adapter,
2118 ((u64)1 << q_vector->v_idx));
2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2129 * This function will clean more than one rx queue associated with a
2132 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2134 struct ixgbe_q_vector *q_vector =
2135 container_of(napi, struct ixgbe_q_vector, napi);
2136 struct ixgbe_adapter *adapter = q_vector->adapter;
2137 struct ixgbe_ring *ring = NULL;
2138 int work_done = 0, i;
2140 bool tx_clean_complete = true;
2142 #ifdef CONFIG_IXGBE_DCA
2143 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2144 ixgbe_update_dca(q_vector);
2147 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2148 for (i = 0; i < q_vector->txr_count; i++) {
2149 ring = adapter->tx_ring[r_idx];
2150 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget /= (q_vector->rxr_count ?: 1);
2158 budget = max(budget, 1);
2159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2160 for (i = 0; i < q_vector->rxr_count; i++) {
2161 ring = adapter->rx_ring[r_idx];
2162 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2163 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2167 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2168 ring = adapter->rx_ring[r_idx];
2169 /* If all Rx work done, exit the polling mode */
2170 if (work_done < budget) {
2171 napi_complete(napi);
2172 if (adapter->rx_itr_setting & 1)
2173 ixgbe_set_itr_msix(q_vector);
2174 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2175 ixgbe_irq_enable_queues(adapter,
2176 ((u64)1 << q_vector->v_idx));
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2188 * This function is optimized for cleaning one queue only on a single
2191 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2193 struct ixgbe_q_vector *q_vector =
2194 container_of(napi, struct ixgbe_q_vector, napi);
2195 struct ixgbe_adapter *adapter = q_vector->adapter;
2196 struct ixgbe_ring *tx_ring = NULL;
2200 #ifdef CONFIG_IXGBE_DCA
2201 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2202 ixgbe_update_dca(q_vector);
2205 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2206 tx_ring = adapter->tx_ring[r_idx];
2208 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2211 /* If all Tx work done, exit the polling mode */
2212 if (work_done < budget) {
2213 napi_complete(napi);
2214 if (adapter->tx_itr_setting & 1)
2215 ixgbe_set_itr_msix(q_vector);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_enable_queues(adapter,
2218 ((u64)1 << q_vector->v_idx));
2224 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2227 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2228 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2230 set_bit(r_idx, q_vector->rxr_idx);
2231 q_vector->rxr_count++;
2232 rx_ring->q_vector = q_vector;
2235 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2239 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2241 set_bit(t_idx, q_vector->txr_idx);
2242 q_vector->txr_count++;
2243 tx_ring->q_vector = q_vector;
2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
2256 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2260 int rxr_idx = 0, txr_idx = 0;
2261 int rxr_remaining = adapter->num_rx_queues;
2262 int txr_remaining = adapter->num_tx_queues;
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2271 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2277 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2279 map_vector_to_rxq(adapter, v_start, rxr_idx);
2281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2282 map_vector_to_txq(adapter, v_start, txr_idx);
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2292 /* Re-adjusting *qpv takes care of the remainder. */
2293 for (i = v_start; i < q_vectors; i++) {
2294 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2295 for (j = 0; j < rqpv; j++) {
2296 map_vector_to_rxq(adapter, i, rxr_idx);
2300 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2301 for (j = 0; j < tqpv; j++) {
2302 map_vector_to_txq(adapter, i, txr_idx);
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2318 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2320 struct net_device *netdev = adapter->netdev;
2321 irqreturn_t (*handler)(int, void *);
2322 int i, vector, q_vectors, err;
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2328 err = ixgbe_map_rings_to_vectors(adapter);
2332 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2337 for (vector = 0; vector < q_vectors; vector++) {
2338 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2339 handler = SET_HANDLER(q_vector);
2341 if (handler == &ixgbe_msix_clean_rx) {
2342 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2343 "%s-%s-%d", netdev->name, "rx", ri++);
2344 } else if (handler == &ixgbe_msix_clean_tx) {
2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "tx", ti++);
2347 } else if (handler == &ixgbe_msix_clean_many) {
2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "TxRx", ri++);
2352 /* skip this unused q_vector */
2355 err = request_irq(adapter->msix_entries[vector].vector,
2356 handler, 0, q_vector->name,
2359 e_err(probe, "request_irq failed for MSIX interrupt "
2360 "Error: %d\n", err);
2361 goto free_queue_irqs;
2365 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2366 err = request_irq(adapter->msix_entries[vector].vector,
2367 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2369 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2370 goto free_queue_irqs;
2376 for (i = vector - 1; i >= 0; i--)
2377 free_irq(adapter->msix_entries[--vector].vector,
2378 adapter->q_vector[i]);
2379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2380 pci_disable_msix(adapter->pdev);
2381 kfree(adapter->msix_entries);
2382 adapter->msix_entries = NULL;
2386 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2389 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2390 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2391 u32 new_itr = q_vector->eitr;
2394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2396 tx_ring->total_packets,
2397 tx_ring->total_bytes);
2398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2400 rx_ring->total_packets,
2401 rx_ring->total_bytes);
2403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2420 if (new_itr != q_vector->eitr) {
2421 /* do an exponential smoothing */
2422 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2424 /* save the algorithm value here */
2425 q_vector->eitr = new_itr;
2427 ixgbe_write_eitr(q_vector);
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2435 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2440 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2441 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2442 mask |= IXGBE_EIMS_GPI_SDP0;
2443 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2444 mask |= IXGBE_EIMS_GPI_SDP1;
2445 switch (adapter->hw.mac.type) {
2446 case ixgbe_mac_82599EB:
2447 case ixgbe_mac_X540:
2448 mask |= IXGBE_EIMS_ECC;
2449 mask |= IXGBE_EIMS_GPI_SDP1;
2450 mask |= IXGBE_EIMS_GPI_SDP2;
2451 if (adapter->num_vfs)
2452 mask |= IXGBE_EIMS_MAILBOX;
2457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2458 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2459 mask |= IXGBE_EIMS_FLOW_DIR;
2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2463 ixgbe_irq_enable_queues(adapter, ~0);
2465 IXGBE_WRITE_FLUSH(&adapter->hw);
2467 if (adapter->num_vfs > 32) {
2468 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2474 * ixgbe_intr - legacy mode Interrupt Handler
2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
2478 static irqreturn_t ixgbe_intr(int irq, void *data)
2480 struct net_device *netdev = data;
2481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2482 struct ixgbe_hw *hw = &adapter->hw;
2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2487 * Workaround for silicon errata on 82598. Mask the interrupts
2488 * before the read of EICR.
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2497 * shared interrupt alert!
2498 * make sure interrupts are enabled because the read will
2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
2505 return IRQ_NONE; /* Not our interrupt */
2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
2513 ixgbe_check_sfp_event(adapter, eicr);
2514 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2515 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2516 adapter->interrupt_event = eicr;
2517 schedule_work(&adapter->check_overtemp_task);
2524 ixgbe_check_fan_failure(adapter, eicr);
2526 if (napi_schedule_prep(&(q_vector->napi))) {
2527 adapter->tx_ring[0]->total_packets = 0;
2528 adapter->tx_ring[0]->total_bytes = 0;
2529 adapter->rx_ring[0]->total_packets = 0;
2530 adapter->rx_ring[0]->total_bytes = 0;
2531 /* would disable interrupts here but EIAM disabled it */
2532 __napi_schedule(&(q_vector->napi));
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2546 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2548 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2550 for (i = 0; i < q_vectors; i++) {
2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2552 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2553 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2554 q_vector->rxr_count = 0;
2555 q_vector->txr_count = 0;
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2566 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2568 struct net_device *netdev = adapter->netdev;
2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 err = ixgbe_request_msix_irqs(adapter);
2573 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2574 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2575 netdev->name, netdev);
2577 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2578 netdev->name, netdev);
2582 e_err(probe, "request_irq failed, Error %d\n", err);
2587 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2589 struct net_device *netdev = adapter->netdev;
2591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2594 q_vectors = adapter->num_msix_vectors;
2597 free_irq(adapter->msix_entries[i].vector, netdev);
2600 for (; i >= 0; i--) {
2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2606 free_irq(adapter->msix_entries[i].vector,
2607 adapter->q_vector[i]);
2610 ixgbe_reset_q_vectors(adapter);
2612 free_irq(adapter->pdev->irq, netdev);
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2620 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2622 switch (adapter->hw.mac.type) {
2623 case ixgbe_mac_82598EB:
2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2626 case ixgbe_mac_82599EB:
2627 case ixgbe_mac_X540:
2628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2631 if (adapter->num_vfs > 32)
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2637 IXGBE_WRITE_FLUSH(&adapter->hw);
2638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2640 for (i = 0; i < adapter->num_msix_vectors; i++)
2641 synchronize_irq(adapter->msix_entries[i].vector);
2643 synchronize_irq(adapter->pdev->irq);
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2651 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2653 struct ixgbe_hw *hw = &adapter->hw;
2655 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2656 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2658 ixgbe_set_ivar(adapter, 0, 0, 0);
2659 ixgbe_set_ivar(adapter, 1, 0, 0);
2661 map_vector_to_rxq(adapter, 0, 0);
2662 map_vector_to_txq(adapter, 0, 0);
2664 e_info(hw, "Legacy interrupt IVAR setup done\n");
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2672 * Configure the Tx descriptor ring after a reset.
2674 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 u64 tdba = ring->dma;
2681 u8 reg_idx = ring->reg_idx;
2683 /* disable queue to avoid issues while updating state */
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2686 txdctl & ~IXGBE_TXDCTL_ENABLE);
2687 IXGBE_WRITE_FLUSH(hw);
2689 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2690 (tdba & DMA_BIT_MASK(32)));
2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2692 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2693 ring->count * sizeof(union ixgbe_adv_tx_desc));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2695 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2696 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2698 /* configure fetching thresholds */
2699 if (adapter->rx_itr_setting == 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl &= ~0x007F0000;
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl |= (8 << 16);
2706 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2711 /* reinitialize flowdirector state */
2712 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2713 adapter->atr_sample_rate) {
2714 ring->atr_sample_rate = adapter->atr_sample_rate;
2715 ring->atr_count = 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2718 ring->atr_sample_rate = 0;
2721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2724 txdctl |= IXGBE_TXDCTL_ENABLE;
2725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw->mac.type == ixgbe_mac_82598EB &&
2729 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2732 /* poll to verify queue is enabled */
2735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2736 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2738 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2741 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2743 struct ixgbe_hw *hw = &adapter->hw;
2747 if (hw->mac.type == ixgbe_mac_82598EB)
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2752 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2755 /* set transmit pool layout */
2756 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2757 switch (adapter->flags & mask) {
2759 case (IXGBE_FLAG_SRIOV_ENABLED):
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2764 case (IXGBE_FLAG_DCB_ENABLED):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2767 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2771 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2775 /* re-enable the arbiter */
2776 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2782 * @adapter: board private structure
2784 * Configure the Tx unit of the MAC after a reset.
2786 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2788 struct ixgbe_hw *hw = &adapter->hw;
2792 ixgbe_setup_mtqc(adapter);
2794 if (hw->mac.type != ixgbe_mac_82598EB) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2797 dmatxctl |= IXGBE_DMATXCTL_TE;
2798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2801 /* Setup the HW Tx Head and Tail descriptor pointers */
2802 for (i = 0; i < adapter->num_tx_queues; i++)
2803 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2806 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2808 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2809 struct ixgbe_ring *rx_ring)
2812 u8 reg_idx = rx_ring->reg_idx;
2814 switch (adapter->hw.mac.type) {
2815 case ixgbe_mac_82598EB: {
2816 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2817 const int mask = feature[RING_F_RSS].mask;
2818 reg_idx = reg_idx & mask;
2821 case ixgbe_mac_82599EB:
2822 case ixgbe_mac_X540:
2827 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2829 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2830 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2831 if (adapter->num_vfs)
2832 srrctl |= IXGBE_SRRCTL_DROP_EN;
2834 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK;
2837 if (ring_is_ps_enabled(rx_ring)) {
2838 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2843 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2845 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2847 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2853 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2855 struct ixgbe_hw *hw = &adapter->hw;
2856 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2859 u32 mrqc = 0, reta = 0;
2864 /* Fill out hash function seeds */
2865 for (i = 0; i < 10; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2868 /* Fill out redirection table */
2869 for (i = 0, j = 0; i < 128; i++, j++) {
2870 if (j == adapter->ring_feature[RING_F_RSS].indices)
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta = (reta << 8) | (j * 0x11);
2876 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2881 rxcsum |= IXGBE_RXCSUM_PCSD;
2882 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2885 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2887 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2888 #ifdef CONFIG_IXGBE_DCB
2889 | IXGBE_FLAG_DCB_ENABLED
2891 | IXGBE_FLAG_SRIOV_ENABLED
2895 #ifdef CONFIG_IXGBE_DCB
2896 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2897 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2899 case (IXGBE_FLAG_DCB_ENABLED):
2900 mrqc = IXGBE_MRQC_RT8TCEN;
2902 #endif /* CONFIG_IXGBE_DCB */
2903 case (IXGBE_FLAG_RSS_ENABLED):
2904 mrqc = IXGBE_MRQC_RSSEN;
2906 case (IXGBE_FLAG_SRIOV_ENABLED):
2907 mrqc = IXGBE_MRQC_VMDQEN;
2913 /* Perform hash on these packet types */
2914 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2915 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2916 | IXGBE_MRQC_RSS_FIELD_IPV6
2917 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2919 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2923 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2924 * @adapter: address of board private structure
2925 * @ring: structure containing ring specific data
2927 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2928 struct ixgbe_ring *ring)
2930 struct ixgbe_hw *hw = &adapter->hw;
2932 u8 reg_idx = ring->reg_idx;
2934 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2935 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2936 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2940 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2941 * @adapter: address of board private structure
2942 * @index: index of ring to set
2944 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2945 struct ixgbe_ring *ring)
2947 struct ixgbe_hw *hw = &adapter->hw;
2950 u8 reg_idx = ring->reg_idx;
2952 if (!ring_is_rsc_enabled(ring))
2955 rx_buf_len = ring->rx_buf_len;
2956 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2957 rscctrl |= IXGBE_RSCCTL_RSCEN;
2959 * we must limit the number of descriptors so that the
2960 * total size of max desc * buf_len is not greater
2963 if (ring_is_ps_enabled(ring)) {
2964 #if (MAX_SKB_FRAGS > 16)
2965 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2966 #elif (MAX_SKB_FRAGS > 8)
2967 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2968 #elif (MAX_SKB_FRAGS > 4)
2969 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2971 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2974 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2975 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2976 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2977 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2979 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2981 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2985 * ixgbe_set_uta - Set unicast filter table address
2986 * @adapter: board private structure
2988 * The unicast table address is a register array of 32-bit registers.
2989 * The table is meant to be used in a way similar to how the MTA is used
2990 * however due to certain limitations in the hardware it is necessary to
2991 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2992 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2994 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2996 struct ixgbe_hw *hw = &adapter->hw;
2999 /* The UTA table only exists on 82599 hardware and newer */
3000 if (hw->mac.type < ixgbe_mac_82599EB)
3003 /* we only need to do this if VMDq is enabled */
3004 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3007 for (i = 0; i < 128; i++)
3008 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3011 #define IXGBE_MAX_RX_DESC_POLL 10
3012 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3013 struct ixgbe_ring *ring)
3015 struct ixgbe_hw *hw = &adapter->hw;
3016 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3018 u8 reg_idx = ring->reg_idx;
3020 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3021 if (hw->mac.type == ixgbe_mac_82598EB &&
3022 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3027 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3028 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3031 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3032 "the polling period\n", reg_idx);
3036 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3037 struct ixgbe_ring *ring)
3039 struct ixgbe_hw *hw = &adapter->hw;
3040 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3042 u8 reg_idx = ring->reg_idx;
3044 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3045 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3047 /* write value back with RXDCTL.ENABLE bit cleared */
3048 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3050 if (hw->mac.type == ixgbe_mac_82598EB &&
3051 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3054 /* the hardware may take up to 100us to really disable the rx queue */
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3058 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3061 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3062 "the polling period\n", reg_idx);
3066 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3067 struct ixgbe_ring *ring)
3069 struct ixgbe_hw *hw = &adapter->hw;
3070 u64 rdba = ring->dma;
3072 u8 reg_idx = ring->reg_idx;
3074 /* disable queue to avoid issues while updating state */
3075 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3076 ixgbe_disable_rx_queue(adapter, ring);
3078 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3079 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3080 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3081 ring->count * sizeof(union ixgbe_adv_rx_desc));
3082 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3083 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3084 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3086 ixgbe_configure_srrctl(adapter, ring);
3087 ixgbe_configure_rscctl(adapter, ring);
3089 /* If operating in IOV mode set RLPML for X540 */
3090 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3091 hw->mac.type == ixgbe_mac_X540) {
3092 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3093 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3094 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3097 if (hw->mac.type == ixgbe_mac_82598EB) {
3099 * enable cache line friendly hardware writes:
3100 * PTHRESH=32 descriptors (half the internal cache),
3101 * this also removes ugly rx_no_buffer_count increment
3102 * HTHRESH=4 descriptors (to minimize latency on fetch)
3103 * WTHRESH=8 burst writeback up to two cache lines
3105 rxdctl &= ~0x3FFFFF;
3109 /* enable receive descriptor ring */
3110 rxdctl |= IXGBE_RXDCTL_ENABLE;
3111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3113 ixgbe_rx_desc_queue_enable(adapter, ring);
3114 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3117 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3119 struct ixgbe_hw *hw = &adapter->hw;
3122 /* PSRTYPE must be initialized in non 82598 adapters */
3123 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3124 IXGBE_PSRTYPE_UDPHDR |
3125 IXGBE_PSRTYPE_IPV4HDR |
3126 IXGBE_PSRTYPE_L2HDR |
3127 IXGBE_PSRTYPE_IPV6HDR;
3129 if (hw->mac.type == ixgbe_mac_82598EB)
3132 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3133 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3135 for (p = 0; p < adapter->num_rx_pools; p++)
3136 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3140 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3142 struct ixgbe_hw *hw = &adapter->hw;
3145 u32 reg_offset, vf_shift;
3148 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3151 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3152 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3153 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3154 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3156 vf_shift = adapter->num_vfs % 32;
3157 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3159 /* Enable only the PF's pool for Tx/Rx */
3160 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3161 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3162 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3163 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3164 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3166 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3167 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3170 * Set up VF register offsets for selected VT Mode,
3171 * i.e. 32 or 64 VFs for SR-IOV
3173 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3174 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3175 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3176 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3178 /* enable Tx loopback for VF/PF communication */
3179 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3180 /* Enable MAC Anti-Spoofing */
3181 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3185 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3187 struct ixgbe_hw *hw = &adapter->hw;
3188 struct net_device *netdev = adapter->netdev;
3189 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3191 struct ixgbe_ring *rx_ring;
3195 /* Decide whether to use packet split mode or not */
3197 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3199 /* Do not use packet split if we're in SR-IOV Mode */
3200 if (adapter->num_vfs)
3201 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3203 /* Disable packet split due to 82599 erratum #45 */
3204 if (hw->mac.type == ixgbe_mac_82599EB)
3205 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3207 /* Set the RX buffer length according to the mode */
3208 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3209 rx_buf_len = IXGBE_RX_HDR_SIZE;
3211 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3212 (netdev->mtu <= ETH_DATA_LEN))
3213 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3215 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3219 /* adjust max frame to be able to do baby jumbo for FCoE */
3220 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3221 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3222 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3224 #endif /* IXGBE_FCOE */
3225 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3226 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3227 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3228 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3230 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3233 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3234 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3235 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3236 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3239 * Setup the HW Rx Head and Tail Descriptor Pointers and
3240 * the Base and Length of the Rx Descriptor Ring
3242 for (i = 0; i < adapter->num_rx_queues; i++) {
3243 rx_ring = adapter->rx_ring[i];
3244 rx_ring->rx_buf_len = rx_buf_len;
3246 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3247 set_ring_ps_enabled(rx_ring);
3249 clear_ring_ps_enabled(rx_ring);
3251 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3252 set_ring_rsc_enabled(rx_ring);
3254 clear_ring_rsc_enabled(rx_ring);
3257 if (netdev->features & NETIF_F_FCOE_MTU) {
3258 struct ixgbe_ring_feature *f;
3259 f = &adapter->ring_feature[RING_F_FCOE];
3260 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3261 clear_ring_ps_enabled(rx_ring);
3262 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3263 rx_ring->rx_buf_len =
3264 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3265 } else if (!ring_is_rsc_enabled(rx_ring) &&
3266 !ring_is_ps_enabled(rx_ring)) {
3267 rx_ring->rx_buf_len =
3268 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3271 #endif /* IXGBE_FCOE */
3275 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3277 struct ixgbe_hw *hw = &adapter->hw;
3278 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3280 switch (hw->mac.type) {
3281 case ixgbe_mac_82598EB:
3283 * For VMDq support of different descriptor types or
3284 * buffer sizes through the use of multiple SRRCTL
3285 * registers, RDRXCTL.MVMEN must be set to 1
3287 * also, the manual doesn't mention it clearly but DCA hints
3288 * will only use queue 0's tags unless this bit is set. Side
3289 * effects of setting this bit are only that SRRCTL must be
3290 * fully programmed [0..15]
3292 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3294 case ixgbe_mac_82599EB:
3295 case ixgbe_mac_X540:
3296 /* Disable RSC for ACK packets */
3297 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3298 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3299 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3300 /* hardware requires some bits to be set by default */
3301 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3302 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3305 /* We should do nothing since we don't know this hardware */
3309 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3313 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3314 * @adapter: board private structure
3316 * Configure the Rx unit of the MAC after a reset.
3318 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3320 struct ixgbe_hw *hw = &adapter->hw;
3324 /* disable receives while setting up the descriptors */
3325 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3326 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3328 ixgbe_setup_psrtype(adapter);
3329 ixgbe_setup_rdrxctl(adapter);
3331 /* Program registers for the distribution of queues */
3332 ixgbe_setup_mrqc(adapter);
3334 ixgbe_set_uta(adapter);
3336 /* set_rx_buffer_len must be called before ring initialization */
3337 ixgbe_set_rx_buffer_len(adapter);
3340 * Setup the HW Rx Head and Tail Descriptor Pointers and
3341 * the Base and Length of the Rx Descriptor Ring
3343 for (i = 0; i < adapter->num_rx_queues; i++)
3344 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3346 /* disable drop enable for 82598 parts */
3347 if (hw->mac.type == ixgbe_mac_82598EB)
3348 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3350 /* enable all receives */
3351 rxctrl |= IXGBE_RXCTRL_RXEN;
3352 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3355 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3358 struct ixgbe_hw *hw = &adapter->hw;
3359 int pool_ndx = adapter->num_vfs;
3361 /* add VID to filter table */
3362 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3363 set_bit(vid, adapter->active_vlans);
3366 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 int pool_ndx = adapter->num_vfs;
3372 /* remove VID from filter table */
3373 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3374 clear_bit(vid, adapter->active_vlans);
3378 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3379 * @adapter: driver data
3381 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3383 struct ixgbe_hw *hw = &adapter->hw;
3386 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3387 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3388 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3392 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3393 * @adapter: driver data
3395 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3397 struct ixgbe_hw *hw = &adapter->hw;
3400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3401 vlnctrl |= IXGBE_VLNCTRL_VFE;
3402 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3403 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3407 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3408 * @adapter: driver data
3410 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3412 struct ixgbe_hw *hw = &adapter->hw;
3416 switch (hw->mac.type) {
3417 case ixgbe_mac_82598EB:
3418 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3419 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3422 case ixgbe_mac_82599EB:
3423 case ixgbe_mac_X540:
3424 for (i = 0; i < adapter->num_rx_queues; i++) {
3425 j = adapter->rx_ring[i]->reg_idx;
3426 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3427 vlnctrl &= ~IXGBE_RXDCTL_VME;
3428 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3437 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3438 * @adapter: driver data
3440 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3442 struct ixgbe_hw *hw = &adapter->hw;
3446 switch (hw->mac.type) {
3447 case ixgbe_mac_82598EB:
3448 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3449 vlnctrl |= IXGBE_VLNCTRL_VME;
3450 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3452 case ixgbe_mac_82599EB:
3453 case ixgbe_mac_X540:
3454 for (i = 0; i < adapter->num_rx_queues; i++) {
3455 j = adapter->rx_ring[i]->reg_idx;
3456 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3457 vlnctrl |= IXGBE_RXDCTL_VME;
3458 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3466 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3470 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3472 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3473 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3477 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3478 * @netdev: network interface device structure
3480 * Writes unicast address list to the RAR table.
3481 * Returns: -ENOMEM on failure/insufficient address space
3482 * 0 on no addresses written
3483 * X on writing X addresses to the RAR table
3485 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3488 struct ixgbe_hw *hw = &adapter->hw;
3489 unsigned int vfn = adapter->num_vfs;
3490 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3493 /* return ENOMEM indicating insufficient memory for addresses */
3494 if (netdev_uc_count(netdev) > rar_entries)
3497 if (!netdev_uc_empty(netdev) && rar_entries) {
3498 struct netdev_hw_addr *ha;
3499 /* return error if we do not support writing to RAR table */
3500 if (!hw->mac.ops.set_rar)
3503 netdev_for_each_uc_addr(ha, netdev) {
3506 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3511 /* write the addresses in reverse order to avoid write combining */
3512 for (; rar_entries > 0 ; rar_entries--)
3513 hw->mac.ops.clear_rar(hw, rar_entries);
3519 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3520 * @netdev: network interface device structure
3522 * The set_rx_method entry point is called whenever the unicast/multicast
3523 * address list or the network interface flags are updated. This routine is
3524 * responsible for configuring the hardware for proper unicast, multicast and
3527 void ixgbe_set_rx_mode(struct net_device *netdev)
3529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3530 struct ixgbe_hw *hw = &adapter->hw;
3531 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3534 /* Check for Promiscuous and All Multicast modes */
3536 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3538 /* set all bits that we expect to always be set */
3539 fctrl |= IXGBE_FCTRL_BAM;
3540 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3541 fctrl |= IXGBE_FCTRL_PMCF;
3543 /* clear the bits we are changing the status of */
3544 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3546 if (netdev->flags & IFF_PROMISC) {
3547 hw->addr_ctrl.user_set_promisc = true;
3548 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3549 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3550 /* don't hardware filter vlans in promisc mode */
3551 ixgbe_vlan_filter_disable(adapter);
3553 if (netdev->flags & IFF_ALLMULTI) {
3554 fctrl |= IXGBE_FCTRL_MPE;
3555 vmolr |= IXGBE_VMOLR_MPE;
3558 * Write addresses to the MTA, if the attempt fails
3559 * then we should just turn on promiscous mode so
3560 * that we can at least receive multicast traffic
3562 hw->mac.ops.update_mc_addr_list(hw, netdev);
3563 vmolr |= IXGBE_VMOLR_ROMPE;
3565 ixgbe_vlan_filter_enable(adapter);
3566 hw->addr_ctrl.user_set_promisc = false;
3568 * Write addresses to available RAR registers, if there is not
3569 * sufficient space to store all the addresses then enable
3570 * unicast promiscous mode
3572 count = ixgbe_write_uc_addr_list(netdev);
3574 fctrl |= IXGBE_FCTRL_UPE;
3575 vmolr |= IXGBE_VMOLR_ROPE;
3579 if (adapter->num_vfs) {
3580 ixgbe_restore_vf_multicasts(adapter);
3581 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3582 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3584 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3589 if (netdev->features & NETIF_F_HW_VLAN_RX)
3590 ixgbe_vlan_strip_enable(adapter);
3592 ixgbe_vlan_strip_disable(adapter);
3595 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3598 struct ixgbe_q_vector *q_vector;
3599 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3601 /* legacy and MSI only use one vector */
3602 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3605 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3606 struct napi_struct *napi;
3607 q_vector = adapter->q_vector[q_idx];
3608 napi = &q_vector->napi;
3609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3610 if (!q_vector->rxr_count || !q_vector->txr_count) {
3611 if (q_vector->txr_count == 1)
3612 napi->poll = &ixgbe_clean_txonly;
3613 else if (q_vector->rxr_count == 1)
3614 napi->poll = &ixgbe_clean_rxonly;
3622 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3625 struct ixgbe_q_vector *q_vector;
3626 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3628 /* legacy and MSI only use one vector */
3629 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3632 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3633 q_vector = adapter->q_vector[q_idx];
3634 napi_disable(&q_vector->napi);
3638 #ifdef CONFIG_IXGBE_DCB
3640 * ixgbe_configure_dcb - Configure DCB hardware
3641 * @adapter: ixgbe adapter struct
3643 * This is called by the driver on open to configure the DCB hardware.
3644 * This is also called by the gennetlink interface when reconfiguring
3647 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3649 struct ixgbe_hw *hw = &adapter->hw;
3650 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3652 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3653 if (hw->mac.type == ixgbe_mac_82598EB)
3654 netif_set_gso_max_size(adapter->netdev, 65536);
3658 if (hw->mac.type == ixgbe_mac_82598EB)
3659 netif_set_gso_max_size(adapter->netdev, 32768);
3662 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3663 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3666 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3668 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3671 /* Enable VLAN tag insert/strip */
3672 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3674 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3676 /* reconfigure the hardware */
3677 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3679 /* Enable RSS Hash per TC */
3680 if (hw->mac.type != ixgbe_mac_82598EB) {
3684 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3686 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3691 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3693 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3698 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3700 struct net_device *netdev = adapter->netdev;
3701 struct ixgbe_hw *hw = &adapter->hw;
3704 #ifdef CONFIG_IXGBE_DCB
3705 ixgbe_configure_dcb(adapter);
3708 ixgbe_set_rx_mode(netdev);
3709 ixgbe_restore_vlan(adapter);
3712 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3713 ixgbe_configure_fcoe(adapter);
3715 #endif /* IXGBE_FCOE */
3716 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 adapter->tx_ring[i]->atr_sample_rate =
3719 adapter->atr_sample_rate;
3720 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3721 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3722 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3724 ixgbe_configure_virtualization(adapter);
3726 ixgbe_configure_tx(adapter);
3727 ixgbe_configure_rx(adapter);
3730 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3732 switch (hw->phy.type) {
3733 case ixgbe_phy_sfp_avago:
3734 case ixgbe_phy_sfp_ftl:
3735 case ixgbe_phy_sfp_intel:
3736 case ixgbe_phy_sfp_unknown:
3737 case ixgbe_phy_sfp_passive_tyco:
3738 case ixgbe_phy_sfp_passive_unknown:
3739 case ixgbe_phy_sfp_active_unknown:
3740 case ixgbe_phy_sfp_ftl_active:
3748 * ixgbe_sfp_link_config - set up SFP+ link
3749 * @adapter: pointer to private adapter struct
3751 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3753 struct ixgbe_hw *hw = &adapter->hw;
3755 if (hw->phy.multispeed_fiber) {
3757 * In multispeed fiber setups, the device may not have
3758 * had a physical connection when the driver loaded.
3759 * If that's the case, the initial link configuration
3760 * couldn't get the MAC into 10G or 1G mode, so we'll
3761 * never have a link status change interrupt fire.
3762 * We need to try and force an autonegotiation
3763 * session, then bring up link.
3765 if (hw->mac.ops.setup_sfp)
3766 hw->mac.ops.setup_sfp(hw);
3767 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3768 schedule_work(&adapter->multispeed_fiber_task);
3771 * Direct Attach Cu and non-multispeed fiber modules
3772 * still need to be configured properly prior to
3775 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3776 schedule_work(&adapter->sfp_config_module_task);
3781 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3782 * @hw: pointer to private hardware struct
3784 * Returns 0 on success, negative on failure
3786 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3789 bool negotiation, link_up = false;
3790 u32 ret = IXGBE_ERR_LINK_SETUP;
3792 if (hw->mac.ops.check_link)
3793 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3798 autoneg = hw->phy.autoneg_advertised;
3799 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3800 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3805 if (hw->mac.ops.setup_link)
3806 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3811 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3813 struct ixgbe_hw *hw = &adapter->hw;
3816 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3817 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3819 gpie |= IXGBE_GPIE_EIAME;
3821 * use EIAM to auto-mask when MSI-X interrupt is asserted
3822 * this saves a register write for every interrupt
3824 switch (hw->mac.type) {
3825 case ixgbe_mac_82598EB:
3826 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3828 case ixgbe_mac_82599EB:
3829 case ixgbe_mac_X540:
3831 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3832 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3836 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3837 * specifically only auto mask tx and rx interrupts */
3838 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3841 /* XXX: to interrupt immediately for EICS writes, enable this */
3842 /* gpie |= IXGBE_GPIE_EIMEN; */
3844 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3845 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3846 gpie |= IXGBE_GPIE_VTMODE_64;
3849 /* Enable fan failure interrupt */
3850 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3851 gpie |= IXGBE_SDP1_GPIEN;
3853 if (hw->mac.type == ixgbe_mac_82599EB)
3854 gpie |= IXGBE_SDP1_GPIEN;
3855 gpie |= IXGBE_SDP2_GPIEN;
3857 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3860 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3862 struct ixgbe_hw *hw = &adapter->hw;
3866 ixgbe_get_hw_control(adapter);
3867 ixgbe_setup_gpie(adapter);
3869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3870 ixgbe_configure_msix(adapter);
3872 ixgbe_configure_msi_and_legacy(adapter);
3874 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3875 if (hw->mac.ops.enable_tx_laser &&
3876 ((hw->phy.multispeed_fiber) ||
3877 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3878 (hw->mac.type == ixgbe_mac_82599EB))))
3879 hw->mac.ops.enable_tx_laser(hw);
3881 clear_bit(__IXGBE_DOWN, &adapter->state);
3882 ixgbe_napi_enable_all(adapter);
3884 if (ixgbe_is_sfp(hw)) {
3885 ixgbe_sfp_link_config(adapter);
3887 err = ixgbe_non_sfp_link_config(hw);
3889 e_err(probe, "link_config FAILED %d\n", err);
3892 /* clear any pending interrupts, may auto mask */
3893 IXGBE_READ_REG(hw, IXGBE_EICR);
3894 ixgbe_irq_enable(adapter, true, true);
3897 * If this adapter has a fan, check to see if we had a failure
3898 * before we enabled the interrupt.
3900 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3901 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3902 if (esdp & IXGBE_ESDP_SDP1)
3903 e_crit(drv, "Fan has stopped, replace the adapter\n");
3907 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3908 * arrived before interrupts were enabled but after probe. Such
3909 * devices wouldn't have their type identified yet. We need to
3910 * kick off the SFP+ module setup first, then try to bring up link.
3911 * If we're not hot-pluggable SFP+, we just need to configure link
3914 if (hw->phy.type == ixgbe_phy_none)
3915 schedule_work(&adapter->sfp_config_module_task);
3917 /* enable transmits */
3918 netif_tx_start_all_queues(adapter->netdev);
3920 /* bring the link up in the watchdog, this could race with our first
3921 * link up interrupt but shouldn't be a problem */
3922 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3923 adapter->link_check_timeout = jiffies;
3924 mod_timer(&adapter->watchdog_timer, jiffies);
3926 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3927 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3928 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3929 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3934 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3936 WARN_ON(in_interrupt());
3937 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3939 ixgbe_down(adapter);
3941 * If SR-IOV enabled then wait a bit before bringing the adapter
3942 * back up to give the VFs time to respond to the reset. The
3943 * two second wait is based upon the watchdog timer cycle in
3946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3949 clear_bit(__IXGBE_RESETTING, &adapter->state);
3952 int ixgbe_up(struct ixgbe_adapter *adapter)
3954 /* hardware has been reset, we need to reload some things */
3955 ixgbe_configure(adapter);
3957 return ixgbe_up_complete(adapter);
3960 void ixgbe_reset(struct ixgbe_adapter *adapter)
3962 struct ixgbe_hw *hw = &adapter->hw;
3965 err = hw->mac.ops.init_hw(hw);
3968 case IXGBE_ERR_SFP_NOT_PRESENT:
3970 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3971 e_dev_err("master disable timed out\n");
3973 case IXGBE_ERR_EEPROM_VERSION:
3974 /* We are running on a pre-production device, log a warning */
3975 e_dev_warn("This device is a pre-production adapter/LOM. "
3976 "Please be aware there may be issuesassociated with "
3977 "your hardware. If you are experiencing problems "
3978 "please contact your Intel or hardware "
3979 "representative who provided you with this "
3983 e_dev_err("Hardware Error: %d\n", err);
3986 /* reprogram the RAR[0] in case user changed it. */
3987 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3992 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3993 * @rx_ring: ring to free buffers from
3995 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3997 struct device *dev = rx_ring->dev;
4001 /* ring already cleared, nothing to do */
4002 if (!rx_ring->rx_buffer_info)
4005 /* Free all the Rx ring sk_buffs */
4006 for (i = 0; i < rx_ring->count; i++) {
4007 struct ixgbe_rx_buffer *rx_buffer_info;
4009 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4010 if (rx_buffer_info->dma) {
4011 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4012 rx_ring->rx_buf_len,
4014 rx_buffer_info->dma = 0;
4016 if (rx_buffer_info->skb) {
4017 struct sk_buff *skb = rx_buffer_info->skb;
4018 rx_buffer_info->skb = NULL;
4020 struct sk_buff *this = skb;
4021 if (IXGBE_RSC_CB(this)->delay_unmap) {
4022 dma_unmap_single(dev,
4023 IXGBE_RSC_CB(this)->dma,
4024 rx_ring->rx_buf_len,
4026 IXGBE_RSC_CB(this)->dma = 0;
4027 IXGBE_RSC_CB(skb)->delay_unmap = false;
4030 dev_kfree_skb(this);
4033 if (!rx_buffer_info->page)
4035 if (rx_buffer_info->page_dma) {
4036 dma_unmap_page(dev, rx_buffer_info->page_dma,
4037 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4038 rx_buffer_info->page_dma = 0;
4040 put_page(rx_buffer_info->page);
4041 rx_buffer_info->page = NULL;
4042 rx_buffer_info->page_offset = 0;
4045 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4046 memset(rx_ring->rx_buffer_info, 0, size);
4048 /* Zero out the descriptor ring */
4049 memset(rx_ring->desc, 0, rx_ring->size);
4051 rx_ring->next_to_clean = 0;
4052 rx_ring->next_to_use = 0;
4056 * ixgbe_clean_tx_ring - Free Tx Buffers
4057 * @tx_ring: ring to be cleaned
4059 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4061 struct ixgbe_tx_buffer *tx_buffer_info;
4065 /* ring already cleared, nothing to do */
4066 if (!tx_ring->tx_buffer_info)
4069 /* Free all the Tx ring sk_buffs */
4070 for (i = 0; i < tx_ring->count; i++) {
4071 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4072 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4075 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4076 memset(tx_ring->tx_buffer_info, 0, size);
4078 /* Zero out the descriptor ring */
4079 memset(tx_ring->desc, 0, tx_ring->size);
4081 tx_ring->next_to_use = 0;
4082 tx_ring->next_to_clean = 0;
4086 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4087 * @adapter: board private structure
4089 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4093 for (i = 0; i < adapter->num_rx_queues; i++)
4094 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4098 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4099 * @adapter: board private structure
4101 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4105 for (i = 0; i < adapter->num_tx_queues; i++)
4106 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4109 void ixgbe_down(struct ixgbe_adapter *adapter)
4111 struct net_device *netdev = adapter->netdev;
4112 struct ixgbe_hw *hw = &adapter->hw;
4116 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4118 /* signal that we are down to the interrupt handler */
4119 set_bit(__IXGBE_DOWN, &adapter->state);
4121 /* disable receive for all VFs and wait one second */
4122 if (adapter->num_vfs) {
4123 /* ping all the active vfs to let them know we are going down */
4124 ixgbe_ping_all_vfs(adapter);
4126 /* Disable all VFTE/VFRE TX/RX */
4127 ixgbe_disable_tx_rx(adapter);
4129 /* Mark all the VFs as inactive */
4130 for (i = 0 ; i < adapter->num_vfs; i++)
4131 adapter->vfinfo[i].clear_to_send = 0;
4134 /* disable receives */
4135 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4136 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4138 /* disable all enabled rx queues */
4139 for (i = 0; i < adapter->num_rx_queues; i++)
4140 /* this call also flushes the previous write */
4141 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4145 netif_tx_stop_all_queues(netdev);
4147 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4148 del_timer_sync(&adapter->sfp_timer);
4149 del_timer_sync(&adapter->watchdog_timer);
4150 cancel_work_sync(&adapter->watchdog_task);
4152 netif_carrier_off(netdev);
4153 netif_tx_disable(netdev);
4155 ixgbe_irq_disable(adapter);
4157 ixgbe_napi_disable_all(adapter);
4159 /* Cleanup the affinity_hint CPU mask memory and callback */
4160 for (i = 0; i < num_q_vectors; i++) {
4161 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4162 /* clear the affinity_mask in the IRQ descriptor */
4163 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4164 /* release the CPU mask memory */
4165 free_cpumask_var(q_vector->affinity_mask);
4168 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4169 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4170 cancel_work_sync(&adapter->fdir_reinit_task);
4172 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4173 cancel_work_sync(&adapter->check_overtemp_task);
4175 /* disable transmits in the hardware now that interrupts are off */
4176 for (i = 0; i < adapter->num_tx_queues; i++) {
4177 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4178 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4179 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4180 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4182 /* Disable the Tx DMA engine on 82599 */
4183 switch (hw->mac.type) {
4184 case ixgbe_mac_82599EB:
4185 case ixgbe_mac_X540:
4186 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4187 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4188 ~IXGBE_DMATXCTL_TE));
4194 /* clear n-tuple filters that are cached */
4195 ethtool_ntuple_flush(netdev);
4197 if (!pci_channel_offline(adapter->pdev))
4198 ixgbe_reset(adapter);
4200 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4201 if (hw->mac.ops.disable_tx_laser &&
4202 ((hw->phy.multispeed_fiber) ||
4203 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4204 (hw->mac.type == ixgbe_mac_82599EB))))
4205 hw->mac.ops.disable_tx_laser(hw);
4207 ixgbe_clean_all_tx_rings(adapter);
4208 ixgbe_clean_all_rx_rings(adapter);
4210 #ifdef CONFIG_IXGBE_DCA
4211 /* since we reset the hardware DCA settings were cleared */
4212 ixgbe_setup_dca(adapter);
4217 * ixgbe_poll - NAPI Rx polling callback
4218 * @napi: structure for representing this polling device
4219 * @budget: how many packets driver is allowed to clean
4221 * This function is used for legacy and MSI, NAPI mode
4223 static int ixgbe_poll(struct napi_struct *napi, int budget)
4225 struct ixgbe_q_vector *q_vector =
4226 container_of(napi, struct ixgbe_q_vector, napi);
4227 struct ixgbe_adapter *adapter = q_vector->adapter;
4228 int tx_clean_complete, work_done = 0;
4230 #ifdef CONFIG_IXGBE_DCA
4231 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4232 ixgbe_update_dca(q_vector);
4235 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4236 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4238 if (!tx_clean_complete)
4241 /* If budget not fully consumed, exit the polling mode */
4242 if (work_done < budget) {
4243 napi_complete(napi);
4244 if (adapter->rx_itr_setting & 1)
4245 ixgbe_set_itr(adapter);
4246 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4247 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4253 * ixgbe_tx_timeout - Respond to a Tx Hang
4254 * @netdev: network interface device structure
4256 static void ixgbe_tx_timeout(struct net_device *netdev)
4258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4260 adapter->tx_timeout_count++;
4262 /* Do the reset outside of interrupt context */
4263 schedule_work(&adapter->reset_task);
4266 static void ixgbe_reset_task(struct work_struct *work)
4268 struct ixgbe_adapter *adapter;
4269 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4271 /* If we're already down or resetting, just bail */
4272 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4273 test_bit(__IXGBE_RESETTING, &adapter->state))
4276 ixgbe_dump(adapter);
4277 netdev_err(adapter->netdev, "Reset adapter\n");
4278 ixgbe_reinit_locked(adapter);
4282 * ixgbe_set_rss_queues: Allocate queues for RSS
4283 * @adapter: board private structure to initialize
4285 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4286 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4289 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4292 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4294 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4296 adapter->num_rx_queues = f->indices;
4297 adapter->num_tx_queues = f->indices;
4307 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4308 * @adapter: board private structure to initialize
4310 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4311 * to the original CPU that initiated the Tx session. This runs in addition
4312 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4313 * Rx load across CPUs using RSS.
4316 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4319 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4321 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4324 /* Flow Director must have RSS enabled */
4325 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4326 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4327 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4328 adapter->num_tx_queues = f_fdir->indices;
4329 adapter->num_rx_queues = f_fdir->indices;
4332 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4333 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4340 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4341 * @adapter: board private structure to initialize
4343 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4344 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4345 * rx queues out of the max number of rx queues, instead, it is used as the
4346 * index of the first rx queue used by FCoE.
4349 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4351 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4353 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4356 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4357 #ifdef CONFIG_IXGBE_DCB
4359 struct net_device *dev = adapter->netdev;
4361 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4362 f->indices = dev->tc_to_txq[tc].count;
4363 f->mask = dev->tc_to_txq[tc].offset;
4366 f->indices = min((int)num_online_cpus(), f->indices);
4368 adapter->num_rx_queues = 1;
4369 adapter->num_tx_queues = 1;
4371 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4372 e_info(probe, "FCoE enabled with RSS\n");
4373 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4374 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4375 ixgbe_set_fdir_queues(adapter);
4377 ixgbe_set_rss_queues(adapter);
4379 /* adding FCoE rx rings to the end */
4380 f->mask = adapter->num_rx_queues;
4381 adapter->num_rx_queues += f->indices;
4382 adapter->num_tx_queues += f->indices;
4387 #endif /* IXGBE_FCOE */
4389 #ifdef CONFIG_IXGBE_DCB
4390 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4393 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4396 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4400 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4401 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4406 adapter->num_rx_queues = f->indices;
4407 adapter->num_tx_queues = f->indices;
4411 /* FCoE enabled queues require special configuration done through
4412 * configure_fcoe() and others. Here we map FCoE indices onto the
4413 * DCB queue pairs allowing FCoE to own configuration later.
4415 ixgbe_set_fcoe_queues(adapter);
4423 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4424 * @adapter: board private structure to initialize
4426 * IOV doesn't actually use anything, so just NAK the
4427 * request for now and let the other queue routines
4428 * figure out what to do.
4430 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4436 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4437 * @adapter: board private structure to initialize
4439 * This is the top level queue allocation routine. The order here is very
4440 * important, starting with the "most" number of features turned on at once,
4441 * and ending with the smallest set of features. This way large combinations
4442 * can be allocated if they're turned on, and smaller combinations are the
4443 * fallthrough conditions.
4446 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4448 /* Start with base case */
4449 adapter->num_rx_queues = 1;
4450 adapter->num_tx_queues = 1;
4451 adapter->num_rx_pools = adapter->num_rx_queues;
4452 adapter->num_rx_queues_per_pool = 1;
4454 if (ixgbe_set_sriov_queues(adapter))
4457 #ifdef CONFIG_IXGBE_DCB
4458 if (ixgbe_set_dcb_queues(adapter))
4463 if (ixgbe_set_fcoe_queues(adapter))
4466 #endif /* IXGBE_FCOE */
4467 if (ixgbe_set_fdir_queues(adapter))
4470 if (ixgbe_set_rss_queues(adapter))
4473 /* fallback to base case */
4474 adapter->num_rx_queues = 1;
4475 adapter->num_tx_queues = 1;
4478 /* Notify the stack of the (possibly) reduced queue counts. */
4479 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4480 return netif_set_real_num_rx_queues(adapter->netdev,
4481 adapter->num_rx_queues);
4484 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4487 int err, vector_threshold;
4489 /* We'll want at least 3 (vector_threshold):
4492 * 3) Other (Link Status Change, etc.)
4493 * 4) TCP Timer (optional)
4495 vector_threshold = MIN_MSIX_COUNT;
4497 /* The more we get, the more we will assign to Tx/Rx Cleanup
4498 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4499 * Right now, we simply care about how many we'll get; we'll
4500 * set them up later while requesting irq's.
4502 while (vectors >= vector_threshold) {
4503 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4505 if (!err) /* Success in acquiring all requested vectors. */
4508 vectors = 0; /* Nasty failure, quit now */
4509 else /* err == number of vectors we should try again with */
4513 if (vectors < vector_threshold) {
4514 /* Can't allocate enough MSI-X interrupts? Oh well.
4515 * This just means we'll go with either a single MSI
4516 * vector or fall back to legacy interrupts.
4518 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4519 "Unable to allocate MSI-X interrupts\n");
4520 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4521 kfree(adapter->msix_entries);
4522 adapter->msix_entries = NULL;
4524 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4526 * Adjust for only the vectors we'll use, which is minimum
4527 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4528 * vectors we were allocated.
4530 adapter->num_msix_vectors = min(vectors,
4531 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4536 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4537 * @adapter: board private structure to initialize
4539 * Cache the descriptor ring offsets for RSS to the assigned rings.
4542 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4546 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4549 for (i = 0; i < adapter->num_rx_queues; i++)
4550 adapter->rx_ring[i]->reg_idx = i;
4551 for (i = 0; i < adapter->num_tx_queues; i++)
4552 adapter->tx_ring[i]->reg_idx = i;
4557 #ifdef CONFIG_IXGBE_DCB
4559 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4560 void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4561 unsigned int *tx, unsigned int *rx)
4563 struct net_device *dev = adapter->netdev;
4564 struct ixgbe_hw *hw = &adapter->hw;
4565 u8 num_tcs = netdev_get_num_tc(dev);
4570 switch (hw->mac.type) {
4571 case ixgbe_mac_82598EB:
4575 case ixgbe_mac_82599EB:
4576 case ixgbe_mac_X540:
4581 } else if (tc < 5) {
4582 *tx = ((tc + 2) << 4);
4584 } else if (tc < num_tcs) {
4585 *tx = ((tc + 8) << 3);
4588 } else if (num_tcs == 4) {
4613 #define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4615 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4618 * @netdev: net device to configure
4619 * @tc: number of traffic classes to enable
4621 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4624 unsigned int q, offset = 0;
4627 netdev_reset_tc(dev);
4629 struct ixgbe_adapter *adapter = netdev_priv(dev);
4631 /* Hardware supports up to 8 traffic classes */
4632 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4635 /* Partition Tx queues evenly amongst traffic classes */
4636 for (i = 0; i < tc; i++) {
4637 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4638 netdev_set_prio_tc_map(dev, i, i);
4639 netdev_set_tc_queue(dev, i, q, offset);
4643 /* This enables multiple traffic class support in the hardware
4644 * which defaults to strict priority transmission by default.
4645 * If traffic classes are already enabled perhaps through DCB
4646 * code path then existing configuration will be used.
4648 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4649 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4650 struct ieee_ets ets = {
4651 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4653 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4655 dev->dcbnl_ops->setdcbx(dev, mode);
4656 dev->dcbnl_ops->ieee_setets(dev, &ets);
4663 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4664 * @adapter: board private structure to initialize
4666 * Cache the descriptor ring offsets for DCB to the assigned rings.
4669 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4671 struct net_device *dev = adapter->netdev;
4673 u8 num_tcs = netdev_get_num_tc(dev);
4675 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4678 for (i = 0, k = 0; i < num_tcs; i++) {
4679 unsigned int tx_s, rx_s;
4680 u16 count = dev->tc_to_txq[i].count;
4682 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4683 for (j = 0; j < count; j++, k++) {
4684 adapter->tx_ring[k]->reg_idx = tx_s + j;
4685 adapter->rx_ring[k]->reg_idx = rx_s + j;
4686 adapter->tx_ring[k]->dcb_tc = i;
4687 adapter->rx_ring[k]->dcb_tc = i;
4696 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4697 * @adapter: board private structure to initialize
4699 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4702 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4707 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4708 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4709 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4710 for (i = 0; i < adapter->num_rx_queues; i++)
4711 adapter->rx_ring[i]->reg_idx = i;
4712 for (i = 0; i < adapter->num_tx_queues; i++)
4713 adapter->tx_ring[i]->reg_idx = i;
4722 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4723 * @adapter: board private structure to initialize
4725 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4728 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4730 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4732 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4734 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4737 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4738 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4739 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4740 ixgbe_cache_ring_fdir(adapter);
4742 ixgbe_cache_ring_rss(adapter);
4744 fcoe_rx_i = f->mask;
4745 fcoe_tx_i = f->mask;
4747 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4748 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4749 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4754 #endif /* IXGBE_FCOE */
4756 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4757 * @adapter: board private structure to initialize
4759 * SR-IOV doesn't use any descriptor rings but changes the default if
4760 * no other mapping is used.
4763 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4765 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4766 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4767 if (adapter->num_vfs)
4774 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4775 * @adapter: board private structure to initialize
4777 * Once we know the feature-set enabled for the device, we'll cache
4778 * the register offset the descriptor ring is assigned to.
4780 * Note, the order the various feature calls is important. It must start with
4781 * the "most" features enabled at the same time, then trickle down to the
4782 * least amount of features turned on at once.
4784 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4786 /* start with default case */
4787 adapter->rx_ring[0]->reg_idx = 0;
4788 adapter->tx_ring[0]->reg_idx = 0;
4790 if (ixgbe_cache_ring_sriov(adapter))
4793 #ifdef CONFIG_IXGBE_DCB
4794 if (ixgbe_cache_ring_dcb(adapter))
4799 if (ixgbe_cache_ring_fcoe(adapter))
4801 #endif /* IXGBE_FCOE */
4803 if (ixgbe_cache_ring_fdir(adapter))
4806 if (ixgbe_cache_ring_rss(adapter))
4811 * ixgbe_alloc_queues - Allocate memory for all rings
4812 * @adapter: board private structure to initialize
4814 * We allocate one ring per queue at run-time since we don't know the
4815 * number of queues at compile-time. The polling_netdev array is
4816 * intended for Multiqueue, but should work fine with a single queue.
4818 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4820 int rx = 0, tx = 0, nid = adapter->node;
4822 if (nid < 0 || !node_online(nid))
4823 nid = first_online_node;
4825 for (; tx < adapter->num_tx_queues; tx++) {
4826 struct ixgbe_ring *ring;
4828 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4830 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4832 goto err_allocation;
4833 ring->count = adapter->tx_ring_count;
4834 ring->queue_index = tx;
4835 ring->numa_node = nid;
4836 ring->dev = &adapter->pdev->dev;
4837 ring->netdev = adapter->netdev;
4839 adapter->tx_ring[tx] = ring;
4842 for (; rx < adapter->num_rx_queues; rx++) {
4843 struct ixgbe_ring *ring;
4845 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4847 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4849 goto err_allocation;
4850 ring->count = adapter->rx_ring_count;
4851 ring->queue_index = rx;
4852 ring->numa_node = nid;
4853 ring->dev = &adapter->pdev->dev;
4854 ring->netdev = adapter->netdev;
4856 adapter->rx_ring[rx] = ring;
4859 ixgbe_cache_ring_register(adapter);
4865 kfree(adapter->tx_ring[--tx]);
4868 kfree(adapter->rx_ring[--rx]);
4873 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4874 * @adapter: board private structure to initialize
4876 * Attempt to configure the interrupts using the best available
4877 * capabilities of the hardware and the kernel.
4879 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4881 struct ixgbe_hw *hw = &adapter->hw;
4883 int vector, v_budget;
4886 * It's easy to be greedy for MSI-X vectors, but it really
4887 * doesn't do us much good if we have a lot more vectors
4888 * than CPU's. So let's be conservative and only ask for
4889 * (roughly) the same number of vectors as there are CPU's.
4891 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4892 (int)num_online_cpus()) + NON_Q_VECTORS;
4895 * At the same time, hardware can only support a maximum of
4896 * hw.mac->max_msix_vectors vectors. With features
4897 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4898 * descriptor queues supported by our device. Thus, we cap it off in
4899 * those rare cases where the cpu count also exceeds our vector limit.
4901 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4903 /* A failure in MSI-X entry allocation isn't fatal, but it does
4904 * mean we disable MSI-X capabilities of the adapter. */
4905 adapter->msix_entries = kcalloc(v_budget,
4906 sizeof(struct msix_entry), GFP_KERNEL);
4907 if (adapter->msix_entries) {
4908 for (vector = 0; vector < v_budget; vector++)
4909 adapter->msix_entries[vector].entry = vector;
4911 ixgbe_acquire_msix_vectors(adapter, v_budget);
4913 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4917 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4918 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4919 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4920 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4922 "Flow Director is not supported while multiple "
4923 "queues are disabled. Disabling Flow Director\n");
4925 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4926 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4927 adapter->atr_sample_rate = 0;
4928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4929 ixgbe_disable_sriov(adapter);
4931 err = ixgbe_set_num_queues(adapter);
4935 err = pci_enable_msi(adapter->pdev);
4937 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4939 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4940 "Unable to allocate MSI interrupt, "
4941 "falling back to legacy. Error: %d\n", err);
4951 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4952 * @adapter: board private structure to initialize
4954 * We allocate one q_vector per queue interrupt. If allocation fails we
4957 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4959 int q_idx, num_q_vectors;
4960 struct ixgbe_q_vector *q_vector;
4961 int (*poll)(struct napi_struct *, int);
4963 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4964 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4965 poll = &ixgbe_clean_rxtx_many;
4971 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4972 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4973 GFP_KERNEL, adapter->node);
4975 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4979 q_vector->adapter = adapter;
4980 if (q_vector->txr_count && !q_vector->rxr_count)
4981 q_vector->eitr = adapter->tx_eitr_param;
4983 q_vector->eitr = adapter->rx_eitr_param;
4984 q_vector->v_idx = q_idx;
4985 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4986 adapter->q_vector[q_idx] = q_vector;
4994 q_vector = adapter->q_vector[q_idx];
4995 netif_napi_del(&q_vector->napi);
4997 adapter->q_vector[q_idx] = NULL;
5003 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5004 * @adapter: board private structure to initialize
5006 * This function frees the memory allocated to the q_vectors. In addition if
5007 * NAPI is enabled it will delete any references to the NAPI struct prior
5008 * to freeing the q_vector.
5010 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5012 int q_idx, num_q_vectors;
5014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5015 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5019 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5020 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5021 adapter->q_vector[q_idx] = NULL;
5022 netif_napi_del(&q_vector->napi);
5027 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5029 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5030 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5031 pci_disable_msix(adapter->pdev);
5032 kfree(adapter->msix_entries);
5033 adapter->msix_entries = NULL;
5034 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5035 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5036 pci_disable_msi(adapter->pdev);
5041 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5042 * @adapter: board private structure to initialize
5044 * We determine which interrupt scheme to use based on...
5045 * - Kernel support (MSI, MSI-X)
5046 * - which can be user-defined (via MODULE_PARAM)
5047 * - Hardware queue count (num_*_queues)
5048 * - defined by miscellaneous hardware support/features (RSS, etc.)
5050 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5054 /* Number of supported queues */
5055 err = ixgbe_set_num_queues(adapter);
5059 err = ixgbe_set_interrupt_capability(adapter);
5061 e_dev_err("Unable to setup interrupt capabilities\n");
5062 goto err_set_interrupt;
5065 err = ixgbe_alloc_q_vectors(adapter);
5067 e_dev_err("Unable to allocate memory for queue vectors\n");
5068 goto err_alloc_q_vectors;
5071 err = ixgbe_alloc_queues(adapter);
5073 e_dev_err("Unable to allocate memory for queues\n");
5074 goto err_alloc_queues;
5077 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5078 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5079 adapter->num_rx_queues, adapter->num_tx_queues);
5081 set_bit(__IXGBE_DOWN, &adapter->state);
5086 ixgbe_free_q_vectors(adapter);
5087 err_alloc_q_vectors:
5088 ixgbe_reset_interrupt_capability(adapter);
5093 static void ring_free_rcu(struct rcu_head *head)
5095 kfree(container_of(head, struct ixgbe_ring, rcu));
5099 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5100 * @adapter: board private structure to clear interrupt scheme on
5102 * We go through and clear interrupt specific resources and reset the structure
5103 * to pre-load conditions
5105 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5109 for (i = 0; i < adapter->num_tx_queues; i++) {
5110 kfree(adapter->tx_ring[i]);
5111 adapter->tx_ring[i] = NULL;
5113 for (i = 0; i < adapter->num_rx_queues; i++) {
5114 struct ixgbe_ring *ring = adapter->rx_ring[i];
5116 /* ixgbe_get_stats64() might access this ring, we must wait
5117 * a grace period before freeing it.
5119 call_rcu(&ring->rcu, ring_free_rcu);
5120 adapter->rx_ring[i] = NULL;
5123 adapter->num_tx_queues = 0;
5124 adapter->num_rx_queues = 0;
5126 ixgbe_free_q_vectors(adapter);
5127 ixgbe_reset_interrupt_capability(adapter);
5131 * ixgbe_sfp_timer - worker thread to find a missing module
5132 * @data: pointer to our adapter struct
5134 static void ixgbe_sfp_timer(unsigned long data)
5136 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5139 * Do the sfp_timer outside of interrupt context due to the
5140 * delays that sfp+ detection requires
5142 schedule_work(&adapter->sfp_task);
5146 * ixgbe_sfp_task - worker thread to find a missing module
5147 * @work: pointer to work_struct containing our data
5149 static void ixgbe_sfp_task(struct work_struct *work)
5151 struct ixgbe_adapter *adapter = container_of(work,
5152 struct ixgbe_adapter,
5154 struct ixgbe_hw *hw = &adapter->hw;
5156 if ((hw->phy.type == ixgbe_phy_nl) &&
5157 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5158 s32 ret = hw->phy.ops.identify_sfp(hw);
5159 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5161 ret = hw->phy.ops.reset(hw);
5162 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5163 e_dev_err("failed to initialize because an unsupported "
5164 "SFP+ module type was detected.\n");
5165 e_dev_err("Reload the driver after installing a "
5166 "supported module.\n");
5167 unregister_netdev(adapter->netdev);
5169 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5171 /* don't need this routine any more */
5172 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5176 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5177 mod_timer(&adapter->sfp_timer,
5178 round_jiffies(jiffies + (2 * HZ)));
5182 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5183 * @adapter: board private structure to initialize
5185 * ixgbe_sw_init initializes the Adapter private data structure.
5186 * Fields are initialized based on PCI device information and
5187 * OS network device settings (MTU size).
5189 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5191 struct ixgbe_hw *hw = &adapter->hw;
5192 struct pci_dev *pdev = adapter->pdev;
5193 struct net_device *dev = adapter->netdev;
5195 #ifdef CONFIG_IXGBE_DCB
5197 struct tc_configuration *tc;
5199 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5201 /* PCI config space info */
5203 hw->vendor_id = pdev->vendor;
5204 hw->device_id = pdev->device;
5205 hw->revision_id = pdev->revision;
5206 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5207 hw->subsystem_device_id = pdev->subsystem_device;
5209 /* Set capability flags */
5210 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5211 adapter->ring_feature[RING_F_RSS].indices = rss;
5212 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5213 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5214 switch (hw->mac.type) {
5215 case ixgbe_mac_82598EB:
5216 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5217 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5218 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5220 case ixgbe_mac_82599EB:
5221 case ixgbe_mac_X540:
5222 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5223 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5224 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5225 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5226 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5227 /* n-tuple support exists, always init our spinlock */
5228 spin_lock_init(&adapter->fdir_perfect_lock);
5229 /* Flow Director hash filters enabled */
5230 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5231 adapter->atr_sample_rate = 20;
5232 adapter->ring_feature[RING_F_FDIR].indices =
5233 IXGBE_MAX_FDIR_INDICES;
5234 adapter->fdir_pballoc = 0;
5236 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5237 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5238 adapter->ring_feature[RING_F_FCOE].indices = 0;
5239 #ifdef CONFIG_IXGBE_DCB
5240 /* Default traffic class to use for FCoE */
5241 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5242 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5244 #endif /* IXGBE_FCOE */
5250 #ifdef CONFIG_IXGBE_DCB
5251 /* Configure DCB traffic classes */
5252 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5253 tc = &adapter->dcb_cfg.tc_config[j];
5254 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5255 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5256 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5257 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5258 tc->dcb_pfc = pfc_disabled;
5260 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5261 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5262 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5263 adapter->dcb_cfg.pfc_mode_enable = false;
5264 adapter->dcb_set_bitmap = 0x00;
5265 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5266 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5271 /* default flow control settings */
5272 hw->fc.requested_mode = ixgbe_fc_full;
5273 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5275 adapter->last_lfc_mode = hw->fc.current_mode;
5277 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5278 hw->fc.low_water = FC_LOW_WATER(max_frame);
5279 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5280 hw->fc.send_xon = true;
5281 hw->fc.disable_fc_autoneg = false;
5283 /* enable itr by default in dynamic mode */
5284 adapter->rx_itr_setting = 1;
5285 adapter->rx_eitr_param = 20000;
5286 adapter->tx_itr_setting = 1;
5287 adapter->tx_eitr_param = 10000;
5289 /* set defaults for eitr in MegaBytes */
5290 adapter->eitr_low = 10;
5291 adapter->eitr_high = 20;
5293 /* set default ring sizes */
5294 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5295 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5297 /* initialize eeprom parameters */
5298 if (ixgbe_init_eeprom_params_generic(hw)) {
5299 e_dev_err("EEPROM initialization failed\n");
5303 /* enable rx csum by default */
5304 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5306 /* get assigned NUMA node */
5307 adapter->node = dev_to_node(&pdev->dev);
5309 set_bit(__IXGBE_DOWN, &adapter->state);
5315 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5316 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5318 * Return 0 on success, negative on failure
5320 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5322 struct device *dev = tx_ring->dev;
5325 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5326 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5327 if (!tx_ring->tx_buffer_info)
5328 tx_ring->tx_buffer_info = vzalloc(size);
5329 if (!tx_ring->tx_buffer_info)
5332 /* round up to nearest 4K */
5333 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5334 tx_ring->size = ALIGN(tx_ring->size, 4096);
5336 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5337 &tx_ring->dma, GFP_KERNEL);
5341 tx_ring->next_to_use = 0;
5342 tx_ring->next_to_clean = 0;
5343 tx_ring->work_limit = tx_ring->count;
5347 vfree(tx_ring->tx_buffer_info);
5348 tx_ring->tx_buffer_info = NULL;
5349 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5354 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5355 * @adapter: board private structure
5357 * If this function returns with an error, then it's possible one or
5358 * more of the rings is populated (while the rest are not). It is the
5359 * callers duty to clean those orphaned rings.
5361 * Return 0 on success, negative on failure
5363 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5367 for (i = 0; i < adapter->num_tx_queues; i++) {
5368 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5371 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5379 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5380 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5382 * Returns 0 on success, negative on failure
5384 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5386 struct device *dev = rx_ring->dev;
5389 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5390 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5391 if (!rx_ring->rx_buffer_info)
5392 rx_ring->rx_buffer_info = vzalloc(size);
5393 if (!rx_ring->rx_buffer_info)
5396 /* Round up to nearest 4K */
5397 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5398 rx_ring->size = ALIGN(rx_ring->size, 4096);
5400 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5401 &rx_ring->dma, GFP_KERNEL);
5406 rx_ring->next_to_clean = 0;
5407 rx_ring->next_to_use = 0;
5411 vfree(rx_ring->rx_buffer_info);
5412 rx_ring->rx_buffer_info = NULL;
5413 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5418 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5419 * @adapter: board private structure
5421 * If this function returns with an error, then it's possible one or
5422 * more of the rings is populated (while the rest are not). It is the
5423 * callers duty to clean those orphaned rings.
5425 * Return 0 on success, negative on failure
5427 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5431 for (i = 0; i < adapter->num_rx_queues; i++) {
5432 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5435 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5443 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5444 * @tx_ring: Tx descriptor ring for a specific queue
5446 * Free all transmit software resources
5448 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5450 ixgbe_clean_tx_ring(tx_ring);
5452 vfree(tx_ring->tx_buffer_info);
5453 tx_ring->tx_buffer_info = NULL;
5455 /* if not set, then don't free */
5459 dma_free_coherent(tx_ring->dev, tx_ring->size,
5460 tx_ring->desc, tx_ring->dma);
5462 tx_ring->desc = NULL;
5466 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5467 * @adapter: board private structure
5469 * Free all transmit software resources
5471 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5475 for (i = 0; i < adapter->num_tx_queues; i++)
5476 if (adapter->tx_ring[i]->desc)
5477 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5481 * ixgbe_free_rx_resources - Free Rx Resources
5482 * @rx_ring: ring to clean the resources from
5484 * Free all receive software resources
5486 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5488 ixgbe_clean_rx_ring(rx_ring);
5490 vfree(rx_ring->rx_buffer_info);
5491 rx_ring->rx_buffer_info = NULL;
5493 /* if not set, then don't free */
5497 dma_free_coherent(rx_ring->dev, rx_ring->size,
5498 rx_ring->desc, rx_ring->dma);
5500 rx_ring->desc = NULL;
5504 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5505 * @adapter: board private structure
5507 * Free all receive software resources
5509 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5513 for (i = 0; i < adapter->num_rx_queues; i++)
5514 if (adapter->rx_ring[i]->desc)
5515 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5519 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5520 * @netdev: network interface device structure
5521 * @new_mtu: new value for maximum frame size
5523 * Returns 0 on success, negative on failure
5525 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5528 struct ixgbe_hw *hw = &adapter->hw;
5529 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5531 /* MTU < 68 is an error and causes problems on some kernels */
5532 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5533 hw->mac.type != ixgbe_mac_X540) {
5534 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5537 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5541 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5542 /* must set new MTU before calling down or up */
5543 netdev->mtu = new_mtu;
5545 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5546 hw->fc.low_water = FC_LOW_WATER(max_frame);
5548 if (netif_running(netdev))
5549 ixgbe_reinit_locked(adapter);
5555 * ixgbe_open - Called when a network interface is made active
5556 * @netdev: network interface device structure
5558 * Returns 0 on success, negative value on failure
5560 * The open entry point is called when a network interface is made
5561 * active by the system (IFF_UP). At this point all resources needed
5562 * for transmit and receive operations are allocated, the interrupt
5563 * handler is registered with the OS, the watchdog timer is started,
5564 * and the stack is notified that the interface is ready.
5566 static int ixgbe_open(struct net_device *netdev)
5568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5571 /* disallow open during test */
5572 if (test_bit(__IXGBE_TESTING, &adapter->state))
5575 netif_carrier_off(netdev);
5577 /* allocate transmit descriptors */
5578 err = ixgbe_setup_all_tx_resources(adapter);
5582 /* allocate receive descriptors */
5583 err = ixgbe_setup_all_rx_resources(adapter);
5587 ixgbe_configure(adapter);
5589 err = ixgbe_request_irq(adapter);
5593 err = ixgbe_up_complete(adapter);
5597 netif_tx_start_all_queues(netdev);
5602 ixgbe_release_hw_control(adapter);
5603 ixgbe_free_irq(adapter);
5606 ixgbe_free_all_rx_resources(adapter);
5608 ixgbe_free_all_tx_resources(adapter);
5609 ixgbe_reset(adapter);
5615 * ixgbe_close - Disables a network interface
5616 * @netdev: network interface device structure
5618 * Returns 0, this is not allowed to fail
5620 * The close entry point is called when an interface is de-activated
5621 * by the OS. The hardware is still under the drivers control, but
5622 * needs to be disabled. A global MAC reset is issued to stop the
5623 * hardware, and all transmit and receive resources are freed.
5625 static int ixgbe_close(struct net_device *netdev)
5627 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5629 ixgbe_down(adapter);
5630 ixgbe_free_irq(adapter);
5632 ixgbe_free_all_tx_resources(adapter);
5633 ixgbe_free_all_rx_resources(adapter);
5635 ixgbe_release_hw_control(adapter);
5641 static int ixgbe_resume(struct pci_dev *pdev)
5643 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5644 struct net_device *netdev = adapter->netdev;
5647 pci_set_power_state(pdev, PCI_D0);
5648 pci_restore_state(pdev);
5650 * pci_restore_state clears dev->state_saved so call
5651 * pci_save_state to restore it.
5653 pci_save_state(pdev);
5655 err = pci_enable_device_mem(pdev);
5657 e_dev_err("Cannot enable PCI device from suspend\n");
5660 pci_set_master(pdev);
5662 pci_wake_from_d3(pdev, false);
5664 err = ixgbe_init_interrupt_scheme(adapter);
5666 e_dev_err("Cannot initialize interrupts for device\n");
5670 ixgbe_reset(adapter);
5672 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5674 if (netif_running(netdev)) {
5675 err = ixgbe_open(netdev);
5680 netif_device_attach(netdev);
5684 #endif /* CONFIG_PM */
5686 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5688 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5689 struct net_device *netdev = adapter->netdev;
5690 struct ixgbe_hw *hw = &adapter->hw;
5692 u32 wufc = adapter->wol;
5697 netif_device_detach(netdev);
5699 if (netif_running(netdev)) {
5700 ixgbe_down(adapter);
5701 ixgbe_free_irq(adapter);
5702 ixgbe_free_all_tx_resources(adapter);
5703 ixgbe_free_all_rx_resources(adapter);
5706 ixgbe_clear_interrupt_scheme(adapter);
5708 kfree(adapter->ixgbe_ieee_pfc);
5709 kfree(adapter->ixgbe_ieee_ets);
5713 retval = pci_save_state(pdev);
5719 ixgbe_set_rx_mode(netdev);
5721 /* turn on all-multi mode if wake on multicast is enabled */
5722 if (wufc & IXGBE_WUFC_MC) {
5723 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5724 fctrl |= IXGBE_FCTRL_MPE;
5725 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5728 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5729 ctrl |= IXGBE_CTRL_GIO_DIS;
5730 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5732 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5734 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5735 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5738 switch (hw->mac.type) {
5739 case ixgbe_mac_82598EB:
5740 pci_wake_from_d3(pdev, false);
5742 case ixgbe_mac_82599EB:
5743 case ixgbe_mac_X540:
5744 pci_wake_from_d3(pdev, !!wufc);
5750 *enable_wake = !!wufc;
5752 ixgbe_release_hw_control(adapter);
5754 pci_disable_device(pdev);
5760 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5765 retval = __ixgbe_shutdown(pdev, &wake);
5770 pci_prepare_to_sleep(pdev);
5772 pci_wake_from_d3(pdev, false);
5773 pci_set_power_state(pdev, PCI_D3hot);
5778 #endif /* CONFIG_PM */
5780 static void ixgbe_shutdown(struct pci_dev *pdev)
5784 __ixgbe_shutdown(pdev, &wake);
5786 if (system_state == SYSTEM_POWER_OFF) {
5787 pci_wake_from_d3(pdev, wake);
5788 pci_set_power_state(pdev, PCI_D3hot);
5793 * ixgbe_update_stats - Update the board statistics counters.
5794 * @adapter: board private structure
5796 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5798 struct net_device *netdev = adapter->netdev;
5799 struct ixgbe_hw *hw = &adapter->hw;
5800 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5802 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5803 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5804 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5805 u64 bytes = 0, packets = 0;
5807 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5808 test_bit(__IXGBE_RESETTING, &adapter->state))
5811 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5814 for (i = 0; i < 16; i++)
5815 adapter->hw_rx_no_dma_resources +=
5816 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5817 for (i = 0; i < adapter->num_rx_queues; i++) {
5818 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5819 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5821 adapter->rsc_total_count = rsc_count;
5822 adapter->rsc_total_flush = rsc_flush;
5825 for (i = 0; i < adapter->num_rx_queues; i++) {
5826 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5827 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5828 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5829 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5830 bytes += rx_ring->stats.bytes;
5831 packets += rx_ring->stats.packets;
5833 adapter->non_eop_descs = non_eop_descs;
5834 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5835 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5836 netdev->stats.rx_bytes = bytes;
5837 netdev->stats.rx_packets = packets;
5841 /* gather some stats to the adapter struct that are per queue */
5842 for (i = 0; i < adapter->num_tx_queues; i++) {
5843 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5844 restart_queue += tx_ring->tx_stats.restart_queue;
5845 tx_busy += tx_ring->tx_stats.tx_busy;
5846 bytes += tx_ring->stats.bytes;
5847 packets += tx_ring->stats.packets;
5849 adapter->restart_queue = restart_queue;
5850 adapter->tx_busy = tx_busy;
5851 netdev->stats.tx_bytes = bytes;
5852 netdev->stats.tx_packets = packets;
5854 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5855 for (i = 0; i < 8; i++) {
5856 /* for packet buffers not used, the register should read 0 */
5857 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5859 hwstats->mpc[i] += mpc;
5860 total_mpc += hwstats->mpc[i];
5861 if (hw->mac.type == ixgbe_mac_82598EB)
5862 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5863 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5864 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5865 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5866 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5867 switch (hw->mac.type) {
5868 case ixgbe_mac_82598EB:
5869 hwstats->pxonrxc[i] +=
5870 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5872 case ixgbe_mac_82599EB:
5873 case ixgbe_mac_X540:
5874 hwstats->pxonrxc[i] +=
5875 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5880 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5881 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5883 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5884 /* work around hardware counting issue */
5885 hwstats->gprc -= missed_rx;
5887 ixgbe_update_xoff_received(adapter);
5889 /* 82598 hardware only has a 32 bit counter in the high register */
5890 switch (hw->mac.type) {
5891 case ixgbe_mac_82598EB:
5892 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5893 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5894 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5895 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5897 case ixgbe_mac_82599EB:
5898 case ixgbe_mac_X540:
5899 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5900 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5901 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5902 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5903 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5904 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5905 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5906 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5907 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5909 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5910 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5911 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5912 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5913 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5914 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5915 #endif /* IXGBE_FCOE */
5920 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5921 hwstats->bprc += bprc;
5922 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5923 if (hw->mac.type == ixgbe_mac_82598EB)
5924 hwstats->mprc -= bprc;
5925 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5926 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5927 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5928 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5929 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5930 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5931 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5932 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5933 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5934 hwstats->lxontxc += lxon;
5935 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5936 hwstats->lxofftxc += lxoff;
5937 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5938 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5939 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5941 * 82598 errata - tx of flow control packets is included in tx counters
5943 xon_off_tot = lxon + lxoff;
5944 hwstats->gptc -= xon_off_tot;
5945 hwstats->mptc -= xon_off_tot;
5946 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5947 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5948 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5949 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5950 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5951 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5952 hwstats->ptc64 -= xon_off_tot;
5953 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5954 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5955 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5956 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5957 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5958 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5960 /* Fill out the OS statistics structure */
5961 netdev->stats.multicast = hwstats->mprc;
5964 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5965 netdev->stats.rx_dropped = 0;
5966 netdev->stats.rx_length_errors = hwstats->rlec;
5967 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5968 netdev->stats.rx_missed_errors = total_mpc;
5972 * ixgbe_watchdog - Timer Call-back
5973 * @data: pointer to adapter cast into an unsigned long
5975 static void ixgbe_watchdog(unsigned long data)
5977 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5978 struct ixgbe_hw *hw = &adapter->hw;
5983 * Do the watchdog outside of interrupt context due to the lovely
5984 * delays that some of the newer hardware requires
5987 if (test_bit(__IXGBE_DOWN, &adapter->state))
5988 goto watchdog_short_circuit;
5990 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5992 * for legacy and MSI interrupts don't set any bits
5993 * that are enabled for EIAM, because this operation
5994 * would set *both* EIMS and EICS for any bit in EIAM
5996 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5997 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5998 goto watchdog_reschedule;
6001 /* get one bit for every active tx/rx interrupt vector */
6002 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6003 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6004 if (qv->rxr_count || qv->txr_count)
6005 eics |= ((u64)1 << i);
6008 /* Cause software interrupt to ensure rx rings are cleaned */
6009 ixgbe_irq_rearm_queues(adapter, eics);
6011 watchdog_reschedule:
6012 /* Reset the timer */
6013 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
6015 watchdog_short_circuit:
6016 schedule_work(&adapter->watchdog_task);
6020 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
6021 * @work: pointer to work_struct containing our data
6023 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
6025 struct ixgbe_adapter *adapter = container_of(work,
6026 struct ixgbe_adapter,
6027 multispeed_fiber_task);
6028 struct ixgbe_hw *hw = &adapter->hw;
6032 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
6033 autoneg = hw->phy.autoneg_advertised;
6034 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6035 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6036 hw->mac.autotry_restart = false;
6037 if (hw->mac.ops.setup_link)
6038 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6039 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6040 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
6044 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
6045 * @work: pointer to work_struct containing our data
6047 static void ixgbe_sfp_config_module_task(struct work_struct *work)
6049 struct ixgbe_adapter *adapter = container_of(work,
6050 struct ixgbe_adapter,
6051 sfp_config_module_task);
6052 struct ixgbe_hw *hw = &adapter->hw;
6055 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
6057 /* Time for electrical oscillations to settle down */
6059 err = hw->phy.ops.identify_sfp(hw);
6061 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6062 e_dev_err("failed to initialize because an unsupported SFP+ "
6063 "module type was detected.\n");
6064 e_dev_err("Reload the driver after installing a supported "
6066 unregister_netdev(adapter->netdev);
6069 if (hw->mac.ops.setup_sfp)
6070 hw->mac.ops.setup_sfp(hw);
6072 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
6073 /* This will also work for DA Twinax connections */
6074 schedule_work(&adapter->multispeed_fiber_task);
6075 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6079 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6080 * @work: pointer to work_struct containing our data
6082 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6084 struct ixgbe_adapter *adapter = container_of(work,
6085 struct ixgbe_adapter,
6087 struct ixgbe_hw *hw = &adapter->hw;
6090 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6091 for (i = 0; i < adapter->num_tx_queues; i++)
6092 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6093 &(adapter->tx_ring[i]->state));
6095 e_err(probe, "failed to finish FDIR re-initialization, "
6096 "ignored adding FDIR ATR filters\n");
6098 /* Done FDIR Re-initialization, enable transmits */
6099 netif_tx_start_all_queues(adapter->netdev);
6102 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6106 /* Do not perform spoof check for 82598 */
6107 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6110 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6113 * ssvpc register is cleared on read, if zero then no
6114 * spoofed packets in the last interval.
6119 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6122 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6125 * ixgbe_watchdog_task - worker thread to bring link up
6126 * @work: pointer to work_struct containing our data
6128 static void ixgbe_watchdog_task(struct work_struct *work)
6130 struct ixgbe_adapter *adapter = container_of(work,
6131 struct ixgbe_adapter,
6133 struct net_device *netdev = adapter->netdev;
6134 struct ixgbe_hw *hw = &adapter->hw;
6138 struct ixgbe_ring *tx_ring;
6139 int some_tx_pending = 0;
6141 mutex_lock(&ixgbe_watchdog_lock);
6143 link_up = adapter->link_up;
6144 link_speed = adapter->link_speed;
6146 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6147 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6150 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6151 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6152 hw->mac.ops.fc_enable(hw, i);
6154 hw->mac.ops.fc_enable(hw, 0);
6157 hw->mac.ops.fc_enable(hw, 0);
6162 time_after(jiffies, (adapter->link_check_timeout +
6163 IXGBE_TRY_LINK_TIMEOUT))) {
6164 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6165 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6167 adapter->link_up = link_up;
6168 adapter->link_speed = link_speed;
6172 if (!netif_carrier_ok(netdev)) {
6173 bool flow_rx, flow_tx;
6175 switch (hw->mac.type) {
6176 case ixgbe_mac_82598EB: {
6177 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6178 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6179 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6180 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6183 case ixgbe_mac_82599EB:
6184 case ixgbe_mac_X540: {
6185 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6186 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6187 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6188 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6197 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6198 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6200 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6202 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6205 ((flow_rx && flow_tx) ? "RX/TX" :
6207 (flow_tx ? "TX" : "None"))));
6209 netif_carrier_on(netdev);
6211 /* Force detection of hung controller */
6212 for (i = 0; i < adapter->num_tx_queues; i++) {
6213 tx_ring = adapter->tx_ring[i];
6214 set_check_for_tx_hang(tx_ring);
6218 adapter->link_up = false;
6219 adapter->link_speed = 0;
6220 if (netif_carrier_ok(netdev)) {
6221 e_info(drv, "NIC Link is Down\n");
6222 netif_carrier_off(netdev);
6226 if (!netif_carrier_ok(netdev)) {
6227 for (i = 0; i < adapter->num_tx_queues; i++) {
6228 tx_ring = adapter->tx_ring[i];
6229 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6230 some_tx_pending = 1;
6235 if (some_tx_pending) {
6236 /* We've lost link, so the controller stops DMA,
6237 * but we've got queued Tx work that's never going
6238 * to get done, so reset controller to flush Tx.
6239 * (Do the reset outside of interrupt context).
6241 schedule_work(&adapter->reset_task);
6245 ixgbe_spoof_check(adapter);
6246 ixgbe_update_stats(adapter);
6247 mutex_unlock(&ixgbe_watchdog_lock);
6250 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6251 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6252 u32 tx_flags, u8 *hdr_len, __be16 protocol)
6254 struct ixgbe_adv_tx_context_desc *context_desc;
6257 struct ixgbe_tx_buffer *tx_buffer_info;
6258 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6259 u32 mss_l4len_idx, l4len;
6261 if (skb_is_gso(skb)) {
6262 if (skb_header_cloned(skb)) {
6263 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6267 l4len = tcp_hdrlen(skb);
6270 if (protocol == htons(ETH_P_IP)) {
6271 struct iphdr *iph = ip_hdr(skb);
6274 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6278 } else if (skb_is_gso_v6(skb)) {
6279 ipv6_hdr(skb)->payload_len = 0;
6280 tcp_hdr(skb)->check =
6281 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6282 &ipv6_hdr(skb)->daddr,
6286 i = tx_ring->next_to_use;
6288 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6289 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6291 /* VLAN MACLEN IPLEN */
6292 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6294 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6295 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6296 IXGBE_ADVTXD_MACLEN_SHIFT);
6297 *hdr_len += skb_network_offset(skb);
6299 (skb_transport_header(skb) - skb_network_header(skb));
6301 (skb_transport_header(skb) - skb_network_header(skb));
6302 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6303 context_desc->seqnum_seed = 0;
6305 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6306 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6307 IXGBE_ADVTXD_DTYP_CTXT);
6309 if (protocol == htons(ETH_P_IP))
6310 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6311 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6312 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6316 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6317 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6318 /* use index 1 for TSO */
6319 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6320 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6322 tx_buffer_info->time_stamp = jiffies;
6323 tx_buffer_info->next_to_watch = i;
6326 if (i == tx_ring->count)
6328 tx_ring->next_to_use = i;
6335 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6341 case cpu_to_be16(ETH_P_IP):
6342 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6343 switch (ip_hdr(skb)->protocol) {
6345 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6348 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6352 case cpu_to_be16(ETH_P_IPV6):
6353 /* XXX what about other V6 headers?? */
6354 switch (ipv6_hdr(skb)->nexthdr) {
6356 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6359 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6364 if (unlikely(net_ratelimit()))
6365 e_warn(probe, "partial checksum but proto=%x!\n",
6373 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6374 struct ixgbe_ring *tx_ring,
6375 struct sk_buff *skb, u32 tx_flags,
6378 struct ixgbe_adv_tx_context_desc *context_desc;
6380 struct ixgbe_tx_buffer *tx_buffer_info;
6381 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6383 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6384 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6385 i = tx_ring->next_to_use;
6386 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6387 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6389 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6391 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6392 vlan_macip_lens |= (skb_network_offset(skb) <<
6393 IXGBE_ADVTXD_MACLEN_SHIFT);
6394 if (skb->ip_summed == CHECKSUM_PARTIAL)
6395 vlan_macip_lens |= (skb_transport_header(skb) -
6396 skb_network_header(skb));
6398 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6399 context_desc->seqnum_seed = 0;
6401 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6402 IXGBE_ADVTXD_DTYP_CTXT);
6404 if (skb->ip_summed == CHECKSUM_PARTIAL)
6405 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6407 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6408 /* use index zero for tx checksum offload */
6409 context_desc->mss_l4len_idx = 0;
6411 tx_buffer_info->time_stamp = jiffies;
6412 tx_buffer_info->next_to_watch = i;
6415 if (i == tx_ring->count)
6417 tx_ring->next_to_use = i;
6425 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6426 struct ixgbe_ring *tx_ring,
6427 struct sk_buff *skb, u32 tx_flags,
6428 unsigned int first, const u8 hdr_len)
6430 struct device *dev = tx_ring->dev;
6431 struct ixgbe_tx_buffer *tx_buffer_info;
6433 unsigned int total = skb->len;
6434 unsigned int offset = 0, size, count = 0, i;
6435 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6437 unsigned int bytecount = skb->len;
6440 i = tx_ring->next_to_use;
6442 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6443 /* excluding fcoe_crc_eof for FCoE */
6444 total -= sizeof(struct fcoe_crc_eof);
6446 len = min(skb_headlen(skb), total);
6448 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6449 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6451 tx_buffer_info->length = size;
6452 tx_buffer_info->mapped_as_page = false;
6453 tx_buffer_info->dma = dma_map_single(dev,
6455 size, DMA_TO_DEVICE);
6456 if (dma_mapping_error(dev, tx_buffer_info->dma))
6458 tx_buffer_info->time_stamp = jiffies;
6459 tx_buffer_info->next_to_watch = i;
6468 if (i == tx_ring->count)
6473 for (f = 0; f < nr_frags; f++) {
6474 struct skb_frag_struct *frag;
6476 frag = &skb_shinfo(skb)->frags[f];
6477 len = min((unsigned int)frag->size, total);
6478 offset = frag->page_offset;
6482 if (i == tx_ring->count)
6485 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6486 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6488 tx_buffer_info->length = size;
6489 tx_buffer_info->dma = dma_map_page(dev,
6493 tx_buffer_info->mapped_as_page = true;
6494 if (dma_mapping_error(dev, tx_buffer_info->dma))
6496 tx_buffer_info->time_stamp = jiffies;
6497 tx_buffer_info->next_to_watch = i;
6508 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6509 gso_segs = skb_shinfo(skb)->gso_segs;
6511 /* adjust for FCoE Sequence Offload */
6512 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6513 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6514 skb_shinfo(skb)->gso_size);
6515 #endif /* IXGBE_FCOE */
6516 bytecount += (gso_segs - 1) * hdr_len;
6518 /* multiply data chunks by size of headers */
6519 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6520 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6521 tx_ring->tx_buffer_info[i].skb = skb;
6522 tx_ring->tx_buffer_info[first].next_to_watch = i;
6527 e_dev_err("TX DMA map failed\n");
6529 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6530 tx_buffer_info->dma = 0;
6531 tx_buffer_info->time_stamp = 0;
6532 tx_buffer_info->next_to_watch = 0;
6536 /* clear timestamp and dma mappings for remaining portion of packet */
6539 i += tx_ring->count;
6541 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6542 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6548 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6549 int tx_flags, int count, u32 paylen, u8 hdr_len)
6551 union ixgbe_adv_tx_desc *tx_desc = NULL;
6552 struct ixgbe_tx_buffer *tx_buffer_info;
6553 u32 olinfo_status = 0, cmd_type_len = 0;
6555 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6557 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6559 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6561 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6562 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6564 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6565 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6567 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6568 IXGBE_ADVTXD_POPTS_SHIFT;
6570 /* use index 1 context for tso */
6571 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6572 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6573 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6574 IXGBE_ADVTXD_POPTS_SHIFT;
6576 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6577 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6578 IXGBE_ADVTXD_POPTS_SHIFT;
6580 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6581 olinfo_status |= IXGBE_ADVTXD_CC;
6582 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6583 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6584 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6587 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6589 i = tx_ring->next_to_use;
6591 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6592 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6593 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6594 tx_desc->read.cmd_type_len =
6595 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6596 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6598 if (i == tx_ring->count)
6602 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6605 * Force memory writes to complete before letting h/w
6606 * know there are new descriptors to fetch. (Only
6607 * applicable for weak-ordered memory model archs,
6612 tx_ring->next_to_use = i;
6613 writel(i, tx_ring->tail);
6616 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6617 u32 tx_flags, __be16 protocol)
6619 struct ixgbe_q_vector *q_vector = ring->q_vector;
6620 union ixgbe_atr_hash_dword input = { .dword = 0 };
6621 union ixgbe_atr_hash_dword common = { .dword = 0 };
6623 unsigned char *network;
6625 struct ipv6hdr *ipv6;
6630 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6634 /* do nothing if sampling is disabled */
6635 if (!ring->atr_sample_rate)
6640 /* snag network header to get L4 type and address */
6641 hdr.network = skb_network_header(skb);
6643 /* Currently only IPv4/IPv6 with TCP is supported */
6644 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6645 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6646 (protocol != __constant_htons(ETH_P_IP) ||
6647 hdr.ipv4->protocol != IPPROTO_TCP))
6652 /* skip this packet since the socket is closing */
6656 /* sample on all syn packets or once every atr sample count */
6657 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6660 /* reset sample count */
6661 ring->atr_count = 0;
6663 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6666 * src and dst are inverted, think how the receiver sees them
6668 * The input is broken into two sections, a non-compressed section
6669 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6670 * is XORed together and stored in the compressed dword.
6672 input.formatted.vlan_id = vlan_id;
6675 * since src port and flex bytes occupy the same word XOR them together
6676 * and write the value to source port portion of compressed dword
6679 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6681 common.port.src ^= th->dest ^ protocol;
6682 common.port.dst ^= th->source;
6684 if (protocol == __constant_htons(ETH_P_IP)) {
6685 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6686 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6688 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6689 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6690 hdr.ipv6->saddr.s6_addr32[1] ^
6691 hdr.ipv6->saddr.s6_addr32[2] ^
6692 hdr.ipv6->saddr.s6_addr32[3] ^
6693 hdr.ipv6->daddr.s6_addr32[0] ^
6694 hdr.ipv6->daddr.s6_addr32[1] ^
6695 hdr.ipv6->daddr.s6_addr32[2] ^
6696 hdr.ipv6->daddr.s6_addr32[3];
6699 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6700 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6701 input, common, ring->queue_index);
6704 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6706 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6707 /* Herbert's original patch had:
6708 * smp_mb__after_netif_stop_queue();
6709 * but since that doesn't exist yet, just open code it. */
6712 /* We need to check again in a case another CPU has just
6713 * made room available. */
6714 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6717 /* A reprieve! - use start_queue because it doesn't call schedule */
6718 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6719 ++tx_ring->tx_stats.restart_queue;
6723 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6725 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6727 return __ixgbe_maybe_stop_tx(tx_ring, size);
6730 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6732 struct ixgbe_adapter *adapter = netdev_priv(dev);
6733 int txq = smp_processor_id();
6737 protocol = vlan_get_protocol(skb);
6739 if (((protocol == htons(ETH_P_FCOE)) ||
6740 (protocol == htons(ETH_P_FIP))) &&
6741 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6742 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6743 txq += adapter->ring_feature[RING_F_FCOE].mask;
6748 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6749 while (unlikely(txq >= dev->real_num_tx_queues))
6750 txq -= dev->real_num_tx_queues;
6754 return skb_tx_hash(dev, skb);
6757 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6758 struct ixgbe_adapter *adapter,
6759 struct ixgbe_ring *tx_ring)
6762 unsigned int tx_flags = 0;
6769 protocol = vlan_get_protocol(skb);
6771 if (vlan_tx_tag_present(skb)) {
6772 tx_flags |= vlan_tx_tag_get(skb);
6773 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6774 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6775 tx_flags |= tx_ring->dcb_tc << 13;
6777 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6778 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6779 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6780 skb->priority != TC_PRIO_CONTROL) {
6781 tx_flags |= tx_ring->dcb_tc << 13;
6782 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6783 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6787 /* for FCoE with DCB, we force the priority to what
6788 * was specified by the switch */
6789 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6790 (protocol == htons(ETH_P_FCOE)))
6791 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6794 /* four things can cause us to need a context descriptor */
6795 if (skb_is_gso(skb) ||
6796 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6797 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6798 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6801 count += TXD_USE_COUNT(skb_headlen(skb));
6802 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6803 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6805 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6806 tx_ring->tx_stats.tx_busy++;
6807 return NETDEV_TX_BUSY;
6810 first = tx_ring->next_to_use;
6811 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6813 /* setup tx offload for FCoE */
6814 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6816 dev_kfree_skb_any(skb);
6817 return NETDEV_TX_OK;
6820 tx_flags |= IXGBE_TX_FLAGS_FSO;
6821 #endif /* IXGBE_FCOE */
6823 if (protocol == htons(ETH_P_IP))
6824 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6825 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6828 dev_kfree_skb_any(skb);
6829 return NETDEV_TX_OK;
6833 tx_flags |= IXGBE_TX_FLAGS_TSO;
6834 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6836 (skb->ip_summed == CHECKSUM_PARTIAL))
6837 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6840 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6842 /* add the ATR filter if ATR is on */
6843 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6844 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6845 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6846 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6849 dev_kfree_skb_any(skb);
6850 tx_ring->tx_buffer_info[first].time_stamp = 0;
6851 tx_ring->next_to_use = first;
6854 return NETDEV_TX_OK;
6857 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6860 struct ixgbe_ring *tx_ring;
6862 tx_ring = adapter->tx_ring[skb->queue_mapping];
6863 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6867 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6868 * @netdev: network interface device structure
6869 * @p: pointer to an address structure
6871 * Returns 0 on success, negative on failure
6873 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6876 struct ixgbe_hw *hw = &adapter->hw;
6877 struct sockaddr *addr = p;
6879 if (!is_valid_ether_addr(addr->sa_data))
6880 return -EADDRNOTAVAIL;
6882 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6883 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6885 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6892 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6894 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6895 struct ixgbe_hw *hw = &adapter->hw;
6899 if (prtad != hw->phy.mdio.prtad)
6901 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6907 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6908 u16 addr, u16 value)
6910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6911 struct ixgbe_hw *hw = &adapter->hw;
6913 if (prtad != hw->phy.mdio.prtad)
6915 return hw->phy.ops.write_reg(hw, addr, devad, value);
6918 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6920 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6922 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6926 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6928 * @netdev: network interface device structure
6930 * Returns non-zero on failure
6932 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6935 struct ixgbe_adapter *adapter = netdev_priv(dev);
6936 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6938 if (is_valid_ether_addr(mac->san_addr)) {
6940 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6947 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6949 * @netdev: network interface device structure
6951 * Returns non-zero on failure
6953 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6956 struct ixgbe_adapter *adapter = netdev_priv(dev);
6957 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6959 if (is_valid_ether_addr(mac->san_addr)) {
6961 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6967 #ifdef CONFIG_NET_POLL_CONTROLLER
6969 * Polling 'interrupt' - used by things like netconsole to send skbs
6970 * without having to re-enable interrupts. It's not called while
6971 * the interrupt routine is executing.
6973 static void ixgbe_netpoll(struct net_device *netdev)
6975 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6978 /* if interface is down do nothing */
6979 if (test_bit(__IXGBE_DOWN, &adapter->state))
6982 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6983 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6984 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6985 for (i = 0; i < num_q_vectors; i++) {
6986 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6987 ixgbe_msix_clean_many(0, q_vector);
6990 ixgbe_intr(adapter->pdev->irq, netdev);
6992 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6996 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6997 struct rtnl_link_stats64 *stats)
6999 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7003 for (i = 0; i < adapter->num_rx_queues; i++) {
7004 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7010 start = u64_stats_fetch_begin_bh(&ring->syncp);
7011 packets = ring->stats.packets;
7012 bytes = ring->stats.bytes;
7013 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7014 stats->rx_packets += packets;
7015 stats->rx_bytes += bytes;
7019 for (i = 0; i < adapter->num_tx_queues; i++) {
7020 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7026 start = u64_stats_fetch_begin_bh(&ring->syncp);
7027 packets = ring->stats.packets;
7028 bytes = ring->stats.bytes;
7029 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7030 stats->tx_packets += packets;
7031 stats->tx_bytes += bytes;
7035 /* following stats updated by ixgbe_watchdog_task() */
7036 stats->multicast = netdev->stats.multicast;
7037 stats->rx_errors = netdev->stats.rx_errors;
7038 stats->rx_length_errors = netdev->stats.rx_length_errors;
7039 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7040 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7045 static const struct net_device_ops ixgbe_netdev_ops = {
7046 .ndo_open = ixgbe_open,
7047 .ndo_stop = ixgbe_close,
7048 .ndo_start_xmit = ixgbe_xmit_frame,
7049 .ndo_select_queue = ixgbe_select_queue,
7050 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7051 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7052 .ndo_validate_addr = eth_validate_addr,
7053 .ndo_set_mac_address = ixgbe_set_mac,
7054 .ndo_change_mtu = ixgbe_change_mtu,
7055 .ndo_tx_timeout = ixgbe_tx_timeout,
7056 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7057 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7058 .ndo_do_ioctl = ixgbe_ioctl,
7059 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7060 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7061 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7062 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7063 .ndo_get_stats64 = ixgbe_get_stats64,
7064 #ifdef CONFIG_IXGBE_DCB
7065 .ndo_setup_tc = ixgbe_setup_tc,
7067 #ifdef CONFIG_NET_POLL_CONTROLLER
7068 .ndo_poll_controller = ixgbe_netpoll,
7071 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7072 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7073 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7074 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7075 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7076 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7077 #endif /* IXGBE_FCOE */
7080 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7081 const struct ixgbe_info *ii)
7083 #ifdef CONFIG_PCI_IOV
7084 struct ixgbe_hw *hw = &adapter->hw;
7087 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7090 /* The 82599 supports up to 64 VFs per physical function
7091 * but this implementation limits allocation to 63 so that
7092 * basic networking resources are still available to the
7095 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7096 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7097 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7099 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7102 /* If call to enable VFs succeeded then allocate memory
7103 * for per VF control structures.
7106 kcalloc(adapter->num_vfs,
7107 sizeof(struct vf_data_storage), GFP_KERNEL);
7108 if (adapter->vfinfo) {
7109 /* Now that we're sure SR-IOV is enabled
7110 * and memory allocated set up the mailbox parameters
7112 ixgbe_init_mbx_params_pf(hw);
7113 memcpy(&hw->mbx.ops, ii->mbx_ops,
7114 sizeof(hw->mbx.ops));
7116 /* Disable RSC when in SR-IOV mode */
7117 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7118 IXGBE_FLAG2_RSC_ENABLED);
7123 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7124 "SRIOV disabled\n");
7125 pci_disable_sriov(adapter->pdev);
7128 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7129 adapter->num_vfs = 0;
7130 #endif /* CONFIG_PCI_IOV */
7134 * ixgbe_probe - Device Initialization Routine
7135 * @pdev: PCI device information struct
7136 * @ent: entry in ixgbe_pci_tbl
7138 * Returns 0 on success, negative on failure
7140 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7141 * The OS initialization, configuring of the adapter private structure,
7142 * and a hardware reset occur.
7144 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7145 const struct pci_device_id *ent)
7147 struct net_device *netdev;
7148 struct ixgbe_adapter *adapter = NULL;
7149 struct ixgbe_hw *hw;
7150 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7151 static int cards_found;
7152 int i, err, pci_using_dac;
7153 u8 part_str[IXGBE_PBANUM_LENGTH];
7154 unsigned int indices = num_possible_cpus();
7160 /* Catch broken hardware that put the wrong VF device ID in
7161 * the PCIe SR-IOV capability.
7163 if (pdev->is_virtfn) {
7164 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7165 pci_name(pdev), pdev->vendor, pdev->device);
7169 err = pci_enable_device_mem(pdev);
7173 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7174 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7177 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7179 err = dma_set_coherent_mask(&pdev->dev,
7183 "No usable DMA configuration, aborting\n");
7190 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7191 IORESOURCE_MEM), ixgbe_driver_name);
7194 "pci_request_selected_regions failed 0x%x\n", err);
7198 pci_enable_pcie_error_reporting(pdev);
7200 pci_set_master(pdev);
7201 pci_save_state(pdev);
7203 if (ii->mac == ixgbe_mac_82598EB)
7204 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7206 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7208 #if defined(CONFIG_DCB)
7209 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7210 #elif defined(IXGBE_FCOE)
7211 indices += min_t(unsigned int, num_possible_cpus(),
7212 IXGBE_MAX_FCOE_INDICES);
7214 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7217 goto err_alloc_etherdev;
7220 SET_NETDEV_DEV(netdev, &pdev->dev);
7222 adapter = netdev_priv(netdev);
7223 pci_set_drvdata(pdev, adapter);
7225 adapter->netdev = netdev;
7226 adapter->pdev = pdev;
7229 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7231 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7232 pci_resource_len(pdev, 0));
7238 for (i = 1; i <= 5; i++) {
7239 if (pci_resource_len(pdev, i) == 0)
7243 netdev->netdev_ops = &ixgbe_netdev_ops;
7244 ixgbe_set_ethtool_ops(netdev);
7245 netdev->watchdog_timeo = 5 * HZ;
7246 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7248 adapter->bd_number = cards_found;
7251 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7252 hw->mac.type = ii->mac;
7255 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7256 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7257 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7258 if (!(eec & (1 << 8)))
7259 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7262 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7263 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7264 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7265 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7266 hw->phy.mdio.mmds = 0;
7267 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7268 hw->phy.mdio.dev = netdev;
7269 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7270 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7272 /* set up this timer and work struct before calling get_invariants
7273 * which might start the timer
7275 init_timer(&adapter->sfp_timer);
7276 adapter->sfp_timer.function = ixgbe_sfp_timer;
7277 adapter->sfp_timer.data = (unsigned long) adapter;
7279 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7281 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7282 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7284 /* a new SFP+ module arrival, called from GPI SDP2 context */
7285 INIT_WORK(&adapter->sfp_config_module_task,
7286 ixgbe_sfp_config_module_task);
7288 ii->get_invariants(hw);
7290 /* setup the private structure */
7291 err = ixgbe_sw_init(adapter);
7295 /* Make it possible the adapter to be woken up via WOL */
7296 switch (adapter->hw.mac.type) {
7297 case ixgbe_mac_82599EB:
7298 case ixgbe_mac_X540:
7299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7306 * If there is a fan on this device and it has failed log the
7309 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7310 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7311 if (esdp & IXGBE_ESDP_SDP1)
7312 e_crit(probe, "Fan has stopped, replace the adapter\n");
7315 /* reset_hw fills in the perm_addr as well */
7316 hw->phy.reset_if_overtemp = true;
7317 err = hw->mac.ops.reset_hw(hw);
7318 hw->phy.reset_if_overtemp = false;
7319 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7320 hw->mac.type == ixgbe_mac_82598EB) {
7322 * Start a kernel thread to watch for a module to arrive.
7323 * Only do this for 82598, since 82599 will generate
7324 * interrupts on module arrival.
7326 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7327 mod_timer(&adapter->sfp_timer,
7328 round_jiffies(jiffies + (2 * HZ)));
7330 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7331 e_dev_err("failed to initialize because an unsupported SFP+ "
7332 "module type was detected.\n");
7333 e_dev_err("Reload the driver after installing a supported "
7337 e_dev_err("HW Init failed: %d\n", err);
7341 ixgbe_probe_vf(adapter, ii);
7343 netdev->features = NETIF_F_SG |
7345 NETIF_F_HW_VLAN_TX |
7346 NETIF_F_HW_VLAN_RX |
7347 NETIF_F_HW_VLAN_FILTER;
7349 netdev->features |= NETIF_F_IPV6_CSUM;
7350 netdev->features |= NETIF_F_TSO;
7351 netdev->features |= NETIF_F_TSO6;
7352 netdev->features |= NETIF_F_GRO;
7354 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7355 netdev->features |= NETIF_F_SCTP_CSUM;
7357 netdev->vlan_features |= NETIF_F_TSO;
7358 netdev->vlan_features |= NETIF_F_TSO6;
7359 netdev->vlan_features |= NETIF_F_IP_CSUM;
7360 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7361 netdev->vlan_features |= NETIF_F_SG;
7363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7364 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7365 IXGBE_FLAG_DCB_ENABLED);
7367 #ifdef CONFIG_IXGBE_DCB
7368 netdev->dcbnl_ops = &dcbnl_ops;
7372 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7373 if (hw->mac.ops.get_device_caps) {
7374 hw->mac.ops.get_device_caps(hw, &device_caps);
7375 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7376 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7379 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7380 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7381 netdev->vlan_features |= NETIF_F_FSO;
7382 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7384 #endif /* IXGBE_FCOE */
7385 if (pci_using_dac) {
7386 netdev->features |= NETIF_F_HIGHDMA;
7387 netdev->vlan_features |= NETIF_F_HIGHDMA;
7390 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7391 netdev->features |= NETIF_F_LRO;
7393 /* make sure the EEPROM is good */
7394 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7395 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7400 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7401 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7403 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7404 e_dev_err("invalid MAC address\n");
7409 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7410 if (hw->mac.ops.disable_tx_laser &&
7411 ((hw->phy.multispeed_fiber) ||
7412 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7413 (hw->mac.type == ixgbe_mac_82599EB))))
7414 hw->mac.ops.disable_tx_laser(hw);
7416 init_timer(&adapter->watchdog_timer);
7417 adapter->watchdog_timer.function = ixgbe_watchdog;
7418 adapter->watchdog_timer.data = (unsigned long)adapter;
7420 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7421 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7423 err = ixgbe_init_interrupt_scheme(adapter);
7427 switch (pdev->device) {
7428 case IXGBE_DEV_ID_82599_SFP:
7429 /* Only this subdevice supports WOL */
7430 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7431 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7432 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7434 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7435 /* All except this subdevice support WOL */
7436 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7437 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7438 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7440 case IXGBE_DEV_ID_82599_KX4:
7441 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7442 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7448 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7450 /* pick up the PCI bus settings for reporting later */
7451 hw->mac.ops.get_bus_info(hw);
7453 /* print bus type/speed/width info */
7454 e_dev_info("(PCI Express:%s:%s) %pM\n",
7455 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7456 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7458 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7459 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7460 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7464 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7466 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7467 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7468 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7469 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7472 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7473 hw->mac.type, hw->phy.type, part_str);
7475 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7476 e_dev_warn("PCI-Express bandwidth available for this card is "
7477 "not sufficient for optimal performance.\n");
7478 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7482 /* save off EEPROM version number */
7483 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7485 /* reset the hardware with the new settings */
7486 err = hw->mac.ops.start_hw(hw);
7488 if (err == IXGBE_ERR_EEPROM_VERSION) {
7489 /* We are running on a pre-production device, log a warning */
7490 e_dev_warn("This device is a pre-production adapter/LOM. "
7491 "Please be aware there may be issues associated "
7492 "with your hardware. If you are experiencing "
7493 "problems please contact your Intel or hardware "
7494 "representative who provided you with this "
7497 strcpy(netdev->name, "eth%d");
7498 err = register_netdev(netdev);
7502 /* carrier off reporting is important to ethtool even BEFORE open */
7503 netif_carrier_off(netdev);
7505 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7506 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7507 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7509 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7510 INIT_WORK(&adapter->check_overtemp_task,
7511 ixgbe_check_overtemp_task);
7512 #ifdef CONFIG_IXGBE_DCA
7513 if (dca_add_requester(&pdev->dev) == 0) {
7514 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7515 ixgbe_setup_dca(adapter);
7518 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7519 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7520 for (i = 0; i < adapter->num_vfs; i++)
7521 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7524 /* add san mac addr to netdev */
7525 ixgbe_add_sanmac_netdev(netdev);
7527 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7532 ixgbe_release_hw_control(adapter);
7533 ixgbe_clear_interrupt_scheme(adapter);
7536 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7537 ixgbe_disable_sriov(adapter);
7538 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7539 del_timer_sync(&adapter->sfp_timer);
7540 cancel_work_sync(&adapter->sfp_task);
7541 cancel_work_sync(&adapter->multispeed_fiber_task);
7542 cancel_work_sync(&adapter->sfp_config_module_task);
7543 iounmap(hw->hw_addr);
7545 free_netdev(netdev);
7547 pci_release_selected_regions(pdev,
7548 pci_select_bars(pdev, IORESOURCE_MEM));
7551 pci_disable_device(pdev);
7556 * ixgbe_remove - Device Removal Routine
7557 * @pdev: PCI device information struct
7559 * ixgbe_remove is called by the PCI subsystem to alert the driver
7560 * that it should release a PCI device. The could be caused by a
7561 * Hot-Plug event, or because the driver is going to be removed from
7564 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7566 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7567 struct net_device *netdev = adapter->netdev;
7569 set_bit(__IXGBE_DOWN, &adapter->state);
7572 * The timers may be rescheduled, so explicitly disable them
7573 * from being rescheduled.
7575 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7576 del_timer_sync(&adapter->watchdog_timer);
7577 del_timer_sync(&adapter->sfp_timer);
7579 cancel_work_sync(&adapter->watchdog_task);
7580 cancel_work_sync(&adapter->sfp_task);
7581 cancel_work_sync(&adapter->multispeed_fiber_task);
7582 cancel_work_sync(&adapter->sfp_config_module_task);
7583 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7584 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7585 cancel_work_sync(&adapter->fdir_reinit_task);
7586 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7587 cancel_work_sync(&adapter->check_overtemp_task);
7589 #ifdef CONFIG_IXGBE_DCA
7590 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7591 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7592 dca_remove_requester(&pdev->dev);
7593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7598 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7599 ixgbe_cleanup_fcoe(adapter);
7601 #endif /* IXGBE_FCOE */
7603 /* remove the added san mac */
7604 ixgbe_del_sanmac_netdev(netdev);
7606 if (netdev->reg_state == NETREG_REGISTERED)
7607 unregister_netdev(netdev);
7609 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7610 ixgbe_disable_sriov(adapter);
7612 ixgbe_clear_interrupt_scheme(adapter);
7614 ixgbe_release_hw_control(adapter);
7616 iounmap(adapter->hw.hw_addr);
7617 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7620 e_dev_info("complete\n");
7622 free_netdev(netdev);
7624 pci_disable_pcie_error_reporting(pdev);
7626 pci_disable_device(pdev);
7630 * ixgbe_io_error_detected - called when PCI error is detected
7631 * @pdev: Pointer to PCI device
7632 * @state: The current pci connection state
7634 * This function is called after a PCI bus error affecting
7635 * this device has been detected.
7637 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7638 pci_channel_state_t state)
7640 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7641 struct net_device *netdev = adapter->netdev;
7643 netif_device_detach(netdev);
7645 if (state == pci_channel_io_perm_failure)
7646 return PCI_ERS_RESULT_DISCONNECT;
7648 if (netif_running(netdev))
7649 ixgbe_down(adapter);
7650 pci_disable_device(pdev);
7652 /* Request a slot reset. */
7653 return PCI_ERS_RESULT_NEED_RESET;
7657 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7658 * @pdev: Pointer to PCI device
7660 * Restart the card from scratch, as if from a cold-boot.
7662 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7664 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7665 pci_ers_result_t result;
7668 if (pci_enable_device_mem(pdev)) {
7669 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7670 result = PCI_ERS_RESULT_DISCONNECT;
7672 pci_set_master(pdev);
7673 pci_restore_state(pdev);
7674 pci_save_state(pdev);
7676 pci_wake_from_d3(pdev, false);
7678 ixgbe_reset(adapter);
7679 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7680 result = PCI_ERS_RESULT_RECOVERED;
7683 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7685 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7686 "failed 0x%0x\n", err);
7687 /* non-fatal, continue */
7694 * ixgbe_io_resume - called when traffic can start flowing again.
7695 * @pdev: Pointer to PCI device
7697 * This callback is called when the error recovery driver tells us that
7698 * its OK to resume normal operation.
7700 static void ixgbe_io_resume(struct pci_dev *pdev)
7702 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7703 struct net_device *netdev = adapter->netdev;
7705 if (netif_running(netdev)) {
7706 if (ixgbe_up(adapter)) {
7707 e_info(probe, "ixgbe_up failed after reset\n");
7712 netif_device_attach(netdev);
7715 static struct pci_error_handlers ixgbe_err_handler = {
7716 .error_detected = ixgbe_io_error_detected,
7717 .slot_reset = ixgbe_io_slot_reset,
7718 .resume = ixgbe_io_resume,
7721 static struct pci_driver ixgbe_driver = {
7722 .name = ixgbe_driver_name,
7723 .id_table = ixgbe_pci_tbl,
7724 .probe = ixgbe_probe,
7725 .remove = __devexit_p(ixgbe_remove),
7727 .suspend = ixgbe_suspend,
7728 .resume = ixgbe_resume,
7730 .shutdown = ixgbe_shutdown,
7731 .err_handler = &ixgbe_err_handler
7735 * ixgbe_init_module - Driver Registration Routine
7737 * ixgbe_init_module is the first routine called when the driver is
7738 * loaded. All it does is register with the PCI subsystem.
7740 static int __init ixgbe_init_module(void)
7743 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7744 pr_info("%s\n", ixgbe_copyright);
7746 #ifdef CONFIG_IXGBE_DCA
7747 dca_register_notify(&dca_notifier);
7750 ret = pci_register_driver(&ixgbe_driver);
7754 module_init(ixgbe_init_module);
7757 * ixgbe_exit_module - Driver Exit Cleanup Routine
7759 * ixgbe_exit_module is called just before the driver is removed
7762 static void __exit ixgbe_exit_module(void)
7764 #ifdef CONFIG_IXGBE_DCA
7765 dca_unregister_notify(&dca_notifier);
7767 pci_unregister_driver(&ixgbe_driver);
7768 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7771 #ifdef CONFIG_IXGBE_DCA
7772 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7777 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7778 __ixgbe_notify_dca);
7780 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7783 #endif /* CONFIG_IXGBE_DCA */
7785 module_exit(ixgbe_exit_module);