drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 #ifdef CONFIG_PM
 139 static int igb_suspend(struct pci_dev *, pm_message_t);
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155 #ifdef CONFIG_PCI_IOV
 156 static unsigned int max_vfs = 0;
 157 module_param(max_vfs, uint, 0);
 158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 159                  "per physical function");
 160 #endif /* CONFIG_PCI_IOV */
 161
 162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 163                      pci_channel_state_t);
 164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 165 static void igb_io_resume(struct pci_dev *);
 166
 167 static struct pci_error_handlers igb_err_handler = {
 168         .error_detected = igb_io_error_detected,
 169         .slot_reset = igb_io_slot_reset,
 170         .resume = igb_io_resume,
 171 };
 172
 173
 174 static struct pci_driver igb_driver = {
 175         .name     = igb_driver_name,
 176         .id_table = igb_pci_tbl,
 177         .probe    = igb_probe,
 178         .remove   = __devexit_p(igb_remove),
 179 #ifdef CONFIG_PM
 180         /* Power Managment Hooks */
 181         .suspend  = igb_suspend,
 182         .resume   = igb_resume,
 183 #endif
 184         .shutdown = igb_shutdown,
 185         .err_handler = &igb_err_handler
 186 };
 187
 188 static int global_quad_port_a; /* global quad port a indication */
 189
 190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 192 MODULE_LICENSE("GPL");
 193 MODULE_VERSION(DRV_VERSION);
 194
 195 /**
 196  * Scale the NIC clock cycle by a large factor so that
 197  * relatively small clock corrections can be added or
 198  * substracted at each clock tick. The drawbacks of a
 199  * large factor are a) that the clock register overflows
 200  * more quickly (not such a big deal) and b) that the
 201  * increment per tick has to fit into 24 bits.
 202  *
 203  * Note that
 204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 205  *             IGB_TSYNC_SCALE
 206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 207  *
 208  * The base scale factor is intentionally a power of two
 209  * so that the division in %struct timecounter can be done with
 210  * a shift.
 211  */
 212 #define IGB_TSYNC_SHIFT (19)
 213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 214
 215 /**
 216  * The duration of one clock cycle of the NIC.
 217  *
 218  * @todo This hard-coded value is part of the specification and might change
 219  * in future hardware revisions. Add revision check.
 220  */
 221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 222
 223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 225 #endif
 226
 227 /**
 228  * igb_read_clock - read raw cycle counter (to be used by time counter)
 229  */
 230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 231 {
 232         struct igb_adapter *adapter =
 233                 container_of(tc, struct igb_adapter, cycles);
 234         struct e1000_hw *hw = &adapter->hw;
 235         u64 stamp;
 236
 237         stamp =  rd32(E1000_SYSTIML);
 238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 239
 240         return stamp;
 241 }
 242
 243 #ifdef DEBUG
 244 /**
 245  * igb_get_hw_dev_name - return device name string
 246  * used by hardware layer to print debugging information
 247  **/
 248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 249 {
 250         struct igb_adapter *adapter = hw->back;
 251         return adapter->netdev->name;
 252 }
 253
 254 /**
 255  * igb_get_time_str - format current NIC and system time as string
 256  */
 257 static char *igb_get_time_str(struct igb_adapter *adapter,
 258                               char buffer[160])
 259 {
 260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 262         struct timespec sys;
 263         struct timespec delta;
 264         getnstimeofday(&sys);
 265
 266         delta = timespec_sub(nic, sys);
 267
 268         sprintf(buffer,
 269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 270                 hw,
 271                 (long)nic.tv_sec, nic.tv_nsec,
 272                 (long)sys.tv_sec, sys.tv_nsec,
 273                 (long)delta.tv_sec, delta.tv_nsec);
 274
 275         return buffer;
 276 }
 277 #endif
 278
 279 /**
 280  * igb_desc_unused - calculate if we have unused descriptors
 281  **/
 282 static int igb_desc_unused(struct igb_ring *ring)
 283 {
 284         if (ring->next_to_clean > ring->next_to_use)
 285                 return ring->next_to_clean - ring->next_to_use - 1;
 286
 287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 288 }
 289
 290 /**
 291  * igb_init_module - Driver Registration Routine
 292  *
 293  * igb_init_module is the first routine called when the driver is
 294  * loaded. All it does is register with the PCI subsystem.
 295  **/
 296 static int __init igb_init_module(void)
 297 {
 298         int ret;
 299         printk(KERN_INFO "%s - version %s\n",
 300                igb_driver_string, igb_driver_version);
 301
 302         printk(KERN_INFO "%s\n", igb_copyright);
 303
 304         global_quad_port_a = 0;
 305
 306 #ifdef CONFIG_IGB_DCA
 307         dca_register_notify(&dca_notifier);
 308 #endif
 309
 310         ret = pci_register_driver(&igb_driver);
 311         return ret;
 312 }
 313
 314 module_init(igb_init_module);
 315
 316 /**
 317  * igb_exit_module - Driver Exit Cleanup Routine
 318  *
 319  * igb_exit_module is called just before the driver is removed
 320  * from memory.
 321  **/
 322 static void __exit igb_exit_module(void)
 323 {
 324 #ifdef CONFIG_IGB_DCA
 325         dca_unregister_notify(&dca_notifier);
 326 #endif
 327         pci_unregister_driver(&igb_driver);
 328 }
 329
 330 module_exit(igb_exit_module);
 331
 332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 333 /**
 334  * igb_cache_ring_register - Descriptor ring to register mapping
 335  * @adapter: board private structure to initialize
 336  *
 337  * Once we know the feature-set enabled for the device, we'll cache
 338  * the register offset the descriptor ring is assigned to.
 339  **/
 340 static void igb_cache_ring_register(struct igb_adapter *adapter)
 341 {
 342         int i;
 343         unsigned int rbase_offset = adapter->vfs_allocated_count;
 344
 345         switch (adapter->hw.mac.type) {
 346         case e1000_82576:
 347                 /* The queues are allocated for virtualization such that VF 0
 348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 349                  * In order to avoid collision we start at the first free queue
 350                  * and continue consuming queues in the same sequence
 351                  */
 352                 for (i = 0; i < adapter->num_rx_queues; i++)
 353                         adapter->rx_ring[i].reg_idx = rbase_offset +
 354                                                       Q_IDX_82576(i);
 355                 for (i = 0; i < adapter->num_tx_queues; i++)
 356                         adapter->tx_ring[i].reg_idx = rbase_offset +
 357                                                       Q_IDX_82576(i);
 358                 break;
 359         case e1000_82575:
 360         default:
 361                 for (i = 0; i < adapter->num_rx_queues; i++)
 362                         adapter->rx_ring[i].reg_idx = i;
 363                 for (i = 0; i < adapter->num_tx_queues; i++)
 364                         adapter->tx_ring[i].reg_idx = i;
 365                 break;
 366         }
 367 }
 368
 369 /**
 370  * igb_alloc_queues - Allocate memory for all rings
 371  * @adapter: board private structure to initialize
 372  *
 373  * We allocate one ring per queue at run-time since we don't know the
 374  * number of queues at compile-time.
 375  **/
 376 static int igb_alloc_queues(struct igb_adapter *adapter)
 377 {
 378         int i;
 379
 380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 381                                    sizeof(struct igb_ring), GFP_KERNEL);
 382         if (!adapter->tx_ring)
 383                 return -ENOMEM;
 384
 385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 386                                    sizeof(struct igb_ring), GFP_KERNEL);
 387         if (!adapter->rx_ring) {
 388                 kfree(adapter->tx_ring);
 389                 return -ENOMEM;
 390         }
 391
 392         adapter->rx_ring->buddy = adapter->tx_ring;
 393
 394         for (i = 0; i < adapter->num_tx_queues; i++) {
 395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 396                 ring->count = adapter->tx_ring_count;
 397                 ring->adapter = adapter;
 398                 ring->queue_index = i;
 399         }
 400         for (i = 0; i < adapter->num_rx_queues; i++) {
 401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 402                 ring->count = adapter->rx_ring_count;
 403                 ring->adapter = adapter;
 404                 ring->queue_index = i;
 405                 ring->itr_register = E1000_ITR;
 406
 407                 /* set a default napi handler for each rx_ring */
 408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 409         }
 410
 411         igb_cache_ring_register(adapter);
 412         return 0;
 413 }
 414
 415 static void igb_free_queues(struct igb_adapter *adapter)
 416 {
 417         int i;
 418
 419         for (i = 0; i < adapter->num_rx_queues; i++)
 420                 netif_napi_del(&adapter->rx_ring[i].napi);
 421
 422         adapter->num_rx_queues = 0;
 423         adapter->num_tx_queues = 0;
 424
 425         kfree(adapter->tx_ring);
 426         kfree(adapter->rx_ring);
 427 }
 428
 429 #define IGB_N0_QUEUE -1
 430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 431                               int tx_queue, int msix_vector)
 432 {
 433         u32 msixbm = 0;
 434         struct e1000_hw *hw = &adapter->hw;
 435         u32 ivar, index;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 /* The 82575 assigns vectors using a bitmask, which matches the
 440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 441                    or more queues to a vector, we write the appropriate bits
 442                    into the MSIXBM register for that vector. */
 443                 if (rx_queue > IGB_N0_QUEUE) {
 444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 446                 }
 447                 if (tx_queue > IGB_N0_QUEUE) {
 448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 449                         adapter->tx_ring[tx_queue].eims_value =
 450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 451                 }
 452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 453                 break;
 454         case e1000_82576:
 455                 /* 82576 uses a table-based method for assigning vectors.
 456                    Each queue has a single entry in the table to which we write
 457                    a vector number along with a "valid" bit.  Sadly, the layout
 458                    of the table is somewhat counterintuitive. */
 459                 if (rx_queue > IGB_N0_QUEUE) {
 460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 461                         ivar = array_rd32(E1000_IVAR0, index);
 462                         if (rx_queue & 0x1) {
 463                                 /* vector goes into third byte of register */
 464                                 ivar = ivar & 0xFF00FFFF;
 465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 466                         } else {
 467                                 /* vector goes into low byte of register */
 468                                 ivar = ivar & 0xFFFFFF00;
 469                                 ivar |= msix_vector | E1000_IVAR_VALID;
 470                         }
 471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 472                         array_wr32(E1000_IVAR0, index, ivar);
 473                 }
 474                 if (tx_queue > IGB_N0_QUEUE) {
 475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 476                         ivar = array_rd32(E1000_IVAR0, index);
 477                         if (tx_queue & 0x1) {
 478                                 /* vector goes into high byte of register */
 479                                 ivar = ivar & 0x00FFFFFF;
 480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 481                         } else {
 482                                 /* vector goes into second byte of register */
 483                                 ivar = ivar & 0xFFFF00FF;
 484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 485                         }
 486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 487                         array_wr32(E1000_IVAR0, index, ivar);
 488                 }
 489                 break;
 490         default:
 491                 BUG();
 492                 break;
 493         }
 494 }
 495
 496 /**
 497  * igb_configure_msix - Configure MSI-X hardware
 498  *
 499  * igb_configure_msix sets up the hardware to properly
 500  * generate MSI-X interrupts.
 501  **/
 502 static void igb_configure_msix(struct igb_adapter *adapter)
 503 {
 504         u32 tmp;
 505         int i, vector = 0;
 506         struct e1000_hw *hw = &adapter->hw;
 507
 508         adapter->eims_enable_mask = 0;
 509         if (hw->mac.type == e1000_82576)
 510                 /* Turn on MSI-X capability first, or our settings
 511                  * won't stick.  And it will take days to debug. */
 512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 514                                    E1000_GPIE_NSICR);
 515
 516         for (i = 0; i < adapter->num_tx_queues; i++) {
 517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 519                 adapter->eims_enable_mask |= tx_ring->eims_value;
 520                 if (tx_ring->itr_val)
 521                         writel(tx_ring->itr_val,
 522                                hw->hw_addr + tx_ring->itr_register);
 523                 else
 524                         writel(1, hw->hw_addr + tx_ring->itr_register);
 525         }
 526
 527         for (i = 0; i < adapter->num_rx_queues; i++) {
 528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 529                 rx_ring->buddy = NULL;
 530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 531                 adapter->eims_enable_mask |= rx_ring->eims_value;
 532                 if (rx_ring->itr_val)
 533                         writel(rx_ring->itr_val,
 534                                hw->hw_addr + rx_ring->itr_register);
 535                 else
 536                         writel(1, hw->hw_addr + rx_ring->itr_register);
 537         }
 538
 539
 540         /* set vector for other causes, i.e. link changes */
 541         switch (hw->mac.type) {
 542         case e1000_82575:
 543                 array_wr32(E1000_MSIXBM(0), vector++,
 544                                       E1000_EIMS_OTHER);
 545
 546                 tmp = rd32(E1000_CTRL_EXT);
 547                 /* enable MSI-X PBA support*/
 548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 549
 550                 /* Auto-Mask interrupts upon ICR read. */
 551                 tmp |= E1000_CTRL_EXT_EIAME;
 552                 tmp |= E1000_CTRL_EXT_IRCA;
 553
 554                 wr32(E1000_CTRL_EXT, tmp);
 555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 556                 adapter->eims_other = E1000_EIMS_OTHER;
 557
 558                 break;
 559
 560         case e1000_82576:
 561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 562                 wr32(E1000_IVAR_MISC, tmp);
 563
 564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 565                 adapter->eims_other = 1 << (vector - 1);
 566                 break;
 567         default:
 568                 /* do nothing, since nothing else supports MSI-X */
 569                 break;
 570         } /* switch (hw->mac.type) */
 571         wrfl();
 572 }
 573
 574 /**
 575  * igb_request_msix - Initialize MSI-X interrupts
 576  *
 577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 578  * kernel.
 579  **/
 580 static int igb_request_msix(struct igb_adapter *adapter)
 581 {
 582         struct net_device *netdev = adapter->netdev;
 583         int i, err = 0, vector = 0;
 584
 585         vector = 0;
 586
 587         for (i = 0; i < adapter->num_tx_queues; i++) {
 588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 590                 err = request_irq(adapter->msix_entries[vector].vector,
 591                                   &igb_msix_tx, 0, ring->name,
 592                                   &(adapter->tx_ring[i]));
 593                 if (err)
 594                         goto out;
 595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 596                 ring->itr_val = 976; /* ~4000 ints/sec */
 597                 vector++;
 598         }
 599         for (i = 0; i < adapter->num_rx_queues; i++) {
 600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 603                 else
 604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 605                 err = request_irq(adapter->msix_entries[vector].vector,
 606                                   &igb_msix_rx, 0, ring->name,
 607                                   &(adapter->rx_ring[i]));
 608                 if (err)
 609                         goto out;
 610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 611                 ring->itr_val = adapter->itr;
 612                 vector++;
 613         }
 614
 615         err = request_irq(adapter->msix_entries[vector].vector,
 616                           &igb_msix_other, 0, netdev->name, netdev);
 617         if (err)
 618                 goto out;
 619
 620         igb_configure_msix(adapter);
 621         return 0;
 622 out:
 623         return err;
 624 }
 625
 626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 627 {
 628         if (adapter->msix_entries) {
 629                 pci_disable_msix(adapter->pdev);
 630                 kfree(adapter->msix_entries);
 631                 adapter->msix_entries = NULL;
 632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 633                 pci_disable_msi(adapter->pdev);
 634         return;
 635 }
 636
 637
 638 /**
 639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 640  *
 641  * Attempt to configure interrupts using the best available
 642  * capabilities of the hardware and kernel.
 643  **/
 644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 645 {
 646         int err;
 647         int numvecs, i;
 648
 649         /* Number of supported queues. */
 650         /* Having more queues than CPUs doesn't make sense. */
 651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 653
 654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 656                                         GFP_KERNEL);
 657         if (!adapter->msix_entries)
 658                 goto msi_only;
 659
 660         for (i = 0; i < numvecs; i++)
 661                 adapter->msix_entries[i].entry = i;
 662
 663         err = pci_enable_msix(adapter->pdev,
 664                               adapter->msix_entries,
 665                               numvecs);
 666         if (err == 0)
 667                 goto out;
 668
 669         igb_reset_interrupt_capability(adapter);
 670
 671         /* If we can't do MSI-X, try MSI */
 672 msi_only:
 673 #ifdef CONFIG_PCI_IOV
 674         /* disable SR-IOV for non MSI-X configurations */
 675         if (adapter->vf_data) {
 676                 struct e1000_hw *hw = &adapter->hw;
 677                 /* disable iov and allow time for transactions to clear */
 678                 pci_disable_sriov(adapter->pdev);
 679                 msleep(500);
 680
 681                 kfree(adapter->vf_data);
 682                 adapter->vf_data = NULL;
 683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 684                 msleep(100);
 685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 686         }
 687 #endif
 688         adapter->num_rx_queues = 1;
 689         adapter->num_tx_queues = 1;
 690         if (!pci_enable_msi(adapter->pdev))
 691                 adapter->flags |= IGB_FLAG_HAS_MSI;
 692 out:
 693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 695         return;
 696 }
 697
 698 /**
 699  * igb_request_irq - initialize interrupts
 700  *
 701  * Attempts to configure interrupts using the best available
 702  * capabilities of the hardware and kernel.
 703  **/
 704 static int igb_request_irq(struct igb_adapter *adapter)
 705 {
 706         struct net_device *netdev = adapter->netdev;
 707         struct e1000_hw *hw = &adapter->hw;
 708         int err = 0;
 709
 710         if (adapter->msix_entries) {
 711                 err = igb_request_msix(adapter);
 712                 if (!err)
 713                         goto request_done;
 714                 /* fall back to MSI */
 715                 igb_reset_interrupt_capability(adapter);
 716                 if (!pci_enable_msi(adapter->pdev))
 717                         adapter->flags |= IGB_FLAG_HAS_MSI;
 718                 igb_free_all_tx_resources(adapter);
 719                 igb_free_all_rx_resources(adapter);
 720                 adapter->num_rx_queues = 1;
 721                 igb_alloc_queues(adapter);
 722         } else {
 723                 switch (hw->mac.type) {
 724                 case e1000_82575:
 725                         wr32(E1000_MSIXBM(0),
 726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 727                         break;
 728                 case e1000_82576:
 729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 730                         break;
 731                 default:
 732                         break;
 733                 }
 734         }
 735
 736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 738                                   netdev->name, netdev);
 739                 if (!err)
 740                         goto request_done;
 741                 /* fall back to legacy interrupts */
 742                 igb_reset_interrupt_capability(adapter);
 743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 744         }
 745
 746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 747                           netdev->name, netdev);
 748
 749         if (err)
 750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 751                         err);
 752
 753 request_done:
 754         return err;
 755 }
 756
 757 static void igb_free_irq(struct igb_adapter *adapter)
 758 {
 759         struct net_device *netdev = adapter->netdev;
 760
 761         if (adapter->msix_entries) {
 762                 int vector = 0, i;
 763
 764                 for (i = 0; i < adapter->num_tx_queues; i++)
 765                         free_irq(adapter->msix_entries[vector++].vector,
 766                                 &(adapter->tx_ring[i]));
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         free_irq(adapter->msix_entries[vector++].vector,
 769                                 &(adapter->rx_ring[i]));
 770
 771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 772                 return;
 773         }
 774
 775         free_irq(adapter->pdev->irq, netdev);
 776 }
 777
 778 /**
 779  * igb_irq_disable - Mask off interrupt generation on the NIC
 780  * @adapter: board private structure
 781  **/
 782 static void igb_irq_disable(struct igb_adapter *adapter)
 783 {
 784         struct e1000_hw *hw = &adapter->hw;
 785
 786         if (adapter->msix_entries) {
 787                 wr32(E1000_EIAM, 0);
 788                 wr32(E1000_EIMC, ~0);
 789                 wr32(E1000_EIAC, 0);
 790         }
 791
 792         wr32(E1000_IAM, 0);
 793         wr32(E1000_IMC, ~0);
 794         wrfl();
 795         synchronize_irq(adapter->pdev->irq);
 796 }
 797
 798 /**
 799  * igb_irq_enable - Enable default interrupt generation settings
 800  * @adapter: board private structure
 801  **/
 802 static void igb_irq_enable(struct igb_adapter *adapter)
 803 {
 804         struct e1000_hw *hw = &adapter->hw;
 805
 806         if (adapter->msix_entries) {
 807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 810                 if (adapter->vfs_allocated_count)
 811                         wr32(E1000_MBVFIMR, 0xFF);
 812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 813                                  E1000_IMS_DOUTSYNC));
 814         } else {
 815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 817         }
 818 }
 819
 820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 821 {
 822         struct net_device *netdev = adapter->netdev;
 823         u16 vid = adapter->hw.mng_cookie.vlan_id;
 824         u16 old_vid = adapter->mng_vlan_id;
 825         if (adapter->vlgrp) {
 826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 827                         if (adapter->hw.mng_cookie.status &
 828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 829                                 igb_vlan_rx_add_vid(netdev, vid);
 830                                 adapter->mng_vlan_id = vid;
 831                         } else
 832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 833
 834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 835                                         (vid != old_vid) &&
 836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 838                 } else
 839                         adapter->mng_vlan_id = vid;
 840         }
 841 }
 842
 843 /**
 844  * igb_release_hw_control - release control of the h/w to f/w
 845  * @adapter: address of board private structure
 846  *
 847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 848  * For ASF and Pass Through versions of f/w this means that the
 849  * driver is no longer loaded.
 850  *
 851  **/
 852 static void igb_release_hw_control(struct igb_adapter *adapter)
 853 {
 854         struct e1000_hw *hw = &adapter->hw;
 855         u32 ctrl_ext;
 856
 857         /* Let firmware take over control of h/w */
 858         ctrl_ext = rd32(E1000_CTRL_EXT);
 859         wr32(E1000_CTRL_EXT,
 860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 861 }
 862
 863
 864 /**
 865  * igb_get_hw_control - get control of the h/w from f/w
 866  * @adapter: address of board private structure
 867  *
 868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 869  * For ASF and Pass Through versions of f/w this means that
 870  * the driver is loaded.
 871  *
 872  **/
 873 static void igb_get_hw_control(struct igb_adapter *adapter)
 874 {
 875         struct e1000_hw *hw = &adapter->hw;
 876         u32 ctrl_ext;
 877
 878         /* Let firmware know the driver has taken over */
 879         ctrl_ext = rd32(E1000_CTRL_EXT);
 880         wr32(E1000_CTRL_EXT,
 881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 882 }
 883
 884 /**
 885  * igb_configure - configure the hardware for RX and TX
 886  * @adapter: private board structure
 887  **/
 888 static void igb_configure(struct igb_adapter *adapter)
 889 {
 890         struct net_device *netdev = adapter->netdev;
 891         int i;
 892
 893         igb_get_hw_control(adapter);
 894         igb_set_multi(netdev);
 895
 896         igb_restore_vlan(adapter);
 897
 898         igb_configure_tx(adapter);
 899         igb_setup_rctl(adapter);
 900         igb_configure_rx(adapter);
 901
 902         igb_rx_fifo_flush_82575(&adapter->hw);
 903
 904         /* call igb_desc_unused which always leaves
 905          * at least 1 descriptor unused to make sure
 906          * next_to_use != next_to_clean */
 907         for (i = 0; i < adapter->num_rx_queues; i++) {
 908                 struct igb_ring *ring = &adapter->rx_ring[i];
 909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 910         }
 911
 912
 913         adapter->tx_queue_len = netdev->tx_queue_len;
 914 }
 915
 916
 917 /**
 918  * igb_up - Open the interface and prepare it to handle traffic
 919  * @adapter: board private structure
 920  **/
 921
 922 int igb_up(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         int i;
 926
 927         /* hardware has been reset, we need to reload some things */
 928         igb_configure(adapter);
 929
 930         clear_bit(__IGB_DOWN, &adapter->state);
 931
 932         for (i = 0; i < adapter->num_rx_queues; i++)
 933                 napi_enable(&adapter->rx_ring[i].napi);
 934         if (adapter->msix_entries)
 935                 igb_configure_msix(adapter);
 936
 937         igb_vmm_control(adapter);
 938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 940
 941         /* Clear any pending interrupts. */
 942         rd32(E1000_ICR);
 943         igb_irq_enable(adapter);
 944
 945         netif_tx_start_all_queues(adapter->netdev);
 946
 947         /* Fire a link change interrupt to start the watchdog. */
 948         wr32(E1000_ICS, E1000_ICS_LSC);
 949         return 0;
 950 }
 951
 952 void igb_down(struct igb_adapter *adapter)
 953 {
 954         struct e1000_hw *hw = &adapter->hw;
 955         struct net_device *netdev = adapter->netdev;
 956         u32 tctl, rctl;
 957         int i;
 958
 959         /* signal that we're down so the interrupt handler does not
 960          * reschedule our watchdog timer */
 961         set_bit(__IGB_DOWN, &adapter->state);
 962
 963         /* disable receives in the hardware */
 964         rctl = rd32(E1000_RCTL);
 965         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 966         /* flush and sleep below */
 967
 968         netif_tx_stop_all_queues(netdev);
 969
 970         /* disable transmits in the hardware */
 971         tctl = rd32(E1000_TCTL);
 972         tctl &= ~E1000_TCTL_EN;
 973         wr32(E1000_TCTL, tctl);
 974         /* flush both disables and wait for them to finish */
 975         wrfl();
 976         msleep(10);
 977
 978         for (i = 0; i < adapter->num_rx_queues; i++)
 979                 napi_disable(&adapter->rx_ring[i].napi);
 980
 981         igb_irq_disable(adapter);
 982
 983         del_timer_sync(&adapter->watchdog_timer);
 984         del_timer_sync(&adapter->phy_info_timer);
 985
 986         netdev->tx_queue_len = adapter->tx_queue_len;
 987         netif_carrier_off(netdev);
 988
 989         /* record the stats before reset*/
 990         igb_update_stats(adapter);
 991
 992         adapter->link_speed = 0;
 993         adapter->link_duplex = 0;
 994
 995         if (!pci_channel_offline(adapter->pdev))
 996                 igb_reset(adapter);
 997         igb_clean_all_tx_rings(adapter);
 998         igb_clean_all_rx_rings(adapter);
 999 }
1000
1001 void igb_reinit_locked(struct igb_adapter *adapter)
1002 {
1003         WARN_ON(in_interrupt());
1004         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1005                 msleep(1);
1006         igb_down(adapter);
1007         igb_up(adapter);
1008         clear_bit(__IGB_RESETTING, &adapter->state);
1009 }
1010
1011 void igb_reset(struct igb_adapter *adapter)
1012 {
1013         struct e1000_hw *hw = &adapter->hw;
1014         struct e1000_mac_info *mac = &hw->mac;
1015         struct e1000_fc_info *fc = &hw->fc;
1016         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1017         u16 hwm;
1018
1019         /* Repartition Pba for greater than 9k mtu
1020          * To take effect CTRL.RST is required.
1021          */
1022         switch (mac->type) {
1023         case e1000_82576:
1024                 pba = E1000_PBA_64K;
1025                 break;
1026         case e1000_82575:
1027         default:
1028                 pba = E1000_PBA_34K;
1029                 break;
1030         }
1031
1032         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1033             (mac->type < e1000_82576)) {
1034                 /* adjust PBA for jumbo frames */
1035                 wr32(E1000_PBA, pba);
1036
1037                 /* To maintain wire speed transmits, the Tx FIFO should be
1038                  * large enough to accommodate two full transmit packets,
1039                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1040                  * the Rx FIFO should be large enough to accommodate at least
1041                  * one full receive packet and is similarly rounded up and
1042                  * expressed in KB. */
1043                 pba = rd32(E1000_PBA);
1044                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1045                 tx_space = pba >> 16;
1046                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1047                 pba &= 0xffff;
1048                 /* the tx fifo also stores 16 bytes of information about the tx
1049                  * but don't include ethernet FCS because hardware appends it */
1050                 min_tx_space = (adapter->max_frame_size +
1051                                 sizeof(union e1000_adv_tx_desc) -
1052                                 ETH_FCS_LEN) * 2;
1053                 min_tx_space = ALIGN(min_tx_space, 1024);
1054                 min_tx_space >>= 10;
1055                 /* software strips receive CRC, so leave room for it */
1056                 min_rx_space = adapter->max_frame_size;
1057                 min_rx_space = ALIGN(min_rx_space, 1024);
1058                 min_rx_space >>= 10;
1059
1060                 /* If current Tx allocation is less than the min Tx FIFO size,
1061                  * and the min Tx FIFO size is less than the current Rx FIFO
1062                  * allocation, take space away from current Rx allocation */
1063                 if (tx_space < min_tx_space &&
1064                     ((min_tx_space - tx_space) < pba)) {
1065                         pba = pba - (min_tx_space - tx_space);
1066
1067                         /* if short on rx space, rx wins and must trump tx
1068                          * adjustment */
1069                         if (pba < min_rx_space)
1070                                 pba = min_rx_space;
1071                 }
1072                 wr32(E1000_PBA, pba);
1073         }
1074
1075         /* flow control settings */
1076         /* The high water mark must be low enough to fit one full frame
1077          * (or the size used for early receive) above it in the Rx FIFO.
1078          * Set it to the lower of:
1079          * - 90% of the Rx FIFO size, or
1080          * - the full Rx FIFO size minus one full frame */
1081         hwm = min(((pba << 10) * 9 / 10),
1082                         ((pba << 10) - 2 * adapter->max_frame_size));
1083
1084         if (mac->type < e1000_82576) {
1085                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1086                 fc->low_water = fc->high_water - 8;
1087         } else {
1088                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1089                 fc->low_water = fc->high_water - 16;
1090         }
1091         fc->pause_time = 0xFFFF;
1092         fc->send_xon = 1;
1093         fc->type = fc->original_type;
1094
1095         /* disable receive for all VFs and wait one second */
1096         if (adapter->vfs_allocated_count) {
1097                 int i;
1098                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1099                         adapter->vf_data[i].clear_to_send = false;
1100
1101                 /* ping all the active vfs to let them know we are going down */
1102                         igb_ping_all_vfs(adapter);
1103
1104                 /* disable transmits and receives */
1105                 wr32(E1000_VFRE, 0);
1106                 wr32(E1000_VFTE, 0);
1107         }
1108
1109         /* Allow time for pending master requests to run */
1110         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1111         wr32(E1000_WUC, 0);
1112
1113         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1114                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1115
1116         igb_update_mng_vlan(adapter);
1117
1118         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1119         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1120
1121         igb_reset_adaptive(&adapter->hw);
1122         igb_get_phy_info(&adapter->hw);
1123 }
1124
1125 static const struct net_device_ops igb_netdev_ops = {
1126         .ndo_open               = igb_open,
1127         .ndo_stop               = igb_close,
1128         .ndo_start_xmit         = igb_xmit_frame_adv,
1129         .ndo_get_stats          = igb_get_stats,
1130         .ndo_set_multicast_list = igb_set_multi,
1131         .ndo_set_mac_address    = igb_set_mac,
1132         .ndo_change_mtu         = igb_change_mtu,
1133         .ndo_do_ioctl           = igb_ioctl,
1134         .ndo_tx_timeout         = igb_tx_timeout,
1135         .ndo_validate_addr      = eth_validate_addr,
1136         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1137         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1138         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1139 #ifdef CONFIG_NET_POLL_CONTROLLER
1140         .ndo_poll_controller    = igb_netpoll,
1141 #endif
1142 };
1143
1144 /**
1145  * igb_probe - Device Initialization Routine
1146  * @pdev: PCI device information struct
1147  * @ent: entry in igb_pci_tbl
1148  *
1149  * Returns 0 on success, negative on failure
1150  *
1151  * igb_probe initializes an adapter identified by a pci_dev structure.
1152  * The OS initialization, configuring of the adapter private structure,
1153  * and a hardware reset occur.
1154  **/
1155 static int __devinit igb_probe(struct pci_dev *pdev,
1156                                const struct pci_device_id *ent)
1157 {
1158         struct net_device *netdev;
1159         struct igb_adapter *adapter;
1160         struct e1000_hw *hw;
1161         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1162         unsigned long mmio_start, mmio_len;
1163         int err, pci_using_dac;
1164         u16 eeprom_data = 0;
1165         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1166         u32 part_num;
1167
1168         err = pci_enable_device_mem(pdev);
1169         if (err)
1170                 return err;
1171
1172         pci_using_dac = 0;
1173         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1174         if (!err) {
1175                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1176                 if (!err)
1177                         pci_using_dac = 1;
1178         } else {
1179                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1180                 if (err) {
1181                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1182                         if (err) {
1183                                 dev_err(&pdev->dev, "No usable DMA "
1184                                         "configuration, aborting\n");
1185                                 goto err_dma;
1186                         }
1187                 }
1188         }
1189
1190         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1191                                            IORESOURCE_MEM),
1192                                            igb_driver_name);
1193         if (err)
1194                 goto err_pci_reg;
1195
1196         err = pci_enable_pcie_error_reporting(pdev);
1197         if (err) {
1198                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1199                         "0x%x\n", err);
1200                 /* non-fatal, continue */
1201         }
1202
1203         pci_set_master(pdev);
1204         pci_save_state(pdev);
1205
1206         err = -ENOMEM;
1207         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1208                                    IGB_ABS_MAX_TX_QUEUES);
1209         if (!netdev)
1210                 goto err_alloc_etherdev;
1211
1212         SET_NETDEV_DEV(netdev, &pdev->dev);
1213
1214         pci_set_drvdata(pdev, netdev);
1215         adapter = netdev_priv(netdev);
1216         adapter->netdev = netdev;
1217         adapter->pdev = pdev;
1218         hw = &adapter->hw;
1219         hw->back = adapter;
1220         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1221
1222         mmio_start = pci_resource_start(pdev, 0);
1223         mmio_len = pci_resource_len(pdev, 0);
1224
1225         err = -EIO;
1226         hw->hw_addr = ioremap(mmio_start, mmio_len);
1227         if (!hw->hw_addr)
1228                 goto err_ioremap;
1229
1230         netdev->netdev_ops = &igb_netdev_ops;
1231         igb_set_ethtool_ops(netdev);
1232         netdev->watchdog_timeo = 5 * HZ;
1233
1234         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1235
1236         netdev->mem_start = mmio_start;
1237         netdev->mem_end = mmio_start + mmio_len;
1238
1239         /* PCI config space info */
1240         hw->vendor_id = pdev->vendor;
1241         hw->device_id = pdev->device;
1242         hw->revision_id = pdev->revision;
1243         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1244         hw->subsystem_device_id = pdev->subsystem_device;
1245
1246         /* setup the private structure */
1247         hw->back = adapter;
1248         /* Copy the default MAC, PHY and NVM function pointers */
1249         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1250         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1251         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1252         /* Initialize skew-specific constants */
1253         err = ei->get_invariants(hw);
1254         if (err)
1255                 goto err_sw_init;
1256
1257 #ifdef CONFIG_PCI_IOV
1258         /* since iov functionality isn't critical to base device function we
1259          * can accept failure.  If it fails we don't allow iov to be enabled */
1260         if (hw->mac.type == e1000_82576) {
1261                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1262                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1263                 int i;
1264                 unsigned char mac_addr[ETH_ALEN];
1265
1266                 if (num_vfs) {
1267                         adapter->vf_data = kcalloc(num_vfs,
1268                                                 sizeof(struct vf_data_storage),
1269                                                 GFP_KERNEL);
1270                         if (!adapter->vf_data) {
1271                                 dev_err(&pdev->dev,
1272                                         "Could not allocate VF private data - "
1273                                         "IOV enable failed\n");
1274                         } else {
1275                                 err = pci_enable_sriov(pdev, num_vfs);
1276                                 if (!err) {
1277                                         adapter->vfs_allocated_count = num_vfs;
1278                                         dev_info(&pdev->dev,
1279                                                  "%d vfs allocated\n",
1280                                                  num_vfs);
1281                                         for (i = 0;
1282                                              i < adapter->vfs_allocated_count;
1283                                              i++) {
1284                                                 random_ether_addr(mac_addr);
1285                                                 igb_set_vf_mac(adapter, i,
1286                                                                mac_addr);
1287                                         }
1288                                 } else {
1289                                         kfree(adapter->vf_data);
1290                                         adapter->vf_data = NULL;
1291                                 }
1292                         }
1293                 }
1294         }
1295
1296 #endif
1297         /* setup the private structure */
1298         err = igb_sw_init(adapter);
1299         if (err)
1300                 goto err_sw_init;
1301
1302         igb_get_bus_info_pcie(hw);
1303
1304         /* set flags */
1305         switch (hw->mac.type) {
1306         case e1000_82575:
1307                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1308                 break;
1309         case e1000_82576:
1310         default:
1311                 break;
1312         }
1313
1314         hw->phy.autoneg_wait_to_complete = false;
1315         hw->mac.adaptive_ifs = true;
1316
1317         /* Copper options */
1318         if (hw->phy.media_type == e1000_media_type_copper) {
1319                 hw->phy.mdix = AUTO_ALL_MODES;
1320                 hw->phy.disable_polarity_correction = false;
1321                 hw->phy.ms_type = e1000_ms_hw_default;
1322         }
1323
1324         if (igb_check_reset_block(hw))
1325                 dev_info(&pdev->dev,
1326                         "PHY reset is blocked due to SOL/IDER session.\n");
1327
1328         netdev->features = NETIF_F_SG |
1329                            NETIF_F_IP_CSUM |
1330                            NETIF_F_HW_VLAN_TX |
1331                            NETIF_F_HW_VLAN_RX |
1332                            NETIF_F_HW_VLAN_FILTER;
1333
1334         netdev->features |= NETIF_F_IPV6_CSUM;
1335         netdev->features |= NETIF_F_TSO;
1336         netdev->features |= NETIF_F_TSO6;
1337
1338         netdev->features |= NETIF_F_GRO;
1339
1340         netdev->vlan_features |= NETIF_F_TSO;
1341         netdev->vlan_features |= NETIF_F_TSO6;
1342         netdev->vlan_features |= NETIF_F_IP_CSUM;
1343         netdev->vlan_features |= NETIF_F_SG;
1344
1345         if (pci_using_dac)
1346                 netdev->features |= NETIF_F_HIGHDMA;
1347
1348         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1349
1350         /* before reading the NVM, reset the controller to put the device in a
1351          * known good starting state */
1352         hw->mac.ops.reset_hw(hw);
1353
1354         /* make sure the NVM is good */
1355         if (igb_validate_nvm_checksum(hw) < 0) {
1356                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1357                 err = -EIO;
1358                 goto err_eeprom;
1359         }
1360
1361         /* copy the MAC address out of the NVM */
1362         if (hw->mac.ops.read_mac_addr(hw))
1363                 dev_err(&pdev->dev, "NVM Read Error\n");
1364
1365         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1366         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1367
1368         if (!is_valid_ether_addr(netdev->perm_addr)) {
1369                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1370                 err = -EIO;
1371                 goto err_eeprom;
1372         }
1373
1374         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1375                     (unsigned long) adapter);
1376         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1377                     (unsigned long) adapter);
1378
1379         INIT_WORK(&adapter->reset_task, igb_reset_task);
1380         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1381
1382         /* Initialize link properties that are user-changeable */
1383         adapter->fc_autoneg = true;
1384         hw->mac.autoneg = true;
1385         hw->phy.autoneg_advertised = 0x2f;
1386
1387         hw->fc.original_type = e1000_fc_default;
1388         hw->fc.type = e1000_fc_default;
1389
1390         adapter->itr_setting = IGB_DEFAULT_ITR;
1391         adapter->itr = IGB_START_ITR;
1392
1393         igb_validate_mdi_setting(hw);
1394
1395         adapter->rx_csum = 1;
1396
1397         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1398          * enable the ACPI Magic Packet filter
1399          */
1400
1401         if (hw->bus.func == 0)
1402                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1403         else if (hw->bus.func == 1)
1404                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1405
1406         if (eeprom_data & eeprom_apme_mask)
1407                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1408
1409         /* now that we have the eeprom settings, apply the special cases where
1410          * the eeprom may be wrong or the board simply won't support wake on
1411          * lan on a particular port */
1412         switch (pdev->device) {
1413         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1414                 adapter->eeprom_wol = 0;
1415                 break;
1416         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1417         case E1000_DEV_ID_82576_FIBER:
1418         case E1000_DEV_ID_82576_SERDES:
1419                 /* Wake events only supported on port A for dual fiber
1420                  * regardless of eeprom setting */
1421                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1422                         adapter->eeprom_wol = 0;
1423                 break;
1424         case E1000_DEV_ID_82576_QUAD_COPPER:
1425                 /* if quad port adapter, disable WoL on all but port A */
1426                 if (global_quad_port_a != 0)
1427                         adapter->eeprom_wol = 0;
1428                 else
1429                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1430                 /* Reset for multiple quad port adapters */
1431                 if (++global_quad_port_a == 4)
1432                         global_quad_port_a = 0;
1433                 break;
1434         }
1435
1436         /* initialize the wol settings based on the eeprom settings */
1437         adapter->wol = adapter->eeprom_wol;
1438         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1439
1440         /* reset the hardware with the new settings */
1441         igb_reset(adapter);
1442
1443         /* let the f/w know that the h/w is now under the control of the
1444          * driver. */
1445         igb_get_hw_control(adapter);
1446
1447         strcpy(netdev->name, "eth%d");
1448         err = register_netdev(netdev);
1449         if (err)
1450                 goto err_register;
1451
1452         /* carrier off reporting is important to ethtool even BEFORE open */
1453         netif_carrier_off(netdev);
1454
1455 #ifdef CONFIG_IGB_DCA
1456         if (dca_add_requester(&pdev->dev) == 0) {
1457                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1458                 dev_info(&pdev->dev, "DCA enabled\n");
1459                 /* Always use CB2 mode, difference is masked
1460                  * in the CB driver. */
1461                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1462                 igb_setup_dca(adapter);
1463         }
1464 #endif
1465
1466         /*
1467          * Initialize hardware timer: we keep it running just in case
1468          * that some program needs it later on.
1469          */
1470         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1471         adapter->cycles.read = igb_read_clock;
1472         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1473         adapter->cycles.mult = 1;
1474         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1475         wr32(E1000_TIMINCA,
1476              (1<<24) |
1477              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1478 #if 0
1479         /*
1480          * Avoid rollover while we initialize by resetting the time counter.
1481          */
1482         wr32(E1000_SYSTIML, 0x00000000);
1483         wr32(E1000_SYSTIMH, 0x00000000);
1484 #else
1485         /*
1486          * Set registers so that rollover occurs soon to test this.
1487          */
1488         wr32(E1000_SYSTIML, 0x00000000);
1489         wr32(E1000_SYSTIMH, 0xFF800000);
1490 #endif
1491         wrfl();
1492         timecounter_init(&adapter->clock,
1493                          &adapter->cycles,
1494                          ktime_to_ns(ktime_get_real()));
1495
1496         /*
1497          * Synchronize our NIC clock against system wall clock. NIC
1498          * time stamp reading requires ~3us per sample, each sample
1499          * was pretty stable even under load => only require 10
1500          * samples for each offset comparison.
1501          */
1502         memset(&adapter->compare, 0, sizeof(adapter->compare));
1503         adapter->compare.source = &adapter->clock;
1504         adapter->compare.target = ktime_get_real;
1505         adapter->compare.num_samples = 10;
1506         timecompare_update(&adapter->compare, 0);
1507
1508 #ifdef DEBUG
1509         {
1510                 char buffer[160];
1511                 printk(KERN_DEBUG
1512                         "igb: %s: hw %p initialized timer\n",
1513                         igb_get_time_str(adapter, buffer),
1514                         &adapter->hw);
1515         }
1516 #endif
1517
1518         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1519         /* print bus type/speed/width info */
1520         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1521                  netdev->name,
1522                  ((hw->bus.speed == e1000_bus_speed_2500)
1523                   ? "2.5Gb/s" : "unknown"),
1524                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1525                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1526                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1527                    "unknown"),
1528                  netdev->dev_addr);
1529
1530         igb_read_part_num(hw, &part_num);
1531         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1532                 (part_num >> 8), (part_num & 0xff));
1533
1534         dev_info(&pdev->dev,
1535                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1536                 adapter->msix_entries ? "MSI-X" :
1537                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1538                 adapter->num_rx_queues, adapter->num_tx_queues);
1539
1540         return 0;
1541
1542 err_register:
1543         igb_release_hw_control(adapter);
1544 err_eeprom:
1545         if (!igb_check_reset_block(hw))
1546                 igb_reset_phy(hw);
1547
1548         if (hw->flash_address)
1549                 iounmap(hw->flash_address);
1550
1551         igb_free_queues(adapter);
1552 err_sw_init:
1553         iounmap(hw->hw_addr);
1554 err_ioremap:
1555         free_netdev(netdev);
1556 err_alloc_etherdev:
1557         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1558                                      IORESOURCE_MEM));
1559 err_pci_reg:
1560 err_dma:
1561         pci_disable_device(pdev);
1562         return err;
1563 }
1564
1565 /**
1566  * igb_remove - Device Removal Routine
1567  * @pdev: PCI device information struct
1568  *
1569  * igb_remove is called by the PCI subsystem to alert the driver
1570  * that it should release a PCI device.  The could be caused by a
1571  * Hot-Plug event, or because the driver is going to be removed from
1572  * memory.
1573  **/
1574 static void __devexit igb_remove(struct pci_dev *pdev)
1575 {
1576         struct net_device *netdev = pci_get_drvdata(pdev);
1577         struct igb_adapter *adapter = netdev_priv(netdev);
1578         struct e1000_hw *hw = &adapter->hw;
1579         int err;
1580
1581         /* flush_scheduled work may reschedule our watchdog task, so
1582          * explicitly disable watchdog tasks from being rescheduled  */
1583         set_bit(__IGB_DOWN, &adapter->state);
1584         del_timer_sync(&adapter->watchdog_timer);
1585         del_timer_sync(&adapter->phy_info_timer);
1586
1587         flush_scheduled_work();
1588
1589 #ifdef CONFIG_IGB_DCA
1590         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1591                 dev_info(&pdev->dev, "DCA disabled\n");
1592                 dca_remove_requester(&pdev->dev);
1593                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1594                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1595         }
1596 #endif
1597
1598         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1599          * would have already happened in close and is redundant. */
1600         igb_release_hw_control(adapter);
1601
1602         unregister_netdev(netdev);
1603
1604         if (!igb_check_reset_block(&adapter->hw))
1605                 igb_reset_phy(&adapter->hw);
1606
1607         igb_reset_interrupt_capability(adapter);
1608
1609         igb_free_queues(adapter);
1610
1611 #ifdef CONFIG_PCI_IOV
1612         /* reclaim resources allocated to VFs */
1613         if (adapter->vf_data) {
1614                 /* disable iov and allow time for transactions to clear */
1615                 pci_disable_sriov(pdev);
1616                 msleep(500);
1617
1618                 kfree(adapter->vf_data);
1619                 adapter->vf_data = NULL;
1620                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1621                 msleep(100);
1622                 dev_info(&pdev->dev, "IOV Disabled\n");
1623         }
1624 #endif
1625         iounmap(hw->hw_addr);
1626         if (hw->flash_address)
1627                 iounmap(hw->flash_address);
1628         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1629                                      IORESOURCE_MEM));
1630
1631         free_netdev(netdev);
1632
1633         err = pci_disable_pcie_error_reporting(pdev);
1634         if (err)
1635                 dev_err(&pdev->dev,
1636                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1637
1638         pci_disable_device(pdev);
1639 }
1640
1641 /**
1642  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1643  * @adapter: board private structure to initialize
1644  *
1645  * igb_sw_init initializes the Adapter private data structure.
1646  * Fields are initialized based on PCI device information and
1647  * OS network device settings (MTU size).
1648  **/
1649 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1650 {
1651         struct e1000_hw *hw = &adapter->hw;
1652         struct net_device *netdev = adapter->netdev;
1653         struct pci_dev *pdev = adapter->pdev;
1654
1655         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1656
1657         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1658         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1659         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1660         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1661         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1662         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1663
1664         /* This call may decrease the number of queues depending on
1665          * interrupt mode. */
1666         igb_set_interrupt_capability(adapter);
1667
1668         if (igb_alloc_queues(adapter)) {
1669                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1670                 return -ENOMEM;
1671         }
1672
1673         /* Explicitly disable IRQ since the NIC can be in any state. */
1674         igb_irq_disable(adapter);
1675
1676         set_bit(__IGB_DOWN, &adapter->state);
1677         return 0;
1678 }
1679
1680 /**
1681  * igb_open - Called when a network interface is made active
1682  * @netdev: network interface device structure
1683  *
1684  * Returns 0 on success, negative value on failure
1685  *
1686  * The open entry point is called when a network interface is made
1687  * active by the system (IFF_UP).  At this point all resources needed
1688  * for transmit and receive operations are allocated, the interrupt
1689  * handler is registered with the OS, the watchdog timer is started,
1690  * and the stack is notified that the interface is ready.
1691  **/
1692 static int igb_open(struct net_device *netdev)
1693 {
1694         struct igb_adapter *adapter = netdev_priv(netdev);
1695         struct e1000_hw *hw = &adapter->hw;
1696         int err;
1697         int i;
1698
1699         /* disallow open during test */
1700         if (test_bit(__IGB_TESTING, &adapter->state))
1701                 return -EBUSY;
1702
1703         netif_carrier_off(netdev);
1704
1705         /* allocate transmit descriptors */
1706         err = igb_setup_all_tx_resources(adapter);
1707         if (err)
1708                 goto err_setup_tx;
1709
1710         /* allocate receive descriptors */
1711         err = igb_setup_all_rx_resources(adapter);
1712         if (err)
1713                 goto err_setup_rx;
1714
1715         /* e1000_power_up_phy(adapter); */
1716
1717         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1718         if ((adapter->hw.mng_cookie.status &
1719              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1720                 igb_update_mng_vlan(adapter);
1721
1722         /* before we allocate an interrupt, we must be ready to handle it.
1723          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1724          * as soon as we call pci_request_irq, so we have to setup our
1725          * clean_rx handler before we do so.  */
1726         igb_configure(adapter);
1727
1728         igb_vmm_control(adapter);
1729         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1730         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1731
1732         err = igb_request_irq(adapter);
1733         if (err)
1734                 goto err_req_irq;
1735
1736         /* From here on the code is the same as igb_up() */
1737         clear_bit(__IGB_DOWN, &adapter->state);
1738
1739         for (i = 0; i < adapter->num_rx_queues; i++)
1740                 napi_enable(&adapter->rx_ring[i].napi);
1741
1742         /* Clear any pending interrupts. */
1743         rd32(E1000_ICR);
1744
1745         igb_irq_enable(adapter);
1746
1747         netif_tx_start_all_queues(netdev);
1748
1749         /* Fire a link status change interrupt to start the watchdog. */
1750         wr32(E1000_ICS, E1000_ICS_LSC);
1751
1752         return 0;
1753
1754 err_req_irq:
1755         igb_release_hw_control(adapter);
1756         /* e1000_power_down_phy(adapter); */
1757         igb_free_all_rx_resources(adapter);
1758 err_setup_rx:
1759         igb_free_all_tx_resources(adapter);
1760 err_setup_tx:
1761         igb_reset(adapter);
1762
1763         return err;
1764 }
1765
1766 /**
1767  * igb_close - Disables a network interface
1768  * @netdev: network interface device structure
1769  *
1770  * Returns 0, this is not allowed to fail
1771  *
1772  * The close entry point is called when an interface is de-activated
1773  * by the OS.  The hardware is still under the driver's control, but
1774  * needs to be disabled.  A global MAC reset is issued to stop the
1775  * hardware, and all transmit and receive resources are freed.
1776  **/
1777 static int igb_close(struct net_device *netdev)
1778 {
1779         struct igb_adapter *adapter = netdev_priv(netdev);
1780
1781         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1782         igb_down(adapter);
1783
1784         igb_free_irq(adapter);
1785
1786         igb_free_all_tx_resources(adapter);
1787         igb_free_all_rx_resources(adapter);
1788
1789         /* kill manageability vlan ID if supported, but not if a vlan with
1790          * the same ID is registered on the host OS (let 8021q kill it) */
1791         if ((adapter->hw.mng_cookie.status &
1792                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1793              !(adapter->vlgrp &&
1794                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1795                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1796
1797         return 0;
1798 }
1799
1800 /**
1801  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1802  * @adapter: board private structure
1803  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1804  *
1805  * Return 0 on success, negative on failure
1806  **/
1807 int igb_setup_tx_resources(struct igb_adapter *adapter,
1808                            struct igb_ring *tx_ring)
1809 {
1810         struct pci_dev *pdev = adapter->pdev;
1811         int size;
1812
1813         size = sizeof(struct igb_buffer) * tx_ring->count;
1814         tx_ring->buffer_info = vmalloc(size);
1815         if (!tx_ring->buffer_info)
1816                 goto err;
1817         memset(tx_ring->buffer_info, 0, size);
1818
1819         /* round up to nearest 4K */
1820         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1821         tx_ring->size = ALIGN(tx_ring->size, 4096);
1822
1823         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1824                                              &tx_ring->dma);
1825
1826         if (!tx_ring->desc)
1827                 goto err;
1828
1829         tx_ring->adapter = adapter;
1830         tx_ring->next_to_use = 0;
1831         tx_ring->next_to_clean = 0;
1832         return 0;
1833
1834 err:
1835         vfree(tx_ring->buffer_info);
1836         dev_err(&adapter->pdev->dev,
1837                 "Unable to allocate memory for the transmit descriptor ring\n");
1838         return -ENOMEM;
1839 }
1840
1841 /**
1842  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1843  *                                (Descriptors) for all queues
1844  * @adapter: board private structure
1845  *
1846  * Return 0 on success, negative on failure
1847  **/
1848 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1849 {
1850         int i, err = 0;
1851         int r_idx;
1852
1853         for (i = 0; i < adapter->num_tx_queues; i++) {
1854                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1855                 if (err) {
1856                         dev_err(&adapter->pdev->dev,
1857                                 "Allocation for Tx Queue %u failed\n", i);
1858                         for (i--; i >= 0; i--)
1859                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1860                         break;
1861                 }
1862         }
1863
1864         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1865                 r_idx = i % adapter->num_tx_queues;
1866                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1867         }
1868         return err;
1869 }
1870
1871 /**
1872  * igb_configure_tx - Configure transmit Unit after Reset
1873  * @adapter: board private structure
1874  *
1875  * Configure the Tx unit of the MAC after a reset.
1876  **/
1877 static void igb_configure_tx(struct igb_adapter *adapter)
1878 {
1879         u64 tdba;
1880         struct e1000_hw *hw = &adapter->hw;
1881         u32 tctl;
1882         u32 txdctl, txctrl;
1883         int i, j;
1884
1885         for (i = 0; i < adapter->num_tx_queues; i++) {
1886                 struct igb_ring *ring = &adapter->tx_ring[i];
1887                 j = ring->reg_idx;
1888                 wr32(E1000_TDLEN(j),
1889                      ring->count * sizeof(union e1000_adv_tx_desc));
1890                 tdba = ring->dma;
1891                 wr32(E1000_TDBAL(j),
1892                      tdba & 0x00000000ffffffffULL);
1893                 wr32(E1000_TDBAH(j), tdba >> 32);
1894
1895                 ring->head = E1000_TDH(j);
1896                 ring->tail = E1000_TDT(j);
1897                 writel(0, hw->hw_addr + ring->tail);
1898                 writel(0, hw->hw_addr + ring->head);
1899                 txdctl = rd32(E1000_TXDCTL(j));
1900                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1901                 wr32(E1000_TXDCTL(j), txdctl);
1902
1903                 /* Turn off Relaxed Ordering on head write-backs.  The
1904                  * writebacks MUST be delivered in order or it will
1905                  * completely screw up our bookeeping.
1906                  */
1907                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1908                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1909                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1910         }
1911
1912         /* disable queue 0 to prevent tail bump w/o re-configuration */
1913         if (adapter->vfs_allocated_count)
1914                 wr32(E1000_TXDCTL(0), 0);
1915
1916         /* Program the Transmit Control Register */
1917         tctl = rd32(E1000_TCTL);
1918         tctl &= ~E1000_TCTL_CT;
1919         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1920                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1921
1922         igb_config_collision_dist(hw);
1923
1924         /* Setup Transmit Descriptor Settings for eop descriptor */
1925         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1926
1927         /* Enable transmits */
1928         tctl |= E1000_TCTL_EN;
1929
1930         wr32(E1000_TCTL, tctl);
1931 }
1932
1933 /**
1934  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1935  * @adapter: board private structure
1936  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1937  *
1938  * Returns 0 on success, negative on failure
1939  **/
1940 int igb_setup_rx_resources(struct igb_adapter *adapter,
1941                            struct igb_ring *rx_ring)
1942 {
1943         struct pci_dev *pdev = adapter->pdev;
1944         int size, desc_len;
1945
1946         size = sizeof(struct igb_buffer) * rx_ring->count;
1947         rx_ring->buffer_info = vmalloc(size);
1948         if (!rx_ring->buffer_info)
1949                 goto err;
1950         memset(rx_ring->buffer_info, 0, size);
1951
1952         desc_len = sizeof(union e1000_adv_rx_desc);
1953
1954         /* Round up to nearest 4K */
1955         rx_ring->size = rx_ring->count * desc_len;
1956         rx_ring->size = ALIGN(rx_ring->size, 4096);
1957
1958         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1959                                              &rx_ring->dma);
1960
1961         if (!rx_ring->desc)
1962                 goto err;
1963
1964         rx_ring->next_to_clean = 0;
1965         rx_ring->next_to_use = 0;
1966
1967         rx_ring->adapter = adapter;
1968
1969         return 0;
1970
1971 err:
1972         vfree(rx_ring->buffer_info);
1973         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1974                 "the receive descriptor ring\n");
1975         return -ENOMEM;
1976 }
1977
1978 /**
1979  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1980  *                                (Descriptors) for all queues
1981  * @adapter: board private structure
1982  *
1983  * Return 0 on success, negative on failure
1984  **/
1985 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1986 {
1987         int i, err = 0;
1988
1989         for (i = 0; i < adapter->num_rx_queues; i++) {
1990                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1991                 if (err) {
1992                         dev_err(&adapter->pdev->dev,
1993                                 "Allocation for Rx Queue %u failed\n", i);
1994                         for (i--; i >= 0; i--)
1995                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1996                         break;
1997                 }
1998         }
1999
2000         return err;
2001 }
2002
2003 /**
2004  * igb_setup_rctl - configure the receive control registers
2005  * @adapter: Board private structure
2006  **/
2007 static void igb_setup_rctl(struct igb_adapter *adapter)
2008 {
2009         struct e1000_hw *hw = &adapter->hw;
2010         u32 rctl;
2011         u32 srrctl = 0;
2012         int i, j;
2013
2014         rctl = rd32(E1000_RCTL);
2015
2016         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2017         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2018
2019         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2020                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2021
2022         /*
2023          * enable stripping of CRC. It's unlikely this will break BMC
2024          * redirection as it did with e1000. Newer features require
2025          * that the HW strips the CRC.
2026          */
2027         rctl |= E1000_RCTL_SECRC;
2028
2029         /*
2030          * disable store bad packets and clear size bits.
2031          */
2032         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2033
2034         /* enable LPE when to prevent packets larger than max_frame_size */
2035                 rctl |= E1000_RCTL_LPE;
2036
2037         /* Setup buffer sizes */
2038         switch (adapter->rx_buffer_len) {
2039         case IGB_RXBUFFER_256:
2040                 rctl |= E1000_RCTL_SZ_256;
2041                 break;
2042         case IGB_RXBUFFER_512:
2043                 rctl |= E1000_RCTL_SZ_512;
2044                 break;
2045         default:
2046                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2047                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2048                 break;
2049         }
2050
2051         /* 82575 and greater support packet-split where the protocol
2052          * header is placed in skb->data and the packet data is
2053          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2054          * In the case of a non-split, skb->data is linearly filled,
2055          * followed by the page buffers.  Therefore, skb->data is
2056          * sized to hold the largest protocol header.
2057          */
2058         /* allocations using alloc_page take too long for regular MTU
2059          * so only enable packet split for jumbo frames */
2060         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2061                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2062                 srrctl |= adapter->rx_ps_hdr_size <<
2063                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2064                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2065         } else {
2066                 adapter->rx_ps_hdr_size = 0;
2067                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2068         }
2069
2070         /* Attention!!!  For SR-IOV PF driver operations you must enable
2071          * queue drop for all VF and PF queues to prevent head of line blocking
2072          * if an un-trusted VF does not provide descriptors to hardware.
2073          */
2074         if (adapter->vfs_allocated_count) {
2075                 u32 vmolr;
2076
2077                 j = adapter->rx_ring[0].reg_idx;
2078
2079                 /* set all queue drop enable bits */
2080                 wr32(E1000_QDE, ALL_QUEUES);
2081                 srrctl |= E1000_SRRCTL_DROP_EN;
2082
2083                 /* disable queue 0 to prevent tail write w/o re-config */
2084                 wr32(E1000_RXDCTL(0), 0);
2085
2086                 vmolr = rd32(E1000_VMOLR(j));
2087                 if (rctl & E1000_RCTL_LPE)
2088                         vmolr |= E1000_VMOLR_LPE;
2089                 if (adapter->num_rx_queues > 0)
2090                         vmolr |= E1000_VMOLR_RSSE;
2091                 wr32(E1000_VMOLR(j), vmolr);
2092         }
2093
2094         for (i = 0; i < adapter->num_rx_queues; i++) {
2095                 j = adapter->rx_ring[i].reg_idx;
2096                 wr32(E1000_SRRCTL(j), srrctl);
2097         }
2098
2099         wr32(E1000_RCTL, rctl);
2100 }
2101
2102 /**
2103  * igb_rlpml_set - set maximum receive packet size
2104  * @adapter: board private structure
2105  *
2106  * Configure maximum receivable packet size.
2107  **/
2108 static void igb_rlpml_set(struct igb_adapter *adapter)
2109 {
2110         u32 max_frame_size = adapter->max_frame_size;
2111         struct e1000_hw *hw = &adapter->hw;
2112         u16 pf_id = adapter->vfs_allocated_count;
2113
2114         if (adapter->vlgrp)
2115                 max_frame_size += VLAN_TAG_SIZE;
2116
2117         /* if vfs are enabled we set RLPML to the largest possible request
2118          * size and set the VMOLR RLPML to the size we need */
2119         if (pf_id) {
2120                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2121                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2122         }
2123
2124         wr32(E1000_RLPML, max_frame_size);
2125 }
2126
2127 /**
2128  * igb_configure_vt_default_pool - Configure VT default pool
2129  * @adapter: board private structure
2130  *
2131  * Configure the default pool
2132  **/
2133 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2134 {
2135         struct e1000_hw *hw = &adapter->hw;
2136         u16 pf_id = adapter->vfs_allocated_count;
2137         u32 vtctl;
2138
2139         /* not in sr-iov mode - do nothing */
2140         if (!pf_id)
2141                 return;
2142
2143         vtctl = rd32(E1000_VT_CTL);
2144         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2145                    E1000_VT_CTL_DISABLE_DEF_POOL);
2146         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2147         wr32(E1000_VT_CTL, vtctl);
2148 }
2149
2150 /**
2151  * igb_configure_rx - Configure receive Unit after Reset
2152  * @adapter: board private structure
2153  *
2154  * Configure the Rx unit of the MAC after a reset.
2155  **/
2156 static void igb_configure_rx(struct igb_adapter *adapter)
2157 {
2158         u64 rdba;
2159         struct e1000_hw *hw = &adapter->hw;
2160         u32 rctl, rxcsum;
2161         u32 rxdctl;
2162         int i;
2163
2164         /* disable receives while setting up the descriptors */
2165         rctl = rd32(E1000_RCTL);
2166         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2167         wrfl();
2168         mdelay(10);
2169
2170         if (adapter->itr_setting > 3)
2171                 wr32(E1000_ITR, adapter->itr);
2172
2173         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2174          * the Base and Length of the Rx Descriptor Ring */
2175         for (i = 0; i < adapter->num_rx_queues; i++) {
2176                 struct igb_ring *ring = &adapter->rx_ring[i];
2177                 int j = ring->reg_idx;
2178                 rdba = ring->dma;
2179                 wr32(E1000_RDBAL(j),
2180                      rdba & 0x00000000ffffffffULL);
2181                 wr32(E1000_RDBAH(j), rdba >> 32);
2182                 wr32(E1000_RDLEN(j),
2183                      ring->count * sizeof(union e1000_adv_rx_desc));
2184
2185                 ring->head = E1000_RDH(j);
2186                 ring->tail = E1000_RDT(j);
2187                 writel(0, hw->hw_addr + ring->tail);
2188                 writel(0, hw->hw_addr + ring->head);
2189
2190                 rxdctl = rd32(E1000_RXDCTL(j));
2191                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2192                 rxdctl &= 0xFFF00000;
2193                 rxdctl |= IGB_RX_PTHRESH;
2194                 rxdctl |= IGB_RX_HTHRESH << 8;
2195                 rxdctl |= IGB_RX_WTHRESH << 16;
2196                 wr32(E1000_RXDCTL(j), rxdctl);
2197         }
2198
2199         if (adapter->num_rx_queues > 1) {
2200                 u32 random[10];
2201                 u32 mrqc;
2202                 u32 j, shift;
2203                 union e1000_reta {
2204                         u32 dword;
2205                         u8  bytes[4];
2206                 } reta;
2207
2208                 get_random_bytes(&random[0], 40);
2209
2210                 if (hw->mac.type >= e1000_82576)
2211                         shift = 0;
2212                 else
2213                         shift = 6;
2214                 for (j = 0; j < (32 * 4); j++) {
2215                         reta.bytes[j & 3] =
2216                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2217                         if ((j & 3) == 3)
2218                                 writel(reta.dword,
2219                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2220                 }
2221                 if (adapter->vfs_allocated_count)
2222                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2223                 else
2224                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2225
2226                 /* Fill out hash function seeds */
2227                 for (j = 0; j < 10; j++)
2228                         array_wr32(E1000_RSSRK(0), j, random[j]);
2229
2230                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2231                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2232                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2233                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2234                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2235                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2236                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2237                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2238
2239
2240                 wr32(E1000_MRQC, mrqc);
2241
2242                 /* Multiqueue and raw packet checksumming are mutually
2243                  * exclusive.  Note that this not the same as TCP/IP
2244                  * checksumming, which works fine. */
2245                 rxcsum = rd32(E1000_RXCSUM);
2246                 rxcsum |= E1000_RXCSUM_PCSD;
2247                 wr32(E1000_RXCSUM, rxcsum);
2248         } else {
2249                 /* Enable multi-queue for sr-iov */
2250                 if (adapter->vfs_allocated_count)
2251                         wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2252                 /* Enable Receive Checksum Offload for TCP and UDP */
2253                 rxcsum = rd32(E1000_RXCSUM);
2254                 if (adapter->rx_csum)
2255                         rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2256                 else
2257                         rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2258
2259                 wr32(E1000_RXCSUM, rxcsum);
2260         }
2261
2262         /* Set the default pool for the PF's first queue */
2263         igb_configure_vt_default_pool(adapter);
2264
2265         igb_rlpml_set(adapter);
2266
2267         /* Enable Receives */
2268         wr32(E1000_RCTL, rctl);
2269 }
2270
2271 /**
2272  * igb_free_tx_resources - Free Tx Resources per Queue
2273  * @tx_ring: Tx descriptor ring for a specific queue
2274  *
2275  * Free all transmit software resources
2276  **/
2277 void igb_free_tx_resources(struct igb_ring *tx_ring)
2278 {
2279         struct pci_dev *pdev = tx_ring->adapter->pdev;
2280
2281         igb_clean_tx_ring(tx_ring);
2282
2283         vfree(tx_ring->buffer_info);
2284         tx_ring->buffer_info = NULL;
2285
2286         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2287
2288         tx_ring->desc = NULL;
2289 }
2290
2291 /**
2292  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2293  * @adapter: board private structure
2294  *
2295  * Free all transmit software resources
2296  **/
2297 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2298 {
2299         int i;
2300
2301         for (i = 0; i < adapter->num_tx_queues; i++)
2302                 igb_free_tx_resources(&adapter->tx_ring[i]);
2303 }
2304
2305 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2306                                            struct igb_buffer *buffer_info)
2307 {
2308         buffer_info->dma = 0;
2309         if (buffer_info->skb) {
2310                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2311                               DMA_TO_DEVICE);
2312                 dev_kfree_skb_any(buffer_info->skb);
2313                 buffer_info->skb = NULL;
2314         }
2315         buffer_info->time_stamp = 0;
2316         /* buffer_info must be completely set up in the transmit path */
2317 }
2318
2319 /**
2320  * igb_clean_tx_ring - Free Tx Buffers
2321  * @tx_ring: ring to be cleaned
2322  **/
2323 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2324 {
2325         struct igb_adapter *adapter = tx_ring->adapter;
2326         struct igb_buffer *buffer_info;
2327         unsigned long size;
2328         unsigned int i;
2329
2330         if (!tx_ring->buffer_info)
2331                 return;
2332         /* Free all the Tx ring sk_buffs */
2333
2334         for (i = 0; i < tx_ring->count; i++) {
2335                 buffer_info = &tx_ring->buffer_info[i];
2336                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2337         }
2338
2339         size = sizeof(struct igb_buffer) * tx_ring->count;
2340         memset(tx_ring->buffer_info, 0, size);
2341
2342         /* Zero out the descriptor ring */
2343
2344         memset(tx_ring->desc, 0, tx_ring->size);
2345
2346         tx_ring->next_to_use = 0;
2347         tx_ring->next_to_clean = 0;
2348
2349         writel(0, adapter->hw.hw_addr + tx_ring->head);
2350         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2351 }
2352
2353 /**
2354  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2355  * @adapter: board private structure
2356  **/
2357 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2358 {
2359         int i;
2360
2361         for (i = 0; i < adapter->num_tx_queues; i++)
2362                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2363 }
2364
2365 /**
2366  * igb_free_rx_resources - Free Rx Resources
2367  * @rx_ring: ring to clean the resources from
2368  *
2369  * Free all receive software resources
2370  **/
2371 void igb_free_rx_resources(struct igb_ring *rx_ring)
2372 {
2373         struct pci_dev *pdev = rx_ring->adapter->pdev;
2374
2375         igb_clean_rx_ring(rx_ring);
2376
2377         vfree(rx_ring->buffer_info);
2378         rx_ring->buffer_info = NULL;
2379
2380         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2381
2382         rx_ring->desc = NULL;
2383 }
2384
2385 /**
2386  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2387  * @adapter: board private structure
2388  *
2389  * Free all receive software resources
2390  **/
2391 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2392 {
2393         int i;
2394
2395         for (i = 0; i < adapter->num_rx_queues; i++)
2396                 igb_free_rx_resources(&adapter->rx_ring[i]);
2397 }
2398
2399 /**
2400  * igb_clean_rx_ring - Free Rx Buffers per Queue
2401  * @rx_ring: ring to free buffers from
2402  **/
2403 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2404 {
2405         struct igb_adapter *adapter = rx_ring->adapter;
2406         struct igb_buffer *buffer_info;
2407         struct pci_dev *pdev = adapter->pdev;
2408         unsigned long size;
2409         unsigned int i;
2410
2411         if (!rx_ring->buffer_info)
2412                 return;
2413         /* Free all the Rx ring sk_buffs */
2414         for (i = 0; i < rx_ring->count; i++) {
2415                 buffer_info = &rx_ring->buffer_info[i];
2416                 if (buffer_info->dma) {
2417                         if (adapter->rx_ps_hdr_size)
2418                                 pci_unmap_single(pdev, buffer_info->dma,
2419                                                  adapter->rx_ps_hdr_size,
2420                                                  PCI_DMA_FROMDEVICE);
2421                         else
2422                                 pci_unmap_single(pdev, buffer_info->dma,
2423                                                  adapter->rx_buffer_len,
2424                                                  PCI_DMA_FROMDEVICE);
2425                         buffer_info->dma = 0;
2426                 }
2427
2428                 if (buffer_info->skb) {
2429                         dev_kfree_skb(buffer_info->skb);
2430                         buffer_info->skb = NULL;
2431                 }
2432                 if (buffer_info->page) {
2433                         if (buffer_info->page_dma)
2434                                 pci_unmap_page(pdev, buffer_info->page_dma,
2435                                                PAGE_SIZE / 2,
2436                                                PCI_DMA_FROMDEVICE);
2437                         put_page(buffer_info->page);
2438                         buffer_info->page = NULL;
2439                         buffer_info->page_dma = 0;
2440                         buffer_info->page_offset = 0;
2441                 }
2442         }
2443
2444         size = sizeof(struct igb_buffer) * rx_ring->count;
2445         memset(rx_ring->buffer_info, 0, size);
2446
2447         /* Zero out the descriptor ring */
2448         memset(rx_ring->desc, 0, rx_ring->size);
2449
2450         rx_ring->next_to_clean = 0;
2451         rx_ring->next_to_use = 0;
2452
2453         writel(0, adapter->hw.hw_addr + rx_ring->head);
2454         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2455 }
2456
2457 /**
2458  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2459  * @adapter: board private structure
2460  **/
2461 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2462 {
2463         int i;
2464
2465         for (i = 0; i < adapter->num_rx_queues; i++)
2466                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2467 }
2468
2469 /**
2470  * igb_set_mac - Change the Ethernet Address of the NIC
2471  * @netdev: network interface device structure
2472  * @p: pointer to an address structure
2473  *
2474  * Returns 0 on success, negative on failure
2475  **/
2476 static int igb_set_mac(struct net_device *netdev, void *p)
2477 {
2478         struct igb_adapter *adapter = netdev_priv(netdev);
2479         struct e1000_hw *hw = &adapter->hw;
2480         struct sockaddr *addr = p;
2481
2482         if (!is_valid_ether_addr(addr->sa_data))
2483                 return -EADDRNOTAVAIL;
2484
2485         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2486         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2487
2488         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2489
2490         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2491
2492         return 0;
2493 }
2494
2495 /**
2496  * igb_set_multi - Multicast and Promiscuous mode set
2497  * @netdev: network interface device structure
2498  *
2499  * The set_multi entry point is called whenever the multicast address
2500  * list or the network interface flags are updated.  This routine is
2501  * responsible for configuring the hardware for proper multicast,
2502  * promiscuous mode, and all-multi behavior.
2503  **/
2504 static void igb_set_multi(struct net_device *netdev)
2505 {
2506         struct igb_adapter *adapter = netdev_priv(netdev);
2507         struct e1000_hw *hw = &adapter->hw;
2508         struct e1000_mac_info *mac = &hw->mac;
2509         struct dev_mc_list *mc_ptr;
2510         u8  *mta_list = NULL;
2511         u32 rctl;
2512         int i;
2513
2514         /* Check for Promiscuous and All Multicast modes */
2515
2516         rctl = rd32(E1000_RCTL);
2517
2518         if (netdev->flags & IFF_PROMISC) {
2519                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2520                 rctl &= ~E1000_RCTL_VFE;
2521         } else {
2522                 if (netdev->flags & IFF_ALLMULTI) {
2523                         rctl |= E1000_RCTL_MPE;
2524                         rctl &= ~E1000_RCTL_UPE;
2525                 } else
2526                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2527                 rctl |= E1000_RCTL_VFE;
2528         }
2529         wr32(E1000_RCTL, rctl);
2530
2531         if (netdev->mc_count) {
2532                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2533                 if (!mta_list) {
2534                         dev_err(&adapter->pdev->dev,
2535                                 "failed to allocate multicast filter list\n");
2536                         return;
2537                 }
2538         }
2539
2540         /* The shared function expects a packed array of only addresses. */
2541         mc_ptr = netdev->mc_list;
2542
2543         for (i = 0; i < netdev->mc_count; i++) {
2544                 if (!mc_ptr)
2545                         break;
2546                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2547                 mc_ptr = mc_ptr->next;
2548         }
2549         igb_update_mc_addr_list(hw, mta_list, i,
2550                                 adapter->vfs_allocated_count + 1,
2551                                 mac->rar_entry_count);
2552
2553         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2554         igb_restore_vf_multicasts(adapter);
2555
2556         kfree(mta_list);
2557 }
2558
2559 /* Need to wait a few seconds after link up to get diagnostic information from
2560  * the phy */
2561 static void igb_update_phy_info(unsigned long data)
2562 {
2563         struct igb_adapter *adapter = (struct igb_adapter *) data;
2564         igb_get_phy_info(&adapter->hw);
2565 }
2566
2567 /**
2568  * igb_has_link - check shared code for link and determine up/down
2569  * @adapter: pointer to driver private info
2570  **/
2571 static bool igb_has_link(struct igb_adapter *adapter)
2572 {
2573         struct e1000_hw *hw = &adapter->hw;
2574         bool link_active = false;
2575         s32 ret_val = 0;
2576
2577         /* get_link_status is set on LSC (link status) interrupt or
2578          * rx sequence error interrupt.  get_link_status will stay
2579          * false until the e1000_check_for_link establishes link
2580          * for copper adapters ONLY
2581          */
2582         switch (hw->phy.media_type) {
2583         case e1000_media_type_copper:
2584                 if (hw->mac.get_link_status) {
2585                         ret_val = hw->mac.ops.check_for_link(hw);
2586                         link_active = !hw->mac.get_link_status;
2587                 } else {
2588                         link_active = true;
2589                 }
2590                 break;
2591         case e1000_media_type_fiber:
2592                 ret_val = hw->mac.ops.check_for_link(hw);
2593                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2594                 break;
2595         case e1000_media_type_internal_serdes:
2596                 ret_val = hw->mac.ops.check_for_link(hw);
2597                 link_active = hw->mac.serdes_has_link;
2598                 break;
2599         default:
2600         case e1000_media_type_unknown:
2601                 break;
2602         }
2603
2604         return link_active;
2605 }
2606
2607 /**
2608  * igb_watchdog - Timer Call-back
2609  * @data: pointer to adapter cast into an unsigned long
2610  **/
2611 static void igb_watchdog(unsigned long data)
2612 {
2613         struct igb_adapter *adapter = (struct igb_adapter *)data;
2614         /* Do the rest outside of interrupt context */
2615         schedule_work(&adapter->watchdog_task);
2616 }
2617
2618 static void igb_watchdog_task(struct work_struct *work)
2619 {
2620         struct igb_adapter *adapter = container_of(work,
2621                                         struct igb_adapter, watchdog_task);
2622         struct e1000_hw *hw = &adapter->hw;
2623         struct net_device *netdev = adapter->netdev;
2624         struct igb_ring *tx_ring = adapter->tx_ring;
2625         u32 link;
2626         u32 eics = 0;
2627         int i;
2628
2629         link = igb_has_link(adapter);
2630         if ((netif_carrier_ok(netdev)) && link)
2631                 goto link_up;
2632
2633         if (link) {
2634                 if (!netif_carrier_ok(netdev)) {
2635                         u32 ctrl;
2636                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2637                                                    &adapter->link_speed,
2638                                                    &adapter->link_duplex);
2639
2640                         ctrl = rd32(E1000_CTRL);
2641                         /* Links status message must follow this format */
2642                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2643                                  "Flow Control: %s\n",
2644                                  netdev->name,
2645                                  adapter->link_speed,
2646                                  adapter->link_duplex == FULL_DUPLEX ?
2647                                  "Full Duplex" : "Half Duplex",
2648                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2649                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2650                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2651                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2652
2653                         /* tweak tx_queue_len according to speed/duplex and
2654                          * adjust the timeout factor */
2655                         netdev->tx_queue_len = adapter->tx_queue_len;
2656                         adapter->tx_timeout_factor = 1;
2657                         switch (adapter->link_speed) {
2658                         case SPEED_10:
2659                                 netdev->tx_queue_len = 10;
2660                                 adapter->tx_timeout_factor = 14;
2661                                 break;
2662                         case SPEED_100:
2663                                 netdev->tx_queue_len = 100;
2664                                 /* maybe add some timeout factor ? */
2665                                 break;
2666                         }
2667
2668                         netif_carrier_on(netdev);
2669
2670                         igb_ping_all_vfs(adapter);
2671
2672                         /* link state has changed, schedule phy info update */
2673                         if (!test_bit(__IGB_DOWN, &adapter->state))
2674                                 mod_timer(&adapter->phy_info_timer,
2675                                           round_jiffies(jiffies + 2 * HZ));
2676                 }
2677         } else {
2678                 if (netif_carrier_ok(netdev)) {
2679                         adapter->link_speed = 0;
2680                         adapter->link_duplex = 0;
2681                         /* Links status message must follow this format */
2682                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2683                                netdev->name);
2684                         netif_carrier_off(netdev);
2685
2686                         igb_ping_all_vfs(adapter);
2687
2688                         /* link state has changed, schedule phy info update */
2689                         if (!test_bit(__IGB_DOWN, &adapter->state))
2690                                 mod_timer(&adapter->phy_info_timer,
2691                                           round_jiffies(jiffies + 2 * HZ));
2692                 }
2693         }
2694
2695 link_up:
2696         igb_update_stats(adapter);
2697
2698         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2699         adapter->tpt_old = adapter->stats.tpt;
2700         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2701         adapter->colc_old = adapter->stats.colc;
2702
2703         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2704         adapter->gorc_old = adapter->stats.gorc;
2705         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2706         adapter->gotc_old = adapter->stats.gotc;
2707
2708         igb_update_adaptive(&adapter->hw);
2709
2710         if (!netif_carrier_ok(netdev)) {
2711                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2712                         /* We've lost link, so the controller stops DMA,
2713                          * but we've got queued Tx work that's never going
2714                          * to get done, so reset controller to flush Tx.
2715                          * (Do the reset outside of interrupt context). */
2716                         adapter->tx_timeout_count++;
2717                         schedule_work(&adapter->reset_task);
2718                 }
2719         }
2720
2721         /* Cause software interrupt to ensure rx ring is cleaned */
2722         if (adapter->msix_entries) {
2723                 for (i = 0; i < adapter->num_rx_queues; i++)
2724                         eics |= adapter->rx_ring[i].eims_value;
2725                 wr32(E1000_EICS, eics);
2726         } else {
2727                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2728         }
2729
2730         /* Force detection of hung controller every watchdog period */
2731         tx_ring->detect_tx_hung = true;
2732
2733         /* Reset the timer */
2734         if (!test_bit(__IGB_DOWN, &adapter->state))
2735                 mod_timer(&adapter->watchdog_timer,
2736                           round_jiffies(jiffies + 2 * HZ));
2737 }
2738
2739 enum latency_range {
2740         lowest_latency = 0,
2741         low_latency = 1,
2742         bulk_latency = 2,
2743         latency_invalid = 255
2744 };
2745
2746
2747 /**
2748  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2749  *
2750  *      Stores a new ITR value based on strictly on packet size.  This
2751  *      algorithm is less sophisticated than that used in igb_update_itr,
2752  *      due to the difficulty of synchronizing statistics across multiple
2753  *      receive rings.  The divisors and thresholds used by this fuction
2754  *      were determined based on theoretical maximum wire speed and testing
2755  *      data, in order to minimize response time while increasing bulk
2756  *      throughput.
2757  *      This functionality is controlled by the InterruptThrottleRate module
2758  *      parameter (see igb_param.c)
2759  *      NOTE:  This function is called only when operating in a multiqueue
2760  *             receive environment.
2761  * @rx_ring: pointer to ring
2762  **/
2763 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2764 {
2765         int new_val = rx_ring->itr_val;
2766         int avg_wire_size = 0;
2767         struct igb_adapter *adapter = rx_ring->adapter;
2768
2769         if (!rx_ring->total_packets)
2770                 goto clear_counts; /* no packets, so don't do anything */
2771
2772         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2773          * ints/sec - ITR timer value of 120 ticks.
2774          */
2775         if (adapter->link_speed != SPEED_1000) {
2776                 new_val = 120;
2777                 goto set_itr_val;
2778         }
2779         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2780
2781         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2782         avg_wire_size += 24;
2783
2784         /* Don't starve jumbo frames */
2785         avg_wire_size = min(avg_wire_size, 3000);
2786
2787         /* Give a little boost to mid-size frames */
2788         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2789                 new_val = avg_wire_size / 3;
2790         else
2791                 new_val = avg_wire_size / 2;
2792
2793 set_itr_val:
2794         if (new_val != rx_ring->itr_val) {
2795                 rx_ring->itr_val = new_val;
2796                 rx_ring->set_itr = 1;
2797         }
2798 clear_counts:
2799         rx_ring->total_bytes = 0;
2800         rx_ring->total_packets = 0;
2801 }
2802
2803 /**
2804  * igb_update_itr - update the dynamic ITR value based on statistics
2805  *      Stores a new ITR value based on packets and byte
2806  *      counts during the last interrupt.  The advantage of per interrupt
2807  *      computation is faster updates and more accurate ITR for the current
2808  *      traffic pattern.  Constants in this function were computed
2809  *      based on theoretical maximum wire speed and thresholds were set based
2810  *      on testing data as well as attempting to minimize response time
2811  *      while increasing bulk throughput.
2812  *      this functionality is controlled by the InterruptThrottleRate module
2813  *      parameter (see igb_param.c)
2814  *      NOTE:  These calculations are only valid when operating in a single-
2815  *             queue environment.
2816  * @adapter: pointer to adapter
2817  * @itr_setting: current adapter->itr
2818  * @packets: the number of packets during this measurement interval
2819  * @bytes: the number of bytes during this measurement interval
2820  **/
2821 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2822                                    int packets, int bytes)
2823 {
2824         unsigned int retval = itr_setting;
2825
2826         if (packets == 0)
2827                 goto update_itr_done;
2828
2829         switch (itr_setting) {
2830         case lowest_latency:
2831                 /* handle TSO and jumbo frames */
2832                 if (bytes/packets > 8000)
2833                         retval = bulk_latency;
2834                 else if ((packets < 5) && (bytes > 512))
2835                         retval = low_latency;
2836                 break;
2837         case low_latency:  /* 50 usec aka 20000 ints/s */
2838                 if (bytes > 10000) {
2839                         /* this if handles the TSO accounting */
2840                         if (bytes/packets > 8000) {
2841                                 retval = bulk_latency;
2842                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2843                                 retval = bulk_latency;
2844                         } else if ((packets > 35)) {
2845                                 retval = lowest_latency;
2846                         }
2847                 } else if (bytes/packets > 2000) {
2848                         retval = bulk_latency;
2849                 } else if (packets <= 2 && bytes < 512) {
2850                         retval = lowest_latency;
2851                 }
2852                 break;
2853         case bulk_latency: /* 250 usec aka 4000 ints/s */
2854                 if (bytes > 25000) {
2855                         if (packets > 35)
2856                                 retval = low_latency;
2857                 } else if (bytes < 1500) {
2858                         retval = low_latency;
2859                 }
2860                 break;
2861         }
2862
2863 update_itr_done:
2864         return retval;
2865 }
2866
2867 static void igb_set_itr(struct igb_adapter *adapter)
2868 {
2869         u16 current_itr;
2870         u32 new_itr = adapter->itr;
2871
2872         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2873         if (adapter->link_speed != SPEED_1000) {
2874                 current_itr = 0;
2875                 new_itr = 4000;
2876                 goto set_itr_now;
2877         }
2878
2879         adapter->rx_itr = igb_update_itr(adapter,
2880                                     adapter->rx_itr,
2881                                     adapter->rx_ring->total_packets,
2882                                     adapter->rx_ring->total_bytes);
2883
2884         if (adapter->rx_ring->buddy) {
2885                 adapter->tx_itr = igb_update_itr(adapter,
2886                                             adapter->tx_itr,
2887                                             adapter->tx_ring->total_packets,
2888                                             adapter->tx_ring->total_bytes);
2889                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2890         } else {
2891                 current_itr = adapter->rx_itr;
2892         }
2893
2894         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2895         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2896                 current_itr = low_latency;
2897
2898         switch (current_itr) {
2899         /* counts and packets in update_itr are dependent on these numbers */
2900         case lowest_latency:
2901                 new_itr = 70000;
2902                 break;
2903         case low_latency:
2904                 new_itr = 20000; /* aka hwitr = ~200 */
2905                 break;
2906         case bulk_latency:
2907                 new_itr = 4000;
2908                 break;
2909         default:
2910                 break;
2911         }
2912
2913 set_itr_now:
2914         adapter->rx_ring->total_bytes = 0;
2915         adapter->rx_ring->total_packets = 0;
2916         if (adapter->rx_ring->buddy) {
2917                 adapter->rx_ring->buddy->total_bytes = 0;
2918                 adapter->rx_ring->buddy->total_packets = 0;
2919         }
2920
2921         if (new_itr != adapter->itr) {
2922                 /* this attempts to bias the interrupt rate towards Bulk
2923                  * by adding intermediate steps when interrupt rate is
2924                  * increasing */
2925                 new_itr = new_itr > adapter->itr ?
2926                              min(adapter->itr + (new_itr >> 2), new_itr) :
2927                              new_itr;
2928                 /* Don't write the value here; it resets the adapter's
2929                  * internal timer, and causes us to delay far longer than
2930                  * we should between interrupts.  Instead, we write the ITR
2931                  * value at the beginning of the next interrupt so the timing
2932                  * ends up being correct.
2933                  */
2934                 adapter->itr = new_itr;
2935                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2936                 adapter->rx_ring->set_itr = 1;
2937         }
2938
2939         return;
2940 }
2941
2942
2943 #define IGB_TX_FLAGS_CSUM               0x00000001
2944 #define IGB_TX_FLAGS_VLAN               0x00000002
2945 #define IGB_TX_FLAGS_TSO                0x00000004
2946 #define IGB_TX_FLAGS_IPV4               0x00000008
2947 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2948 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2949 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2950
2951 static inline int igb_tso_adv(struct igb_adapter *adapter,
2952                               struct igb_ring *tx_ring,
2953                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2954 {
2955         struct e1000_adv_tx_context_desc *context_desc;
2956         unsigned int i;
2957         int err;
2958         struct igb_buffer *buffer_info;
2959         u32 info = 0, tu_cmd = 0;
2960         u32 mss_l4len_idx, l4len;
2961         *hdr_len = 0;
2962
2963         if (skb_header_cloned(skb)) {
2964                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2965                 if (err)
2966                         return err;
2967         }
2968
2969         l4len = tcp_hdrlen(skb);
2970         *hdr_len += l4len;
2971
2972         if (skb->protocol == htons(ETH_P_IP)) {
2973                 struct iphdr *iph = ip_hdr(skb);
2974                 iph->tot_len = 0;
2975                 iph->check = 0;
2976                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2977                                                          iph->daddr, 0,
2978                                                          IPPROTO_TCP,
2979                                                          0);
2980         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2981                 ipv6_hdr(skb)->payload_len = 0;
2982                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2983                                                        &ipv6_hdr(skb)->daddr,
2984                                                        0, IPPROTO_TCP, 0);
2985         }
2986
2987         i = tx_ring->next_to_use;
2988
2989         buffer_info = &tx_ring->buffer_info[i];
2990         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2991         /* VLAN MACLEN IPLEN */
2992         if (tx_flags & IGB_TX_FLAGS_VLAN)
2993                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2994         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2995         *hdr_len += skb_network_offset(skb);
2996         info |= skb_network_header_len(skb);
2997         *hdr_len += skb_network_header_len(skb);
2998         context_desc->vlan_macip_lens = cpu_to_le32(info);
2999
3000         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3001         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3002
3003         if (skb->protocol == htons(ETH_P_IP))
3004                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3005         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3006
3007         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3008
3009         /* MSS L4LEN IDX */
3010         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3011         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3012
3013         /* For 82575, context index must be unique per ring. */
3014         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3015                 mss_l4len_idx |= tx_ring->queue_index << 4;
3016
3017         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3018         context_desc->seqnum_seed = 0;
3019
3020         buffer_info->time_stamp = jiffies;
3021         buffer_info->next_to_watch = i;
3022         buffer_info->dma = 0;
3023         i++;
3024         if (i == tx_ring->count)
3025                 i = 0;
3026
3027         tx_ring->next_to_use = i;
3028
3029         return true;
3030 }
3031
3032 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3033                                         struct igb_ring *tx_ring,
3034                                         struct sk_buff *skb, u32 tx_flags)
3035 {
3036         struct e1000_adv_tx_context_desc *context_desc;
3037         unsigned int i;
3038         struct igb_buffer *buffer_info;
3039         u32 info = 0, tu_cmd = 0;
3040
3041         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3042             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3043                 i = tx_ring->next_to_use;
3044                 buffer_info = &tx_ring->buffer_info[i];
3045                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3046
3047                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3048                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3049                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3050                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3051                         info |= skb_network_header_len(skb);
3052
3053                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3054
3055                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3056
3057                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3058                         __be16 protocol;
3059
3060                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3061                                 const struct vlan_ethhdr *vhdr =
3062                                           (const struct vlan_ethhdr*)skb->data;
3063
3064                                 protocol = vhdr->h_vlan_encapsulated_proto;
3065                         } else {
3066                                 protocol = skb->protocol;
3067                         }
3068
3069                         switch (protocol) {
3070                         case cpu_to_be16(ETH_P_IP):
3071                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3072                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3073                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3074                                 break;
3075                         case cpu_to_be16(ETH_P_IPV6):
3076                                 /* XXX what about other V6 headers?? */
3077                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3078                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3079                                 break;
3080                         default:
3081                                 if (unlikely(net_ratelimit()))
3082                                         dev_warn(&adapter->pdev->dev,
3083                                             "partial checksum but proto=%x!\n",
3084                                             skb->protocol);
3085                                 break;
3086                         }
3087                 }
3088
3089                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3090                 context_desc->seqnum_seed = 0;
3091                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3092                         context_desc->mss_l4len_idx =
3093                                 cpu_to_le32(tx_ring->queue_index << 4);
3094                 else
3095                         context_desc->mss_l4len_idx = 0;
3096
3097                 buffer_info->time_stamp = jiffies;
3098                 buffer_info->next_to_watch = i;
3099                 buffer_info->dma = 0;
3100
3101                 i++;
3102                 if (i == tx_ring->count)
3103                         i = 0;
3104                 tx_ring->next_to_use = i;
3105
3106                 return true;
3107         }
3108         return false;
3109 }
3110
3111 #define IGB_MAX_TXD_PWR 16
3112 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3113
3114 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3115                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3116                                  unsigned int first)
3117 {
3118         struct igb_buffer *buffer_info;
3119         unsigned int len = skb_headlen(skb);
3120         unsigned int count = 0, i;
3121         unsigned int f;
3122         dma_addr_t *map;
3123
3124         i = tx_ring->next_to_use;
3125
3126         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3127                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3128                 return 0;
3129         }
3130
3131         map = skb_shinfo(skb)->dma_maps;
3132
3133         buffer_info = &tx_ring->buffer_info[i];
3134         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3135         buffer_info->length = len;
3136         /* set time_stamp *before* dma to help avoid a possible race */
3137         buffer_info->time_stamp = jiffies;
3138         buffer_info->next_to_watch = i;
3139         buffer_info->dma = map[count];
3140         count++;
3141
3142         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3143                 struct skb_frag_struct *frag;
3144
3145                 i++;
3146                 if (i == tx_ring->count)
3147                         i = 0;
3148
3149                 frag = &skb_shinfo(skb)->frags[f];
3150                 len = frag->size;
3151
3152                 buffer_info = &tx_ring->buffer_info[i];
3153                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3154                 buffer_info->length = len;
3155                 buffer_info->time_stamp = jiffies;
3156                 buffer_info->next_to_watch = i;
3157                 buffer_info->dma = map[count];
3158                 count++;
3159         }
3160
3161         tx_ring->buffer_info[i].skb = skb;
3162         tx_ring->buffer_info[first].next_to_watch = i;
3163
3164         return count;
3165 }
3166
3167 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3168                                     struct igb_ring *tx_ring,
3169                                     int tx_flags, int count, u32 paylen,
3170                                     u8 hdr_len)
3171 {
3172         union e1000_adv_tx_desc *tx_desc = NULL;
3173         struct igb_buffer *buffer_info;
3174         u32 olinfo_status = 0, cmd_type_len;
3175         unsigned int i;
3176
3177         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3178                         E1000_ADVTXD_DCMD_DEXT);
3179
3180         if (tx_flags & IGB_TX_FLAGS_VLAN)
3181                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3182
3183         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3184                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3185
3186         if (tx_flags & IGB_TX_FLAGS_TSO) {
3187                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3188
3189                 /* insert tcp checksum */
3190                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3191
3192                 /* insert ip checksum */
3193                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3194                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3195
3196         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3197                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3198         }
3199
3200         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3201             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3202                          IGB_TX_FLAGS_VLAN)))
3203                 olinfo_status |= tx_ring->queue_index << 4;
3204
3205         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3206
3207         i = tx_ring->next_to_use;
3208         while (count--) {
3209                 buffer_info = &tx_ring->buffer_info[i];
3210                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3211                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3212                 tx_desc->read.cmd_type_len =
3213                         cpu_to_le32(cmd_type_len | buffer_info->length);
3214                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3215                 i++;
3216                 if (i == tx_ring->count)
3217                         i = 0;
3218         }
3219
3220         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3221         /* Force memory writes to complete before letting h/w
3222          * know there are new descriptors to fetch.  (Only
3223          * applicable for weak-ordered memory model archs,
3224          * such as IA-64). */
3225         wmb();
3226
3227         tx_ring->next_to_use = i;
3228         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3229         /* we need this if more than one processor can write to our tail
3230          * at a time, it syncronizes IO on IA64/Altix systems */
3231         mmiowb();
3232 }
3233
3234 static int __igb_maybe_stop_tx(struct net_device *netdev,
3235                                struct igb_ring *tx_ring, int size)
3236 {
3237         struct igb_adapter *adapter = netdev_priv(netdev);
3238
3239         netif_stop_subqueue(netdev, tx_ring->queue_index);
3240
3241         /* Herbert's original patch had:
3242          *  smp_mb__after_netif_stop_queue();
3243          * but since that doesn't exist yet, just open code it. */
3244         smp_mb();
3245
3246         /* We need to check again in a case another CPU has just
3247          * made room available. */
3248         if (igb_desc_unused(tx_ring) < size)
3249                 return -EBUSY;
3250
3251         /* A reprieve! */
3252         netif_wake_subqueue(netdev, tx_ring->queue_index);
3253         ++adapter->restart_queue;
3254         return 0;
3255 }
3256
3257 static int igb_maybe_stop_tx(struct net_device *netdev,
3258                              struct igb_ring *tx_ring, int size)
3259 {
3260         if (igb_desc_unused(tx_ring) >= size)
3261                 return 0;
3262         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3263 }
3264
3265 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3266                                    struct net_device *netdev,
3267                                    struct igb_ring *tx_ring)
3268 {
3269         struct igb_adapter *adapter = netdev_priv(netdev);
3270         unsigned int first;
3271         unsigned int tx_flags = 0;
3272         u8 hdr_len = 0;
3273         int count = 0;
3274         int tso = 0;
3275         union skb_shared_tx *shtx;
3276
3277         if (test_bit(__IGB_DOWN, &adapter->state)) {
3278                 dev_kfree_skb_any(skb);
3279                 return NETDEV_TX_OK;
3280         }
3281
3282         if (skb->len <= 0) {
3283                 dev_kfree_skb_any(skb);
3284                 return NETDEV_TX_OK;
3285         }
3286
3287         /* need: 1 descriptor per page,
3288          *       + 2 desc gap to keep tail from touching head,
3289          *       + 1 desc for skb->data,
3290          *       + 1 desc for context descriptor,
3291          * otherwise try next time */
3292         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3293                 /* this is a hard error */
3294                 return NETDEV_TX_BUSY;
3295         }
3296
3297         /*
3298          * TODO: check that there currently is no other packet with
3299          * time stamping in the queue
3300          *
3301          * When doing time stamping, keep the connection to the socket
3302          * a while longer: it is still needed by skb_hwtstamp_tx(),
3303          * called either in igb_tx_hwtstamp() or by our caller when
3304          * doing software time stamping.
3305          */
3306         shtx = skb_tx(skb);
3307         if (unlikely(shtx->hardware)) {
3308                 shtx->in_progress = 1;
3309                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3310         }
3311
3312         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3313                 tx_flags |= IGB_TX_FLAGS_VLAN;
3314                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3315         }
3316
3317         if (skb->protocol == htons(ETH_P_IP))
3318                 tx_flags |= IGB_TX_FLAGS_IPV4;
3319
3320         first = tx_ring->next_to_use;
3321         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3322                                               &hdr_len) : 0;
3323
3324         if (tso < 0) {
3325                 dev_kfree_skb_any(skb);
3326                 return NETDEV_TX_OK;
3327         }
3328
3329         if (tso)
3330                 tx_flags |= IGB_TX_FLAGS_TSO;
3331         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3332                  (skb->ip_summed == CHECKSUM_PARTIAL))
3333                 tx_flags |= IGB_TX_FLAGS_CSUM;
3334
3335         /*
3336          * count reflects descriptors mapped, if 0 then mapping error
3337          * has occured and we need to rewind the descriptor queue
3338          */
3339         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3340
3341         if (count) {
3342                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3343                                  skb->len, hdr_len);
3344                 netdev->trans_start = jiffies;
3345                 /* Make sure there is space in the ring for the next send. */
3346                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3347         } else {
3348                 dev_kfree_skb_any(skb);
3349                 tx_ring->buffer_info[first].time_stamp = 0;
3350                 tx_ring->next_to_use = first;
3351         }
3352
3353         return NETDEV_TX_OK;
3354 }
3355
3356 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3357 {
3358         struct igb_adapter *adapter = netdev_priv(netdev);
3359         struct igb_ring *tx_ring;
3360
3361         int r_idx = 0;
3362         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3363         tx_ring = adapter->multi_tx_table[r_idx];
3364
3365         /* This goes back to the question of how to logically map a tx queue
3366          * to a flow.  Right now, performance is impacted slightly negatively
3367          * if using multiple tx queues.  If the stack breaks away from a
3368          * single qdisc implementation, we can look at this again. */
3369         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3370 }
3371
3372 /**
3373  * igb_tx_timeout - Respond to a Tx Hang
3374  * @netdev: network interface device structure
3375  **/
3376 static void igb_tx_timeout(struct net_device *netdev)
3377 {
3378         struct igb_adapter *adapter = netdev_priv(netdev);
3379         struct e1000_hw *hw = &adapter->hw;
3380
3381         /* Do the reset outside of interrupt context */
3382         adapter->tx_timeout_count++;
3383         schedule_work(&adapter->reset_task);
3384         wr32(E1000_EICS,
3385              (adapter->eims_enable_mask & ~adapter->eims_other));
3386 }
3387
3388 static void igb_reset_task(struct work_struct *work)
3389 {
3390         struct igb_adapter *adapter;
3391         adapter = container_of(work, struct igb_adapter, reset_task);
3392
3393         igb_reinit_locked(adapter);
3394 }
3395
3396 /**
3397  * igb_get_stats - Get System Network Statistics
3398  * @netdev: network interface device structure
3399  *
3400  * Returns the address of the device statistics structure.
3401  * The statistics are actually updated from the timer callback.
3402  **/
3403 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3404 {
3405         struct igb_adapter *adapter = netdev_priv(netdev);
3406
3407         /* only return the current stats */
3408         return &adapter->net_stats;
3409 }
3410
3411 /**
3412  * igb_change_mtu - Change the Maximum Transfer Unit
3413  * @netdev: network interface device structure
3414  * @new_mtu: new value for maximum frame size
3415  *
3416  * Returns 0 on success, negative on failure
3417  **/
3418 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3419 {
3420         struct igb_adapter *adapter = netdev_priv(netdev);
3421         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3422
3423         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3424             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3425                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3426                 return -EINVAL;
3427         }
3428
3429         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3430                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3431                 return -EINVAL;
3432         }
3433
3434         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3435                 msleep(1);
3436
3437         /* igb_down has a dependency on max_frame_size */
3438         adapter->max_frame_size = max_frame;
3439         if (netif_running(netdev))
3440                 igb_down(adapter);
3441
3442         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3443          * means we reserve 2 more, this pushes us to allocate from the next
3444          * larger slab size.
3445          * i.e. RXBUFFER_2048 --> size-4096 slab
3446          */
3447
3448         if (max_frame <= IGB_RXBUFFER_256)
3449                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3450         else if (max_frame <= IGB_RXBUFFER_512)
3451                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3452         else if (max_frame <= IGB_RXBUFFER_1024)
3453                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3454         else if (max_frame <= IGB_RXBUFFER_2048)
3455                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3456         else
3457 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3458                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3459 #else
3460                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3461 #endif
3462
3463         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3464         if (adapter->vfs_allocated_count &&
3465             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3466                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3467
3468         /* adjust allocation if LPE protects us, and we aren't using SBP */
3469         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3470              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3471                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3472
3473         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3474                  netdev->mtu, new_mtu);
3475         netdev->mtu = new_mtu;
3476
3477         if (netif_running(netdev))
3478                 igb_up(adapter);
3479         else
3480                 igb_reset(adapter);
3481
3482         clear_bit(__IGB_RESETTING, &adapter->state);
3483
3484         return 0;
3485 }
3486
3487 /**
3488  * igb_update_stats - Update the board statistics counters
3489  * @adapter: board private structure
3490  **/
3491
3492 void igb_update_stats(struct igb_adapter *adapter)
3493 {
3494         struct e1000_hw *hw = &adapter->hw;
3495         struct pci_dev *pdev = adapter->pdev;
3496         u16 phy_tmp;
3497
3498 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3499
3500         /*
3501          * Prevent stats update while adapter is being reset, or if the pci
3502          * connection is down.
3503          */
3504         if (adapter->link_speed == 0)
3505                 return;
3506         if (pci_channel_offline(pdev))
3507                 return;
3508
3509         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3510         adapter->stats.gprc += rd32(E1000_GPRC);
3511         adapter->stats.gorc += rd32(E1000_GORCL);
3512         rd32(E1000_GORCH); /* clear GORCL */
3513         adapter->stats.bprc += rd32(E1000_BPRC);
3514         adapter->stats.mprc += rd32(E1000_MPRC);
3515         adapter->stats.roc += rd32(E1000_ROC);
3516
3517         adapter->stats.prc64 += rd32(E1000_PRC64);
3518         adapter->stats.prc127 += rd32(E1000_PRC127);
3519         adapter->stats.prc255 += rd32(E1000_PRC255);
3520         adapter->stats.prc511 += rd32(E1000_PRC511);
3521         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3522         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3523         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3524         adapter->stats.sec += rd32(E1000_SEC);
3525
3526         adapter->stats.mpc += rd32(E1000_MPC);
3527         adapter->stats.scc += rd32(E1000_SCC);
3528         adapter->stats.ecol += rd32(E1000_ECOL);
3529         adapter->stats.mcc += rd32(E1000_MCC);
3530         adapter->stats.latecol += rd32(E1000_LATECOL);
3531         adapter->stats.dc += rd32(E1000_DC);
3532         adapter->stats.rlec += rd32(E1000_RLEC);
3533         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3534         adapter->stats.xontxc += rd32(E1000_XONTXC);
3535         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3536         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3537         adapter->stats.fcruc += rd32(E1000_FCRUC);
3538         adapter->stats.gptc += rd32(E1000_GPTC);
3539         adapter->stats.gotc += rd32(E1000_GOTCL);
3540         rd32(E1000_GOTCH); /* clear GOTCL */
3541         adapter->stats.rnbc += rd32(E1000_RNBC);
3542         adapter->stats.ruc += rd32(E1000_RUC);
3543         adapter->stats.rfc += rd32(E1000_RFC);
3544         adapter->stats.rjc += rd32(E1000_RJC);
3545         adapter->stats.tor += rd32(E1000_TORH);
3546         adapter->stats.tot += rd32(E1000_TOTH);
3547         adapter->stats.tpr += rd32(E1000_TPR);
3548
3549         adapter->stats.ptc64 += rd32(E1000_PTC64);
3550         adapter->stats.ptc127 += rd32(E1000_PTC127);
3551         adapter->stats.ptc255 += rd32(E1000_PTC255);
3552         adapter->stats.ptc511 += rd32(E1000_PTC511);
3553         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3554         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3555
3556         adapter->stats.mptc += rd32(E1000_MPTC);
3557         adapter->stats.bptc += rd32(E1000_BPTC);
3558
3559         /* used for adaptive IFS */
3560
3561         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3562         adapter->stats.tpt += hw->mac.tx_packet_delta;
3563         hw->mac.collision_delta = rd32(E1000_COLC);
3564         adapter->stats.colc += hw->mac.collision_delta;
3565
3566         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3567         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3568         adapter->stats.tncrs += rd32(E1000_TNCRS);
3569         adapter->stats.tsctc += rd32(E1000_TSCTC);
3570         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3571
3572         adapter->stats.iac += rd32(E1000_IAC);
3573         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3574         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3575         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3576         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3577         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3578         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3579         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3580         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3581
3582         /* Fill out the OS statistics structure */
3583         adapter->net_stats.multicast = adapter->stats.mprc;
3584         adapter->net_stats.collisions = adapter->stats.colc;
3585
3586         /* Rx Errors */
3587
3588         /* RLEC on some newer hardware can be incorrect so build
3589         * our own version based on RUC and ROC */
3590         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3591                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3592                 adapter->stats.ruc + adapter->stats.roc +
3593                 adapter->stats.cexterr;
3594         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3595                                               adapter->stats.roc;
3596         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3597         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3598         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3599
3600         /* Tx Errors */
3601         adapter->net_stats.tx_errors = adapter->stats.ecol +
3602                                        adapter->stats.latecol;
3603         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3604         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3605         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3606
3607         /* Tx Dropped needs to be maintained elsewhere */
3608
3609         /* Phy Stats */
3610         if (hw->phy.media_type == e1000_media_type_copper) {
3611                 if ((adapter->link_speed == SPEED_1000) &&
3612                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3613                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3614                         adapter->phy_stats.idle_errors += phy_tmp;
3615                 }
3616         }
3617
3618         /* Management Stats */
3619         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3620         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3621         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3622 }
3623
3624 static irqreturn_t igb_msix_other(int irq, void *data)
3625 {
3626         struct net_device *netdev = data;
3627         struct igb_adapter *adapter = netdev_priv(netdev);
3628         struct e1000_hw *hw = &adapter->hw;
3629         u32 icr = rd32(E1000_ICR);
3630
3631         /* reading ICR causes bit 31 of EICR to be cleared */
3632
3633         if(icr & E1000_ICR_DOUTSYNC) {
3634                 /* HW is reporting DMA is out of sync */
3635                 adapter->stats.doosync++;
3636         }
3637
3638         /* Check for a mailbox event */
3639         if (icr & E1000_ICR_VMMB)
3640                 igb_msg_task(adapter);
3641
3642         if (icr & E1000_ICR_LSC) {
3643                 hw->mac.get_link_status = 1;
3644                 /* guard against interrupt when we're going down */
3645                 if (!test_bit(__IGB_DOWN, &adapter->state))
3646                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3647         }
3648
3649         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3650         wr32(E1000_EIMS, adapter->eims_other);
3651
3652         return IRQ_HANDLED;
3653 }
3654
3655 static irqreturn_t igb_msix_tx(int irq, void *data)
3656 {
3657         struct igb_ring *tx_ring = data;
3658         struct igb_adapter *adapter = tx_ring->adapter;
3659         struct e1000_hw *hw = &adapter->hw;
3660
3661 #ifdef CONFIG_IGB_DCA
3662         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3663                 igb_update_tx_dca(tx_ring);
3664 #endif
3665
3666         tx_ring->total_bytes = 0;
3667         tx_ring->total_packets = 0;
3668
3669         /* auto mask will automatically reenable the interrupt when we write
3670          * EICS */
3671         if (!igb_clean_tx_irq(tx_ring))
3672                 /* Ring was not completely cleaned, so fire another interrupt */
3673                 wr32(E1000_EICS, tx_ring->eims_value);
3674         else
3675                 wr32(E1000_EIMS, tx_ring->eims_value);
3676
3677         return IRQ_HANDLED;
3678 }
3679
3680 static void igb_write_itr(struct igb_ring *ring)
3681 {
3682         struct e1000_hw *hw = &ring->adapter->hw;
3683         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3684                 switch (hw->mac.type) {
3685                 case e1000_82576:
3686                         wr32(ring->itr_register, ring->itr_val |
3687                              0x80000000);
3688                         break;
3689                 default:
3690                         wr32(ring->itr_register, ring->itr_val |
3691                              (ring->itr_val << 16));
3692                         break;
3693                 }
3694                 ring->set_itr = 0;
3695         }
3696 }
3697
3698 static irqreturn_t igb_msix_rx(int irq, void *data)
3699 {
3700         struct igb_ring *rx_ring = data;
3701
3702         /* Write the ITR value calculated at the end of the
3703          * previous interrupt.
3704          */
3705
3706         igb_write_itr(rx_ring);
3707
3708         if (napi_schedule_prep(&rx_ring->napi))
3709                 __napi_schedule(&rx_ring->napi);
3710
3711 #ifdef CONFIG_IGB_DCA
3712         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3713                 igb_update_rx_dca(rx_ring);
3714 #endif
3715                 return IRQ_HANDLED;
3716 }
3717
3718 #ifdef CONFIG_IGB_DCA
3719 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3720 {
3721         u32 dca_rxctrl;
3722         struct igb_adapter *adapter = rx_ring->adapter;
3723         struct e1000_hw *hw = &adapter->hw;
3724         int cpu = get_cpu();
3725         int q = rx_ring->reg_idx;
3726
3727         if (rx_ring->cpu != cpu) {
3728                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3729                 if (hw->mac.type == e1000_82576) {
3730                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3731                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3732                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3733                 } else {
3734                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3735                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3736                 }
3737                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3738                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3739                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3740                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3741                 rx_ring->cpu = cpu;
3742         }
3743         put_cpu();
3744 }
3745
3746 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3747 {
3748         u32 dca_txctrl;
3749         struct igb_adapter *adapter = tx_ring->adapter;
3750         struct e1000_hw *hw = &adapter->hw;
3751         int cpu = get_cpu();
3752         int q = tx_ring->reg_idx;
3753
3754         if (tx_ring->cpu != cpu) {
3755                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3756                 if (hw->mac.type == e1000_82576) {
3757                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3758                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3759                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3760                 } else {
3761                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3762                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3763                 }
3764                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3765                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3766                 tx_ring->cpu = cpu;
3767         }
3768         put_cpu();
3769 }
3770
3771 static void igb_setup_dca(struct igb_adapter *adapter)
3772 {
3773         int i;
3774
3775         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3776                 return;
3777
3778         for (i = 0; i < adapter->num_tx_queues; i++) {
3779                 adapter->tx_ring[i].cpu = -1;
3780                 igb_update_tx_dca(&adapter->tx_ring[i]);
3781         }
3782         for (i = 0; i < adapter->num_rx_queues; i++) {
3783                 adapter->rx_ring[i].cpu = -1;
3784                 igb_update_rx_dca(&adapter->rx_ring[i]);
3785         }
3786 }
3787
3788 static int __igb_notify_dca(struct device *dev, void *data)
3789 {
3790         struct net_device *netdev = dev_get_drvdata(dev);
3791         struct igb_adapter *adapter = netdev_priv(netdev);
3792         struct e1000_hw *hw = &adapter->hw;
3793         unsigned long event = *(unsigned long *)data;
3794
3795         switch (event) {
3796         case DCA_PROVIDER_ADD:
3797                 /* if already enabled, don't do it again */
3798                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3799                         break;
3800                 /* Always use CB2 mode, difference is masked
3801                  * in the CB driver. */
3802                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3803                 if (dca_add_requester(dev) == 0) {
3804                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3805                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3806                         igb_setup_dca(adapter);
3807                         break;
3808                 }
3809                 /* Fall Through since DCA is disabled. */
3810         case DCA_PROVIDER_REMOVE:
3811                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3812                         /* without this a class_device is left
3813                          * hanging around in the sysfs model */
3814                         dca_remove_requester(dev);
3815                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3816                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3817                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3818                 }
3819                 break;
3820         }
3821
3822         return 0;
3823 }
3824
3825 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3826                           void *p)
3827 {
3828         int ret_val;
3829
3830         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3831                                          __igb_notify_dca);
3832
3833         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3834 }
3835 #endif /* CONFIG_IGB_DCA */
3836
3837 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3838 {
3839         struct e1000_hw *hw = &adapter->hw;
3840         u32 ping;
3841         int i;
3842
3843         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3844                 ping = E1000_PF_CONTROL_MSG;
3845                 if (adapter->vf_data[i].clear_to_send)
3846                         ping |= E1000_VT_MSGTYPE_CTS;
3847                 igb_write_mbx(hw, &ping, 1, i);
3848         }
3849 }
3850
3851 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3852                                   u32 *msgbuf, u32 vf)
3853 {
3854         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3855         u16 *hash_list = (u16 *)&msgbuf[1];
3856         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3857         int i;
3858
3859         /* only up to 30 hash values supported */
3860         if (n > 30)
3861                 n = 30;
3862
3863         /* salt away the number of multi cast addresses assigned
3864          * to this VF for later use to restore when the PF multi cast
3865          * list changes
3866          */
3867         vf_data->num_vf_mc_hashes = n;
3868
3869         /* VFs are limited to using the MTA hash table for their multicast
3870          * addresses */
3871         for (i = 0; i < n; i++)
3872                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3873
3874         /* Flush and reset the mta with the new values */
3875         igb_set_multi(adapter->netdev);
3876
3877         return 0;
3878 }
3879
3880 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3881 {
3882         struct e1000_hw *hw = &adapter->hw;
3883         struct vf_data_storage *vf_data;
3884         int i, j;
3885
3886         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3887                 vf_data = &adapter->vf_data[i];
3888                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3889                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3890         }
3891 }
3892
3893 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3894 {
3895         struct e1000_hw *hw = &adapter->hw;
3896         u32 pool_mask, reg, vid;
3897         int i;
3898
3899         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3900
3901         /* Find the vlan filter for this id */
3902         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3903                 reg = rd32(E1000_VLVF(i));
3904
3905                 /* remove the vf from the pool */
3906                 reg &= ~pool_mask;
3907
3908                 /* if pool is empty then remove entry from vfta */
3909                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3910                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3911                         reg = 0;
3912                         vid = reg & E1000_VLVF_VLANID_MASK;
3913                         igb_vfta_set(hw, vid, false);
3914                 }
3915
3916                 wr32(E1000_VLVF(i), reg);
3917         }
3918 }
3919
3920 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3921 {
3922         struct e1000_hw *hw = &adapter->hw;
3923         u32 reg, i;
3924
3925         /* It is an error to call this function when VFs are not enabled */
3926         if (!adapter->vfs_allocated_count)
3927                 return -1;
3928
3929         /* Find the vlan filter for this id */
3930         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3931                 reg = rd32(E1000_VLVF(i));
3932                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3933                     vid == (reg & E1000_VLVF_VLANID_MASK))
3934                         break;
3935         }
3936
3937         if (add) {
3938                 if (i == E1000_VLVF_ARRAY_SIZE) {
3939                         /* Did not find a matching VLAN ID entry that was
3940                          * enabled.  Search for a free filter entry, i.e.
3941                          * one without the enable bit set
3942                          */
3943                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3944                                 reg = rd32(E1000_VLVF(i));
3945                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3946                                         break;
3947                         }
3948                 }
3949                 if (i < E1000_VLVF_ARRAY_SIZE) {
3950                         /* Found an enabled/available entry */
3951                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3952
3953                         /* if !enabled we need to set this up in vfta */
3954                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3955                                 /* add VID to filter table, if bit already set
3956                                  * PF must have added it outside of table */
3957                                 if (igb_vfta_set(hw, vid, true))
3958                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3959                                                 adapter->vfs_allocated_count);
3960                                 reg |= E1000_VLVF_VLANID_ENABLE;
3961                         }
3962                         reg &= ~E1000_VLVF_VLANID_MASK;
3963                         reg |= vid;
3964
3965                         wr32(E1000_VLVF(i), reg);
3966                         return 0;
3967                 }
3968         } else {
3969                 if (i < E1000_VLVF_ARRAY_SIZE) {
3970                         /* remove vf from the pool */
3971                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3972                         /* if pool is empty then remove entry from vfta */
3973                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3974                                 reg = 0;
3975                                 igb_vfta_set(hw, vid, false);
3976                         }
3977                         wr32(E1000_VLVF(i), reg);
3978                         return 0;
3979                 }
3980         }
3981         return -1;
3982 }
3983
3984 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3985 {
3986         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3987         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3988
3989         return igb_vlvf_set(adapter, vid, add, vf);
3990 }
3991
3992 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3993 {
3994         struct e1000_hw *hw = &adapter->hw;
3995
3996         /* disable mailbox functionality for vf */
3997         adapter->vf_data[vf].clear_to_send = false;
3998
3999         /* reset offloads to defaults */
4000         igb_set_vmolr(hw, vf);
4001
4002         /* reset vlans for device */
4003         igb_clear_vf_vfta(adapter, vf);
4004
4005         /* reset multicast table array for vf */
4006         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4007
4008         /* Flush and reset the mta with the new values */
4009         igb_set_multi(adapter->netdev);
4010 }
4011
4012 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4013 {
4014         struct e1000_hw *hw = &adapter->hw;
4015         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4016         u32 reg, msgbuf[3];
4017         u8 *addr = (u8 *)(&msgbuf[1]);
4018
4019         /* process all the same items cleared in a function level reset */
4020         igb_vf_reset_event(adapter, vf);
4021
4022         /* set vf mac address */
4023         igb_rar_set(hw, vf_mac, vf + 1);
4024         igb_set_rah_pool(hw, vf, vf + 1);
4025
4026         /* enable transmit and receive for vf */
4027         reg = rd32(E1000_VFTE);
4028         wr32(E1000_VFTE, reg | (1 << vf));
4029         reg = rd32(E1000_VFRE);
4030         wr32(E1000_VFRE, reg | (1 << vf));
4031
4032         /* enable mailbox functionality for vf */
4033         adapter->vf_data[vf].clear_to_send = true;
4034
4035         /* reply to reset with ack and vf mac address */
4036         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4037         memcpy(addr, vf_mac, 6);
4038         igb_write_mbx(hw, msgbuf, 3, vf);
4039 }
4040
4041 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4042 {
4043                 unsigned char *addr = (char *)&msg[1];
4044                 int err = -1;
4045
4046                 if (is_valid_ether_addr(addr))
4047                         err = igb_set_vf_mac(adapter, vf, addr);
4048
4049                 return err;
4050
4051 }
4052
4053 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4054 {
4055         struct e1000_hw *hw = &adapter->hw;
4056         u32 msg = E1000_VT_MSGTYPE_NACK;
4057
4058         /* if device isn't clear to send it shouldn't be reading either */
4059         if (!adapter->vf_data[vf].clear_to_send)
4060                 igb_write_mbx(hw, &msg, 1, vf);
4061 }
4062
4063
4064 static void igb_msg_task(struct igb_adapter *adapter)
4065 {
4066         struct e1000_hw *hw = &adapter->hw;
4067         u32 vf;
4068
4069         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4070                 /* process any reset requests */
4071                 if (!igb_check_for_rst(hw, vf)) {
4072                         adapter->vf_data[vf].clear_to_send = false;
4073                         igb_vf_reset_event(adapter, vf);
4074                 }
4075
4076                 /* process any messages pending */
4077                 if (!igb_check_for_msg(hw, vf))
4078                         igb_rcv_msg_from_vf(adapter, vf);
4079
4080                 /* process any acks */
4081                 if (!igb_check_for_ack(hw, vf))
4082                         igb_rcv_ack_from_vf(adapter, vf);
4083
4084         }
4085 }
4086
4087 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4088 {
4089         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4090         u32 msgbuf[mbx_size];
4091         struct e1000_hw *hw = &adapter->hw;
4092         s32 retval;
4093
4094         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4095
4096         if (retval)
4097                 dev_err(&adapter->pdev->dev,
4098                         "Error receiving message from VF\n");
4099
4100         /* this is a message we already processed, do nothing */
4101         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4102                 return retval;
4103
4104         /*
4105          * until the vf completes a reset it should not be
4106          * allowed to start any configuration.
4107          */
4108
4109         if (msgbuf[0] == E1000_VF_RESET) {
4110                 igb_vf_reset_msg(adapter, vf);
4111
4112                 return retval;
4113         }
4114
4115         if (!adapter->vf_data[vf].clear_to_send) {
4116                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4117                 igb_write_mbx(hw, msgbuf, 1, vf);
4118                 return retval;
4119         }
4120
4121         switch ((msgbuf[0] & 0xFFFF)) {
4122         case E1000_VF_SET_MAC_ADDR:
4123                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4124                 break;
4125         case E1000_VF_SET_MULTICAST:
4126                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4127                 break;
4128         case E1000_VF_SET_LPE:
4129                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4130                 break;
4131         case E1000_VF_SET_VLAN:
4132                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4133                 break;
4134         default:
4135                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4136                 retval = -1;
4137                 break;
4138         }
4139
4140         /* notify the VF of the results of what it sent us */
4141         if (retval)
4142                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4143         else
4144                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4145
4146         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4147
4148         igb_write_mbx(hw, msgbuf, 1, vf);
4149
4150         return retval;
4151 }
4152
4153 /**
4154  * igb_intr_msi - Interrupt Handler
4155  * @irq: interrupt number
4156  * @data: pointer to a network interface device structure
4157  **/
4158 static irqreturn_t igb_intr_msi(int irq, void *data)
4159 {
4160         struct net_device *netdev = data;
4161         struct igb_adapter *adapter = netdev_priv(netdev);
4162         struct e1000_hw *hw = &adapter->hw;
4163         /* read ICR disables interrupts using IAM */
4164         u32 icr = rd32(E1000_ICR);
4165
4166         igb_write_itr(adapter->rx_ring);
4167
4168         if(icr & E1000_ICR_DOUTSYNC) {
4169                 /* HW is reporting DMA is out of sync */
4170                 adapter->stats.doosync++;
4171         }
4172
4173         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4174                 hw->mac.get_link_status = 1;
4175                 if (!test_bit(__IGB_DOWN, &adapter->state))
4176                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4177         }
4178
4179         napi_schedule(&adapter->rx_ring[0].napi);
4180
4181         return IRQ_HANDLED;
4182 }
4183
4184 /**
4185  * igb_intr - Legacy Interrupt Handler
4186  * @irq: interrupt number
4187  * @data: pointer to a network interface device structure
4188  **/
4189 static irqreturn_t igb_intr(int irq, void *data)
4190 {
4191         struct net_device *netdev = data;
4192         struct igb_adapter *adapter = netdev_priv(netdev);
4193         struct e1000_hw *hw = &adapter->hw;
4194         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4195          * need for the IMC write */
4196         u32 icr = rd32(E1000_ICR);
4197         if (!icr)
4198                 return IRQ_NONE;  /* Not our interrupt */
4199
4200         igb_write_itr(adapter->rx_ring);
4201
4202         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4203          * not set, then the adapter didn't send an interrupt */
4204         if (!(icr & E1000_ICR_INT_ASSERTED))
4205                 return IRQ_NONE;
4206
4207         if(icr & E1000_ICR_DOUTSYNC) {
4208                 /* HW is reporting DMA is out of sync */
4209                 adapter->stats.doosync++;
4210         }
4211
4212         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4213                 hw->mac.get_link_status = 1;
4214                 /* guard against interrupt when we're going down */
4215                 if (!test_bit(__IGB_DOWN, &adapter->state))
4216                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4217         }
4218
4219         napi_schedule(&adapter->rx_ring[0].napi);
4220
4221         return IRQ_HANDLED;
4222 }
4223
4224 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4225 {
4226         struct igb_adapter *adapter = rx_ring->adapter;
4227         struct e1000_hw *hw = &adapter->hw;
4228
4229         if (adapter->itr_setting & 3) {
4230                 if (adapter->num_rx_queues == 1)
4231                         igb_set_itr(adapter);
4232                 else
4233                         igb_update_ring_itr(rx_ring);
4234         }
4235
4236         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4237                 if (adapter->msix_entries)
4238                         wr32(E1000_EIMS, rx_ring->eims_value);
4239                 else
4240                         igb_irq_enable(adapter);
4241         }
4242 }
4243
4244 /**
4245  * igb_poll - NAPI Rx polling callback
4246  * @napi: napi polling structure
4247  * @budget: count of how many packets we should handle
4248  **/
4249 static int igb_poll(struct napi_struct *napi, int budget)
4250 {
4251         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4252         int work_done = 0;
4253
4254 #ifdef CONFIG_IGB_DCA
4255         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4256                 igb_update_rx_dca(rx_ring);
4257 #endif
4258         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4259
4260         if (rx_ring->buddy) {
4261 #ifdef CONFIG_IGB_DCA
4262                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4263                         igb_update_tx_dca(rx_ring->buddy);
4264 #endif
4265                 if (!igb_clean_tx_irq(rx_ring->buddy))
4266                         work_done = budget;
4267         }
4268
4269         /* If not enough Rx work done, exit the polling mode */
4270         if (work_done < budget) {
4271                 napi_complete(napi);
4272                 igb_rx_irq_enable(rx_ring);
4273         }
4274
4275         return work_done;
4276 }
4277
4278 /**
4279  * igb_hwtstamp - utility function which checks for TX time stamp
4280  * @adapter: board private structure
4281  * @skb: packet that was just sent
4282  *
4283  * If we were asked to do hardware stamping and such a time stamp is
4284  * available, then it must have been for this skb here because we only
4285  * allow only one such packet into the queue.
4286  */
4287 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4288 {
4289         union skb_shared_tx *shtx = skb_tx(skb);
4290         struct e1000_hw *hw = &adapter->hw;
4291
4292         if (unlikely(shtx->hardware)) {
4293                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4294                 if (valid) {
4295                         u64 regval = rd32(E1000_TXSTMPL);
4296                         u64 ns;
4297                         struct skb_shared_hwtstamps shhwtstamps;
4298
4299                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4300                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4301                         ns = timecounter_cyc2time(&adapter->clock,
4302                                                   regval);
4303                         timecompare_update(&adapter->compare, ns);
4304                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4305                         shhwtstamps.syststamp =
4306                                 timecompare_transform(&adapter->compare, ns);
4307                         skb_tstamp_tx(skb, &shhwtstamps);
4308                 }
4309         }
4310 }
4311
4312 /**
4313  * igb_clean_tx_irq - Reclaim resources after transmit completes
4314  * @adapter: board private structure
4315  * returns true if ring is completely cleaned
4316  **/
4317 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4318 {
4319         struct igb_adapter *adapter = tx_ring->adapter;
4320         struct net_device *netdev = adapter->netdev;
4321         struct e1000_hw *hw = &adapter->hw;
4322         struct igb_buffer *buffer_info;
4323         struct sk_buff *skb;
4324         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4325         unsigned int total_bytes = 0, total_packets = 0;
4326         unsigned int i, eop, count = 0;
4327         bool cleaned = false;
4328
4329         i = tx_ring->next_to_clean;
4330         eop = tx_ring->buffer_info[i].next_to_watch;
4331         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4332
4333         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4334                (count < tx_ring->count)) {
4335                 for (cleaned = false; !cleaned; count++) {
4336                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4337                         buffer_info = &tx_ring->buffer_info[i];
4338                         cleaned = (i == eop);
4339                         skb = buffer_info->skb;
4340
4341                         if (skb) {
4342                                 unsigned int segs, bytecount;
4343                                 /* gso_segs is currently only valid for tcp */
4344                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4345                                 /* multiply data chunks by size of headers */
4346                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4347                                             skb->len;
4348                                 total_packets += segs;
4349                                 total_bytes += bytecount;
4350
4351                                 igb_tx_hwtstamp(adapter, skb);
4352                         }
4353
4354                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4355                         tx_desc->wb.status = 0;
4356
4357                         i++;
4358                         if (i == tx_ring->count)
4359                                 i = 0;
4360                 }
4361                 eop = tx_ring->buffer_info[i].next_to_watch;
4362                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4363         }
4364
4365         tx_ring->next_to_clean = i;
4366
4367         if (unlikely(count &&
4368                      netif_carrier_ok(netdev) &&
4369                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4370                 /* Make sure that anybody stopping the queue after this
4371                  * sees the new next_to_clean.
4372                  */
4373                 smp_mb();
4374                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4375                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4376                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4377                         ++adapter->restart_queue;
4378                 }
4379         }
4380
4381         if (tx_ring->detect_tx_hung) {
4382                 /* Detect a transmit hang in hardware, this serializes the
4383                  * check with the clearing of time_stamp and movement of i */
4384                 tx_ring->detect_tx_hung = false;
4385                 if (tx_ring->buffer_info[i].time_stamp &&
4386                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4387                                (adapter->tx_timeout_factor * HZ))
4388                     && !(rd32(E1000_STATUS) &
4389                          E1000_STATUS_TXOFF)) {
4390
4391                         /* detected Tx unit hang */
4392                         dev_err(&adapter->pdev->dev,
4393                                 "Detected Tx Unit Hang\n"
4394                                 "  Tx Queue             <%d>\n"
4395                                 "  TDH                  <%x>\n"
4396                                 "  TDT                  <%x>\n"
4397                                 "  next_to_use          <%x>\n"
4398                                 "  next_to_clean        <%x>\n"
4399                                 "buffer_info[next_to_clean]\n"
4400                                 "  time_stamp           <%lx>\n"
4401                                 "  next_to_watch        <%x>\n"
4402                                 "  jiffies              <%lx>\n"
4403                                 "  desc.status          <%x>\n",
4404                                 tx_ring->queue_index,
4405                                 readl(adapter->hw.hw_addr + tx_ring->head),
4406                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4407                                 tx_ring->next_to_use,
4408                                 tx_ring->next_to_clean,
4409                                 tx_ring->buffer_info[i].time_stamp,
4410                                 eop,
4411                                 jiffies,
4412                                 eop_desc->wb.status);
4413                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4414                 }
4415         }
4416         tx_ring->total_bytes += total_bytes;
4417         tx_ring->total_packets += total_packets;
4418         tx_ring->tx_stats.bytes += total_bytes;
4419         tx_ring->tx_stats.packets += total_packets;
4420         adapter->net_stats.tx_bytes += total_bytes;
4421         adapter->net_stats.tx_packets += total_packets;
4422         return (count < tx_ring->count);
4423 }
4424
4425 /**
4426  * igb_receive_skb - helper function to handle rx indications
4427  * @ring: pointer to receive ring receving this packet
4428  * @status: descriptor status field as written by hardware
4429  * @rx_desc: receive descriptor containing vlan and type information.
4430  * @skb: pointer to sk_buff to be indicated to stack
4431  **/
4432 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4433                             union e1000_adv_rx_desc * rx_desc,
4434                             struct sk_buff *skb)
4435 {
4436         struct igb_adapter * adapter = ring->adapter;
4437         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4438
4439         skb_record_rx_queue(skb, ring->queue_index);
4440         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4441                 if (vlan_extracted)
4442                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
4443                                          le16_to_cpu(rx_desc->wb.upper.vlan),
4444                                          skb);
4445                 else
4446                         napi_gro_receive(&ring->napi, skb);
4447         } else {
4448                 if (vlan_extracted)
4449                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4450                                           le16_to_cpu(rx_desc->wb.upper.vlan));
4451                 else
4452                         netif_receive_skb(skb);
4453         }
4454 }
4455
4456 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4457                                        u32 status_err, struct sk_buff *skb)
4458 {
4459         skb->ip_summed = CHECKSUM_NONE;
4460
4461         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4462         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4463                 return;
4464         /* TCP/UDP checksum error bit is set */
4465         if (status_err &
4466             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4467                 /* let the stack verify checksum errors */
4468                 adapter->hw_csum_err++;
4469                 return;
4470         }
4471         /* It must be a TCP or UDP packet with a valid checksum */
4472         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4473                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4474
4475         adapter->hw_csum_good++;
4476 }
4477
4478 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4479                                  int *work_done, int budget)
4480 {
4481         struct igb_adapter *adapter = rx_ring->adapter;
4482         struct net_device *netdev = adapter->netdev;
4483         struct e1000_hw *hw = &adapter->hw;
4484         struct pci_dev *pdev = adapter->pdev;
4485         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4486         struct igb_buffer *buffer_info , *next_buffer;
4487         struct sk_buff *skb;
4488         bool cleaned = false;
4489         int cleaned_count = 0;
4490         unsigned int total_bytes = 0, total_packets = 0;
4491         unsigned int i;
4492         u32 length, hlen, staterr;
4493
4494         i = rx_ring->next_to_clean;
4495         buffer_info = &rx_ring->buffer_info[i];
4496         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4497         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4498
4499         while (staterr & E1000_RXD_STAT_DD) {
4500                 if (*work_done >= budget)
4501                         break;
4502                 (*work_done)++;
4503
4504                 skb = buffer_info->skb;
4505                 prefetch(skb->data - NET_IP_ALIGN);
4506                 buffer_info->skb = NULL;
4507
4508                 i++;
4509                 if (i == rx_ring->count)
4510                         i = 0;
4511                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4512                 prefetch(next_rxd);
4513                 next_buffer = &rx_ring->buffer_info[i];
4514
4515                 length = le16_to_cpu(rx_desc->wb.upper.length);
4516                 cleaned = true;
4517                 cleaned_count++;
4518
4519                 if (!adapter->rx_ps_hdr_size) {
4520                         pci_unmap_single(pdev, buffer_info->dma,
4521                                          adapter->rx_buffer_len +
4522                                            NET_IP_ALIGN,
4523                                          PCI_DMA_FROMDEVICE);
4524                         skb_put(skb, length);
4525                         goto send_up;
4526                 }
4527
4528                 /* HW will not DMA in data larger than the given buffer, even
4529                  * if it parses the (NFS, of course) header to be larger.  In
4530                  * that case, it fills the header buffer and spills the rest
4531                  * into the page.
4532                  */
4533                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4534                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4535                 if (hlen > adapter->rx_ps_hdr_size)
4536                         hlen = adapter->rx_ps_hdr_size;
4537
4538                 if (!skb_shinfo(skb)->nr_frags) {
4539                         pci_unmap_single(pdev, buffer_info->dma,
4540                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4541                                          PCI_DMA_FROMDEVICE);
4542                         skb_put(skb, hlen);
4543                 }
4544
4545                 if (length) {
4546                         pci_unmap_page(pdev, buffer_info->page_dma,
4547                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4548                         buffer_info->page_dma = 0;
4549
4550                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4551                                                 buffer_info->page,
4552                                                 buffer_info->page_offset,
4553                                                 length);
4554
4555                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4556                             (page_count(buffer_info->page) != 1))
4557                                 buffer_info->page = NULL;
4558                         else
4559                                 get_page(buffer_info->page);
4560
4561                         skb->len += length;
4562                         skb->data_len += length;
4563
4564                         skb->truesize += length;
4565                 }
4566
4567                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4568                         buffer_info->skb = next_buffer->skb;
4569                         buffer_info->dma = next_buffer->dma;
4570                         next_buffer->skb = skb;
4571                         next_buffer->dma = 0;
4572                         goto next_desc;
4573                 }
4574 send_up:
4575                 /*
4576                  * If this bit is set, then the RX registers contain
4577                  * the time stamp. No other packet will be time
4578                  * stamped until we read these registers, so read the
4579                  * registers to make them available again. Because
4580                  * only one packet can be time stamped at a time, we
4581                  * know that the register values must belong to this
4582                  * one here and therefore we don't need to compare
4583                  * any of the additional attributes stored for it.
4584                  *
4585                  * If nothing went wrong, then it should have a
4586                  * skb_shared_tx that we can turn into a
4587                  * skb_shared_hwtstamps.
4588                  *
4589                  * TODO: can time stamping be triggered (thus locking
4590                  * the registers) without the packet reaching this point
4591                  * here? In that case RX time stamping would get stuck.
4592                  *
4593                  * TODO: in "time stamp all packets" mode this bit is
4594                  * not set. Need a global flag for this mode and then
4595                  * always read the registers. Cannot be done without
4596                  * a race condition.
4597                  */
4598                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4599                         u64 regval;
4600                         u64 ns;
4601                         struct skb_shared_hwtstamps *shhwtstamps =
4602                                 skb_hwtstamps(skb);
4603
4604                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4605                              "igb: no RX time stamp available for time stamped packet");
4606                         regval = rd32(E1000_RXSTMPL);
4607                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4608                         ns = timecounter_cyc2time(&adapter->clock, regval);
4609                         timecompare_update(&adapter->compare, ns);
4610                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4611                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4612                         shhwtstamps->syststamp =
4613                                 timecompare_transform(&adapter->compare, ns);
4614                 }
4615
4616                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4617                         dev_kfree_skb_irq(skb);
4618                         goto next_desc;
4619                 }
4620
4621                 total_bytes += skb->len;
4622                 total_packets++;
4623
4624                 igb_rx_checksum_adv(adapter, staterr, skb);
4625
4626                 skb->protocol = eth_type_trans(skb, netdev);
4627
4628                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4629
4630 next_desc:
4631                 rx_desc->wb.upper.status_error = 0;
4632
4633                 /* return some buffers to hardware, one at a time is too slow */
4634                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4635                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4636                         cleaned_count = 0;
4637                 }
4638
4639                 /* use prefetched values */
4640                 rx_desc = next_rxd;
4641                 buffer_info = next_buffer;
4642                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4643         }
4644
4645         rx_ring->next_to_clean = i;
4646         cleaned_count = igb_desc_unused(rx_ring);
4647
4648         if (cleaned_count)
4649                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4650
4651         rx_ring->total_packets += total_packets;
4652         rx_ring->total_bytes += total_bytes;
4653         rx_ring->rx_stats.packets += total_packets;
4654         rx_ring->rx_stats.bytes += total_bytes;
4655         adapter->net_stats.rx_bytes += total_bytes;
4656         adapter->net_stats.rx_packets += total_packets;
4657         return cleaned;
4658 }
4659
4660 /**
4661  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4662  * @adapter: address of board private structure
4663  **/
4664 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4665                                      int cleaned_count)
4666 {
4667         struct igb_adapter *adapter = rx_ring->adapter;
4668         struct net_device *netdev = adapter->netdev;
4669         struct pci_dev *pdev = adapter->pdev;
4670         union e1000_adv_rx_desc *rx_desc;
4671         struct igb_buffer *buffer_info;
4672         struct sk_buff *skb;
4673         unsigned int i;
4674         int bufsz;
4675
4676         i = rx_ring->next_to_use;
4677         buffer_info = &rx_ring->buffer_info[i];
4678
4679         if (adapter->rx_ps_hdr_size)
4680                 bufsz = adapter->rx_ps_hdr_size;
4681         else
4682                 bufsz = adapter->rx_buffer_len;
4683         bufsz += NET_IP_ALIGN;
4684
4685         while (cleaned_count--) {
4686                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4687
4688                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4689                         if (!buffer_info->page) {
4690                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4691                                 if (!buffer_info->page) {
4692                                         adapter->alloc_rx_buff_failed++;
4693                                         goto no_buffers;
4694                                 }
4695                                 buffer_info->page_offset = 0;
4696                         } else {
4697                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4698                         }
4699                         buffer_info->page_dma =
4700                                 pci_map_page(pdev, buffer_info->page,
4701                                              buffer_info->page_offset,
4702                                              PAGE_SIZE / 2,
4703                                              PCI_DMA_FROMDEVICE);
4704                 }
4705
4706                 if (!buffer_info->skb) {
4707                         skb = netdev_alloc_skb(netdev, bufsz);
4708                         if (!skb) {
4709                                 adapter->alloc_rx_buff_failed++;
4710                                 goto no_buffers;
4711                         }
4712
4713                         /* Make buffer alignment 2 beyond a 16 byte boundary
4714                          * this will result in a 16 byte aligned IP header after
4715                          * the 14 byte MAC header is removed
4716                          */
4717                         skb_reserve(skb, NET_IP_ALIGN);
4718
4719                         buffer_info->skb = skb;
4720                         buffer_info->dma = pci_map_single(pdev, skb->data,
4721                                                           bufsz,
4722                                                           PCI_DMA_FROMDEVICE);
4723                 }
4724                 /* Refresh the desc even if buffer_addrs didn't change because
4725                  * each write-back erases this info. */
4726                 if (adapter->rx_ps_hdr_size) {
4727                         rx_desc->read.pkt_addr =
4728                              cpu_to_le64(buffer_info->page_dma);
4729                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4730                 } else {
4731                         rx_desc->read.pkt_addr =
4732                              cpu_to_le64(buffer_info->dma);
4733                         rx_desc->read.hdr_addr = 0;
4734                 }
4735
4736                 i++;
4737                 if (i == rx_ring->count)
4738                         i = 0;
4739                 buffer_info = &rx_ring->buffer_info[i];
4740         }
4741
4742 no_buffers:
4743         if (rx_ring->next_to_use != i) {
4744                 rx_ring->next_to_use = i;
4745                 if (i == 0)
4746                         i = (rx_ring->count - 1);
4747                 else
4748                         i--;
4749
4750                 /* Force memory writes to complete before letting h/w
4751                  * know there are new descriptors to fetch.  (Only
4752                  * applicable for weak-ordered memory model archs,
4753                  * such as IA-64). */
4754                 wmb();
4755                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4756         }
4757 }
4758
4759 /**
4760  * igb_mii_ioctl -
4761  * @netdev:
4762  * @ifreq:
4763  * @cmd:
4764  **/
4765 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4766 {
4767         struct igb_adapter *adapter = netdev_priv(netdev);
4768         struct mii_ioctl_data *data = if_mii(ifr);
4769
4770         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4771                 return -EOPNOTSUPP;
4772
4773         switch (cmd) {
4774         case SIOCGMIIPHY:
4775                 data->phy_id = adapter->hw.phy.addr;
4776                 break;
4777         case SIOCGMIIREG:
4778                 if (!capable(CAP_NET_ADMIN))
4779                         return -EPERM;
4780                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4781                                      &data->val_out))
4782                         return -EIO;
4783                 break;
4784         case SIOCSMIIREG:
4785         default:
4786                 return -EOPNOTSUPP;
4787         }
4788         return 0;
4789 }
4790
4791 /**
4792  * igb_hwtstamp_ioctl - control hardware time stamping
4793  * @netdev:
4794  * @ifreq:
4795  * @cmd:
4796  *
4797  * Outgoing time stamping can be enabled and disabled. Play nice and
4798  * disable it when requested, although it shouldn't case any overhead
4799  * when no packet needs it. At most one packet in the queue may be
4800  * marked for time stamping, otherwise it would be impossible to tell
4801  * for sure to which packet the hardware time stamp belongs.
4802  *
4803  * Incoming time stamping has to be configured via the hardware
4804  * filters. Not all combinations are supported, in particular event
4805  * type has to be specified. Matching the kind of event packet is
4806  * not supported, with the exception of "all V2 events regardless of
4807  * level 2 or 4".
4808  *
4809  **/
4810 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4811                               struct ifreq *ifr, int cmd)
4812 {
4813         struct igb_adapter *adapter = netdev_priv(netdev);
4814         struct e1000_hw *hw = &adapter->hw;
4815         struct hwtstamp_config config;
4816         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4817         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4818         u32 tsync_rx_ctl_type = 0;
4819         u32 tsync_rx_cfg = 0;
4820         int is_l4 = 0;
4821         int is_l2 = 0;
4822         short port = 319; /* PTP */
4823         u32 regval;
4824
4825         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4826                 return -EFAULT;
4827
4828         /* reserved for future extensions */
4829         if (config.flags)
4830                 return -EINVAL;
4831
4832         switch (config.tx_type) {
4833         case HWTSTAMP_TX_OFF:
4834                 tsync_tx_ctl_bit = 0;
4835                 break;
4836         case HWTSTAMP_TX_ON:
4837                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4838                 break;
4839         default:
4840                 return -ERANGE;
4841         }
4842
4843         switch (config.rx_filter) {
4844         case HWTSTAMP_FILTER_NONE:
4845                 tsync_rx_ctl_bit = 0;
4846                 break;
4847         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4848         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4849         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4850         case HWTSTAMP_FILTER_ALL:
4851                 /*
4852                  * register TSYNCRXCFG must be set, therefore it is not
4853                  * possible to time stamp both Sync and Delay_Req messages
4854                  * => fall back to time stamping all packets
4855                  */
4856                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4857                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4858                 break;
4859         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4860                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4861                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4862                 is_l4 = 1;
4863                 break;
4864         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4865                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4866                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4867                 is_l4 = 1;
4868                 break;
4869         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4870         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4871                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4872                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4873                 is_l2 = 1;
4874                 is_l4 = 1;
4875                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4876                 break;
4877         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4878         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4879                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4880                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4881                 is_l2 = 1;
4882                 is_l4 = 1;
4883                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4884                 break;
4885         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4886         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4887         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4888                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4889                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4890                 is_l2 = 1;
4891                 break;
4892         default:
4893                 return -ERANGE;
4894         }
4895
4896         /* enable/disable TX */
4897         regval = rd32(E1000_TSYNCTXCTL);
4898         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4899         wr32(E1000_TSYNCTXCTL, regval);
4900
4901         /* enable/disable RX, define which PTP packets are time stamped */
4902         regval = rd32(E1000_TSYNCRXCTL);
4903         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4904         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4905         wr32(E1000_TSYNCRXCTL, regval);
4906         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4907
4908         /*
4909          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4910          *                                          (Ethertype to filter on)
4911          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4912          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4913          */
4914         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4915
4916         /* L4 Queue Filter[0]: only filter by source and destination port */
4917         wr32(E1000_SPQF0, htons(port));
4918         wr32(E1000_IMIREXT(0), is_l4 ?
4919              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4920         wr32(E1000_IMIR(0), is_l4 ?
4921              (htons(port)
4922               | (0<<16) /* immediate interrupt disabled */
4923               | 0 /* (1<<17) bit cleared: do not bypass
4924                      destination port check */)
4925                 : 0);
4926         wr32(E1000_FTQF0, is_l4 ?
4927              (0x11 /* UDP */
4928               | (1<<15) /* VF not compared */
4929               | (1<<27) /* Enable Timestamping */
4930               | (7<<28) /* only source port filter enabled,
4931                            source/target address and protocol
4932                            masked */)
4933              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4934                                       enabled */));
4935
4936         wrfl();
4937
4938         adapter->hwtstamp_config = config;
4939
4940         /* clear TX/RX time stamp registers, just to be sure */
4941         regval = rd32(E1000_TXSTMPH);
4942         regval = rd32(E1000_RXSTMPH);
4943
4944         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4945                 -EFAULT : 0;
4946 }
4947
4948 /**
4949  * igb_ioctl -
4950  * @netdev:
4951  * @ifreq:
4952  * @cmd:
4953  **/
4954 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4955 {
4956         switch (cmd) {
4957         case SIOCGMIIPHY:
4958         case SIOCGMIIREG:
4959         case SIOCSMIIREG:
4960                 return igb_mii_ioctl(netdev, ifr, cmd);
4961         case SIOCSHWTSTAMP:
4962                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4963         default:
4964                 return -EOPNOTSUPP;
4965         }
4966 }
4967
4968 static void igb_vlan_rx_register(struct net_device *netdev,
4969                                  struct vlan_group *grp)
4970 {
4971         struct igb_adapter *adapter = netdev_priv(netdev);
4972         struct e1000_hw *hw = &adapter->hw;
4973         u32 ctrl, rctl;
4974
4975         igb_irq_disable(adapter);
4976         adapter->vlgrp = grp;
4977
4978         if (grp) {
4979                 /* enable VLAN tag insert/strip */
4980                 ctrl = rd32(E1000_CTRL);
4981                 ctrl |= E1000_CTRL_VME;
4982                 wr32(E1000_CTRL, ctrl);
4983
4984                 /* enable VLAN receive filtering */
4985                 rctl = rd32(E1000_RCTL);
4986                 rctl &= ~E1000_RCTL_CFIEN;
4987                 wr32(E1000_RCTL, rctl);
4988                 igb_update_mng_vlan(adapter);
4989         } else {
4990                 /* disable VLAN tag insert/strip */
4991                 ctrl = rd32(E1000_CTRL);
4992                 ctrl &= ~E1000_CTRL_VME;
4993                 wr32(E1000_CTRL, ctrl);
4994
4995                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4996                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4997                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4998                 }
4999         }
5000
5001         igb_rlpml_set(adapter);
5002
5003         if (!test_bit(__IGB_DOWN, &adapter->state))
5004                 igb_irq_enable(adapter);
5005 }
5006
5007 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5008 {
5009         struct igb_adapter *adapter = netdev_priv(netdev);
5010         struct e1000_hw *hw = &adapter->hw;
5011         int pf_id = adapter->vfs_allocated_count;
5012
5013         if ((hw->mng_cookie.status &
5014              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5015             (vid == adapter->mng_vlan_id))
5016                 return;
5017
5018         /* add vid to vlvf if sr-iov is enabled,
5019          * if that fails add directly to filter table */
5020         if (igb_vlvf_set(adapter, vid, true, pf_id))
5021                 igb_vfta_set(hw, vid, true);
5022
5023 }
5024
5025 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5026 {
5027         struct igb_adapter *adapter = netdev_priv(netdev);
5028         struct e1000_hw *hw = &adapter->hw;
5029         int pf_id = adapter->vfs_allocated_count;
5030
5031         igb_irq_disable(adapter);
5032         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5033
5034         if (!test_bit(__IGB_DOWN, &adapter->state))
5035                 igb_irq_enable(adapter);
5036
5037         if ((adapter->hw.mng_cookie.status &
5038              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5039             (vid == adapter->mng_vlan_id)) {
5040                 /* release control to f/w */
5041                 igb_release_hw_control(adapter);
5042                 return;
5043         }
5044
5045         /* remove vid from vlvf if sr-iov is enabled,
5046          * if not in vlvf remove from vfta */
5047         if (igb_vlvf_set(adapter, vid, false, pf_id))
5048                 igb_vfta_set(hw, vid, false);
5049 }
5050
5051 static void igb_restore_vlan(struct igb_adapter *adapter)
5052 {
5053         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5054
5055         if (adapter->vlgrp) {
5056                 u16 vid;
5057                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5058                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5059                                 continue;
5060                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5061                 }
5062         }
5063 }
5064
5065 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5066 {
5067         struct e1000_mac_info *mac = &adapter->hw.mac;
5068
5069         mac->autoneg = 0;
5070
5071         /* Fiber NICs only allow 1000 gbps Full duplex */
5072         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5073                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5074                 dev_err(&adapter->pdev->dev,
5075                         "Unsupported Speed/Duplex configuration\n");
5076                 return -EINVAL;
5077         }
5078
5079         switch (spddplx) {
5080         case SPEED_10 + DUPLEX_HALF:
5081                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5082                 break;
5083         case SPEED_10 + DUPLEX_FULL:
5084                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5085                 break;
5086         case SPEED_100 + DUPLEX_HALF:
5087                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5088                 break;
5089         case SPEED_100 + DUPLEX_FULL:
5090                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5091                 break;
5092         case SPEED_1000 + DUPLEX_FULL:
5093                 mac->autoneg = 1;
5094                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5095                 break;
5096         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5097         default:
5098                 dev_err(&adapter->pdev->dev,
5099                         "Unsupported Speed/Duplex configuration\n");
5100                 return -EINVAL;
5101         }
5102         return 0;
5103 }
5104
5105 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5106 {
5107         struct net_device *netdev = pci_get_drvdata(pdev);
5108         struct igb_adapter *adapter = netdev_priv(netdev);
5109         struct e1000_hw *hw = &adapter->hw;
5110         u32 ctrl, rctl, status;
5111         u32 wufc = adapter->wol;
5112 #ifdef CONFIG_PM
5113         int retval = 0;
5114 #endif
5115
5116         netif_device_detach(netdev);
5117
5118         if (netif_running(netdev))
5119                 igb_close(netdev);
5120
5121         igb_reset_interrupt_capability(adapter);
5122
5123         igb_free_queues(adapter);
5124
5125 #ifdef CONFIG_PM
5126         retval = pci_save_state(pdev);
5127         if (retval)
5128                 return retval;
5129 #endif
5130
5131         status = rd32(E1000_STATUS);
5132         if (status & E1000_STATUS_LU)
5133                 wufc &= ~E1000_WUFC_LNKC;
5134
5135         if (wufc) {
5136                 igb_setup_rctl(adapter);
5137                 igb_set_multi(netdev);
5138
5139                 /* turn on all-multi mode if wake on multicast is enabled */
5140                 if (wufc & E1000_WUFC_MC) {
5141                         rctl = rd32(E1000_RCTL);
5142                         rctl |= E1000_RCTL_MPE;
5143                         wr32(E1000_RCTL, rctl);
5144                 }
5145
5146                 ctrl = rd32(E1000_CTRL);
5147                 /* advertise wake from D3Cold */
5148                 #define E1000_CTRL_ADVD3WUC 0x00100000
5149                 /* phy power management enable */
5150                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5151                 ctrl |= E1000_CTRL_ADVD3WUC;
5152                 wr32(E1000_CTRL, ctrl);
5153
5154                 /* Allow time for pending master requests to run */
5155                 igb_disable_pcie_master(&adapter->hw);
5156
5157                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5158                 wr32(E1000_WUFC, wufc);
5159         } else {
5160                 wr32(E1000_WUC, 0);
5161                 wr32(E1000_WUFC, 0);
5162         }
5163
5164         *enable_wake = wufc || adapter->en_mng_pt;
5165         if (!*enable_wake)
5166                 igb_shutdown_fiber_serdes_link_82575(hw);
5167
5168         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5169          * would have already happened in close and is redundant. */
5170         igb_release_hw_control(adapter);
5171
5172         pci_disable_device(pdev);
5173
5174         return 0;
5175 }
5176
5177 #ifdef CONFIG_PM
5178 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5179 {
5180         int retval;
5181         bool wake;
5182
5183         retval = __igb_shutdown(pdev, &wake);
5184         if (retval)
5185                 return retval;
5186
5187         if (wake) {
5188                 pci_prepare_to_sleep(pdev);
5189         } else {
5190                 pci_wake_from_d3(pdev, false);
5191                 pci_set_power_state(pdev, PCI_D3hot);
5192         }
5193
5194         return 0;
5195 }
5196
5197 static int igb_resume(struct pci_dev *pdev)
5198 {
5199         struct net_device *netdev = pci_get_drvdata(pdev);
5200         struct igb_adapter *adapter = netdev_priv(netdev);
5201         struct e1000_hw *hw = &adapter->hw;
5202         u32 err;
5203
5204         pci_set_power_state(pdev, PCI_D0);
5205         pci_restore_state(pdev);
5206
5207         err = pci_enable_device_mem(pdev);
5208         if (err) {
5209                 dev_err(&pdev->dev,
5210                         "igb: Cannot enable PCI device from suspend\n");
5211                 return err;
5212         }
5213         pci_set_master(pdev);
5214
5215         pci_enable_wake(pdev, PCI_D3hot, 0);
5216         pci_enable_wake(pdev, PCI_D3cold, 0);
5217
5218         igb_set_interrupt_capability(adapter);
5219
5220         if (igb_alloc_queues(adapter)) {
5221                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5222                 return -ENOMEM;
5223         }
5224
5225         /* e1000_power_up_phy(adapter); */
5226
5227         igb_reset(adapter);
5228
5229         /* let the f/w know that the h/w is now under the control of the
5230          * driver. */
5231         igb_get_hw_control(adapter);
5232
5233         wr32(E1000_WUS, ~0);
5234
5235         if (netif_running(netdev)) {
5236                 err = igb_open(netdev);
5237                 if (err)
5238                         return err;
5239         }
5240
5241         netif_device_attach(netdev);
5242
5243         return 0;
5244 }
5245 #endif
5246
5247 static void igb_shutdown(struct pci_dev *pdev)
5248 {
5249         bool wake;
5250
5251         __igb_shutdown(pdev, &wake);
5252
5253         if (system_state == SYSTEM_POWER_OFF) {
5254                 pci_wake_from_d3(pdev, wake);
5255                 pci_set_power_state(pdev, PCI_D3hot);
5256         }
5257 }
5258
5259 #ifdef CONFIG_NET_POLL_CONTROLLER
5260 /*
5261  * Polling 'interrupt' - used by things like netconsole to send skbs
5262  * without having to re-enable interrupts. It's not called while
5263  * the interrupt routine is executing.
5264  */
5265 static void igb_netpoll(struct net_device *netdev)
5266 {
5267         struct igb_adapter *adapter = netdev_priv(netdev);
5268         struct e1000_hw *hw = &adapter->hw;
5269         int i;
5270
5271         if (!adapter->msix_entries) {
5272                 igb_irq_disable(adapter);
5273                 napi_schedule(&adapter->rx_ring[0].napi);
5274                 return;
5275         }
5276
5277         for (i = 0; i < adapter->num_tx_queues; i++) {
5278                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5279                 wr32(E1000_EIMC, tx_ring->eims_value);
5280                 igb_clean_tx_irq(tx_ring);
5281                 wr32(E1000_EIMS, tx_ring->eims_value);
5282         }
5283
5284         for (i = 0; i < adapter->num_rx_queues; i++) {
5285                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5286                 wr32(E1000_EIMC, rx_ring->eims_value);
5287                 napi_schedule(&rx_ring->napi);
5288         }
5289 }
5290 #endif /* CONFIG_NET_POLL_CONTROLLER */
5291
5292 /**
5293  * igb_io_error_detected - called when PCI error is detected
5294  * @pdev: Pointer to PCI device
5295  * @state: The current pci connection state
5296  *
5297  * This function is called after a PCI bus error affecting
5298  * this device has been detected.
5299  */
5300 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5301                                               pci_channel_state_t state)
5302 {
5303         struct net_device *netdev = pci_get_drvdata(pdev);
5304         struct igb_adapter *adapter = netdev_priv(netdev);
5305
5306         netif_device_detach(netdev);
5307
5308         if (netif_running(netdev))
5309                 igb_down(adapter);
5310         pci_disable_device(pdev);
5311
5312         /* Request a slot slot reset. */
5313         return PCI_ERS_RESULT_NEED_RESET;
5314 }
5315
5316 /**
5317  * igb_io_slot_reset - called after the pci bus has been reset.
5318  * @pdev: Pointer to PCI device
5319  *
5320  * Restart the card from scratch, as if from a cold-boot. Implementation
5321  * resembles the first-half of the igb_resume routine.
5322  */
5323 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5324 {
5325         struct net_device *netdev = pci_get_drvdata(pdev);
5326         struct igb_adapter *adapter = netdev_priv(netdev);
5327         struct e1000_hw *hw = &adapter->hw;
5328         pci_ers_result_t result;
5329         int err;
5330
5331         if (pci_enable_device_mem(pdev)) {
5332                 dev_err(&pdev->dev,
5333                         "Cannot re-enable PCI device after reset.\n");
5334                 result = PCI_ERS_RESULT_DISCONNECT;
5335         } else {
5336                 pci_set_master(pdev);
5337                 pci_restore_state(pdev);
5338
5339                 pci_enable_wake(pdev, PCI_D3hot, 0);
5340                 pci_enable_wake(pdev, PCI_D3cold, 0);
5341
5342                 igb_reset(adapter);
5343                 wr32(E1000_WUS, ~0);
5344                 result = PCI_ERS_RESULT_RECOVERED;
5345         }
5346
5347         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5348         if (err) {
5349                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5350                         "failed 0x%0x\n", err);
5351                 /* non-fatal, continue */
5352         }
5353
5354         return result;
5355 }
5356
5357 /**
5358  * igb_io_resume - called when traffic can start flowing again.
5359  * @pdev: Pointer to PCI device
5360  *
5361  * This callback is called when the error recovery driver tells us that
5362  * its OK to resume normal operation. Implementation resembles the
5363  * second-half of the igb_resume routine.
5364  */
5365 static void igb_io_resume(struct pci_dev *pdev)
5366 {
5367         struct net_device *netdev = pci_get_drvdata(pdev);
5368         struct igb_adapter *adapter = netdev_priv(netdev);
5369
5370         if (netif_running(netdev)) {
5371                 if (igb_up(adapter)) {
5372                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5373                         return;
5374                 }
5375         }
5376
5377         netif_device_attach(netdev);
5378
5379         /* let the f/w know that the h/w is now under the control of the
5380          * driver. */
5381         igb_get_hw_control(adapter);
5382 }
5383
5384 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5385 {
5386         u32 reg_data;
5387
5388         reg_data = rd32(E1000_VMOLR(vfn));
5389         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5390                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5391                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5392                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5393                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5394         wr32(E1000_VMOLR(vfn), reg_data);
5395 }
5396
5397 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5398                                  int vfn)
5399 {
5400         struct e1000_hw *hw = &adapter->hw;
5401         u32 vmolr;
5402
5403         vmolr = rd32(E1000_VMOLR(vfn));
5404         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5405         vmolr |= size | E1000_VMOLR_LPE;
5406         wr32(E1000_VMOLR(vfn), vmolr);
5407
5408         return 0;
5409 }
5410
5411 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5412 {
5413         u32 reg_data;
5414
5415         reg_data = rd32(E1000_RAH(entry));
5416         reg_data &= ~E1000_RAH_POOL_MASK;
5417         reg_data |= E1000_RAH_POOL_1 << pool;;
5418         wr32(E1000_RAH(entry), reg_data);
5419 }
5420
5421 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5422                                   int entry_count, u16 total_rar_filters)
5423 {
5424         struct e1000_hw *hw = &adapter->hw;
5425         int i = adapter->vfs_allocated_count + 1;
5426
5427         if ((i + entry_count) < total_rar_filters)
5428                 total_rar_filters = i + entry_count;
5429
5430         for (; i < total_rar_filters; i++)
5431                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5432 }
5433
5434 static int igb_set_vf_mac(struct igb_adapter *adapter,
5435                           int vf, unsigned char *mac_addr)
5436 {
5437         struct e1000_hw *hw = &adapter->hw;
5438         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5439
5440         igb_rar_set(hw, mac_addr, rar_entry);
5441
5442         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5443
5444         igb_set_rah_pool(hw, vf, rar_entry);
5445
5446         return 0;
5447 }
5448
5449 static void igb_vmm_control(struct igb_adapter *adapter)
5450 {
5451         struct e1000_hw *hw = &adapter->hw;
5452         u32 reg_data;
5453
5454         if (!adapter->vfs_allocated_count)
5455                 return;
5456
5457         /* VF's need PF reset indication before they
5458          * can send/receive mail */
5459         reg_data = rd32(E1000_CTRL_EXT);
5460         reg_data |= E1000_CTRL_EXT_PFRSTD;
5461         wr32(E1000_CTRL_EXT, reg_data);
5462
5463         igb_vmdq_set_loopback_pf(hw, true);
5464         igb_vmdq_set_replication_pf(hw, true);
5465 }
5466
5467 /* igb_main.c */