drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 #ifdef CONFIG_PM
 139 static int igb_suspend(struct pci_dev *, pm_message_t);
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155 #ifdef CONFIG_PCI_IOV
 156 static unsigned int max_vfs = 0;
 157 module_param(max_vfs, uint, 0);
 158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 159                  "per physical function");
 160 #endif /* CONFIG_PCI_IOV */
 161
 162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 163                      pci_channel_state_t);
 164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 165 static void igb_io_resume(struct pci_dev *);
 166
 167 static struct pci_error_handlers igb_err_handler = {
 168         .error_detected = igb_io_error_detected,
 169         .slot_reset = igb_io_slot_reset,
 170         .resume = igb_io_resume,
 171 };
 172
 173
 174 static struct pci_driver igb_driver = {
 175         .name     = igb_driver_name,
 176         .id_table = igb_pci_tbl,
 177         .probe    = igb_probe,
 178         .remove   = __devexit_p(igb_remove),
 179 #ifdef CONFIG_PM
 180         /* Power Managment Hooks */
 181         .suspend  = igb_suspend,
 182         .resume   = igb_resume,
 183 #endif
 184         .shutdown = igb_shutdown,
 185         .err_handler = &igb_err_handler
 186 };
 187
 188 static int global_quad_port_a; /* global quad port a indication */
 189
 190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 192 MODULE_LICENSE("GPL");
 193 MODULE_VERSION(DRV_VERSION);
 194
 195 /**
 196  * Scale the NIC clock cycle by a large factor so that
 197  * relatively small clock corrections can be added or
 198  * substracted at each clock tick. The drawbacks of a
 199  * large factor are a) that the clock register overflows
 200  * more quickly (not such a big deal) and b) that the
 201  * increment per tick has to fit into 24 bits.
 202  *
 203  * Note that
 204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 205  *             IGB_TSYNC_SCALE
 206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 207  *
 208  * The base scale factor is intentionally a power of two
 209  * so that the division in %struct timecounter can be done with
 210  * a shift.
 211  */
 212 #define IGB_TSYNC_SHIFT (19)
 213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 214
 215 /**
 216  * The duration of one clock cycle of the NIC.
 217  *
 218  * @todo This hard-coded value is part of the specification and might change
 219  * in future hardware revisions. Add revision check.
 220  */
 221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 222
 223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 225 #endif
 226
 227 /**
 228  * igb_read_clock - read raw cycle counter (to be used by time counter)
 229  */
 230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 231 {
 232         struct igb_adapter *adapter =
 233                 container_of(tc, struct igb_adapter, cycles);
 234         struct e1000_hw *hw = &adapter->hw;
 235         u64 stamp;
 236
 237         stamp =  rd32(E1000_SYSTIML);
 238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 239
 240         return stamp;
 241 }
 242
 243 #ifdef DEBUG
 244 /**
 245  * igb_get_hw_dev_name - return device name string
 246  * used by hardware layer to print debugging information
 247  **/
 248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 249 {
 250         struct igb_adapter *adapter = hw->back;
 251         return adapter->netdev->name;
 252 }
 253
 254 /**
 255  * igb_get_time_str - format current NIC and system time as string
 256  */
 257 static char *igb_get_time_str(struct igb_adapter *adapter,
 258                               char buffer[160])
 259 {
 260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 262         struct timespec sys;
 263         struct timespec delta;
 264         getnstimeofday(&sys);
 265
 266         delta = timespec_sub(nic, sys);
 267
 268         sprintf(buffer,
 269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 270                 hw,
 271                 (long)nic.tv_sec, nic.tv_nsec,
 272                 (long)sys.tv_sec, sys.tv_nsec,
 273                 (long)delta.tv_sec, delta.tv_nsec);
 274
 275         return buffer;
 276 }
 277 #endif
 278
 279 /**
 280  * igb_desc_unused - calculate if we have unused descriptors
 281  **/
 282 static int igb_desc_unused(struct igb_ring *ring)
 283 {
 284         if (ring->next_to_clean > ring->next_to_use)
 285                 return ring->next_to_clean - ring->next_to_use - 1;
 286
 287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 288 }
 289
 290 /**
 291  * igb_init_module - Driver Registration Routine
 292  *
 293  * igb_init_module is the first routine called when the driver is
 294  * loaded. All it does is register with the PCI subsystem.
 295  **/
 296 static int __init igb_init_module(void)
 297 {
 298         int ret;
 299         printk(KERN_INFO "%s - version %s\n",
 300                igb_driver_string, igb_driver_version);
 301
 302         printk(KERN_INFO "%s\n", igb_copyright);
 303
 304         global_quad_port_a = 0;
 305
 306 #ifdef CONFIG_IGB_DCA
 307         dca_register_notify(&dca_notifier);
 308 #endif
 309
 310         ret = pci_register_driver(&igb_driver);
 311         return ret;
 312 }
 313
 314 module_init(igb_init_module);
 315
 316 /**
 317  * igb_exit_module - Driver Exit Cleanup Routine
 318  *
 319  * igb_exit_module is called just before the driver is removed
 320  * from memory.
 321  **/
 322 static void __exit igb_exit_module(void)
 323 {
 324 #ifdef CONFIG_IGB_DCA
 325         dca_unregister_notify(&dca_notifier);
 326 #endif
 327         pci_unregister_driver(&igb_driver);
 328 }
 329
 330 module_exit(igb_exit_module);
 331
 332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 333 /**
 334  * igb_cache_ring_register - Descriptor ring to register mapping
 335  * @adapter: board private structure to initialize
 336  *
 337  * Once we know the feature-set enabled for the device, we'll cache
 338  * the register offset the descriptor ring is assigned to.
 339  **/
 340 static void igb_cache_ring_register(struct igb_adapter *adapter)
 341 {
 342         int i;
 343         unsigned int rbase_offset = adapter->vfs_allocated_count;
 344
 345         switch (adapter->hw.mac.type) {
 346         case e1000_82576:
 347                 /* The queues are allocated for virtualization such that VF 0
 348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 349                  * In order to avoid collision we start at the first free queue
 350                  * and continue consuming queues in the same sequence
 351                  */
 352                 for (i = 0; i < adapter->num_rx_queues; i++)
 353                         adapter->rx_ring[i].reg_idx = rbase_offset +
 354                                                       Q_IDX_82576(i);
 355                 for (i = 0; i < adapter->num_tx_queues; i++)
 356                         adapter->tx_ring[i].reg_idx = rbase_offset +
 357                                                       Q_IDX_82576(i);
 358                 break;
 359         case e1000_82575:
 360         default:
 361                 for (i = 0; i < adapter->num_rx_queues; i++)
 362                         adapter->rx_ring[i].reg_idx = i;
 363                 for (i = 0; i < adapter->num_tx_queues; i++)
 364                         adapter->tx_ring[i].reg_idx = i;
 365                 break;
 366         }
 367 }
 368
 369 /**
 370  * igb_alloc_queues - Allocate memory for all rings
 371  * @adapter: board private structure to initialize
 372  *
 373  * We allocate one ring per queue at run-time since we don't know the
 374  * number of queues at compile-time.
 375  **/
 376 static int igb_alloc_queues(struct igb_adapter *adapter)
 377 {
 378         int i;
 379
 380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 381                                    sizeof(struct igb_ring), GFP_KERNEL);
 382         if (!adapter->tx_ring)
 383                 return -ENOMEM;
 384
 385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 386                                    sizeof(struct igb_ring), GFP_KERNEL);
 387         if (!adapter->rx_ring) {
 388                 kfree(adapter->tx_ring);
 389                 return -ENOMEM;
 390         }
 391
 392         adapter->rx_ring->buddy = adapter->tx_ring;
 393
 394         for (i = 0; i < adapter->num_tx_queues; i++) {
 395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 396                 ring->count = adapter->tx_ring_count;
 397                 ring->adapter = adapter;
 398                 ring->queue_index = i;
 399         }
 400         for (i = 0; i < adapter->num_rx_queues; i++) {
 401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 402                 ring->count = adapter->rx_ring_count;
 403                 ring->adapter = adapter;
 404                 ring->queue_index = i;
 405                 ring->itr_register = E1000_ITR;
 406
 407                 /* set a default napi handler for each rx_ring */
 408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 409         }
 410
 411         igb_cache_ring_register(adapter);
 412         return 0;
 413 }
 414
 415 static void igb_free_queues(struct igb_adapter *adapter)
 416 {
 417         int i;
 418
 419         for (i = 0; i < adapter->num_rx_queues; i++)
 420                 netif_napi_del(&adapter->rx_ring[i].napi);
 421
 422         adapter->num_rx_queues = 0;
 423         adapter->num_tx_queues = 0;
 424
 425         kfree(adapter->tx_ring);
 426         kfree(adapter->rx_ring);
 427 }
 428
 429 #define IGB_N0_QUEUE -1
 430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 431                               int tx_queue, int msix_vector)
 432 {
 433         u32 msixbm = 0;
 434         struct e1000_hw *hw = &adapter->hw;
 435         u32 ivar, index;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 /* The 82575 assigns vectors using a bitmask, which matches the
 440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 441                    or more queues to a vector, we write the appropriate bits
 442                    into the MSIXBM register for that vector. */
 443                 if (rx_queue > IGB_N0_QUEUE) {
 444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 446                 }
 447                 if (tx_queue > IGB_N0_QUEUE) {
 448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 449                         adapter->tx_ring[tx_queue].eims_value =
 450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 451                 }
 452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 453                 break;
 454         case e1000_82576:
 455                 /* 82576 uses a table-based method for assigning vectors.
 456                    Each queue has a single entry in the table to which we write
 457                    a vector number along with a "valid" bit.  Sadly, the layout
 458                    of the table is somewhat counterintuitive. */
 459                 if (rx_queue > IGB_N0_QUEUE) {
 460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 461                         ivar = array_rd32(E1000_IVAR0, index);
 462                         if (rx_queue & 0x1) {
 463                                 /* vector goes into third byte of register */
 464                                 ivar = ivar & 0xFF00FFFF;
 465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 466                         } else {
 467                                 /* vector goes into low byte of register */
 468                                 ivar = ivar & 0xFFFFFF00;
 469                                 ivar |= msix_vector | E1000_IVAR_VALID;
 470                         }
 471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 472                         array_wr32(E1000_IVAR0, index, ivar);
 473                 }
 474                 if (tx_queue > IGB_N0_QUEUE) {
 475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 476                         ivar = array_rd32(E1000_IVAR0, index);
 477                         if (tx_queue & 0x1) {
 478                                 /* vector goes into high byte of register */
 479                                 ivar = ivar & 0x00FFFFFF;
 480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 481                         } else {
 482                                 /* vector goes into second byte of register */
 483                                 ivar = ivar & 0xFFFF00FF;
 484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 485                         }
 486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 487                         array_wr32(E1000_IVAR0, index, ivar);
 488                 }
 489                 break;
 490         default:
 491                 BUG();
 492                 break;
 493         }
 494 }
 495
 496 /**
 497  * igb_configure_msix - Configure MSI-X hardware
 498  *
 499  * igb_configure_msix sets up the hardware to properly
 500  * generate MSI-X interrupts.
 501  **/
 502 static void igb_configure_msix(struct igb_adapter *adapter)
 503 {
 504         u32 tmp;
 505         int i, vector = 0;
 506         struct e1000_hw *hw = &adapter->hw;
 507
 508         adapter->eims_enable_mask = 0;
 509         if (hw->mac.type == e1000_82576)
 510                 /* Turn on MSI-X capability first, or our settings
 511                  * won't stick.  And it will take days to debug. */
 512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 514                                    E1000_GPIE_NSICR);
 515
 516         for (i = 0; i < adapter->num_tx_queues; i++) {
 517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 519                 adapter->eims_enable_mask |= tx_ring->eims_value;
 520                 if (tx_ring->itr_val)
 521                         writel(tx_ring->itr_val,
 522                                hw->hw_addr + tx_ring->itr_register);
 523                 else
 524                         writel(1, hw->hw_addr + tx_ring->itr_register);
 525         }
 526
 527         for (i = 0; i < adapter->num_rx_queues; i++) {
 528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 529                 rx_ring->buddy = NULL;
 530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 531                 adapter->eims_enable_mask |= rx_ring->eims_value;
 532                 if (rx_ring->itr_val)
 533                         writel(rx_ring->itr_val,
 534                                hw->hw_addr + rx_ring->itr_register);
 535                 else
 536                         writel(1, hw->hw_addr + rx_ring->itr_register);
 537         }
 538
 539
 540         /* set vector for other causes, i.e. link changes */
 541         switch (hw->mac.type) {
 542         case e1000_82575:
 543                 array_wr32(E1000_MSIXBM(0), vector++,
 544                                       E1000_EIMS_OTHER);
 545
 546                 tmp = rd32(E1000_CTRL_EXT);
 547                 /* enable MSI-X PBA support*/
 548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 549
 550                 /* Auto-Mask interrupts upon ICR read. */
 551                 tmp |= E1000_CTRL_EXT_EIAME;
 552                 tmp |= E1000_CTRL_EXT_IRCA;
 553
 554                 wr32(E1000_CTRL_EXT, tmp);
 555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 556                 adapter->eims_other = E1000_EIMS_OTHER;
 557
 558                 break;
 559
 560         case e1000_82576:
 561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 562                 wr32(E1000_IVAR_MISC, tmp);
 563
 564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 565                 adapter->eims_other = 1 << (vector - 1);
 566                 break;
 567         default:
 568                 /* do nothing, since nothing else supports MSI-X */
 569                 break;
 570         } /* switch (hw->mac.type) */
 571         wrfl();
 572 }
 573
 574 /**
 575  * igb_request_msix - Initialize MSI-X interrupts
 576  *
 577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 578  * kernel.
 579  **/
 580 static int igb_request_msix(struct igb_adapter *adapter)
 581 {
 582         struct net_device *netdev = adapter->netdev;
 583         int i, err = 0, vector = 0;
 584
 585         vector = 0;
 586
 587         for (i = 0; i < adapter->num_tx_queues; i++) {
 588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 590                 err = request_irq(adapter->msix_entries[vector].vector,
 591                                   &igb_msix_tx, 0, ring->name,
 592                                   &(adapter->tx_ring[i]));
 593                 if (err)
 594                         goto out;
 595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 596                 ring->itr_val = 976; /* ~4000 ints/sec */
 597                 vector++;
 598         }
 599         for (i = 0; i < adapter->num_rx_queues; i++) {
 600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 603                 else
 604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 605                 err = request_irq(adapter->msix_entries[vector].vector,
 606                                   &igb_msix_rx, 0, ring->name,
 607                                   &(adapter->rx_ring[i]));
 608                 if (err)
 609                         goto out;
 610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 611                 ring->itr_val = adapter->itr;
 612                 vector++;
 613         }
 614
 615         err = request_irq(adapter->msix_entries[vector].vector,
 616                           &igb_msix_other, 0, netdev->name, netdev);
 617         if (err)
 618                 goto out;
 619
 620         igb_configure_msix(adapter);
 621         return 0;
 622 out:
 623         return err;
 624 }
 625
 626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 627 {
 628         if (adapter->msix_entries) {
 629                 pci_disable_msix(adapter->pdev);
 630                 kfree(adapter->msix_entries);
 631                 adapter->msix_entries = NULL;
 632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 633                 pci_disable_msi(adapter->pdev);
 634         return;
 635 }
 636
 637
 638 /**
 639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 640  *
 641  * Attempt to configure interrupts using the best available
 642  * capabilities of the hardware and kernel.
 643  **/
 644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 645 {
 646         int err;
 647         int numvecs, i;
 648
 649         /* Number of supported queues. */
 650         /* Having more queues than CPUs doesn't make sense. */
 651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 653
 654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 656                                         GFP_KERNEL);
 657         if (!adapter->msix_entries)
 658                 goto msi_only;
 659
 660         for (i = 0; i < numvecs; i++)
 661                 adapter->msix_entries[i].entry = i;
 662
 663         err = pci_enable_msix(adapter->pdev,
 664                               adapter->msix_entries,
 665                               numvecs);
 666         if (err == 0)
 667                 goto out;
 668
 669         igb_reset_interrupt_capability(adapter);
 670
 671         /* If we can't do MSI-X, try MSI */
 672 msi_only:
 673 #ifdef CONFIG_PCI_IOV
 674         /* disable SR-IOV for non MSI-X configurations */
 675         if (adapter->vf_data) {
 676                 struct e1000_hw *hw = &adapter->hw;
 677                 /* disable iov and allow time for transactions to clear */
 678                 pci_disable_sriov(adapter->pdev);
 679                 msleep(500);
 680
 681                 kfree(adapter->vf_data);
 682                 adapter->vf_data = NULL;
 683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 684                 msleep(100);
 685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 686         }
 687 #endif
 688         adapter->num_rx_queues = 1;
 689         adapter->num_tx_queues = 1;
 690         if (!pci_enable_msi(adapter->pdev))
 691                 adapter->flags |= IGB_FLAG_HAS_MSI;
 692 out:
 693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 695         return;
 696 }
 697
 698 /**
 699  * igb_request_irq - initialize interrupts
 700  *
 701  * Attempts to configure interrupts using the best available
 702  * capabilities of the hardware and kernel.
 703  **/
 704 static int igb_request_irq(struct igb_adapter *adapter)
 705 {
 706         struct net_device *netdev = adapter->netdev;
 707         struct e1000_hw *hw = &adapter->hw;
 708         int err = 0;
 709
 710         if (adapter->msix_entries) {
 711                 err = igb_request_msix(adapter);
 712                 if (!err)
 713                         goto request_done;
 714                 /* fall back to MSI */
 715                 igb_reset_interrupt_capability(adapter);
 716                 if (!pci_enable_msi(adapter->pdev))
 717                         adapter->flags |= IGB_FLAG_HAS_MSI;
 718                 igb_free_all_tx_resources(adapter);
 719                 igb_free_all_rx_resources(adapter);
 720                 adapter->num_rx_queues = 1;
 721                 igb_alloc_queues(adapter);
 722         } else {
 723                 switch (hw->mac.type) {
 724                 case e1000_82575:
 725                         wr32(E1000_MSIXBM(0),
 726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 727                         break;
 728                 case e1000_82576:
 729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 730                         break;
 731                 default:
 732                         break;
 733                 }
 734         }
 735
 736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 738                                   netdev->name, netdev);
 739                 if (!err)
 740                         goto request_done;
 741                 /* fall back to legacy interrupts */
 742                 igb_reset_interrupt_capability(adapter);
 743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 744         }
 745
 746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 747                           netdev->name, netdev);
 748
 749         if (err)
 750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 751                         err);
 752
 753 request_done:
 754         return err;
 755 }
 756
 757 static void igb_free_irq(struct igb_adapter *adapter)
 758 {
 759         struct net_device *netdev = adapter->netdev;
 760
 761         if (adapter->msix_entries) {
 762                 int vector = 0, i;
 763
 764                 for (i = 0; i < adapter->num_tx_queues; i++)
 765                         free_irq(adapter->msix_entries[vector++].vector,
 766                                 &(adapter->tx_ring[i]));
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         free_irq(adapter->msix_entries[vector++].vector,
 769                                 &(adapter->rx_ring[i]));
 770
 771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 772                 return;
 773         }
 774
 775         free_irq(adapter->pdev->irq, netdev);
 776 }
 777
 778 /**
 779  * igb_irq_disable - Mask off interrupt generation on the NIC
 780  * @adapter: board private structure
 781  **/
 782 static void igb_irq_disable(struct igb_adapter *adapter)
 783 {
 784         struct e1000_hw *hw = &adapter->hw;
 785
 786         if (adapter->msix_entries) {
 787                 wr32(E1000_EIAM, 0);
 788                 wr32(E1000_EIMC, ~0);
 789                 wr32(E1000_EIAC, 0);
 790         }
 791
 792         wr32(E1000_IAM, 0);
 793         wr32(E1000_IMC, ~0);
 794         wrfl();
 795         synchronize_irq(adapter->pdev->irq);
 796 }
 797
 798 /**
 799  * igb_irq_enable - Enable default interrupt generation settings
 800  * @adapter: board private structure
 801  **/
 802 static void igb_irq_enable(struct igb_adapter *adapter)
 803 {
 804         struct e1000_hw *hw = &adapter->hw;
 805
 806         if (adapter->msix_entries) {
 807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 810                 if (adapter->vfs_allocated_count)
 811                         wr32(E1000_MBVFIMR, 0xFF);
 812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 813                                  E1000_IMS_DOUTSYNC));
 814         } else {
 815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 817         }
 818 }
 819
 820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 821 {
 822         struct net_device *netdev = adapter->netdev;
 823         u16 vid = adapter->hw.mng_cookie.vlan_id;
 824         u16 old_vid = adapter->mng_vlan_id;
 825         if (adapter->vlgrp) {
 826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 827                         if (adapter->hw.mng_cookie.status &
 828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 829                                 igb_vlan_rx_add_vid(netdev, vid);
 830                                 adapter->mng_vlan_id = vid;
 831                         } else
 832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 833
 834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 835                                         (vid != old_vid) &&
 836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 838                 } else
 839                         adapter->mng_vlan_id = vid;
 840         }
 841 }
 842
 843 /**
 844  * igb_release_hw_control - release control of the h/w to f/w
 845  * @adapter: address of board private structure
 846  *
 847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 848  * For ASF and Pass Through versions of f/w this means that the
 849  * driver is no longer loaded.
 850  *
 851  **/
 852 static void igb_release_hw_control(struct igb_adapter *adapter)
 853 {
 854         struct e1000_hw *hw = &adapter->hw;
 855         u32 ctrl_ext;
 856
 857         /* Let firmware take over control of h/w */
 858         ctrl_ext = rd32(E1000_CTRL_EXT);
 859         wr32(E1000_CTRL_EXT,
 860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 861 }
 862
 863
 864 /**
 865  * igb_get_hw_control - get control of the h/w from f/w
 866  * @adapter: address of board private structure
 867  *
 868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 869  * For ASF and Pass Through versions of f/w this means that
 870  * the driver is loaded.
 871  *
 872  **/
 873 static void igb_get_hw_control(struct igb_adapter *adapter)
 874 {
 875         struct e1000_hw *hw = &adapter->hw;
 876         u32 ctrl_ext;
 877
 878         /* Let firmware know the driver has taken over */
 879         ctrl_ext = rd32(E1000_CTRL_EXT);
 880         wr32(E1000_CTRL_EXT,
 881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 882 }
 883
 884 /**
 885  * igb_configure - configure the hardware for RX and TX
 886  * @adapter: private board structure
 887  **/
 888 static void igb_configure(struct igb_adapter *adapter)
 889 {
 890         struct net_device *netdev = adapter->netdev;
 891         int i;
 892
 893         igb_get_hw_control(adapter);
 894         igb_set_multi(netdev);
 895
 896         igb_restore_vlan(adapter);
 897
 898         igb_configure_tx(adapter);
 899         igb_setup_rctl(adapter);
 900         igb_configure_rx(adapter);
 901
 902         igb_rx_fifo_flush_82575(&adapter->hw);
 903
 904         /* call igb_desc_unused which always leaves
 905          * at least 1 descriptor unused to make sure
 906          * next_to_use != next_to_clean */
 907         for (i = 0; i < adapter->num_rx_queues; i++) {
 908                 struct igb_ring *ring = &adapter->rx_ring[i];
 909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 910         }
 911
 912
 913         adapter->tx_queue_len = netdev->tx_queue_len;
 914 }
 915
 916
 917 /**
 918  * igb_up - Open the interface and prepare it to handle traffic
 919  * @adapter: board private structure
 920  **/
 921
 922 int igb_up(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         int i;
 926
 927         /* hardware has been reset, we need to reload some things */
 928         igb_configure(adapter);
 929
 930         clear_bit(__IGB_DOWN, &adapter->state);
 931
 932         for (i = 0; i < adapter->num_rx_queues; i++)
 933                 napi_enable(&adapter->rx_ring[i].napi);
 934         if (adapter->msix_entries)
 935                 igb_configure_msix(adapter);
 936
 937         igb_vmm_control(adapter);
 938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 940
 941         /* Clear any pending interrupts. */
 942         rd32(E1000_ICR);
 943         igb_irq_enable(adapter);
 944
 945         netif_tx_start_all_queues(adapter->netdev);
 946
 947         /* Fire a link change interrupt to start the watchdog. */
 948         wr32(E1000_ICS, E1000_ICS_LSC);
 949         return 0;
 950 }
 951
 952 void igb_down(struct igb_adapter *adapter)
 953 {
 954         struct e1000_hw *hw = &adapter->hw;
 955         struct net_device *netdev = adapter->netdev;
 956         u32 tctl, rctl;
 957         int i;
 958
 959         /* signal that we're down so the interrupt handler does not
 960          * reschedule our watchdog timer */
 961         set_bit(__IGB_DOWN, &adapter->state);
 962
 963         /* disable receives in the hardware */
 964         rctl = rd32(E1000_RCTL);
 965         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 966         /* flush and sleep below */
 967
 968         netif_tx_stop_all_queues(netdev);
 969
 970         /* disable transmits in the hardware */
 971         tctl = rd32(E1000_TCTL);
 972         tctl &= ~E1000_TCTL_EN;
 973         wr32(E1000_TCTL, tctl);
 974         /* flush both disables and wait for them to finish */
 975         wrfl();
 976         msleep(10);
 977
 978         for (i = 0; i < adapter->num_rx_queues; i++)
 979                 napi_disable(&adapter->rx_ring[i].napi);
 980
 981         igb_irq_disable(adapter);
 982
 983         del_timer_sync(&adapter->watchdog_timer);
 984         del_timer_sync(&adapter->phy_info_timer);
 985
 986         netdev->tx_queue_len = adapter->tx_queue_len;
 987         netif_carrier_off(netdev);
 988
 989         /* record the stats before reset*/
 990         igb_update_stats(adapter);
 991
 992         adapter->link_speed = 0;
 993         adapter->link_duplex = 0;
 994
 995         if (!pci_channel_offline(adapter->pdev))
 996                 igb_reset(adapter);
 997         igb_clean_all_tx_rings(adapter);
 998         igb_clean_all_rx_rings(adapter);
 999 }
1000
1001 void igb_reinit_locked(struct igb_adapter *adapter)
1002 {
1003         WARN_ON(in_interrupt());
1004         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1005                 msleep(1);
1006         igb_down(adapter);
1007         igb_up(adapter);
1008         clear_bit(__IGB_RESETTING, &adapter->state);
1009 }
1010
1011 void igb_reset(struct igb_adapter *adapter)
1012 {
1013         struct e1000_hw *hw = &adapter->hw;
1014         struct e1000_mac_info *mac = &hw->mac;
1015         struct e1000_fc_info *fc = &hw->fc;
1016         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1017         u16 hwm;
1018
1019         /* Repartition Pba for greater than 9k mtu
1020          * To take effect CTRL.RST is required.
1021          */
1022         switch (mac->type) {
1023         case e1000_82576:
1024                 pba = E1000_PBA_64K;
1025                 break;
1026         case e1000_82575:
1027         default:
1028                 pba = E1000_PBA_34K;
1029                 break;
1030         }
1031
1032         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1033             (mac->type < e1000_82576)) {
1034                 /* adjust PBA for jumbo frames */
1035                 wr32(E1000_PBA, pba);
1036
1037                 /* To maintain wire speed transmits, the Tx FIFO should be
1038                  * large enough to accommodate two full transmit packets,
1039                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1040                  * the Rx FIFO should be large enough to accommodate at least
1041                  * one full receive packet and is similarly rounded up and
1042                  * expressed in KB. */
1043                 pba = rd32(E1000_PBA);
1044                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1045                 tx_space = pba >> 16;
1046                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1047                 pba &= 0xffff;
1048                 /* the tx fifo also stores 16 bytes of information about the tx
1049                  * but don't include ethernet FCS because hardware appends it */
1050                 min_tx_space = (adapter->max_frame_size +
1051                                 sizeof(union e1000_adv_tx_desc) -
1052                                 ETH_FCS_LEN) * 2;
1053                 min_tx_space = ALIGN(min_tx_space, 1024);
1054                 min_tx_space >>= 10;
1055                 /* software strips receive CRC, so leave room for it */
1056                 min_rx_space = adapter->max_frame_size;
1057                 min_rx_space = ALIGN(min_rx_space, 1024);
1058                 min_rx_space >>= 10;
1059
1060                 /* If current Tx allocation is less than the min Tx FIFO size,
1061                  * and the min Tx FIFO size is less than the current Rx FIFO
1062                  * allocation, take space away from current Rx allocation */
1063                 if (tx_space < min_tx_space &&
1064                     ((min_tx_space - tx_space) < pba)) {
1065                         pba = pba - (min_tx_space - tx_space);
1066
1067                         /* if short on rx space, rx wins and must trump tx
1068                          * adjustment */
1069                         if (pba < min_rx_space)
1070                                 pba = min_rx_space;
1071                 }
1072                 wr32(E1000_PBA, pba);
1073         }
1074
1075         /* flow control settings */
1076         /* The high water mark must be low enough to fit one full frame
1077          * (or the size used for early receive) above it in the Rx FIFO.
1078          * Set it to the lower of:
1079          * - 90% of the Rx FIFO size, or
1080          * - the full Rx FIFO size minus one full frame */
1081         hwm = min(((pba << 10) * 9 / 10),
1082                         ((pba << 10) - 2 * adapter->max_frame_size));
1083
1084         if (mac->type < e1000_82576) {
1085                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1086                 fc->low_water = fc->high_water - 8;
1087         } else {
1088                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1089                 fc->low_water = fc->high_water - 16;
1090         }
1091         fc->pause_time = 0xFFFF;
1092         fc->send_xon = 1;
1093         fc->type = fc->original_type;
1094
1095         /* disable receive for all VFs and wait one second */
1096         if (adapter->vfs_allocated_count) {
1097                 int i;
1098                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1099                         adapter->vf_data[i].clear_to_send = false;
1100
1101                 /* ping all the active vfs to let them know we are going down */
1102                         igb_ping_all_vfs(adapter);
1103
1104                 /* disable transmits and receives */
1105                 wr32(E1000_VFRE, 0);
1106                 wr32(E1000_VFTE, 0);
1107         }
1108
1109         /* Allow time for pending master requests to run */
1110         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1111         wr32(E1000_WUC, 0);
1112
1113         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1114                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1115
1116         igb_update_mng_vlan(adapter);
1117
1118         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1119         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1120
1121         igb_reset_adaptive(&adapter->hw);
1122         igb_get_phy_info(&adapter->hw);
1123 }
1124
1125 static const struct net_device_ops igb_netdev_ops = {
1126         .ndo_open               = igb_open,
1127         .ndo_stop               = igb_close,
1128         .ndo_start_xmit         = igb_xmit_frame_adv,
1129         .ndo_get_stats          = igb_get_stats,
1130         .ndo_set_multicast_list = igb_set_multi,
1131         .ndo_set_mac_address    = igb_set_mac,
1132         .ndo_change_mtu         = igb_change_mtu,
1133         .ndo_do_ioctl           = igb_ioctl,
1134         .ndo_tx_timeout         = igb_tx_timeout,
1135         .ndo_validate_addr      = eth_validate_addr,
1136         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1137         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1138         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1139 #ifdef CONFIG_NET_POLL_CONTROLLER
1140         .ndo_poll_controller    = igb_netpoll,
1141 #endif
1142 };
1143
1144 /**
1145  * igb_probe - Device Initialization Routine
1146  * @pdev: PCI device information struct
1147  * @ent: entry in igb_pci_tbl
1148  *
1149  * Returns 0 on success, negative on failure
1150  *
1151  * igb_probe initializes an adapter identified by a pci_dev structure.
1152  * The OS initialization, configuring of the adapter private structure,
1153  * and a hardware reset occur.
1154  **/
1155 static int __devinit igb_probe(struct pci_dev *pdev,
1156                                const struct pci_device_id *ent)
1157 {
1158         struct net_device *netdev;
1159         struct igb_adapter *adapter;
1160         struct e1000_hw *hw;
1161         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1162         unsigned long mmio_start, mmio_len;
1163         int err, pci_using_dac;
1164         u16 eeprom_data = 0;
1165         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1166         u32 part_num;
1167
1168         err = pci_enable_device_mem(pdev);
1169         if (err)
1170                 return err;
1171
1172         pci_using_dac = 0;
1173         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1174         if (!err) {
1175                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1176                 if (!err)
1177                         pci_using_dac = 1;
1178         } else {
1179                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1180                 if (err) {
1181                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1182                         if (err) {
1183                                 dev_err(&pdev->dev, "No usable DMA "
1184                                         "configuration, aborting\n");
1185                                 goto err_dma;
1186                         }
1187                 }
1188         }
1189
1190         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1191                                            IORESOURCE_MEM),
1192                                            igb_driver_name);
1193         if (err)
1194                 goto err_pci_reg;
1195
1196         err = pci_enable_pcie_error_reporting(pdev);
1197         if (err) {
1198                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1199                         "0x%x\n", err);
1200                 /* non-fatal, continue */
1201         }
1202
1203         pci_set_master(pdev);
1204         pci_save_state(pdev);
1205
1206         err = -ENOMEM;
1207         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1208                                    IGB_ABS_MAX_TX_QUEUES);
1209         if (!netdev)
1210                 goto err_alloc_etherdev;
1211
1212         SET_NETDEV_DEV(netdev, &pdev->dev);
1213
1214         pci_set_drvdata(pdev, netdev);
1215         adapter = netdev_priv(netdev);
1216         adapter->netdev = netdev;
1217         adapter->pdev = pdev;
1218         hw = &adapter->hw;
1219         hw->back = adapter;
1220         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1221
1222         mmio_start = pci_resource_start(pdev, 0);
1223         mmio_len = pci_resource_len(pdev, 0);
1224
1225         err = -EIO;
1226         hw->hw_addr = ioremap(mmio_start, mmio_len);
1227         if (!hw->hw_addr)
1228                 goto err_ioremap;
1229
1230         netdev->netdev_ops = &igb_netdev_ops;
1231         igb_set_ethtool_ops(netdev);
1232         netdev->watchdog_timeo = 5 * HZ;
1233
1234         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1235
1236         netdev->mem_start = mmio_start;
1237         netdev->mem_end = mmio_start + mmio_len;
1238
1239         /* PCI config space info */
1240         hw->vendor_id = pdev->vendor;
1241         hw->device_id = pdev->device;
1242         hw->revision_id = pdev->revision;
1243         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1244         hw->subsystem_device_id = pdev->subsystem_device;
1245
1246         /* setup the private structure */
1247         hw->back = adapter;
1248         /* Copy the default MAC, PHY and NVM function pointers */
1249         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1250         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1251         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1252         /* Initialize skew-specific constants */
1253         err = ei->get_invariants(hw);
1254         if (err)
1255                 goto err_sw_init;
1256
1257 #ifdef CONFIG_PCI_IOV
1258         /* since iov functionality isn't critical to base device function we
1259          * can accept failure.  If it fails we don't allow iov to be enabled */
1260         if (hw->mac.type == e1000_82576) {
1261                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1262                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1263                 int i;
1264                 unsigned char mac_addr[ETH_ALEN];
1265
1266                 if (num_vfs) {
1267                         adapter->vf_data = kcalloc(num_vfs,
1268                                                 sizeof(struct vf_data_storage),
1269                                                 GFP_KERNEL);
1270                         if (!adapter->vf_data) {
1271                                 dev_err(&pdev->dev,
1272                                         "Could not allocate VF private data - "
1273                                         "IOV enable failed\n");
1274                         } else {
1275                                 err = pci_enable_sriov(pdev, num_vfs);
1276                                 if (!err) {
1277                                         adapter->vfs_allocated_count = num_vfs;
1278                                         dev_info(&pdev->dev,
1279                                                  "%d vfs allocated\n",
1280                                                  num_vfs);
1281                                         for (i = 0;
1282                                              i < adapter->vfs_allocated_count;
1283                                              i++) {
1284                                                 random_ether_addr(mac_addr);
1285                                                 igb_set_vf_mac(adapter, i,
1286                                                                mac_addr);
1287                                         }
1288                                 } else {
1289                                         kfree(adapter->vf_data);
1290                                         adapter->vf_data = NULL;
1291                                 }
1292                         }
1293                 }
1294         }
1295
1296 #endif
1297         /* setup the private structure */
1298         err = igb_sw_init(adapter);
1299         if (err)
1300                 goto err_sw_init;
1301
1302         igb_get_bus_info_pcie(hw);
1303
1304         /* set flags */
1305         switch (hw->mac.type) {
1306         case e1000_82575:
1307                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1308                 break;
1309         case e1000_82576:
1310         default:
1311                 break;
1312         }
1313
1314         hw->phy.autoneg_wait_to_complete = false;
1315         hw->mac.adaptive_ifs = true;
1316
1317         /* Copper options */
1318         if (hw->phy.media_type == e1000_media_type_copper) {
1319                 hw->phy.mdix = AUTO_ALL_MODES;
1320                 hw->phy.disable_polarity_correction = false;
1321                 hw->phy.ms_type = e1000_ms_hw_default;
1322         }
1323
1324         if (igb_check_reset_block(hw))
1325                 dev_info(&pdev->dev,
1326                         "PHY reset is blocked due to SOL/IDER session.\n");
1327
1328         netdev->features = NETIF_F_SG |
1329                            NETIF_F_IP_CSUM |
1330                            NETIF_F_HW_VLAN_TX |
1331                            NETIF_F_HW_VLAN_RX |
1332                            NETIF_F_HW_VLAN_FILTER;
1333
1334         netdev->features |= NETIF_F_IPV6_CSUM;
1335         netdev->features |= NETIF_F_TSO;
1336         netdev->features |= NETIF_F_TSO6;
1337
1338         netdev->features |= NETIF_F_GRO;
1339
1340         netdev->vlan_features |= NETIF_F_TSO;
1341         netdev->vlan_features |= NETIF_F_TSO6;
1342         netdev->vlan_features |= NETIF_F_IP_CSUM;
1343         netdev->vlan_features |= NETIF_F_SG;
1344
1345         if (pci_using_dac)
1346                 netdev->features |= NETIF_F_HIGHDMA;
1347
1348         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1349
1350         /* before reading the NVM, reset the controller to put the device in a
1351          * known good starting state */
1352         hw->mac.ops.reset_hw(hw);
1353
1354         /* make sure the NVM is good */
1355         if (igb_validate_nvm_checksum(hw) < 0) {
1356                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1357                 err = -EIO;
1358                 goto err_eeprom;
1359         }
1360
1361         /* copy the MAC address out of the NVM */
1362         if (hw->mac.ops.read_mac_addr(hw))
1363                 dev_err(&pdev->dev, "NVM Read Error\n");
1364
1365         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1366         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1367
1368         if (!is_valid_ether_addr(netdev->perm_addr)) {
1369                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1370                 err = -EIO;
1371                 goto err_eeprom;
1372         }
1373
1374         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1375                     (unsigned long) adapter);
1376         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1377                     (unsigned long) adapter);
1378
1379         INIT_WORK(&adapter->reset_task, igb_reset_task);
1380         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1381
1382         /* Initialize link properties that are user-changeable */
1383         adapter->fc_autoneg = true;
1384         hw->mac.autoneg = true;
1385         hw->phy.autoneg_advertised = 0x2f;
1386
1387         hw->fc.original_type = e1000_fc_default;
1388         hw->fc.type = e1000_fc_default;
1389
1390         adapter->itr_setting = IGB_DEFAULT_ITR;
1391         adapter->itr = IGB_START_ITR;
1392
1393         igb_validate_mdi_setting(hw);
1394
1395         adapter->rx_csum = 1;
1396
1397         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1398          * enable the ACPI Magic Packet filter
1399          */
1400
1401         if (hw->bus.func == 0)
1402                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1403         else if (hw->bus.func == 1)
1404                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1405
1406         if (eeprom_data & eeprom_apme_mask)
1407                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1408
1409         /* now that we have the eeprom settings, apply the special cases where
1410          * the eeprom may be wrong or the board simply won't support wake on
1411          * lan on a particular port */
1412         switch (pdev->device) {
1413         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1414                 adapter->eeprom_wol = 0;
1415                 break;
1416         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1417         case E1000_DEV_ID_82576_FIBER:
1418         case E1000_DEV_ID_82576_SERDES:
1419                 /* Wake events only supported on port A for dual fiber
1420                  * regardless of eeprom setting */
1421                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1422                         adapter->eeprom_wol = 0;
1423                 break;
1424         case E1000_DEV_ID_82576_QUAD_COPPER:
1425                 /* if quad port adapter, disable WoL on all but port A */
1426                 if (global_quad_port_a != 0)
1427                         adapter->eeprom_wol = 0;
1428                 else
1429                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1430                 /* Reset for multiple quad port adapters */
1431                 if (++global_quad_port_a == 4)
1432                         global_quad_port_a = 0;
1433                 break;
1434         }
1435
1436         /* initialize the wol settings based on the eeprom settings */
1437         adapter->wol = adapter->eeprom_wol;
1438         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1439
1440         /* reset the hardware with the new settings */
1441         igb_reset(adapter);
1442
1443         /* let the f/w know that the h/w is now under the control of the
1444          * driver. */
1445         igb_get_hw_control(adapter);
1446
1447         strcpy(netdev->name, "eth%d");
1448         err = register_netdev(netdev);
1449         if (err)
1450                 goto err_register;
1451
1452         /* carrier off reporting is important to ethtool even BEFORE open */
1453         netif_carrier_off(netdev);
1454
1455 #ifdef CONFIG_IGB_DCA
1456         if (dca_add_requester(&pdev->dev) == 0) {
1457                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1458                 dev_info(&pdev->dev, "DCA enabled\n");
1459                 /* Always use CB2 mode, difference is masked
1460                  * in the CB driver. */
1461                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1462                 igb_setup_dca(adapter);
1463         }
1464 #endif
1465
1466         /*
1467          * Initialize hardware timer: we keep it running just in case
1468          * that some program needs it later on.
1469          */
1470         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1471         adapter->cycles.read = igb_read_clock;
1472         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1473         adapter->cycles.mult = 1;
1474         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1475         wr32(E1000_TIMINCA,
1476              (1<<24) |
1477              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1478 #if 0
1479         /*
1480          * Avoid rollover while we initialize by resetting the time counter.
1481          */
1482         wr32(E1000_SYSTIML, 0x00000000);
1483         wr32(E1000_SYSTIMH, 0x00000000);
1484 #else
1485         /*
1486          * Set registers so that rollover occurs soon to test this.
1487          */
1488         wr32(E1000_SYSTIML, 0x00000000);
1489         wr32(E1000_SYSTIMH, 0xFF800000);
1490 #endif
1491         wrfl();
1492         timecounter_init(&adapter->clock,
1493                          &adapter->cycles,
1494                          ktime_to_ns(ktime_get_real()));
1495
1496         /*
1497          * Synchronize our NIC clock against system wall clock. NIC
1498          * time stamp reading requires ~3us per sample, each sample
1499          * was pretty stable even under load => only require 10
1500          * samples for each offset comparison.
1501          */
1502         memset(&adapter->compare, 0, sizeof(adapter->compare));
1503         adapter->compare.source = &adapter->clock;
1504         adapter->compare.target = ktime_get_real;
1505         adapter->compare.num_samples = 10;
1506         timecompare_update(&adapter->compare, 0);
1507
1508 #ifdef DEBUG
1509         {
1510                 char buffer[160];
1511                 printk(KERN_DEBUG
1512                         "igb: %s: hw %p initialized timer\n",
1513                         igb_get_time_str(adapter, buffer),
1514                         &adapter->hw);
1515         }
1516 #endif
1517
1518         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1519         /* print bus type/speed/width info */
1520         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1521                  netdev->name,
1522                  ((hw->bus.speed == e1000_bus_speed_2500)
1523                   ? "2.5Gb/s" : "unknown"),
1524                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1525                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1526                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1527                    "unknown"),
1528                  netdev->dev_addr);
1529
1530         igb_read_part_num(hw, &part_num);
1531         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1532                 (part_num >> 8), (part_num & 0xff));
1533
1534         dev_info(&pdev->dev,
1535                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1536                 adapter->msix_entries ? "MSI-X" :
1537                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1538                 adapter->num_rx_queues, adapter->num_tx_queues);
1539
1540         return 0;
1541
1542 err_register:
1543         igb_release_hw_control(adapter);
1544 err_eeprom:
1545         if (!igb_check_reset_block(hw))
1546                 igb_reset_phy(hw);
1547
1548         if (hw->flash_address)
1549                 iounmap(hw->flash_address);
1550
1551         igb_free_queues(adapter);
1552 err_sw_init:
1553         iounmap(hw->hw_addr);
1554 err_ioremap:
1555         free_netdev(netdev);
1556 err_alloc_etherdev:
1557         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1558                                      IORESOURCE_MEM));
1559 err_pci_reg:
1560 err_dma:
1561         pci_disable_device(pdev);
1562         return err;
1563 }
1564
1565 /**
1566  * igb_remove - Device Removal Routine
1567  * @pdev: PCI device information struct
1568  *
1569  * igb_remove is called by the PCI subsystem to alert the driver
1570  * that it should release a PCI device.  The could be caused by a
1571  * Hot-Plug event, or because the driver is going to be removed from
1572  * memory.
1573  **/
1574 static void __devexit igb_remove(struct pci_dev *pdev)
1575 {
1576         struct net_device *netdev = pci_get_drvdata(pdev);
1577         struct igb_adapter *adapter = netdev_priv(netdev);
1578         struct e1000_hw *hw = &adapter->hw;
1579         int err;
1580
1581         /* flush_scheduled work may reschedule our watchdog task, so
1582          * explicitly disable watchdog tasks from being rescheduled  */
1583         set_bit(__IGB_DOWN, &adapter->state);
1584         del_timer_sync(&adapter->watchdog_timer);
1585         del_timer_sync(&adapter->phy_info_timer);
1586
1587         flush_scheduled_work();
1588
1589 #ifdef CONFIG_IGB_DCA
1590         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1591                 dev_info(&pdev->dev, "DCA disabled\n");
1592                 dca_remove_requester(&pdev->dev);
1593                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1594                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1595         }
1596 #endif
1597
1598         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1599          * would have already happened in close and is redundant. */
1600         igb_release_hw_control(adapter);
1601
1602         unregister_netdev(netdev);
1603
1604         if (!igb_check_reset_block(&adapter->hw))
1605                 igb_reset_phy(&adapter->hw);
1606
1607         igb_reset_interrupt_capability(adapter);
1608
1609         igb_free_queues(adapter);
1610
1611 #ifdef CONFIG_PCI_IOV
1612         /* reclaim resources allocated to VFs */
1613         if (adapter->vf_data) {
1614                 /* disable iov and allow time for transactions to clear */
1615                 pci_disable_sriov(pdev);
1616                 msleep(500);
1617
1618                 kfree(adapter->vf_data);
1619                 adapter->vf_data = NULL;
1620                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1621                 msleep(100);
1622                 dev_info(&pdev->dev, "IOV Disabled\n");
1623         }
1624 #endif
1625         iounmap(hw->hw_addr);
1626         if (hw->flash_address)
1627                 iounmap(hw->flash_address);
1628         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1629                                      IORESOURCE_MEM));
1630
1631         free_netdev(netdev);
1632
1633         err = pci_disable_pcie_error_reporting(pdev);
1634         if (err)
1635                 dev_err(&pdev->dev,
1636                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1637
1638         pci_disable_device(pdev);
1639 }
1640
1641 /**
1642  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1643  * @adapter: board private structure to initialize
1644  *
1645  * igb_sw_init initializes the Adapter private data structure.
1646  * Fields are initialized based on PCI device information and
1647  * OS network device settings (MTU size).
1648  **/
1649 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1650 {
1651         struct e1000_hw *hw = &adapter->hw;
1652         struct net_device *netdev = adapter->netdev;
1653         struct pci_dev *pdev = adapter->pdev;
1654
1655         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1656
1657         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1658         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1659         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1660         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1661         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1662         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1663
1664         /* This call may decrease the number of queues depending on
1665          * interrupt mode. */
1666         igb_set_interrupt_capability(adapter);
1667
1668         if (igb_alloc_queues(adapter)) {
1669                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1670                 return -ENOMEM;
1671         }
1672
1673         /* Explicitly disable IRQ since the NIC can be in any state. */
1674         igb_irq_disable(adapter);
1675
1676         set_bit(__IGB_DOWN, &adapter->state);
1677         return 0;
1678 }
1679
1680 /**
1681  * igb_open - Called when a network interface is made active
1682  * @netdev: network interface device structure
1683  *
1684  * Returns 0 on success, negative value on failure
1685  *
1686  * The open entry point is called when a network interface is made
1687  * active by the system (IFF_UP).  At this point all resources needed
1688  * for transmit and receive operations are allocated, the interrupt
1689  * handler is registered with the OS, the watchdog timer is started,
1690  * and the stack is notified that the interface is ready.
1691  **/
1692 static int igb_open(struct net_device *netdev)
1693 {
1694         struct igb_adapter *adapter = netdev_priv(netdev);
1695         struct e1000_hw *hw = &adapter->hw;
1696         int err;
1697         int i;
1698
1699         /* disallow open during test */
1700         if (test_bit(__IGB_TESTING, &adapter->state))
1701                 return -EBUSY;
1702
1703         netif_carrier_off(netdev);
1704
1705         /* allocate transmit descriptors */
1706         err = igb_setup_all_tx_resources(adapter);
1707         if (err)
1708                 goto err_setup_tx;
1709
1710         /* allocate receive descriptors */
1711         err = igb_setup_all_rx_resources(adapter);
1712         if (err)
1713                 goto err_setup_rx;
1714
1715         /* e1000_power_up_phy(adapter); */
1716
1717         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1718         if ((adapter->hw.mng_cookie.status &
1719              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1720                 igb_update_mng_vlan(adapter);
1721
1722         /* before we allocate an interrupt, we must be ready to handle it.
1723          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1724          * as soon as we call pci_request_irq, so we have to setup our
1725          * clean_rx handler before we do so.  */
1726         igb_configure(adapter);
1727
1728         igb_vmm_control(adapter);
1729         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1730         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1731
1732         err = igb_request_irq(adapter);
1733         if (err)
1734                 goto err_req_irq;
1735
1736         /* From here on the code is the same as igb_up() */
1737         clear_bit(__IGB_DOWN, &adapter->state);
1738
1739         for (i = 0; i < adapter->num_rx_queues; i++)
1740                 napi_enable(&adapter->rx_ring[i].napi);
1741
1742         /* Clear any pending interrupts. */
1743         rd32(E1000_ICR);
1744
1745         igb_irq_enable(adapter);
1746
1747         netif_tx_start_all_queues(netdev);
1748
1749         /* Fire a link status change interrupt to start the watchdog. */
1750         wr32(E1000_ICS, E1000_ICS_LSC);
1751
1752         return 0;
1753
1754 err_req_irq:
1755         igb_release_hw_control(adapter);
1756         /* e1000_power_down_phy(adapter); */
1757         igb_free_all_rx_resources(adapter);
1758 err_setup_rx:
1759         igb_free_all_tx_resources(adapter);
1760 err_setup_tx:
1761         igb_reset(adapter);
1762
1763         return err;
1764 }
1765
1766 /**
1767  * igb_close - Disables a network interface
1768  * @netdev: network interface device structure
1769  *
1770  * Returns 0, this is not allowed to fail
1771  *
1772  * The close entry point is called when an interface is de-activated
1773  * by the OS.  The hardware is still under the driver's control, but
1774  * needs to be disabled.  A global MAC reset is issued to stop the
1775  * hardware, and all transmit and receive resources are freed.
1776  **/
1777 static int igb_close(struct net_device *netdev)
1778 {
1779         struct igb_adapter *adapter = netdev_priv(netdev);
1780
1781         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1782         igb_down(adapter);
1783
1784         igb_free_irq(adapter);
1785
1786         igb_free_all_tx_resources(adapter);
1787         igb_free_all_rx_resources(adapter);
1788
1789         /* kill manageability vlan ID if supported, but not if a vlan with
1790          * the same ID is registered on the host OS (let 8021q kill it) */
1791         if ((adapter->hw.mng_cookie.status &
1792                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1793              !(adapter->vlgrp &&
1794                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1795                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1796
1797         return 0;
1798 }
1799
1800 /**
1801  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1802  * @adapter: board private structure
1803  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1804  *
1805  * Return 0 on success, negative on failure
1806  **/
1807 int igb_setup_tx_resources(struct igb_adapter *adapter,
1808                            struct igb_ring *tx_ring)
1809 {
1810         struct pci_dev *pdev = adapter->pdev;
1811         int size;
1812
1813         size = sizeof(struct igb_buffer) * tx_ring->count;
1814         tx_ring->buffer_info = vmalloc(size);
1815         if (!tx_ring->buffer_info)
1816                 goto err;
1817         memset(tx_ring->buffer_info, 0, size);
1818
1819         /* round up to nearest 4K */
1820         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1821         tx_ring->size = ALIGN(tx_ring->size, 4096);
1822
1823         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1824                                              &tx_ring->dma);
1825
1826         if (!tx_ring->desc)
1827                 goto err;
1828
1829         tx_ring->adapter = adapter;
1830         tx_ring->next_to_use = 0;
1831         tx_ring->next_to_clean = 0;
1832         return 0;
1833
1834 err:
1835         vfree(tx_ring->buffer_info);
1836         dev_err(&adapter->pdev->dev,
1837                 "Unable to allocate memory for the transmit descriptor ring\n");
1838         return -ENOMEM;
1839 }
1840
1841 /**
1842  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1843  *                                (Descriptors) for all queues
1844  * @adapter: board private structure
1845  *
1846  * Return 0 on success, negative on failure
1847  **/
1848 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1849 {
1850         int i, err = 0;
1851         int r_idx;
1852
1853         for (i = 0; i < adapter->num_tx_queues; i++) {
1854                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1855                 if (err) {
1856                         dev_err(&adapter->pdev->dev,
1857                                 "Allocation for Tx Queue %u failed\n", i);
1858                         for (i--; i >= 0; i--)
1859                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1860                         break;
1861                 }
1862         }
1863
1864         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1865                 r_idx = i % adapter->num_tx_queues;
1866                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1867         }
1868         return err;
1869 }
1870
1871 /**
1872  * igb_configure_tx - Configure transmit Unit after Reset
1873  * @adapter: board private structure
1874  *
1875  * Configure the Tx unit of the MAC after a reset.
1876  **/
1877 static void igb_configure_tx(struct igb_adapter *adapter)
1878 {
1879         u64 tdba;
1880         struct e1000_hw *hw = &adapter->hw;
1881         u32 tctl;
1882         u32 txdctl, txctrl;
1883         int i, j;
1884
1885         for (i = 0; i < adapter->num_tx_queues; i++) {
1886                 struct igb_ring *ring = &adapter->tx_ring[i];
1887                 j = ring->reg_idx;
1888                 wr32(E1000_TDLEN(j),
1889                      ring->count * sizeof(union e1000_adv_tx_desc));
1890                 tdba = ring->dma;
1891                 wr32(E1000_TDBAL(j),
1892                      tdba & 0x00000000ffffffffULL);
1893                 wr32(E1000_TDBAH(j), tdba >> 32);
1894
1895                 ring->head = E1000_TDH(j);
1896                 ring->tail = E1000_TDT(j);
1897                 writel(0, hw->hw_addr + ring->tail);
1898                 writel(0, hw->hw_addr + ring->head);
1899                 txdctl = rd32(E1000_TXDCTL(j));
1900                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1901                 wr32(E1000_TXDCTL(j), txdctl);
1902
1903                 /* Turn off Relaxed Ordering on head write-backs.  The
1904                  * writebacks MUST be delivered in order or it will
1905                  * completely screw up our bookeeping.
1906                  */
1907                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1908                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1909                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1910         }
1911
1912         /* disable queue 0 to prevent tail bump w/o re-configuration */
1913         if (adapter->vfs_allocated_count)
1914                 wr32(E1000_TXDCTL(0), 0);
1915
1916         /* Program the Transmit Control Register */
1917         tctl = rd32(E1000_TCTL);
1918         tctl &= ~E1000_TCTL_CT;
1919         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1920                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1921
1922         igb_config_collision_dist(hw);
1923
1924         /* Setup Transmit Descriptor Settings for eop descriptor */
1925         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1926
1927         /* Enable transmits */
1928         tctl |= E1000_TCTL_EN;
1929
1930         wr32(E1000_TCTL, tctl);
1931 }
1932
1933 /**
1934  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1935  * @adapter: board private structure
1936  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1937  *
1938  * Returns 0 on success, negative on failure
1939  **/
1940 int igb_setup_rx_resources(struct igb_adapter *adapter,
1941                            struct igb_ring *rx_ring)
1942 {
1943         struct pci_dev *pdev = adapter->pdev;
1944         int size, desc_len;
1945
1946         size = sizeof(struct igb_buffer) * rx_ring->count;
1947         rx_ring->buffer_info = vmalloc(size);
1948         if (!rx_ring->buffer_info)
1949                 goto err;
1950         memset(rx_ring->buffer_info, 0, size);
1951
1952         desc_len = sizeof(union e1000_adv_rx_desc);
1953
1954         /* Round up to nearest 4K */
1955         rx_ring->size = rx_ring->count * desc_len;
1956         rx_ring->size = ALIGN(rx_ring->size, 4096);
1957
1958         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1959                                              &rx_ring->dma);
1960
1961         if (!rx_ring->desc)
1962                 goto err;
1963
1964         rx_ring->next_to_clean = 0;
1965         rx_ring->next_to_use = 0;
1966
1967         rx_ring->adapter = adapter;
1968
1969         return 0;
1970
1971 err:
1972         vfree(rx_ring->buffer_info);
1973         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1974                 "the receive descriptor ring\n");
1975         return -ENOMEM;
1976 }
1977
1978 /**
1979  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1980  *                                (Descriptors) for all queues
1981  * @adapter: board private structure
1982  *
1983  * Return 0 on success, negative on failure
1984  **/
1985 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1986 {
1987         int i, err = 0;
1988
1989         for (i = 0; i < adapter->num_rx_queues; i++) {
1990                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1991                 if (err) {
1992                         dev_err(&adapter->pdev->dev,
1993                                 "Allocation for Rx Queue %u failed\n", i);
1994                         for (i--; i >= 0; i--)
1995                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1996                         break;
1997                 }
1998         }
1999
2000         return err;
2001 }
2002
2003 /**
2004  * igb_setup_rctl - configure the receive control registers
2005  * @adapter: Board private structure
2006  **/
2007 static void igb_setup_rctl(struct igb_adapter *adapter)
2008 {
2009         struct e1000_hw *hw = &adapter->hw;
2010         u32 rctl;
2011         u32 srrctl = 0;
2012         int i, j;
2013
2014         rctl = rd32(E1000_RCTL);
2015
2016         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2017         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2018
2019         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2020                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2021
2022         /*
2023          * enable stripping of CRC. It's unlikely this will break BMC
2024          * redirection as it did with e1000. Newer features require
2025          * that the HW strips the CRC.
2026          */
2027         rctl |= E1000_RCTL_SECRC;
2028
2029         /*
2030          * disable store bad packets and clear size bits.
2031          */
2032         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2033
2034         /* enable LPE when to prevent packets larger than max_frame_size */
2035                 rctl |= E1000_RCTL_LPE;
2036
2037         /* Setup buffer sizes */
2038         switch (adapter->rx_buffer_len) {
2039         case IGB_RXBUFFER_256:
2040                 rctl |= E1000_RCTL_SZ_256;
2041                 break;
2042         case IGB_RXBUFFER_512:
2043                 rctl |= E1000_RCTL_SZ_512;
2044                 break;
2045         default:
2046                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2047                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2048                 break;
2049         }
2050
2051         /* 82575 and greater support packet-split where the protocol
2052          * header is placed in skb->data and the packet data is
2053          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2054          * In the case of a non-split, skb->data is linearly filled,
2055          * followed by the page buffers.  Therefore, skb->data is
2056          * sized to hold the largest protocol header.
2057          */
2058         /* allocations using alloc_page take too long for regular MTU
2059          * so only enable packet split for jumbo frames */
2060         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2061                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2062                 srrctl |= adapter->rx_ps_hdr_size <<
2063                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2064                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2065         } else {
2066                 adapter->rx_ps_hdr_size = 0;
2067                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2068         }
2069
2070         /* Attention!!!  For SR-IOV PF driver operations you must enable
2071          * queue drop for all VF and PF queues to prevent head of line blocking
2072          * if an un-trusted VF does not provide descriptors to hardware.
2073          */
2074         if (adapter->vfs_allocated_count) {
2075                 u32 vmolr;
2076
2077                 j = adapter->rx_ring[0].reg_idx;
2078
2079                 /* set all queue drop enable bits */
2080                 wr32(E1000_QDE, ALL_QUEUES);
2081                 srrctl |= E1000_SRRCTL_DROP_EN;
2082
2083                 /* disable queue 0 to prevent tail write w/o re-config */
2084                 wr32(E1000_RXDCTL(0), 0);
2085
2086                 vmolr = rd32(E1000_VMOLR(j));
2087                 if (rctl & E1000_RCTL_LPE)
2088                         vmolr |= E1000_VMOLR_LPE;
2089                 if (adapter->num_rx_queues > 0)
2090                         vmolr |= E1000_VMOLR_RSSE;
2091                 wr32(E1000_VMOLR(j), vmolr);
2092         }
2093
2094         for (i = 0; i < adapter->num_rx_queues; i++) {
2095                 j = adapter->rx_ring[i].reg_idx;
2096                 wr32(E1000_SRRCTL(j), srrctl);
2097         }
2098
2099         wr32(E1000_RCTL, rctl);
2100 }
2101
2102 /**
2103  * igb_rlpml_set - set maximum receive packet size
2104  * @adapter: board private structure
2105  *
2106  * Configure maximum receivable packet size.
2107  **/
2108 static void igb_rlpml_set(struct igb_adapter *adapter)
2109 {
2110         u32 max_frame_size = adapter->max_frame_size;
2111         struct e1000_hw *hw = &adapter->hw;
2112         u16 pf_id = adapter->vfs_allocated_count;
2113
2114         if (adapter->vlgrp)
2115                 max_frame_size += VLAN_TAG_SIZE;
2116
2117         /* if vfs are enabled we set RLPML to the largest possible request
2118          * size and set the VMOLR RLPML to the size we need */
2119         if (pf_id) {
2120                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2121                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2122         }
2123
2124         wr32(E1000_RLPML, max_frame_size);
2125 }
2126
2127 /**
2128  * igb_configure_vt_default_pool - Configure VT default pool
2129  * @adapter: board private structure
2130  *
2131  * Configure the default pool
2132  **/
2133 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2134 {
2135         struct e1000_hw *hw = &adapter->hw;
2136         u16 pf_id = adapter->vfs_allocated_count;
2137         u32 vtctl;
2138
2139         /* not in sr-iov mode - do nothing */
2140         if (!pf_id)
2141                 return;
2142
2143         vtctl = rd32(E1000_VT_CTL);
2144         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2145                    E1000_VT_CTL_DISABLE_DEF_POOL);
2146         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2147         wr32(E1000_VT_CTL, vtctl);
2148 }
2149
2150 /**
2151  * igb_configure_rx - Configure receive Unit after Reset
2152  * @adapter: board private structure
2153  *
2154  * Configure the Rx unit of the MAC after a reset.
2155  **/
2156 static void igb_configure_rx(struct igb_adapter *adapter)
2157 {
2158         u64 rdba;
2159         struct e1000_hw *hw = &adapter->hw;
2160         u32 rctl, rxcsum;
2161         u32 rxdctl;
2162         int i;
2163
2164         /* disable receives while setting up the descriptors */
2165         rctl = rd32(E1000_RCTL);
2166         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2167         wrfl();
2168         mdelay(10);
2169
2170         if (adapter->itr_setting > 3)
2171                 wr32(E1000_ITR, adapter->itr);
2172
2173         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2174          * the Base and Length of the Rx Descriptor Ring */
2175         for (i = 0; i < adapter->num_rx_queues; i++) {
2176                 struct igb_ring *ring = &adapter->rx_ring[i];
2177                 int j = ring->reg_idx;
2178                 rdba = ring->dma;
2179                 wr32(E1000_RDBAL(j),
2180                      rdba & 0x00000000ffffffffULL);
2181                 wr32(E1000_RDBAH(j), rdba >> 32);
2182                 wr32(E1000_RDLEN(j),
2183                      ring->count * sizeof(union e1000_adv_rx_desc));
2184
2185                 ring->head = E1000_RDH(j);
2186                 ring->tail = E1000_RDT(j);
2187                 writel(0, hw->hw_addr + ring->tail);
2188                 writel(0, hw->hw_addr + ring->head);
2189
2190                 rxdctl = rd32(E1000_RXDCTL(j));
2191                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2192                 rxdctl &= 0xFFF00000;
2193                 rxdctl |= IGB_RX_PTHRESH;
2194                 rxdctl |= IGB_RX_HTHRESH << 8;
2195                 rxdctl |= IGB_RX_WTHRESH << 16;
2196                 wr32(E1000_RXDCTL(j), rxdctl);
2197         }
2198
2199         if (adapter->num_rx_queues > 1) {
2200                 u32 random[10];
2201                 u32 mrqc;
2202                 u32 j, shift;
2203                 union e1000_reta {
2204                         u32 dword;
2205                         u8  bytes[4];
2206                 } reta;
2207
2208                 get_random_bytes(&random[0], 40);
2209
2210                 if (hw->mac.type >= e1000_82576)
2211                         shift = 0;
2212                 else
2213                         shift = 6;
2214                 for (j = 0; j < (32 * 4); j++) {
2215                         reta.bytes[j & 3] =
2216                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2217                         if ((j & 3) == 3)
2218                                 writel(reta.dword,
2219                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2220                 }
2221                 if (adapter->vfs_allocated_count)
2222                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2223                 else
2224                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2225
2226                 /* Fill out hash function seeds */
2227                 for (j = 0; j < 10; j++)
2228                         array_wr32(E1000_RSSRK(0), j, random[j]);
2229
2230                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2231                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2232                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2233                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2234                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2235                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2236                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2237                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2238
2239                 wr32(E1000_MRQC, mrqc);
2240         } else if (adapter->vfs_allocated_count) {
2241                 /* Enable multi-queue for sr-iov */
2242                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2243         }
2244
2245         /* Enable Receive Checksum Offload for TCP and UDP */
2246         rxcsum = rd32(E1000_RXCSUM);
2247         /* Disable raw packet checksumming */
2248         rxcsum |= E1000_RXCSUM_PCSD;
2249         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2250         if (!adapter->rx_csum)
2251                 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL);
2252         wr32(E1000_RXCSUM, rxcsum);
2253
2254         /* Set the default pool for the PF's first queue */
2255         igb_configure_vt_default_pool(adapter);
2256
2257         igb_rlpml_set(adapter);
2258
2259         /* Enable Receives */
2260         wr32(E1000_RCTL, rctl);
2261 }
2262
2263 /**
2264  * igb_free_tx_resources - Free Tx Resources per Queue
2265  * @tx_ring: Tx descriptor ring for a specific queue
2266  *
2267  * Free all transmit software resources
2268  **/
2269 void igb_free_tx_resources(struct igb_ring *tx_ring)
2270 {
2271         struct pci_dev *pdev = tx_ring->adapter->pdev;
2272
2273         igb_clean_tx_ring(tx_ring);
2274
2275         vfree(tx_ring->buffer_info);
2276         tx_ring->buffer_info = NULL;
2277
2278         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2279
2280         tx_ring->desc = NULL;
2281 }
2282
2283 /**
2284  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2285  * @adapter: board private structure
2286  *
2287  * Free all transmit software resources
2288  **/
2289 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2290 {
2291         int i;
2292
2293         for (i = 0; i < adapter->num_tx_queues; i++)
2294                 igb_free_tx_resources(&adapter->tx_ring[i]);
2295 }
2296
2297 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2298                                            struct igb_buffer *buffer_info)
2299 {
2300         buffer_info->dma = 0;
2301         if (buffer_info->skb) {
2302                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2303                               DMA_TO_DEVICE);
2304                 dev_kfree_skb_any(buffer_info->skb);
2305                 buffer_info->skb = NULL;
2306         }
2307         buffer_info->time_stamp = 0;
2308         /* buffer_info must be completely set up in the transmit path */
2309 }
2310
2311 /**
2312  * igb_clean_tx_ring - Free Tx Buffers
2313  * @tx_ring: ring to be cleaned
2314  **/
2315 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2316 {
2317         struct igb_adapter *adapter = tx_ring->adapter;
2318         struct igb_buffer *buffer_info;
2319         unsigned long size;
2320         unsigned int i;
2321
2322         if (!tx_ring->buffer_info)
2323                 return;
2324         /* Free all the Tx ring sk_buffs */
2325
2326         for (i = 0; i < tx_ring->count; i++) {
2327                 buffer_info = &tx_ring->buffer_info[i];
2328                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2329         }
2330
2331         size = sizeof(struct igb_buffer) * tx_ring->count;
2332         memset(tx_ring->buffer_info, 0, size);
2333
2334         /* Zero out the descriptor ring */
2335
2336         memset(tx_ring->desc, 0, tx_ring->size);
2337
2338         tx_ring->next_to_use = 0;
2339         tx_ring->next_to_clean = 0;
2340
2341         writel(0, adapter->hw.hw_addr + tx_ring->head);
2342         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2343 }
2344
2345 /**
2346  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2347  * @adapter: board private structure
2348  **/
2349 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2350 {
2351         int i;
2352
2353         for (i = 0; i < adapter->num_tx_queues; i++)
2354                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2355 }
2356
2357 /**
2358  * igb_free_rx_resources - Free Rx Resources
2359  * @rx_ring: ring to clean the resources from
2360  *
2361  * Free all receive software resources
2362  **/
2363 void igb_free_rx_resources(struct igb_ring *rx_ring)
2364 {
2365         struct pci_dev *pdev = rx_ring->adapter->pdev;
2366
2367         igb_clean_rx_ring(rx_ring);
2368
2369         vfree(rx_ring->buffer_info);
2370         rx_ring->buffer_info = NULL;
2371
2372         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2373
2374         rx_ring->desc = NULL;
2375 }
2376
2377 /**
2378  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2379  * @adapter: board private structure
2380  *
2381  * Free all receive software resources
2382  **/
2383 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2384 {
2385         int i;
2386
2387         for (i = 0; i < adapter->num_rx_queues; i++)
2388                 igb_free_rx_resources(&adapter->rx_ring[i]);
2389 }
2390
2391 /**
2392  * igb_clean_rx_ring - Free Rx Buffers per Queue
2393  * @rx_ring: ring to free buffers from
2394  **/
2395 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2396 {
2397         struct igb_adapter *adapter = rx_ring->adapter;
2398         struct igb_buffer *buffer_info;
2399         struct pci_dev *pdev = adapter->pdev;
2400         unsigned long size;
2401         unsigned int i;
2402
2403         if (!rx_ring->buffer_info)
2404                 return;
2405         /* Free all the Rx ring sk_buffs */
2406         for (i = 0; i < rx_ring->count; i++) {
2407                 buffer_info = &rx_ring->buffer_info[i];
2408                 if (buffer_info->dma) {
2409                         if (adapter->rx_ps_hdr_size)
2410                                 pci_unmap_single(pdev, buffer_info->dma,
2411                                                  adapter->rx_ps_hdr_size,
2412                                                  PCI_DMA_FROMDEVICE);
2413                         else
2414                                 pci_unmap_single(pdev, buffer_info->dma,
2415                                                  adapter->rx_buffer_len,
2416                                                  PCI_DMA_FROMDEVICE);
2417                         buffer_info->dma = 0;
2418                 }
2419
2420                 if (buffer_info->skb) {
2421                         dev_kfree_skb(buffer_info->skb);
2422                         buffer_info->skb = NULL;
2423                 }
2424                 if (buffer_info->page) {
2425                         if (buffer_info->page_dma)
2426                                 pci_unmap_page(pdev, buffer_info->page_dma,
2427                                                PAGE_SIZE / 2,
2428                                                PCI_DMA_FROMDEVICE);
2429                         put_page(buffer_info->page);
2430                         buffer_info->page = NULL;
2431                         buffer_info->page_dma = 0;
2432                         buffer_info->page_offset = 0;
2433                 }
2434         }
2435
2436         size = sizeof(struct igb_buffer) * rx_ring->count;
2437         memset(rx_ring->buffer_info, 0, size);
2438
2439         /* Zero out the descriptor ring */
2440         memset(rx_ring->desc, 0, rx_ring->size);
2441
2442         rx_ring->next_to_clean = 0;
2443         rx_ring->next_to_use = 0;
2444
2445         writel(0, adapter->hw.hw_addr + rx_ring->head);
2446         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2447 }
2448
2449 /**
2450  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2451  * @adapter: board private structure
2452  **/
2453 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2454 {
2455         int i;
2456
2457         for (i = 0; i < adapter->num_rx_queues; i++)
2458                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2459 }
2460
2461 /**
2462  * igb_set_mac - Change the Ethernet Address of the NIC
2463  * @netdev: network interface device structure
2464  * @p: pointer to an address structure
2465  *
2466  * Returns 0 on success, negative on failure
2467  **/
2468 static int igb_set_mac(struct net_device *netdev, void *p)
2469 {
2470         struct igb_adapter *adapter = netdev_priv(netdev);
2471         struct e1000_hw *hw = &adapter->hw;
2472         struct sockaddr *addr = p;
2473
2474         if (!is_valid_ether_addr(addr->sa_data))
2475                 return -EADDRNOTAVAIL;
2476
2477         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2478         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2479
2480         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2481
2482         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2483
2484         return 0;
2485 }
2486
2487 /**
2488  * igb_set_multi - Multicast and Promiscuous mode set
2489  * @netdev: network interface device structure
2490  *
2491  * The set_multi entry point is called whenever the multicast address
2492  * list or the network interface flags are updated.  This routine is
2493  * responsible for configuring the hardware for proper multicast,
2494  * promiscuous mode, and all-multi behavior.
2495  **/
2496 static void igb_set_multi(struct net_device *netdev)
2497 {
2498         struct igb_adapter *adapter = netdev_priv(netdev);
2499         struct e1000_hw *hw = &adapter->hw;
2500         struct e1000_mac_info *mac = &hw->mac;
2501         struct dev_mc_list *mc_ptr;
2502         u8  *mta_list = NULL;
2503         u32 rctl;
2504         int i;
2505
2506         /* Check for Promiscuous and All Multicast modes */
2507
2508         rctl = rd32(E1000_RCTL);
2509
2510         if (netdev->flags & IFF_PROMISC) {
2511                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2512                 rctl &= ~E1000_RCTL_VFE;
2513         } else {
2514                 if (netdev->flags & IFF_ALLMULTI) {
2515                         rctl |= E1000_RCTL_MPE;
2516                         rctl &= ~E1000_RCTL_UPE;
2517                 } else
2518                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2519                 rctl |= E1000_RCTL_VFE;
2520         }
2521         wr32(E1000_RCTL, rctl);
2522
2523         if (netdev->mc_count) {
2524                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2525                 if (!mta_list) {
2526                         dev_err(&adapter->pdev->dev,
2527                                 "failed to allocate multicast filter list\n");
2528                         return;
2529                 }
2530         }
2531
2532         /* The shared function expects a packed array of only addresses. */
2533         mc_ptr = netdev->mc_list;
2534
2535         for (i = 0; i < netdev->mc_count; i++) {
2536                 if (!mc_ptr)
2537                         break;
2538                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2539                 mc_ptr = mc_ptr->next;
2540         }
2541         igb_update_mc_addr_list(hw, mta_list, i,
2542                                 adapter->vfs_allocated_count + 1,
2543                                 mac->rar_entry_count);
2544
2545         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2546         igb_restore_vf_multicasts(adapter);
2547
2548         kfree(mta_list);
2549 }
2550
2551 /* Need to wait a few seconds after link up to get diagnostic information from
2552  * the phy */
2553 static void igb_update_phy_info(unsigned long data)
2554 {
2555         struct igb_adapter *adapter = (struct igb_adapter *) data;
2556         igb_get_phy_info(&adapter->hw);
2557 }
2558
2559 /**
2560  * igb_has_link - check shared code for link and determine up/down
2561  * @adapter: pointer to driver private info
2562  **/
2563 static bool igb_has_link(struct igb_adapter *adapter)
2564 {
2565         struct e1000_hw *hw = &adapter->hw;
2566         bool link_active = false;
2567         s32 ret_val = 0;
2568
2569         /* get_link_status is set on LSC (link status) interrupt or
2570          * rx sequence error interrupt.  get_link_status will stay
2571          * false until the e1000_check_for_link establishes link
2572          * for copper adapters ONLY
2573          */
2574         switch (hw->phy.media_type) {
2575         case e1000_media_type_copper:
2576                 if (hw->mac.get_link_status) {
2577                         ret_val = hw->mac.ops.check_for_link(hw);
2578                         link_active = !hw->mac.get_link_status;
2579                 } else {
2580                         link_active = true;
2581                 }
2582                 break;
2583         case e1000_media_type_fiber:
2584                 ret_val = hw->mac.ops.check_for_link(hw);
2585                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2586                 break;
2587         case e1000_media_type_internal_serdes:
2588                 ret_val = hw->mac.ops.check_for_link(hw);
2589                 link_active = hw->mac.serdes_has_link;
2590                 break;
2591         default:
2592         case e1000_media_type_unknown:
2593                 break;
2594         }
2595
2596         return link_active;
2597 }
2598
2599 /**
2600  * igb_watchdog - Timer Call-back
2601  * @data: pointer to adapter cast into an unsigned long
2602  **/
2603 static void igb_watchdog(unsigned long data)
2604 {
2605         struct igb_adapter *adapter = (struct igb_adapter *)data;
2606         /* Do the rest outside of interrupt context */
2607         schedule_work(&adapter->watchdog_task);
2608 }
2609
2610 static void igb_watchdog_task(struct work_struct *work)
2611 {
2612         struct igb_adapter *adapter = container_of(work,
2613                                         struct igb_adapter, watchdog_task);
2614         struct e1000_hw *hw = &adapter->hw;
2615         struct net_device *netdev = adapter->netdev;
2616         struct igb_ring *tx_ring = adapter->tx_ring;
2617         u32 link;
2618         u32 eics = 0;
2619         int i;
2620
2621         link = igb_has_link(adapter);
2622         if ((netif_carrier_ok(netdev)) && link)
2623                 goto link_up;
2624
2625         if (link) {
2626                 if (!netif_carrier_ok(netdev)) {
2627                         u32 ctrl;
2628                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2629                                                    &adapter->link_speed,
2630                                                    &adapter->link_duplex);
2631
2632                         ctrl = rd32(E1000_CTRL);
2633                         /* Links status message must follow this format */
2634                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2635                                  "Flow Control: %s\n",
2636                                  netdev->name,
2637                                  adapter->link_speed,
2638                                  adapter->link_duplex == FULL_DUPLEX ?
2639                                  "Full Duplex" : "Half Duplex",
2640                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2641                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2642                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2643                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2644
2645                         /* tweak tx_queue_len according to speed/duplex and
2646                          * adjust the timeout factor */
2647                         netdev->tx_queue_len = adapter->tx_queue_len;
2648                         adapter->tx_timeout_factor = 1;
2649                         switch (adapter->link_speed) {
2650                         case SPEED_10:
2651                                 netdev->tx_queue_len = 10;
2652                                 adapter->tx_timeout_factor = 14;
2653                                 break;
2654                         case SPEED_100:
2655                                 netdev->tx_queue_len = 100;
2656                                 /* maybe add some timeout factor ? */
2657                                 break;
2658                         }
2659
2660                         netif_carrier_on(netdev);
2661
2662                         igb_ping_all_vfs(adapter);
2663
2664                         /* link state has changed, schedule phy info update */
2665                         if (!test_bit(__IGB_DOWN, &adapter->state))
2666                                 mod_timer(&adapter->phy_info_timer,
2667                                           round_jiffies(jiffies + 2 * HZ));
2668                 }
2669         } else {
2670                 if (netif_carrier_ok(netdev)) {
2671                         adapter->link_speed = 0;
2672                         adapter->link_duplex = 0;
2673                         /* Links status message must follow this format */
2674                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2675                                netdev->name);
2676                         netif_carrier_off(netdev);
2677
2678                         igb_ping_all_vfs(adapter);
2679
2680                         /* link state has changed, schedule phy info update */
2681                         if (!test_bit(__IGB_DOWN, &adapter->state))
2682                                 mod_timer(&adapter->phy_info_timer,
2683                                           round_jiffies(jiffies + 2 * HZ));
2684                 }
2685         }
2686
2687 link_up:
2688         igb_update_stats(adapter);
2689
2690         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2691         adapter->tpt_old = adapter->stats.tpt;
2692         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2693         adapter->colc_old = adapter->stats.colc;
2694
2695         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2696         adapter->gorc_old = adapter->stats.gorc;
2697         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2698         adapter->gotc_old = adapter->stats.gotc;
2699
2700         igb_update_adaptive(&adapter->hw);
2701
2702         if (!netif_carrier_ok(netdev)) {
2703                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2704                         /* We've lost link, so the controller stops DMA,
2705                          * but we've got queued Tx work that's never going
2706                          * to get done, so reset controller to flush Tx.
2707                          * (Do the reset outside of interrupt context). */
2708                         adapter->tx_timeout_count++;
2709                         schedule_work(&adapter->reset_task);
2710                 }
2711         }
2712
2713         /* Cause software interrupt to ensure rx ring is cleaned */
2714         if (adapter->msix_entries) {
2715                 for (i = 0; i < adapter->num_rx_queues; i++)
2716                         eics |= adapter->rx_ring[i].eims_value;
2717                 wr32(E1000_EICS, eics);
2718         } else {
2719                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2720         }
2721
2722         /* Force detection of hung controller every watchdog period */
2723         tx_ring->detect_tx_hung = true;
2724
2725         /* Reset the timer */
2726         if (!test_bit(__IGB_DOWN, &adapter->state))
2727                 mod_timer(&adapter->watchdog_timer,
2728                           round_jiffies(jiffies + 2 * HZ));
2729 }
2730
2731 enum latency_range {
2732         lowest_latency = 0,
2733         low_latency = 1,
2734         bulk_latency = 2,
2735         latency_invalid = 255
2736 };
2737
2738
2739 /**
2740  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2741  *
2742  *      Stores a new ITR value based on strictly on packet size.  This
2743  *      algorithm is less sophisticated than that used in igb_update_itr,
2744  *      due to the difficulty of synchronizing statistics across multiple
2745  *      receive rings.  The divisors and thresholds used by this fuction
2746  *      were determined based on theoretical maximum wire speed and testing
2747  *      data, in order to minimize response time while increasing bulk
2748  *      throughput.
2749  *      This functionality is controlled by the InterruptThrottleRate module
2750  *      parameter (see igb_param.c)
2751  *      NOTE:  This function is called only when operating in a multiqueue
2752  *             receive environment.
2753  * @rx_ring: pointer to ring
2754  **/
2755 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2756 {
2757         int new_val = rx_ring->itr_val;
2758         int avg_wire_size = 0;
2759         struct igb_adapter *adapter = rx_ring->adapter;
2760
2761         if (!rx_ring->total_packets)
2762                 goto clear_counts; /* no packets, so don't do anything */
2763
2764         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2765          * ints/sec - ITR timer value of 120 ticks.
2766          */
2767         if (adapter->link_speed != SPEED_1000) {
2768                 new_val = 120;
2769                 goto set_itr_val;
2770         }
2771         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2772
2773         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2774         avg_wire_size += 24;
2775
2776         /* Don't starve jumbo frames */
2777         avg_wire_size = min(avg_wire_size, 3000);
2778
2779         /* Give a little boost to mid-size frames */
2780         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2781                 new_val = avg_wire_size / 3;
2782         else
2783                 new_val = avg_wire_size / 2;
2784
2785 set_itr_val:
2786         if (new_val != rx_ring->itr_val) {
2787                 rx_ring->itr_val = new_val;
2788                 rx_ring->set_itr = 1;
2789         }
2790 clear_counts:
2791         rx_ring->total_bytes = 0;
2792         rx_ring->total_packets = 0;
2793 }
2794
2795 /**
2796  * igb_update_itr - update the dynamic ITR value based on statistics
2797  *      Stores a new ITR value based on packets and byte
2798  *      counts during the last interrupt.  The advantage of per interrupt
2799  *      computation is faster updates and more accurate ITR for the current
2800  *      traffic pattern.  Constants in this function were computed
2801  *      based on theoretical maximum wire speed and thresholds were set based
2802  *      on testing data as well as attempting to minimize response time
2803  *      while increasing bulk throughput.
2804  *      this functionality is controlled by the InterruptThrottleRate module
2805  *      parameter (see igb_param.c)
2806  *      NOTE:  These calculations are only valid when operating in a single-
2807  *             queue environment.
2808  * @adapter: pointer to adapter
2809  * @itr_setting: current adapter->itr
2810  * @packets: the number of packets during this measurement interval
2811  * @bytes: the number of bytes during this measurement interval
2812  **/
2813 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2814                                    int packets, int bytes)
2815 {
2816         unsigned int retval = itr_setting;
2817
2818         if (packets == 0)
2819                 goto update_itr_done;
2820
2821         switch (itr_setting) {
2822         case lowest_latency:
2823                 /* handle TSO and jumbo frames */
2824                 if (bytes/packets > 8000)
2825                         retval = bulk_latency;
2826                 else if ((packets < 5) && (bytes > 512))
2827                         retval = low_latency;
2828                 break;
2829         case low_latency:  /* 50 usec aka 20000 ints/s */
2830                 if (bytes > 10000) {
2831                         /* this if handles the TSO accounting */
2832                         if (bytes/packets > 8000) {
2833                                 retval = bulk_latency;
2834                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2835                                 retval = bulk_latency;
2836                         } else if ((packets > 35)) {
2837                                 retval = lowest_latency;
2838                         }
2839                 } else if (bytes/packets > 2000) {
2840                         retval = bulk_latency;
2841                 } else if (packets <= 2 && bytes < 512) {
2842                         retval = lowest_latency;
2843                 }
2844                 break;
2845         case bulk_latency: /* 250 usec aka 4000 ints/s */
2846                 if (bytes > 25000) {
2847                         if (packets > 35)
2848                                 retval = low_latency;
2849                 } else if (bytes < 1500) {
2850                         retval = low_latency;
2851                 }
2852                 break;
2853         }
2854
2855 update_itr_done:
2856         return retval;
2857 }
2858
2859 static void igb_set_itr(struct igb_adapter *adapter)
2860 {
2861         u16 current_itr;
2862         u32 new_itr = adapter->itr;
2863
2864         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2865         if (adapter->link_speed != SPEED_1000) {
2866                 current_itr = 0;
2867                 new_itr = 4000;
2868                 goto set_itr_now;
2869         }
2870
2871         adapter->rx_itr = igb_update_itr(adapter,
2872                                     adapter->rx_itr,
2873                                     adapter->rx_ring->total_packets,
2874                                     adapter->rx_ring->total_bytes);
2875
2876         if (adapter->rx_ring->buddy) {
2877                 adapter->tx_itr = igb_update_itr(adapter,
2878                                             adapter->tx_itr,
2879                                             adapter->tx_ring->total_packets,
2880                                             adapter->tx_ring->total_bytes);
2881                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2882         } else {
2883                 current_itr = adapter->rx_itr;
2884         }
2885
2886         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2887         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2888                 current_itr = low_latency;
2889
2890         switch (current_itr) {
2891         /* counts and packets in update_itr are dependent on these numbers */
2892         case lowest_latency:
2893                 new_itr = 56;  /* aka 70,000 ints/sec */
2894                 break;
2895         case low_latency:
2896                 new_itr = 196; /* aka 20,000 ints/sec */
2897                 break;
2898         case bulk_latency:
2899                 new_itr = 980; /* aka 4,000 ints/sec */
2900                 break;
2901         default:
2902                 break;
2903         }
2904
2905 set_itr_now:
2906         adapter->rx_ring->total_bytes = 0;
2907         adapter->rx_ring->total_packets = 0;
2908         if (adapter->rx_ring->buddy) {
2909                 adapter->rx_ring->buddy->total_bytes = 0;
2910                 adapter->rx_ring->buddy->total_packets = 0;
2911         }
2912
2913         if (new_itr != adapter->itr) {
2914                 /* this attempts to bias the interrupt rate towards Bulk
2915                  * by adding intermediate steps when interrupt rate is
2916                  * increasing */
2917                 new_itr = new_itr > adapter->itr ?
2918                              max((new_itr * adapter->itr) /
2919                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2920                              new_itr;
2921                 /* Don't write the value here; it resets the adapter's
2922                  * internal timer, and causes us to delay far longer than
2923                  * we should between interrupts.  Instead, we write the ITR
2924                  * value at the beginning of the next interrupt so the timing
2925                  * ends up being correct.
2926                  */
2927                 adapter->itr = new_itr;
2928                 adapter->rx_ring->itr_val = new_itr;
2929                 adapter->rx_ring->set_itr = 1;
2930         }
2931
2932         return;
2933 }
2934
2935
2936 #define IGB_TX_FLAGS_CSUM               0x00000001
2937 #define IGB_TX_FLAGS_VLAN               0x00000002
2938 #define IGB_TX_FLAGS_TSO                0x00000004
2939 #define IGB_TX_FLAGS_IPV4               0x00000008
2940 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2941 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2942 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2943
2944 static inline int igb_tso_adv(struct igb_adapter *adapter,
2945                               struct igb_ring *tx_ring,
2946                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2947 {
2948         struct e1000_adv_tx_context_desc *context_desc;
2949         unsigned int i;
2950         int err;
2951         struct igb_buffer *buffer_info;
2952         u32 info = 0, tu_cmd = 0;
2953         u32 mss_l4len_idx, l4len;
2954         *hdr_len = 0;
2955
2956         if (skb_header_cloned(skb)) {
2957                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2958                 if (err)
2959                         return err;
2960         }
2961
2962         l4len = tcp_hdrlen(skb);
2963         *hdr_len += l4len;
2964
2965         if (skb->protocol == htons(ETH_P_IP)) {
2966                 struct iphdr *iph = ip_hdr(skb);
2967                 iph->tot_len = 0;
2968                 iph->check = 0;
2969                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2970                                                          iph->daddr, 0,
2971                                                          IPPROTO_TCP,
2972                                                          0);
2973         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2974                 ipv6_hdr(skb)->payload_len = 0;
2975                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2976                                                        &ipv6_hdr(skb)->daddr,
2977                                                        0, IPPROTO_TCP, 0);
2978         }
2979
2980         i = tx_ring->next_to_use;
2981
2982         buffer_info = &tx_ring->buffer_info[i];
2983         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2984         /* VLAN MACLEN IPLEN */
2985         if (tx_flags & IGB_TX_FLAGS_VLAN)
2986                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2987         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2988         *hdr_len += skb_network_offset(skb);
2989         info |= skb_network_header_len(skb);
2990         *hdr_len += skb_network_header_len(skb);
2991         context_desc->vlan_macip_lens = cpu_to_le32(info);
2992
2993         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2994         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2995
2996         if (skb->protocol == htons(ETH_P_IP))
2997                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2998         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2999
3000         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3001
3002         /* MSS L4LEN IDX */
3003         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3004         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3005
3006         /* For 82575, context index must be unique per ring. */
3007         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3008                 mss_l4len_idx |= tx_ring->queue_index << 4;
3009
3010         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3011         context_desc->seqnum_seed = 0;
3012
3013         buffer_info->time_stamp = jiffies;
3014         buffer_info->next_to_watch = i;
3015         buffer_info->dma = 0;
3016         i++;
3017         if (i == tx_ring->count)
3018                 i = 0;
3019
3020         tx_ring->next_to_use = i;
3021
3022         return true;
3023 }
3024
3025 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3026                                         struct igb_ring *tx_ring,
3027                                         struct sk_buff *skb, u32 tx_flags)
3028 {
3029         struct e1000_adv_tx_context_desc *context_desc;
3030         unsigned int i;
3031         struct igb_buffer *buffer_info;
3032         u32 info = 0, tu_cmd = 0;
3033
3034         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3035             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3036                 i = tx_ring->next_to_use;
3037                 buffer_info = &tx_ring->buffer_info[i];
3038                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3039
3040                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3041                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3042                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3043                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3044                         info |= skb_network_header_len(skb);
3045
3046                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3047
3048                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3049
3050                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3051                         __be16 protocol;
3052
3053                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3054                                 const struct vlan_ethhdr *vhdr =
3055                                           (const struct vlan_ethhdr*)skb->data;
3056
3057                                 protocol = vhdr->h_vlan_encapsulated_proto;
3058                         } else {
3059                                 protocol = skb->protocol;
3060                         }
3061
3062                         switch (protocol) {
3063                         case cpu_to_be16(ETH_P_IP):
3064                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3065                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3066                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3067                                 break;
3068                         case cpu_to_be16(ETH_P_IPV6):
3069                                 /* XXX what about other V6 headers?? */
3070                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3071                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3072                                 break;
3073                         default:
3074                                 if (unlikely(net_ratelimit()))
3075                                         dev_warn(&adapter->pdev->dev,
3076                                             "partial checksum but proto=%x!\n",
3077                                             skb->protocol);
3078                                 break;
3079                         }
3080                 }
3081
3082                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3083                 context_desc->seqnum_seed = 0;
3084                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3085                         context_desc->mss_l4len_idx =
3086                                 cpu_to_le32(tx_ring->queue_index << 4);
3087                 else
3088                         context_desc->mss_l4len_idx = 0;
3089
3090                 buffer_info->time_stamp = jiffies;
3091                 buffer_info->next_to_watch = i;
3092                 buffer_info->dma = 0;
3093
3094                 i++;
3095                 if (i == tx_ring->count)
3096                         i = 0;
3097                 tx_ring->next_to_use = i;
3098
3099                 return true;
3100         }
3101         return false;
3102 }
3103
3104 #define IGB_MAX_TXD_PWR 16
3105 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3106
3107 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3108                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3109                                  unsigned int first)
3110 {
3111         struct igb_buffer *buffer_info;
3112         unsigned int len = skb_headlen(skb);
3113         unsigned int count = 0, i;
3114         unsigned int f;
3115         dma_addr_t *map;
3116
3117         i = tx_ring->next_to_use;
3118
3119         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3120                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3121                 return 0;
3122         }
3123
3124         map = skb_shinfo(skb)->dma_maps;
3125
3126         buffer_info = &tx_ring->buffer_info[i];
3127         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3128         buffer_info->length = len;
3129         /* set time_stamp *before* dma to help avoid a possible race */
3130         buffer_info->time_stamp = jiffies;
3131         buffer_info->next_to_watch = i;
3132         buffer_info->dma = map[count];
3133         count++;
3134
3135         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3136                 struct skb_frag_struct *frag;
3137
3138                 i++;
3139                 if (i == tx_ring->count)
3140                         i = 0;
3141
3142                 frag = &skb_shinfo(skb)->frags[f];
3143                 len = frag->size;
3144
3145                 buffer_info = &tx_ring->buffer_info[i];
3146                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3147                 buffer_info->length = len;
3148                 buffer_info->time_stamp = jiffies;
3149                 buffer_info->next_to_watch = i;
3150                 buffer_info->dma = map[count];
3151                 count++;
3152         }
3153
3154         tx_ring->buffer_info[i].skb = skb;
3155         tx_ring->buffer_info[first].next_to_watch = i;
3156
3157         return count;
3158 }
3159
3160 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3161                                     struct igb_ring *tx_ring,
3162                                     int tx_flags, int count, u32 paylen,
3163                                     u8 hdr_len)
3164 {
3165         union e1000_adv_tx_desc *tx_desc = NULL;
3166         struct igb_buffer *buffer_info;
3167         u32 olinfo_status = 0, cmd_type_len;
3168         unsigned int i;
3169
3170         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3171                         E1000_ADVTXD_DCMD_DEXT);
3172
3173         if (tx_flags & IGB_TX_FLAGS_VLAN)
3174                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3175
3176         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3177                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3178
3179         if (tx_flags & IGB_TX_FLAGS_TSO) {
3180                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3181
3182                 /* insert tcp checksum */
3183                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3184
3185                 /* insert ip checksum */
3186                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3187                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3188
3189         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3190                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3191         }
3192
3193         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3194             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3195                          IGB_TX_FLAGS_VLAN)))
3196                 olinfo_status |= tx_ring->queue_index << 4;
3197
3198         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3199
3200         i = tx_ring->next_to_use;
3201         while (count--) {
3202                 buffer_info = &tx_ring->buffer_info[i];
3203                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3204                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3205                 tx_desc->read.cmd_type_len =
3206                         cpu_to_le32(cmd_type_len | buffer_info->length);
3207                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3208                 i++;
3209                 if (i == tx_ring->count)
3210                         i = 0;
3211         }
3212
3213         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3214         /* Force memory writes to complete before letting h/w
3215          * know there are new descriptors to fetch.  (Only
3216          * applicable for weak-ordered memory model archs,
3217          * such as IA-64). */
3218         wmb();
3219
3220         tx_ring->next_to_use = i;
3221         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3222         /* we need this if more than one processor can write to our tail
3223          * at a time, it syncronizes IO on IA64/Altix systems */
3224         mmiowb();
3225 }
3226
3227 static int __igb_maybe_stop_tx(struct net_device *netdev,
3228                                struct igb_ring *tx_ring, int size)
3229 {
3230         struct igb_adapter *adapter = netdev_priv(netdev);
3231
3232         netif_stop_subqueue(netdev, tx_ring->queue_index);
3233
3234         /* Herbert's original patch had:
3235          *  smp_mb__after_netif_stop_queue();
3236          * but since that doesn't exist yet, just open code it. */
3237         smp_mb();
3238
3239         /* We need to check again in a case another CPU has just
3240          * made room available. */
3241         if (igb_desc_unused(tx_ring) < size)
3242                 return -EBUSY;
3243
3244         /* A reprieve! */
3245         netif_wake_subqueue(netdev, tx_ring->queue_index);
3246         ++adapter->restart_queue;
3247         return 0;
3248 }
3249
3250 static int igb_maybe_stop_tx(struct net_device *netdev,
3251                              struct igb_ring *tx_ring, int size)
3252 {
3253         if (igb_desc_unused(tx_ring) >= size)
3254                 return 0;
3255         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3256 }
3257
3258 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3259                                    struct net_device *netdev,
3260                                    struct igb_ring *tx_ring)
3261 {
3262         struct igb_adapter *adapter = netdev_priv(netdev);
3263         unsigned int first;
3264         unsigned int tx_flags = 0;
3265         u8 hdr_len = 0;
3266         int count = 0;
3267         int tso = 0;
3268         union skb_shared_tx *shtx;
3269
3270         if (test_bit(__IGB_DOWN, &adapter->state)) {
3271                 dev_kfree_skb_any(skb);
3272                 return NETDEV_TX_OK;
3273         }
3274
3275         if (skb->len <= 0) {
3276                 dev_kfree_skb_any(skb);
3277                 return NETDEV_TX_OK;
3278         }
3279
3280         /* need: 1 descriptor per page,
3281          *       + 2 desc gap to keep tail from touching head,
3282          *       + 1 desc for skb->data,
3283          *       + 1 desc for context descriptor,
3284          * otherwise try next time */
3285         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3286                 /* this is a hard error */
3287                 return NETDEV_TX_BUSY;
3288         }
3289
3290         /*
3291          * TODO: check that there currently is no other packet with
3292          * time stamping in the queue
3293          *
3294          * When doing time stamping, keep the connection to the socket
3295          * a while longer: it is still needed by skb_hwtstamp_tx(),
3296          * called either in igb_tx_hwtstamp() or by our caller when
3297          * doing software time stamping.
3298          */
3299         shtx = skb_tx(skb);
3300         if (unlikely(shtx->hardware)) {
3301                 shtx->in_progress = 1;
3302                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3303         }
3304
3305         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3306                 tx_flags |= IGB_TX_FLAGS_VLAN;
3307                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3308         }
3309
3310         if (skb->protocol == htons(ETH_P_IP))
3311                 tx_flags |= IGB_TX_FLAGS_IPV4;
3312
3313         first = tx_ring->next_to_use;
3314         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3315                                               &hdr_len) : 0;
3316
3317         if (tso < 0) {
3318                 dev_kfree_skb_any(skb);
3319                 return NETDEV_TX_OK;
3320         }
3321
3322         if (tso)
3323                 tx_flags |= IGB_TX_FLAGS_TSO;
3324         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3325                  (skb->ip_summed == CHECKSUM_PARTIAL))
3326                 tx_flags |= IGB_TX_FLAGS_CSUM;
3327
3328         /*
3329          * count reflects descriptors mapped, if 0 then mapping error
3330          * has occured and we need to rewind the descriptor queue
3331          */
3332         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3333
3334         if (count) {
3335                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3336                                  skb->len, hdr_len);
3337                 netdev->trans_start = jiffies;
3338                 /* Make sure there is space in the ring for the next send. */
3339                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3340         } else {
3341                 dev_kfree_skb_any(skb);
3342                 tx_ring->buffer_info[first].time_stamp = 0;
3343                 tx_ring->next_to_use = first;
3344         }
3345
3346         return NETDEV_TX_OK;
3347 }
3348
3349 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3350 {
3351         struct igb_adapter *adapter = netdev_priv(netdev);
3352         struct igb_ring *tx_ring;
3353
3354         int r_idx = 0;
3355         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3356         tx_ring = adapter->multi_tx_table[r_idx];
3357
3358         /* This goes back to the question of how to logically map a tx queue
3359          * to a flow.  Right now, performance is impacted slightly negatively
3360          * if using multiple tx queues.  If the stack breaks away from a
3361          * single qdisc implementation, we can look at this again. */
3362         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3363 }
3364
3365 /**
3366  * igb_tx_timeout - Respond to a Tx Hang
3367  * @netdev: network interface device structure
3368  **/
3369 static void igb_tx_timeout(struct net_device *netdev)
3370 {
3371         struct igb_adapter *adapter = netdev_priv(netdev);
3372         struct e1000_hw *hw = &adapter->hw;
3373
3374         /* Do the reset outside of interrupt context */
3375         adapter->tx_timeout_count++;
3376         schedule_work(&adapter->reset_task);
3377         wr32(E1000_EICS,
3378              (adapter->eims_enable_mask & ~adapter->eims_other));
3379 }
3380
3381 static void igb_reset_task(struct work_struct *work)
3382 {
3383         struct igb_adapter *adapter;
3384         adapter = container_of(work, struct igb_adapter, reset_task);
3385
3386         igb_reinit_locked(adapter);
3387 }
3388
3389 /**
3390  * igb_get_stats - Get System Network Statistics
3391  * @netdev: network interface device structure
3392  *
3393  * Returns the address of the device statistics structure.
3394  * The statistics are actually updated from the timer callback.
3395  **/
3396 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3397 {
3398         struct igb_adapter *adapter = netdev_priv(netdev);
3399
3400         /* only return the current stats */
3401         return &adapter->net_stats;
3402 }
3403
3404 /**
3405  * igb_change_mtu - Change the Maximum Transfer Unit
3406  * @netdev: network interface device structure
3407  * @new_mtu: new value for maximum frame size
3408  *
3409  * Returns 0 on success, negative on failure
3410  **/
3411 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3412 {
3413         struct igb_adapter *adapter = netdev_priv(netdev);
3414         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3415
3416         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3417             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3418                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3419                 return -EINVAL;
3420         }
3421
3422         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3423                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3424                 return -EINVAL;
3425         }
3426
3427         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3428                 msleep(1);
3429
3430         /* igb_down has a dependency on max_frame_size */
3431         adapter->max_frame_size = max_frame;
3432         if (netif_running(netdev))
3433                 igb_down(adapter);
3434
3435         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3436          * means we reserve 2 more, this pushes us to allocate from the next
3437          * larger slab size.
3438          * i.e. RXBUFFER_2048 --> size-4096 slab
3439          */
3440
3441         if (max_frame <= IGB_RXBUFFER_256)
3442                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3443         else if (max_frame <= IGB_RXBUFFER_512)
3444                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3445         else if (max_frame <= IGB_RXBUFFER_1024)
3446                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3447         else if (max_frame <= IGB_RXBUFFER_2048)
3448                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3449         else
3450 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3451                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3452 #else
3453                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3454 #endif
3455
3456         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3457         if (adapter->vfs_allocated_count &&
3458             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3459                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3460
3461         /* adjust allocation if LPE protects us, and we aren't using SBP */
3462         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3463              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3464                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3465
3466         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3467                  netdev->mtu, new_mtu);
3468         netdev->mtu = new_mtu;
3469
3470         if (netif_running(netdev))
3471                 igb_up(adapter);
3472         else
3473                 igb_reset(adapter);
3474
3475         clear_bit(__IGB_RESETTING, &adapter->state);
3476
3477         return 0;
3478 }
3479
3480 /**
3481  * igb_update_stats - Update the board statistics counters
3482  * @adapter: board private structure
3483  **/
3484
3485 void igb_update_stats(struct igb_adapter *adapter)
3486 {
3487         struct e1000_hw *hw = &adapter->hw;
3488         struct pci_dev *pdev = adapter->pdev;
3489         u16 phy_tmp;
3490
3491 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3492
3493         /*
3494          * Prevent stats update while adapter is being reset, or if the pci
3495          * connection is down.
3496          */
3497         if (adapter->link_speed == 0)
3498                 return;
3499         if (pci_channel_offline(pdev))
3500                 return;
3501
3502         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3503         adapter->stats.gprc += rd32(E1000_GPRC);
3504         adapter->stats.gorc += rd32(E1000_GORCL);
3505         rd32(E1000_GORCH); /* clear GORCL */
3506         adapter->stats.bprc += rd32(E1000_BPRC);
3507         adapter->stats.mprc += rd32(E1000_MPRC);
3508         adapter->stats.roc += rd32(E1000_ROC);
3509
3510         adapter->stats.prc64 += rd32(E1000_PRC64);
3511         adapter->stats.prc127 += rd32(E1000_PRC127);
3512         adapter->stats.prc255 += rd32(E1000_PRC255);
3513         adapter->stats.prc511 += rd32(E1000_PRC511);
3514         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3515         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3516         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3517         adapter->stats.sec += rd32(E1000_SEC);
3518
3519         adapter->stats.mpc += rd32(E1000_MPC);
3520         adapter->stats.scc += rd32(E1000_SCC);
3521         adapter->stats.ecol += rd32(E1000_ECOL);
3522         adapter->stats.mcc += rd32(E1000_MCC);
3523         adapter->stats.latecol += rd32(E1000_LATECOL);
3524         adapter->stats.dc += rd32(E1000_DC);
3525         adapter->stats.rlec += rd32(E1000_RLEC);
3526         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3527         adapter->stats.xontxc += rd32(E1000_XONTXC);
3528         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3529         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3530         adapter->stats.fcruc += rd32(E1000_FCRUC);
3531         adapter->stats.gptc += rd32(E1000_GPTC);
3532         adapter->stats.gotc += rd32(E1000_GOTCL);
3533         rd32(E1000_GOTCH); /* clear GOTCL */
3534         adapter->stats.rnbc += rd32(E1000_RNBC);
3535         adapter->stats.ruc += rd32(E1000_RUC);
3536         adapter->stats.rfc += rd32(E1000_RFC);
3537         adapter->stats.rjc += rd32(E1000_RJC);
3538         adapter->stats.tor += rd32(E1000_TORH);
3539         adapter->stats.tot += rd32(E1000_TOTH);
3540         adapter->stats.tpr += rd32(E1000_TPR);
3541
3542         adapter->stats.ptc64 += rd32(E1000_PTC64);
3543         adapter->stats.ptc127 += rd32(E1000_PTC127);
3544         adapter->stats.ptc255 += rd32(E1000_PTC255);
3545         adapter->stats.ptc511 += rd32(E1000_PTC511);
3546         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3547         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3548
3549         adapter->stats.mptc += rd32(E1000_MPTC);
3550         adapter->stats.bptc += rd32(E1000_BPTC);
3551
3552         /* used for adaptive IFS */
3553
3554         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3555         adapter->stats.tpt += hw->mac.tx_packet_delta;
3556         hw->mac.collision_delta = rd32(E1000_COLC);
3557         adapter->stats.colc += hw->mac.collision_delta;
3558
3559         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3560         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3561         adapter->stats.tncrs += rd32(E1000_TNCRS);
3562         adapter->stats.tsctc += rd32(E1000_TSCTC);
3563         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3564
3565         adapter->stats.iac += rd32(E1000_IAC);
3566         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3567         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3568         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3569         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3570         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3571         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3572         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3573         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3574
3575         /* Fill out the OS statistics structure */
3576         adapter->net_stats.multicast = adapter->stats.mprc;
3577         adapter->net_stats.collisions = adapter->stats.colc;
3578
3579         /* Rx Errors */
3580
3581         /* RLEC on some newer hardware can be incorrect so build
3582         * our own version based on RUC and ROC */
3583         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3584                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3585                 adapter->stats.ruc + adapter->stats.roc +
3586                 adapter->stats.cexterr;
3587         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3588                                               adapter->stats.roc;
3589         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3590         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3591         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3592
3593         /* Tx Errors */
3594         adapter->net_stats.tx_errors = adapter->stats.ecol +
3595                                        adapter->stats.latecol;
3596         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3597         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3598         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3599
3600         /* Tx Dropped needs to be maintained elsewhere */
3601
3602         /* Phy Stats */
3603         if (hw->phy.media_type == e1000_media_type_copper) {
3604                 if ((adapter->link_speed == SPEED_1000) &&
3605                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3606                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3607                         adapter->phy_stats.idle_errors += phy_tmp;
3608                 }
3609         }
3610
3611         /* Management Stats */
3612         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3613         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3614         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3615 }
3616
3617 static irqreturn_t igb_msix_other(int irq, void *data)
3618 {
3619         struct net_device *netdev = data;
3620         struct igb_adapter *adapter = netdev_priv(netdev);
3621         struct e1000_hw *hw = &adapter->hw;
3622         u32 icr = rd32(E1000_ICR);
3623
3624         /* reading ICR causes bit 31 of EICR to be cleared */
3625
3626         if(icr & E1000_ICR_DOUTSYNC) {
3627                 /* HW is reporting DMA is out of sync */
3628                 adapter->stats.doosync++;
3629         }
3630
3631         /* Check for a mailbox event */
3632         if (icr & E1000_ICR_VMMB)
3633                 igb_msg_task(adapter);
3634
3635         if (icr & E1000_ICR_LSC) {
3636                 hw->mac.get_link_status = 1;
3637                 /* guard against interrupt when we're going down */
3638                 if (!test_bit(__IGB_DOWN, &adapter->state))
3639                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3640         }
3641
3642         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3643         wr32(E1000_EIMS, adapter->eims_other);
3644
3645         return IRQ_HANDLED;
3646 }
3647
3648 static irqreturn_t igb_msix_tx(int irq, void *data)
3649 {
3650         struct igb_ring *tx_ring = data;
3651         struct igb_adapter *adapter = tx_ring->adapter;
3652         struct e1000_hw *hw = &adapter->hw;
3653
3654 #ifdef CONFIG_IGB_DCA
3655         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3656                 igb_update_tx_dca(tx_ring);
3657 #endif
3658
3659         tx_ring->total_bytes = 0;
3660         tx_ring->total_packets = 0;
3661
3662         /* auto mask will automatically reenable the interrupt when we write
3663          * EICS */
3664         if (!igb_clean_tx_irq(tx_ring))
3665                 /* Ring was not completely cleaned, so fire another interrupt */
3666                 wr32(E1000_EICS, tx_ring->eims_value);
3667         else
3668                 wr32(E1000_EIMS, tx_ring->eims_value);
3669
3670         return IRQ_HANDLED;
3671 }
3672
3673 static void igb_write_itr(struct igb_ring *ring)
3674 {
3675         struct e1000_hw *hw = &ring->adapter->hw;
3676         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3677                 switch (hw->mac.type) {
3678                 case e1000_82576:
3679                         wr32(ring->itr_register, ring->itr_val |
3680                              0x80000000);
3681                         break;
3682                 default:
3683                         wr32(ring->itr_register, ring->itr_val |
3684                              (ring->itr_val << 16));
3685                         break;
3686                 }
3687                 ring->set_itr = 0;
3688         }
3689 }
3690
3691 static irqreturn_t igb_msix_rx(int irq, void *data)
3692 {
3693         struct igb_ring *rx_ring = data;
3694
3695         /* Write the ITR value calculated at the end of the
3696          * previous interrupt.
3697          */
3698
3699         igb_write_itr(rx_ring);
3700
3701         if (napi_schedule_prep(&rx_ring->napi))
3702                 __napi_schedule(&rx_ring->napi);
3703
3704 #ifdef CONFIG_IGB_DCA
3705         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3706                 igb_update_rx_dca(rx_ring);
3707 #endif
3708                 return IRQ_HANDLED;
3709 }
3710
3711 #ifdef CONFIG_IGB_DCA
3712 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3713 {
3714         u32 dca_rxctrl;
3715         struct igb_adapter *adapter = rx_ring->adapter;
3716         struct e1000_hw *hw = &adapter->hw;
3717         int cpu = get_cpu();
3718         int q = rx_ring->reg_idx;
3719
3720         if (rx_ring->cpu != cpu) {
3721                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3722                 if (hw->mac.type == e1000_82576) {
3723                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3724                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3725                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3726                 } else {
3727                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3728                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3729                 }
3730                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3731                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3732                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3733                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3734                 rx_ring->cpu = cpu;
3735         }
3736         put_cpu();
3737 }
3738
3739 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3740 {
3741         u32 dca_txctrl;
3742         struct igb_adapter *adapter = tx_ring->adapter;
3743         struct e1000_hw *hw = &adapter->hw;
3744         int cpu = get_cpu();
3745         int q = tx_ring->reg_idx;
3746
3747         if (tx_ring->cpu != cpu) {
3748                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3749                 if (hw->mac.type == e1000_82576) {
3750                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3751                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3752                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3753                 } else {
3754                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3755                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3756                 }
3757                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3758                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3759                 tx_ring->cpu = cpu;
3760         }
3761         put_cpu();
3762 }
3763
3764 static void igb_setup_dca(struct igb_adapter *adapter)
3765 {
3766         int i;
3767
3768         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3769                 return;
3770
3771         for (i = 0; i < adapter->num_tx_queues; i++) {
3772                 adapter->tx_ring[i].cpu = -1;
3773                 igb_update_tx_dca(&adapter->tx_ring[i]);
3774         }
3775         for (i = 0; i < adapter->num_rx_queues; i++) {
3776                 adapter->rx_ring[i].cpu = -1;
3777                 igb_update_rx_dca(&adapter->rx_ring[i]);
3778         }
3779 }
3780
3781 static int __igb_notify_dca(struct device *dev, void *data)
3782 {
3783         struct net_device *netdev = dev_get_drvdata(dev);
3784         struct igb_adapter *adapter = netdev_priv(netdev);
3785         struct e1000_hw *hw = &adapter->hw;
3786         unsigned long event = *(unsigned long *)data;
3787
3788         switch (event) {
3789         case DCA_PROVIDER_ADD:
3790                 /* if already enabled, don't do it again */
3791                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3792                         break;
3793                 /* Always use CB2 mode, difference is masked
3794                  * in the CB driver. */
3795                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3796                 if (dca_add_requester(dev) == 0) {
3797                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3798                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3799                         igb_setup_dca(adapter);
3800                         break;
3801                 }
3802                 /* Fall Through since DCA is disabled. */
3803         case DCA_PROVIDER_REMOVE:
3804                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3805                         /* without this a class_device is left
3806                          * hanging around in the sysfs model */
3807                         dca_remove_requester(dev);
3808                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3809                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3810                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3811                 }
3812                 break;
3813         }
3814
3815         return 0;
3816 }
3817
3818 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3819                           void *p)
3820 {
3821         int ret_val;
3822
3823         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3824                                          __igb_notify_dca);
3825
3826         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3827 }
3828 #endif /* CONFIG_IGB_DCA */
3829
3830 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3831 {
3832         struct e1000_hw *hw = &adapter->hw;
3833         u32 ping;
3834         int i;
3835
3836         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3837                 ping = E1000_PF_CONTROL_MSG;
3838                 if (adapter->vf_data[i].clear_to_send)
3839                         ping |= E1000_VT_MSGTYPE_CTS;
3840                 igb_write_mbx(hw, &ping, 1, i);
3841         }
3842 }
3843
3844 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3845                                   u32 *msgbuf, u32 vf)
3846 {
3847         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3848         u16 *hash_list = (u16 *)&msgbuf[1];
3849         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3850         int i;
3851
3852         /* only up to 30 hash values supported */
3853         if (n > 30)
3854                 n = 30;
3855
3856         /* salt away the number of multi cast addresses assigned
3857          * to this VF for later use to restore when the PF multi cast
3858          * list changes
3859          */
3860         vf_data->num_vf_mc_hashes = n;
3861
3862         /* VFs are limited to using the MTA hash table for their multicast
3863          * addresses */
3864         for (i = 0; i < n; i++)
3865                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3866
3867         /* Flush and reset the mta with the new values */
3868         igb_set_multi(adapter->netdev);
3869
3870         return 0;
3871 }
3872
3873 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3874 {
3875         struct e1000_hw *hw = &adapter->hw;
3876         struct vf_data_storage *vf_data;
3877         int i, j;
3878
3879         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3880                 vf_data = &adapter->vf_data[i];
3881                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3882                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3883         }
3884 }
3885
3886 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3887 {
3888         struct e1000_hw *hw = &adapter->hw;
3889         u32 pool_mask, reg, vid;
3890         int i;
3891
3892         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3893
3894         /* Find the vlan filter for this id */
3895         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3896                 reg = rd32(E1000_VLVF(i));
3897
3898                 /* remove the vf from the pool */
3899                 reg &= ~pool_mask;
3900
3901                 /* if pool is empty then remove entry from vfta */
3902                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3903                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3904                         reg = 0;
3905                         vid = reg & E1000_VLVF_VLANID_MASK;
3906                         igb_vfta_set(hw, vid, false);
3907                 }
3908
3909                 wr32(E1000_VLVF(i), reg);
3910         }
3911 }
3912
3913 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3914 {
3915         struct e1000_hw *hw = &adapter->hw;
3916         u32 reg, i;
3917
3918         /* It is an error to call this function when VFs are not enabled */
3919         if (!adapter->vfs_allocated_count)
3920                 return -1;
3921
3922         /* Find the vlan filter for this id */
3923         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3924                 reg = rd32(E1000_VLVF(i));
3925                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3926                     vid == (reg & E1000_VLVF_VLANID_MASK))
3927                         break;
3928         }
3929
3930         if (add) {
3931                 if (i == E1000_VLVF_ARRAY_SIZE) {
3932                         /* Did not find a matching VLAN ID entry that was
3933                          * enabled.  Search for a free filter entry, i.e.
3934                          * one without the enable bit set
3935                          */
3936                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3937                                 reg = rd32(E1000_VLVF(i));
3938                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3939                                         break;
3940                         }
3941                 }
3942                 if (i < E1000_VLVF_ARRAY_SIZE) {
3943                         /* Found an enabled/available entry */
3944                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3945
3946                         /* if !enabled we need to set this up in vfta */
3947                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3948                                 /* add VID to filter table, if bit already set
3949                                  * PF must have added it outside of table */
3950                                 if (igb_vfta_set(hw, vid, true))
3951                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3952                                                 adapter->vfs_allocated_count);
3953                                 reg |= E1000_VLVF_VLANID_ENABLE;
3954                         }
3955                         reg &= ~E1000_VLVF_VLANID_MASK;
3956                         reg |= vid;
3957
3958                         wr32(E1000_VLVF(i), reg);
3959                         return 0;
3960                 }
3961         } else {
3962                 if (i < E1000_VLVF_ARRAY_SIZE) {
3963                         /* remove vf from the pool */
3964                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3965                         /* if pool is empty then remove entry from vfta */
3966                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3967                                 reg = 0;
3968                                 igb_vfta_set(hw, vid, false);
3969                         }
3970                         wr32(E1000_VLVF(i), reg);
3971                         return 0;
3972                 }
3973         }
3974         return -1;
3975 }
3976
3977 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3978 {
3979         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3980         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3981
3982         return igb_vlvf_set(adapter, vid, add, vf);
3983 }
3984
3985 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3986 {
3987         struct e1000_hw *hw = &adapter->hw;
3988
3989         /* disable mailbox functionality for vf */
3990         adapter->vf_data[vf].clear_to_send = false;
3991
3992         /* reset offloads to defaults */
3993         igb_set_vmolr(hw, vf);
3994
3995         /* reset vlans for device */
3996         igb_clear_vf_vfta(adapter, vf);
3997
3998         /* reset multicast table array for vf */
3999         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4000
4001         /* Flush and reset the mta with the new values */
4002         igb_set_multi(adapter->netdev);
4003 }
4004
4005 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4006 {
4007         struct e1000_hw *hw = &adapter->hw;
4008         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4009         u32 reg, msgbuf[3];
4010         u8 *addr = (u8 *)(&msgbuf[1]);
4011
4012         /* process all the same items cleared in a function level reset */
4013         igb_vf_reset_event(adapter, vf);
4014
4015         /* set vf mac address */
4016         igb_rar_set(hw, vf_mac, vf + 1);
4017         igb_set_rah_pool(hw, vf, vf + 1);
4018
4019         /* enable transmit and receive for vf */
4020         reg = rd32(E1000_VFTE);
4021         wr32(E1000_VFTE, reg | (1 << vf));
4022         reg = rd32(E1000_VFRE);
4023         wr32(E1000_VFRE, reg | (1 << vf));
4024
4025         /* enable mailbox functionality for vf */
4026         adapter->vf_data[vf].clear_to_send = true;
4027
4028         /* reply to reset with ack and vf mac address */
4029         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4030         memcpy(addr, vf_mac, 6);
4031         igb_write_mbx(hw, msgbuf, 3, vf);
4032 }
4033
4034 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4035 {
4036                 unsigned char *addr = (char *)&msg[1];
4037                 int err = -1;
4038
4039                 if (is_valid_ether_addr(addr))
4040                         err = igb_set_vf_mac(adapter, vf, addr);
4041
4042                 return err;
4043
4044 }
4045
4046 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4047 {
4048         struct e1000_hw *hw = &adapter->hw;
4049         u32 msg = E1000_VT_MSGTYPE_NACK;
4050
4051         /* if device isn't clear to send it shouldn't be reading either */
4052         if (!adapter->vf_data[vf].clear_to_send)
4053                 igb_write_mbx(hw, &msg, 1, vf);
4054 }
4055
4056
4057 static void igb_msg_task(struct igb_adapter *adapter)
4058 {
4059         struct e1000_hw *hw = &adapter->hw;
4060         u32 vf;
4061
4062         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4063                 /* process any reset requests */
4064                 if (!igb_check_for_rst(hw, vf)) {
4065                         adapter->vf_data[vf].clear_to_send = false;
4066                         igb_vf_reset_event(adapter, vf);
4067                 }
4068
4069                 /* process any messages pending */
4070                 if (!igb_check_for_msg(hw, vf))
4071                         igb_rcv_msg_from_vf(adapter, vf);
4072
4073                 /* process any acks */
4074                 if (!igb_check_for_ack(hw, vf))
4075                         igb_rcv_ack_from_vf(adapter, vf);
4076
4077         }
4078 }
4079
4080 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4081 {
4082         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4083         u32 msgbuf[mbx_size];
4084         struct e1000_hw *hw = &adapter->hw;
4085         s32 retval;
4086
4087         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4088
4089         if (retval)
4090                 dev_err(&adapter->pdev->dev,
4091                         "Error receiving message from VF\n");
4092
4093         /* this is a message we already processed, do nothing */
4094         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4095                 return retval;
4096
4097         /*
4098          * until the vf completes a reset it should not be
4099          * allowed to start any configuration.
4100          */
4101
4102         if (msgbuf[0] == E1000_VF_RESET) {
4103                 igb_vf_reset_msg(adapter, vf);
4104
4105                 return retval;
4106         }
4107
4108         if (!adapter->vf_data[vf].clear_to_send) {
4109                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4110                 igb_write_mbx(hw, msgbuf, 1, vf);
4111                 return retval;
4112         }
4113
4114         switch ((msgbuf[0] & 0xFFFF)) {
4115         case E1000_VF_SET_MAC_ADDR:
4116                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4117                 break;
4118         case E1000_VF_SET_MULTICAST:
4119                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4120                 break;
4121         case E1000_VF_SET_LPE:
4122                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4123                 break;
4124         case E1000_VF_SET_VLAN:
4125                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4126                 break;
4127         default:
4128                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4129                 retval = -1;
4130                 break;
4131         }
4132
4133         /* notify the VF of the results of what it sent us */
4134         if (retval)
4135                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4136         else
4137                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4138
4139         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4140
4141         igb_write_mbx(hw, msgbuf, 1, vf);
4142
4143         return retval;
4144 }
4145
4146 /**
4147  * igb_intr_msi - Interrupt Handler
4148  * @irq: interrupt number
4149  * @data: pointer to a network interface device structure
4150  **/
4151 static irqreturn_t igb_intr_msi(int irq, void *data)
4152 {
4153         struct net_device *netdev = data;
4154         struct igb_adapter *adapter = netdev_priv(netdev);
4155         struct e1000_hw *hw = &adapter->hw;
4156         /* read ICR disables interrupts using IAM */
4157         u32 icr = rd32(E1000_ICR);
4158
4159         igb_write_itr(adapter->rx_ring);
4160
4161         if(icr & E1000_ICR_DOUTSYNC) {
4162                 /* HW is reporting DMA is out of sync */
4163                 adapter->stats.doosync++;
4164         }
4165
4166         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4167                 hw->mac.get_link_status = 1;
4168                 if (!test_bit(__IGB_DOWN, &adapter->state))
4169                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4170         }
4171
4172         napi_schedule(&adapter->rx_ring[0].napi);
4173
4174         return IRQ_HANDLED;
4175 }
4176
4177 /**
4178  * igb_intr - Legacy Interrupt Handler
4179  * @irq: interrupt number
4180  * @data: pointer to a network interface device structure
4181  **/
4182 static irqreturn_t igb_intr(int irq, void *data)
4183 {
4184         struct net_device *netdev = data;
4185         struct igb_adapter *adapter = netdev_priv(netdev);
4186         struct e1000_hw *hw = &adapter->hw;
4187         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4188          * need for the IMC write */
4189         u32 icr = rd32(E1000_ICR);
4190         if (!icr)
4191                 return IRQ_NONE;  /* Not our interrupt */
4192
4193         igb_write_itr(adapter->rx_ring);
4194
4195         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4196          * not set, then the adapter didn't send an interrupt */
4197         if (!(icr & E1000_ICR_INT_ASSERTED))
4198                 return IRQ_NONE;
4199
4200         if(icr & E1000_ICR_DOUTSYNC) {
4201                 /* HW is reporting DMA is out of sync */
4202                 adapter->stats.doosync++;
4203         }
4204
4205         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4206                 hw->mac.get_link_status = 1;
4207                 /* guard against interrupt when we're going down */
4208                 if (!test_bit(__IGB_DOWN, &adapter->state))
4209                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4210         }
4211
4212         napi_schedule(&adapter->rx_ring[0].napi);
4213
4214         return IRQ_HANDLED;
4215 }
4216
4217 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4218 {
4219         struct igb_adapter *adapter = rx_ring->adapter;
4220         struct e1000_hw *hw = &adapter->hw;
4221
4222         if (adapter->itr_setting & 3) {
4223                 if (adapter->num_rx_queues == 1)
4224                         igb_set_itr(adapter);
4225                 else
4226                         igb_update_ring_itr(rx_ring);
4227         }
4228
4229         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4230                 if (adapter->msix_entries)
4231                         wr32(E1000_EIMS, rx_ring->eims_value);
4232                 else
4233                         igb_irq_enable(adapter);
4234         }
4235 }
4236
4237 /**
4238  * igb_poll - NAPI Rx polling callback
4239  * @napi: napi polling structure
4240  * @budget: count of how many packets we should handle
4241  **/
4242 static int igb_poll(struct napi_struct *napi, int budget)
4243 {
4244         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4245         int work_done = 0;
4246
4247 #ifdef CONFIG_IGB_DCA
4248         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4249                 igb_update_rx_dca(rx_ring);
4250 #endif
4251         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4252
4253         if (rx_ring->buddy) {
4254 #ifdef CONFIG_IGB_DCA
4255                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4256                         igb_update_tx_dca(rx_ring->buddy);
4257 #endif
4258                 if (!igb_clean_tx_irq(rx_ring->buddy))
4259                         work_done = budget;
4260         }
4261
4262         /* If not enough Rx work done, exit the polling mode */
4263         if (work_done < budget) {
4264                 napi_complete(napi);
4265                 igb_rx_irq_enable(rx_ring);
4266         }
4267
4268         return work_done;
4269 }
4270
4271 /**
4272  * igb_hwtstamp - utility function which checks for TX time stamp
4273  * @adapter: board private structure
4274  * @skb: packet that was just sent
4275  *
4276  * If we were asked to do hardware stamping and such a time stamp is
4277  * available, then it must have been for this skb here because we only
4278  * allow only one such packet into the queue.
4279  */
4280 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4281 {
4282         union skb_shared_tx *shtx = skb_tx(skb);
4283         struct e1000_hw *hw = &adapter->hw;
4284
4285         if (unlikely(shtx->hardware)) {
4286                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4287                 if (valid) {
4288                         u64 regval = rd32(E1000_TXSTMPL);
4289                         u64 ns;
4290                         struct skb_shared_hwtstamps shhwtstamps;
4291
4292                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4293                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4294                         ns = timecounter_cyc2time(&adapter->clock,
4295                                                   regval);
4296                         timecompare_update(&adapter->compare, ns);
4297                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4298                         shhwtstamps.syststamp =
4299                                 timecompare_transform(&adapter->compare, ns);
4300                         skb_tstamp_tx(skb, &shhwtstamps);
4301                 }
4302         }
4303 }
4304
4305 /**
4306  * igb_clean_tx_irq - Reclaim resources after transmit completes
4307  * @adapter: board private structure
4308  * returns true if ring is completely cleaned
4309  **/
4310 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4311 {
4312         struct igb_adapter *adapter = tx_ring->adapter;
4313         struct net_device *netdev = adapter->netdev;
4314         struct e1000_hw *hw = &adapter->hw;
4315         struct igb_buffer *buffer_info;
4316         struct sk_buff *skb;
4317         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4318         unsigned int total_bytes = 0, total_packets = 0;
4319         unsigned int i, eop, count = 0;
4320         bool cleaned = false;
4321
4322         i = tx_ring->next_to_clean;
4323         eop = tx_ring->buffer_info[i].next_to_watch;
4324         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4325
4326         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4327                (count < tx_ring->count)) {
4328                 for (cleaned = false; !cleaned; count++) {
4329                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4330                         buffer_info = &tx_ring->buffer_info[i];
4331                         cleaned = (i == eop);
4332                         skb = buffer_info->skb;
4333
4334                         if (skb) {
4335                                 unsigned int segs, bytecount;
4336                                 /* gso_segs is currently only valid for tcp */
4337                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4338                                 /* multiply data chunks by size of headers */
4339                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4340                                             skb->len;
4341                                 total_packets += segs;
4342                                 total_bytes += bytecount;
4343
4344                                 igb_tx_hwtstamp(adapter, skb);
4345                         }
4346
4347                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4348                         tx_desc->wb.status = 0;
4349
4350                         i++;
4351                         if (i == tx_ring->count)
4352                                 i = 0;
4353                 }
4354                 eop = tx_ring->buffer_info[i].next_to_watch;
4355                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4356         }
4357
4358         tx_ring->next_to_clean = i;
4359
4360         if (unlikely(count &&
4361                      netif_carrier_ok(netdev) &&
4362                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4363                 /* Make sure that anybody stopping the queue after this
4364                  * sees the new next_to_clean.
4365                  */
4366                 smp_mb();
4367                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4368                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4369                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4370                         ++adapter->restart_queue;
4371                 }
4372         }
4373
4374         if (tx_ring->detect_tx_hung) {
4375                 /* Detect a transmit hang in hardware, this serializes the
4376                  * check with the clearing of time_stamp and movement of i */
4377                 tx_ring->detect_tx_hung = false;
4378                 if (tx_ring->buffer_info[i].time_stamp &&
4379                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4380                                (adapter->tx_timeout_factor * HZ))
4381                     && !(rd32(E1000_STATUS) &
4382                          E1000_STATUS_TXOFF)) {
4383
4384                         /* detected Tx unit hang */
4385                         dev_err(&adapter->pdev->dev,
4386                                 "Detected Tx Unit Hang\n"
4387                                 "  Tx Queue             <%d>\n"
4388                                 "  TDH                  <%x>\n"
4389                                 "  TDT                  <%x>\n"
4390                                 "  next_to_use          <%x>\n"
4391                                 "  next_to_clean        <%x>\n"
4392                                 "buffer_info[next_to_clean]\n"
4393                                 "  time_stamp           <%lx>\n"
4394                                 "  next_to_watch        <%x>\n"
4395                                 "  jiffies              <%lx>\n"
4396                                 "  desc.status          <%x>\n",
4397                                 tx_ring->queue_index,
4398                                 readl(adapter->hw.hw_addr + tx_ring->head),
4399                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4400                                 tx_ring->next_to_use,
4401                                 tx_ring->next_to_clean,
4402                                 tx_ring->buffer_info[i].time_stamp,
4403                                 eop,
4404                                 jiffies,
4405                                 eop_desc->wb.status);
4406                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4407                 }
4408         }
4409         tx_ring->total_bytes += total_bytes;
4410         tx_ring->total_packets += total_packets;
4411         tx_ring->tx_stats.bytes += total_bytes;
4412         tx_ring->tx_stats.packets += total_packets;
4413         adapter->net_stats.tx_bytes += total_bytes;
4414         adapter->net_stats.tx_packets += total_packets;
4415         return (count < tx_ring->count);
4416 }
4417
4418 /**
4419  * igb_receive_skb - helper function to handle rx indications
4420  * @ring: pointer to receive ring receving this packet
4421  * @status: descriptor status field as written by hardware
4422  * @rx_desc: receive descriptor containing vlan and type information.
4423  * @skb: pointer to sk_buff to be indicated to stack
4424  **/
4425 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4426                             union e1000_adv_rx_desc * rx_desc,
4427                             struct sk_buff *skb)
4428 {
4429         struct igb_adapter * adapter = ring->adapter;
4430         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4431
4432         skb_record_rx_queue(skb, ring->queue_index);
4433         if (vlan_extracted)
4434                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4435                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4436                                  skb);
4437         else
4438                 napi_gro_receive(&ring->napi, skb);
4439 }
4440
4441 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4442                                        u32 status_err, struct sk_buff *skb)
4443 {
4444         skb->ip_summed = CHECKSUM_NONE;
4445
4446         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4447         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4448                 return;
4449         /* TCP/UDP checksum error bit is set */
4450         if (status_err &
4451             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4452                 /* let the stack verify checksum errors */
4453                 adapter->hw_csum_err++;
4454                 return;
4455         }
4456         /* It must be a TCP or UDP packet with a valid checksum */
4457         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4458                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4459
4460         adapter->hw_csum_good++;
4461 }
4462
4463 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4464                                  int *work_done, int budget)
4465 {
4466         struct igb_adapter *adapter = rx_ring->adapter;
4467         struct net_device *netdev = adapter->netdev;
4468         struct e1000_hw *hw = &adapter->hw;
4469         struct pci_dev *pdev = adapter->pdev;
4470         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4471         struct igb_buffer *buffer_info , *next_buffer;
4472         struct sk_buff *skb;
4473         bool cleaned = false;
4474         int cleaned_count = 0;
4475         unsigned int total_bytes = 0, total_packets = 0;
4476         unsigned int i;
4477         u32 length, hlen, staterr;
4478
4479         i = rx_ring->next_to_clean;
4480         buffer_info = &rx_ring->buffer_info[i];
4481         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4482         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4483
4484         while (staterr & E1000_RXD_STAT_DD) {
4485                 if (*work_done >= budget)
4486                         break;
4487                 (*work_done)++;
4488
4489                 skb = buffer_info->skb;
4490                 prefetch(skb->data - NET_IP_ALIGN);
4491                 buffer_info->skb = NULL;
4492
4493                 i++;
4494                 if (i == rx_ring->count)
4495                         i = 0;
4496                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4497                 prefetch(next_rxd);
4498                 next_buffer = &rx_ring->buffer_info[i];
4499
4500                 length = le16_to_cpu(rx_desc->wb.upper.length);
4501                 cleaned = true;
4502                 cleaned_count++;
4503
4504                 if (!adapter->rx_ps_hdr_size) {
4505                         pci_unmap_single(pdev, buffer_info->dma,
4506                                          adapter->rx_buffer_len +
4507                                            NET_IP_ALIGN,
4508                                          PCI_DMA_FROMDEVICE);
4509                         skb_put(skb, length);
4510                         goto send_up;
4511                 }
4512
4513                 /* HW will not DMA in data larger than the given buffer, even
4514                  * if it parses the (NFS, of course) header to be larger.  In
4515                  * that case, it fills the header buffer and spills the rest
4516                  * into the page.
4517                  */
4518                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4519                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4520                 if (hlen > adapter->rx_ps_hdr_size)
4521                         hlen = adapter->rx_ps_hdr_size;
4522
4523                 if (!skb_shinfo(skb)->nr_frags) {
4524                         pci_unmap_single(pdev, buffer_info->dma,
4525                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4526                                          PCI_DMA_FROMDEVICE);
4527                         skb_put(skb, hlen);
4528                 }
4529
4530                 if (length) {
4531                         pci_unmap_page(pdev, buffer_info->page_dma,
4532                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4533                         buffer_info->page_dma = 0;
4534
4535                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4536                                                 buffer_info->page,
4537                                                 buffer_info->page_offset,
4538                                                 length);
4539
4540                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4541                             (page_count(buffer_info->page) != 1))
4542                                 buffer_info->page = NULL;
4543                         else
4544                                 get_page(buffer_info->page);
4545
4546                         skb->len += length;
4547                         skb->data_len += length;
4548
4549                         skb->truesize += length;
4550                 }
4551
4552                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4553                         buffer_info->skb = next_buffer->skb;
4554                         buffer_info->dma = next_buffer->dma;
4555                         next_buffer->skb = skb;
4556                         next_buffer->dma = 0;
4557                         goto next_desc;
4558                 }
4559 send_up:
4560                 /*
4561                  * If this bit is set, then the RX registers contain
4562                  * the time stamp. No other packet will be time
4563                  * stamped until we read these registers, so read the
4564                  * registers to make them available again. Because
4565                  * only one packet can be time stamped at a time, we
4566                  * know that the register values must belong to this
4567                  * one here and therefore we don't need to compare
4568                  * any of the additional attributes stored for it.
4569                  *
4570                  * If nothing went wrong, then it should have a
4571                  * skb_shared_tx that we can turn into a
4572                  * skb_shared_hwtstamps.
4573                  *
4574                  * TODO: can time stamping be triggered (thus locking
4575                  * the registers) without the packet reaching this point
4576                  * here? In that case RX time stamping would get stuck.
4577                  *
4578                  * TODO: in "time stamp all packets" mode this bit is
4579                  * not set. Need a global flag for this mode and then
4580                  * always read the registers. Cannot be done without
4581                  * a race condition.
4582                  */
4583                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4584                         u64 regval;
4585                         u64 ns;
4586                         struct skb_shared_hwtstamps *shhwtstamps =
4587                                 skb_hwtstamps(skb);
4588
4589                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4590                              "igb: no RX time stamp available for time stamped packet");
4591                         regval = rd32(E1000_RXSTMPL);
4592                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4593                         ns = timecounter_cyc2time(&adapter->clock, regval);
4594                         timecompare_update(&adapter->compare, ns);
4595                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4596                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4597                         shhwtstamps->syststamp =
4598                                 timecompare_transform(&adapter->compare, ns);
4599                 }
4600
4601                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4602                         dev_kfree_skb_irq(skb);
4603                         goto next_desc;
4604                 }
4605
4606                 total_bytes += skb->len;
4607                 total_packets++;
4608
4609                 igb_rx_checksum_adv(adapter, staterr, skb);
4610
4611                 skb->protocol = eth_type_trans(skb, netdev);
4612
4613                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4614
4615 next_desc:
4616                 rx_desc->wb.upper.status_error = 0;
4617
4618                 /* return some buffers to hardware, one at a time is too slow */
4619                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4620                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4621                         cleaned_count = 0;
4622                 }
4623
4624                 /* use prefetched values */
4625                 rx_desc = next_rxd;
4626                 buffer_info = next_buffer;
4627                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4628         }
4629
4630         rx_ring->next_to_clean = i;
4631         cleaned_count = igb_desc_unused(rx_ring);
4632
4633         if (cleaned_count)
4634                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4635
4636         rx_ring->total_packets += total_packets;
4637         rx_ring->total_bytes += total_bytes;
4638         rx_ring->rx_stats.packets += total_packets;
4639         rx_ring->rx_stats.bytes += total_bytes;
4640         adapter->net_stats.rx_bytes += total_bytes;
4641         adapter->net_stats.rx_packets += total_packets;
4642         return cleaned;
4643 }
4644
4645 /**
4646  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4647  * @adapter: address of board private structure
4648  **/
4649 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4650                                      int cleaned_count)
4651 {
4652         struct igb_adapter *adapter = rx_ring->adapter;
4653         struct net_device *netdev = adapter->netdev;
4654         struct pci_dev *pdev = adapter->pdev;
4655         union e1000_adv_rx_desc *rx_desc;
4656         struct igb_buffer *buffer_info;
4657         struct sk_buff *skb;
4658         unsigned int i;
4659         int bufsz;
4660
4661         i = rx_ring->next_to_use;
4662         buffer_info = &rx_ring->buffer_info[i];
4663
4664         if (adapter->rx_ps_hdr_size)
4665                 bufsz = adapter->rx_ps_hdr_size;
4666         else
4667                 bufsz = adapter->rx_buffer_len;
4668         bufsz += NET_IP_ALIGN;
4669
4670         while (cleaned_count--) {
4671                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4672
4673                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4674                         if (!buffer_info->page) {
4675                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4676                                 if (!buffer_info->page) {
4677                                         adapter->alloc_rx_buff_failed++;
4678                                         goto no_buffers;
4679                                 }
4680                                 buffer_info->page_offset = 0;
4681                         } else {
4682                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4683                         }
4684                         buffer_info->page_dma =
4685                                 pci_map_page(pdev, buffer_info->page,
4686                                              buffer_info->page_offset,
4687                                              PAGE_SIZE / 2,
4688                                              PCI_DMA_FROMDEVICE);
4689                 }
4690
4691                 if (!buffer_info->skb) {
4692                         skb = netdev_alloc_skb(netdev, bufsz);
4693                         if (!skb) {
4694                                 adapter->alloc_rx_buff_failed++;
4695                                 goto no_buffers;
4696                         }
4697
4698                         /* Make buffer alignment 2 beyond a 16 byte boundary
4699                          * this will result in a 16 byte aligned IP header after
4700                          * the 14 byte MAC header is removed
4701                          */
4702                         skb_reserve(skb, NET_IP_ALIGN);
4703
4704                         buffer_info->skb = skb;
4705                         buffer_info->dma = pci_map_single(pdev, skb->data,
4706                                                           bufsz,
4707                                                           PCI_DMA_FROMDEVICE);
4708                 }
4709                 /* Refresh the desc even if buffer_addrs didn't change because
4710                  * each write-back erases this info. */
4711                 if (adapter->rx_ps_hdr_size) {
4712                         rx_desc->read.pkt_addr =
4713                              cpu_to_le64(buffer_info->page_dma);
4714                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4715                 } else {
4716                         rx_desc->read.pkt_addr =
4717                              cpu_to_le64(buffer_info->dma);
4718                         rx_desc->read.hdr_addr = 0;
4719                 }
4720
4721                 i++;
4722                 if (i == rx_ring->count)
4723                         i = 0;
4724                 buffer_info = &rx_ring->buffer_info[i];
4725         }
4726
4727 no_buffers:
4728         if (rx_ring->next_to_use != i) {
4729                 rx_ring->next_to_use = i;
4730                 if (i == 0)
4731                         i = (rx_ring->count - 1);
4732                 else
4733                         i--;
4734
4735                 /* Force memory writes to complete before letting h/w
4736                  * know there are new descriptors to fetch.  (Only
4737                  * applicable for weak-ordered memory model archs,
4738                  * such as IA-64). */
4739                 wmb();
4740                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4741         }
4742 }
4743
4744 /**
4745  * igb_mii_ioctl -
4746  * @netdev:
4747  * @ifreq:
4748  * @cmd:
4749  **/
4750 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4751 {
4752         struct igb_adapter *adapter = netdev_priv(netdev);
4753         struct mii_ioctl_data *data = if_mii(ifr);
4754
4755         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4756                 return -EOPNOTSUPP;
4757
4758         switch (cmd) {
4759         case SIOCGMIIPHY:
4760                 data->phy_id = adapter->hw.phy.addr;
4761                 break;
4762         case SIOCGMIIREG:
4763                 if (!capable(CAP_NET_ADMIN))
4764                         return -EPERM;
4765                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4766                                      &data->val_out))
4767                         return -EIO;
4768                 break;
4769         case SIOCSMIIREG:
4770         default:
4771                 return -EOPNOTSUPP;
4772         }
4773         return 0;
4774 }
4775
4776 /**
4777  * igb_hwtstamp_ioctl - control hardware time stamping
4778  * @netdev:
4779  * @ifreq:
4780  * @cmd:
4781  *
4782  * Outgoing time stamping can be enabled and disabled. Play nice and
4783  * disable it when requested, although it shouldn't case any overhead
4784  * when no packet needs it. At most one packet in the queue may be
4785  * marked for time stamping, otherwise it would be impossible to tell
4786  * for sure to which packet the hardware time stamp belongs.
4787  *
4788  * Incoming time stamping has to be configured via the hardware
4789  * filters. Not all combinations are supported, in particular event
4790  * type has to be specified. Matching the kind of event packet is
4791  * not supported, with the exception of "all V2 events regardless of
4792  * level 2 or 4".
4793  *
4794  **/
4795 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4796                               struct ifreq *ifr, int cmd)
4797 {
4798         struct igb_adapter *adapter = netdev_priv(netdev);
4799         struct e1000_hw *hw = &adapter->hw;
4800         struct hwtstamp_config config;
4801         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4802         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4803         u32 tsync_rx_ctl_type = 0;
4804         u32 tsync_rx_cfg = 0;
4805         int is_l4 = 0;
4806         int is_l2 = 0;
4807         short port = 319; /* PTP */
4808         u32 regval;
4809
4810         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4811                 return -EFAULT;
4812
4813         /* reserved for future extensions */
4814         if (config.flags)
4815                 return -EINVAL;
4816
4817         switch (config.tx_type) {
4818         case HWTSTAMP_TX_OFF:
4819                 tsync_tx_ctl_bit = 0;
4820                 break;
4821         case HWTSTAMP_TX_ON:
4822                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4823                 break;
4824         default:
4825                 return -ERANGE;
4826         }
4827
4828         switch (config.rx_filter) {
4829         case HWTSTAMP_FILTER_NONE:
4830                 tsync_rx_ctl_bit = 0;
4831                 break;
4832         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4833         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4834         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4835         case HWTSTAMP_FILTER_ALL:
4836                 /*
4837                  * register TSYNCRXCFG must be set, therefore it is not
4838                  * possible to time stamp both Sync and Delay_Req messages
4839                  * => fall back to time stamping all packets
4840                  */
4841                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4842                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4843                 break;
4844         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4845                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4846                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4847                 is_l4 = 1;
4848                 break;
4849         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4850                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4851                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4852                 is_l4 = 1;
4853                 break;
4854         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4855         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4856                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4857                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4858                 is_l2 = 1;
4859                 is_l4 = 1;
4860                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4861                 break;
4862         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4863         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4864                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4865                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4866                 is_l2 = 1;
4867                 is_l4 = 1;
4868                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4869                 break;
4870         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4871         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4872         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4873                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4874                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4875                 is_l2 = 1;
4876                 break;
4877         default:
4878                 return -ERANGE;
4879         }
4880
4881         /* enable/disable TX */
4882         regval = rd32(E1000_TSYNCTXCTL);
4883         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4884         wr32(E1000_TSYNCTXCTL, regval);
4885
4886         /* enable/disable RX, define which PTP packets are time stamped */
4887         regval = rd32(E1000_TSYNCRXCTL);
4888         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4889         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4890         wr32(E1000_TSYNCRXCTL, regval);
4891         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4892
4893         /*
4894          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4895          *                                          (Ethertype to filter on)
4896          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4897          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4898          */
4899         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4900
4901         /* L4 Queue Filter[0]: only filter by source and destination port */
4902         wr32(E1000_SPQF0, htons(port));
4903         wr32(E1000_IMIREXT(0), is_l4 ?
4904              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4905         wr32(E1000_IMIR(0), is_l4 ?
4906              (htons(port)
4907               | (0<<16) /* immediate interrupt disabled */
4908               | 0 /* (1<<17) bit cleared: do not bypass
4909                      destination port check */)
4910                 : 0);
4911         wr32(E1000_FTQF0, is_l4 ?
4912              (0x11 /* UDP */
4913               | (1<<15) /* VF not compared */
4914               | (1<<27) /* Enable Timestamping */
4915               | (7<<28) /* only source port filter enabled,
4916                            source/target address and protocol
4917                            masked */)
4918              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4919                                       enabled */));
4920
4921         wrfl();
4922
4923         adapter->hwtstamp_config = config;
4924
4925         /* clear TX/RX time stamp registers, just to be sure */
4926         regval = rd32(E1000_TXSTMPH);
4927         regval = rd32(E1000_RXSTMPH);
4928
4929         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4930                 -EFAULT : 0;
4931 }
4932
4933 /**
4934  * igb_ioctl -
4935  * @netdev:
4936  * @ifreq:
4937  * @cmd:
4938  **/
4939 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4940 {
4941         switch (cmd) {
4942         case SIOCGMIIPHY:
4943         case SIOCGMIIREG:
4944         case SIOCSMIIREG:
4945                 return igb_mii_ioctl(netdev, ifr, cmd);
4946         case SIOCSHWTSTAMP:
4947                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4948         default:
4949                 return -EOPNOTSUPP;
4950         }
4951 }
4952
4953 static void igb_vlan_rx_register(struct net_device *netdev,
4954                                  struct vlan_group *grp)
4955 {
4956         struct igb_adapter *adapter = netdev_priv(netdev);
4957         struct e1000_hw *hw = &adapter->hw;
4958         u32 ctrl, rctl;
4959
4960         igb_irq_disable(adapter);
4961         adapter->vlgrp = grp;
4962
4963         if (grp) {
4964                 /* enable VLAN tag insert/strip */
4965                 ctrl = rd32(E1000_CTRL);
4966                 ctrl |= E1000_CTRL_VME;
4967                 wr32(E1000_CTRL, ctrl);
4968
4969                 /* enable VLAN receive filtering */
4970                 rctl = rd32(E1000_RCTL);
4971                 rctl &= ~E1000_RCTL_CFIEN;
4972                 wr32(E1000_RCTL, rctl);
4973                 igb_update_mng_vlan(adapter);
4974         } else {
4975                 /* disable VLAN tag insert/strip */
4976                 ctrl = rd32(E1000_CTRL);
4977                 ctrl &= ~E1000_CTRL_VME;
4978                 wr32(E1000_CTRL, ctrl);
4979
4980                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4981                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4982                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4983                 }
4984         }
4985
4986         igb_rlpml_set(adapter);
4987
4988         if (!test_bit(__IGB_DOWN, &adapter->state))
4989                 igb_irq_enable(adapter);
4990 }
4991
4992 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4993 {
4994         struct igb_adapter *adapter = netdev_priv(netdev);
4995         struct e1000_hw *hw = &adapter->hw;
4996         int pf_id = adapter->vfs_allocated_count;
4997
4998         if ((hw->mng_cookie.status &
4999              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5000             (vid == adapter->mng_vlan_id))
5001                 return;
5002
5003         /* add vid to vlvf if sr-iov is enabled,
5004          * if that fails add directly to filter table */
5005         if (igb_vlvf_set(adapter, vid, true, pf_id))
5006                 igb_vfta_set(hw, vid, true);
5007
5008 }
5009
5010 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5011 {
5012         struct igb_adapter *adapter = netdev_priv(netdev);
5013         struct e1000_hw *hw = &adapter->hw;
5014         int pf_id = adapter->vfs_allocated_count;
5015
5016         igb_irq_disable(adapter);
5017         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5018
5019         if (!test_bit(__IGB_DOWN, &adapter->state))
5020                 igb_irq_enable(adapter);
5021
5022         if ((adapter->hw.mng_cookie.status &
5023              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5024             (vid == adapter->mng_vlan_id)) {
5025                 /* release control to f/w */
5026                 igb_release_hw_control(adapter);
5027                 return;
5028         }
5029
5030         /* remove vid from vlvf if sr-iov is enabled,
5031          * if not in vlvf remove from vfta */
5032         if (igb_vlvf_set(adapter, vid, false, pf_id))
5033                 igb_vfta_set(hw, vid, false);
5034 }
5035
5036 static void igb_restore_vlan(struct igb_adapter *adapter)
5037 {
5038         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5039
5040         if (adapter->vlgrp) {
5041                 u16 vid;
5042                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5043                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5044                                 continue;
5045                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5046                 }
5047         }
5048 }
5049
5050 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5051 {
5052         struct e1000_mac_info *mac = &adapter->hw.mac;
5053
5054         mac->autoneg = 0;
5055
5056         /* Fiber NICs only allow 1000 gbps Full duplex */
5057         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5058                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5059                 dev_err(&adapter->pdev->dev,
5060                         "Unsupported Speed/Duplex configuration\n");
5061                 return -EINVAL;
5062         }
5063
5064         switch (spddplx) {
5065         case SPEED_10 + DUPLEX_HALF:
5066                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5067                 break;
5068         case SPEED_10 + DUPLEX_FULL:
5069                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5070                 break;
5071         case SPEED_100 + DUPLEX_HALF:
5072                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5073                 break;
5074         case SPEED_100 + DUPLEX_FULL:
5075                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5076                 break;
5077         case SPEED_1000 + DUPLEX_FULL:
5078                 mac->autoneg = 1;
5079                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5080                 break;
5081         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5082         default:
5083                 dev_err(&adapter->pdev->dev,
5084                         "Unsupported Speed/Duplex configuration\n");
5085                 return -EINVAL;
5086         }
5087         return 0;
5088 }
5089
5090 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5091 {
5092         struct net_device *netdev = pci_get_drvdata(pdev);
5093         struct igb_adapter *adapter = netdev_priv(netdev);
5094         struct e1000_hw *hw = &adapter->hw;
5095         u32 ctrl, rctl, status;
5096         u32 wufc = adapter->wol;
5097 #ifdef CONFIG_PM
5098         int retval = 0;
5099 #endif
5100
5101         netif_device_detach(netdev);
5102
5103         if (netif_running(netdev))
5104                 igb_close(netdev);
5105
5106         igb_reset_interrupt_capability(adapter);
5107
5108         igb_free_queues(adapter);
5109
5110 #ifdef CONFIG_PM
5111         retval = pci_save_state(pdev);
5112         if (retval)
5113                 return retval;
5114 #endif
5115
5116         status = rd32(E1000_STATUS);
5117         if (status & E1000_STATUS_LU)
5118                 wufc &= ~E1000_WUFC_LNKC;
5119
5120         if (wufc) {
5121                 igb_setup_rctl(adapter);
5122                 igb_set_multi(netdev);
5123
5124                 /* turn on all-multi mode if wake on multicast is enabled */
5125                 if (wufc & E1000_WUFC_MC) {
5126                         rctl = rd32(E1000_RCTL);
5127                         rctl |= E1000_RCTL_MPE;
5128                         wr32(E1000_RCTL, rctl);
5129                 }
5130
5131                 ctrl = rd32(E1000_CTRL);
5132                 /* advertise wake from D3Cold */
5133                 #define E1000_CTRL_ADVD3WUC 0x00100000
5134                 /* phy power management enable */
5135                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5136                 ctrl |= E1000_CTRL_ADVD3WUC;
5137                 wr32(E1000_CTRL, ctrl);
5138
5139                 /* Allow time for pending master requests to run */
5140                 igb_disable_pcie_master(&adapter->hw);
5141
5142                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5143                 wr32(E1000_WUFC, wufc);
5144         } else {
5145                 wr32(E1000_WUC, 0);
5146                 wr32(E1000_WUFC, 0);
5147         }
5148
5149         *enable_wake = wufc || adapter->en_mng_pt;
5150         if (!*enable_wake)
5151                 igb_shutdown_fiber_serdes_link_82575(hw);
5152
5153         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5154          * would have already happened in close and is redundant. */
5155         igb_release_hw_control(adapter);
5156
5157         pci_disable_device(pdev);
5158
5159         return 0;
5160 }
5161
5162 #ifdef CONFIG_PM
5163 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5164 {
5165         int retval;
5166         bool wake;
5167
5168         retval = __igb_shutdown(pdev, &wake);
5169         if (retval)
5170                 return retval;
5171
5172         if (wake) {
5173                 pci_prepare_to_sleep(pdev);
5174         } else {
5175                 pci_wake_from_d3(pdev, false);
5176                 pci_set_power_state(pdev, PCI_D3hot);
5177         }
5178
5179         return 0;
5180 }
5181
5182 static int igb_resume(struct pci_dev *pdev)
5183 {
5184         struct net_device *netdev = pci_get_drvdata(pdev);
5185         struct igb_adapter *adapter = netdev_priv(netdev);
5186         struct e1000_hw *hw = &adapter->hw;
5187         u32 err;
5188
5189         pci_set_power_state(pdev, PCI_D0);
5190         pci_restore_state(pdev);
5191
5192         err = pci_enable_device_mem(pdev);
5193         if (err) {
5194                 dev_err(&pdev->dev,
5195                         "igb: Cannot enable PCI device from suspend\n");
5196                 return err;
5197         }
5198         pci_set_master(pdev);
5199
5200         pci_enable_wake(pdev, PCI_D3hot, 0);
5201         pci_enable_wake(pdev, PCI_D3cold, 0);
5202
5203         igb_set_interrupt_capability(adapter);
5204
5205         if (igb_alloc_queues(adapter)) {
5206                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5207                 return -ENOMEM;
5208         }
5209
5210         /* e1000_power_up_phy(adapter); */
5211
5212         igb_reset(adapter);
5213
5214         /* let the f/w know that the h/w is now under the control of the
5215          * driver. */
5216         igb_get_hw_control(adapter);
5217
5218         wr32(E1000_WUS, ~0);
5219
5220         if (netif_running(netdev)) {
5221                 err = igb_open(netdev);
5222                 if (err)
5223                         return err;
5224         }
5225
5226         netif_device_attach(netdev);
5227
5228         return 0;
5229 }
5230 #endif
5231
5232 static void igb_shutdown(struct pci_dev *pdev)
5233 {
5234         bool wake;
5235
5236         __igb_shutdown(pdev, &wake);
5237
5238         if (system_state == SYSTEM_POWER_OFF) {
5239                 pci_wake_from_d3(pdev, wake);
5240                 pci_set_power_state(pdev, PCI_D3hot);
5241         }
5242 }
5243
5244 #ifdef CONFIG_NET_POLL_CONTROLLER
5245 /*
5246  * Polling 'interrupt' - used by things like netconsole to send skbs
5247  * without having to re-enable interrupts. It's not called while
5248  * the interrupt routine is executing.
5249  */
5250 static void igb_netpoll(struct net_device *netdev)
5251 {
5252         struct igb_adapter *adapter = netdev_priv(netdev);
5253         struct e1000_hw *hw = &adapter->hw;
5254         int i;
5255
5256         if (!adapter->msix_entries) {
5257                 igb_irq_disable(adapter);
5258                 napi_schedule(&adapter->rx_ring[0].napi);
5259                 return;
5260         }
5261
5262         for (i = 0; i < adapter->num_tx_queues; i++) {
5263                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5264                 wr32(E1000_EIMC, tx_ring->eims_value);
5265                 igb_clean_tx_irq(tx_ring);
5266                 wr32(E1000_EIMS, tx_ring->eims_value);
5267         }
5268
5269         for (i = 0; i < adapter->num_rx_queues; i++) {
5270                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5271                 wr32(E1000_EIMC, rx_ring->eims_value);
5272                 napi_schedule(&rx_ring->napi);
5273         }
5274 }
5275 #endif /* CONFIG_NET_POLL_CONTROLLER */
5276
5277 /**
5278  * igb_io_error_detected - called when PCI error is detected
5279  * @pdev: Pointer to PCI device
5280  * @state: The current pci connection state
5281  *
5282  * This function is called after a PCI bus error affecting
5283  * this device has been detected.
5284  */
5285 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5286                                               pci_channel_state_t state)
5287 {
5288         struct net_device *netdev = pci_get_drvdata(pdev);
5289         struct igb_adapter *adapter = netdev_priv(netdev);
5290
5291         netif_device_detach(netdev);
5292
5293         if (netif_running(netdev))
5294                 igb_down(adapter);
5295         pci_disable_device(pdev);
5296
5297         /* Request a slot slot reset. */
5298         return PCI_ERS_RESULT_NEED_RESET;
5299 }
5300
5301 /**
5302  * igb_io_slot_reset - called after the pci bus has been reset.
5303  * @pdev: Pointer to PCI device
5304  *
5305  * Restart the card from scratch, as if from a cold-boot. Implementation
5306  * resembles the first-half of the igb_resume routine.
5307  */
5308 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5309 {
5310         struct net_device *netdev = pci_get_drvdata(pdev);
5311         struct igb_adapter *adapter = netdev_priv(netdev);
5312         struct e1000_hw *hw = &adapter->hw;
5313         pci_ers_result_t result;
5314         int err;
5315
5316         if (pci_enable_device_mem(pdev)) {
5317                 dev_err(&pdev->dev,
5318                         "Cannot re-enable PCI device after reset.\n");
5319                 result = PCI_ERS_RESULT_DISCONNECT;
5320         } else {
5321                 pci_set_master(pdev);
5322                 pci_restore_state(pdev);
5323
5324                 pci_enable_wake(pdev, PCI_D3hot, 0);
5325                 pci_enable_wake(pdev, PCI_D3cold, 0);
5326
5327                 igb_reset(adapter);
5328                 wr32(E1000_WUS, ~0);
5329                 result = PCI_ERS_RESULT_RECOVERED;
5330         }
5331
5332         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5333         if (err) {
5334                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5335                         "failed 0x%0x\n", err);
5336                 /* non-fatal, continue */
5337         }
5338
5339         return result;
5340 }
5341
5342 /**
5343  * igb_io_resume - called when traffic can start flowing again.
5344  * @pdev: Pointer to PCI device
5345  *
5346  * This callback is called when the error recovery driver tells us that
5347  * its OK to resume normal operation. Implementation resembles the
5348  * second-half of the igb_resume routine.
5349  */
5350 static void igb_io_resume(struct pci_dev *pdev)
5351 {
5352         struct net_device *netdev = pci_get_drvdata(pdev);
5353         struct igb_adapter *adapter = netdev_priv(netdev);
5354
5355         if (netif_running(netdev)) {
5356                 if (igb_up(adapter)) {
5357                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5358                         return;
5359                 }
5360         }
5361
5362         netif_device_attach(netdev);
5363
5364         /* let the f/w know that the h/w is now under the control of the
5365          * driver. */
5366         igb_get_hw_control(adapter);
5367 }
5368
5369 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5370 {
5371         u32 reg_data;
5372
5373         reg_data = rd32(E1000_VMOLR(vfn));
5374         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5375                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5376                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5377                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5378                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5379         wr32(E1000_VMOLR(vfn), reg_data);
5380 }
5381
5382 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5383                                  int vfn)
5384 {
5385         struct e1000_hw *hw = &adapter->hw;
5386         u32 vmolr;
5387
5388         vmolr = rd32(E1000_VMOLR(vfn));
5389         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5390         vmolr |= size | E1000_VMOLR_LPE;
5391         wr32(E1000_VMOLR(vfn), vmolr);
5392
5393         return 0;
5394 }
5395
5396 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5397 {
5398         u32 reg_data;
5399
5400         reg_data = rd32(E1000_RAH(entry));
5401         reg_data &= ~E1000_RAH_POOL_MASK;
5402         reg_data |= E1000_RAH_POOL_1 << pool;;
5403         wr32(E1000_RAH(entry), reg_data);
5404 }
5405
5406 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5407                                   int entry_count, u16 total_rar_filters)
5408 {
5409         struct e1000_hw *hw = &adapter->hw;
5410         int i = adapter->vfs_allocated_count + 1;
5411
5412         if ((i + entry_count) < total_rar_filters)
5413                 total_rar_filters = i + entry_count;
5414
5415         for (; i < total_rar_filters; i++)
5416                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5417 }
5418
5419 static int igb_set_vf_mac(struct igb_adapter *adapter,
5420                           int vf, unsigned char *mac_addr)
5421 {
5422         struct e1000_hw *hw = &adapter->hw;
5423         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5424
5425         igb_rar_set(hw, mac_addr, rar_entry);
5426
5427         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5428
5429         igb_set_rah_pool(hw, vf, rar_entry);
5430
5431         return 0;
5432 }
5433
5434 static void igb_vmm_control(struct igb_adapter *adapter)
5435 {
5436         struct e1000_hw *hw = &adapter->hw;
5437         u32 reg_data;
5438
5439         if (!adapter->vfs_allocated_count)
5440                 return;
5441
5442         /* VF's need PF reset indication before they
5443          * can send/receive mail */
5444         reg_data = rd32(E1000_CTRL_EXT);
5445         reg_data |= E1000_CTRL_EXT_PFRSTD;
5446         wr32(E1000_CTRL_EXT, reg_data);
5447
5448         igb_vmdq_set_loopback_pf(hw, true);
5449         igb_vmdq_set_replication_pf(hw, true);
5450 }
5451
5452 /* igb_main.c */