drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/mii.h>
  38 #include <linux/ethtool.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/pci.h>
  41 #include <linux/pci-aspm.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/aer.h>
  46 #ifdef CONFIG_IGB_DCA
  47 #include <linux/dca.h>
  48 #endif
  49 #include "igb.h"
  50
  51 #define DRV_VERSION "1.2.45-k2"
  52 char igb_driver_name[] = "igb";
  53 char igb_driver_version[] = DRV_VERSION;
  54 static const char igb_driver_string[] =
  55                                 "Intel(R) Gigabit Ethernet Network Driver";
  56 static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
  57
  58 static const struct e1000_info *igb_info_tbl[] = {
  59         [board_82575] = &e1000_82575_info,
  60 };
  61
  62 static struct pci_device_id igb_pci_tbl[] = {
  63         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  69         /* required last entry */
  70         {0, }
  71 };
  72
  73 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  74
  75 void igb_reset(struct igb_adapter *);
  76 static int igb_setup_all_tx_resources(struct igb_adapter *);
  77 static int igb_setup_all_rx_resources(struct igb_adapter *);
  78 static void igb_free_all_tx_resources(struct igb_adapter *);
  79 static void igb_free_all_rx_resources(struct igb_adapter *);
  80 void igb_update_stats(struct igb_adapter *);
  81 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  82 static void __devexit igb_remove(struct pci_dev *pdev);
  83 static int igb_sw_init(struct igb_adapter *);
  84 static int igb_open(struct net_device *);
  85 static int igb_close(struct net_device *);
  86 static void igb_configure_tx(struct igb_adapter *);
  87 static void igb_configure_rx(struct igb_adapter *);
  88 static void igb_setup_rctl(struct igb_adapter *);
  89 static void igb_clean_all_tx_rings(struct igb_adapter *);
  90 static void igb_clean_all_rx_rings(struct igb_adapter *);
  91 static void igb_clean_tx_ring(struct igb_ring *);
  92 static void igb_clean_rx_ring(struct igb_ring *);
  93 static void igb_set_multi(struct net_device *);
  94 static void igb_update_phy_info(unsigned long);
  95 static void igb_watchdog(unsigned long);
  96 static void igb_watchdog_task(struct work_struct *);
  97 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
  98                                   struct igb_ring *);
  99 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 100 static struct net_device_stats *igb_get_stats(struct net_device *);
 101 static int igb_change_mtu(struct net_device *, int);
 102 static int igb_set_mac(struct net_device *, void *);
 103 static irqreturn_t igb_intr(int irq, void *);
 104 static irqreturn_t igb_intr_msi(int irq, void *);
 105 static irqreturn_t igb_msix_other(int irq, void *);
 106 static irqreturn_t igb_msix_rx(int irq, void *);
 107 static irqreturn_t igb_msix_tx(int irq, void *);
 108 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
 109 #ifdef CONFIG_IGB_DCA
 110 static void igb_update_rx_dca(struct igb_ring *);
 111 static void igb_update_tx_dca(struct igb_ring *);
 112 static void igb_setup_dca(struct igb_adapter *);
 113 #endif /* CONFIG_IGB_DCA */
 114 static bool igb_clean_tx_irq(struct igb_ring *);
 115 static int igb_poll(struct napi_struct *, int);
 116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 118 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 119 static void igb_tx_timeout(struct net_device *);
 120 static void igb_reset_task(struct work_struct *);
 121 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 122 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 123 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 124 static void igb_restore_vlan(struct igb_adapter *);
 125
 126 static int igb_suspend(struct pci_dev *, pm_message_t);
 127 #ifdef CONFIG_PM
 128 static int igb_resume(struct pci_dev *);
 129 #endif
 130 static void igb_shutdown(struct pci_dev *);
 131 #ifdef CONFIG_IGB_DCA
 132 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 133 static struct notifier_block dca_notifier = {
 134         .notifier_call  = igb_notify_dca,
 135         .next           = NULL,
 136         .priority       = 0
 137 };
 138 #endif
 139
 140 #ifdef CONFIG_NET_POLL_CONTROLLER
 141 /* for netdump / net console */
 142 static void igb_netpoll(struct net_device *);
 143 #endif
 144
 145 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 146                      pci_channel_state_t);
 147 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 148 static void igb_io_resume(struct pci_dev *);
 149
 150 static struct pci_error_handlers igb_err_handler = {
 151         .error_detected = igb_io_error_detected,
 152         .slot_reset = igb_io_slot_reset,
 153         .resume = igb_io_resume,
 154 };
 155
 156
 157 static struct pci_driver igb_driver = {
 158         .name     = igb_driver_name,
 159         .id_table = igb_pci_tbl,
 160         .probe    = igb_probe,
 161         .remove   = __devexit_p(igb_remove),
 162 #ifdef CONFIG_PM
 163         /* Power Managment Hooks */
 164         .suspend  = igb_suspend,
 165         .resume   = igb_resume,
 166 #endif
 167         .shutdown = igb_shutdown,
 168         .err_handler = &igb_err_handler
 169 };
 170
 171 static int global_quad_port_a; /* global quad port a indication */
 172
 173 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 174 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 175 MODULE_LICENSE("GPL");
 176 MODULE_VERSION(DRV_VERSION);
 177
 178 #ifdef DEBUG
 179 /**
 180  * igb_get_hw_dev_name - return device name string
 181  * used by hardware layer to print debugging information
 182  **/
 183 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 184 {
 185         struct igb_adapter *adapter = hw->back;
 186         return adapter->netdev->name;
 187 }
 188 #endif
 189
 190 /**
 191  * igb_init_module - Driver Registration Routine
 192  *
 193  * igb_init_module is the first routine called when the driver is
 194  * loaded. All it does is register with the PCI subsystem.
 195  **/
 196 static int __init igb_init_module(void)
 197 {
 198         int ret;
 199         printk(KERN_INFO "%s - version %s\n",
 200                igb_driver_string, igb_driver_version);
 201
 202         printk(KERN_INFO "%s\n", igb_copyright);
 203
 204         global_quad_port_a = 0;
 205
 206 #ifdef CONFIG_IGB_DCA
 207         dca_register_notify(&dca_notifier);
 208 #endif
 209
 210         ret = pci_register_driver(&igb_driver);
 211         return ret;
 212 }
 213
 214 module_init(igb_init_module);
 215
 216 /**
 217  * igb_exit_module - Driver Exit Cleanup Routine
 218  *
 219  * igb_exit_module is called just before the driver is removed
 220  * from memory.
 221  **/
 222 static void __exit igb_exit_module(void)
 223 {
 224 #ifdef CONFIG_IGB_DCA
 225         dca_unregister_notify(&dca_notifier);
 226 #endif
 227         pci_unregister_driver(&igb_driver);
 228 }
 229
 230 module_exit(igb_exit_module);
 231
 232 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 233 /**
 234  * igb_cache_ring_register - Descriptor ring to register mapping
 235  * @adapter: board private structure to initialize
 236  *
 237  * Once we know the feature-set enabled for the device, we'll cache
 238  * the register offset the descriptor ring is assigned to.
 239  **/
 240 static void igb_cache_ring_register(struct igb_adapter *adapter)
 241 {
 242         int i;
 243
 244         switch (adapter->hw.mac.type) {
 245         case e1000_82576:
 246                 /* The queues are allocated for virtualization such that VF 0
 247                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 248                  * In order to avoid collision we start at the first free queue
 249                  * and continue consuming queues in the same sequence
 250                  */
 251                 for (i = 0; i < adapter->num_rx_queues; i++)
 252                         adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
 253                 for (i = 0; i < adapter->num_tx_queues; i++)
 254                         adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
 255                 break;
 256         case e1000_82575:
 257         default:
 258                 for (i = 0; i < adapter->num_rx_queues; i++)
 259                         adapter->rx_ring[i].reg_idx = i;
 260                 for (i = 0; i < adapter->num_tx_queues; i++)
 261                         adapter->tx_ring[i].reg_idx = i;
 262                 break;
 263         }
 264 }
 265
 266 /**
 267  * igb_alloc_queues - Allocate memory for all rings
 268  * @adapter: board private structure to initialize
 269  *
 270  * We allocate one ring per queue at run-time since we don't know the
 271  * number of queues at compile-time.
 272  **/
 273 static int igb_alloc_queues(struct igb_adapter *adapter)
 274 {
 275         int i;
 276
 277         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 278                                    sizeof(struct igb_ring), GFP_KERNEL);
 279         if (!adapter->tx_ring)
 280                 return -ENOMEM;
 281
 282         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 283                                    sizeof(struct igb_ring), GFP_KERNEL);
 284         if (!adapter->rx_ring) {
 285                 kfree(adapter->tx_ring);
 286                 return -ENOMEM;
 287         }
 288
 289         adapter->rx_ring->buddy = adapter->tx_ring;
 290
 291         for (i = 0; i < adapter->num_tx_queues; i++) {
 292                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 293                 ring->count = adapter->tx_ring_count;
 294                 ring->adapter = adapter;
 295                 ring->queue_index = i;
 296         }
 297         for (i = 0; i < adapter->num_rx_queues; i++) {
 298                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 299                 ring->count = adapter->rx_ring_count;
 300                 ring->adapter = adapter;
 301                 ring->queue_index = i;
 302                 ring->itr_register = E1000_ITR;
 303
 304                 /* set a default napi handler for each rx_ring */
 305                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 306         }
 307
 308         igb_cache_ring_register(adapter);
 309         return 0;
 310 }
 311
 312 static void igb_free_queues(struct igb_adapter *adapter)
 313 {
 314         int i;
 315
 316         for (i = 0; i < adapter->num_rx_queues; i++)
 317                 netif_napi_del(&adapter->rx_ring[i].napi);
 318
 319         kfree(adapter->tx_ring);
 320         kfree(adapter->rx_ring);
 321 }
 322
 323 #define IGB_N0_QUEUE -1
 324 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 325                               int tx_queue, int msix_vector)
 326 {
 327         u32 msixbm = 0;
 328         struct e1000_hw *hw = &adapter->hw;
 329         u32 ivar, index;
 330
 331         switch (hw->mac.type) {
 332         case e1000_82575:
 333                 /* The 82575 assigns vectors using a bitmask, which matches the
 334                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 335                    or more queues to a vector, we write the appropriate bits
 336                    into the MSIXBM register for that vector. */
 337                 if (rx_queue > IGB_N0_QUEUE) {
 338                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 339                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 340                 }
 341                 if (tx_queue > IGB_N0_QUEUE) {
 342                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 343                         adapter->tx_ring[tx_queue].eims_value =
 344                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 345                 }
 346                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 347                 break;
 348         case e1000_82576:
 349                 /* 82576 uses a table-based method for assigning vectors.
 350                    Each queue has a single entry in the table to which we write
 351                    a vector number along with a "valid" bit.  Sadly, the layout
 352                    of the table is somewhat counterintuitive. */
 353                 if (rx_queue > IGB_N0_QUEUE) {
 354                         index = (rx_queue >> 1);
 355                         ivar = array_rd32(E1000_IVAR0, index);
 356                         if (rx_queue & 0x1) {
 357                                 /* vector goes into third byte of register */
 358                                 ivar = ivar & 0xFF00FFFF;
 359                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 360                         } else {
 361                                 /* vector goes into low byte of register */
 362                                 ivar = ivar & 0xFFFFFF00;
 363                                 ivar |= msix_vector | E1000_IVAR_VALID;
 364                         }
 365                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 366                         array_wr32(E1000_IVAR0, index, ivar);
 367                 }
 368                 if (tx_queue > IGB_N0_QUEUE) {
 369                         index = (tx_queue >> 1);
 370                         ivar = array_rd32(E1000_IVAR0, index);
 371                         if (tx_queue & 0x1) {
 372                                 /* vector goes into high byte of register */
 373                                 ivar = ivar & 0x00FFFFFF;
 374                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 375                         } else {
 376                                 /* vector goes into second byte of register */
 377                                 ivar = ivar & 0xFFFF00FF;
 378                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 379                         }
 380                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 381                         array_wr32(E1000_IVAR0, index, ivar);
 382                 }
 383                 break;
 384         default:
 385                 BUG();
 386                 break;
 387         }
 388 }
 389
 390 /**
 391  * igb_configure_msix - Configure MSI-X hardware
 392  *
 393  * igb_configure_msix sets up the hardware to properly
 394  * generate MSI-X interrupts.
 395  **/
 396 static void igb_configure_msix(struct igb_adapter *adapter)
 397 {
 398         u32 tmp;
 399         int i, vector = 0;
 400         struct e1000_hw *hw = &adapter->hw;
 401
 402         adapter->eims_enable_mask = 0;
 403         if (hw->mac.type == e1000_82576)
 404                 /* Turn on MSI-X capability first, or our settings
 405                  * won't stick.  And it will take days to debug. */
 406                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 407                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 408                                    E1000_GPIE_NSICR);
 409
 410         for (i = 0; i < adapter->num_tx_queues; i++) {
 411                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 412                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 413                 adapter->eims_enable_mask |= tx_ring->eims_value;
 414                 if (tx_ring->itr_val)
 415                         writel(tx_ring->itr_val,
 416                                hw->hw_addr + tx_ring->itr_register);
 417                 else
 418                         writel(1, hw->hw_addr + tx_ring->itr_register);
 419         }
 420
 421         for (i = 0; i < adapter->num_rx_queues; i++) {
 422                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 423                 rx_ring->buddy = NULL;
 424                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 425                 adapter->eims_enable_mask |= rx_ring->eims_value;
 426                 if (rx_ring->itr_val)
 427                         writel(rx_ring->itr_val,
 428                                hw->hw_addr + rx_ring->itr_register);
 429                 else
 430                         writel(1, hw->hw_addr + rx_ring->itr_register);
 431         }
 432
 433
 434         /* set vector for other causes, i.e. link changes */
 435         switch (hw->mac.type) {
 436         case e1000_82575:
 437                 array_wr32(E1000_MSIXBM(0), vector++,
 438                                       E1000_EIMS_OTHER);
 439
 440                 tmp = rd32(E1000_CTRL_EXT);
 441                 /* enable MSI-X PBA support*/
 442                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 443
 444                 /* Auto-Mask interrupts upon ICR read. */
 445                 tmp |= E1000_CTRL_EXT_EIAME;
 446                 tmp |= E1000_CTRL_EXT_IRCA;
 447
 448                 wr32(E1000_CTRL_EXT, tmp);
 449                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 450                 adapter->eims_other = E1000_EIMS_OTHER;
 451
 452                 break;
 453
 454         case e1000_82576:
 455                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 456                 wr32(E1000_IVAR_MISC, tmp);
 457
 458                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 459                 adapter->eims_other = 1 << (vector - 1);
 460                 break;
 461         default:
 462                 /* do nothing, since nothing else supports MSI-X */
 463                 break;
 464         } /* switch (hw->mac.type) */
 465         wrfl();
 466 }
 467
 468 /**
 469  * igb_request_msix - Initialize MSI-X interrupts
 470  *
 471  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 472  * kernel.
 473  **/
 474 static int igb_request_msix(struct igb_adapter *adapter)
 475 {
 476         struct net_device *netdev = adapter->netdev;
 477         int i, err = 0, vector = 0;
 478
 479         vector = 0;
 480
 481         for (i = 0; i < adapter->num_tx_queues; i++) {
 482                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 483                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 484                 err = request_irq(adapter->msix_entries[vector].vector,
 485                                   &igb_msix_tx, 0, ring->name,
 486                                   &(adapter->tx_ring[i]));
 487                 if (err)
 488                         goto out;
 489                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 490                 ring->itr_val = 976; /* ~4000 ints/sec */
 491                 vector++;
 492         }
 493         for (i = 0; i < adapter->num_rx_queues; i++) {
 494                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 495                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 496                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 497                 else
 498                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 499                 err = request_irq(adapter->msix_entries[vector].vector,
 500                                   &igb_msix_rx, 0, ring->name,
 501                                   &(adapter->rx_ring[i]));
 502                 if (err)
 503                         goto out;
 504                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 505                 ring->itr_val = adapter->itr;
 506                 /* overwrite the poll routine for MSIX, we've already done
 507                  * netif_napi_add */
 508                 ring->napi.poll = &igb_clean_rx_ring_msix;
 509                 vector++;
 510         }
 511
 512         err = request_irq(adapter->msix_entries[vector].vector,
 513                           &igb_msix_other, 0, netdev->name, netdev);
 514         if (err)
 515                 goto out;
 516
 517         igb_configure_msix(adapter);
 518         return 0;
 519 out:
 520         return err;
 521 }
 522
 523 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 524 {
 525         if (adapter->msix_entries) {
 526                 pci_disable_msix(adapter->pdev);
 527                 kfree(adapter->msix_entries);
 528                 adapter->msix_entries = NULL;
 529         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 530                 pci_disable_msi(adapter->pdev);
 531         return;
 532 }
 533
 534
 535 /**
 536  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 537  *
 538  * Attempt to configure interrupts using the best available
 539  * capabilities of the hardware and kernel.
 540  **/
 541 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 542 {
 543         int err;
 544         int numvecs, i;
 545
 546         /* Number of supported queues. */
 547         /* Having more queues than CPUs doesn't make sense. */
 548         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 549         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 550
 551         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 552         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 553                                         GFP_KERNEL);
 554         if (!adapter->msix_entries)
 555                 goto msi_only;
 556
 557         for (i = 0; i < numvecs; i++)
 558                 adapter->msix_entries[i].entry = i;
 559
 560         err = pci_enable_msix(adapter->pdev,
 561                               adapter->msix_entries,
 562                               numvecs);
 563         if (err == 0)
 564                 goto out;
 565
 566         igb_reset_interrupt_capability(adapter);
 567
 568         /* If we can't do MSI-X, try MSI */
 569 msi_only:
 570         adapter->num_rx_queues = 1;
 571         adapter->num_tx_queues = 1;
 572         if (!pci_enable_msi(adapter->pdev))
 573                 adapter->flags |= IGB_FLAG_HAS_MSI;
 574 out:
 575         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 576         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 577         return;
 578 }
 579
 580 /**
 581  * igb_request_irq - initialize interrupts
 582  *
 583  * Attempts to configure interrupts using the best available
 584  * capabilities of the hardware and kernel.
 585  **/
 586 static int igb_request_irq(struct igb_adapter *adapter)
 587 {
 588         struct net_device *netdev = adapter->netdev;
 589         struct e1000_hw *hw = &adapter->hw;
 590         int err = 0;
 591
 592         if (adapter->msix_entries) {
 593                 err = igb_request_msix(adapter);
 594                 if (!err)
 595                         goto request_done;
 596                 /* fall back to MSI */
 597                 igb_reset_interrupt_capability(adapter);
 598                 if (!pci_enable_msi(adapter->pdev))
 599                         adapter->flags |= IGB_FLAG_HAS_MSI;
 600                 igb_free_all_tx_resources(adapter);
 601                 igb_free_all_rx_resources(adapter);
 602                 adapter->num_rx_queues = 1;
 603                 igb_alloc_queues(adapter);
 604         } else {
 605                 switch (hw->mac.type) {
 606                 case e1000_82575:
 607                         wr32(E1000_MSIXBM(0),
 608                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 609                         break;
 610                 case e1000_82576:
 611                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 612                         break;
 613                 default:
 614                         break;
 615                 }
 616         }
 617
 618         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 619                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 620                                   netdev->name, netdev);
 621                 if (!err)
 622                         goto request_done;
 623                 /* fall back to legacy interrupts */
 624                 igb_reset_interrupt_capability(adapter);
 625                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 626         }
 627
 628         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 629                           netdev->name, netdev);
 630
 631         if (err)
 632                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 633                         err);
 634
 635 request_done:
 636         return err;
 637 }
 638
 639 static void igb_free_irq(struct igb_adapter *adapter)
 640 {
 641         struct net_device *netdev = adapter->netdev;
 642
 643         if (adapter->msix_entries) {
 644                 int vector = 0, i;
 645
 646                 for (i = 0; i < adapter->num_tx_queues; i++)
 647                         free_irq(adapter->msix_entries[vector++].vector,
 648                                 &(adapter->tx_ring[i]));
 649                 for (i = 0; i < adapter->num_rx_queues; i++)
 650                         free_irq(adapter->msix_entries[vector++].vector,
 651                                 &(adapter->rx_ring[i]));
 652
 653                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 654                 return;
 655         }
 656
 657         free_irq(adapter->pdev->irq, netdev);
 658 }
 659
 660 /**
 661  * igb_irq_disable - Mask off interrupt generation on the NIC
 662  * @adapter: board private structure
 663  **/
 664 static void igb_irq_disable(struct igb_adapter *adapter)
 665 {
 666         struct e1000_hw *hw = &adapter->hw;
 667
 668         if (adapter->msix_entries) {
 669                 wr32(E1000_EIAM, 0);
 670                 wr32(E1000_EIMC, ~0);
 671                 wr32(E1000_EIAC, 0);
 672         }
 673
 674         wr32(E1000_IAM, 0);
 675         wr32(E1000_IMC, ~0);
 676         wrfl();
 677         synchronize_irq(adapter->pdev->irq);
 678 }
 679
 680 /**
 681  * igb_irq_enable - Enable default interrupt generation settings
 682  * @adapter: board private structure
 683  **/
 684 static void igb_irq_enable(struct igb_adapter *adapter)
 685 {
 686         struct e1000_hw *hw = &adapter->hw;
 687
 688         if (adapter->msix_entries) {
 689                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 690                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 691                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 692                 wr32(E1000_IMS, E1000_IMS_LSC);
 693         } else {
 694                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 695                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 696         }
 697 }
 698
 699 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 700 {
 701         struct net_device *netdev = adapter->netdev;
 702         u16 vid = adapter->hw.mng_cookie.vlan_id;
 703         u16 old_vid = adapter->mng_vlan_id;
 704         if (adapter->vlgrp) {
 705                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 706                         if (adapter->hw.mng_cookie.status &
 707                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 708                                 igb_vlan_rx_add_vid(netdev, vid);
 709                                 adapter->mng_vlan_id = vid;
 710                         } else
 711                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 712
 713                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 714                                         (vid != old_vid) &&
 715                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 716                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 717                 } else
 718                         adapter->mng_vlan_id = vid;
 719         }
 720 }
 721
 722 /**
 723  * igb_release_hw_control - release control of the h/w to f/w
 724  * @adapter: address of board private structure
 725  *
 726  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 727  * For ASF and Pass Through versions of f/w this means that the
 728  * driver is no longer loaded.
 729  *
 730  **/
 731 static void igb_release_hw_control(struct igb_adapter *adapter)
 732 {
 733         struct e1000_hw *hw = &adapter->hw;
 734         u32 ctrl_ext;
 735
 736         /* Let firmware take over control of h/w */
 737         ctrl_ext = rd32(E1000_CTRL_EXT);
 738         wr32(E1000_CTRL_EXT,
 739                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 740 }
 741
 742
 743 /**
 744  * igb_get_hw_control - get control of the h/w from f/w
 745  * @adapter: address of board private structure
 746  *
 747  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 748  * For ASF and Pass Through versions of f/w this means that
 749  * the driver is loaded.
 750  *
 751  **/
 752 static void igb_get_hw_control(struct igb_adapter *adapter)
 753 {
 754         struct e1000_hw *hw = &adapter->hw;
 755         u32 ctrl_ext;
 756
 757         /* Let firmware know the driver has taken over */
 758         ctrl_ext = rd32(E1000_CTRL_EXT);
 759         wr32(E1000_CTRL_EXT,
 760                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 761 }
 762
 763 /**
 764  * igb_configure - configure the hardware for RX and TX
 765  * @adapter: private board structure
 766  **/
 767 static void igb_configure(struct igb_adapter *adapter)
 768 {
 769         struct net_device *netdev = adapter->netdev;
 770         int i;
 771
 772         igb_get_hw_control(adapter);
 773         igb_set_multi(netdev);
 774
 775         igb_restore_vlan(adapter);
 776
 777         igb_configure_tx(adapter);
 778         igb_setup_rctl(adapter);
 779         igb_configure_rx(adapter);
 780
 781         igb_rx_fifo_flush_82575(&adapter->hw);
 782
 783         /* call IGB_DESC_UNUSED which always leaves
 784          * at least 1 descriptor unused to make sure
 785          * next_to_use != next_to_clean */
 786         for (i = 0; i < adapter->num_rx_queues; i++) {
 787                 struct igb_ring *ring = &adapter->rx_ring[i];
 788                 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
 789         }
 790
 791
 792         adapter->tx_queue_len = netdev->tx_queue_len;
 793 }
 794
 795
 796 /**
 797  * igb_up - Open the interface and prepare it to handle traffic
 798  * @adapter: board private structure
 799  **/
 800
 801 int igb_up(struct igb_adapter *adapter)
 802 {
 803         struct e1000_hw *hw = &adapter->hw;
 804         int i;
 805
 806         /* hardware has been reset, we need to reload some things */
 807         igb_configure(adapter);
 808
 809         clear_bit(__IGB_DOWN, &adapter->state);
 810
 811         for (i = 0; i < adapter->num_rx_queues; i++)
 812                 napi_enable(&adapter->rx_ring[i].napi);
 813         if (adapter->msix_entries)
 814                 igb_configure_msix(adapter);
 815
 816         /* Clear any pending interrupts. */
 817         rd32(E1000_ICR);
 818         igb_irq_enable(adapter);
 819
 820         /* Fire a link change interrupt to start the watchdog. */
 821         wr32(E1000_ICS, E1000_ICS_LSC);
 822         return 0;
 823 }
 824
 825 void igb_down(struct igb_adapter *adapter)
 826 {
 827         struct e1000_hw *hw = &adapter->hw;
 828         struct net_device *netdev = adapter->netdev;
 829         u32 tctl, rctl;
 830         int i;
 831
 832         /* signal that we're down so the interrupt handler does not
 833          * reschedule our watchdog timer */
 834         set_bit(__IGB_DOWN, &adapter->state);
 835
 836         /* disable receives in the hardware */
 837         rctl = rd32(E1000_RCTL);
 838         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 839         /* flush and sleep below */
 840
 841         netif_tx_stop_all_queues(netdev);
 842
 843         /* disable transmits in the hardware */
 844         tctl = rd32(E1000_TCTL);
 845         tctl &= ~E1000_TCTL_EN;
 846         wr32(E1000_TCTL, tctl);
 847         /* flush both disables and wait for them to finish */
 848         wrfl();
 849         msleep(10);
 850
 851         for (i = 0; i < adapter->num_rx_queues; i++)
 852                 napi_disable(&adapter->rx_ring[i].napi);
 853
 854         igb_irq_disable(adapter);
 855
 856         del_timer_sync(&adapter->watchdog_timer);
 857         del_timer_sync(&adapter->phy_info_timer);
 858
 859         netdev->tx_queue_len = adapter->tx_queue_len;
 860         netif_carrier_off(netdev);
 861         adapter->link_speed = 0;
 862         adapter->link_duplex = 0;
 863
 864         if (!pci_channel_offline(adapter->pdev))
 865                 igb_reset(adapter);
 866         igb_clean_all_tx_rings(adapter);
 867         igb_clean_all_rx_rings(adapter);
 868 }
 869
 870 void igb_reinit_locked(struct igb_adapter *adapter)
 871 {
 872         WARN_ON(in_interrupt());
 873         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 874                 msleep(1);
 875         igb_down(adapter);
 876         igb_up(adapter);
 877         clear_bit(__IGB_RESETTING, &adapter->state);
 878 }
 879
 880 void igb_reset(struct igb_adapter *adapter)
 881 {
 882         struct e1000_hw *hw = &adapter->hw;
 883         struct e1000_mac_info *mac = &hw->mac;
 884         struct e1000_fc_info *fc = &hw->fc;
 885         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
 886         u16 hwm;
 887
 888         /* Repartition Pba for greater than 9k mtu
 889          * To take effect CTRL.RST is required.
 890          */
 891         if (mac->type != e1000_82576) {
 892         pba = E1000_PBA_34K;
 893         }
 894         else {
 895                 pba = E1000_PBA_64K;
 896         }
 897
 898         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
 899             (mac->type < e1000_82576)) {
 900                 /* adjust PBA for jumbo frames */
 901                 wr32(E1000_PBA, pba);
 902
 903                 /* To maintain wire speed transmits, the Tx FIFO should be
 904                  * large enough to accommodate two full transmit packets,
 905                  * rounded up to the next 1KB and expressed in KB.  Likewise,
 906                  * the Rx FIFO should be large enough to accommodate at least
 907                  * one full receive packet and is similarly rounded up and
 908                  * expressed in KB. */
 909                 pba = rd32(E1000_PBA);
 910                 /* upper 16 bits has Tx packet buffer allocation size in KB */
 911                 tx_space = pba >> 16;
 912                 /* lower 16 bits has Rx packet buffer allocation size in KB */
 913                 pba &= 0xffff;
 914                 /* the tx fifo also stores 16 bytes of information about the tx
 915                  * but don't include ethernet FCS because hardware appends it */
 916                 min_tx_space = (adapter->max_frame_size +
 917                                 sizeof(struct e1000_tx_desc) -
 918                                 ETH_FCS_LEN) * 2;
 919                 min_tx_space = ALIGN(min_tx_space, 1024);
 920                 min_tx_space >>= 10;
 921                 /* software strips receive CRC, so leave room for it */
 922                 min_rx_space = adapter->max_frame_size;
 923                 min_rx_space = ALIGN(min_rx_space, 1024);
 924                 min_rx_space >>= 10;
 925
 926                 /* If current Tx allocation is less than the min Tx FIFO size,
 927                  * and the min Tx FIFO size is less than the current Rx FIFO
 928                  * allocation, take space away from current Rx allocation */
 929                 if (tx_space < min_tx_space &&
 930                     ((min_tx_space - tx_space) < pba)) {
 931                         pba = pba - (min_tx_space - tx_space);
 932
 933                         /* if short on rx space, rx wins and must trump tx
 934                          * adjustment */
 935                         if (pba < min_rx_space)
 936                                 pba = min_rx_space;
 937                 }
 938                 wr32(E1000_PBA, pba);
 939         }
 940
 941         /* flow control settings */
 942         /* The high water mark must be low enough to fit one full frame
 943          * (or the size used for early receive) above it in the Rx FIFO.
 944          * Set it to the lower of:
 945          * - 90% of the Rx FIFO size, or
 946          * - the full Rx FIFO size minus one full frame */
 947         hwm = min(((pba << 10) * 9 / 10),
 948                         ((pba << 10) - 2 * adapter->max_frame_size));
 949
 950         if (mac->type < e1000_82576) {
 951                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
 952                 fc->low_water = fc->high_water - 8;
 953         } else {
 954                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
 955                 fc->low_water = fc->high_water - 16;
 956         }
 957         fc->pause_time = 0xFFFF;
 958         fc->send_xon = 1;
 959         fc->type = fc->original_type;
 960
 961         /* Allow time for pending master requests to run */
 962         adapter->hw.mac.ops.reset_hw(&adapter->hw);
 963         wr32(E1000_WUC, 0);
 964
 965         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
 966                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
 967
 968         igb_update_mng_vlan(adapter);
 969
 970         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
 971         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
 972
 973         igb_reset_adaptive(&adapter->hw);
 974         igb_get_phy_info(&adapter->hw);
 975 }
 976
 977 static const struct net_device_ops igb_netdev_ops = {
 978         .ndo_open               = igb_open,
 979         .ndo_stop               = igb_close,
 980         .ndo_start_xmit         = igb_xmit_frame_adv,
 981         .ndo_get_stats          = igb_get_stats,
 982         .ndo_set_multicast_list = igb_set_multi,
 983         .ndo_set_mac_address    = igb_set_mac,
 984         .ndo_change_mtu         = igb_change_mtu,
 985         .ndo_do_ioctl           = igb_ioctl,
 986         .ndo_tx_timeout         = igb_tx_timeout,
 987         .ndo_validate_addr      = eth_validate_addr,
 988         .ndo_vlan_rx_register   = igb_vlan_rx_register,
 989         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
 990         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
 991 #ifdef CONFIG_NET_POLL_CONTROLLER
 992         .ndo_poll_controller    = igb_netpoll,
 993 #endif
 994 };
 995
 996 /**
 997  * igb_probe - Device Initialization Routine
 998  * @pdev: PCI device information struct
 999  * @ent: entry in igb_pci_tbl
1000  *
1001  * Returns 0 on success, negative on failure
1002  *
1003  * igb_probe initializes an adapter identified by a pci_dev structure.
1004  * The OS initialization, configuring of the adapter private structure,
1005  * and a hardware reset occur.
1006  **/
1007 static int __devinit igb_probe(struct pci_dev *pdev,
1008                                const struct pci_device_id *ent)
1009 {
1010         struct net_device *netdev;
1011         struct igb_adapter *adapter;
1012         struct e1000_hw *hw;
1013         struct pci_dev *us_dev;
1014         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1015         unsigned long mmio_start, mmio_len;
1016         int i, err, pci_using_dac, pos;
1017         u16 eeprom_data = 0, state = 0;
1018         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1019         u32 part_num;
1020
1021         err = pci_enable_device_mem(pdev);
1022         if (err)
1023                 return err;
1024
1025         pci_using_dac = 0;
1026         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1027         if (!err) {
1028                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1029                 if (!err)
1030                         pci_using_dac = 1;
1031         } else {
1032                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1033                 if (err) {
1034                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1035                         if (err) {
1036                                 dev_err(&pdev->dev, "No usable DMA "
1037                                         "configuration, aborting\n");
1038                                 goto err_dma;
1039                         }
1040                 }
1041         }
1042
1043         /* 82575 requires that the pci-e link partner disable the L0s state */
1044         switch (pdev->device) {
1045         case E1000_DEV_ID_82575EB_COPPER:
1046         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1047         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1048                 us_dev = pdev->bus->self;
1049                 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1050                 if (pos) {
1051                         pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1052                                              &state);
1053                         state &= ~PCIE_LINK_STATE_L0S;
1054                         pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055                                               state);
1056                         dev_info(&pdev->dev,
1057                                  "Disabling ASPM L0s upstream switch port %s\n",
1058                                  pci_name(us_dev));
1059                 }
1060         default:
1061                 break;
1062         }
1063
1064         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1065                                            IORESOURCE_MEM),
1066                                            igb_driver_name);
1067         if (err)
1068                 goto err_pci_reg;
1069
1070         err = pci_enable_pcie_error_reporting(pdev);
1071         if (err) {
1072                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1073                         "0x%x\n", err);
1074                 /* non-fatal, continue */
1075         }
1076
1077         pci_set_master(pdev);
1078         pci_save_state(pdev);
1079
1080         err = -ENOMEM;
1081         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1082         if (!netdev)
1083                 goto err_alloc_etherdev;
1084
1085         SET_NETDEV_DEV(netdev, &pdev->dev);
1086
1087         pci_set_drvdata(pdev, netdev);
1088         adapter = netdev_priv(netdev);
1089         adapter->netdev = netdev;
1090         adapter->pdev = pdev;
1091         hw = &adapter->hw;
1092         hw->back = adapter;
1093         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1094
1095         mmio_start = pci_resource_start(pdev, 0);
1096         mmio_len = pci_resource_len(pdev, 0);
1097
1098         err = -EIO;
1099         adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1100         if (!adapter->hw.hw_addr)
1101                 goto err_ioremap;
1102
1103         netdev->netdev_ops = &igb_netdev_ops;
1104         igb_set_ethtool_ops(netdev);
1105         netdev->watchdog_timeo = 5 * HZ;
1106
1107         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1108
1109         netdev->mem_start = mmio_start;
1110         netdev->mem_end = mmio_start + mmio_len;
1111
1112         /* PCI config space info */
1113         hw->vendor_id = pdev->vendor;
1114         hw->device_id = pdev->device;
1115         hw->revision_id = pdev->revision;
1116         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1117         hw->subsystem_device_id = pdev->subsystem_device;
1118
1119         /* setup the private structure */
1120         hw->back = adapter;
1121         /* Copy the default MAC, PHY and NVM function pointers */
1122         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1123         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1124         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1125         /* Initialize skew-specific constants */
1126         err = ei->get_invariants(hw);
1127         if (err)
1128                 goto err_hw_init;
1129
1130         err = igb_sw_init(adapter);
1131         if (err)
1132                 goto err_sw_init;
1133
1134         igb_get_bus_info_pcie(hw);
1135
1136         /* set flags */
1137         switch (hw->mac.type) {
1138         case e1000_82575:
1139                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1140                 break;
1141         case e1000_82576:
1142         default:
1143                 break;
1144         }
1145
1146         hw->phy.autoneg_wait_to_complete = false;
1147         hw->mac.adaptive_ifs = true;
1148
1149         /* Copper options */
1150         if (hw->phy.media_type == e1000_media_type_copper) {
1151                 hw->phy.mdix = AUTO_ALL_MODES;
1152                 hw->phy.disable_polarity_correction = false;
1153                 hw->phy.ms_type = e1000_ms_hw_default;
1154         }
1155
1156         if (igb_check_reset_block(hw))
1157                 dev_info(&pdev->dev,
1158                         "PHY reset is blocked due to SOL/IDER session.\n");
1159
1160         netdev->features = NETIF_F_SG |
1161                            NETIF_F_HW_CSUM |
1162                            NETIF_F_HW_VLAN_TX |
1163                            NETIF_F_HW_VLAN_RX |
1164                            NETIF_F_HW_VLAN_FILTER;
1165
1166         netdev->features |= NETIF_F_TSO;
1167         netdev->features |= NETIF_F_TSO6;
1168
1169 #ifdef CONFIG_IGB_LRO
1170         netdev->features |= NETIF_F_GRO;
1171 #endif
1172
1173         netdev->vlan_features |= NETIF_F_TSO;
1174         netdev->vlan_features |= NETIF_F_TSO6;
1175         netdev->vlan_features |= NETIF_F_HW_CSUM;
1176         netdev->vlan_features |= NETIF_F_SG;
1177
1178         if (pci_using_dac)
1179                 netdev->features |= NETIF_F_HIGHDMA;
1180
1181         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1182
1183         /* before reading the NVM, reset the controller to put the device in a
1184          * known good starting state */
1185         hw->mac.ops.reset_hw(hw);
1186
1187         /* make sure the NVM is good */
1188         if (igb_validate_nvm_checksum(hw) < 0) {
1189                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1190                 err = -EIO;
1191                 goto err_eeprom;
1192         }
1193
1194         /* copy the MAC address out of the NVM */
1195         if (hw->mac.ops.read_mac_addr(hw))
1196                 dev_err(&pdev->dev, "NVM Read Error\n");
1197
1198         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1199         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1200
1201         if (!is_valid_ether_addr(netdev->perm_addr)) {
1202                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1203                 err = -EIO;
1204                 goto err_eeprom;
1205         }
1206
1207         init_timer(&adapter->watchdog_timer);
1208         adapter->watchdog_timer.function = &igb_watchdog;
1209         adapter->watchdog_timer.data = (unsigned long) adapter;
1210
1211         init_timer(&adapter->phy_info_timer);
1212         adapter->phy_info_timer.function = &igb_update_phy_info;
1213         adapter->phy_info_timer.data = (unsigned long) adapter;
1214
1215         INIT_WORK(&adapter->reset_task, igb_reset_task);
1216         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1217
1218         /* Initialize link & ring properties that are user-changeable */
1219         adapter->tx_ring->count = 256;
1220         for (i = 0; i < adapter->num_tx_queues; i++)
1221                 adapter->tx_ring[i].count = adapter->tx_ring->count;
1222         adapter->rx_ring->count = 256;
1223         for (i = 0; i < adapter->num_rx_queues; i++)
1224                 adapter->rx_ring[i].count = adapter->rx_ring->count;
1225
1226         adapter->fc_autoneg = true;
1227         hw->mac.autoneg = true;
1228         hw->phy.autoneg_advertised = 0x2f;
1229
1230         hw->fc.original_type = e1000_fc_default;
1231         hw->fc.type = e1000_fc_default;
1232
1233         adapter->itr_setting = 3;
1234         adapter->itr = IGB_START_ITR;
1235
1236         igb_validate_mdi_setting(hw);
1237
1238         adapter->rx_csum = 1;
1239
1240         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1241          * enable the ACPI Magic Packet filter
1242          */
1243
1244         if (hw->bus.func == 0 ||
1245             hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1246                 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1247                                      &eeprom_data);
1248
1249         if (eeprom_data & eeprom_apme_mask)
1250                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1251
1252         /* now that we have the eeprom settings, apply the special cases where
1253          * the eeprom may be wrong or the board simply won't support wake on
1254          * lan on a particular port */
1255         switch (pdev->device) {
1256         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1257                 adapter->eeprom_wol = 0;
1258                 break;
1259         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1260         case E1000_DEV_ID_82576_FIBER:
1261         case E1000_DEV_ID_82576_SERDES:
1262                 /* Wake events only supported on port A for dual fiber
1263                  * regardless of eeprom setting */
1264                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1265                         adapter->eeprom_wol = 0;
1266                 break;
1267         }
1268
1269         /* initialize the wol settings based on the eeprom settings */
1270         adapter->wol = adapter->eeprom_wol;
1271         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1272
1273         /* reset the hardware with the new settings */
1274         igb_reset(adapter);
1275
1276         /* let the f/w know that the h/w is now under the control of the
1277          * driver. */
1278         igb_get_hw_control(adapter);
1279
1280         /* tell the stack to leave us alone until igb_open() is called */
1281         netif_carrier_off(netdev);
1282         netif_tx_stop_all_queues(netdev);
1283
1284         strcpy(netdev->name, "eth%d");
1285         err = register_netdev(netdev);
1286         if (err)
1287                 goto err_register;
1288
1289 #ifdef CONFIG_IGB_DCA
1290         if (dca_add_requester(&pdev->dev) == 0) {
1291                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1292                 dev_info(&pdev->dev, "DCA enabled\n");
1293                 /* Always use CB2 mode, difference is masked
1294                  * in the CB driver. */
1295                 wr32(E1000_DCA_CTRL, 2);
1296                 igb_setup_dca(adapter);
1297         }
1298 #endif
1299
1300         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1301         /* print bus type/speed/width info */
1302         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1303                  netdev->name,
1304                  ((hw->bus.speed == e1000_bus_speed_2500)
1305                   ? "2.5Gb/s" : "unknown"),
1306                  ((hw->bus.width == e1000_bus_width_pcie_x4)
1307                   ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1308                   ? "Width x1" : "unknown"),
1309                  netdev->dev_addr);
1310
1311         igb_read_part_num(hw, &part_num);
1312         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1313                 (part_num >> 8), (part_num & 0xff));
1314
1315         dev_info(&pdev->dev,
1316                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1317                 adapter->msix_entries ? "MSI-X" :
1318                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1319                 adapter->num_rx_queues, adapter->num_tx_queues);
1320
1321         return 0;
1322
1323 err_register:
1324         igb_release_hw_control(adapter);
1325 err_eeprom:
1326         if (!igb_check_reset_block(hw))
1327                 igb_reset_phy(hw);
1328
1329         if (hw->flash_address)
1330                 iounmap(hw->flash_address);
1331
1332         igb_free_queues(adapter);
1333 err_sw_init:
1334 err_hw_init:
1335         iounmap(hw->hw_addr);
1336 err_ioremap:
1337         free_netdev(netdev);
1338 err_alloc_etherdev:
1339         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1340                                      IORESOURCE_MEM));
1341 err_pci_reg:
1342 err_dma:
1343         pci_disable_device(pdev);
1344         return err;
1345 }
1346
1347 /**
1348  * igb_remove - Device Removal Routine
1349  * @pdev: PCI device information struct
1350  *
1351  * igb_remove is called by the PCI subsystem to alert the driver
1352  * that it should release a PCI device.  The could be caused by a
1353  * Hot-Plug event, or because the driver is going to be removed from
1354  * memory.
1355  **/
1356 static void __devexit igb_remove(struct pci_dev *pdev)
1357 {
1358         struct net_device *netdev = pci_get_drvdata(pdev);
1359         struct igb_adapter *adapter = netdev_priv(netdev);
1360 #ifdef CONFIG_IGB_DCA
1361         struct e1000_hw *hw = &adapter->hw;
1362 #endif
1363         int err;
1364
1365         /* flush_scheduled work may reschedule our watchdog task, so
1366          * explicitly disable watchdog tasks from being rescheduled  */
1367         set_bit(__IGB_DOWN, &adapter->state);
1368         del_timer_sync(&adapter->watchdog_timer);
1369         del_timer_sync(&adapter->phy_info_timer);
1370
1371         flush_scheduled_work();
1372
1373 #ifdef CONFIG_IGB_DCA
1374         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1375                 dev_info(&pdev->dev, "DCA disabled\n");
1376                 dca_remove_requester(&pdev->dev);
1377                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1378                 wr32(E1000_DCA_CTRL, 1);
1379         }
1380 #endif
1381
1382         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1383          * would have already happened in close and is redundant. */
1384         igb_release_hw_control(adapter);
1385
1386         unregister_netdev(netdev);
1387
1388         if (!igb_check_reset_block(&adapter->hw))
1389                 igb_reset_phy(&adapter->hw);
1390
1391         igb_reset_interrupt_capability(adapter);
1392
1393         igb_free_queues(adapter);
1394
1395         iounmap(adapter->hw.hw_addr);
1396         if (adapter->hw.flash_address)
1397                 iounmap(adapter->hw.flash_address);
1398         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1399                                      IORESOURCE_MEM));
1400
1401         free_netdev(netdev);
1402
1403         err = pci_disable_pcie_error_reporting(pdev);
1404         if (err)
1405                 dev_err(&pdev->dev,
1406                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1407
1408         pci_disable_device(pdev);
1409 }
1410
1411 /**
1412  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1413  * @adapter: board private structure to initialize
1414  *
1415  * igb_sw_init initializes the Adapter private data structure.
1416  * Fields are initialized based on PCI device information and
1417  * OS network device settings (MTU size).
1418  **/
1419 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1420 {
1421         struct e1000_hw *hw = &adapter->hw;
1422         struct net_device *netdev = adapter->netdev;
1423         struct pci_dev *pdev = adapter->pdev;
1424
1425         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1426
1427         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1428         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1429         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1430         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1431         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1432         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1433
1434         /* This call may decrease the number of queues depending on
1435          * interrupt mode. */
1436         igb_set_interrupt_capability(adapter);
1437
1438         if (igb_alloc_queues(adapter)) {
1439                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1440                 return -ENOMEM;
1441         }
1442
1443         /* Explicitly disable IRQ since the NIC can be in any state. */
1444         igb_irq_disable(adapter);
1445
1446         set_bit(__IGB_DOWN, &adapter->state);
1447         return 0;
1448 }
1449
1450 /**
1451  * igb_open - Called when a network interface is made active
1452  * @netdev: network interface device structure
1453  *
1454  * Returns 0 on success, negative value on failure
1455  *
1456  * The open entry point is called when a network interface is made
1457  * active by the system (IFF_UP).  At this point all resources needed
1458  * for transmit and receive operations are allocated, the interrupt
1459  * handler is registered with the OS, the watchdog timer is started,
1460  * and the stack is notified that the interface is ready.
1461  **/
1462 static int igb_open(struct net_device *netdev)
1463 {
1464         struct igb_adapter *adapter = netdev_priv(netdev);
1465         struct e1000_hw *hw = &adapter->hw;
1466         int err;
1467         int i;
1468
1469         /* disallow open during test */
1470         if (test_bit(__IGB_TESTING, &adapter->state))
1471                 return -EBUSY;
1472
1473         /* allocate transmit descriptors */
1474         err = igb_setup_all_tx_resources(adapter);
1475         if (err)
1476                 goto err_setup_tx;
1477
1478         /* allocate receive descriptors */
1479         err = igb_setup_all_rx_resources(adapter);
1480         if (err)
1481                 goto err_setup_rx;
1482
1483         /* e1000_power_up_phy(adapter); */
1484
1485         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1486         if ((adapter->hw.mng_cookie.status &
1487              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1488                 igb_update_mng_vlan(adapter);
1489
1490         /* before we allocate an interrupt, we must be ready to handle it.
1491          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1492          * as soon as we call pci_request_irq, so we have to setup our
1493          * clean_rx handler before we do so.  */
1494         igb_configure(adapter);
1495
1496         err = igb_request_irq(adapter);
1497         if (err)
1498                 goto err_req_irq;
1499
1500         /* From here on the code is the same as igb_up() */
1501         clear_bit(__IGB_DOWN, &adapter->state);
1502
1503         for (i = 0; i < adapter->num_rx_queues; i++)
1504                 napi_enable(&adapter->rx_ring[i].napi);
1505
1506         /* Clear any pending interrupts. */
1507         rd32(E1000_ICR);
1508
1509         igb_irq_enable(adapter);
1510
1511         netif_tx_start_all_queues(netdev);
1512
1513         /* Fire a link status change interrupt to start the watchdog. */
1514         wr32(E1000_ICS, E1000_ICS_LSC);
1515
1516         return 0;
1517
1518 err_req_irq:
1519         igb_release_hw_control(adapter);
1520         /* e1000_power_down_phy(adapter); */
1521         igb_free_all_rx_resources(adapter);
1522 err_setup_rx:
1523         igb_free_all_tx_resources(adapter);
1524 err_setup_tx:
1525         igb_reset(adapter);
1526
1527         return err;
1528 }
1529
1530 /**
1531  * igb_close - Disables a network interface
1532  * @netdev: network interface device structure
1533  *
1534  * Returns 0, this is not allowed to fail
1535  *
1536  * The close entry point is called when an interface is de-activated
1537  * by the OS.  The hardware is still under the driver's control, but
1538  * needs to be disabled.  A global MAC reset is issued to stop the
1539  * hardware, and all transmit and receive resources are freed.
1540  **/
1541 static int igb_close(struct net_device *netdev)
1542 {
1543         struct igb_adapter *adapter = netdev_priv(netdev);
1544
1545         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1546         igb_down(adapter);
1547
1548         igb_free_irq(adapter);
1549
1550         igb_free_all_tx_resources(adapter);
1551         igb_free_all_rx_resources(adapter);
1552
1553         /* kill manageability vlan ID if supported, but not if a vlan with
1554          * the same ID is registered on the host OS (let 8021q kill it) */
1555         if ((adapter->hw.mng_cookie.status &
1556                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1557              !(adapter->vlgrp &&
1558                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1559                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1560
1561         return 0;
1562 }
1563
1564 /**
1565  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1566  * @adapter: board private structure
1567  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1568  *
1569  * Return 0 on success, negative on failure
1570  **/
1571
1572 int igb_setup_tx_resources(struct igb_adapter *adapter,
1573                            struct igb_ring *tx_ring)
1574 {
1575         struct pci_dev *pdev = adapter->pdev;
1576         int size;
1577
1578         size = sizeof(struct igb_buffer) * tx_ring->count;
1579         tx_ring->buffer_info = vmalloc(size);
1580         if (!tx_ring->buffer_info)
1581                 goto err;
1582         memset(tx_ring->buffer_info, 0, size);
1583
1584         /* round up to nearest 4K */
1585         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1586         tx_ring->size = ALIGN(tx_ring->size, 4096);
1587
1588         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1589                                              &tx_ring->dma);
1590
1591         if (!tx_ring->desc)
1592                 goto err;
1593
1594         tx_ring->adapter = adapter;
1595         tx_ring->next_to_use = 0;
1596         tx_ring->next_to_clean = 0;
1597         return 0;
1598
1599 err:
1600         vfree(tx_ring->buffer_info);
1601         dev_err(&adapter->pdev->dev,
1602                 "Unable to allocate memory for the transmit descriptor ring\n");
1603         return -ENOMEM;
1604 }
1605
1606 /**
1607  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1608  *                                (Descriptors) for all queues
1609  * @adapter: board private structure
1610  *
1611  * Return 0 on success, negative on failure
1612  **/
1613 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1614 {
1615         int i, err = 0;
1616         int r_idx;
1617
1618         for (i = 0; i < adapter->num_tx_queues; i++) {
1619                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1620                 if (err) {
1621                         dev_err(&adapter->pdev->dev,
1622                                 "Allocation for Tx Queue %u failed\n", i);
1623                         for (i--; i >= 0; i--)
1624                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1625                         break;
1626                 }
1627         }
1628
1629         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1630                 r_idx = i % adapter->num_tx_queues;
1631                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1632         }
1633         return err;
1634 }
1635
1636 /**
1637  * igb_configure_tx - Configure transmit Unit after Reset
1638  * @adapter: board private structure
1639  *
1640  * Configure the Tx unit of the MAC after a reset.
1641  **/
1642 static void igb_configure_tx(struct igb_adapter *adapter)
1643 {
1644         u64 tdba;
1645         struct e1000_hw *hw = &adapter->hw;
1646         u32 tctl;
1647         u32 txdctl, txctrl;
1648         int i, j;
1649
1650         for (i = 0; i < adapter->num_tx_queues; i++) {
1651                 struct igb_ring *ring = &(adapter->tx_ring[i]);
1652                 j = ring->reg_idx;
1653                 wr32(E1000_TDLEN(j),
1654                                 ring->count * sizeof(struct e1000_tx_desc));
1655                 tdba = ring->dma;
1656                 wr32(E1000_TDBAL(j),
1657                                 tdba & 0x00000000ffffffffULL);
1658                 wr32(E1000_TDBAH(j), tdba >> 32);
1659
1660                 ring->head = E1000_TDH(j);
1661                 ring->tail = E1000_TDT(j);
1662                 writel(0, hw->hw_addr + ring->tail);
1663                 writel(0, hw->hw_addr + ring->head);
1664                 txdctl = rd32(E1000_TXDCTL(j));
1665                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1666                 wr32(E1000_TXDCTL(j), txdctl);
1667
1668                 /* Turn off Relaxed Ordering on head write-backs.  The
1669                  * writebacks MUST be delivered in order or it will
1670                  * completely screw up our bookeeping.
1671                  */
1672                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1673                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1674                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1675         }
1676
1677
1678
1679         /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1680
1681         /* Program the Transmit Control Register */
1682
1683         tctl = rd32(E1000_TCTL);
1684         tctl &= ~E1000_TCTL_CT;
1685         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1686                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1687
1688         igb_config_collision_dist(hw);
1689
1690         /* Setup Transmit Descriptor Settings for eop descriptor */
1691         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1692
1693         /* Enable transmits */
1694         tctl |= E1000_TCTL_EN;
1695
1696         wr32(E1000_TCTL, tctl);
1697 }
1698
1699 /**
1700  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1701  * @adapter: board private structure
1702  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1703  *
1704  * Returns 0 on success, negative on failure
1705  **/
1706
1707 int igb_setup_rx_resources(struct igb_adapter *adapter,
1708                            struct igb_ring *rx_ring)
1709 {
1710         struct pci_dev *pdev = adapter->pdev;
1711         int size, desc_len;
1712
1713         size = sizeof(struct igb_buffer) * rx_ring->count;
1714         rx_ring->buffer_info = vmalloc(size);
1715         if (!rx_ring->buffer_info)
1716                 goto err;
1717         memset(rx_ring->buffer_info, 0, size);
1718
1719         desc_len = sizeof(union e1000_adv_rx_desc);
1720
1721         /* Round up to nearest 4K */
1722         rx_ring->size = rx_ring->count * desc_len;
1723         rx_ring->size = ALIGN(rx_ring->size, 4096);
1724
1725         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1726                                              &rx_ring->dma);
1727
1728         if (!rx_ring->desc)
1729                 goto err;
1730
1731         rx_ring->next_to_clean = 0;
1732         rx_ring->next_to_use = 0;
1733
1734         rx_ring->adapter = adapter;
1735
1736         return 0;
1737
1738 err:
1739         vfree(rx_ring->buffer_info);
1740         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1741                 "the receive descriptor ring\n");
1742         return -ENOMEM;
1743 }
1744
1745 /**
1746  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1747  *                                (Descriptors) for all queues
1748  * @adapter: board private structure
1749  *
1750  * Return 0 on success, negative on failure
1751  **/
1752 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1753 {
1754         int i, err = 0;
1755
1756         for (i = 0; i < adapter->num_rx_queues; i++) {
1757                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1758                 if (err) {
1759                         dev_err(&adapter->pdev->dev,
1760                                 "Allocation for Rx Queue %u failed\n", i);
1761                         for (i--; i >= 0; i--)
1762                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1763                         break;
1764                 }
1765         }
1766
1767         return err;
1768 }
1769
1770 /**
1771  * igb_setup_rctl - configure the receive control registers
1772  * @adapter: Board private structure
1773  **/
1774 static void igb_setup_rctl(struct igb_adapter *adapter)
1775 {
1776         struct e1000_hw *hw = &adapter->hw;
1777         u32 rctl;
1778         u32 srrctl = 0;
1779         int i, j;
1780
1781         rctl = rd32(E1000_RCTL);
1782
1783         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1784         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1785
1786         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1787                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1788
1789         /*
1790          * enable stripping of CRC. It's unlikely this will break BMC
1791          * redirection as it did with e1000. Newer features require
1792          * that the HW strips the CRC.
1793         */
1794         rctl |= E1000_RCTL_SECRC;
1795
1796         /*
1797          * disable store bad packets and clear size bits.
1798          */
1799         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1800
1801         /* enable LPE when to prevent packets larger than max_frame_size */
1802                 rctl |= E1000_RCTL_LPE;
1803
1804         /* Setup buffer sizes */
1805         switch (adapter->rx_buffer_len) {
1806         case IGB_RXBUFFER_256:
1807                 rctl |= E1000_RCTL_SZ_256;
1808                 break;
1809         case IGB_RXBUFFER_512:
1810                 rctl |= E1000_RCTL_SZ_512;
1811                 break;
1812         default:
1813                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1814                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1815                 break;
1816         }
1817
1818         /* 82575 and greater support packet-split where the protocol
1819          * header is placed in skb->data and the packet data is
1820          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1821          * In the case of a non-split, skb->data is linearly filled,
1822          * followed by the page buffers.  Therefore, skb->data is
1823          * sized to hold the largest protocol header.
1824          */
1825         /* allocations using alloc_page take too long for regular MTU
1826          * so only enable packet split for jumbo frames */
1827         if (adapter->netdev->mtu > ETH_DATA_LEN) {
1828                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1829                 srrctl |= adapter->rx_ps_hdr_size <<
1830                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1831                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1832         } else {
1833                 adapter->rx_ps_hdr_size = 0;
1834                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1835         }
1836
1837         for (i = 0; i < adapter->num_rx_queues; i++) {
1838                 j = adapter->rx_ring[i].reg_idx;
1839                 wr32(E1000_SRRCTL(j), srrctl);
1840         }
1841
1842         wr32(E1000_RCTL, rctl);
1843 }
1844
1845 /**
1846  * igb_configure_rx - Configure receive Unit after Reset
1847  * @adapter: board private structure
1848  *
1849  * Configure the Rx unit of the MAC after a reset.
1850  **/
1851 static void igb_configure_rx(struct igb_adapter *adapter)
1852 {
1853         u64 rdba;
1854         struct e1000_hw *hw = &adapter->hw;
1855         u32 rctl, rxcsum;
1856         u32 rxdctl;
1857         int i, j;
1858
1859         /* disable receives while setting up the descriptors */
1860         rctl = rd32(E1000_RCTL);
1861         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1862         wrfl();
1863         mdelay(10);
1864
1865         if (adapter->itr_setting > 3)
1866                 wr32(E1000_ITR, adapter->itr);
1867
1868         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1869          * the Base and Length of the Rx Descriptor Ring */
1870         for (i = 0; i < adapter->num_rx_queues; i++) {
1871                 struct igb_ring *ring = &(adapter->rx_ring[i]);
1872                 j = ring->reg_idx;
1873                 rdba = ring->dma;
1874                 wr32(E1000_RDBAL(j),
1875                                 rdba & 0x00000000ffffffffULL);
1876                 wr32(E1000_RDBAH(j), rdba >> 32);
1877                 wr32(E1000_RDLEN(j),
1878                                ring->count * sizeof(union e1000_adv_rx_desc));
1879
1880                 ring->head = E1000_RDH(j);
1881                 ring->tail = E1000_RDT(j);
1882                 writel(0, hw->hw_addr + ring->tail);
1883                 writel(0, hw->hw_addr + ring->head);
1884
1885                 rxdctl = rd32(E1000_RXDCTL(j));
1886                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1887                 rxdctl &= 0xFFF00000;
1888                 rxdctl |= IGB_RX_PTHRESH;
1889                 rxdctl |= IGB_RX_HTHRESH << 8;
1890                 rxdctl |= IGB_RX_WTHRESH << 16;
1891                 wr32(E1000_RXDCTL(j), rxdctl);
1892         }
1893
1894         if (adapter->num_rx_queues > 1) {
1895                 u32 random[10];
1896                 u32 mrqc;
1897                 u32 j, shift;
1898                 union e1000_reta {
1899                         u32 dword;
1900                         u8  bytes[4];
1901                 } reta;
1902
1903                 get_random_bytes(&random[0], 40);
1904
1905                 if (hw->mac.type >= e1000_82576)
1906                         shift = 0;
1907                 else
1908                         shift = 6;
1909                 for (j = 0; j < (32 * 4); j++) {
1910                         reta.bytes[j & 3] =
1911                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
1912                         if ((j & 3) == 3)
1913                                 writel(reta.dword,
1914                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
1915                 }
1916                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1917
1918                 /* Fill out hash function seeds */
1919                 for (j = 0; j < 10; j++)
1920                         array_wr32(E1000_RSSRK(0), j, random[j]);
1921
1922                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1923                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
1924                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1925                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
1926                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1927                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
1928                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1929                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1930
1931
1932                 wr32(E1000_MRQC, mrqc);
1933
1934                 /* Multiqueue and raw packet checksumming are mutually
1935                  * exclusive.  Note that this not the same as TCP/IP
1936                  * checksumming, which works fine. */
1937                 rxcsum = rd32(E1000_RXCSUM);
1938                 rxcsum |= E1000_RXCSUM_PCSD;
1939                 wr32(E1000_RXCSUM, rxcsum);
1940         } else {
1941                 /* Enable Receive Checksum Offload for TCP and UDP */
1942                 rxcsum = rd32(E1000_RXCSUM);
1943                 if (adapter->rx_csum) {
1944                         rxcsum |= E1000_RXCSUM_TUOFL;
1945
1946                         /* Enable IPv4 payload checksum for UDP fragments
1947                          * Must be used in conjunction with packet-split. */
1948                         if (adapter->rx_ps_hdr_size)
1949                                 rxcsum |= E1000_RXCSUM_IPPCSE;
1950                 } else {
1951                         rxcsum &= ~E1000_RXCSUM_TUOFL;
1952                         /* don't need to clear IPPCSE as it defaults to 0 */
1953                 }
1954                 wr32(E1000_RXCSUM, rxcsum);
1955         }
1956
1957         if (adapter->vlgrp)
1958                 wr32(E1000_RLPML,
1959                                 adapter->max_frame_size + VLAN_TAG_SIZE);
1960         else
1961                 wr32(E1000_RLPML, adapter->max_frame_size);
1962
1963         /* Enable Receives */
1964         wr32(E1000_RCTL, rctl);
1965 }
1966
1967 /**
1968  * igb_free_tx_resources - Free Tx Resources per Queue
1969  * @tx_ring: Tx descriptor ring for a specific queue
1970  *
1971  * Free all transmit software resources
1972  **/
1973 void igb_free_tx_resources(struct igb_ring *tx_ring)
1974 {
1975         struct pci_dev *pdev = tx_ring->adapter->pdev;
1976
1977         igb_clean_tx_ring(tx_ring);
1978
1979         vfree(tx_ring->buffer_info);
1980         tx_ring->buffer_info = NULL;
1981
1982         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1983
1984         tx_ring->desc = NULL;
1985 }
1986
1987 /**
1988  * igb_free_all_tx_resources - Free Tx Resources for All Queues
1989  * @adapter: board private structure
1990  *
1991  * Free all transmit software resources
1992  **/
1993 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1994 {
1995         int i;
1996
1997         for (i = 0; i < adapter->num_tx_queues; i++)
1998                 igb_free_tx_resources(&adapter->tx_ring[i]);
1999 }
2000
2001 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2002                                            struct igb_buffer *buffer_info)
2003 {
2004         if (buffer_info->dma) {
2005                 pci_unmap_page(adapter->pdev,
2006                                 buffer_info->dma,
2007                                 buffer_info->length,
2008                                 PCI_DMA_TODEVICE);
2009                 buffer_info->dma = 0;
2010         }
2011         if (buffer_info->skb) {
2012                 dev_kfree_skb_any(buffer_info->skb);
2013                 buffer_info->skb = NULL;
2014         }
2015         buffer_info->time_stamp = 0;
2016         /* buffer_info must be completely set up in the transmit path */
2017 }
2018
2019 /**
2020  * igb_clean_tx_ring - Free Tx Buffers
2021  * @tx_ring: ring to be cleaned
2022  **/
2023 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2024 {
2025         struct igb_adapter *adapter = tx_ring->adapter;
2026         struct igb_buffer *buffer_info;
2027         unsigned long size;
2028         unsigned int i;
2029
2030         if (!tx_ring->buffer_info)
2031                 return;
2032         /* Free all the Tx ring sk_buffs */
2033
2034         for (i = 0; i < tx_ring->count; i++) {
2035                 buffer_info = &tx_ring->buffer_info[i];
2036                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2037         }
2038
2039         size = sizeof(struct igb_buffer) * tx_ring->count;
2040         memset(tx_ring->buffer_info, 0, size);
2041
2042         /* Zero out the descriptor ring */
2043
2044         memset(tx_ring->desc, 0, tx_ring->size);
2045
2046         tx_ring->next_to_use = 0;
2047         tx_ring->next_to_clean = 0;
2048
2049         writel(0, adapter->hw.hw_addr + tx_ring->head);
2050         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2051 }
2052
2053 /**
2054  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2055  * @adapter: board private structure
2056  **/
2057 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2058 {
2059         int i;
2060
2061         for (i = 0; i < adapter->num_tx_queues; i++)
2062                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2063 }
2064
2065 /**
2066  * igb_free_rx_resources - Free Rx Resources
2067  * @rx_ring: ring to clean the resources from
2068  *
2069  * Free all receive software resources
2070  **/
2071 void igb_free_rx_resources(struct igb_ring *rx_ring)
2072 {
2073         struct pci_dev *pdev = rx_ring->adapter->pdev;
2074
2075         igb_clean_rx_ring(rx_ring);
2076
2077         vfree(rx_ring->buffer_info);
2078         rx_ring->buffer_info = NULL;
2079
2080         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2081
2082         rx_ring->desc = NULL;
2083 }
2084
2085 /**
2086  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2087  * @adapter: board private structure
2088  *
2089  * Free all receive software resources
2090  **/
2091 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2092 {
2093         int i;
2094
2095         for (i = 0; i < adapter->num_rx_queues; i++)
2096                 igb_free_rx_resources(&adapter->rx_ring[i]);
2097 }
2098
2099 /**
2100  * igb_clean_rx_ring - Free Rx Buffers per Queue
2101  * @rx_ring: ring to free buffers from
2102  **/
2103 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2104 {
2105         struct igb_adapter *adapter = rx_ring->adapter;
2106         struct igb_buffer *buffer_info;
2107         struct pci_dev *pdev = adapter->pdev;
2108         unsigned long size;
2109         unsigned int i;
2110
2111         if (!rx_ring->buffer_info)
2112                 return;
2113         /* Free all the Rx ring sk_buffs */
2114         for (i = 0; i < rx_ring->count; i++) {
2115                 buffer_info = &rx_ring->buffer_info[i];
2116                 if (buffer_info->dma) {
2117                         if (adapter->rx_ps_hdr_size)
2118                                 pci_unmap_single(pdev, buffer_info->dma,
2119                                                  adapter->rx_ps_hdr_size,
2120                                                  PCI_DMA_FROMDEVICE);
2121                         else
2122                                 pci_unmap_single(pdev, buffer_info->dma,
2123                                                  adapter->rx_buffer_len,
2124                                                  PCI_DMA_FROMDEVICE);
2125                         buffer_info->dma = 0;
2126                 }
2127
2128                 if (buffer_info->skb) {
2129                         dev_kfree_skb(buffer_info->skb);
2130                         buffer_info->skb = NULL;
2131                 }
2132                 if (buffer_info->page) {
2133                         if (buffer_info->page_dma)
2134                                 pci_unmap_page(pdev, buffer_info->page_dma,
2135                                                PAGE_SIZE / 2,
2136                                                PCI_DMA_FROMDEVICE);
2137                         put_page(buffer_info->page);
2138                         buffer_info->page = NULL;
2139                         buffer_info->page_dma = 0;
2140                         buffer_info->page_offset = 0;
2141                 }
2142         }
2143
2144         size = sizeof(struct igb_buffer) * rx_ring->count;
2145         memset(rx_ring->buffer_info, 0, size);
2146
2147         /* Zero out the descriptor ring */
2148         memset(rx_ring->desc, 0, rx_ring->size);
2149
2150         rx_ring->next_to_clean = 0;
2151         rx_ring->next_to_use = 0;
2152
2153         writel(0, adapter->hw.hw_addr + rx_ring->head);
2154         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2155 }
2156
2157 /**
2158  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2159  * @adapter: board private structure
2160  **/
2161 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2162 {
2163         int i;
2164
2165         for (i = 0; i < adapter->num_rx_queues; i++)
2166                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2167 }
2168
2169 /**
2170  * igb_set_mac - Change the Ethernet Address of the NIC
2171  * @netdev: network interface device structure
2172  * @p: pointer to an address structure
2173  *
2174  * Returns 0 on success, negative on failure
2175  **/
2176 static int igb_set_mac(struct net_device *netdev, void *p)
2177 {
2178         struct igb_adapter *adapter = netdev_priv(netdev);
2179         struct sockaddr *addr = p;
2180
2181         if (!is_valid_ether_addr(addr->sa_data))
2182                 return -EADDRNOTAVAIL;
2183
2184         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2185         memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2186
2187         adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2188
2189         return 0;
2190 }
2191
2192 /**
2193  * igb_set_multi - Multicast and Promiscuous mode set
2194  * @netdev: network interface device structure
2195  *
2196  * The set_multi entry point is called whenever the multicast address
2197  * list or the network interface flags are updated.  This routine is
2198  * responsible for configuring the hardware for proper multicast,
2199  * promiscuous mode, and all-multi behavior.
2200  **/
2201 static void igb_set_multi(struct net_device *netdev)
2202 {
2203         struct igb_adapter *adapter = netdev_priv(netdev);
2204         struct e1000_hw *hw = &adapter->hw;
2205         struct e1000_mac_info *mac = &hw->mac;
2206         struct dev_mc_list *mc_ptr;
2207         u8  *mta_list;
2208         u32 rctl;
2209         int i;
2210
2211         /* Check for Promiscuous and All Multicast modes */
2212
2213         rctl = rd32(E1000_RCTL);
2214
2215         if (netdev->flags & IFF_PROMISC) {
2216                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2217                 rctl &= ~E1000_RCTL_VFE;
2218         } else {
2219                 if (netdev->flags & IFF_ALLMULTI) {
2220                         rctl |= E1000_RCTL_MPE;
2221                         rctl &= ~E1000_RCTL_UPE;
2222                 } else
2223                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2224                 rctl |= E1000_RCTL_VFE;
2225         }
2226         wr32(E1000_RCTL, rctl);
2227
2228         if (!netdev->mc_count) {
2229                 /* nothing to program, so clear mc list */
2230                 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
2231                                           mac->rar_entry_count);
2232                 return;
2233         }
2234
2235         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2236         if (!mta_list)
2237                 return;
2238
2239         /* The shared function expects a packed array of only addresses. */
2240         mc_ptr = netdev->mc_list;
2241
2242         for (i = 0; i < netdev->mc_count; i++) {
2243                 if (!mc_ptr)
2244                         break;
2245                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2246                 mc_ptr = mc_ptr->next;
2247         }
2248         igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2249                                       mac->rar_entry_count);
2250         kfree(mta_list);
2251 }
2252
2253 /* Need to wait a few seconds after link up to get diagnostic information from
2254  * the phy */
2255 static void igb_update_phy_info(unsigned long data)
2256 {
2257         struct igb_adapter *adapter = (struct igb_adapter *) data;
2258         igb_get_phy_info(&adapter->hw);
2259 }
2260
2261 /**
2262  * igb_has_link - check shared code for link and determine up/down
2263  * @adapter: pointer to driver private info
2264  **/
2265 static bool igb_has_link(struct igb_adapter *adapter)
2266 {
2267         struct e1000_hw *hw = &adapter->hw;
2268         bool link_active = false;
2269         s32 ret_val = 0;
2270
2271         /* get_link_status is set on LSC (link status) interrupt or
2272          * rx sequence error interrupt.  get_link_status will stay
2273          * false until the e1000_check_for_link establishes link
2274          * for copper adapters ONLY
2275          */
2276         switch (hw->phy.media_type) {
2277         case e1000_media_type_copper:
2278                 if (hw->mac.get_link_status) {
2279                         ret_val = hw->mac.ops.check_for_link(hw);
2280                         link_active = !hw->mac.get_link_status;
2281                 } else {
2282                         link_active = true;
2283                 }
2284                 break;
2285         case e1000_media_type_fiber:
2286                 ret_val = hw->mac.ops.check_for_link(hw);
2287                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2288                 break;
2289         case e1000_media_type_internal_serdes:
2290                 ret_val = hw->mac.ops.check_for_link(hw);
2291                 link_active = hw->mac.serdes_has_link;
2292                 break;
2293         default:
2294         case e1000_media_type_unknown:
2295                 break;
2296         }
2297
2298         return link_active;
2299 }
2300
2301 /**
2302  * igb_watchdog - Timer Call-back
2303  * @data: pointer to adapter cast into an unsigned long
2304  **/
2305 static void igb_watchdog(unsigned long data)
2306 {
2307         struct igb_adapter *adapter = (struct igb_adapter *)data;
2308         /* Do the rest outside of interrupt context */
2309         schedule_work(&adapter->watchdog_task);
2310 }
2311
2312 static void igb_watchdog_task(struct work_struct *work)
2313 {
2314         struct igb_adapter *adapter = container_of(work,
2315                                         struct igb_adapter, watchdog_task);
2316         struct e1000_hw *hw = &adapter->hw;
2317
2318         struct net_device *netdev = adapter->netdev;
2319         struct igb_ring *tx_ring = adapter->tx_ring;
2320         struct e1000_mac_info *mac = &adapter->hw.mac;
2321         u32 link;
2322         u32 eics = 0;
2323         s32 ret_val;
2324         int i;
2325
2326         link = igb_has_link(adapter);
2327         if ((netif_carrier_ok(netdev)) && link)
2328                 goto link_up;
2329
2330         if (link) {
2331                 if (!netif_carrier_ok(netdev)) {
2332                         u32 ctrl;
2333                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2334                                                    &adapter->link_speed,
2335                                                    &adapter->link_duplex);
2336
2337                         ctrl = rd32(E1000_CTRL);
2338                         /* Links status message must follow this format */
2339                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2340                                  "Flow Control: %s\n",
2341                                  netdev->name,
2342                                  adapter->link_speed,
2343                                  adapter->link_duplex == FULL_DUPLEX ?
2344                                  "Full Duplex" : "Half Duplex",
2345                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2346                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2347                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2348                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2349
2350                         /* tweak tx_queue_len according to speed/duplex and
2351                          * adjust the timeout factor */
2352                         netdev->tx_queue_len = adapter->tx_queue_len;
2353                         adapter->tx_timeout_factor = 1;
2354                         switch (adapter->link_speed) {
2355                         case SPEED_10:
2356                                 netdev->tx_queue_len = 10;
2357                                 adapter->tx_timeout_factor = 14;
2358                                 break;
2359                         case SPEED_100:
2360                                 netdev->tx_queue_len = 100;
2361                                 /* maybe add some timeout factor ? */
2362                                 break;
2363                         }
2364
2365                         netif_carrier_on(netdev);
2366                         netif_tx_wake_all_queues(netdev);
2367
2368                         if (!test_bit(__IGB_DOWN, &adapter->state))
2369                                 mod_timer(&adapter->phy_info_timer,
2370                                           round_jiffies(jiffies + 2 * HZ));
2371                 }
2372         } else {
2373                 if (netif_carrier_ok(netdev)) {
2374                         adapter->link_speed = 0;
2375                         adapter->link_duplex = 0;
2376                         /* Links status message must follow this format */
2377                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2378                                netdev->name);
2379                         netif_carrier_off(netdev);
2380                         netif_tx_stop_all_queues(netdev);
2381                         if (!test_bit(__IGB_DOWN, &adapter->state))
2382                                 mod_timer(&adapter->phy_info_timer,
2383                                           round_jiffies(jiffies + 2 * HZ));
2384                 }
2385         }
2386
2387 link_up:
2388         igb_update_stats(adapter);
2389
2390         mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2391         adapter->tpt_old = adapter->stats.tpt;
2392         mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2393         adapter->colc_old = adapter->stats.colc;
2394
2395         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2396         adapter->gorc_old = adapter->stats.gorc;
2397         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2398         adapter->gotc_old = adapter->stats.gotc;
2399
2400         igb_update_adaptive(&adapter->hw);
2401
2402         if (!netif_carrier_ok(netdev)) {
2403                 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2404                         /* We've lost link, so the controller stops DMA,
2405                          * but we've got queued Tx work that's never going
2406                          * to get done, so reset controller to flush Tx.
2407                          * (Do the reset outside of interrupt context). */
2408                         adapter->tx_timeout_count++;
2409                         schedule_work(&adapter->reset_task);
2410                 }
2411         }
2412
2413         /* Cause software interrupt to ensure rx ring is cleaned */
2414         if (adapter->msix_entries) {
2415                 for (i = 0; i < adapter->num_rx_queues; i++)
2416                         eics |= adapter->rx_ring[i].eims_value;
2417                 wr32(E1000_EICS, eics);
2418         } else {
2419                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2420         }
2421
2422         /* Force detection of hung controller every watchdog period */
2423         tx_ring->detect_tx_hung = true;
2424
2425         /* Reset the timer */
2426         if (!test_bit(__IGB_DOWN, &adapter->state))
2427                 mod_timer(&adapter->watchdog_timer,
2428                           round_jiffies(jiffies + 2 * HZ));
2429 }
2430
2431 enum latency_range {
2432         lowest_latency = 0,
2433         low_latency = 1,
2434         bulk_latency = 2,
2435         latency_invalid = 255
2436 };
2437
2438
2439 /**
2440  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2441  *
2442  *      Stores a new ITR value based on strictly on packet size.  This
2443  *      algorithm is less sophisticated than that used in igb_update_itr,
2444  *      due to the difficulty of synchronizing statistics across multiple
2445  *      receive rings.  The divisors and thresholds used by this fuction
2446  *      were determined based on theoretical maximum wire speed and testing
2447  *      data, in order to minimize response time while increasing bulk
2448  *      throughput.
2449  *      This functionality is controlled by the InterruptThrottleRate module
2450  *      parameter (see igb_param.c)
2451  *      NOTE:  This function is called only when operating in a multiqueue
2452  *             receive environment.
2453  * @rx_ring: pointer to ring
2454  **/
2455 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2456 {
2457         int new_val = rx_ring->itr_val;
2458         int avg_wire_size = 0;
2459         struct igb_adapter *adapter = rx_ring->adapter;
2460
2461         if (!rx_ring->total_packets)
2462                 goto clear_counts; /* no packets, so don't do anything */
2463
2464         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2465          * ints/sec - ITR timer value of 120 ticks.
2466          */
2467         if (adapter->link_speed != SPEED_1000) {
2468                 new_val = 120;
2469                 goto set_itr_val;
2470         }
2471         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2472
2473         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2474         avg_wire_size += 24;
2475
2476         /* Don't starve jumbo frames */
2477         avg_wire_size = min(avg_wire_size, 3000);
2478
2479         /* Give a little boost to mid-size frames */
2480         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2481                 new_val = avg_wire_size / 3;
2482         else
2483                 new_val = avg_wire_size / 2;
2484
2485 set_itr_val:
2486         if (new_val != rx_ring->itr_val) {
2487                 rx_ring->itr_val = new_val;
2488                 rx_ring->set_itr = 1;
2489         }
2490 clear_counts:
2491         rx_ring->total_bytes = 0;
2492         rx_ring->total_packets = 0;
2493 }
2494
2495 /**
2496  * igb_update_itr - update the dynamic ITR value based on statistics
2497  *      Stores a new ITR value based on packets and byte
2498  *      counts during the last interrupt.  The advantage of per interrupt
2499  *      computation is faster updates and more accurate ITR for the current
2500  *      traffic pattern.  Constants in this function were computed
2501  *      based on theoretical maximum wire speed and thresholds were set based
2502  *      on testing data as well as attempting to minimize response time
2503  *      while increasing bulk throughput.
2504  *      this functionality is controlled by the InterruptThrottleRate module
2505  *      parameter (see igb_param.c)
2506  *      NOTE:  These calculations are only valid when operating in a single-
2507  *             queue environment.
2508  * @adapter: pointer to adapter
2509  * @itr_setting: current adapter->itr
2510  * @packets: the number of packets during this measurement interval
2511  * @bytes: the number of bytes during this measurement interval
2512  **/
2513 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2514                                    int packets, int bytes)
2515 {
2516         unsigned int retval = itr_setting;
2517
2518         if (packets == 0)
2519                 goto update_itr_done;
2520
2521         switch (itr_setting) {
2522         case lowest_latency:
2523                 /* handle TSO and jumbo frames */
2524                 if (bytes/packets > 8000)
2525                         retval = bulk_latency;
2526                 else if ((packets < 5) && (bytes > 512))
2527                         retval = low_latency;
2528                 break;
2529         case low_latency:  /* 50 usec aka 20000 ints/s */
2530                 if (bytes > 10000) {
2531                         /* this if handles the TSO accounting */
2532                         if (bytes/packets > 8000) {
2533                                 retval = bulk_latency;
2534                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2535                                 retval = bulk_latency;
2536                         } else if ((packets > 35)) {
2537                                 retval = lowest_latency;
2538                         }
2539                 } else if (bytes/packets > 2000) {
2540                         retval = bulk_latency;
2541                 } else if (packets <= 2 && bytes < 512) {
2542                         retval = lowest_latency;
2543                 }
2544                 break;
2545         case bulk_latency: /* 250 usec aka 4000 ints/s */
2546                 if (bytes > 25000) {
2547                         if (packets > 35)
2548                                 retval = low_latency;
2549                 } else if (bytes < 6000) {
2550                         retval = low_latency;
2551                 }
2552                 break;
2553         }
2554
2555 update_itr_done:
2556         return retval;
2557 }
2558
2559 static void igb_set_itr(struct igb_adapter *adapter)
2560 {
2561         u16 current_itr;
2562         u32 new_itr = adapter->itr;
2563
2564         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2565         if (adapter->link_speed != SPEED_1000) {
2566                 current_itr = 0;
2567                 new_itr = 4000;
2568                 goto set_itr_now;
2569         }
2570
2571         adapter->rx_itr = igb_update_itr(adapter,
2572                                     adapter->rx_itr,
2573                                     adapter->rx_ring->total_packets,
2574                                     adapter->rx_ring->total_bytes);
2575
2576         if (adapter->rx_ring->buddy) {
2577                 adapter->tx_itr = igb_update_itr(adapter,
2578                                             adapter->tx_itr,
2579                                             adapter->tx_ring->total_packets,
2580                                             adapter->tx_ring->total_bytes);
2581
2582                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2583         } else {
2584                 current_itr = adapter->rx_itr;
2585         }
2586
2587         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2588         if (adapter->itr_setting == 3 &&
2589             current_itr == lowest_latency)
2590                 current_itr = low_latency;
2591
2592         switch (current_itr) {
2593         /* counts and packets in update_itr are dependent on these numbers */
2594         case lowest_latency:
2595                 new_itr = 70000;
2596                 break;
2597         case low_latency:
2598                 new_itr = 20000; /* aka hwitr = ~200 */
2599                 break;
2600         case bulk_latency:
2601                 new_itr = 4000;
2602                 break;
2603         default:
2604                 break;
2605         }
2606
2607 set_itr_now:
2608         adapter->rx_ring->total_bytes = 0;
2609         adapter->rx_ring->total_packets = 0;
2610         if (adapter->rx_ring->buddy) {
2611                 adapter->rx_ring->buddy->total_bytes = 0;
2612                 adapter->rx_ring->buddy->total_packets = 0;
2613         }
2614
2615         if (new_itr != adapter->itr) {
2616                 /* this attempts to bias the interrupt rate towards Bulk
2617                  * by adding intermediate steps when interrupt rate is
2618                  * increasing */
2619                 new_itr = new_itr > adapter->itr ?
2620                              min(adapter->itr + (new_itr >> 2), new_itr) :
2621                              new_itr;
2622                 /* Don't write the value here; it resets the adapter's
2623                  * internal timer, and causes us to delay far longer than
2624                  * we should between interrupts.  Instead, we write the ITR
2625                  * value at the beginning of the next interrupt so the timing
2626                  * ends up being correct.
2627                  */
2628                 adapter->itr = new_itr;
2629                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2630                 adapter->rx_ring->set_itr = 1;
2631         }
2632
2633         return;
2634 }
2635
2636
2637 #define IGB_TX_FLAGS_CSUM               0x00000001
2638 #define IGB_TX_FLAGS_VLAN               0x00000002
2639 #define IGB_TX_FLAGS_TSO                0x00000004
2640 #define IGB_TX_FLAGS_IPV4               0x00000008
2641 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2642 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2643
2644 static inline int igb_tso_adv(struct igb_adapter *adapter,
2645                               struct igb_ring *tx_ring,
2646                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2647 {
2648         struct e1000_adv_tx_context_desc *context_desc;
2649         unsigned int i;
2650         int err;
2651         struct igb_buffer *buffer_info;
2652         u32 info = 0, tu_cmd = 0;
2653         u32 mss_l4len_idx, l4len;
2654         *hdr_len = 0;
2655
2656         if (skb_header_cloned(skb)) {
2657                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2658                 if (err)
2659                         return err;
2660         }
2661
2662         l4len = tcp_hdrlen(skb);
2663         *hdr_len += l4len;
2664
2665         if (skb->protocol == htons(ETH_P_IP)) {
2666                 struct iphdr *iph = ip_hdr(skb);
2667                 iph->tot_len = 0;
2668                 iph->check = 0;
2669                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2670                                                          iph->daddr, 0,
2671                                                          IPPROTO_TCP,
2672                                                          0);
2673         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2674                 ipv6_hdr(skb)->payload_len = 0;
2675                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2676                                                        &ipv6_hdr(skb)->daddr,
2677                                                        0, IPPROTO_TCP, 0);
2678         }
2679
2680         i = tx_ring->next_to_use;
2681
2682         buffer_info = &tx_ring->buffer_info[i];
2683         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2684         /* VLAN MACLEN IPLEN */
2685         if (tx_flags & IGB_TX_FLAGS_VLAN)
2686                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2687         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2688         *hdr_len += skb_network_offset(skb);
2689         info |= skb_network_header_len(skb);
2690         *hdr_len += skb_network_header_len(skb);
2691         context_desc->vlan_macip_lens = cpu_to_le32(info);
2692
2693         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2694         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2695
2696         if (skb->protocol == htons(ETH_P_IP))
2697                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2698         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2699
2700         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2701
2702         /* MSS L4LEN IDX */
2703         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2704         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2705
2706         /* Context index must be unique per ring. */
2707         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2708                 mss_l4len_idx |= tx_ring->queue_index << 4;
2709
2710         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2711         context_desc->seqnum_seed = 0;
2712
2713         buffer_info->time_stamp = jiffies;
2714         buffer_info->next_to_watch = i;
2715         buffer_info->dma = 0;
2716         i++;
2717         if (i == tx_ring->count)
2718                 i = 0;
2719
2720         tx_ring->next_to_use = i;
2721
2722         return true;
2723 }
2724
2725 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2726                                         struct igb_ring *tx_ring,
2727                                         struct sk_buff *skb, u32 tx_flags)
2728 {
2729         struct e1000_adv_tx_context_desc *context_desc;
2730         unsigned int i;
2731         struct igb_buffer *buffer_info;
2732         u32 info = 0, tu_cmd = 0;
2733
2734         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2735             (tx_flags & IGB_TX_FLAGS_VLAN)) {
2736                 i = tx_ring->next_to_use;
2737                 buffer_info = &tx_ring->buffer_info[i];
2738                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2739
2740                 if (tx_flags & IGB_TX_FLAGS_VLAN)
2741                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2742                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2743                 if (skb->ip_summed == CHECKSUM_PARTIAL)
2744                         info |= skb_network_header_len(skb);
2745
2746                 context_desc->vlan_macip_lens = cpu_to_le32(info);
2747
2748                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2749
2750                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2751                         switch (skb->protocol) {
2752                         case cpu_to_be16(ETH_P_IP):
2753                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2754                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2755                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2756                                 break;
2757                         case cpu_to_be16(ETH_P_IPV6):
2758                                 /* XXX what about other V6 headers?? */
2759                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2760                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2761                                 break;
2762                         default:
2763                                 if (unlikely(net_ratelimit()))
2764                                         dev_warn(&adapter->pdev->dev,
2765                                             "partial checksum but proto=%x!\n",
2766                                             skb->protocol);
2767                                 break;
2768                         }
2769                 }
2770
2771                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2772                 context_desc->seqnum_seed = 0;
2773                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2774                         context_desc->mss_l4len_idx =
2775                                 cpu_to_le32(tx_ring->queue_index << 4);
2776
2777                 buffer_info->time_stamp = jiffies;
2778                 buffer_info->next_to_watch = i;
2779                 buffer_info->dma = 0;
2780
2781                 i++;
2782                 if (i == tx_ring->count)
2783                         i = 0;
2784                 tx_ring->next_to_use = i;
2785
2786                 return true;
2787         }
2788
2789
2790         return false;
2791 }
2792
2793 #define IGB_MAX_TXD_PWR 16
2794 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
2795
2796 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2797                                  struct igb_ring *tx_ring, struct sk_buff *skb,
2798                                  unsigned int first)
2799 {
2800         struct igb_buffer *buffer_info;
2801         unsigned int len = skb_headlen(skb);
2802         unsigned int count = 0, i;
2803         unsigned int f;
2804
2805         i = tx_ring->next_to_use;
2806
2807         buffer_info = &tx_ring->buffer_info[i];
2808         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2809         buffer_info->length = len;
2810         /* set time_stamp *before* dma to help avoid a possible race */
2811         buffer_info->time_stamp = jiffies;
2812         buffer_info->next_to_watch = i;
2813         buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2814                                           PCI_DMA_TODEVICE);
2815         count++;
2816         i++;
2817         if (i == tx_ring->count)
2818                 i = 0;
2819
2820         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2821                 struct skb_frag_struct *frag;
2822
2823                 frag = &skb_shinfo(skb)->frags[f];
2824                 len = frag->size;
2825
2826                 buffer_info = &tx_ring->buffer_info[i];
2827                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2828                 buffer_info->length = len;
2829                 buffer_info->time_stamp = jiffies;
2830                 buffer_info->next_to_watch = i;
2831                 buffer_info->dma = pci_map_page(adapter->pdev,
2832                                                 frag->page,
2833                                                 frag->page_offset,
2834                                                 len,
2835                                                 PCI_DMA_TODEVICE);
2836
2837                 count++;
2838                 i++;
2839                 if (i == tx_ring->count)
2840                         i = 0;
2841         }
2842
2843         i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2844         tx_ring->buffer_info[i].skb = skb;
2845         tx_ring->buffer_info[first].next_to_watch = i;
2846
2847         return count;
2848 }
2849
2850 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2851                                     struct igb_ring *tx_ring,
2852                                     int tx_flags, int count, u32 paylen,
2853                                     u8 hdr_len)
2854 {
2855         union e1000_adv_tx_desc *tx_desc = NULL;
2856         struct igb_buffer *buffer_info;
2857         u32 olinfo_status = 0, cmd_type_len;
2858         unsigned int i;
2859
2860         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2861                         E1000_ADVTXD_DCMD_DEXT);
2862
2863         if (tx_flags & IGB_TX_FLAGS_VLAN)
2864                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2865
2866         if (tx_flags & IGB_TX_FLAGS_TSO) {
2867                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2868
2869                 /* insert tcp checksum */
2870                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2871
2872                 /* insert ip checksum */
2873                 if (tx_flags & IGB_TX_FLAGS_IPV4)
2874                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2875
2876         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2877                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2878         }
2879
2880         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2881             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2882                          IGB_TX_FLAGS_VLAN)))
2883                 olinfo_status |= tx_ring->queue_index << 4;
2884
2885         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2886
2887         i = tx_ring->next_to_use;
2888         while (count--) {
2889                 buffer_info = &tx_ring->buffer_info[i];
2890                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2891                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2892                 tx_desc->read.cmd_type_len =
2893                         cpu_to_le32(cmd_type_len | buffer_info->length);
2894                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2895                 i++;
2896                 if (i == tx_ring->count)
2897                         i = 0;
2898         }
2899
2900         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2901         /* Force memory writes to complete before letting h/w
2902          * know there are new descriptors to fetch.  (Only
2903          * applicable for weak-ordered memory model archs,
2904          * such as IA-64). */
2905         wmb();
2906
2907         tx_ring->next_to_use = i;
2908         writel(i, adapter->hw.hw_addr + tx_ring->tail);
2909         /* we need this if more than one processor can write to our tail
2910          * at a time, it syncronizes IO on IA64/Altix systems */
2911         mmiowb();
2912 }
2913
2914 static int __igb_maybe_stop_tx(struct net_device *netdev,
2915                                struct igb_ring *tx_ring, int size)
2916 {
2917         struct igb_adapter *adapter = netdev_priv(netdev);
2918
2919         netif_stop_subqueue(netdev, tx_ring->queue_index);
2920
2921         /* Herbert's original patch had:
2922          *  smp_mb__after_netif_stop_queue();
2923          * but since that doesn't exist yet, just open code it. */
2924         smp_mb();
2925
2926         /* We need to check again in a case another CPU has just
2927          * made room available. */
2928         if (IGB_DESC_UNUSED(tx_ring) < size)
2929                 return -EBUSY;
2930
2931         /* A reprieve! */
2932         netif_wake_subqueue(netdev, tx_ring->queue_index);
2933         ++adapter->restart_queue;
2934         return 0;
2935 }
2936
2937 static int igb_maybe_stop_tx(struct net_device *netdev,
2938                              struct igb_ring *tx_ring, int size)
2939 {
2940         if (IGB_DESC_UNUSED(tx_ring) >= size)
2941                 return 0;
2942         return __igb_maybe_stop_tx(netdev, tx_ring, size);
2943 }
2944
2945 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2946
2947 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2948                                    struct net_device *netdev,
2949                                    struct igb_ring *tx_ring)
2950 {
2951         struct igb_adapter *adapter = netdev_priv(netdev);
2952         unsigned int first;
2953         unsigned int tx_flags = 0;
2954         unsigned int len;
2955         u8 hdr_len = 0;
2956         int tso = 0;
2957
2958         len = skb_headlen(skb);
2959
2960         if (test_bit(__IGB_DOWN, &adapter->state)) {
2961                 dev_kfree_skb_any(skb);
2962                 return NETDEV_TX_OK;
2963         }
2964
2965         if (skb->len <= 0) {
2966                 dev_kfree_skb_any(skb);
2967                 return NETDEV_TX_OK;
2968         }
2969
2970         /* need: 1 descriptor per page,
2971          *       + 2 desc gap to keep tail from touching head,
2972          *       + 1 desc for skb->data,
2973          *       + 1 desc for context descriptor,
2974          * otherwise try next time */
2975         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2976                 /* this is a hard error */
2977                 return NETDEV_TX_BUSY;
2978         }
2979         skb_orphan(skb);
2980
2981         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2982                 tx_flags |= IGB_TX_FLAGS_VLAN;
2983                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2984         }
2985
2986         if (skb->protocol == htons(ETH_P_IP))
2987                 tx_flags |= IGB_TX_FLAGS_IPV4;
2988
2989         first = tx_ring->next_to_use;
2990
2991         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2992                                               &hdr_len) : 0;
2993
2994         if (tso < 0) {
2995                 dev_kfree_skb_any(skb);
2996                 return NETDEV_TX_OK;
2997         }
2998
2999         if (tso)
3000                 tx_flags |= IGB_TX_FLAGS_TSO;
3001         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3002                         if (skb->ip_summed == CHECKSUM_PARTIAL)
3003                                 tx_flags |= IGB_TX_FLAGS_CSUM;
3004
3005         igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3006                          igb_tx_map_adv(adapter, tx_ring, skb, first),
3007                          skb->len, hdr_len);
3008
3009         netdev->trans_start = jiffies;
3010
3011         /* Make sure there is space in the ring for the next send. */
3012         igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3013
3014         return NETDEV_TX_OK;
3015 }
3016
3017 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3018 {
3019         struct igb_adapter *adapter = netdev_priv(netdev);
3020         struct igb_ring *tx_ring;
3021
3022         int r_idx = 0;
3023         r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3024         tx_ring = adapter->multi_tx_table[r_idx];
3025
3026         /* This goes back to the question of how to logically map a tx queue
3027          * to a flow.  Right now, performance is impacted slightly negatively
3028          * if using multiple tx queues.  If the stack breaks away from a
3029          * single qdisc implementation, we can look at this again. */
3030         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3031 }
3032
3033 /**
3034  * igb_tx_timeout - Respond to a Tx Hang
3035  * @netdev: network interface device structure
3036  **/
3037 static void igb_tx_timeout(struct net_device *netdev)
3038 {
3039         struct igb_adapter *adapter = netdev_priv(netdev);
3040         struct e1000_hw *hw = &adapter->hw;
3041
3042         /* Do the reset outside of interrupt context */
3043         adapter->tx_timeout_count++;
3044         schedule_work(&adapter->reset_task);
3045         wr32(E1000_EICS, adapter->eims_enable_mask &
3046                 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3047 }
3048
3049 static void igb_reset_task(struct work_struct *work)
3050 {
3051         struct igb_adapter *adapter;
3052         adapter = container_of(work, struct igb_adapter, reset_task);
3053
3054         igb_reinit_locked(adapter);
3055 }
3056
3057 /**
3058  * igb_get_stats - Get System Network Statistics
3059  * @netdev: network interface device structure
3060  *
3061  * Returns the address of the device statistics structure.
3062  * The statistics are actually updated from the timer callback.
3063  **/
3064 static struct net_device_stats *
3065 igb_get_stats(struct net_device *netdev)
3066 {
3067         struct igb_adapter *adapter = netdev_priv(netdev);
3068
3069         /* only return the current stats */
3070         return &adapter->net_stats;
3071 }
3072
3073 /**
3074  * igb_change_mtu - Change the Maximum Transfer Unit
3075  * @netdev: network interface device structure
3076  * @new_mtu: new value for maximum frame size
3077  *
3078  * Returns 0 on success, negative on failure
3079  **/
3080 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3081 {
3082         struct igb_adapter *adapter = netdev_priv(netdev);
3083         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3084
3085         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3086             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3087                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3088                 return -EINVAL;
3089         }
3090
3091 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3092         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3093                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3094                 return -EINVAL;
3095         }
3096
3097         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3098                 msleep(1);
3099         /* igb_down has a dependency on max_frame_size */
3100         adapter->max_frame_size = max_frame;
3101         if (netif_running(netdev))
3102                 igb_down(adapter);
3103
3104         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3105          * means we reserve 2 more, this pushes us to allocate from the next
3106          * larger slab size.
3107          * i.e. RXBUFFER_2048 --> size-4096 slab
3108          */
3109
3110         if (max_frame <= IGB_RXBUFFER_256)
3111                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3112         else if (max_frame <= IGB_RXBUFFER_512)
3113                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3114         else if (max_frame <= IGB_RXBUFFER_1024)
3115                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3116         else if (max_frame <= IGB_RXBUFFER_2048)
3117                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3118         else
3119 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3120                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3121 #else
3122                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3123 #endif
3124         /* adjust allocation if LPE protects us, and we aren't using SBP */
3125         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3126              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3127                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3128
3129         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3130                  netdev->mtu, new_mtu);
3131         netdev->mtu = new_mtu;
3132
3133         if (netif_running(netdev))
3134                 igb_up(adapter);
3135         else
3136                 igb_reset(adapter);
3137
3138         clear_bit(__IGB_RESETTING, &adapter->state);
3139
3140         return 0;
3141 }
3142
3143 /**
3144  * igb_update_stats - Update the board statistics counters
3145  * @adapter: board private structure
3146  **/
3147
3148 void igb_update_stats(struct igb_adapter *adapter)
3149 {
3150         struct e1000_hw *hw = &adapter->hw;
3151         struct pci_dev *pdev = adapter->pdev;
3152         u16 phy_tmp;
3153
3154 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3155
3156         /*
3157          * Prevent stats update while adapter is being reset, or if the pci
3158          * connection is down.
3159          */
3160         if (adapter->link_speed == 0)
3161                 return;
3162         if (pci_channel_offline(pdev))
3163                 return;
3164
3165         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3166         adapter->stats.gprc += rd32(E1000_GPRC);
3167         adapter->stats.gorc += rd32(E1000_GORCL);
3168         rd32(E1000_GORCH); /* clear GORCL */
3169         adapter->stats.bprc += rd32(E1000_BPRC);
3170         adapter->stats.mprc += rd32(E1000_MPRC);
3171         adapter->stats.roc += rd32(E1000_ROC);
3172
3173         adapter->stats.prc64 += rd32(E1000_PRC64);
3174         adapter->stats.prc127 += rd32(E1000_PRC127);
3175         adapter->stats.prc255 += rd32(E1000_PRC255);
3176         adapter->stats.prc511 += rd32(E1000_PRC511);
3177         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3178         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3179         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3180         adapter->stats.sec += rd32(E1000_SEC);
3181
3182         adapter->stats.mpc += rd32(E1000_MPC);
3183         adapter->stats.scc += rd32(E1000_SCC);
3184         adapter->stats.ecol += rd32(E1000_ECOL);
3185         adapter->stats.mcc += rd32(E1000_MCC);
3186         adapter->stats.latecol += rd32(E1000_LATECOL);
3187         adapter->stats.dc += rd32(E1000_DC);
3188         adapter->stats.rlec += rd32(E1000_RLEC);
3189         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3190         adapter->stats.xontxc += rd32(E1000_XONTXC);
3191         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3192         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3193         adapter->stats.fcruc += rd32(E1000_FCRUC);
3194         adapter->stats.gptc += rd32(E1000_GPTC);
3195         adapter->stats.gotc += rd32(E1000_GOTCL);
3196         rd32(E1000_GOTCH); /* clear GOTCL */
3197         adapter->stats.rnbc += rd32(E1000_RNBC);
3198         adapter->stats.ruc += rd32(E1000_RUC);
3199         adapter->stats.rfc += rd32(E1000_RFC);
3200         adapter->stats.rjc += rd32(E1000_RJC);
3201         adapter->stats.tor += rd32(E1000_TORH);
3202         adapter->stats.tot += rd32(E1000_TOTH);
3203         adapter->stats.tpr += rd32(E1000_TPR);
3204
3205         adapter->stats.ptc64 += rd32(E1000_PTC64);
3206         adapter->stats.ptc127 += rd32(E1000_PTC127);
3207         adapter->stats.ptc255 += rd32(E1000_PTC255);
3208         adapter->stats.ptc511 += rd32(E1000_PTC511);
3209         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3210         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3211
3212         adapter->stats.mptc += rd32(E1000_MPTC);
3213         adapter->stats.bptc += rd32(E1000_BPTC);
3214
3215         /* used for adaptive IFS */
3216
3217         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3218         adapter->stats.tpt += hw->mac.tx_packet_delta;
3219         hw->mac.collision_delta = rd32(E1000_COLC);
3220         adapter->stats.colc += hw->mac.collision_delta;
3221
3222         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3223         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3224         adapter->stats.tncrs += rd32(E1000_TNCRS);
3225         adapter->stats.tsctc += rd32(E1000_TSCTC);
3226         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3227
3228         adapter->stats.iac += rd32(E1000_IAC);
3229         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3230         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3231         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3232         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3233         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3234         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3235         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3236         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3237
3238         /* Fill out the OS statistics structure */
3239         adapter->net_stats.multicast = adapter->stats.mprc;
3240         adapter->net_stats.collisions = adapter->stats.colc;
3241
3242         /* Rx Errors */
3243
3244         /* RLEC on some newer hardware can be incorrect so build
3245         * our own version based on RUC and ROC */
3246         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3247                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3248                 adapter->stats.ruc + adapter->stats.roc +
3249                 adapter->stats.cexterr;
3250         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3251                                               adapter->stats.roc;
3252         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3253         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3254         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3255
3256         /* Tx Errors */
3257         adapter->net_stats.tx_errors = adapter->stats.ecol +
3258                                        adapter->stats.latecol;
3259         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3260         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3261         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3262
3263         /* Tx Dropped needs to be maintained elsewhere */
3264
3265         /* Phy Stats */
3266         if (hw->phy.media_type == e1000_media_type_copper) {
3267                 if ((adapter->link_speed == SPEED_1000) &&
3268                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
3269                                               &phy_tmp))) {
3270                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3271                         adapter->phy_stats.idle_errors += phy_tmp;
3272                 }
3273         }
3274
3275         /* Management Stats */
3276         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3277         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3278         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3279 }
3280
3281
3282 static irqreturn_t igb_msix_other(int irq, void *data)
3283 {
3284         struct net_device *netdev = data;
3285         struct igb_adapter *adapter = netdev_priv(netdev);
3286         struct e1000_hw *hw = &adapter->hw;
3287         u32 icr = rd32(E1000_ICR);
3288
3289         /* reading ICR causes bit 31 of EICR to be cleared */
3290         if (!(icr & E1000_ICR_LSC))
3291                 goto no_link_interrupt;
3292         hw->mac.get_link_status = 1;
3293         /* guard against interrupt when we're going down */
3294         if (!test_bit(__IGB_DOWN, &adapter->state))
3295                 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3296
3297 no_link_interrupt:
3298         wr32(E1000_IMS, E1000_IMS_LSC);
3299         wr32(E1000_EIMS, adapter->eims_other);
3300
3301         return IRQ_HANDLED;
3302 }
3303
3304 static irqreturn_t igb_msix_tx(int irq, void *data)
3305 {
3306         struct igb_ring *tx_ring = data;
3307         struct igb_adapter *adapter = tx_ring->adapter;
3308         struct e1000_hw *hw = &adapter->hw;
3309
3310 #ifdef CONFIG_IGB_DCA
3311         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3312                 igb_update_tx_dca(tx_ring);
3313 #endif
3314         tx_ring->total_bytes = 0;
3315         tx_ring->total_packets = 0;
3316
3317         /* auto mask will automatically reenable the interrupt when we write
3318          * EICS */
3319         if (!igb_clean_tx_irq(tx_ring))
3320                 /* Ring was not completely cleaned, so fire another interrupt */
3321                 wr32(E1000_EICS, tx_ring->eims_value);
3322         else
3323                 wr32(E1000_EIMS, tx_ring->eims_value);
3324
3325         return IRQ_HANDLED;
3326 }
3327
3328 static void igb_write_itr(struct igb_ring *ring)
3329 {
3330         struct e1000_hw *hw = &ring->adapter->hw;
3331         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3332                 switch (hw->mac.type) {
3333                 case e1000_82576:
3334                         wr32(ring->itr_register,
3335                              ring->itr_val |
3336                              0x80000000);
3337                         break;
3338                 default:
3339                         wr32(ring->itr_register,
3340                              ring->itr_val |
3341                              (ring->itr_val << 16));
3342                         break;
3343                 }
3344                 ring->set_itr = 0;
3345         }
3346 }
3347
3348 static irqreturn_t igb_msix_rx(int irq, void *data)
3349 {
3350         struct igb_ring *rx_ring = data;
3351
3352         /* Write the ITR value calculated at the end of the
3353          * previous interrupt.
3354          */
3355
3356         igb_write_itr(rx_ring);
3357
3358         if (napi_schedule_prep(&rx_ring->napi))
3359                 __napi_schedule(&rx_ring->napi);
3360
3361 #ifdef CONFIG_IGB_DCA
3362         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3363                 igb_update_rx_dca(rx_ring);
3364 #endif
3365                 return IRQ_HANDLED;
3366 }
3367
3368 #ifdef CONFIG_IGB_DCA
3369 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3370 {
3371         u32 dca_rxctrl;
3372         struct igb_adapter *adapter = rx_ring->adapter;
3373         struct e1000_hw *hw = &adapter->hw;
3374         int cpu = get_cpu();
3375         int q = rx_ring->reg_idx;
3376
3377         if (rx_ring->cpu != cpu) {
3378                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3379                 if (hw->mac.type == e1000_82576) {
3380                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3381                         dca_rxctrl |= dca_get_tag(cpu) <<
3382                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3383                 } else {
3384                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3385                         dca_rxctrl |= dca_get_tag(cpu);
3386                 }
3387                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3388                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3389                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3390                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3391                 rx_ring->cpu = cpu;
3392         }
3393         put_cpu();
3394 }
3395
3396 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3397 {
3398         u32 dca_txctrl;
3399         struct igb_adapter *adapter = tx_ring->adapter;
3400         struct e1000_hw *hw = &adapter->hw;
3401         int cpu = get_cpu();
3402         int q = tx_ring->reg_idx;
3403
3404         if (tx_ring->cpu != cpu) {
3405                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3406                 if (hw->mac.type == e1000_82576) {
3407                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3408                         dca_txctrl |= dca_get_tag(cpu) <<
3409                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3410                 } else {
3411                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3412                         dca_txctrl |= dca_get_tag(cpu);
3413                 }
3414                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3415                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3416                 tx_ring->cpu = cpu;
3417         }
3418         put_cpu();
3419 }
3420
3421 static void igb_setup_dca(struct igb_adapter *adapter)
3422 {
3423         int i;
3424
3425         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3426                 return;
3427
3428         for (i = 0; i < adapter->num_tx_queues; i++) {
3429                 adapter->tx_ring[i].cpu = -1;
3430                 igb_update_tx_dca(&adapter->tx_ring[i]);
3431         }
3432         for (i = 0; i < adapter->num_rx_queues; i++) {
3433                 adapter->rx_ring[i].cpu = -1;
3434                 igb_update_rx_dca(&adapter->rx_ring[i]);
3435         }
3436 }
3437
3438 static int __igb_notify_dca(struct device *dev, void *data)
3439 {
3440         struct net_device *netdev = dev_get_drvdata(dev);
3441         struct igb_adapter *adapter = netdev_priv(netdev);
3442         struct e1000_hw *hw = &adapter->hw;
3443         unsigned long event = *(unsigned long *)data;
3444
3445         switch (event) {
3446         case DCA_PROVIDER_ADD:
3447                 /* if already enabled, don't do it again */
3448                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3449                         break;
3450                 /* Always use CB2 mode, difference is masked
3451                  * in the CB driver. */
3452                 wr32(E1000_DCA_CTRL, 2);
3453                 if (dca_add_requester(dev) == 0) {
3454                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3455                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3456                         igb_setup_dca(adapter);
3457                         break;
3458                 }
3459                 /* Fall Through since DCA is disabled. */
3460         case DCA_PROVIDER_REMOVE:
3461                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3462                         /* without this a class_device is left
3463                          * hanging around in the sysfs model */
3464                         dca_remove_requester(dev);
3465                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3466                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3467                         wr32(E1000_DCA_CTRL, 1);
3468                 }
3469                 break;
3470         }
3471
3472         return 0;
3473 }
3474
3475 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3476                           void *p)
3477 {
3478         int ret_val;
3479
3480         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3481                                          __igb_notify_dca);
3482
3483         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3484 }
3485 #endif /* CONFIG_IGB_DCA */
3486
3487 /**
3488  * igb_intr_msi - Interrupt Handler
3489  * @irq: interrupt number
3490  * @data: pointer to a network interface device structure
3491  **/
3492 static irqreturn_t igb_intr_msi(int irq, void *data)
3493 {
3494         struct net_device *netdev = data;
3495         struct igb_adapter *adapter = netdev_priv(netdev);
3496         struct e1000_hw *hw = &adapter->hw;
3497         /* read ICR disables interrupts using IAM */
3498         u32 icr = rd32(E1000_ICR);
3499
3500         igb_write_itr(adapter->rx_ring);
3501
3502         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3503                 hw->mac.get_link_status = 1;
3504                 if (!test_bit(__IGB_DOWN, &adapter->state))
3505                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3506         }
3507
3508         napi_schedule(&adapter->rx_ring[0].napi);
3509
3510         return IRQ_HANDLED;
3511 }
3512
3513 /**
3514  * igb_intr - Interrupt Handler
3515  * @irq: interrupt number
3516  * @data: pointer to a network interface device structure
3517  **/
3518 static irqreturn_t igb_intr(int irq, void *data)
3519 {
3520         struct net_device *netdev = data;
3521         struct igb_adapter *adapter = netdev_priv(netdev);
3522         struct e1000_hw *hw = &adapter->hw;
3523         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
3524          * need for the IMC write */
3525         u32 icr = rd32(E1000_ICR);
3526         u32 eicr = 0;
3527         if (!icr)
3528                 return IRQ_NONE;  /* Not our interrupt */
3529
3530         igb_write_itr(adapter->rx_ring);
3531
3532         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3533          * not set, then the adapter didn't send an interrupt */
3534         if (!(icr & E1000_ICR_INT_ASSERTED))
3535                 return IRQ_NONE;
3536
3537         eicr = rd32(E1000_EICR);
3538
3539         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3540                 hw->mac.get_link_status = 1;
3541                 /* guard against interrupt when we're going down */
3542                 if (!test_bit(__IGB_DOWN, &adapter->state))
3543                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3544         }
3545
3546         napi_schedule(&adapter->rx_ring[0].napi);
3547
3548         return IRQ_HANDLED;
3549 }
3550
3551 /**
3552  * igb_poll - NAPI Rx polling callback
3553  * @napi: napi polling structure
3554  * @budget: count of how many packets we should handle
3555  **/
3556 static int igb_poll(struct napi_struct *napi, int budget)
3557 {
3558         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3559         struct igb_adapter *adapter = rx_ring->adapter;
3560         struct net_device *netdev = adapter->netdev;
3561         int tx_clean_complete, work_done = 0;
3562
3563         /* this poll routine only supports one tx and one rx queue */
3564 #ifdef CONFIG_IGB_DCA
3565         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3566                 igb_update_tx_dca(&adapter->tx_ring[0]);
3567 #endif
3568         tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3569
3570 #ifdef CONFIG_IGB_DCA
3571         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3572                 igb_update_rx_dca(&adapter->rx_ring[0]);
3573 #endif
3574         igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3575
3576         /* If no Tx and not enough Rx work done, exit the polling mode */
3577         if ((tx_clean_complete && (work_done < budget)) ||
3578             !netif_running(netdev)) {
3579                 if (adapter->itr_setting & 3)
3580                         igb_set_itr(adapter);
3581                 napi_complete(napi);
3582                 if (!test_bit(__IGB_DOWN, &adapter->state))
3583                         igb_irq_enable(adapter);
3584                 return 0;
3585         }
3586
3587         return 1;
3588 }
3589
3590 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3591 {
3592         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3593         struct igb_adapter *adapter = rx_ring->adapter;
3594         struct e1000_hw *hw = &adapter->hw;
3595         struct net_device *netdev = adapter->netdev;
3596         int work_done = 0;
3597
3598 #ifdef CONFIG_IGB_DCA
3599         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3600                 igb_update_rx_dca(rx_ring);
3601 #endif
3602         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3603
3604
3605         /* If not enough Rx work done, exit the polling mode */
3606         if ((work_done == 0) || !netif_running(netdev)) {
3607                 napi_complete(napi);
3608
3609                 if (adapter->itr_setting & 3) {
3610                         if (adapter->num_rx_queues == 1)
3611                                 igb_set_itr(adapter);
3612                         else
3613                                 igb_update_ring_itr(rx_ring);
3614                 }
3615
3616                 if (!test_bit(__IGB_DOWN, &adapter->state))
3617                         wr32(E1000_EIMS, rx_ring->eims_value);
3618
3619                 return 0;
3620         }
3621
3622         return 1;
3623 }
3624
3625 /**
3626  * igb_clean_tx_irq - Reclaim resources after transmit completes
3627  * @adapter: board private structure
3628  * returns true if ring is completely cleaned
3629  **/
3630 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3631 {
3632         struct igb_adapter *adapter = tx_ring->adapter;
3633         struct net_device *netdev = adapter->netdev;
3634         struct e1000_hw *hw = &adapter->hw;
3635         struct igb_buffer *buffer_info;
3636         struct sk_buff *skb;
3637         union e1000_adv_tx_desc *tx_desc, *eop_desc;
3638         unsigned int total_bytes = 0, total_packets = 0;
3639         unsigned int i, eop, count = 0;
3640         bool cleaned = false;
3641
3642         i = tx_ring->next_to_clean;
3643         eop = tx_ring->buffer_info[i].next_to_watch;
3644         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3645
3646         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3647                (count < tx_ring->count)) {
3648                 for (cleaned = false; !cleaned; count++) {
3649                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3650                         buffer_info = &tx_ring->buffer_info[i];
3651                         cleaned = (i == eop);
3652                         skb = buffer_info->skb;
3653
3654                         if (skb) {
3655                                 unsigned int segs, bytecount;
3656                                 /* gso_segs is currently only valid for tcp */
3657                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
3658                                 /* multiply data chunks by size of headers */
3659                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
3660                                             skb->len;
3661                                 total_packets += segs;
3662                                 total_bytes += bytecount;
3663                         }
3664
3665                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
3666                         tx_desc->wb.status = 0;
3667
3668                         i++;
3669                         if (i == tx_ring->count)
3670                                 i = 0;
3671                 }
3672
3673                 eop = tx_ring->buffer_info[i].next_to_watch;
3674                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3675         }
3676
3677         tx_ring->next_to_clean = i;
3678
3679         if (unlikely(count &&
3680                      netif_carrier_ok(netdev) &&
3681                      IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3682                 /* Make sure that anybody stopping the queue after this
3683                  * sees the new next_to_clean.
3684                  */
3685                 smp_mb();
3686                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3687                     !(test_bit(__IGB_DOWN, &adapter->state))) {
3688                         netif_wake_subqueue(netdev, tx_ring->queue_index);
3689                         ++adapter->restart_queue;
3690                 }
3691         }
3692
3693         if (tx_ring->detect_tx_hung) {
3694                 /* Detect a transmit hang in hardware, this serializes the
3695                  * check with the clearing of time_stamp and movement of i */
3696                 tx_ring->detect_tx_hung = false;
3697                 if (tx_ring->buffer_info[i].time_stamp &&
3698                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3699                                (adapter->tx_timeout_factor * HZ))
3700                     && !(rd32(E1000_STATUS) &
3701                          E1000_STATUS_TXOFF)) {
3702
3703                         /* detected Tx unit hang */
3704                         dev_err(&adapter->pdev->dev,
3705                                 "Detected Tx Unit Hang\n"
3706                                 "  Tx Queue             <%d>\n"
3707                                 "  TDH                  <%x>\n"
3708                                 "  TDT                  <%x>\n"
3709                                 "  next_to_use          <%x>\n"
3710                                 "  next_to_clean        <%x>\n"
3711                                 "buffer_info[next_to_clean]\n"
3712                                 "  time_stamp           <%lx>\n"
3713                                 "  next_to_watch        <%x>\n"
3714                                 "  jiffies              <%lx>\n"
3715                                 "  desc.status          <%x>\n",
3716                                 tx_ring->queue_index,
3717                                 readl(adapter->hw.hw_addr + tx_ring->head),
3718                                 readl(adapter->hw.hw_addr + tx_ring->tail),
3719                                 tx_ring->next_to_use,
3720                                 tx_ring->next_to_clean,
3721                                 tx_ring->buffer_info[i].time_stamp,
3722                                 eop,
3723                                 jiffies,
3724                                 eop_desc->wb.status);
3725                         netif_stop_subqueue(netdev, tx_ring->queue_index);
3726                 }
3727         }
3728         tx_ring->total_bytes += total_bytes;
3729         tx_ring->total_packets += total_packets;
3730         tx_ring->tx_stats.bytes += total_bytes;
3731         tx_ring->tx_stats.packets += total_packets;
3732         adapter->net_stats.tx_bytes += total_bytes;
3733         adapter->net_stats.tx_packets += total_packets;
3734         return (count < tx_ring->count);
3735 }
3736
3737 /**
3738  * igb_receive_skb - helper function to handle rx indications
3739  * @ring: pointer to receive ring receving this packet
3740  * @status: descriptor status field as written by hardware
3741  * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3742  * @skb: pointer to sk_buff to be indicated to stack
3743  **/
3744 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3745                             union e1000_adv_rx_desc * rx_desc,
3746                             struct sk_buff *skb)
3747 {
3748         struct igb_adapter * adapter = ring->adapter;
3749         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3750
3751         skb_record_rx_queue(skb, ring->queue_index);
3752         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
3753                 if (vlan_extracted)
3754                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
3755                                          le16_to_cpu(rx_desc->wb.upper.vlan),
3756                                          skb);
3757                 else
3758                         napi_gro_receive(&ring->napi, skb);
3759         } else {
3760                 if (vlan_extracted)
3761                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3762                                           le16_to_cpu(rx_desc->wb.upper.vlan));
3763                 else
3764                         netif_receive_skb(skb);
3765         }
3766 }
3767
3768
3769 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3770                                        u32 status_err, struct sk_buff *skb)
3771 {
3772         skb->ip_summed = CHECKSUM_NONE;
3773
3774         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3775         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3776                 return;
3777         /* TCP/UDP checksum error bit is set */
3778         if (status_err &
3779             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3780                 /* let the stack verify checksum errors */
3781                 adapter->hw_csum_err++;
3782                 return;
3783         }
3784         /* It must be a TCP or UDP packet with a valid checksum */
3785         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3786                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3787
3788         adapter->hw_csum_good++;
3789 }
3790
3791 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3792                                  int *work_done, int budget)
3793 {
3794         struct igb_adapter *adapter = rx_ring->adapter;
3795         struct net_device *netdev = adapter->netdev;
3796         struct pci_dev *pdev = adapter->pdev;
3797         union e1000_adv_rx_desc *rx_desc , *next_rxd;
3798         struct igb_buffer *buffer_info , *next_buffer;
3799         struct sk_buff *skb;
3800         unsigned int i;
3801         u32 length, hlen, staterr;
3802         bool cleaned = false;
3803         int cleaned_count = 0;
3804         unsigned int total_bytes = 0, total_packets = 0;
3805
3806         i = rx_ring->next_to_clean;
3807         buffer_info = &rx_ring->buffer_info[i];
3808         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3809         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3810
3811         while (staterr & E1000_RXD_STAT_DD) {
3812                 if (*work_done >= budget)
3813                         break;
3814                 (*work_done)++;
3815
3816                 skb = buffer_info->skb;
3817                 prefetch(skb->data - NET_IP_ALIGN);
3818                 buffer_info->skb = NULL;
3819
3820                 i++;
3821                 if (i == rx_ring->count)
3822                         i = 0;
3823                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3824                 prefetch(next_rxd);
3825                 next_buffer = &rx_ring->buffer_info[i];
3826
3827                 length = le16_to_cpu(rx_desc->wb.upper.length);
3828                 cleaned = true;
3829                 cleaned_count++;
3830
3831                 if (!adapter->rx_ps_hdr_size) {
3832                         pci_unmap_single(pdev, buffer_info->dma,
3833                                          adapter->rx_buffer_len +
3834                                            NET_IP_ALIGN,
3835                                          PCI_DMA_FROMDEVICE);
3836                         skb_put(skb, length);
3837                         goto send_up;
3838                 }
3839
3840                 /* HW will not DMA in data larger than the given buffer, even
3841                  * if it parses the (NFS, of course) header to be larger.  In
3842                  * that case, it fills the header buffer and spills the rest
3843                  * into the page.
3844                  */
3845                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3846                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3847                 if (hlen > adapter->rx_ps_hdr_size)
3848                         hlen = adapter->rx_ps_hdr_size;
3849
3850                 if (!skb_shinfo(skb)->nr_frags) {
3851                         pci_unmap_single(pdev, buffer_info->dma,
3852                                          adapter->rx_ps_hdr_size +
3853                                            NET_IP_ALIGN,
3854                                          PCI_DMA_FROMDEVICE);
3855                         skb_put(skb, hlen);
3856                 }
3857
3858                 if (length) {
3859                         pci_unmap_page(pdev, buffer_info->page_dma,
3860                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3861                         buffer_info->page_dma = 0;
3862
3863                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3864                                                 buffer_info->page,
3865                                                 buffer_info->page_offset,
3866                                                 length);
3867
3868                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3869                             (page_count(buffer_info->page) != 1))
3870                                 buffer_info->page = NULL;
3871                         else
3872                                 get_page(buffer_info->page);
3873
3874                         skb->len += length;
3875                         skb->data_len += length;
3876
3877                         skb->truesize += length;
3878                 }
3879
3880                 if (!(staterr & E1000_RXD_STAT_EOP)) {
3881                         buffer_info->skb = next_buffer->skb;
3882                         buffer_info->dma = next_buffer->dma;
3883                         next_buffer->skb = skb;
3884                         next_buffer->dma = 0;
3885                         goto next_desc;
3886                 }
3887 send_up:
3888                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3889                         dev_kfree_skb_irq(skb);
3890                         goto next_desc;
3891                 }
3892
3893                 total_bytes += skb->len;
3894                 total_packets++;
3895
3896                 igb_rx_checksum_adv(adapter, staterr, skb);
3897
3898                 skb->protocol = eth_type_trans(skb, netdev);
3899
3900                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3901
3902 next_desc:
3903                 rx_desc->wb.upper.status_error = 0;
3904
3905                 /* return some buffers to hardware, one at a time is too slow */
3906                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3907                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3908                         cleaned_count = 0;
3909                 }
3910
3911                 /* use prefetched values */
3912                 rx_desc = next_rxd;
3913                 buffer_info = next_buffer;
3914                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3915         }
3916
3917         rx_ring->next_to_clean = i;
3918         cleaned_count = IGB_DESC_UNUSED(rx_ring);
3919
3920         if (cleaned_count)
3921                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3922
3923         rx_ring->total_packets += total_packets;
3924         rx_ring->total_bytes += total_bytes;
3925         rx_ring->rx_stats.packets += total_packets;
3926         rx_ring->rx_stats.bytes += total_bytes;
3927         adapter->net_stats.rx_bytes += total_bytes;
3928         adapter->net_stats.rx_packets += total_packets;
3929         return cleaned;
3930 }
3931
3932
3933 /**
3934  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3935  * @adapter: address of board private structure
3936  **/
3937 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3938                                      int cleaned_count)
3939 {
3940         struct igb_adapter *adapter = rx_ring->adapter;
3941         struct net_device *netdev = adapter->netdev;
3942         struct pci_dev *pdev = adapter->pdev;
3943         union e1000_adv_rx_desc *rx_desc;
3944         struct igb_buffer *buffer_info;
3945         struct sk_buff *skb;
3946         unsigned int i;
3947         int bufsz;
3948
3949         i = rx_ring->next_to_use;
3950         buffer_info = &rx_ring->buffer_info[i];
3951
3952         if (adapter->rx_ps_hdr_size)
3953                 bufsz = adapter->rx_ps_hdr_size;
3954         else
3955                 bufsz = adapter->rx_buffer_len;
3956         bufsz += NET_IP_ALIGN;
3957
3958         while (cleaned_count--) {
3959                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3960
3961                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
3962                         if (!buffer_info->page) {
3963                                 buffer_info->page = alloc_page(GFP_ATOMIC);
3964                                 if (!buffer_info->page) {
3965                                         adapter->alloc_rx_buff_failed++;
3966                                         goto no_buffers;
3967                                 }
3968                                 buffer_info->page_offset = 0;
3969                         } else {
3970                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
3971                         }
3972                         buffer_info->page_dma =
3973                                 pci_map_page(pdev, buffer_info->page,
3974                                              buffer_info->page_offset,
3975                                              PAGE_SIZE / 2,
3976                                              PCI_DMA_FROMDEVICE);
3977                 }
3978
3979                 if (!buffer_info->skb) {
3980                         skb = netdev_alloc_skb(netdev, bufsz);
3981                         if (!skb) {
3982                                 adapter->alloc_rx_buff_failed++;
3983                                 goto no_buffers;
3984                         }
3985
3986                         /* Make buffer alignment 2 beyond a 16 byte boundary
3987                          * this will result in a 16 byte aligned IP header after
3988                          * the 14 byte MAC header is removed
3989                          */
3990                         skb_reserve(skb, NET_IP_ALIGN);
3991
3992                         buffer_info->skb = skb;
3993                         buffer_info->dma = pci_map_single(pdev, skb->data,
3994                                                           bufsz,
3995                                                           PCI_DMA_FROMDEVICE);
3996                 }
3997                 /* Refresh the desc even if buffer_addrs didn't change because
3998                  * each write-back erases this info. */
3999                 if (adapter->rx_ps_hdr_size) {
4000                         rx_desc->read.pkt_addr =
4001                              cpu_to_le64(buffer_info->page_dma);
4002                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4003                 } else {
4004                         rx_desc->read.pkt_addr =
4005                              cpu_to_le64(buffer_info->dma);
4006                         rx_desc->read.hdr_addr = 0;
4007                 }
4008
4009                 i++;
4010                 if (i == rx_ring->count)
4011                         i = 0;
4012                 buffer_info = &rx_ring->buffer_info[i];
4013         }
4014
4015 no_buffers:
4016         if (rx_ring->next_to_use != i) {
4017                 rx_ring->next_to_use = i;
4018                 if (i == 0)
4019                         i = (rx_ring->count - 1);
4020                 else
4021                         i--;
4022
4023                 /* Force memory writes to complete before letting h/w
4024                  * know there are new descriptors to fetch.  (Only
4025                  * applicable for weak-ordered memory model archs,
4026                  * such as IA-64). */
4027                 wmb();
4028                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4029         }
4030 }
4031
4032 /**
4033  * igb_mii_ioctl -
4034  * @netdev:
4035  * @ifreq:
4036  * @cmd:
4037  **/
4038 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4039 {
4040         struct igb_adapter *adapter = netdev_priv(netdev);
4041         struct mii_ioctl_data *data = if_mii(ifr);
4042
4043         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4044                 return -EOPNOTSUPP;
4045
4046         switch (cmd) {
4047         case SIOCGMIIPHY:
4048                 data->phy_id = adapter->hw.phy.addr;
4049                 break;
4050         case SIOCGMIIREG:
4051                 if (!capable(CAP_NET_ADMIN))
4052                         return -EPERM;
4053                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4054                                      &data->val_out))
4055                         return -EIO;
4056                 break;
4057         case SIOCSMIIREG:
4058         default:
4059                 return -EOPNOTSUPP;
4060         }
4061         return 0;
4062 }
4063
4064 /**
4065  * igb_ioctl -
4066  * @netdev:
4067  * @ifreq:
4068  * @cmd:
4069  **/
4070 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4071 {
4072         switch (cmd) {
4073         case SIOCGMIIPHY:
4074         case SIOCGMIIREG:
4075         case SIOCSMIIREG:
4076                 return igb_mii_ioctl(netdev, ifr, cmd);
4077         default:
4078                 return -EOPNOTSUPP;
4079         }
4080 }
4081
4082 static void igb_vlan_rx_register(struct net_device *netdev,
4083                                  struct vlan_group *grp)
4084 {
4085         struct igb_adapter *adapter = netdev_priv(netdev);
4086         struct e1000_hw *hw = &adapter->hw;
4087         u32 ctrl, rctl;
4088
4089         igb_irq_disable(adapter);
4090         adapter->vlgrp = grp;
4091
4092         if (grp) {
4093                 /* enable VLAN tag insert/strip */
4094                 ctrl = rd32(E1000_CTRL);
4095                 ctrl |= E1000_CTRL_VME;
4096                 wr32(E1000_CTRL, ctrl);
4097
4098                 /* enable VLAN receive filtering */
4099                 rctl = rd32(E1000_RCTL);
4100                 rctl &= ~E1000_RCTL_CFIEN;
4101                 wr32(E1000_RCTL, rctl);
4102                 igb_update_mng_vlan(adapter);
4103                 wr32(E1000_RLPML,
4104                                 adapter->max_frame_size + VLAN_TAG_SIZE);
4105         } else {
4106                 /* disable VLAN tag insert/strip */
4107                 ctrl = rd32(E1000_CTRL);
4108                 ctrl &= ~E1000_CTRL_VME;
4109                 wr32(E1000_CTRL, ctrl);
4110
4111                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4112                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4113                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4114                 }
4115                 wr32(E1000_RLPML,
4116                                 adapter->max_frame_size);
4117         }
4118
4119         if (!test_bit(__IGB_DOWN, &adapter->state))
4120                 igb_irq_enable(adapter);
4121 }
4122
4123 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4124 {
4125         struct igb_adapter *adapter = netdev_priv(netdev);
4126         struct e1000_hw *hw = &adapter->hw;
4127         u32 vfta, index;
4128
4129         if ((adapter->hw.mng_cookie.status &
4130              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4131             (vid == adapter->mng_vlan_id))
4132                 return;
4133         /* add VID to filter table */
4134         index = (vid >> 5) & 0x7F;
4135         vfta = array_rd32(E1000_VFTA, index);
4136         vfta |= (1 << (vid & 0x1F));
4137         igb_write_vfta(&adapter->hw, index, vfta);
4138 }
4139
4140 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4141 {
4142         struct igb_adapter *adapter = netdev_priv(netdev);
4143         struct e1000_hw *hw = &adapter->hw;
4144         u32 vfta, index;
4145
4146         igb_irq_disable(adapter);
4147         vlan_group_set_device(adapter->vlgrp, vid, NULL);
4148
4149         if (!test_bit(__IGB_DOWN, &adapter->state))
4150                 igb_irq_enable(adapter);
4151
4152         if ((adapter->hw.mng_cookie.status &
4153              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4154             (vid == adapter->mng_vlan_id)) {
4155                 /* release control to f/w */
4156                 igb_release_hw_control(adapter);
4157                 return;
4158         }
4159
4160         /* remove VID from filter table */
4161         index = (vid >> 5) & 0x7F;
4162         vfta = array_rd32(E1000_VFTA, index);
4163         vfta &= ~(1 << (vid & 0x1F));
4164         igb_write_vfta(&adapter->hw, index, vfta);
4165 }
4166
4167 static void igb_restore_vlan(struct igb_adapter *adapter)
4168 {
4169         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4170
4171         if (adapter->vlgrp) {
4172                 u16 vid;
4173                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4174                         if (!vlan_group_get_device(adapter->vlgrp, vid))
4175                                 continue;
4176                         igb_vlan_rx_add_vid(adapter->netdev, vid);
4177                 }
4178         }
4179 }
4180
4181 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4182 {
4183         struct e1000_mac_info *mac = &adapter->hw.mac;
4184
4185         mac->autoneg = 0;
4186
4187         /* Fiber NICs only allow 1000 gbps Full duplex */
4188         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4189                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4190                 dev_err(&adapter->pdev->dev,
4191                         "Unsupported Speed/Duplex configuration\n");
4192                 return -EINVAL;
4193         }
4194
4195         switch (spddplx) {
4196         case SPEED_10 + DUPLEX_HALF:
4197                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4198                 break;
4199         case SPEED_10 + DUPLEX_FULL:
4200                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4201                 break;
4202         case SPEED_100 + DUPLEX_HALF:
4203                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4204                 break;
4205         case SPEED_100 + DUPLEX_FULL:
4206                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4207                 break;
4208         case SPEED_1000 + DUPLEX_FULL:
4209                 mac->autoneg = 1;
4210                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4211                 break;
4212         case SPEED_1000 + DUPLEX_HALF: /* not supported */
4213         default:
4214                 dev_err(&adapter->pdev->dev,
4215                         "Unsupported Speed/Duplex configuration\n");
4216                 return -EINVAL;
4217         }
4218         return 0;
4219 }
4220
4221
4222 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4223 {
4224         struct net_device *netdev = pci_get_drvdata(pdev);
4225         struct igb_adapter *adapter = netdev_priv(netdev);
4226         struct e1000_hw *hw = &adapter->hw;
4227         u32 ctrl, rctl, status;
4228         u32 wufc = adapter->wol;
4229 #ifdef CONFIG_PM
4230         int retval = 0;
4231 #endif
4232
4233         netif_device_detach(netdev);
4234
4235         if (netif_running(netdev))
4236                 igb_close(netdev);
4237
4238         igb_reset_interrupt_capability(adapter);
4239
4240         igb_free_queues(adapter);
4241
4242 #ifdef CONFIG_PM
4243         retval = pci_save_state(pdev);
4244         if (retval)
4245                 return retval;
4246 #endif
4247
4248         status = rd32(E1000_STATUS);
4249         if (status & E1000_STATUS_LU)
4250                 wufc &= ~E1000_WUFC_LNKC;
4251
4252         if (wufc) {
4253                 igb_setup_rctl(adapter);
4254                 igb_set_multi(netdev);
4255
4256                 /* turn on all-multi mode if wake on multicast is enabled */
4257                 if (wufc & E1000_WUFC_MC) {
4258                         rctl = rd32(E1000_RCTL);
4259                         rctl |= E1000_RCTL_MPE;
4260                         wr32(E1000_RCTL, rctl);
4261                 }
4262
4263                 ctrl = rd32(E1000_CTRL);
4264                 /* advertise wake from D3Cold */
4265                 #define E1000_CTRL_ADVD3WUC 0x00100000
4266                 /* phy power management enable */
4267                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4268                 ctrl |= E1000_CTRL_ADVD3WUC;
4269                 wr32(E1000_CTRL, ctrl);
4270
4271                 /* Allow time for pending master requests to run */
4272                 igb_disable_pcie_master(&adapter->hw);
4273
4274                 wr32(E1000_WUC, E1000_WUC_PME_EN);
4275                 wr32(E1000_WUFC, wufc);
4276         } else {
4277                 wr32(E1000_WUC, 0);
4278                 wr32(E1000_WUFC, 0);
4279         }
4280
4281         /* make sure adapter isn't asleep if manageability/wol is enabled */
4282         if (wufc || adapter->en_mng_pt) {
4283                 pci_enable_wake(pdev, PCI_D3hot, 1);
4284                 pci_enable_wake(pdev, PCI_D3cold, 1);
4285         } else {
4286                 igb_shutdown_fiber_serdes_link_82575(hw);
4287                 pci_enable_wake(pdev, PCI_D3hot, 0);
4288                 pci_enable_wake(pdev, PCI_D3cold, 0);
4289         }
4290
4291         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
4292          * would have already happened in close and is redundant. */
4293         igb_release_hw_control(adapter);
4294
4295         pci_disable_device(pdev);
4296
4297         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4298
4299         return 0;
4300 }
4301
4302 #ifdef CONFIG_PM
4303 static int igb_resume(struct pci_dev *pdev)
4304 {
4305         struct net_device *netdev = pci_get_drvdata(pdev);
4306         struct igb_adapter *adapter = netdev_priv(netdev);
4307         struct e1000_hw *hw = &adapter->hw;
4308         u32 err;
4309
4310         pci_set_power_state(pdev, PCI_D0);
4311         pci_restore_state(pdev);
4312
4313         err = pci_enable_device_mem(pdev);
4314         if (err) {
4315                 dev_err(&pdev->dev,
4316                         "igb: Cannot enable PCI device from suspend\n");
4317                 return err;
4318         }
4319         pci_set_master(pdev);
4320
4321         pci_enable_wake(pdev, PCI_D3hot, 0);
4322         pci_enable_wake(pdev, PCI_D3cold, 0);
4323
4324         igb_set_interrupt_capability(adapter);
4325
4326         if (igb_alloc_queues(adapter)) {
4327                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4328                 return -ENOMEM;
4329         }
4330
4331         /* e1000_power_up_phy(adapter); */
4332
4333         igb_reset(adapter);
4334         wr32(E1000_WUS, ~0);
4335
4336         if (netif_running(netdev)) {
4337                 err = igb_open(netdev);
4338                 if (err)
4339                         return err;
4340         }
4341
4342         netif_device_attach(netdev);
4343
4344         /* let the f/w know that the h/w is now under the control of the
4345          * driver. */
4346         igb_get_hw_control(adapter);
4347
4348         return 0;
4349 }
4350 #endif
4351
4352 static void igb_shutdown(struct pci_dev *pdev)
4353 {
4354         igb_suspend(pdev, PMSG_SUSPEND);
4355 }
4356
4357 #ifdef CONFIG_NET_POLL_CONTROLLER
4358 /*
4359  * Polling 'interrupt' - used by things like netconsole to send skbs
4360  * without having to re-enable interrupts. It's not called while
4361  * the interrupt routine is executing.
4362  */
4363 static void igb_netpoll(struct net_device *netdev)
4364 {
4365         struct igb_adapter *adapter = netdev_priv(netdev);
4366         int i;
4367         int work_done = 0;
4368
4369         igb_irq_disable(adapter);
4370         adapter->flags |= IGB_FLAG_IN_NETPOLL;
4371
4372         for (i = 0; i < adapter->num_tx_queues; i++)
4373                 igb_clean_tx_irq(&adapter->tx_ring[i]);
4374
4375         for (i = 0; i < adapter->num_rx_queues; i++)
4376                 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
4377                                      &work_done,
4378                                      adapter->rx_ring[i].napi.weight);
4379
4380         adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
4381         igb_irq_enable(adapter);
4382 }
4383 #endif /* CONFIG_NET_POLL_CONTROLLER */
4384
4385 /**
4386  * igb_io_error_detected - called when PCI error is detected
4387  * @pdev: Pointer to PCI device
4388  * @state: The current pci connection state
4389  *
4390  * This function is called after a PCI bus error affecting
4391  * this device has been detected.
4392  */
4393 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4394                                               pci_channel_state_t state)
4395 {
4396         struct net_device *netdev = pci_get_drvdata(pdev);
4397         struct igb_adapter *adapter = netdev_priv(netdev);
4398
4399         netif_device_detach(netdev);
4400
4401         if (netif_running(netdev))
4402                 igb_down(adapter);
4403         pci_disable_device(pdev);
4404
4405         /* Request a slot slot reset. */
4406         return PCI_ERS_RESULT_NEED_RESET;
4407 }
4408
4409 /**
4410  * igb_io_slot_reset - called after the pci bus has been reset.
4411  * @pdev: Pointer to PCI device
4412  *
4413  * Restart the card from scratch, as if from a cold-boot. Implementation
4414  * resembles the first-half of the igb_resume routine.
4415  */
4416 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4417 {
4418         struct net_device *netdev = pci_get_drvdata(pdev);
4419         struct igb_adapter *adapter = netdev_priv(netdev);
4420         struct e1000_hw *hw = &adapter->hw;
4421         pci_ers_result_t result;
4422         int err;
4423
4424         if (pci_enable_device_mem(pdev)) {
4425                 dev_err(&pdev->dev,
4426                         "Cannot re-enable PCI device after reset.\n");
4427                 result = PCI_ERS_RESULT_DISCONNECT;
4428         } else {
4429                 pci_set_master(pdev);
4430                 pci_restore_state(pdev);
4431
4432                 pci_enable_wake(pdev, PCI_D3hot, 0);
4433                 pci_enable_wake(pdev, PCI_D3cold, 0);
4434
4435                 igb_reset(adapter);
4436                 wr32(E1000_WUS, ~0);
4437                 result = PCI_ERS_RESULT_RECOVERED;
4438         }
4439
4440         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4441         if (err) {
4442                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4443                         "failed 0x%0x\n", err);
4444                 /* non-fatal, continue */
4445         }
4446
4447         return result;
4448 }
4449
4450 /**
4451  * igb_io_resume - called when traffic can start flowing again.
4452  * @pdev: Pointer to PCI device
4453  *
4454  * This callback is called when the error recovery driver tells us that
4455  * its OK to resume normal operation. Implementation resembles the
4456  * second-half of the igb_resume routine.
4457  */
4458 static void igb_io_resume(struct pci_dev *pdev)
4459 {
4460         struct net_device *netdev = pci_get_drvdata(pdev);
4461         struct igb_adapter *adapter = netdev_priv(netdev);
4462
4463         if (netif_running(netdev)) {
4464                 if (igb_up(adapter)) {
4465                         dev_err(&pdev->dev, "igb_up failed after reset\n");
4466                         return;
4467                 }
4468         }
4469
4470         netif_device_attach(netdev);
4471
4472         /* let the f/w know that the h/w is now under the control of the
4473          * driver. */
4474         igb_get_hw_control(adapter);
4475 }
4476
4477 /* igb_main.c */