drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 #ifdef CONFIG_PM
 139 static int igb_suspend(struct pci_dev *, pm_message_t);
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155 #ifdef CONFIG_PCI_IOV
 156 static unsigned int max_vfs = 0;
 157 module_param(max_vfs, uint, 0);
 158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 159                  "per physical function");
 160 #endif /* CONFIG_PCI_IOV */
 161
 162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 163                      pci_channel_state_t);
 164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 165 static void igb_io_resume(struct pci_dev *);
 166
 167 static struct pci_error_handlers igb_err_handler = {
 168         .error_detected = igb_io_error_detected,
 169         .slot_reset = igb_io_slot_reset,
 170         .resume = igb_io_resume,
 171 };
 172
 173
 174 static struct pci_driver igb_driver = {
 175         .name     = igb_driver_name,
 176         .id_table = igb_pci_tbl,
 177         .probe    = igb_probe,
 178         .remove   = __devexit_p(igb_remove),
 179 #ifdef CONFIG_PM
 180         /* Power Managment Hooks */
 181         .suspend  = igb_suspend,
 182         .resume   = igb_resume,
 183 #endif
 184         .shutdown = igb_shutdown,
 185         .err_handler = &igb_err_handler
 186 };
 187
 188 static int global_quad_port_a; /* global quad port a indication */
 189
 190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 192 MODULE_LICENSE("GPL");
 193 MODULE_VERSION(DRV_VERSION);
 194
 195 /**
 196  * Scale the NIC clock cycle by a large factor so that
 197  * relatively small clock corrections can be added or
 198  * substracted at each clock tick. The drawbacks of a
 199  * large factor are a) that the clock register overflows
 200  * more quickly (not such a big deal) and b) that the
 201  * increment per tick has to fit into 24 bits.
 202  *
 203  * Note that
 204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 205  *             IGB_TSYNC_SCALE
 206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 207  *
 208  * The base scale factor is intentionally a power of two
 209  * so that the division in %struct timecounter can be done with
 210  * a shift.
 211  */
 212 #define IGB_TSYNC_SHIFT (19)
 213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 214
 215 /**
 216  * The duration of one clock cycle of the NIC.
 217  *
 218  * @todo This hard-coded value is part of the specification and might change
 219  * in future hardware revisions. Add revision check.
 220  */
 221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 222
 223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 225 #endif
 226
 227 /**
 228  * igb_read_clock - read raw cycle counter (to be used by time counter)
 229  */
 230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 231 {
 232         struct igb_adapter *adapter =
 233                 container_of(tc, struct igb_adapter, cycles);
 234         struct e1000_hw *hw = &adapter->hw;
 235         u64 stamp;
 236
 237         stamp =  rd32(E1000_SYSTIML);
 238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 239
 240         return stamp;
 241 }
 242
 243 #ifdef DEBUG
 244 /**
 245  * igb_get_hw_dev_name - return device name string
 246  * used by hardware layer to print debugging information
 247  **/
 248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 249 {
 250         struct igb_adapter *adapter = hw->back;
 251         return adapter->netdev->name;
 252 }
 253
 254 /**
 255  * igb_get_time_str - format current NIC and system time as string
 256  */
 257 static char *igb_get_time_str(struct igb_adapter *adapter,
 258                               char buffer[160])
 259 {
 260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 262         struct timespec sys;
 263         struct timespec delta;
 264         getnstimeofday(&sys);
 265
 266         delta = timespec_sub(nic, sys);
 267
 268         sprintf(buffer,
 269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 270                 hw,
 271                 (long)nic.tv_sec, nic.tv_nsec,
 272                 (long)sys.tv_sec, sys.tv_nsec,
 273                 (long)delta.tv_sec, delta.tv_nsec);
 274
 275         return buffer;
 276 }
 277 #endif
 278
 279 /**
 280  * igb_desc_unused - calculate if we have unused descriptors
 281  **/
 282 static int igb_desc_unused(struct igb_ring *ring)
 283 {
 284         if (ring->next_to_clean > ring->next_to_use)
 285                 return ring->next_to_clean - ring->next_to_use - 1;
 286
 287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 288 }
 289
 290 /**
 291  * igb_init_module - Driver Registration Routine
 292  *
 293  * igb_init_module is the first routine called when the driver is
 294  * loaded. All it does is register with the PCI subsystem.
 295  **/
 296 static int __init igb_init_module(void)
 297 {
 298         int ret;
 299         printk(KERN_INFO "%s - version %s\n",
 300                igb_driver_string, igb_driver_version);
 301
 302         printk(KERN_INFO "%s\n", igb_copyright);
 303
 304         global_quad_port_a = 0;
 305
 306 #ifdef CONFIG_IGB_DCA
 307         dca_register_notify(&dca_notifier);
 308 #endif
 309
 310         ret = pci_register_driver(&igb_driver);
 311         return ret;
 312 }
 313
 314 module_init(igb_init_module);
 315
 316 /**
 317  * igb_exit_module - Driver Exit Cleanup Routine
 318  *
 319  * igb_exit_module is called just before the driver is removed
 320  * from memory.
 321  **/
 322 static void __exit igb_exit_module(void)
 323 {
 324 #ifdef CONFIG_IGB_DCA
 325         dca_unregister_notify(&dca_notifier);
 326 #endif
 327         pci_unregister_driver(&igb_driver);
 328 }
 329
 330 module_exit(igb_exit_module);
 331
 332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 333 /**
 334  * igb_cache_ring_register - Descriptor ring to register mapping
 335  * @adapter: board private structure to initialize
 336  *
 337  * Once we know the feature-set enabled for the device, we'll cache
 338  * the register offset the descriptor ring is assigned to.
 339  **/
 340 static void igb_cache_ring_register(struct igb_adapter *adapter)
 341 {
 342         int i;
 343         unsigned int rbase_offset = adapter->vfs_allocated_count;
 344
 345         switch (adapter->hw.mac.type) {
 346         case e1000_82576:
 347                 /* The queues are allocated for virtualization such that VF 0
 348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 349                  * In order to avoid collision we start at the first free queue
 350                  * and continue consuming queues in the same sequence
 351                  */
 352                 for (i = 0; i < adapter->num_rx_queues; i++)
 353                         adapter->rx_ring[i].reg_idx = rbase_offset +
 354                                                       Q_IDX_82576(i);
 355                 for (i = 0; i < adapter->num_tx_queues; i++)
 356                         adapter->tx_ring[i].reg_idx = rbase_offset +
 357                                                       Q_IDX_82576(i);
 358                 break;
 359         case e1000_82575:
 360         default:
 361                 for (i = 0; i < adapter->num_rx_queues; i++)
 362                         adapter->rx_ring[i].reg_idx = i;
 363                 for (i = 0; i < adapter->num_tx_queues; i++)
 364                         adapter->tx_ring[i].reg_idx = i;
 365                 break;
 366         }
 367 }
 368
 369 /**
 370  * igb_alloc_queues - Allocate memory for all rings
 371  * @adapter: board private structure to initialize
 372  *
 373  * We allocate one ring per queue at run-time since we don't know the
 374  * number of queues at compile-time.
 375  **/
 376 static int igb_alloc_queues(struct igb_adapter *adapter)
 377 {
 378         int i;
 379
 380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 381                                    sizeof(struct igb_ring), GFP_KERNEL);
 382         if (!adapter->tx_ring)
 383                 return -ENOMEM;
 384
 385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 386                                    sizeof(struct igb_ring), GFP_KERNEL);
 387         if (!adapter->rx_ring) {
 388                 kfree(adapter->tx_ring);
 389                 return -ENOMEM;
 390         }
 391
 392         adapter->rx_ring->buddy = adapter->tx_ring;
 393
 394         for (i = 0; i < adapter->num_tx_queues; i++) {
 395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 396                 ring->count = adapter->tx_ring_count;
 397                 ring->adapter = adapter;
 398                 ring->queue_index = i;
 399         }
 400         for (i = 0; i < adapter->num_rx_queues; i++) {
 401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 402                 ring->count = adapter->rx_ring_count;
 403                 ring->adapter = adapter;
 404                 ring->queue_index = i;
 405                 ring->itr_register = E1000_ITR;
 406
 407                 /* set a default napi handler for each rx_ring */
 408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 409         }
 410
 411         igb_cache_ring_register(adapter);
 412         return 0;
 413 }
 414
 415 static void igb_free_queues(struct igb_adapter *adapter)
 416 {
 417         int i;
 418
 419         for (i = 0; i < adapter->num_rx_queues; i++)
 420                 netif_napi_del(&adapter->rx_ring[i].napi);
 421
 422         adapter->num_rx_queues = 0;
 423         adapter->num_tx_queues = 0;
 424
 425         kfree(adapter->tx_ring);
 426         kfree(adapter->rx_ring);
 427 }
 428
 429 #define IGB_N0_QUEUE -1
 430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 431                               int tx_queue, int msix_vector)
 432 {
 433         u32 msixbm = 0;
 434         struct e1000_hw *hw = &adapter->hw;
 435         u32 ivar, index;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 /* The 82575 assigns vectors using a bitmask, which matches the
 440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 441                    or more queues to a vector, we write the appropriate bits
 442                    into the MSIXBM register for that vector. */
 443                 if (rx_queue > IGB_N0_QUEUE) {
 444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 446                 }
 447                 if (tx_queue > IGB_N0_QUEUE) {
 448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 449                         adapter->tx_ring[tx_queue].eims_value =
 450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 451                 }
 452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 453                 break;
 454         case e1000_82576:
 455                 /* 82576 uses a table-based method for assigning vectors.
 456                    Each queue has a single entry in the table to which we write
 457                    a vector number along with a "valid" bit.  Sadly, the layout
 458                    of the table is somewhat counterintuitive. */
 459                 if (rx_queue > IGB_N0_QUEUE) {
 460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 461                         ivar = array_rd32(E1000_IVAR0, index);
 462                         if (rx_queue & 0x1) {
 463                                 /* vector goes into third byte of register */
 464                                 ivar = ivar & 0xFF00FFFF;
 465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 466                         } else {
 467                                 /* vector goes into low byte of register */
 468                                 ivar = ivar & 0xFFFFFF00;
 469                                 ivar |= msix_vector | E1000_IVAR_VALID;
 470                         }
 471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 472                         array_wr32(E1000_IVAR0, index, ivar);
 473                 }
 474                 if (tx_queue > IGB_N0_QUEUE) {
 475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 476                         ivar = array_rd32(E1000_IVAR0, index);
 477                         if (tx_queue & 0x1) {
 478                                 /* vector goes into high byte of register */
 479                                 ivar = ivar & 0x00FFFFFF;
 480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 481                         } else {
 482                                 /* vector goes into second byte of register */
 483                                 ivar = ivar & 0xFFFF00FF;
 484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 485                         }
 486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 487                         array_wr32(E1000_IVAR0, index, ivar);
 488                 }
 489                 break;
 490         default:
 491                 BUG();
 492                 break;
 493         }
 494 }
 495
 496 /**
 497  * igb_configure_msix - Configure MSI-X hardware
 498  *
 499  * igb_configure_msix sets up the hardware to properly
 500  * generate MSI-X interrupts.
 501  **/
 502 static void igb_configure_msix(struct igb_adapter *adapter)
 503 {
 504         u32 tmp;
 505         int i, vector = 0;
 506         struct e1000_hw *hw = &adapter->hw;
 507
 508         adapter->eims_enable_mask = 0;
 509         if (hw->mac.type == e1000_82576)
 510                 /* Turn on MSI-X capability first, or our settings
 511                  * won't stick.  And it will take days to debug. */
 512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 514                                    E1000_GPIE_NSICR);
 515
 516         for (i = 0; i < adapter->num_tx_queues; i++) {
 517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 519                 adapter->eims_enable_mask |= tx_ring->eims_value;
 520                 if (tx_ring->itr_val)
 521                         writel(tx_ring->itr_val,
 522                                hw->hw_addr + tx_ring->itr_register);
 523                 else
 524                         writel(1, hw->hw_addr + tx_ring->itr_register);
 525         }
 526
 527         for (i = 0; i < adapter->num_rx_queues; i++) {
 528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 529                 rx_ring->buddy = NULL;
 530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 531                 adapter->eims_enable_mask |= rx_ring->eims_value;
 532                 if (rx_ring->itr_val)
 533                         writel(rx_ring->itr_val,
 534                                hw->hw_addr + rx_ring->itr_register);
 535                 else
 536                         writel(1, hw->hw_addr + rx_ring->itr_register);
 537         }
 538
 539
 540         /* set vector for other causes, i.e. link changes */
 541         switch (hw->mac.type) {
 542         case e1000_82575:
 543                 array_wr32(E1000_MSIXBM(0), vector++,
 544                                       E1000_EIMS_OTHER);
 545
 546                 tmp = rd32(E1000_CTRL_EXT);
 547                 /* enable MSI-X PBA support*/
 548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 549
 550                 /* Auto-Mask interrupts upon ICR read. */
 551                 tmp |= E1000_CTRL_EXT_EIAME;
 552                 tmp |= E1000_CTRL_EXT_IRCA;
 553
 554                 wr32(E1000_CTRL_EXT, tmp);
 555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 556                 adapter->eims_other = E1000_EIMS_OTHER;
 557
 558                 break;
 559
 560         case e1000_82576:
 561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 562                 wr32(E1000_IVAR_MISC, tmp);
 563
 564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 565                 adapter->eims_other = 1 << (vector - 1);
 566                 break;
 567         default:
 568                 /* do nothing, since nothing else supports MSI-X */
 569                 break;
 570         } /* switch (hw->mac.type) */
 571         wrfl();
 572 }
 573
 574 /**
 575  * igb_request_msix - Initialize MSI-X interrupts
 576  *
 577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 578  * kernel.
 579  **/
 580 static int igb_request_msix(struct igb_adapter *adapter)
 581 {
 582         struct net_device *netdev = adapter->netdev;
 583         int i, err = 0, vector = 0;
 584
 585         vector = 0;
 586
 587         for (i = 0; i < adapter->num_tx_queues; i++) {
 588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 590                 err = request_irq(adapter->msix_entries[vector].vector,
 591                                   &igb_msix_tx, 0, ring->name,
 592                                   &(adapter->tx_ring[i]));
 593                 if (err)
 594                         goto out;
 595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 596                 ring->itr_val = 976; /* ~4000 ints/sec */
 597                 vector++;
 598         }
 599         for (i = 0; i < adapter->num_rx_queues; i++) {
 600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 603                 else
 604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 605                 err = request_irq(adapter->msix_entries[vector].vector,
 606                                   &igb_msix_rx, 0, ring->name,
 607                                   &(adapter->rx_ring[i]));
 608                 if (err)
 609                         goto out;
 610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 611                 ring->itr_val = adapter->itr;
 612                 vector++;
 613         }
 614
 615         err = request_irq(adapter->msix_entries[vector].vector,
 616                           &igb_msix_other, 0, netdev->name, netdev);
 617         if (err)
 618                 goto out;
 619
 620         igb_configure_msix(adapter);
 621         return 0;
 622 out:
 623         return err;
 624 }
 625
 626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 627 {
 628         if (adapter->msix_entries) {
 629                 pci_disable_msix(adapter->pdev);
 630                 kfree(adapter->msix_entries);
 631                 adapter->msix_entries = NULL;
 632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 633                 pci_disable_msi(adapter->pdev);
 634         return;
 635 }
 636
 637
 638 /**
 639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 640  *
 641  * Attempt to configure interrupts using the best available
 642  * capabilities of the hardware and kernel.
 643  **/
 644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 645 {
 646         int err;
 647         int numvecs, i;
 648
 649         /* Number of supported queues. */
 650         /* Having more queues than CPUs doesn't make sense. */
 651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 653
 654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 656                                         GFP_KERNEL);
 657         if (!adapter->msix_entries)
 658                 goto msi_only;
 659
 660         for (i = 0; i < numvecs; i++)
 661                 adapter->msix_entries[i].entry = i;
 662
 663         err = pci_enable_msix(adapter->pdev,
 664                               adapter->msix_entries,
 665                               numvecs);
 666         if (err == 0)
 667                 goto out;
 668
 669         igb_reset_interrupt_capability(adapter);
 670
 671         /* If we can't do MSI-X, try MSI */
 672 msi_only:
 673 #ifdef CONFIG_PCI_IOV
 674         /* disable SR-IOV for non MSI-X configurations */
 675         if (adapter->vf_data) {
 676                 struct e1000_hw *hw = &adapter->hw;
 677                 /* disable iov and allow time for transactions to clear */
 678                 pci_disable_sriov(adapter->pdev);
 679                 msleep(500);
 680
 681                 kfree(adapter->vf_data);
 682                 adapter->vf_data = NULL;
 683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 684                 msleep(100);
 685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 686         }
 687 #endif
 688         adapter->num_rx_queues = 1;
 689         adapter->num_tx_queues = 1;
 690         if (!pci_enable_msi(adapter->pdev))
 691                 adapter->flags |= IGB_FLAG_HAS_MSI;
 692 out:
 693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 695         return;
 696 }
 697
 698 /**
 699  * igb_request_irq - initialize interrupts
 700  *
 701  * Attempts to configure interrupts using the best available
 702  * capabilities of the hardware and kernel.
 703  **/
 704 static int igb_request_irq(struct igb_adapter *adapter)
 705 {
 706         struct net_device *netdev = adapter->netdev;
 707         struct e1000_hw *hw = &adapter->hw;
 708         int err = 0;
 709
 710         if (adapter->msix_entries) {
 711                 err = igb_request_msix(adapter);
 712                 if (!err)
 713                         goto request_done;
 714                 /* fall back to MSI */
 715                 igb_reset_interrupt_capability(adapter);
 716                 if (!pci_enable_msi(adapter->pdev))
 717                         adapter->flags |= IGB_FLAG_HAS_MSI;
 718                 igb_free_all_tx_resources(adapter);
 719                 igb_free_all_rx_resources(adapter);
 720                 adapter->num_rx_queues = 1;
 721                 igb_alloc_queues(adapter);
 722         } else {
 723                 switch (hw->mac.type) {
 724                 case e1000_82575:
 725                         wr32(E1000_MSIXBM(0),
 726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 727                         break;
 728                 case e1000_82576:
 729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 730                         break;
 731                 default:
 732                         break;
 733                 }
 734         }
 735
 736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 738                                   netdev->name, netdev);
 739                 if (!err)
 740                         goto request_done;
 741                 /* fall back to legacy interrupts */
 742                 igb_reset_interrupt_capability(adapter);
 743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 744         }
 745
 746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 747                           netdev->name, netdev);
 748
 749         if (err)
 750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 751                         err);
 752
 753 request_done:
 754         return err;
 755 }
 756
 757 static void igb_free_irq(struct igb_adapter *adapter)
 758 {
 759         struct net_device *netdev = adapter->netdev;
 760
 761         if (adapter->msix_entries) {
 762                 int vector = 0, i;
 763
 764                 for (i = 0; i < adapter->num_tx_queues; i++)
 765                         free_irq(adapter->msix_entries[vector++].vector,
 766                                 &(adapter->tx_ring[i]));
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         free_irq(adapter->msix_entries[vector++].vector,
 769                                 &(adapter->rx_ring[i]));
 770
 771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 772                 return;
 773         }
 774
 775         free_irq(adapter->pdev->irq, netdev);
 776 }
 777
 778 /**
 779  * igb_irq_disable - Mask off interrupt generation on the NIC
 780  * @adapter: board private structure
 781  **/
 782 static void igb_irq_disable(struct igb_adapter *adapter)
 783 {
 784         struct e1000_hw *hw = &adapter->hw;
 785
 786         if (adapter->msix_entries) {
 787                 wr32(E1000_EIAM, 0);
 788                 wr32(E1000_EIMC, ~0);
 789                 wr32(E1000_EIAC, 0);
 790         }
 791
 792         wr32(E1000_IAM, 0);
 793         wr32(E1000_IMC, ~0);
 794         wrfl();
 795         synchronize_irq(adapter->pdev->irq);
 796 }
 797
 798 /**
 799  * igb_irq_enable - Enable default interrupt generation settings
 800  * @adapter: board private structure
 801  **/
 802 static void igb_irq_enable(struct igb_adapter *adapter)
 803 {
 804         struct e1000_hw *hw = &adapter->hw;
 805
 806         if (adapter->msix_entries) {
 807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 810                 if (adapter->vfs_allocated_count)
 811                         wr32(E1000_MBVFIMR, 0xFF);
 812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 813                                  E1000_IMS_DOUTSYNC));
 814         } else {
 815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 817         }
 818 }
 819
 820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 821 {
 822         struct net_device *netdev = adapter->netdev;
 823         u16 vid = adapter->hw.mng_cookie.vlan_id;
 824         u16 old_vid = adapter->mng_vlan_id;
 825         if (adapter->vlgrp) {
 826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 827                         if (adapter->hw.mng_cookie.status &
 828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 829                                 igb_vlan_rx_add_vid(netdev, vid);
 830                                 adapter->mng_vlan_id = vid;
 831                         } else
 832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 833
 834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 835                                         (vid != old_vid) &&
 836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 838                 } else
 839                         adapter->mng_vlan_id = vid;
 840         }
 841 }
 842
 843 /**
 844  * igb_release_hw_control - release control of the h/w to f/w
 845  * @adapter: address of board private structure
 846  *
 847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 848  * For ASF and Pass Through versions of f/w this means that the
 849  * driver is no longer loaded.
 850  *
 851  **/
 852 static void igb_release_hw_control(struct igb_adapter *adapter)
 853 {
 854         struct e1000_hw *hw = &adapter->hw;
 855         u32 ctrl_ext;
 856
 857         /* Let firmware take over control of h/w */
 858         ctrl_ext = rd32(E1000_CTRL_EXT);
 859         wr32(E1000_CTRL_EXT,
 860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 861 }
 862
 863
 864 /**
 865  * igb_get_hw_control - get control of the h/w from f/w
 866  * @adapter: address of board private structure
 867  *
 868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 869  * For ASF and Pass Through versions of f/w this means that
 870  * the driver is loaded.
 871  *
 872  **/
 873 static void igb_get_hw_control(struct igb_adapter *adapter)
 874 {
 875         struct e1000_hw *hw = &adapter->hw;
 876         u32 ctrl_ext;
 877
 878         /* Let firmware know the driver has taken over */
 879         ctrl_ext = rd32(E1000_CTRL_EXT);
 880         wr32(E1000_CTRL_EXT,
 881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 882 }
 883
 884 /**
 885  * igb_configure - configure the hardware for RX and TX
 886  * @adapter: private board structure
 887  **/
 888 static void igb_configure(struct igb_adapter *adapter)
 889 {
 890         struct net_device *netdev = adapter->netdev;
 891         int i;
 892
 893         igb_get_hw_control(adapter);
 894         igb_set_multi(netdev);
 895
 896         igb_restore_vlan(adapter);
 897
 898         igb_configure_tx(adapter);
 899         igb_setup_rctl(adapter);
 900         igb_configure_rx(adapter);
 901
 902         igb_rx_fifo_flush_82575(&adapter->hw);
 903
 904         /* call igb_desc_unused which always leaves
 905          * at least 1 descriptor unused to make sure
 906          * next_to_use != next_to_clean */
 907         for (i = 0; i < adapter->num_rx_queues; i++) {
 908                 struct igb_ring *ring = &adapter->rx_ring[i];
 909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 910         }
 911
 912
 913         adapter->tx_queue_len = netdev->tx_queue_len;
 914 }
 915
 916
 917 /**
 918  * igb_up - Open the interface and prepare it to handle traffic
 919  * @adapter: board private structure
 920  **/
 921
 922 int igb_up(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         int i;
 926
 927         /* hardware has been reset, we need to reload some things */
 928         igb_configure(adapter);
 929
 930         clear_bit(__IGB_DOWN, &adapter->state);
 931
 932         for (i = 0; i < adapter->num_rx_queues; i++)
 933                 napi_enable(&adapter->rx_ring[i].napi);
 934         if (adapter->msix_entries)
 935                 igb_configure_msix(adapter);
 936
 937         igb_vmm_control(adapter);
 938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 940
 941         /* Clear any pending interrupts. */
 942         rd32(E1000_ICR);
 943         igb_irq_enable(adapter);
 944
 945         netif_tx_start_all_queues(adapter->netdev);
 946
 947         /* Fire a link change interrupt to start the watchdog. */
 948         wr32(E1000_ICS, E1000_ICS_LSC);
 949         return 0;
 950 }
 951
 952 void igb_down(struct igb_adapter *adapter)
 953 {
 954         struct e1000_hw *hw = &adapter->hw;
 955         struct net_device *netdev = adapter->netdev;
 956         u32 tctl, rctl;
 957         int i;
 958
 959         /* signal that we're down so the interrupt handler does not
 960          * reschedule our watchdog timer */
 961         set_bit(__IGB_DOWN, &adapter->state);
 962
 963         /* disable receives in the hardware */
 964         rctl = rd32(E1000_RCTL);
 965         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 966         /* flush and sleep below */
 967
 968         netif_tx_stop_all_queues(netdev);
 969
 970         /* disable transmits in the hardware */
 971         tctl = rd32(E1000_TCTL);
 972         tctl &= ~E1000_TCTL_EN;
 973         wr32(E1000_TCTL, tctl);
 974         /* flush both disables and wait for them to finish */
 975         wrfl();
 976         msleep(10);
 977
 978         for (i = 0; i < adapter->num_rx_queues; i++)
 979                 napi_disable(&adapter->rx_ring[i].napi);
 980
 981         igb_irq_disable(adapter);
 982
 983         del_timer_sync(&adapter->watchdog_timer);
 984         del_timer_sync(&adapter->phy_info_timer);
 985
 986         netdev->tx_queue_len = adapter->tx_queue_len;
 987         netif_carrier_off(netdev);
 988
 989         /* record the stats before reset*/
 990         igb_update_stats(adapter);
 991
 992         adapter->link_speed = 0;
 993         adapter->link_duplex = 0;
 994
 995         if (!pci_channel_offline(adapter->pdev))
 996                 igb_reset(adapter);
 997         igb_clean_all_tx_rings(adapter);
 998         igb_clean_all_rx_rings(adapter);
 999 #ifdef CONFIG_IGB_DCA
1000
1001         /* since we reset the hardware DCA settings were cleared */
1002         igb_setup_dca(adapter);
1003 #endif
1004 }
1005
1006 void igb_reinit_locked(struct igb_adapter *adapter)
1007 {
1008         WARN_ON(in_interrupt());
1009         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1010                 msleep(1);
1011         igb_down(adapter);
1012         igb_up(adapter);
1013         clear_bit(__IGB_RESETTING, &adapter->state);
1014 }
1015
1016 void igb_reset(struct igb_adapter *adapter)
1017 {
1018         struct e1000_hw *hw = &adapter->hw;
1019         struct e1000_mac_info *mac = &hw->mac;
1020         struct e1000_fc_info *fc = &hw->fc;
1021         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1022         u16 hwm;
1023
1024         /* Repartition Pba for greater than 9k mtu
1025          * To take effect CTRL.RST is required.
1026          */
1027         switch (mac->type) {
1028         case e1000_82576:
1029                 pba = E1000_PBA_64K;
1030                 break;
1031         case e1000_82575:
1032         default:
1033                 pba = E1000_PBA_34K;
1034                 break;
1035         }
1036
1037         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1038             (mac->type < e1000_82576)) {
1039                 /* adjust PBA for jumbo frames */
1040                 wr32(E1000_PBA, pba);
1041
1042                 /* To maintain wire speed transmits, the Tx FIFO should be
1043                  * large enough to accommodate two full transmit packets,
1044                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1045                  * the Rx FIFO should be large enough to accommodate at least
1046                  * one full receive packet and is similarly rounded up and
1047                  * expressed in KB. */
1048                 pba = rd32(E1000_PBA);
1049                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1050                 tx_space = pba >> 16;
1051                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1052                 pba &= 0xffff;
1053                 /* the tx fifo also stores 16 bytes of information about the tx
1054                  * but don't include ethernet FCS because hardware appends it */
1055                 min_tx_space = (adapter->max_frame_size +
1056                                 sizeof(union e1000_adv_tx_desc) -
1057                                 ETH_FCS_LEN) * 2;
1058                 min_tx_space = ALIGN(min_tx_space, 1024);
1059                 min_tx_space >>= 10;
1060                 /* software strips receive CRC, so leave room for it */
1061                 min_rx_space = adapter->max_frame_size;
1062                 min_rx_space = ALIGN(min_rx_space, 1024);
1063                 min_rx_space >>= 10;
1064
1065                 /* If current Tx allocation is less than the min Tx FIFO size,
1066                  * and the min Tx FIFO size is less than the current Rx FIFO
1067                  * allocation, take space away from current Rx allocation */
1068                 if (tx_space < min_tx_space &&
1069                     ((min_tx_space - tx_space) < pba)) {
1070                         pba = pba - (min_tx_space - tx_space);
1071
1072                         /* if short on rx space, rx wins and must trump tx
1073                          * adjustment */
1074                         if (pba < min_rx_space)
1075                                 pba = min_rx_space;
1076                 }
1077                 wr32(E1000_PBA, pba);
1078         }
1079
1080         /* flow control settings */
1081         /* The high water mark must be low enough to fit one full frame
1082          * (or the size used for early receive) above it in the Rx FIFO.
1083          * Set it to the lower of:
1084          * - 90% of the Rx FIFO size, or
1085          * - the full Rx FIFO size minus one full frame */
1086         hwm = min(((pba << 10) * 9 / 10),
1087                         ((pba << 10) - 2 * adapter->max_frame_size));
1088
1089         if (mac->type < e1000_82576) {
1090                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1091                 fc->low_water = fc->high_water - 8;
1092         } else {
1093                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1094                 fc->low_water = fc->high_water - 16;
1095         }
1096         fc->pause_time = 0xFFFF;
1097         fc->send_xon = 1;
1098         fc->type = fc->original_type;
1099
1100         /* disable receive for all VFs and wait one second */
1101         if (adapter->vfs_allocated_count) {
1102                 int i;
1103                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1104                         adapter->vf_data[i].clear_to_send = false;
1105
1106                 /* ping all the active vfs to let them know we are going down */
1107                         igb_ping_all_vfs(adapter);
1108
1109                 /* disable transmits and receives */
1110                 wr32(E1000_VFRE, 0);
1111                 wr32(E1000_VFTE, 0);
1112         }
1113
1114         /* Allow time for pending master requests to run */
1115         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1116         wr32(E1000_WUC, 0);
1117
1118         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1119                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1120
1121         igb_update_mng_vlan(adapter);
1122
1123         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1124         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1125
1126         igb_reset_adaptive(&adapter->hw);
1127         igb_get_phy_info(&adapter->hw);
1128 }
1129
1130 static const struct net_device_ops igb_netdev_ops = {
1131         .ndo_open               = igb_open,
1132         .ndo_stop               = igb_close,
1133         .ndo_start_xmit         = igb_xmit_frame_adv,
1134         .ndo_get_stats          = igb_get_stats,
1135         .ndo_set_multicast_list = igb_set_multi,
1136         .ndo_set_mac_address    = igb_set_mac,
1137         .ndo_change_mtu         = igb_change_mtu,
1138         .ndo_do_ioctl           = igb_ioctl,
1139         .ndo_tx_timeout         = igb_tx_timeout,
1140         .ndo_validate_addr      = eth_validate_addr,
1141         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1142         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1143         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1144 #ifdef CONFIG_NET_POLL_CONTROLLER
1145         .ndo_poll_controller    = igb_netpoll,
1146 #endif
1147 };
1148
1149 /**
1150  * igb_probe - Device Initialization Routine
1151  * @pdev: PCI device information struct
1152  * @ent: entry in igb_pci_tbl
1153  *
1154  * Returns 0 on success, negative on failure
1155  *
1156  * igb_probe initializes an adapter identified by a pci_dev structure.
1157  * The OS initialization, configuring of the adapter private structure,
1158  * and a hardware reset occur.
1159  **/
1160 static int __devinit igb_probe(struct pci_dev *pdev,
1161                                const struct pci_device_id *ent)
1162 {
1163         struct net_device *netdev;
1164         struct igb_adapter *adapter;
1165         struct e1000_hw *hw;
1166         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1167         unsigned long mmio_start, mmio_len;
1168         int err, pci_using_dac;
1169         u16 eeprom_data = 0;
1170         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1171         u32 part_num;
1172
1173         err = pci_enable_device_mem(pdev);
1174         if (err)
1175                 return err;
1176
1177         pci_using_dac = 0;
1178         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1179         if (!err) {
1180                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1181                 if (!err)
1182                         pci_using_dac = 1;
1183         } else {
1184                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1185                 if (err) {
1186                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1187                         if (err) {
1188                                 dev_err(&pdev->dev, "No usable DMA "
1189                                         "configuration, aborting\n");
1190                                 goto err_dma;
1191                         }
1192                 }
1193         }
1194
1195         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1196                                            IORESOURCE_MEM),
1197                                            igb_driver_name);
1198         if (err)
1199                 goto err_pci_reg;
1200
1201         err = pci_enable_pcie_error_reporting(pdev);
1202         if (err) {
1203                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1204                         "0x%x\n", err);
1205                 /* non-fatal, continue */
1206         }
1207
1208         pci_set_master(pdev);
1209         pci_save_state(pdev);
1210
1211         err = -ENOMEM;
1212         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1213                                    IGB_ABS_MAX_TX_QUEUES);
1214         if (!netdev)
1215                 goto err_alloc_etherdev;
1216
1217         SET_NETDEV_DEV(netdev, &pdev->dev);
1218
1219         pci_set_drvdata(pdev, netdev);
1220         adapter = netdev_priv(netdev);
1221         adapter->netdev = netdev;
1222         adapter->pdev = pdev;
1223         hw = &adapter->hw;
1224         hw->back = adapter;
1225         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1226
1227         mmio_start = pci_resource_start(pdev, 0);
1228         mmio_len = pci_resource_len(pdev, 0);
1229
1230         err = -EIO;
1231         hw->hw_addr = ioremap(mmio_start, mmio_len);
1232         if (!hw->hw_addr)
1233                 goto err_ioremap;
1234
1235         netdev->netdev_ops = &igb_netdev_ops;
1236         igb_set_ethtool_ops(netdev);
1237         netdev->watchdog_timeo = 5 * HZ;
1238
1239         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1240
1241         netdev->mem_start = mmio_start;
1242         netdev->mem_end = mmio_start + mmio_len;
1243
1244         /* PCI config space info */
1245         hw->vendor_id = pdev->vendor;
1246         hw->device_id = pdev->device;
1247         hw->revision_id = pdev->revision;
1248         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1249         hw->subsystem_device_id = pdev->subsystem_device;
1250
1251         /* setup the private structure */
1252         hw->back = adapter;
1253         /* Copy the default MAC, PHY and NVM function pointers */
1254         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1255         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1256         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1257         /* Initialize skew-specific constants */
1258         err = ei->get_invariants(hw);
1259         if (err)
1260                 goto err_sw_init;
1261
1262 #ifdef CONFIG_PCI_IOV
1263         /* since iov functionality isn't critical to base device function we
1264          * can accept failure.  If it fails we don't allow iov to be enabled */
1265         if (hw->mac.type == e1000_82576) {
1266                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1267                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1268                 int i;
1269                 unsigned char mac_addr[ETH_ALEN];
1270
1271                 if (num_vfs) {
1272                         adapter->vf_data = kcalloc(num_vfs,
1273                                                 sizeof(struct vf_data_storage),
1274                                                 GFP_KERNEL);
1275                         if (!adapter->vf_data) {
1276                                 dev_err(&pdev->dev,
1277                                         "Could not allocate VF private data - "
1278                                         "IOV enable failed\n");
1279                         } else {
1280                                 err = pci_enable_sriov(pdev, num_vfs);
1281                                 if (!err) {
1282                                         adapter->vfs_allocated_count = num_vfs;
1283                                         dev_info(&pdev->dev,
1284                                                  "%d vfs allocated\n",
1285                                                  num_vfs);
1286                                         for (i = 0;
1287                                              i < adapter->vfs_allocated_count;
1288                                              i++) {
1289                                                 random_ether_addr(mac_addr);
1290                                                 igb_set_vf_mac(adapter, i,
1291                                                                mac_addr);
1292                                         }
1293                                 } else {
1294                                         kfree(adapter->vf_data);
1295                                         adapter->vf_data = NULL;
1296                                 }
1297                         }
1298                 }
1299         }
1300
1301 #endif
1302         /* setup the private structure */
1303         err = igb_sw_init(adapter);
1304         if (err)
1305                 goto err_sw_init;
1306
1307         igb_get_bus_info_pcie(hw);
1308
1309         /* set flags */
1310         switch (hw->mac.type) {
1311         case e1000_82575:
1312                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1313                 break;
1314         case e1000_82576:
1315         default:
1316                 break;
1317         }
1318
1319         hw->phy.autoneg_wait_to_complete = false;
1320         hw->mac.adaptive_ifs = true;
1321
1322         /* Copper options */
1323         if (hw->phy.media_type == e1000_media_type_copper) {
1324                 hw->phy.mdix = AUTO_ALL_MODES;
1325                 hw->phy.disable_polarity_correction = false;
1326                 hw->phy.ms_type = e1000_ms_hw_default;
1327         }
1328
1329         if (igb_check_reset_block(hw))
1330                 dev_info(&pdev->dev,
1331                         "PHY reset is blocked due to SOL/IDER session.\n");
1332
1333         netdev->features = NETIF_F_SG |
1334                            NETIF_F_IP_CSUM |
1335                            NETIF_F_HW_VLAN_TX |
1336                            NETIF_F_HW_VLAN_RX |
1337                            NETIF_F_HW_VLAN_FILTER;
1338
1339         netdev->features |= NETIF_F_IPV6_CSUM;
1340         netdev->features |= NETIF_F_TSO;
1341         netdev->features |= NETIF_F_TSO6;
1342
1343         netdev->features |= NETIF_F_GRO;
1344
1345         netdev->vlan_features |= NETIF_F_TSO;
1346         netdev->vlan_features |= NETIF_F_TSO6;
1347         netdev->vlan_features |= NETIF_F_IP_CSUM;
1348         netdev->vlan_features |= NETIF_F_SG;
1349
1350         if (pci_using_dac)
1351                 netdev->features |= NETIF_F_HIGHDMA;
1352
1353         if (adapter->hw.mac.type == e1000_82576)
1354                 netdev->features |= NETIF_F_SCTP_CSUM;
1355
1356         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1357
1358         /* before reading the NVM, reset the controller to put the device in a
1359          * known good starting state */
1360         hw->mac.ops.reset_hw(hw);
1361
1362         /* make sure the NVM is good */
1363         if (igb_validate_nvm_checksum(hw) < 0) {
1364                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1365                 err = -EIO;
1366                 goto err_eeprom;
1367         }
1368
1369         /* copy the MAC address out of the NVM */
1370         if (hw->mac.ops.read_mac_addr(hw))
1371                 dev_err(&pdev->dev, "NVM Read Error\n");
1372
1373         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1374         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1375
1376         if (!is_valid_ether_addr(netdev->perm_addr)) {
1377                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1378                 err = -EIO;
1379                 goto err_eeprom;
1380         }
1381
1382         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1383                     (unsigned long) adapter);
1384         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1385                     (unsigned long) adapter);
1386
1387         INIT_WORK(&adapter->reset_task, igb_reset_task);
1388         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1389
1390         /* Initialize link properties that are user-changeable */
1391         adapter->fc_autoneg = true;
1392         hw->mac.autoneg = true;
1393         hw->phy.autoneg_advertised = 0x2f;
1394
1395         hw->fc.original_type = e1000_fc_default;
1396         hw->fc.type = e1000_fc_default;
1397
1398         adapter->itr_setting = IGB_DEFAULT_ITR;
1399         adapter->itr = IGB_START_ITR;
1400
1401         igb_validate_mdi_setting(hw);
1402
1403         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1404          * enable the ACPI Magic Packet filter
1405          */
1406
1407         if (hw->bus.func == 0)
1408                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1409         else if (hw->bus.func == 1)
1410                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1411
1412         if (eeprom_data & eeprom_apme_mask)
1413                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1414
1415         /* now that we have the eeprom settings, apply the special cases where
1416          * the eeprom may be wrong or the board simply won't support wake on
1417          * lan on a particular port */
1418         switch (pdev->device) {
1419         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1420                 adapter->eeprom_wol = 0;
1421                 break;
1422         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1423         case E1000_DEV_ID_82576_FIBER:
1424         case E1000_DEV_ID_82576_SERDES:
1425                 /* Wake events only supported on port A for dual fiber
1426                  * regardless of eeprom setting */
1427                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1428                         adapter->eeprom_wol = 0;
1429                 break;
1430         case E1000_DEV_ID_82576_QUAD_COPPER:
1431                 /* if quad port adapter, disable WoL on all but port A */
1432                 if (global_quad_port_a != 0)
1433                         adapter->eeprom_wol = 0;
1434                 else
1435                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1436                 /* Reset for multiple quad port adapters */
1437                 if (++global_quad_port_a == 4)
1438                         global_quad_port_a = 0;
1439                 break;
1440         }
1441
1442         /* initialize the wol settings based on the eeprom settings */
1443         adapter->wol = adapter->eeprom_wol;
1444         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1445
1446         /* reset the hardware with the new settings */
1447         igb_reset(adapter);
1448
1449         /* let the f/w know that the h/w is now under the control of the
1450          * driver. */
1451         igb_get_hw_control(adapter);
1452
1453         strcpy(netdev->name, "eth%d");
1454         err = register_netdev(netdev);
1455         if (err)
1456                 goto err_register;
1457
1458         /* carrier off reporting is important to ethtool even BEFORE open */
1459         netif_carrier_off(netdev);
1460
1461 #ifdef CONFIG_IGB_DCA
1462         if (dca_add_requester(&pdev->dev) == 0) {
1463                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1464                 dev_info(&pdev->dev, "DCA enabled\n");
1465                 igb_setup_dca(adapter);
1466         }
1467 #endif
1468
1469         /*
1470          * Initialize hardware timer: we keep it running just in case
1471          * that some program needs it later on.
1472          */
1473         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1474         adapter->cycles.read = igb_read_clock;
1475         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1476         adapter->cycles.mult = 1;
1477         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1478         wr32(E1000_TIMINCA,
1479              (1<<24) |
1480              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1481 #if 0
1482         /*
1483          * Avoid rollover while we initialize by resetting the time counter.
1484          */
1485         wr32(E1000_SYSTIML, 0x00000000);
1486         wr32(E1000_SYSTIMH, 0x00000000);
1487 #else
1488         /*
1489          * Set registers so that rollover occurs soon to test this.
1490          */
1491         wr32(E1000_SYSTIML, 0x00000000);
1492         wr32(E1000_SYSTIMH, 0xFF800000);
1493 #endif
1494         wrfl();
1495         timecounter_init(&adapter->clock,
1496                          &adapter->cycles,
1497                          ktime_to_ns(ktime_get_real()));
1498
1499         /*
1500          * Synchronize our NIC clock against system wall clock. NIC
1501          * time stamp reading requires ~3us per sample, each sample
1502          * was pretty stable even under load => only require 10
1503          * samples for each offset comparison.
1504          */
1505         memset(&adapter->compare, 0, sizeof(adapter->compare));
1506         adapter->compare.source = &adapter->clock;
1507         adapter->compare.target = ktime_get_real;
1508         adapter->compare.num_samples = 10;
1509         timecompare_update(&adapter->compare, 0);
1510
1511 #ifdef DEBUG
1512         {
1513                 char buffer[160];
1514                 printk(KERN_DEBUG
1515                         "igb: %s: hw %p initialized timer\n",
1516                         igb_get_time_str(adapter, buffer),
1517                         &adapter->hw);
1518         }
1519 #endif
1520
1521         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1522         /* print bus type/speed/width info */
1523         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1524                  netdev->name,
1525                  ((hw->bus.speed == e1000_bus_speed_2500)
1526                   ? "2.5Gb/s" : "unknown"),
1527                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1528                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1529                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1530                    "unknown"),
1531                  netdev->dev_addr);
1532
1533         igb_read_part_num(hw, &part_num);
1534         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1535                 (part_num >> 8), (part_num & 0xff));
1536
1537         dev_info(&pdev->dev,
1538                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1539                 adapter->msix_entries ? "MSI-X" :
1540                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1541                 adapter->num_rx_queues, adapter->num_tx_queues);
1542
1543         return 0;
1544
1545 err_register:
1546         igb_release_hw_control(adapter);
1547 err_eeprom:
1548         if (!igb_check_reset_block(hw))
1549                 igb_reset_phy(hw);
1550
1551         if (hw->flash_address)
1552                 iounmap(hw->flash_address);
1553
1554         igb_free_queues(adapter);
1555 err_sw_init:
1556         iounmap(hw->hw_addr);
1557 err_ioremap:
1558         free_netdev(netdev);
1559 err_alloc_etherdev:
1560         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1561                                      IORESOURCE_MEM));
1562 err_pci_reg:
1563 err_dma:
1564         pci_disable_device(pdev);
1565         return err;
1566 }
1567
1568 /**
1569  * igb_remove - Device Removal Routine
1570  * @pdev: PCI device information struct
1571  *
1572  * igb_remove is called by the PCI subsystem to alert the driver
1573  * that it should release a PCI device.  The could be caused by a
1574  * Hot-Plug event, or because the driver is going to be removed from
1575  * memory.
1576  **/
1577 static void __devexit igb_remove(struct pci_dev *pdev)
1578 {
1579         struct net_device *netdev = pci_get_drvdata(pdev);
1580         struct igb_adapter *adapter = netdev_priv(netdev);
1581         struct e1000_hw *hw = &adapter->hw;
1582         int err;
1583
1584         /* flush_scheduled work may reschedule our watchdog task, so
1585          * explicitly disable watchdog tasks from being rescheduled  */
1586         set_bit(__IGB_DOWN, &adapter->state);
1587         del_timer_sync(&adapter->watchdog_timer);
1588         del_timer_sync(&adapter->phy_info_timer);
1589
1590         flush_scheduled_work();
1591
1592 #ifdef CONFIG_IGB_DCA
1593         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1594                 dev_info(&pdev->dev, "DCA disabled\n");
1595                 dca_remove_requester(&pdev->dev);
1596                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1597                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1598         }
1599 #endif
1600
1601         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1602          * would have already happened in close and is redundant. */
1603         igb_release_hw_control(adapter);
1604
1605         unregister_netdev(netdev);
1606
1607         if (!igb_check_reset_block(&adapter->hw))
1608                 igb_reset_phy(&adapter->hw);
1609
1610         igb_reset_interrupt_capability(adapter);
1611
1612         igb_free_queues(adapter);
1613
1614 #ifdef CONFIG_PCI_IOV
1615         /* reclaim resources allocated to VFs */
1616         if (adapter->vf_data) {
1617                 /* disable iov and allow time for transactions to clear */
1618                 pci_disable_sriov(pdev);
1619                 msleep(500);
1620
1621                 kfree(adapter->vf_data);
1622                 adapter->vf_data = NULL;
1623                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1624                 msleep(100);
1625                 dev_info(&pdev->dev, "IOV Disabled\n");
1626         }
1627 #endif
1628         iounmap(hw->hw_addr);
1629         if (hw->flash_address)
1630                 iounmap(hw->flash_address);
1631         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1632                                      IORESOURCE_MEM));
1633
1634         free_netdev(netdev);
1635
1636         err = pci_disable_pcie_error_reporting(pdev);
1637         if (err)
1638                 dev_err(&pdev->dev,
1639                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1640
1641         pci_disable_device(pdev);
1642 }
1643
1644 /**
1645  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1646  * @adapter: board private structure to initialize
1647  *
1648  * igb_sw_init initializes the Adapter private data structure.
1649  * Fields are initialized based on PCI device information and
1650  * OS network device settings (MTU size).
1651  **/
1652 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1653 {
1654         struct e1000_hw *hw = &adapter->hw;
1655         struct net_device *netdev = adapter->netdev;
1656         struct pci_dev *pdev = adapter->pdev;
1657
1658         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1659
1660         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1661         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1662         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1663         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1664         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1665         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1666
1667         /* This call may decrease the number of queues depending on
1668          * interrupt mode. */
1669         igb_set_interrupt_capability(adapter);
1670
1671         if (igb_alloc_queues(adapter)) {
1672                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1673                 return -ENOMEM;
1674         }
1675
1676         /* Explicitly disable IRQ since the NIC can be in any state. */
1677         igb_irq_disable(adapter);
1678
1679         set_bit(__IGB_DOWN, &adapter->state);
1680         return 0;
1681 }
1682
1683 /**
1684  * igb_open - Called when a network interface is made active
1685  * @netdev: network interface device structure
1686  *
1687  * Returns 0 on success, negative value on failure
1688  *
1689  * The open entry point is called when a network interface is made
1690  * active by the system (IFF_UP).  At this point all resources needed
1691  * for transmit and receive operations are allocated, the interrupt
1692  * handler is registered with the OS, the watchdog timer is started,
1693  * and the stack is notified that the interface is ready.
1694  **/
1695 static int igb_open(struct net_device *netdev)
1696 {
1697         struct igb_adapter *adapter = netdev_priv(netdev);
1698         struct e1000_hw *hw = &adapter->hw;
1699         int err;
1700         int i;
1701
1702         /* disallow open during test */
1703         if (test_bit(__IGB_TESTING, &adapter->state))
1704                 return -EBUSY;
1705
1706         netif_carrier_off(netdev);
1707
1708         /* allocate transmit descriptors */
1709         err = igb_setup_all_tx_resources(adapter);
1710         if (err)
1711                 goto err_setup_tx;
1712
1713         /* allocate receive descriptors */
1714         err = igb_setup_all_rx_resources(adapter);
1715         if (err)
1716                 goto err_setup_rx;
1717
1718         /* e1000_power_up_phy(adapter); */
1719
1720         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1721         if ((adapter->hw.mng_cookie.status &
1722              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1723                 igb_update_mng_vlan(adapter);
1724
1725         /* before we allocate an interrupt, we must be ready to handle it.
1726          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1727          * as soon as we call pci_request_irq, so we have to setup our
1728          * clean_rx handler before we do so.  */
1729         igb_configure(adapter);
1730
1731         igb_vmm_control(adapter);
1732         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1733         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1734
1735         err = igb_request_irq(adapter);
1736         if (err)
1737                 goto err_req_irq;
1738
1739         /* From here on the code is the same as igb_up() */
1740         clear_bit(__IGB_DOWN, &adapter->state);
1741
1742         for (i = 0; i < adapter->num_rx_queues; i++)
1743                 napi_enable(&adapter->rx_ring[i].napi);
1744
1745         /* Clear any pending interrupts. */
1746         rd32(E1000_ICR);
1747
1748         igb_irq_enable(adapter);
1749
1750         netif_tx_start_all_queues(netdev);
1751
1752         /* Fire a link status change interrupt to start the watchdog. */
1753         wr32(E1000_ICS, E1000_ICS_LSC);
1754
1755         return 0;
1756
1757 err_req_irq:
1758         igb_release_hw_control(adapter);
1759         /* e1000_power_down_phy(adapter); */
1760         igb_free_all_rx_resources(adapter);
1761 err_setup_rx:
1762         igb_free_all_tx_resources(adapter);
1763 err_setup_tx:
1764         igb_reset(adapter);
1765
1766         return err;
1767 }
1768
1769 /**
1770  * igb_close - Disables a network interface
1771  * @netdev: network interface device structure
1772  *
1773  * Returns 0, this is not allowed to fail
1774  *
1775  * The close entry point is called when an interface is de-activated
1776  * by the OS.  The hardware is still under the driver's control, but
1777  * needs to be disabled.  A global MAC reset is issued to stop the
1778  * hardware, and all transmit and receive resources are freed.
1779  **/
1780 static int igb_close(struct net_device *netdev)
1781 {
1782         struct igb_adapter *adapter = netdev_priv(netdev);
1783
1784         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1785         igb_down(adapter);
1786
1787         igb_free_irq(adapter);
1788
1789         igb_free_all_tx_resources(adapter);
1790         igb_free_all_rx_resources(adapter);
1791
1792         /* kill manageability vlan ID if supported, but not if a vlan with
1793          * the same ID is registered on the host OS (let 8021q kill it) */
1794         if ((adapter->hw.mng_cookie.status &
1795                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1796              !(adapter->vlgrp &&
1797                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1798                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1799
1800         return 0;
1801 }
1802
1803 /**
1804  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1805  * @adapter: board private structure
1806  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1807  *
1808  * Return 0 on success, negative on failure
1809  **/
1810 int igb_setup_tx_resources(struct igb_adapter *adapter,
1811                            struct igb_ring *tx_ring)
1812 {
1813         struct pci_dev *pdev = adapter->pdev;
1814         int size;
1815
1816         size = sizeof(struct igb_buffer) * tx_ring->count;
1817         tx_ring->buffer_info = vmalloc(size);
1818         if (!tx_ring->buffer_info)
1819                 goto err;
1820         memset(tx_ring->buffer_info, 0, size);
1821
1822         /* round up to nearest 4K */
1823         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1824         tx_ring->size = ALIGN(tx_ring->size, 4096);
1825
1826         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1827                                              &tx_ring->dma);
1828
1829         if (!tx_ring->desc)
1830                 goto err;
1831
1832         tx_ring->adapter = adapter;
1833         tx_ring->next_to_use = 0;
1834         tx_ring->next_to_clean = 0;
1835         return 0;
1836
1837 err:
1838         vfree(tx_ring->buffer_info);
1839         dev_err(&adapter->pdev->dev,
1840                 "Unable to allocate memory for the transmit descriptor ring\n");
1841         return -ENOMEM;
1842 }
1843
1844 /**
1845  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1846  *                                (Descriptors) for all queues
1847  * @adapter: board private structure
1848  *
1849  * Return 0 on success, negative on failure
1850  **/
1851 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1852 {
1853         int i, err = 0;
1854         int r_idx;
1855
1856         for (i = 0; i < adapter->num_tx_queues; i++) {
1857                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1858                 if (err) {
1859                         dev_err(&adapter->pdev->dev,
1860                                 "Allocation for Tx Queue %u failed\n", i);
1861                         for (i--; i >= 0; i--)
1862                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1863                         break;
1864                 }
1865         }
1866
1867         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1868                 r_idx = i % adapter->num_tx_queues;
1869                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1870         }
1871         return err;
1872 }
1873
1874 /**
1875  * igb_configure_tx - Configure transmit Unit after Reset
1876  * @adapter: board private structure
1877  *
1878  * Configure the Tx unit of the MAC after a reset.
1879  **/
1880 static void igb_configure_tx(struct igb_adapter *adapter)
1881 {
1882         u64 tdba;
1883         struct e1000_hw *hw = &adapter->hw;
1884         u32 tctl;
1885         u32 txdctl, txctrl;
1886         int i, j;
1887
1888         for (i = 0; i < adapter->num_tx_queues; i++) {
1889                 struct igb_ring *ring = &adapter->tx_ring[i];
1890                 j = ring->reg_idx;
1891                 wr32(E1000_TDLEN(j),
1892                      ring->count * sizeof(union e1000_adv_tx_desc));
1893                 tdba = ring->dma;
1894                 wr32(E1000_TDBAL(j),
1895                      tdba & 0x00000000ffffffffULL);
1896                 wr32(E1000_TDBAH(j), tdba >> 32);
1897
1898                 ring->head = E1000_TDH(j);
1899                 ring->tail = E1000_TDT(j);
1900                 writel(0, hw->hw_addr + ring->tail);
1901                 writel(0, hw->hw_addr + ring->head);
1902                 txdctl = rd32(E1000_TXDCTL(j));
1903                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1904                 wr32(E1000_TXDCTL(j), txdctl);
1905
1906                 /* Turn off Relaxed Ordering on head write-backs.  The
1907                  * writebacks MUST be delivered in order or it will
1908                  * completely screw up our bookeeping.
1909                  */
1910                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1911                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1912                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1913         }
1914
1915         /* disable queue 0 to prevent tail bump w/o re-configuration */
1916         if (adapter->vfs_allocated_count)
1917                 wr32(E1000_TXDCTL(0), 0);
1918
1919         /* Program the Transmit Control Register */
1920         tctl = rd32(E1000_TCTL);
1921         tctl &= ~E1000_TCTL_CT;
1922         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1923                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1924
1925         igb_config_collision_dist(hw);
1926
1927         /* Setup Transmit Descriptor Settings for eop descriptor */
1928         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1929
1930         /* Enable transmits */
1931         tctl |= E1000_TCTL_EN;
1932
1933         wr32(E1000_TCTL, tctl);
1934 }
1935
1936 /**
1937  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1938  * @adapter: board private structure
1939  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1940  *
1941  * Returns 0 on success, negative on failure
1942  **/
1943 int igb_setup_rx_resources(struct igb_adapter *adapter,
1944                            struct igb_ring *rx_ring)
1945 {
1946         struct pci_dev *pdev = adapter->pdev;
1947         int size, desc_len;
1948
1949         size = sizeof(struct igb_buffer) * rx_ring->count;
1950         rx_ring->buffer_info = vmalloc(size);
1951         if (!rx_ring->buffer_info)
1952                 goto err;
1953         memset(rx_ring->buffer_info, 0, size);
1954
1955         desc_len = sizeof(union e1000_adv_rx_desc);
1956
1957         /* Round up to nearest 4K */
1958         rx_ring->size = rx_ring->count * desc_len;
1959         rx_ring->size = ALIGN(rx_ring->size, 4096);
1960
1961         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1962                                              &rx_ring->dma);
1963
1964         if (!rx_ring->desc)
1965                 goto err;
1966
1967         rx_ring->next_to_clean = 0;
1968         rx_ring->next_to_use = 0;
1969
1970         rx_ring->adapter = adapter;
1971
1972         return 0;
1973
1974 err:
1975         vfree(rx_ring->buffer_info);
1976         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1977                 "the receive descriptor ring\n");
1978         return -ENOMEM;
1979 }
1980
1981 /**
1982  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1983  *                                (Descriptors) for all queues
1984  * @adapter: board private structure
1985  *
1986  * Return 0 on success, negative on failure
1987  **/
1988 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1989 {
1990         int i, err = 0;
1991
1992         for (i = 0; i < adapter->num_rx_queues; i++) {
1993                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1994                 if (err) {
1995                         dev_err(&adapter->pdev->dev,
1996                                 "Allocation for Rx Queue %u failed\n", i);
1997                         for (i--; i >= 0; i--)
1998                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1999                         break;
2000                 }
2001         }
2002
2003         return err;
2004 }
2005
2006 /**
2007  * igb_setup_rctl - configure the receive control registers
2008  * @adapter: Board private structure
2009  **/
2010 static void igb_setup_rctl(struct igb_adapter *adapter)
2011 {
2012         struct e1000_hw *hw = &adapter->hw;
2013         u32 rctl;
2014         u32 srrctl = 0;
2015         int i;
2016
2017         rctl = rd32(E1000_RCTL);
2018
2019         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2020         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2021
2022         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2023                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2024
2025         /*
2026          * enable stripping of CRC. It's unlikely this will break BMC
2027          * redirection as it did with e1000. Newer features require
2028          * that the HW strips the CRC.
2029          */
2030         rctl |= E1000_RCTL_SECRC;
2031
2032         /*
2033          * disable store bad packets and clear size bits.
2034          */
2035         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2036
2037         /* enable LPE when to prevent packets larger than max_frame_size */
2038                 rctl |= E1000_RCTL_LPE;
2039
2040         /* Setup buffer sizes */
2041         switch (adapter->rx_buffer_len) {
2042         case IGB_RXBUFFER_256:
2043                 rctl |= E1000_RCTL_SZ_256;
2044                 break;
2045         case IGB_RXBUFFER_512:
2046                 rctl |= E1000_RCTL_SZ_512;
2047                 break;
2048         default:
2049                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2050                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2051                 break;
2052         }
2053
2054         /* 82575 and greater support packet-split where the protocol
2055          * header is placed in skb->data and the packet data is
2056          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2057          * In the case of a non-split, skb->data is linearly filled,
2058          * followed by the page buffers.  Therefore, skb->data is
2059          * sized to hold the largest protocol header.
2060          */
2061         /* allocations using alloc_page take too long for regular MTU
2062          * so only enable packet split for jumbo frames */
2063         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2064                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2065                 srrctl |= adapter->rx_ps_hdr_size <<
2066                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2067                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2068         } else {
2069                 adapter->rx_ps_hdr_size = 0;
2070                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2071         }
2072
2073         /* Attention!!!  For SR-IOV PF driver operations you must enable
2074          * queue drop for all VF and PF queues to prevent head of line blocking
2075          * if an un-trusted VF does not provide descriptors to hardware.
2076          */
2077         if (adapter->vfs_allocated_count) {
2078                 u32 vmolr;
2079
2080                 /* set all queue drop enable bits */
2081                 wr32(E1000_QDE, ALL_QUEUES);
2082                 srrctl |= E1000_SRRCTL_DROP_EN;
2083
2084                 /* disable queue 0 to prevent tail write w/o re-config */
2085                 wr32(E1000_RXDCTL(0), 0);
2086
2087                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2088                 if (rctl & E1000_RCTL_LPE)
2089                         vmolr |= E1000_VMOLR_LPE;
2090                 if (adapter->num_rx_queues > 1)
2091                         vmolr |= E1000_VMOLR_RSSE;
2092                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2093         }
2094
2095         for (i = 0; i < adapter->num_rx_queues; i++) {
2096                 int j = adapter->rx_ring[i].reg_idx;
2097                 wr32(E1000_SRRCTL(j), srrctl);
2098         }
2099
2100         wr32(E1000_RCTL, rctl);
2101 }
2102
2103 /**
2104  * igb_rlpml_set - set maximum receive packet size
2105  * @adapter: board private structure
2106  *
2107  * Configure maximum receivable packet size.
2108  **/
2109 static void igb_rlpml_set(struct igb_adapter *adapter)
2110 {
2111         u32 max_frame_size = adapter->max_frame_size;
2112         struct e1000_hw *hw = &adapter->hw;
2113         u16 pf_id = adapter->vfs_allocated_count;
2114
2115         if (adapter->vlgrp)
2116                 max_frame_size += VLAN_TAG_SIZE;
2117
2118         /* if vfs are enabled we set RLPML to the largest possible request
2119          * size and set the VMOLR RLPML to the size we need */
2120         if (pf_id) {
2121                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2122                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2123         }
2124
2125         wr32(E1000_RLPML, max_frame_size);
2126 }
2127
2128 /**
2129  * igb_configure_vt_default_pool - Configure VT default pool
2130  * @adapter: board private structure
2131  *
2132  * Configure the default pool
2133  **/
2134 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2135 {
2136         struct e1000_hw *hw = &adapter->hw;
2137         u16 pf_id = adapter->vfs_allocated_count;
2138         u32 vtctl;
2139
2140         /* not in sr-iov mode - do nothing */
2141         if (!pf_id)
2142                 return;
2143
2144         vtctl = rd32(E1000_VT_CTL);
2145         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2146                    E1000_VT_CTL_DISABLE_DEF_POOL);
2147         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2148         wr32(E1000_VT_CTL, vtctl);
2149 }
2150
2151 /**
2152  * igb_configure_rx - Configure receive Unit after Reset
2153  * @adapter: board private structure
2154  *
2155  * Configure the Rx unit of the MAC after a reset.
2156  **/
2157 static void igb_configure_rx(struct igb_adapter *adapter)
2158 {
2159         u64 rdba;
2160         struct e1000_hw *hw = &adapter->hw;
2161         u32 rctl, rxcsum;
2162         u32 rxdctl;
2163         int i;
2164
2165         /* disable receives while setting up the descriptors */
2166         rctl = rd32(E1000_RCTL);
2167         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2168         wrfl();
2169         mdelay(10);
2170
2171         if (adapter->itr_setting > 3)
2172                 wr32(E1000_ITR, adapter->itr);
2173
2174         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2175          * the Base and Length of the Rx Descriptor Ring */
2176         for (i = 0; i < adapter->num_rx_queues; i++) {
2177                 struct igb_ring *ring = &adapter->rx_ring[i];
2178                 int j = ring->reg_idx;
2179                 rdba = ring->dma;
2180                 wr32(E1000_RDBAL(j),
2181                      rdba & 0x00000000ffffffffULL);
2182                 wr32(E1000_RDBAH(j), rdba >> 32);
2183                 wr32(E1000_RDLEN(j),
2184                      ring->count * sizeof(union e1000_adv_rx_desc));
2185
2186                 ring->head = E1000_RDH(j);
2187                 ring->tail = E1000_RDT(j);
2188                 writel(0, hw->hw_addr + ring->tail);
2189                 writel(0, hw->hw_addr + ring->head);
2190
2191                 rxdctl = rd32(E1000_RXDCTL(j));
2192                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2193                 rxdctl &= 0xFFF00000;
2194                 rxdctl |= IGB_RX_PTHRESH;
2195                 rxdctl |= IGB_RX_HTHRESH << 8;
2196                 rxdctl |= IGB_RX_WTHRESH << 16;
2197                 wr32(E1000_RXDCTL(j), rxdctl);
2198         }
2199
2200         if (adapter->num_rx_queues > 1) {
2201                 u32 random[10];
2202                 u32 mrqc;
2203                 u32 j, shift;
2204                 union e1000_reta {
2205                         u32 dword;
2206                         u8  bytes[4];
2207                 } reta;
2208
2209                 get_random_bytes(&random[0], 40);
2210
2211                 if (hw->mac.type >= e1000_82576)
2212                         shift = 0;
2213                 else
2214                         shift = 6;
2215                 for (j = 0; j < (32 * 4); j++) {
2216                         reta.bytes[j & 3] =
2217                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2218                         if ((j & 3) == 3)
2219                                 writel(reta.dword,
2220                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2221                 }
2222                 if (adapter->vfs_allocated_count)
2223                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2224                 else
2225                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2226
2227                 /* Fill out hash function seeds */
2228                 for (j = 0; j < 10; j++)
2229                         array_wr32(E1000_RSSRK(0), j, random[j]);
2230
2231                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2232                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2233                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2234                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2235                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2236                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2237                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2238                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2239
2240                 wr32(E1000_MRQC, mrqc);
2241         } else if (adapter->vfs_allocated_count) {
2242                 /* Enable multi-queue for sr-iov */
2243                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2244         }
2245
2246         /* Enable Receive Checksum Offload for TCP and UDP */
2247         rxcsum = rd32(E1000_RXCSUM);
2248         /* Disable raw packet checksumming */
2249         rxcsum |= E1000_RXCSUM_PCSD;
2250
2251         if (adapter->hw.mac.type == e1000_82576)
2252                 /* Enable Receive Checksum Offload for SCTP */
2253                 rxcsum |= E1000_RXCSUM_CRCOFL;
2254
2255         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2256         wr32(E1000_RXCSUM, rxcsum);
2257
2258         /* Set the default pool for the PF's first queue */
2259         igb_configure_vt_default_pool(adapter);
2260
2261         igb_rlpml_set(adapter);
2262
2263         /* Enable Receives */
2264         wr32(E1000_RCTL, rctl);
2265 }
2266
2267 /**
2268  * igb_free_tx_resources - Free Tx Resources per Queue
2269  * @tx_ring: Tx descriptor ring for a specific queue
2270  *
2271  * Free all transmit software resources
2272  **/
2273 void igb_free_tx_resources(struct igb_ring *tx_ring)
2274 {
2275         struct pci_dev *pdev = tx_ring->adapter->pdev;
2276
2277         igb_clean_tx_ring(tx_ring);
2278
2279         vfree(tx_ring->buffer_info);
2280         tx_ring->buffer_info = NULL;
2281
2282         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2283
2284         tx_ring->desc = NULL;
2285 }
2286
2287 /**
2288  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2289  * @adapter: board private structure
2290  *
2291  * Free all transmit software resources
2292  **/
2293 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2294 {
2295         int i;
2296
2297         for (i = 0; i < adapter->num_tx_queues; i++)
2298                 igb_free_tx_resources(&adapter->tx_ring[i]);
2299 }
2300
2301 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2302                                            struct igb_buffer *buffer_info)
2303 {
2304         buffer_info->dma = 0;
2305         if (buffer_info->skb) {
2306                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2307                               DMA_TO_DEVICE);
2308                 dev_kfree_skb_any(buffer_info->skb);
2309                 buffer_info->skb = NULL;
2310         }
2311         buffer_info->time_stamp = 0;
2312         /* buffer_info must be completely set up in the transmit path */
2313 }
2314
2315 /**
2316  * igb_clean_tx_ring - Free Tx Buffers
2317  * @tx_ring: ring to be cleaned
2318  **/
2319 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2320 {
2321         struct igb_adapter *adapter = tx_ring->adapter;
2322         struct igb_buffer *buffer_info;
2323         unsigned long size;
2324         unsigned int i;
2325
2326         if (!tx_ring->buffer_info)
2327                 return;
2328         /* Free all the Tx ring sk_buffs */
2329
2330         for (i = 0; i < tx_ring->count; i++) {
2331                 buffer_info = &tx_ring->buffer_info[i];
2332                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2333         }
2334
2335         size = sizeof(struct igb_buffer) * tx_ring->count;
2336         memset(tx_ring->buffer_info, 0, size);
2337
2338         /* Zero out the descriptor ring */
2339
2340         memset(tx_ring->desc, 0, tx_ring->size);
2341
2342         tx_ring->next_to_use = 0;
2343         tx_ring->next_to_clean = 0;
2344
2345         writel(0, adapter->hw.hw_addr + tx_ring->head);
2346         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2347 }
2348
2349 /**
2350  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2351  * @adapter: board private structure
2352  **/
2353 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2354 {
2355         int i;
2356
2357         for (i = 0; i < adapter->num_tx_queues; i++)
2358                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2359 }
2360
2361 /**
2362  * igb_free_rx_resources - Free Rx Resources
2363  * @rx_ring: ring to clean the resources from
2364  *
2365  * Free all receive software resources
2366  **/
2367 void igb_free_rx_resources(struct igb_ring *rx_ring)
2368 {
2369         struct pci_dev *pdev = rx_ring->adapter->pdev;
2370
2371         igb_clean_rx_ring(rx_ring);
2372
2373         vfree(rx_ring->buffer_info);
2374         rx_ring->buffer_info = NULL;
2375
2376         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2377
2378         rx_ring->desc = NULL;
2379 }
2380
2381 /**
2382  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2383  * @adapter: board private structure
2384  *
2385  * Free all receive software resources
2386  **/
2387 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2388 {
2389         int i;
2390
2391         for (i = 0; i < adapter->num_rx_queues; i++)
2392                 igb_free_rx_resources(&adapter->rx_ring[i]);
2393 }
2394
2395 /**
2396  * igb_clean_rx_ring - Free Rx Buffers per Queue
2397  * @rx_ring: ring to free buffers from
2398  **/
2399 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2400 {
2401         struct igb_adapter *adapter = rx_ring->adapter;
2402         struct igb_buffer *buffer_info;
2403         struct pci_dev *pdev = adapter->pdev;
2404         unsigned long size;
2405         unsigned int i;
2406
2407         if (!rx_ring->buffer_info)
2408                 return;
2409         /* Free all the Rx ring sk_buffs */
2410         for (i = 0; i < rx_ring->count; i++) {
2411                 buffer_info = &rx_ring->buffer_info[i];
2412                 if (buffer_info->dma) {
2413                         if (adapter->rx_ps_hdr_size)
2414                                 pci_unmap_single(pdev, buffer_info->dma,
2415                                                  adapter->rx_ps_hdr_size,
2416                                                  PCI_DMA_FROMDEVICE);
2417                         else
2418                                 pci_unmap_single(pdev, buffer_info->dma,
2419                                                  adapter->rx_buffer_len,
2420                                                  PCI_DMA_FROMDEVICE);
2421                         buffer_info->dma = 0;
2422                 }
2423
2424                 if (buffer_info->skb) {
2425                         dev_kfree_skb(buffer_info->skb);
2426                         buffer_info->skb = NULL;
2427                 }
2428                 if (buffer_info->page) {
2429                         if (buffer_info->page_dma)
2430                                 pci_unmap_page(pdev, buffer_info->page_dma,
2431                                                PAGE_SIZE / 2,
2432                                                PCI_DMA_FROMDEVICE);
2433                         put_page(buffer_info->page);
2434                         buffer_info->page = NULL;
2435                         buffer_info->page_dma = 0;
2436                         buffer_info->page_offset = 0;
2437                 }
2438         }
2439
2440         size = sizeof(struct igb_buffer) * rx_ring->count;
2441         memset(rx_ring->buffer_info, 0, size);
2442
2443         /* Zero out the descriptor ring */
2444         memset(rx_ring->desc, 0, rx_ring->size);
2445
2446         rx_ring->next_to_clean = 0;
2447         rx_ring->next_to_use = 0;
2448
2449         writel(0, adapter->hw.hw_addr + rx_ring->head);
2450         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2451 }
2452
2453 /**
2454  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2455  * @adapter: board private structure
2456  **/
2457 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2458 {
2459         int i;
2460
2461         for (i = 0; i < adapter->num_rx_queues; i++)
2462                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2463 }
2464
2465 /**
2466  * igb_set_mac - Change the Ethernet Address of the NIC
2467  * @netdev: network interface device structure
2468  * @p: pointer to an address structure
2469  *
2470  * Returns 0 on success, negative on failure
2471  **/
2472 static int igb_set_mac(struct net_device *netdev, void *p)
2473 {
2474         struct igb_adapter *adapter = netdev_priv(netdev);
2475         struct e1000_hw *hw = &adapter->hw;
2476         struct sockaddr *addr = p;
2477
2478         if (!is_valid_ether_addr(addr->sa_data))
2479                 return -EADDRNOTAVAIL;
2480
2481         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2482         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2483
2484         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2485
2486         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2487
2488         return 0;
2489 }
2490
2491 /**
2492  * igb_set_multi - Multicast and Promiscuous mode set
2493  * @netdev: network interface device structure
2494  *
2495  * The set_multi entry point is called whenever the multicast address
2496  * list or the network interface flags are updated.  This routine is
2497  * responsible for configuring the hardware for proper multicast,
2498  * promiscuous mode, and all-multi behavior.
2499  **/
2500 static void igb_set_multi(struct net_device *netdev)
2501 {
2502         struct igb_adapter *adapter = netdev_priv(netdev);
2503         struct e1000_hw *hw = &adapter->hw;
2504         struct e1000_mac_info *mac = &hw->mac;
2505         struct dev_mc_list *mc_ptr;
2506         u8  *mta_list = NULL;
2507         u32 rctl;
2508         int i;
2509
2510         /* Check for Promiscuous and All Multicast modes */
2511
2512         rctl = rd32(E1000_RCTL);
2513
2514         if (netdev->flags & IFF_PROMISC) {
2515                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2516                 rctl &= ~E1000_RCTL_VFE;
2517         } else {
2518                 if (netdev->flags & IFF_ALLMULTI) {
2519                         rctl |= E1000_RCTL_MPE;
2520                         rctl &= ~E1000_RCTL_UPE;
2521                 } else
2522                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2523                 rctl |= E1000_RCTL_VFE;
2524         }
2525         wr32(E1000_RCTL, rctl);
2526
2527         if (netdev->mc_count) {
2528                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2529                 if (!mta_list) {
2530                         dev_err(&adapter->pdev->dev,
2531                                 "failed to allocate multicast filter list\n");
2532                         return;
2533                 }
2534         }
2535
2536         /* The shared function expects a packed array of only addresses. */
2537         mc_ptr = netdev->mc_list;
2538
2539         for (i = 0; i < netdev->mc_count; i++) {
2540                 if (!mc_ptr)
2541                         break;
2542                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2543                 mc_ptr = mc_ptr->next;
2544         }
2545         igb_update_mc_addr_list(hw, mta_list, i,
2546                                 adapter->vfs_allocated_count + 1,
2547                                 mac->rar_entry_count);
2548
2549         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2550         igb_restore_vf_multicasts(adapter);
2551
2552         kfree(mta_list);
2553 }
2554
2555 /* Need to wait a few seconds after link up to get diagnostic information from
2556  * the phy */
2557 static void igb_update_phy_info(unsigned long data)
2558 {
2559         struct igb_adapter *adapter = (struct igb_adapter *) data;
2560         igb_get_phy_info(&adapter->hw);
2561 }
2562
2563 /**
2564  * igb_has_link - check shared code for link and determine up/down
2565  * @adapter: pointer to driver private info
2566  **/
2567 static bool igb_has_link(struct igb_adapter *adapter)
2568 {
2569         struct e1000_hw *hw = &adapter->hw;
2570         bool link_active = false;
2571         s32 ret_val = 0;
2572
2573         /* get_link_status is set on LSC (link status) interrupt or
2574          * rx sequence error interrupt.  get_link_status will stay
2575          * false until the e1000_check_for_link establishes link
2576          * for copper adapters ONLY
2577          */
2578         switch (hw->phy.media_type) {
2579         case e1000_media_type_copper:
2580                 if (hw->mac.get_link_status) {
2581                         ret_val = hw->mac.ops.check_for_link(hw);
2582                         link_active = !hw->mac.get_link_status;
2583                 } else {
2584                         link_active = true;
2585                 }
2586                 break;
2587         case e1000_media_type_fiber:
2588                 ret_val = hw->mac.ops.check_for_link(hw);
2589                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2590                 break;
2591         case e1000_media_type_internal_serdes:
2592                 ret_val = hw->mac.ops.check_for_link(hw);
2593                 link_active = hw->mac.serdes_has_link;
2594                 break;
2595         default:
2596         case e1000_media_type_unknown:
2597                 break;
2598         }
2599
2600         return link_active;
2601 }
2602
2603 /**
2604  * igb_watchdog - Timer Call-back
2605  * @data: pointer to adapter cast into an unsigned long
2606  **/
2607 static void igb_watchdog(unsigned long data)
2608 {
2609         struct igb_adapter *adapter = (struct igb_adapter *)data;
2610         /* Do the rest outside of interrupt context */
2611         schedule_work(&adapter->watchdog_task);
2612 }
2613
2614 static void igb_watchdog_task(struct work_struct *work)
2615 {
2616         struct igb_adapter *adapter = container_of(work,
2617                                         struct igb_adapter, watchdog_task);
2618         struct e1000_hw *hw = &adapter->hw;
2619         struct net_device *netdev = adapter->netdev;
2620         struct igb_ring *tx_ring = adapter->tx_ring;
2621         u32 link;
2622         u32 eics = 0;
2623         int i;
2624
2625         link = igb_has_link(adapter);
2626         if ((netif_carrier_ok(netdev)) && link)
2627                 goto link_up;
2628
2629         if (link) {
2630                 if (!netif_carrier_ok(netdev)) {
2631                         u32 ctrl;
2632                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2633                                                    &adapter->link_speed,
2634                                                    &adapter->link_duplex);
2635
2636                         ctrl = rd32(E1000_CTRL);
2637                         /* Links status message must follow this format */
2638                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2639                                  "Flow Control: %s\n",
2640                                  netdev->name,
2641                                  adapter->link_speed,
2642                                  adapter->link_duplex == FULL_DUPLEX ?
2643                                  "Full Duplex" : "Half Duplex",
2644                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2645                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2646                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2647                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2648
2649                         /* tweak tx_queue_len according to speed/duplex and
2650                          * adjust the timeout factor */
2651                         netdev->tx_queue_len = adapter->tx_queue_len;
2652                         adapter->tx_timeout_factor = 1;
2653                         switch (adapter->link_speed) {
2654                         case SPEED_10:
2655                                 netdev->tx_queue_len = 10;
2656                                 adapter->tx_timeout_factor = 14;
2657                                 break;
2658                         case SPEED_100:
2659                                 netdev->tx_queue_len = 100;
2660                                 /* maybe add some timeout factor ? */
2661                                 break;
2662                         }
2663
2664                         netif_carrier_on(netdev);
2665
2666                         igb_ping_all_vfs(adapter);
2667
2668                         /* link state has changed, schedule phy info update */
2669                         if (!test_bit(__IGB_DOWN, &adapter->state))
2670                                 mod_timer(&adapter->phy_info_timer,
2671                                           round_jiffies(jiffies + 2 * HZ));
2672                 }
2673         } else {
2674                 if (netif_carrier_ok(netdev)) {
2675                         adapter->link_speed = 0;
2676                         adapter->link_duplex = 0;
2677                         /* Links status message must follow this format */
2678                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2679                                netdev->name);
2680                         netif_carrier_off(netdev);
2681
2682                         igb_ping_all_vfs(adapter);
2683
2684                         /* link state has changed, schedule phy info update */
2685                         if (!test_bit(__IGB_DOWN, &adapter->state))
2686                                 mod_timer(&adapter->phy_info_timer,
2687                                           round_jiffies(jiffies + 2 * HZ));
2688                 }
2689         }
2690
2691 link_up:
2692         igb_update_stats(adapter);
2693
2694         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2695         adapter->tpt_old = adapter->stats.tpt;
2696         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2697         adapter->colc_old = adapter->stats.colc;
2698
2699         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2700         adapter->gorc_old = adapter->stats.gorc;
2701         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2702         adapter->gotc_old = adapter->stats.gotc;
2703
2704         igb_update_adaptive(&adapter->hw);
2705
2706         if (!netif_carrier_ok(netdev)) {
2707                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2708                         /* We've lost link, so the controller stops DMA,
2709                          * but we've got queued Tx work that's never going
2710                          * to get done, so reset controller to flush Tx.
2711                          * (Do the reset outside of interrupt context). */
2712                         adapter->tx_timeout_count++;
2713                         schedule_work(&adapter->reset_task);
2714                         /* return immediately since reset is imminent */
2715                         return;
2716                 }
2717         }
2718
2719         /* Cause software interrupt to ensure rx ring is cleaned */
2720         if (adapter->msix_entries) {
2721                 for (i = 0; i < adapter->num_rx_queues; i++)
2722                         eics |= adapter->rx_ring[i].eims_value;
2723                 wr32(E1000_EICS, eics);
2724         } else {
2725                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2726         }
2727
2728         /* Force detection of hung controller every watchdog period */
2729         tx_ring->detect_tx_hung = true;
2730
2731         /* Reset the timer */
2732         if (!test_bit(__IGB_DOWN, &adapter->state))
2733                 mod_timer(&adapter->watchdog_timer,
2734                           round_jiffies(jiffies + 2 * HZ));
2735 }
2736
2737 enum latency_range {
2738         lowest_latency = 0,
2739         low_latency = 1,
2740         bulk_latency = 2,
2741         latency_invalid = 255
2742 };
2743
2744
2745 /**
2746  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2747  *
2748  *      Stores a new ITR value based on strictly on packet size.  This
2749  *      algorithm is less sophisticated than that used in igb_update_itr,
2750  *      due to the difficulty of synchronizing statistics across multiple
2751  *      receive rings.  The divisors and thresholds used by this fuction
2752  *      were determined based on theoretical maximum wire speed and testing
2753  *      data, in order to minimize response time while increasing bulk
2754  *      throughput.
2755  *      This functionality is controlled by the InterruptThrottleRate module
2756  *      parameter (see igb_param.c)
2757  *      NOTE:  This function is called only when operating in a multiqueue
2758  *             receive environment.
2759  * @rx_ring: pointer to ring
2760  **/
2761 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2762 {
2763         int new_val = rx_ring->itr_val;
2764         int avg_wire_size = 0;
2765         struct igb_adapter *adapter = rx_ring->adapter;
2766
2767         if (!rx_ring->total_packets)
2768                 goto clear_counts; /* no packets, so don't do anything */
2769
2770         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2771          * ints/sec - ITR timer value of 120 ticks.
2772          */
2773         if (adapter->link_speed != SPEED_1000) {
2774                 new_val = 120;
2775                 goto set_itr_val;
2776         }
2777         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2778
2779         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2780         avg_wire_size += 24;
2781
2782         /* Don't starve jumbo frames */
2783         avg_wire_size = min(avg_wire_size, 3000);
2784
2785         /* Give a little boost to mid-size frames */
2786         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2787                 new_val = avg_wire_size / 3;
2788         else
2789                 new_val = avg_wire_size / 2;
2790
2791 set_itr_val:
2792         if (new_val != rx_ring->itr_val) {
2793                 rx_ring->itr_val = new_val;
2794                 rx_ring->set_itr = 1;
2795         }
2796 clear_counts:
2797         rx_ring->total_bytes = 0;
2798         rx_ring->total_packets = 0;
2799 }
2800
2801 /**
2802  * igb_update_itr - update the dynamic ITR value based on statistics
2803  *      Stores a new ITR value based on packets and byte
2804  *      counts during the last interrupt.  The advantage of per interrupt
2805  *      computation is faster updates and more accurate ITR for the current
2806  *      traffic pattern.  Constants in this function were computed
2807  *      based on theoretical maximum wire speed and thresholds were set based
2808  *      on testing data as well as attempting to minimize response time
2809  *      while increasing bulk throughput.
2810  *      this functionality is controlled by the InterruptThrottleRate module
2811  *      parameter (see igb_param.c)
2812  *      NOTE:  These calculations are only valid when operating in a single-
2813  *             queue environment.
2814  * @adapter: pointer to adapter
2815  * @itr_setting: current adapter->itr
2816  * @packets: the number of packets during this measurement interval
2817  * @bytes: the number of bytes during this measurement interval
2818  **/
2819 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2820                                    int packets, int bytes)
2821 {
2822         unsigned int retval = itr_setting;
2823
2824         if (packets == 0)
2825                 goto update_itr_done;
2826
2827         switch (itr_setting) {
2828         case lowest_latency:
2829                 /* handle TSO and jumbo frames */
2830                 if (bytes/packets > 8000)
2831                         retval = bulk_latency;
2832                 else if ((packets < 5) && (bytes > 512))
2833                         retval = low_latency;
2834                 break;
2835         case low_latency:  /* 50 usec aka 20000 ints/s */
2836                 if (bytes > 10000) {
2837                         /* this if handles the TSO accounting */
2838                         if (bytes/packets > 8000) {
2839                                 retval = bulk_latency;
2840                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2841                                 retval = bulk_latency;
2842                         } else if ((packets > 35)) {
2843                                 retval = lowest_latency;
2844                         }
2845                 } else if (bytes/packets > 2000) {
2846                         retval = bulk_latency;
2847                 } else if (packets <= 2 && bytes < 512) {
2848                         retval = lowest_latency;
2849                 }
2850                 break;
2851         case bulk_latency: /* 250 usec aka 4000 ints/s */
2852                 if (bytes > 25000) {
2853                         if (packets > 35)
2854                                 retval = low_latency;
2855                 } else if (bytes < 1500) {
2856                         retval = low_latency;
2857                 }
2858                 break;
2859         }
2860
2861 update_itr_done:
2862         return retval;
2863 }
2864
2865 static void igb_set_itr(struct igb_adapter *adapter)
2866 {
2867         u16 current_itr;
2868         u32 new_itr = adapter->itr;
2869
2870         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2871         if (adapter->link_speed != SPEED_1000) {
2872                 current_itr = 0;
2873                 new_itr = 4000;
2874                 goto set_itr_now;
2875         }
2876
2877         adapter->rx_itr = igb_update_itr(adapter,
2878                                     adapter->rx_itr,
2879                                     adapter->rx_ring->total_packets,
2880                                     adapter->rx_ring->total_bytes);
2881
2882         if (adapter->rx_ring->buddy) {
2883                 adapter->tx_itr = igb_update_itr(adapter,
2884                                             adapter->tx_itr,
2885                                             adapter->tx_ring->total_packets,
2886                                             adapter->tx_ring->total_bytes);
2887                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2888         } else {
2889                 current_itr = adapter->rx_itr;
2890         }
2891
2892         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2893         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2894                 current_itr = low_latency;
2895
2896         switch (current_itr) {
2897         /* counts and packets in update_itr are dependent on these numbers */
2898         case lowest_latency:
2899                 new_itr = 56;  /* aka 70,000 ints/sec */
2900                 break;
2901         case low_latency:
2902                 new_itr = 196; /* aka 20,000 ints/sec */
2903                 break;
2904         case bulk_latency:
2905                 new_itr = 980; /* aka 4,000 ints/sec */
2906                 break;
2907         default:
2908                 break;
2909         }
2910
2911 set_itr_now:
2912         adapter->rx_ring->total_bytes = 0;
2913         adapter->rx_ring->total_packets = 0;
2914         if (adapter->rx_ring->buddy) {
2915                 adapter->rx_ring->buddy->total_bytes = 0;
2916                 adapter->rx_ring->buddy->total_packets = 0;
2917         }
2918
2919         if (new_itr != adapter->itr) {
2920                 /* this attempts to bias the interrupt rate towards Bulk
2921                  * by adding intermediate steps when interrupt rate is
2922                  * increasing */
2923                 new_itr = new_itr > adapter->itr ?
2924                              max((new_itr * adapter->itr) /
2925                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2926                              new_itr;
2927                 /* Don't write the value here; it resets the adapter's
2928                  * internal timer, and causes us to delay far longer than
2929                  * we should between interrupts.  Instead, we write the ITR
2930                  * value at the beginning of the next interrupt so the timing
2931                  * ends up being correct.
2932                  */
2933                 adapter->itr = new_itr;
2934                 adapter->rx_ring->itr_val = new_itr;
2935                 adapter->rx_ring->set_itr = 1;
2936         }
2937
2938         return;
2939 }
2940
2941
2942 #define IGB_TX_FLAGS_CSUM               0x00000001
2943 #define IGB_TX_FLAGS_VLAN               0x00000002
2944 #define IGB_TX_FLAGS_TSO                0x00000004
2945 #define IGB_TX_FLAGS_IPV4               0x00000008
2946 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2947 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2948 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2949
2950 static inline int igb_tso_adv(struct igb_adapter *adapter,
2951                               struct igb_ring *tx_ring,
2952                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2953 {
2954         struct e1000_adv_tx_context_desc *context_desc;
2955         unsigned int i;
2956         int err;
2957         struct igb_buffer *buffer_info;
2958         u32 info = 0, tu_cmd = 0;
2959         u32 mss_l4len_idx, l4len;
2960         *hdr_len = 0;
2961
2962         if (skb_header_cloned(skb)) {
2963                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2964                 if (err)
2965                         return err;
2966         }
2967
2968         l4len = tcp_hdrlen(skb);
2969         *hdr_len += l4len;
2970
2971         if (skb->protocol == htons(ETH_P_IP)) {
2972                 struct iphdr *iph = ip_hdr(skb);
2973                 iph->tot_len = 0;
2974                 iph->check = 0;
2975                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2976                                                          iph->daddr, 0,
2977                                                          IPPROTO_TCP,
2978                                                          0);
2979         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2980                 ipv6_hdr(skb)->payload_len = 0;
2981                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2982                                                        &ipv6_hdr(skb)->daddr,
2983                                                        0, IPPROTO_TCP, 0);
2984         }
2985
2986         i = tx_ring->next_to_use;
2987
2988         buffer_info = &tx_ring->buffer_info[i];
2989         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2990         /* VLAN MACLEN IPLEN */
2991         if (tx_flags & IGB_TX_FLAGS_VLAN)
2992                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2993         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2994         *hdr_len += skb_network_offset(skb);
2995         info |= skb_network_header_len(skb);
2996         *hdr_len += skb_network_header_len(skb);
2997         context_desc->vlan_macip_lens = cpu_to_le32(info);
2998
2999         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3000         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3001
3002         if (skb->protocol == htons(ETH_P_IP))
3003                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3004         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3005
3006         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3007
3008         /* MSS L4LEN IDX */
3009         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3010         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3011
3012         /* For 82575, context index must be unique per ring. */
3013         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3014                 mss_l4len_idx |= tx_ring->queue_index << 4;
3015
3016         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3017         context_desc->seqnum_seed = 0;
3018
3019         buffer_info->time_stamp = jiffies;
3020         buffer_info->next_to_watch = i;
3021         buffer_info->dma = 0;
3022         i++;
3023         if (i == tx_ring->count)
3024                 i = 0;
3025
3026         tx_ring->next_to_use = i;
3027
3028         return true;
3029 }
3030
3031 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3032                                         struct igb_ring *tx_ring,
3033                                         struct sk_buff *skb, u32 tx_flags)
3034 {
3035         struct e1000_adv_tx_context_desc *context_desc;
3036         unsigned int i;
3037         struct igb_buffer *buffer_info;
3038         u32 info = 0, tu_cmd = 0;
3039
3040         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3041             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3042                 i = tx_ring->next_to_use;
3043                 buffer_info = &tx_ring->buffer_info[i];
3044                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3045
3046                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3047                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3048                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3049                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3050                         info |= skb_network_header_len(skb);
3051
3052                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3053
3054                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3055
3056                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3057                         __be16 protocol;
3058
3059                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3060                                 const struct vlan_ethhdr *vhdr =
3061                                           (const struct vlan_ethhdr*)skb->data;
3062
3063                                 protocol = vhdr->h_vlan_encapsulated_proto;
3064                         } else {
3065                                 protocol = skb->protocol;
3066                         }
3067
3068                         switch (protocol) {
3069                         case cpu_to_be16(ETH_P_IP):
3070                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3071                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3072                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3073                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3074                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3075                                 break;
3076                         case cpu_to_be16(ETH_P_IPV6):
3077                                 /* XXX what about other V6 headers?? */
3078                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3079                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3080                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3081                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3082                                 break;
3083                         default:
3084                                 if (unlikely(net_ratelimit()))
3085                                         dev_warn(&adapter->pdev->dev,
3086                                             "partial checksum but proto=%x!\n",
3087                                             skb->protocol);
3088                                 break;
3089                         }
3090                 }
3091
3092                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3093                 context_desc->seqnum_seed = 0;
3094                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3095                         context_desc->mss_l4len_idx =
3096                                 cpu_to_le32(tx_ring->queue_index << 4);
3097                 else
3098                         context_desc->mss_l4len_idx = 0;
3099
3100                 buffer_info->time_stamp = jiffies;
3101                 buffer_info->next_to_watch = i;
3102                 buffer_info->dma = 0;
3103
3104                 i++;
3105                 if (i == tx_ring->count)
3106                         i = 0;
3107                 tx_ring->next_to_use = i;
3108
3109                 return true;
3110         }
3111         return false;
3112 }
3113
3114 #define IGB_MAX_TXD_PWR 16
3115 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3116
3117 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3118                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3119                                  unsigned int first)
3120 {
3121         struct igb_buffer *buffer_info;
3122         unsigned int len = skb_headlen(skb);
3123         unsigned int count = 0, i;
3124         unsigned int f;
3125         dma_addr_t *map;
3126
3127         i = tx_ring->next_to_use;
3128
3129         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3130                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3131                 return 0;
3132         }
3133
3134         map = skb_shinfo(skb)->dma_maps;
3135
3136         buffer_info = &tx_ring->buffer_info[i];
3137         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3138         buffer_info->length = len;
3139         /* set time_stamp *before* dma to help avoid a possible race */
3140         buffer_info->time_stamp = jiffies;
3141         buffer_info->next_to_watch = i;
3142         buffer_info->dma = skb_shinfo(skb)->dma_head;
3143
3144         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3145                 struct skb_frag_struct *frag;
3146
3147                 i++;
3148                 if (i == tx_ring->count)
3149                         i = 0;
3150
3151                 frag = &skb_shinfo(skb)->frags[f];
3152                 len = frag->size;
3153
3154                 buffer_info = &tx_ring->buffer_info[i];
3155                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3156                 buffer_info->length = len;
3157                 buffer_info->time_stamp = jiffies;
3158                 buffer_info->next_to_watch = i;
3159                 buffer_info->dma = map[count];
3160                 count++;
3161         }
3162
3163         tx_ring->buffer_info[i].skb = skb;
3164         tx_ring->buffer_info[first].next_to_watch = i;
3165
3166         return count + 1;
3167 }
3168
3169 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3170                                     struct igb_ring *tx_ring,
3171                                     int tx_flags, int count, u32 paylen,
3172                                     u8 hdr_len)
3173 {
3174         union e1000_adv_tx_desc *tx_desc = NULL;
3175         struct igb_buffer *buffer_info;
3176         u32 olinfo_status = 0, cmd_type_len;
3177         unsigned int i;
3178
3179         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3180                         E1000_ADVTXD_DCMD_DEXT);
3181
3182         if (tx_flags & IGB_TX_FLAGS_VLAN)
3183                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3184
3185         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3186                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3187
3188         if (tx_flags & IGB_TX_FLAGS_TSO) {
3189                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3190
3191                 /* insert tcp checksum */
3192                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3193
3194                 /* insert ip checksum */
3195                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3196                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3197
3198         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3199                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3200         }
3201
3202         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3203             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3204                          IGB_TX_FLAGS_VLAN)))
3205                 olinfo_status |= tx_ring->queue_index << 4;
3206
3207         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3208
3209         i = tx_ring->next_to_use;
3210         while (count--) {
3211                 buffer_info = &tx_ring->buffer_info[i];
3212                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3213                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3214                 tx_desc->read.cmd_type_len =
3215                         cpu_to_le32(cmd_type_len | buffer_info->length);
3216                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3217                 i++;
3218                 if (i == tx_ring->count)
3219                         i = 0;
3220         }
3221
3222         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3223         /* Force memory writes to complete before letting h/w
3224          * know there are new descriptors to fetch.  (Only
3225          * applicable for weak-ordered memory model archs,
3226          * such as IA-64). */
3227         wmb();
3228
3229         tx_ring->next_to_use = i;
3230         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3231         /* we need this if more than one processor can write to our tail
3232          * at a time, it syncronizes IO on IA64/Altix systems */
3233         mmiowb();
3234 }
3235
3236 static int __igb_maybe_stop_tx(struct net_device *netdev,
3237                                struct igb_ring *tx_ring, int size)
3238 {
3239         struct igb_adapter *adapter = netdev_priv(netdev);
3240
3241         netif_stop_subqueue(netdev, tx_ring->queue_index);
3242
3243         /* Herbert's original patch had:
3244          *  smp_mb__after_netif_stop_queue();
3245          * but since that doesn't exist yet, just open code it. */
3246         smp_mb();
3247
3248         /* We need to check again in a case another CPU has just
3249          * made room available. */
3250         if (igb_desc_unused(tx_ring) < size)
3251                 return -EBUSY;
3252
3253         /* A reprieve! */
3254         netif_wake_subqueue(netdev, tx_ring->queue_index);
3255         ++adapter->restart_queue;
3256         return 0;
3257 }
3258
3259 static int igb_maybe_stop_tx(struct net_device *netdev,
3260                              struct igb_ring *tx_ring, int size)
3261 {
3262         if (igb_desc_unused(tx_ring) >= size)
3263                 return 0;
3264         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3265 }
3266
3267 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3268                                    struct net_device *netdev,
3269                                    struct igb_ring *tx_ring)
3270 {
3271         struct igb_adapter *adapter = netdev_priv(netdev);
3272         unsigned int first;
3273         unsigned int tx_flags = 0;
3274         u8 hdr_len = 0;
3275         int count = 0;
3276         int tso = 0;
3277         union skb_shared_tx *shtx;
3278
3279         if (test_bit(__IGB_DOWN, &adapter->state)) {
3280                 dev_kfree_skb_any(skb);
3281                 return NETDEV_TX_OK;
3282         }
3283
3284         if (skb->len <= 0) {
3285                 dev_kfree_skb_any(skb);
3286                 return NETDEV_TX_OK;
3287         }
3288
3289         /* need: 1 descriptor per page,
3290          *       + 2 desc gap to keep tail from touching head,
3291          *       + 1 desc for skb->data,
3292          *       + 1 desc for context descriptor,
3293          * otherwise try next time */
3294         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3295                 /* this is a hard error */
3296                 return NETDEV_TX_BUSY;
3297         }
3298
3299         /*
3300          * TODO: check that there currently is no other packet with
3301          * time stamping in the queue
3302          *
3303          * When doing time stamping, keep the connection to the socket
3304          * a while longer: it is still needed by skb_hwtstamp_tx(),
3305          * called either in igb_tx_hwtstamp() or by our caller when
3306          * doing software time stamping.
3307          */
3308         shtx = skb_tx(skb);
3309         if (unlikely(shtx->hardware)) {
3310                 shtx->in_progress = 1;
3311                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3312         }
3313
3314         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3315                 tx_flags |= IGB_TX_FLAGS_VLAN;
3316                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3317         }
3318
3319         if (skb->protocol == htons(ETH_P_IP))
3320                 tx_flags |= IGB_TX_FLAGS_IPV4;
3321
3322         first = tx_ring->next_to_use;
3323         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3324                                               &hdr_len) : 0;
3325
3326         if (tso < 0) {
3327                 dev_kfree_skb_any(skb);
3328                 return NETDEV_TX_OK;
3329         }
3330
3331         if (tso)
3332                 tx_flags |= IGB_TX_FLAGS_TSO;
3333         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3334                  (skb->ip_summed == CHECKSUM_PARTIAL))
3335                 tx_flags |= IGB_TX_FLAGS_CSUM;
3336
3337         /*
3338          * count reflects descriptors mapped, if 0 then mapping error
3339          * has occured and we need to rewind the descriptor queue
3340          */
3341         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3342
3343         if (count) {
3344                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3345                                  skb->len, hdr_len);
3346                 /* Make sure there is space in the ring for the next send. */
3347                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3348         } else {
3349                 dev_kfree_skb_any(skb);
3350                 tx_ring->buffer_info[first].time_stamp = 0;
3351                 tx_ring->next_to_use = first;
3352         }
3353
3354         return NETDEV_TX_OK;
3355 }
3356
3357 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3358 {
3359         struct igb_adapter *adapter = netdev_priv(netdev);
3360         struct igb_ring *tx_ring;
3361
3362         int r_idx = 0;
3363         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3364         tx_ring = adapter->multi_tx_table[r_idx];
3365
3366         /* This goes back to the question of how to logically map a tx queue
3367          * to a flow.  Right now, performance is impacted slightly negatively
3368          * if using multiple tx queues.  If the stack breaks away from a
3369          * single qdisc implementation, we can look at this again. */
3370         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3371 }
3372
3373 /**
3374  * igb_tx_timeout - Respond to a Tx Hang
3375  * @netdev: network interface device structure
3376  **/
3377 static void igb_tx_timeout(struct net_device *netdev)
3378 {
3379         struct igb_adapter *adapter = netdev_priv(netdev);
3380         struct e1000_hw *hw = &adapter->hw;
3381
3382         /* Do the reset outside of interrupt context */
3383         adapter->tx_timeout_count++;
3384         schedule_work(&adapter->reset_task);
3385         wr32(E1000_EICS,
3386              (adapter->eims_enable_mask & ~adapter->eims_other));
3387 }
3388
3389 static void igb_reset_task(struct work_struct *work)
3390 {
3391         struct igb_adapter *adapter;
3392         adapter = container_of(work, struct igb_adapter, reset_task);
3393
3394         igb_reinit_locked(adapter);
3395 }
3396
3397 /**
3398  * igb_get_stats - Get System Network Statistics
3399  * @netdev: network interface device structure
3400  *
3401  * Returns the address of the device statistics structure.
3402  * The statistics are actually updated from the timer callback.
3403  **/
3404 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3405 {
3406         struct igb_adapter *adapter = netdev_priv(netdev);
3407
3408         /* only return the current stats */
3409         return &adapter->net_stats;
3410 }
3411
3412 /**
3413  * igb_change_mtu - Change the Maximum Transfer Unit
3414  * @netdev: network interface device structure
3415  * @new_mtu: new value for maximum frame size
3416  *
3417  * Returns 0 on success, negative on failure
3418  **/
3419 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3420 {
3421         struct igb_adapter *adapter = netdev_priv(netdev);
3422         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3423
3424         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3425             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3426                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3427                 return -EINVAL;
3428         }
3429
3430         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3431                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3432                 return -EINVAL;
3433         }
3434
3435         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3436                 msleep(1);
3437
3438         /* igb_down has a dependency on max_frame_size */
3439         adapter->max_frame_size = max_frame;
3440         if (netif_running(netdev))
3441                 igb_down(adapter);
3442
3443         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3444          * means we reserve 2 more, this pushes us to allocate from the next
3445          * larger slab size.
3446          * i.e. RXBUFFER_2048 --> size-4096 slab
3447          */
3448
3449         if (max_frame <= IGB_RXBUFFER_256)
3450                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3451         else if (max_frame <= IGB_RXBUFFER_512)
3452                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3453         else if (max_frame <= IGB_RXBUFFER_1024)
3454                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3455         else if (max_frame <= IGB_RXBUFFER_2048)
3456                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3457         else
3458 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3459                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3460 #else
3461                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3462 #endif
3463
3464         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3465         if (adapter->vfs_allocated_count &&
3466             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3467                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3468
3469         /* adjust allocation if LPE protects us, and we aren't using SBP */
3470         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3471              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3472                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3473
3474         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3475                  netdev->mtu, new_mtu);
3476         netdev->mtu = new_mtu;
3477
3478         if (netif_running(netdev))
3479                 igb_up(adapter);
3480         else
3481                 igb_reset(adapter);
3482
3483         clear_bit(__IGB_RESETTING, &adapter->state);
3484
3485         return 0;
3486 }
3487
3488 /**
3489  * igb_update_stats - Update the board statistics counters
3490  * @adapter: board private structure
3491  **/
3492
3493 void igb_update_stats(struct igb_adapter *adapter)
3494 {
3495         struct e1000_hw *hw = &adapter->hw;
3496         struct pci_dev *pdev = adapter->pdev;
3497         u16 phy_tmp;
3498
3499 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3500
3501         /*
3502          * Prevent stats update while adapter is being reset, or if the pci
3503          * connection is down.
3504          */
3505         if (adapter->link_speed == 0)
3506                 return;
3507         if (pci_channel_offline(pdev))
3508                 return;
3509
3510         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3511         adapter->stats.gprc += rd32(E1000_GPRC);
3512         adapter->stats.gorc += rd32(E1000_GORCL);
3513         rd32(E1000_GORCH); /* clear GORCL */
3514         adapter->stats.bprc += rd32(E1000_BPRC);
3515         adapter->stats.mprc += rd32(E1000_MPRC);
3516         adapter->stats.roc += rd32(E1000_ROC);
3517
3518         adapter->stats.prc64 += rd32(E1000_PRC64);
3519         adapter->stats.prc127 += rd32(E1000_PRC127);
3520         adapter->stats.prc255 += rd32(E1000_PRC255);
3521         adapter->stats.prc511 += rd32(E1000_PRC511);
3522         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3523         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3524         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3525         adapter->stats.sec += rd32(E1000_SEC);
3526
3527         adapter->stats.mpc += rd32(E1000_MPC);
3528         adapter->stats.scc += rd32(E1000_SCC);
3529         adapter->stats.ecol += rd32(E1000_ECOL);
3530         adapter->stats.mcc += rd32(E1000_MCC);
3531         adapter->stats.latecol += rd32(E1000_LATECOL);
3532         adapter->stats.dc += rd32(E1000_DC);
3533         adapter->stats.rlec += rd32(E1000_RLEC);
3534         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3535         adapter->stats.xontxc += rd32(E1000_XONTXC);
3536         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3537         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3538         adapter->stats.fcruc += rd32(E1000_FCRUC);
3539         adapter->stats.gptc += rd32(E1000_GPTC);
3540         adapter->stats.gotc += rd32(E1000_GOTCL);
3541         rd32(E1000_GOTCH); /* clear GOTCL */
3542         adapter->stats.rnbc += rd32(E1000_RNBC);
3543         adapter->stats.ruc += rd32(E1000_RUC);
3544         adapter->stats.rfc += rd32(E1000_RFC);
3545         adapter->stats.rjc += rd32(E1000_RJC);
3546         adapter->stats.tor += rd32(E1000_TORH);
3547         adapter->stats.tot += rd32(E1000_TOTH);
3548         adapter->stats.tpr += rd32(E1000_TPR);
3549
3550         adapter->stats.ptc64 += rd32(E1000_PTC64);
3551         adapter->stats.ptc127 += rd32(E1000_PTC127);
3552         adapter->stats.ptc255 += rd32(E1000_PTC255);
3553         adapter->stats.ptc511 += rd32(E1000_PTC511);
3554         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3555         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3556
3557         adapter->stats.mptc += rd32(E1000_MPTC);
3558         adapter->stats.bptc += rd32(E1000_BPTC);
3559
3560         /* used for adaptive IFS */
3561
3562         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3563         adapter->stats.tpt += hw->mac.tx_packet_delta;
3564         hw->mac.collision_delta = rd32(E1000_COLC);
3565         adapter->stats.colc += hw->mac.collision_delta;
3566
3567         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3568         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3569         adapter->stats.tncrs += rd32(E1000_TNCRS);
3570         adapter->stats.tsctc += rd32(E1000_TSCTC);
3571         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3572
3573         adapter->stats.iac += rd32(E1000_IAC);
3574         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3575         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3576         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3577         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3578         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3579         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3580         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3581         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3582
3583         /* Fill out the OS statistics structure */
3584         adapter->net_stats.multicast = adapter->stats.mprc;
3585         adapter->net_stats.collisions = adapter->stats.colc;
3586
3587         /* Rx Errors */
3588
3589         if (hw->mac.type != e1000_82575) {
3590                 u32 rqdpc_tmp;
3591                 u64 rqdpc_total = 0;
3592                 int i;
3593                 /* Read out drops stats per RX queue.  Notice RQDPC (Receive
3594                  * Queue Drop Packet Count) stats only gets incremented, if
3595                  * the DROP_EN but it set (in the SRRCTL register for that
3596                  * queue).  If DROP_EN bit is NOT set, then the some what
3597                  * equivalent count is stored in RNBC (not per queue basis).
3598                  * Also note the drop count is due to lack of available
3599                  * descriptors.
3600                  */
3601                 for (i = 0; i < adapter->num_rx_queues; i++) {
3602                         rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3603                         adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3604                         rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3605                 }
3606                 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3607         }
3608
3609         /* Note RNBC (Receive No Buffers Count) is an not an exact
3610          * drop count as the hardware FIFO might save the day.  Thats
3611          * one of the reason for saving it in rx_fifo_errors, as its
3612          * potentially not a true drop.
3613          */
3614         adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3615
3616         /* RLEC on some newer hardware can be incorrect so build
3617          * our own version based on RUC and ROC */
3618         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3619                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3620                 adapter->stats.ruc + adapter->stats.roc +
3621                 adapter->stats.cexterr;
3622         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3623                                               adapter->stats.roc;
3624         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3625         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3626         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3627
3628         /* Tx Errors */
3629         adapter->net_stats.tx_errors = adapter->stats.ecol +
3630                                        adapter->stats.latecol;
3631         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3632         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3633         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3634
3635         /* Tx Dropped needs to be maintained elsewhere */
3636
3637         /* Phy Stats */
3638         if (hw->phy.media_type == e1000_media_type_copper) {
3639                 if ((adapter->link_speed == SPEED_1000) &&
3640                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3641                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3642                         adapter->phy_stats.idle_errors += phy_tmp;
3643                 }
3644         }
3645
3646         /* Management Stats */
3647         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3648         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3649         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3650 }
3651
3652 static irqreturn_t igb_msix_other(int irq, void *data)
3653 {
3654         struct net_device *netdev = data;
3655         struct igb_adapter *adapter = netdev_priv(netdev);
3656         struct e1000_hw *hw = &adapter->hw;
3657         u32 icr = rd32(E1000_ICR);
3658
3659         /* reading ICR causes bit 31 of EICR to be cleared */
3660
3661         if(icr & E1000_ICR_DOUTSYNC) {
3662                 /* HW is reporting DMA is out of sync */
3663                 adapter->stats.doosync++;
3664         }
3665
3666         /* Check for a mailbox event */
3667         if (icr & E1000_ICR_VMMB)
3668                 igb_msg_task(adapter);
3669
3670         if (icr & E1000_ICR_LSC) {
3671                 hw->mac.get_link_status = 1;
3672                 /* guard against interrupt when we're going down */
3673                 if (!test_bit(__IGB_DOWN, &adapter->state))
3674                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3675         }
3676
3677         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3678         wr32(E1000_EIMS, adapter->eims_other);
3679
3680         return IRQ_HANDLED;
3681 }
3682
3683 static irqreturn_t igb_msix_tx(int irq, void *data)
3684 {
3685         struct igb_ring *tx_ring = data;
3686         struct igb_adapter *adapter = tx_ring->adapter;
3687         struct e1000_hw *hw = &adapter->hw;
3688
3689 #ifdef CONFIG_IGB_DCA
3690         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3691                 igb_update_tx_dca(tx_ring);
3692 #endif
3693
3694         tx_ring->total_bytes = 0;
3695         tx_ring->total_packets = 0;
3696
3697         /* auto mask will automatically reenable the interrupt when we write
3698          * EICS */
3699         if (!igb_clean_tx_irq(tx_ring))
3700                 /* Ring was not completely cleaned, so fire another interrupt */
3701                 wr32(E1000_EICS, tx_ring->eims_value);
3702         else
3703                 wr32(E1000_EIMS, tx_ring->eims_value);
3704
3705         return IRQ_HANDLED;
3706 }
3707
3708 static void igb_write_itr(struct igb_ring *ring)
3709 {
3710         struct e1000_hw *hw = &ring->adapter->hw;
3711         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3712                 switch (hw->mac.type) {
3713                 case e1000_82576:
3714                         wr32(ring->itr_register, ring->itr_val |
3715                              0x80000000);
3716                         break;
3717                 default:
3718                         wr32(ring->itr_register, ring->itr_val |
3719                              (ring->itr_val << 16));
3720                         break;
3721                 }
3722                 ring->set_itr = 0;
3723         }
3724 }
3725
3726 static irqreturn_t igb_msix_rx(int irq, void *data)
3727 {
3728         struct igb_ring *rx_ring = data;
3729
3730         /* Write the ITR value calculated at the end of the
3731          * previous interrupt.
3732          */
3733
3734         igb_write_itr(rx_ring);
3735
3736         if (napi_schedule_prep(&rx_ring->napi))
3737                 __napi_schedule(&rx_ring->napi);
3738
3739 #ifdef CONFIG_IGB_DCA
3740         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3741                 igb_update_rx_dca(rx_ring);
3742 #endif
3743                 return IRQ_HANDLED;
3744 }
3745
3746 #ifdef CONFIG_IGB_DCA
3747 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3748 {
3749         u32 dca_rxctrl;
3750         struct igb_adapter *adapter = rx_ring->adapter;
3751         struct e1000_hw *hw = &adapter->hw;
3752         int cpu = get_cpu();
3753         int q = rx_ring->reg_idx;
3754
3755         if (rx_ring->cpu != cpu) {
3756                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3757                 if (hw->mac.type == e1000_82576) {
3758                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3759                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3760                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3761                 } else {
3762                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3763                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3764                 }
3765                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3766                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3767                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3768                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3769                 rx_ring->cpu = cpu;
3770         }
3771         put_cpu();
3772 }
3773
3774 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3775 {
3776         u32 dca_txctrl;
3777         struct igb_adapter *adapter = tx_ring->adapter;
3778         struct e1000_hw *hw = &adapter->hw;
3779         int cpu = get_cpu();
3780         int q = tx_ring->reg_idx;
3781
3782         if (tx_ring->cpu != cpu) {
3783                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3784                 if (hw->mac.type == e1000_82576) {
3785                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3786                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3787                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3788                 } else {
3789                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3790                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3791                 }
3792                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3793                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3794                 tx_ring->cpu = cpu;
3795         }
3796         put_cpu();
3797 }
3798
3799 static void igb_setup_dca(struct igb_adapter *adapter)
3800 {
3801         struct e1000_hw *hw = &adapter->hw;
3802         int i;
3803
3804         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3805                 return;
3806
3807         /* Always use CB2 mode, difference is masked in the CB driver. */
3808         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3809
3810         for (i = 0; i < adapter->num_tx_queues; i++) {
3811                 adapter->tx_ring[i].cpu = -1;
3812                 igb_update_tx_dca(&adapter->tx_ring[i]);
3813         }
3814         for (i = 0; i < adapter->num_rx_queues; i++) {
3815                 adapter->rx_ring[i].cpu = -1;
3816                 igb_update_rx_dca(&adapter->rx_ring[i]);
3817         }
3818 }
3819
3820 static int __igb_notify_dca(struct device *dev, void *data)
3821 {
3822         struct net_device *netdev = dev_get_drvdata(dev);
3823         struct igb_adapter *adapter = netdev_priv(netdev);
3824         struct e1000_hw *hw = &adapter->hw;
3825         unsigned long event = *(unsigned long *)data;
3826
3827         switch (event) {
3828         case DCA_PROVIDER_ADD:
3829                 /* if already enabled, don't do it again */
3830                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3831                         break;
3832                 /* Always use CB2 mode, difference is masked
3833                  * in the CB driver. */
3834                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3835                 if (dca_add_requester(dev) == 0) {
3836                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3837                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3838                         igb_setup_dca(adapter);
3839                         break;
3840                 }
3841                 /* Fall Through since DCA is disabled. */
3842         case DCA_PROVIDER_REMOVE:
3843                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3844                         /* without this a class_device is left
3845                          * hanging around in the sysfs model */
3846                         dca_remove_requester(dev);
3847                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3848                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3849                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3850                 }
3851                 break;
3852         }
3853
3854         return 0;
3855 }
3856
3857 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3858                           void *p)
3859 {
3860         int ret_val;
3861
3862         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3863                                          __igb_notify_dca);
3864
3865         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3866 }
3867 #endif /* CONFIG_IGB_DCA */
3868
3869 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3870 {
3871         struct e1000_hw *hw = &adapter->hw;
3872         u32 ping;
3873         int i;
3874
3875         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3876                 ping = E1000_PF_CONTROL_MSG;
3877                 if (adapter->vf_data[i].clear_to_send)
3878                         ping |= E1000_VT_MSGTYPE_CTS;
3879                 igb_write_mbx(hw, &ping, 1, i);
3880         }
3881 }
3882
3883 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3884                                   u32 *msgbuf, u32 vf)
3885 {
3886         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3887         u16 *hash_list = (u16 *)&msgbuf[1];
3888         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3889         int i;
3890
3891         /* only up to 30 hash values supported */
3892         if (n > 30)
3893                 n = 30;
3894
3895         /* salt away the number of multi cast addresses assigned
3896          * to this VF for later use to restore when the PF multi cast
3897          * list changes
3898          */
3899         vf_data->num_vf_mc_hashes = n;
3900
3901         /* VFs are limited to using the MTA hash table for their multicast
3902          * addresses */
3903         for (i = 0; i < n; i++)
3904                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3905
3906         /* Flush and reset the mta with the new values */
3907         igb_set_multi(adapter->netdev);
3908
3909         return 0;
3910 }
3911
3912 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3913 {
3914         struct e1000_hw *hw = &adapter->hw;
3915         struct vf_data_storage *vf_data;
3916         int i, j;
3917
3918         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3919                 vf_data = &adapter->vf_data[i];
3920                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3921                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3922         }
3923 }
3924
3925 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3926 {
3927         struct e1000_hw *hw = &adapter->hw;
3928         u32 pool_mask, reg, vid;
3929         int i;
3930
3931         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3932
3933         /* Find the vlan filter for this id */
3934         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3935                 reg = rd32(E1000_VLVF(i));
3936
3937                 /* remove the vf from the pool */
3938                 reg &= ~pool_mask;
3939
3940                 /* if pool is empty then remove entry from vfta */
3941                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3942                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3943                         reg = 0;
3944                         vid = reg & E1000_VLVF_VLANID_MASK;
3945                         igb_vfta_set(hw, vid, false);
3946                 }
3947
3948                 wr32(E1000_VLVF(i), reg);
3949         }
3950 }
3951
3952 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3953 {
3954         struct e1000_hw *hw = &adapter->hw;
3955         u32 reg, i;
3956
3957         /* It is an error to call this function when VFs are not enabled */
3958         if (!adapter->vfs_allocated_count)
3959                 return -1;
3960
3961         /* Find the vlan filter for this id */
3962         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3963                 reg = rd32(E1000_VLVF(i));
3964                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3965                     vid == (reg & E1000_VLVF_VLANID_MASK))
3966                         break;
3967         }
3968
3969         if (add) {
3970                 if (i == E1000_VLVF_ARRAY_SIZE) {
3971                         /* Did not find a matching VLAN ID entry that was
3972                          * enabled.  Search for a free filter entry, i.e.
3973                          * one without the enable bit set
3974                          */
3975                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3976                                 reg = rd32(E1000_VLVF(i));
3977                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3978                                         break;
3979                         }
3980                 }
3981                 if (i < E1000_VLVF_ARRAY_SIZE) {
3982                         /* Found an enabled/available entry */
3983                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3984
3985                         /* if !enabled we need to set this up in vfta */
3986                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3987                                 /* add VID to filter table, if bit already set
3988                                  * PF must have added it outside of table */
3989                                 if (igb_vfta_set(hw, vid, true))
3990                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3991                                                 adapter->vfs_allocated_count);
3992                                 reg |= E1000_VLVF_VLANID_ENABLE;
3993                         }
3994                         reg &= ~E1000_VLVF_VLANID_MASK;
3995                         reg |= vid;
3996
3997                         wr32(E1000_VLVF(i), reg);
3998                         return 0;
3999                 }
4000         } else {
4001                 if (i < E1000_VLVF_ARRAY_SIZE) {
4002                         /* remove vf from the pool */
4003                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4004                         /* if pool is empty then remove entry from vfta */
4005                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4006                                 reg = 0;
4007                                 igb_vfta_set(hw, vid, false);
4008                         }
4009                         wr32(E1000_VLVF(i), reg);
4010                         return 0;
4011                 }
4012         }
4013         return -1;
4014 }
4015
4016 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4017 {
4018         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4019         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4020
4021         return igb_vlvf_set(adapter, vid, add, vf);
4022 }
4023
4024 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4025 {
4026         struct e1000_hw *hw = &adapter->hw;
4027
4028         /* disable mailbox functionality for vf */
4029         adapter->vf_data[vf].clear_to_send = false;
4030
4031         /* reset offloads to defaults */
4032         igb_set_vmolr(hw, vf);
4033
4034         /* reset vlans for device */
4035         igb_clear_vf_vfta(adapter, vf);
4036
4037         /* reset multicast table array for vf */
4038         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4039
4040         /* Flush and reset the mta with the new values */
4041         igb_set_multi(adapter->netdev);
4042 }
4043
4044 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4045 {
4046         struct e1000_hw *hw = &adapter->hw;
4047         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4048         u32 reg, msgbuf[3];
4049         u8 *addr = (u8 *)(&msgbuf[1]);
4050
4051         /* process all the same items cleared in a function level reset */
4052         igb_vf_reset_event(adapter, vf);
4053
4054         /* set vf mac address */
4055         igb_rar_set(hw, vf_mac, vf + 1);
4056         igb_set_rah_pool(hw, vf, vf + 1);
4057
4058         /* enable transmit and receive for vf */
4059         reg = rd32(E1000_VFTE);
4060         wr32(E1000_VFTE, reg | (1 << vf));
4061         reg = rd32(E1000_VFRE);
4062         wr32(E1000_VFRE, reg | (1 << vf));
4063
4064         /* enable mailbox functionality for vf */
4065         adapter->vf_data[vf].clear_to_send = true;
4066
4067         /* reply to reset with ack and vf mac address */
4068         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4069         memcpy(addr, vf_mac, 6);
4070         igb_write_mbx(hw, msgbuf, 3, vf);
4071 }
4072
4073 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4074 {
4075                 unsigned char *addr = (char *)&msg[1];
4076                 int err = -1;
4077
4078                 if (is_valid_ether_addr(addr))
4079                         err = igb_set_vf_mac(adapter, vf, addr);
4080
4081                 return err;
4082
4083 }
4084
4085 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4086 {
4087         struct e1000_hw *hw = &adapter->hw;
4088         u32 msg = E1000_VT_MSGTYPE_NACK;
4089
4090         /* if device isn't clear to send it shouldn't be reading either */
4091         if (!adapter->vf_data[vf].clear_to_send)
4092                 igb_write_mbx(hw, &msg, 1, vf);
4093 }
4094
4095
4096 static void igb_msg_task(struct igb_adapter *adapter)
4097 {
4098         struct e1000_hw *hw = &adapter->hw;
4099         u32 vf;
4100
4101         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4102                 /* process any reset requests */
4103                 if (!igb_check_for_rst(hw, vf)) {
4104                         adapter->vf_data[vf].clear_to_send = false;
4105                         igb_vf_reset_event(adapter, vf);
4106                 }
4107
4108                 /* process any messages pending */
4109                 if (!igb_check_for_msg(hw, vf))
4110                         igb_rcv_msg_from_vf(adapter, vf);
4111
4112                 /* process any acks */
4113                 if (!igb_check_for_ack(hw, vf))
4114                         igb_rcv_ack_from_vf(adapter, vf);
4115
4116         }
4117 }
4118
4119 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4120 {
4121         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4122         u32 msgbuf[mbx_size];
4123         struct e1000_hw *hw = &adapter->hw;
4124         s32 retval;
4125
4126         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4127
4128         if (retval)
4129                 dev_err(&adapter->pdev->dev,
4130                         "Error receiving message from VF\n");
4131
4132         /* this is a message we already processed, do nothing */
4133         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4134                 return retval;
4135
4136         /*
4137          * until the vf completes a reset it should not be
4138          * allowed to start any configuration.
4139          */
4140
4141         if (msgbuf[0] == E1000_VF_RESET) {
4142                 igb_vf_reset_msg(adapter, vf);
4143
4144                 return retval;
4145         }
4146
4147         if (!adapter->vf_data[vf].clear_to_send) {
4148                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4149                 igb_write_mbx(hw, msgbuf, 1, vf);
4150                 return retval;
4151         }
4152
4153         switch ((msgbuf[0] & 0xFFFF)) {
4154         case E1000_VF_SET_MAC_ADDR:
4155                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4156                 break;
4157         case E1000_VF_SET_MULTICAST:
4158                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4159                 break;
4160         case E1000_VF_SET_LPE:
4161                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4162                 break;
4163         case E1000_VF_SET_VLAN:
4164                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4165                 break;
4166         default:
4167                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4168                 retval = -1;
4169                 break;
4170         }
4171
4172         /* notify the VF of the results of what it sent us */
4173         if (retval)
4174                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4175         else
4176                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4177
4178         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4179
4180         igb_write_mbx(hw, msgbuf, 1, vf);
4181
4182         return retval;
4183 }
4184
4185 /**
4186  * igb_intr_msi - Interrupt Handler
4187  * @irq: interrupt number
4188  * @data: pointer to a network interface device structure
4189  **/
4190 static irqreturn_t igb_intr_msi(int irq, void *data)
4191 {
4192         struct net_device *netdev = data;
4193         struct igb_adapter *adapter = netdev_priv(netdev);
4194         struct e1000_hw *hw = &adapter->hw;
4195         /* read ICR disables interrupts using IAM */
4196         u32 icr = rd32(E1000_ICR);
4197
4198         igb_write_itr(adapter->rx_ring);
4199
4200         if(icr & E1000_ICR_DOUTSYNC) {
4201                 /* HW is reporting DMA is out of sync */
4202                 adapter->stats.doosync++;
4203         }
4204
4205         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4206                 hw->mac.get_link_status = 1;
4207                 if (!test_bit(__IGB_DOWN, &adapter->state))
4208                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4209         }
4210
4211         napi_schedule(&adapter->rx_ring[0].napi);
4212
4213         return IRQ_HANDLED;
4214 }
4215
4216 /**
4217  * igb_intr - Legacy Interrupt Handler
4218  * @irq: interrupt number
4219  * @data: pointer to a network interface device structure
4220  **/
4221 static irqreturn_t igb_intr(int irq, void *data)
4222 {
4223         struct net_device *netdev = data;
4224         struct igb_adapter *adapter = netdev_priv(netdev);
4225         struct e1000_hw *hw = &adapter->hw;
4226         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4227          * need for the IMC write */
4228         u32 icr = rd32(E1000_ICR);
4229         if (!icr)
4230                 return IRQ_NONE;  /* Not our interrupt */
4231
4232         igb_write_itr(adapter->rx_ring);
4233
4234         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4235          * not set, then the adapter didn't send an interrupt */
4236         if (!(icr & E1000_ICR_INT_ASSERTED))
4237                 return IRQ_NONE;
4238
4239         if(icr & E1000_ICR_DOUTSYNC) {
4240                 /* HW is reporting DMA is out of sync */
4241                 adapter->stats.doosync++;
4242         }
4243
4244         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4245                 hw->mac.get_link_status = 1;
4246                 /* guard against interrupt when we're going down */
4247                 if (!test_bit(__IGB_DOWN, &adapter->state))
4248                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4249         }
4250
4251         napi_schedule(&adapter->rx_ring[0].napi);
4252
4253         return IRQ_HANDLED;
4254 }
4255
4256 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4257 {
4258         struct igb_adapter *adapter = rx_ring->adapter;
4259         struct e1000_hw *hw = &adapter->hw;
4260
4261         if (adapter->itr_setting & 3) {
4262                 if (adapter->num_rx_queues == 1)
4263                         igb_set_itr(adapter);
4264                 else
4265                         igb_update_ring_itr(rx_ring);
4266         }
4267
4268         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4269                 if (adapter->msix_entries)
4270                         wr32(E1000_EIMS, rx_ring->eims_value);
4271                 else
4272                         igb_irq_enable(adapter);
4273         }
4274 }
4275
4276 /**
4277  * igb_poll - NAPI Rx polling callback
4278  * @napi: napi polling structure
4279  * @budget: count of how many packets we should handle
4280  **/
4281 static int igb_poll(struct napi_struct *napi, int budget)
4282 {
4283         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4284         int work_done = 0;
4285
4286 #ifdef CONFIG_IGB_DCA
4287         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4288                 igb_update_rx_dca(rx_ring);
4289 #endif
4290         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4291
4292         if (rx_ring->buddy) {
4293 #ifdef CONFIG_IGB_DCA
4294                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4295                         igb_update_tx_dca(rx_ring->buddy);
4296 #endif
4297                 if (!igb_clean_tx_irq(rx_ring->buddy))
4298                         work_done = budget;
4299         }
4300
4301         /* If not enough Rx work done, exit the polling mode */
4302         if (work_done < budget) {
4303                 napi_complete(napi);
4304                 igb_rx_irq_enable(rx_ring);
4305         }
4306
4307         return work_done;
4308 }
4309
4310 /**
4311  * igb_hwtstamp - utility function which checks for TX time stamp
4312  * @adapter: board private structure
4313  * @skb: packet that was just sent
4314  *
4315  * If we were asked to do hardware stamping and such a time stamp is
4316  * available, then it must have been for this skb here because we only
4317  * allow only one such packet into the queue.
4318  */
4319 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4320 {
4321         union skb_shared_tx *shtx = skb_tx(skb);
4322         struct e1000_hw *hw = &adapter->hw;
4323
4324         if (unlikely(shtx->hardware)) {
4325                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4326                 if (valid) {
4327                         u64 regval = rd32(E1000_TXSTMPL);
4328                         u64 ns;
4329                         struct skb_shared_hwtstamps shhwtstamps;
4330
4331                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4332                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4333                         ns = timecounter_cyc2time(&adapter->clock,
4334                                                   regval);
4335                         timecompare_update(&adapter->compare, ns);
4336                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4337                         shhwtstamps.syststamp =
4338                                 timecompare_transform(&adapter->compare, ns);
4339                         skb_tstamp_tx(skb, &shhwtstamps);
4340                 }
4341         }
4342 }
4343
4344 /**
4345  * igb_clean_tx_irq - Reclaim resources after transmit completes
4346  * @adapter: board private structure
4347  * returns true if ring is completely cleaned
4348  **/
4349 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4350 {
4351         struct igb_adapter *adapter = tx_ring->adapter;
4352         struct net_device *netdev = adapter->netdev;
4353         struct e1000_hw *hw = &adapter->hw;
4354         struct igb_buffer *buffer_info;
4355         struct sk_buff *skb;
4356         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4357         unsigned int total_bytes = 0, total_packets = 0;
4358         unsigned int i, eop, count = 0;
4359         bool cleaned = false;
4360
4361         i = tx_ring->next_to_clean;
4362         eop = tx_ring->buffer_info[i].next_to_watch;
4363         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4364
4365         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4366                (count < tx_ring->count)) {
4367                 for (cleaned = false; !cleaned; count++) {
4368                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4369                         buffer_info = &tx_ring->buffer_info[i];
4370                         cleaned = (i == eop);
4371                         skb = buffer_info->skb;
4372
4373                         if (skb) {
4374                                 unsigned int segs, bytecount;
4375                                 /* gso_segs is currently only valid for tcp */
4376                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4377                                 /* multiply data chunks by size of headers */
4378                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4379                                             skb->len;
4380                                 total_packets += segs;
4381                                 total_bytes += bytecount;
4382
4383                                 igb_tx_hwtstamp(adapter, skb);
4384                         }
4385
4386                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4387                         tx_desc->wb.status = 0;
4388
4389                         i++;
4390                         if (i == tx_ring->count)
4391                                 i = 0;
4392                 }
4393                 eop = tx_ring->buffer_info[i].next_to_watch;
4394                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4395         }
4396
4397         tx_ring->next_to_clean = i;
4398
4399         if (unlikely(count &&
4400                      netif_carrier_ok(netdev) &&
4401                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4402                 /* Make sure that anybody stopping the queue after this
4403                  * sees the new next_to_clean.
4404                  */
4405                 smp_mb();
4406                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4407                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4408                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4409                         ++adapter->restart_queue;
4410                 }
4411         }
4412
4413         if (tx_ring->detect_tx_hung) {
4414                 /* Detect a transmit hang in hardware, this serializes the
4415                  * check with the clearing of time_stamp and movement of i */
4416                 tx_ring->detect_tx_hung = false;
4417                 if (tx_ring->buffer_info[i].time_stamp &&
4418                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4419                                (adapter->tx_timeout_factor * HZ))
4420                     && !(rd32(E1000_STATUS) &
4421                          E1000_STATUS_TXOFF)) {
4422
4423                         /* detected Tx unit hang */
4424                         dev_err(&adapter->pdev->dev,
4425                                 "Detected Tx Unit Hang\n"
4426                                 "  Tx Queue             <%d>\n"
4427                                 "  TDH                  <%x>\n"
4428                                 "  TDT                  <%x>\n"
4429                                 "  next_to_use          <%x>\n"
4430                                 "  next_to_clean        <%x>\n"
4431                                 "buffer_info[next_to_clean]\n"
4432                                 "  time_stamp           <%lx>\n"
4433                                 "  next_to_watch        <%x>\n"
4434                                 "  jiffies              <%lx>\n"
4435                                 "  desc.status          <%x>\n",
4436                                 tx_ring->queue_index,
4437                                 readl(adapter->hw.hw_addr + tx_ring->head),
4438                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4439                                 tx_ring->next_to_use,
4440                                 tx_ring->next_to_clean,
4441                                 tx_ring->buffer_info[i].time_stamp,
4442                                 eop,
4443                                 jiffies,
4444                                 eop_desc->wb.status);
4445                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4446                 }
4447         }
4448         tx_ring->total_bytes += total_bytes;
4449         tx_ring->total_packets += total_packets;
4450         tx_ring->tx_stats.bytes += total_bytes;
4451         tx_ring->tx_stats.packets += total_packets;
4452         adapter->net_stats.tx_bytes += total_bytes;
4453         adapter->net_stats.tx_packets += total_packets;
4454         return (count < tx_ring->count);
4455 }
4456
4457 /**
4458  * igb_receive_skb - helper function to handle rx indications
4459  * @ring: pointer to receive ring receving this packet
4460  * @status: descriptor status field as written by hardware
4461  * @rx_desc: receive descriptor containing vlan and type information.
4462  * @skb: pointer to sk_buff to be indicated to stack
4463  **/
4464 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4465                             union e1000_adv_rx_desc * rx_desc,
4466                             struct sk_buff *skb)
4467 {
4468         struct igb_adapter * adapter = ring->adapter;
4469         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4470
4471         skb_record_rx_queue(skb, ring->queue_index);
4472         if (vlan_extracted)
4473                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4474                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4475                                  skb);
4476         else
4477                 napi_gro_receive(&ring->napi, skb);
4478 }
4479
4480 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4481                                        u32 status_err, struct sk_buff *skb)
4482 {
4483         skb->ip_summed = CHECKSUM_NONE;
4484
4485         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4486         if ((status_err & E1000_RXD_STAT_IXSM) ||
4487             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4488                 return;
4489         /* TCP/UDP checksum error bit is set */
4490         if (status_err &
4491             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4492                 /*
4493                  * work around errata with sctp packets where the TCPE aka
4494                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4495                  * packets, (aka let the stack check the crc32c)
4496                  */
4497                 if (!((adapter->hw.mac.type == e1000_82576) &&
4498                       (skb->len == 60)))
4499                         adapter->hw_csum_err++;
4500                 /* let the stack verify checksum errors */
4501                 return;
4502         }
4503         /* It must be a TCP or UDP packet with a valid checksum */
4504         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4505                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4506
4507         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4508         adapter->hw_csum_good++;
4509 }
4510
4511 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4512                                  int *work_done, int budget)
4513 {
4514         struct igb_adapter *adapter = rx_ring->adapter;
4515         struct net_device *netdev = adapter->netdev;
4516         struct e1000_hw *hw = &adapter->hw;
4517         struct pci_dev *pdev = adapter->pdev;
4518         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4519         struct igb_buffer *buffer_info , *next_buffer;
4520         struct sk_buff *skb;
4521         bool cleaned = false;
4522         int cleaned_count = 0;
4523         unsigned int total_bytes = 0, total_packets = 0;
4524         unsigned int i;
4525         u32 length, hlen, staterr;
4526
4527         i = rx_ring->next_to_clean;
4528         buffer_info = &rx_ring->buffer_info[i];
4529         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4530         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4531
4532         while (staterr & E1000_RXD_STAT_DD) {
4533                 if (*work_done >= budget)
4534                         break;
4535                 (*work_done)++;
4536
4537                 skb = buffer_info->skb;
4538                 prefetch(skb->data - NET_IP_ALIGN);
4539                 buffer_info->skb = NULL;
4540
4541                 i++;
4542                 if (i == rx_ring->count)
4543                         i = 0;
4544                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4545                 prefetch(next_rxd);
4546                 next_buffer = &rx_ring->buffer_info[i];
4547
4548                 length = le16_to_cpu(rx_desc->wb.upper.length);
4549                 cleaned = true;
4550                 cleaned_count++;
4551
4552                 /* this is the fast path for the non-packet split case */
4553                 if (!adapter->rx_ps_hdr_size) {
4554                         pci_unmap_single(pdev, buffer_info->dma,
4555                                          adapter->rx_buffer_len,
4556                                          PCI_DMA_FROMDEVICE);
4557                         buffer_info->dma = 0;
4558                         skb_put(skb, length);
4559                         goto send_up;
4560                 }
4561
4562                 /* HW will not DMA in data larger than the given buffer, even
4563                  * if it parses the (NFS, of course) header to be larger.  In
4564                  * that case, it fills the header buffer and spills the rest
4565                  * into the page.
4566                  */
4567                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4568                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4569                 if (hlen > adapter->rx_ps_hdr_size)
4570                         hlen = adapter->rx_ps_hdr_size;
4571
4572                 if (!skb_shinfo(skb)->nr_frags) {
4573                         pci_unmap_single(pdev, buffer_info->dma,
4574                                          adapter->rx_ps_hdr_size,
4575                                          PCI_DMA_FROMDEVICE);
4576                         buffer_info->dma = 0;
4577                         skb_put(skb, hlen);
4578                 }
4579
4580                 if (length) {
4581                         pci_unmap_page(pdev, buffer_info->page_dma,
4582                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4583                         buffer_info->page_dma = 0;
4584
4585                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4586                                                 buffer_info->page,
4587                                                 buffer_info->page_offset,
4588                                                 length);
4589
4590                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4591                             (page_count(buffer_info->page) != 1))
4592                                 buffer_info->page = NULL;
4593                         else
4594                                 get_page(buffer_info->page);
4595
4596                         skb->len += length;
4597                         skb->data_len += length;
4598
4599                         skb->truesize += length;
4600                 }
4601
4602                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4603                         buffer_info->skb = next_buffer->skb;
4604                         buffer_info->dma = next_buffer->dma;
4605                         next_buffer->skb = skb;
4606                         next_buffer->dma = 0;
4607                         goto next_desc;
4608                 }
4609 send_up:
4610                 /*
4611                  * If this bit is set, then the RX registers contain
4612                  * the time stamp. No other packet will be time
4613                  * stamped until we read these registers, so read the
4614                  * registers to make them available again. Because
4615                  * only one packet can be time stamped at a time, we
4616                  * know that the register values must belong to this
4617                  * one here and therefore we don't need to compare
4618                  * any of the additional attributes stored for it.
4619                  *
4620                  * If nothing went wrong, then it should have a
4621                  * skb_shared_tx that we can turn into a
4622                  * skb_shared_hwtstamps.
4623                  *
4624                  * TODO: can time stamping be triggered (thus locking
4625                  * the registers) without the packet reaching this point
4626                  * here? In that case RX time stamping would get stuck.
4627                  *
4628                  * TODO: in "time stamp all packets" mode this bit is
4629                  * not set. Need a global flag for this mode and then
4630                  * always read the registers. Cannot be done without
4631                  * a race condition.
4632                  */
4633                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4634                         u64 regval;
4635                         u64 ns;
4636                         struct skb_shared_hwtstamps *shhwtstamps =
4637                                 skb_hwtstamps(skb);
4638
4639                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4640                              "igb: no RX time stamp available for time stamped packet");
4641                         regval = rd32(E1000_RXSTMPL);
4642                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4643                         ns = timecounter_cyc2time(&adapter->clock, regval);
4644                         timecompare_update(&adapter->compare, ns);
4645                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4646                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4647                         shhwtstamps->syststamp =
4648                                 timecompare_transform(&adapter->compare, ns);
4649                 }
4650
4651                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4652                         dev_kfree_skb_irq(skb);
4653                         goto next_desc;
4654                 }
4655
4656                 total_bytes += skb->len;
4657                 total_packets++;
4658
4659                 igb_rx_checksum_adv(adapter, staterr, skb);
4660
4661                 skb->protocol = eth_type_trans(skb, netdev);
4662
4663                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4664
4665 next_desc:
4666                 rx_desc->wb.upper.status_error = 0;
4667
4668                 /* return some buffers to hardware, one at a time is too slow */
4669                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4670                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4671                         cleaned_count = 0;
4672                 }
4673
4674                 /* use prefetched values */
4675                 rx_desc = next_rxd;
4676                 buffer_info = next_buffer;
4677                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4678         }
4679
4680         rx_ring->next_to_clean = i;
4681         cleaned_count = igb_desc_unused(rx_ring);
4682
4683         if (cleaned_count)
4684                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4685
4686         rx_ring->total_packets += total_packets;
4687         rx_ring->total_bytes += total_bytes;
4688         rx_ring->rx_stats.packets += total_packets;
4689         rx_ring->rx_stats.bytes += total_bytes;
4690         adapter->net_stats.rx_bytes += total_bytes;
4691         adapter->net_stats.rx_packets += total_packets;
4692         return cleaned;
4693 }
4694
4695 /**
4696  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4697  * @adapter: address of board private structure
4698  **/
4699 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4700                                      int cleaned_count)
4701 {
4702         struct igb_adapter *adapter = rx_ring->adapter;
4703         struct net_device *netdev = adapter->netdev;
4704         struct pci_dev *pdev = adapter->pdev;
4705         union e1000_adv_rx_desc *rx_desc;
4706         struct igb_buffer *buffer_info;
4707         struct sk_buff *skb;
4708         unsigned int i;
4709         int bufsz;
4710
4711         i = rx_ring->next_to_use;
4712         buffer_info = &rx_ring->buffer_info[i];
4713
4714         if (adapter->rx_ps_hdr_size)
4715                 bufsz = adapter->rx_ps_hdr_size;
4716         else
4717                 bufsz = adapter->rx_buffer_len;
4718
4719         while (cleaned_count--) {
4720                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4721
4722                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4723                         if (!buffer_info->page) {
4724                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4725                                 if (!buffer_info->page) {
4726                                         adapter->alloc_rx_buff_failed++;
4727                                         goto no_buffers;
4728                                 }
4729                                 buffer_info->page_offset = 0;
4730                         } else {
4731                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4732                         }
4733                         buffer_info->page_dma =
4734                                 pci_map_page(pdev, buffer_info->page,
4735                                              buffer_info->page_offset,
4736                                              PAGE_SIZE / 2,
4737                                              PCI_DMA_FROMDEVICE);
4738                 }
4739
4740                 if (!buffer_info->skb) {
4741                         skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4742                         if (!skb) {
4743                                 adapter->alloc_rx_buff_failed++;
4744                                 goto no_buffers;
4745                         }
4746
4747                         /* Make buffer alignment 2 beyond a 16 byte boundary
4748                          * this will result in a 16 byte aligned IP header after
4749                          * the 14 byte MAC header is removed
4750                          */
4751                         skb_reserve(skb, NET_IP_ALIGN);
4752
4753                         buffer_info->skb = skb;
4754                         buffer_info->dma = pci_map_single(pdev, skb->data,
4755                                                           bufsz,
4756                                                           PCI_DMA_FROMDEVICE);
4757                 }
4758                 /* Refresh the desc even if buffer_addrs didn't change because
4759                  * each write-back erases this info. */
4760                 if (adapter->rx_ps_hdr_size) {
4761                         rx_desc->read.pkt_addr =
4762                              cpu_to_le64(buffer_info->page_dma);
4763                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4764                 } else {
4765                         rx_desc->read.pkt_addr =
4766                              cpu_to_le64(buffer_info->dma);
4767                         rx_desc->read.hdr_addr = 0;
4768                 }
4769
4770                 i++;
4771                 if (i == rx_ring->count)
4772                         i = 0;
4773                 buffer_info = &rx_ring->buffer_info[i];
4774         }
4775
4776 no_buffers:
4777         if (rx_ring->next_to_use != i) {
4778                 rx_ring->next_to_use = i;
4779                 if (i == 0)
4780                         i = (rx_ring->count - 1);
4781                 else
4782                         i--;
4783
4784                 /* Force memory writes to complete before letting h/w
4785                  * know there are new descriptors to fetch.  (Only
4786                  * applicable for weak-ordered memory model archs,
4787                  * such as IA-64). */
4788                 wmb();
4789                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4790         }
4791 }
4792
4793 /**
4794  * igb_mii_ioctl -
4795  * @netdev:
4796  * @ifreq:
4797  * @cmd:
4798  **/
4799 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4800 {
4801         struct igb_adapter *adapter = netdev_priv(netdev);
4802         struct mii_ioctl_data *data = if_mii(ifr);
4803
4804         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4805                 return -EOPNOTSUPP;
4806
4807         switch (cmd) {
4808         case SIOCGMIIPHY:
4809                 data->phy_id = adapter->hw.phy.addr;
4810                 break;
4811         case SIOCGMIIREG:
4812                 if (!capable(CAP_NET_ADMIN))
4813                         return -EPERM;
4814                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4815                                      &data->val_out))
4816                         return -EIO;
4817                 break;
4818         case SIOCSMIIREG:
4819         default:
4820                 return -EOPNOTSUPP;
4821         }
4822         return 0;
4823 }
4824
4825 /**
4826  * igb_hwtstamp_ioctl - control hardware time stamping
4827  * @netdev:
4828  * @ifreq:
4829  * @cmd:
4830  *
4831  * Outgoing time stamping can be enabled and disabled. Play nice and
4832  * disable it when requested, although it shouldn't case any overhead
4833  * when no packet needs it. At most one packet in the queue may be
4834  * marked for time stamping, otherwise it would be impossible to tell
4835  * for sure to which packet the hardware time stamp belongs.
4836  *
4837  * Incoming time stamping has to be configured via the hardware
4838  * filters. Not all combinations are supported, in particular event
4839  * type has to be specified. Matching the kind of event packet is
4840  * not supported, with the exception of "all V2 events regardless of
4841  * level 2 or 4".
4842  *
4843  **/
4844 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4845                               struct ifreq *ifr, int cmd)
4846 {
4847         struct igb_adapter *adapter = netdev_priv(netdev);
4848         struct e1000_hw *hw = &adapter->hw;
4849         struct hwtstamp_config config;
4850         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4851         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4852         u32 tsync_rx_ctl_type = 0;
4853         u32 tsync_rx_cfg = 0;
4854         int is_l4 = 0;
4855         int is_l2 = 0;
4856         short port = 319; /* PTP */
4857         u32 regval;
4858
4859         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4860                 return -EFAULT;
4861
4862         /* reserved for future extensions */
4863         if (config.flags)
4864                 return -EINVAL;
4865
4866         switch (config.tx_type) {
4867         case HWTSTAMP_TX_OFF:
4868                 tsync_tx_ctl_bit = 0;
4869                 break;
4870         case HWTSTAMP_TX_ON:
4871                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4872                 break;
4873         default:
4874                 return -ERANGE;
4875         }
4876
4877         switch (config.rx_filter) {
4878         case HWTSTAMP_FILTER_NONE:
4879                 tsync_rx_ctl_bit = 0;
4880                 break;
4881         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4882         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4883         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4884         case HWTSTAMP_FILTER_ALL:
4885                 /*
4886                  * register TSYNCRXCFG must be set, therefore it is not
4887                  * possible to time stamp both Sync and Delay_Req messages
4888                  * => fall back to time stamping all packets
4889                  */
4890                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4891                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4892                 break;
4893         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4894                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4895                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4896                 is_l4 = 1;
4897                 break;
4898         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4899                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4900                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4901                 is_l4 = 1;
4902                 break;
4903         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4904         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4905                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4906                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4907                 is_l2 = 1;
4908                 is_l4 = 1;
4909                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4910                 break;
4911         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4912         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4913                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4914                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4915                 is_l2 = 1;
4916                 is_l4 = 1;
4917                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4918                 break;
4919         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4920         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4921         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4922                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4923                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4924                 is_l2 = 1;
4925                 break;
4926         default:
4927                 return -ERANGE;
4928         }
4929
4930         /* enable/disable TX */
4931         regval = rd32(E1000_TSYNCTXCTL);
4932         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4933         wr32(E1000_TSYNCTXCTL, regval);
4934
4935         /* enable/disable RX, define which PTP packets are time stamped */
4936         regval = rd32(E1000_TSYNCRXCTL);
4937         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4938         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4939         wr32(E1000_TSYNCRXCTL, regval);
4940         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4941
4942         /*
4943          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4944          *                                          (Ethertype to filter on)
4945          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4946          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4947          */
4948         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4949
4950         /* L4 Queue Filter[0]: only filter by source and destination port */
4951         wr32(E1000_SPQF0, htons(port));
4952         wr32(E1000_IMIREXT(0), is_l4 ?
4953              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4954         wr32(E1000_IMIR(0), is_l4 ?
4955              (htons(port)
4956               | (0<<16) /* immediate interrupt disabled */
4957               | 0 /* (1<<17) bit cleared: do not bypass
4958                      destination port check */)
4959                 : 0);
4960         wr32(E1000_FTQF0, is_l4 ?
4961              (0x11 /* UDP */
4962               | (1<<15) /* VF not compared */
4963               | (1<<27) /* Enable Timestamping */
4964               | (7<<28) /* only source port filter enabled,
4965                            source/target address and protocol
4966                            masked */)
4967              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4968                                       enabled */));
4969
4970         wrfl();
4971
4972         adapter->hwtstamp_config = config;
4973
4974         /* clear TX/RX time stamp registers, just to be sure */
4975         regval = rd32(E1000_TXSTMPH);
4976         regval = rd32(E1000_RXSTMPH);
4977
4978         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4979                 -EFAULT : 0;
4980 }
4981
4982 /**
4983  * igb_ioctl -
4984  * @netdev:
4985  * @ifreq:
4986  * @cmd:
4987  **/
4988 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4989 {
4990         switch (cmd) {
4991         case SIOCGMIIPHY:
4992         case SIOCGMIIREG:
4993         case SIOCSMIIREG:
4994                 return igb_mii_ioctl(netdev, ifr, cmd);
4995         case SIOCSHWTSTAMP:
4996                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4997         default:
4998                 return -EOPNOTSUPP;
4999         }
5000 }
5001
5002 static void igb_vlan_rx_register(struct net_device *netdev,
5003                                  struct vlan_group *grp)
5004 {
5005         struct igb_adapter *adapter = netdev_priv(netdev);
5006         struct e1000_hw *hw = &adapter->hw;
5007         u32 ctrl, rctl;
5008
5009         igb_irq_disable(adapter);
5010         adapter->vlgrp = grp;
5011
5012         if (grp) {
5013                 /* enable VLAN tag insert/strip */
5014                 ctrl = rd32(E1000_CTRL);
5015                 ctrl |= E1000_CTRL_VME;
5016                 wr32(E1000_CTRL, ctrl);
5017
5018                 /* enable VLAN receive filtering */
5019                 rctl = rd32(E1000_RCTL);
5020                 rctl &= ~E1000_RCTL_CFIEN;
5021                 wr32(E1000_RCTL, rctl);
5022                 igb_update_mng_vlan(adapter);
5023         } else {
5024                 /* disable VLAN tag insert/strip */
5025                 ctrl = rd32(E1000_CTRL);
5026                 ctrl &= ~E1000_CTRL_VME;
5027                 wr32(E1000_CTRL, ctrl);
5028
5029                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5030                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5031                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5032                 }
5033         }
5034
5035         igb_rlpml_set(adapter);
5036
5037         if (!test_bit(__IGB_DOWN, &adapter->state))
5038                 igb_irq_enable(adapter);
5039 }
5040
5041 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5042 {
5043         struct igb_adapter *adapter = netdev_priv(netdev);
5044         struct e1000_hw *hw = &adapter->hw;
5045         int pf_id = adapter->vfs_allocated_count;
5046
5047         if ((hw->mng_cookie.status &
5048              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5049             (vid == adapter->mng_vlan_id))
5050                 return;
5051
5052         /* add vid to vlvf if sr-iov is enabled,
5053          * if that fails add directly to filter table */
5054         if (igb_vlvf_set(adapter, vid, true, pf_id))
5055                 igb_vfta_set(hw, vid, true);
5056
5057 }
5058
5059 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5060 {
5061         struct igb_adapter *adapter = netdev_priv(netdev);
5062         struct e1000_hw *hw = &adapter->hw;
5063         int pf_id = adapter->vfs_allocated_count;
5064
5065         igb_irq_disable(adapter);
5066         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5067
5068         if (!test_bit(__IGB_DOWN, &adapter->state))
5069                 igb_irq_enable(adapter);
5070
5071         if ((adapter->hw.mng_cookie.status &
5072              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5073             (vid == adapter->mng_vlan_id)) {
5074                 /* release control to f/w */
5075                 igb_release_hw_control(adapter);
5076                 return;
5077         }
5078
5079         /* remove vid from vlvf if sr-iov is enabled,
5080          * if not in vlvf remove from vfta */
5081         if (igb_vlvf_set(adapter, vid, false, pf_id))
5082                 igb_vfta_set(hw, vid, false);
5083 }
5084
5085 static void igb_restore_vlan(struct igb_adapter *adapter)
5086 {
5087         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5088
5089         if (adapter->vlgrp) {
5090                 u16 vid;
5091                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5092                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5093                                 continue;
5094                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5095                 }
5096         }
5097 }
5098
5099 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5100 {
5101         struct e1000_mac_info *mac = &adapter->hw.mac;
5102
5103         mac->autoneg = 0;
5104
5105         /* Fiber NICs only allow 1000 gbps Full duplex */
5106         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5107                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5108                 dev_err(&adapter->pdev->dev,
5109                         "Unsupported Speed/Duplex configuration\n");
5110                 return -EINVAL;
5111         }
5112
5113         switch (spddplx) {
5114         case SPEED_10 + DUPLEX_HALF:
5115                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5116                 break;
5117         case SPEED_10 + DUPLEX_FULL:
5118                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5119                 break;
5120         case SPEED_100 + DUPLEX_HALF:
5121                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5122                 break;
5123         case SPEED_100 + DUPLEX_FULL:
5124                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5125                 break;
5126         case SPEED_1000 + DUPLEX_FULL:
5127                 mac->autoneg = 1;
5128                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5129                 break;
5130         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5131         default:
5132                 dev_err(&adapter->pdev->dev,
5133                         "Unsupported Speed/Duplex configuration\n");
5134                 return -EINVAL;
5135         }
5136         return 0;
5137 }
5138
5139 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5140 {
5141         struct net_device *netdev = pci_get_drvdata(pdev);
5142         struct igb_adapter *adapter = netdev_priv(netdev);
5143         struct e1000_hw *hw = &adapter->hw;
5144         u32 ctrl, rctl, status;
5145         u32 wufc = adapter->wol;
5146 #ifdef CONFIG_PM
5147         int retval = 0;
5148 #endif
5149
5150         netif_device_detach(netdev);
5151
5152         if (netif_running(netdev))
5153                 igb_close(netdev);
5154
5155         igb_reset_interrupt_capability(adapter);
5156
5157         igb_free_queues(adapter);
5158
5159 #ifdef CONFIG_PM
5160         retval = pci_save_state(pdev);
5161         if (retval)
5162                 return retval;
5163 #endif
5164
5165         status = rd32(E1000_STATUS);
5166         if (status & E1000_STATUS_LU)
5167                 wufc &= ~E1000_WUFC_LNKC;
5168
5169         if (wufc) {
5170                 igb_setup_rctl(adapter);
5171                 igb_set_multi(netdev);
5172
5173                 /* turn on all-multi mode if wake on multicast is enabled */
5174                 if (wufc & E1000_WUFC_MC) {
5175                         rctl = rd32(E1000_RCTL);
5176                         rctl |= E1000_RCTL_MPE;
5177                         wr32(E1000_RCTL, rctl);
5178                 }
5179
5180                 ctrl = rd32(E1000_CTRL);
5181                 /* advertise wake from D3Cold */
5182                 #define E1000_CTRL_ADVD3WUC 0x00100000
5183                 /* phy power management enable */
5184                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5185                 ctrl |= E1000_CTRL_ADVD3WUC;
5186                 wr32(E1000_CTRL, ctrl);
5187
5188                 /* Allow time for pending master requests to run */
5189                 igb_disable_pcie_master(&adapter->hw);
5190
5191                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5192                 wr32(E1000_WUFC, wufc);
5193         } else {
5194                 wr32(E1000_WUC, 0);
5195                 wr32(E1000_WUFC, 0);
5196         }
5197
5198         *enable_wake = wufc || adapter->en_mng_pt;
5199         if (!*enable_wake)
5200                 igb_shutdown_fiber_serdes_link_82575(hw);
5201
5202         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5203          * would have already happened in close and is redundant. */
5204         igb_release_hw_control(adapter);
5205
5206         pci_disable_device(pdev);
5207
5208         return 0;
5209 }
5210
5211 #ifdef CONFIG_PM
5212 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5213 {
5214         int retval;
5215         bool wake;
5216
5217         retval = __igb_shutdown(pdev, &wake);
5218         if (retval)
5219                 return retval;
5220
5221         if (wake) {
5222                 pci_prepare_to_sleep(pdev);
5223         } else {
5224                 pci_wake_from_d3(pdev, false);
5225                 pci_set_power_state(pdev, PCI_D3hot);
5226         }
5227
5228         return 0;
5229 }
5230
5231 static int igb_resume(struct pci_dev *pdev)
5232 {
5233         struct net_device *netdev = pci_get_drvdata(pdev);
5234         struct igb_adapter *adapter = netdev_priv(netdev);
5235         struct e1000_hw *hw = &adapter->hw;
5236         u32 err;
5237
5238         pci_set_power_state(pdev, PCI_D0);
5239         pci_restore_state(pdev);
5240
5241         err = pci_enable_device_mem(pdev);
5242         if (err) {
5243                 dev_err(&pdev->dev,
5244                         "igb: Cannot enable PCI device from suspend\n");
5245                 return err;
5246         }
5247         pci_set_master(pdev);
5248
5249         pci_enable_wake(pdev, PCI_D3hot, 0);
5250         pci_enable_wake(pdev, PCI_D3cold, 0);
5251
5252         igb_set_interrupt_capability(adapter);
5253
5254         if (igb_alloc_queues(adapter)) {
5255                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5256                 return -ENOMEM;
5257         }
5258
5259         /* e1000_power_up_phy(adapter); */
5260
5261         igb_reset(adapter);
5262
5263         /* let the f/w know that the h/w is now under the control of the
5264          * driver. */
5265         igb_get_hw_control(adapter);
5266
5267         wr32(E1000_WUS, ~0);
5268
5269         if (netif_running(netdev)) {
5270                 err = igb_open(netdev);
5271                 if (err)
5272                         return err;
5273         }
5274
5275         netif_device_attach(netdev);
5276
5277         return 0;
5278 }
5279 #endif
5280
5281 static void igb_shutdown(struct pci_dev *pdev)
5282 {
5283         bool wake;
5284
5285         __igb_shutdown(pdev, &wake);
5286
5287         if (system_state == SYSTEM_POWER_OFF) {
5288                 pci_wake_from_d3(pdev, wake);
5289                 pci_set_power_state(pdev, PCI_D3hot);
5290         }
5291 }
5292
5293 #ifdef CONFIG_NET_POLL_CONTROLLER
5294 /*
5295  * Polling 'interrupt' - used by things like netconsole to send skbs
5296  * without having to re-enable interrupts. It's not called while
5297  * the interrupt routine is executing.
5298  */
5299 static void igb_netpoll(struct net_device *netdev)
5300 {
5301         struct igb_adapter *adapter = netdev_priv(netdev);
5302         struct e1000_hw *hw = &adapter->hw;
5303         int i;
5304
5305         if (!adapter->msix_entries) {
5306                 igb_irq_disable(adapter);
5307                 napi_schedule(&adapter->rx_ring[0].napi);
5308                 return;
5309         }
5310
5311         for (i = 0; i < adapter->num_tx_queues; i++) {
5312                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5313                 wr32(E1000_EIMC, tx_ring->eims_value);
5314                 igb_clean_tx_irq(tx_ring);
5315                 wr32(E1000_EIMS, tx_ring->eims_value);
5316         }
5317
5318         for (i = 0; i < adapter->num_rx_queues; i++) {
5319                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5320                 wr32(E1000_EIMC, rx_ring->eims_value);
5321                 napi_schedule(&rx_ring->napi);
5322         }
5323 }
5324 #endif /* CONFIG_NET_POLL_CONTROLLER */
5325
5326 /**
5327  * igb_io_error_detected - called when PCI error is detected
5328  * @pdev: Pointer to PCI device
5329  * @state: The current pci connection state
5330  *
5331  * This function is called after a PCI bus error affecting
5332  * this device has been detected.
5333  */
5334 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5335                                               pci_channel_state_t state)
5336 {
5337         struct net_device *netdev = pci_get_drvdata(pdev);
5338         struct igb_adapter *adapter = netdev_priv(netdev);
5339
5340         netif_device_detach(netdev);
5341
5342         if (state == pci_channel_io_perm_failure)
5343                 return PCI_ERS_RESULT_DISCONNECT;
5344
5345         if (netif_running(netdev))
5346                 igb_down(adapter);
5347         pci_disable_device(pdev);
5348
5349         /* Request a slot slot reset. */
5350         return PCI_ERS_RESULT_NEED_RESET;
5351 }
5352
5353 /**
5354  * igb_io_slot_reset - called after the pci bus has been reset.
5355  * @pdev: Pointer to PCI device
5356  *
5357  * Restart the card from scratch, as if from a cold-boot. Implementation
5358  * resembles the first-half of the igb_resume routine.
5359  */
5360 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5361 {
5362         struct net_device *netdev = pci_get_drvdata(pdev);
5363         struct igb_adapter *adapter = netdev_priv(netdev);
5364         struct e1000_hw *hw = &adapter->hw;
5365         pci_ers_result_t result;
5366         int err;
5367
5368         if (pci_enable_device_mem(pdev)) {
5369                 dev_err(&pdev->dev,
5370                         "Cannot re-enable PCI device after reset.\n");
5371                 result = PCI_ERS_RESULT_DISCONNECT;
5372         } else {
5373                 pci_set_master(pdev);
5374                 pci_restore_state(pdev);
5375
5376                 pci_enable_wake(pdev, PCI_D3hot, 0);
5377                 pci_enable_wake(pdev, PCI_D3cold, 0);
5378
5379                 igb_reset(adapter);
5380                 wr32(E1000_WUS, ~0);
5381                 result = PCI_ERS_RESULT_RECOVERED;
5382         }
5383
5384         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5385         if (err) {
5386                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5387                         "failed 0x%0x\n", err);
5388                 /* non-fatal, continue */
5389         }
5390
5391         return result;
5392 }
5393
5394 /**
5395  * igb_io_resume - called when traffic can start flowing again.
5396  * @pdev: Pointer to PCI device
5397  *
5398  * This callback is called when the error recovery driver tells us that
5399  * its OK to resume normal operation. Implementation resembles the
5400  * second-half of the igb_resume routine.
5401  */
5402 static void igb_io_resume(struct pci_dev *pdev)
5403 {
5404         struct net_device *netdev = pci_get_drvdata(pdev);
5405         struct igb_adapter *adapter = netdev_priv(netdev);
5406
5407         if (netif_running(netdev)) {
5408                 if (igb_up(adapter)) {
5409                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5410                         return;
5411                 }
5412         }
5413
5414         netif_device_attach(netdev);
5415
5416         /* let the f/w know that the h/w is now under the control of the
5417          * driver. */
5418         igb_get_hw_control(adapter);
5419 }
5420
5421 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5422 {
5423         u32 reg_data;
5424
5425         reg_data = rd32(E1000_VMOLR(vfn));
5426         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5427                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5428                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5429                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5430                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5431         wr32(E1000_VMOLR(vfn), reg_data);
5432 }
5433
5434 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5435                                  int vfn)
5436 {
5437         struct e1000_hw *hw = &adapter->hw;
5438         u32 vmolr;
5439
5440         vmolr = rd32(E1000_VMOLR(vfn));
5441         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5442         vmolr |= size | E1000_VMOLR_LPE;
5443         wr32(E1000_VMOLR(vfn), vmolr);
5444
5445         return 0;
5446 }
5447
5448 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5449 {
5450         u32 reg_data;
5451
5452         reg_data = rd32(E1000_RAH(entry));
5453         reg_data &= ~E1000_RAH_POOL_MASK;
5454         reg_data |= E1000_RAH_POOL_1 << pool;;
5455         wr32(E1000_RAH(entry), reg_data);
5456 }
5457
5458 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5459                                   int entry_count, u16 total_rar_filters)
5460 {
5461         struct e1000_hw *hw = &adapter->hw;
5462         int i = adapter->vfs_allocated_count + 1;
5463
5464         if ((i + entry_count) < total_rar_filters)
5465                 total_rar_filters = i + entry_count;
5466
5467         for (; i < total_rar_filters; i++)
5468                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5469 }
5470
5471 static int igb_set_vf_mac(struct igb_adapter *adapter,
5472                           int vf, unsigned char *mac_addr)
5473 {
5474         struct e1000_hw *hw = &adapter->hw;
5475         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5476
5477         igb_rar_set(hw, mac_addr, rar_entry);
5478
5479         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5480
5481         igb_set_rah_pool(hw, vf, rar_entry);
5482
5483         return 0;
5484 }
5485
5486 static void igb_vmm_control(struct igb_adapter *adapter)
5487 {
5488         struct e1000_hw *hw = &adapter->hw;
5489         u32 reg_data;
5490
5491         if (!adapter->vfs_allocated_count)
5492                 return;
5493
5494         /* VF's need PF reset indication before they
5495          * can send/receive mail */
5496         reg_data = rd32(E1000_CTRL_EXT);
5497         reg_data |= E1000_CTRL_EXT_PFRSTD;
5498         wr32(E1000_CTRL_EXT, reg_data);
5499
5500         igb_vmdq_set_loopback_pf(hw, true);
5501         igb_vmdq_set_replication_pf(hw, true);
5502 }
5503
5504 /* igb_main.c */