drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/mii.h>
  38 #include <linux/ethtool.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/pci.h>
  41 #include <linux/pci-aspm.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/aer.h>
  46 #ifdef CONFIG_IGB_DCA
  47 #include <linux/dca.h>
  48 #endif
  49 #include "igb.h"
  50
  51 #define DRV_VERSION "1.3.16-k2"
  52 char igb_driver_name[] = "igb";
  53 char igb_driver_version[] = DRV_VERSION;
  54 static const char igb_driver_string[] =
  55                                 "Intel(R) Gigabit Ethernet Network Driver";
  56 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  57
  58 static const struct e1000_info *igb_info_tbl[] = {
  59         [board_82575] = &e1000_82575_info,
  60 };
  61
  62 static struct pci_device_id igb_pci_tbl[] = {
  63         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  69         /* required last entry */
  70         {0, }
  71 };
  72
  73 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  74
  75 void igb_reset(struct igb_adapter *);
  76 static int igb_setup_all_tx_resources(struct igb_adapter *);
  77 static int igb_setup_all_rx_resources(struct igb_adapter *);
  78 static void igb_free_all_tx_resources(struct igb_adapter *);
  79 static void igb_free_all_rx_resources(struct igb_adapter *);
  80 void igb_update_stats(struct igb_adapter *);
  81 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  82 static void __devexit igb_remove(struct pci_dev *pdev);
  83 static int igb_sw_init(struct igb_adapter *);
  84 static int igb_open(struct net_device *);
  85 static int igb_close(struct net_device *);
  86 static void igb_configure_tx(struct igb_adapter *);
  87 static void igb_configure_rx(struct igb_adapter *);
  88 static void igb_setup_rctl(struct igb_adapter *);
  89 static void igb_clean_all_tx_rings(struct igb_adapter *);
  90 static void igb_clean_all_rx_rings(struct igb_adapter *);
  91 static void igb_clean_tx_ring(struct igb_ring *);
  92 static void igb_clean_rx_ring(struct igb_ring *);
  93 static void igb_set_multi(struct net_device *);
  94 static void igb_update_phy_info(unsigned long);
  95 static void igb_watchdog(unsigned long);
  96 static void igb_watchdog_task(struct work_struct *);
  97 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
  98                                   struct igb_ring *);
  99 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 100 static struct net_device_stats *igb_get_stats(struct net_device *);
 101 static int igb_change_mtu(struct net_device *, int);
 102 static int igb_set_mac(struct net_device *, void *);
 103 static irqreturn_t igb_intr(int irq, void *);
 104 static irqreturn_t igb_intr_msi(int irq, void *);
 105 static irqreturn_t igb_msix_other(int irq, void *);
 106 static irqreturn_t igb_msix_rx(int irq, void *);
 107 static irqreturn_t igb_msix_tx(int irq, void *);
 108 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
 109 #ifdef CONFIG_IGB_DCA
 110 static void igb_update_rx_dca(struct igb_ring *);
 111 static void igb_update_tx_dca(struct igb_ring *);
 112 static void igb_setup_dca(struct igb_adapter *);
 113 #endif /* CONFIG_IGB_DCA */
 114 static bool igb_clean_tx_irq(struct igb_ring *);
 115 static int igb_poll(struct napi_struct *, int);
 116 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 117 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 118 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 119 static void igb_tx_timeout(struct net_device *);
 120 static void igb_reset_task(struct work_struct *);
 121 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 122 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 123 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 124 static void igb_restore_vlan(struct igb_adapter *);
 125
 126 static int igb_suspend(struct pci_dev *, pm_message_t);
 127 #ifdef CONFIG_PM
 128 static int igb_resume(struct pci_dev *);
 129 #endif
 130 static void igb_shutdown(struct pci_dev *);
 131 #ifdef CONFIG_IGB_DCA
 132 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 133 static struct notifier_block dca_notifier = {
 134         .notifier_call  = igb_notify_dca,
 135         .next           = NULL,
 136         .priority       = 0
 137 };
 138 #endif
 139
 140 #ifdef CONFIG_NET_POLL_CONTROLLER
 141 /* for netdump / net console */
 142 static void igb_netpoll(struct net_device *);
 143 #endif
 144
 145 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 146                      pci_channel_state_t);
 147 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 148 static void igb_io_resume(struct pci_dev *);
 149
 150 static struct pci_error_handlers igb_err_handler = {
 151         .error_detected = igb_io_error_detected,
 152         .slot_reset = igb_io_slot_reset,
 153         .resume = igb_io_resume,
 154 };
 155
 156
 157 static struct pci_driver igb_driver = {
 158         .name     = igb_driver_name,
 159         .id_table = igb_pci_tbl,
 160         .probe    = igb_probe,
 161         .remove   = __devexit_p(igb_remove),
 162 #ifdef CONFIG_PM
 163         /* Power Managment Hooks */
 164         .suspend  = igb_suspend,
 165         .resume   = igb_resume,
 166 #endif
 167         .shutdown = igb_shutdown,
 168         .err_handler = &igb_err_handler
 169 };
 170
 171 static int global_quad_port_a; /* global quad port a indication */
 172
 173 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 174 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 175 MODULE_LICENSE("GPL");
 176 MODULE_VERSION(DRV_VERSION);
 177
 178 #ifdef DEBUG
 179 /**
 180  * igb_get_hw_dev_name - return device name string
 181  * used by hardware layer to print debugging information
 182  **/
 183 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 184 {
 185         struct igb_adapter *adapter = hw->back;
 186         return adapter->netdev->name;
 187 }
 188 #endif
 189
 190 /**
 191  * igb_init_module - Driver Registration Routine
 192  *
 193  * igb_init_module is the first routine called when the driver is
 194  * loaded. All it does is register with the PCI subsystem.
 195  **/
 196 static int __init igb_init_module(void)
 197 {
 198         int ret;
 199         printk(KERN_INFO "%s - version %s\n",
 200                igb_driver_string, igb_driver_version);
 201
 202         printk(KERN_INFO "%s\n", igb_copyright);
 203
 204         global_quad_port_a = 0;
 205
 206 #ifdef CONFIG_IGB_DCA
 207         dca_register_notify(&dca_notifier);
 208 #endif
 209
 210         ret = pci_register_driver(&igb_driver);
 211         return ret;
 212 }
 213
 214 module_init(igb_init_module);
 215
 216 /**
 217  * igb_exit_module - Driver Exit Cleanup Routine
 218  *
 219  * igb_exit_module is called just before the driver is removed
 220  * from memory.
 221  **/
 222 static void __exit igb_exit_module(void)
 223 {
 224 #ifdef CONFIG_IGB_DCA
 225         dca_unregister_notify(&dca_notifier);
 226 #endif
 227         pci_unregister_driver(&igb_driver);
 228 }
 229
 230 module_exit(igb_exit_module);
 231
 232 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 233 /**
 234  * igb_cache_ring_register - Descriptor ring to register mapping
 235  * @adapter: board private structure to initialize
 236  *
 237  * Once we know the feature-set enabled for the device, we'll cache
 238  * the register offset the descriptor ring is assigned to.
 239  **/
 240 static void igb_cache_ring_register(struct igb_adapter *adapter)
 241 {
 242         int i;
 243
 244         switch (adapter->hw.mac.type) {
 245         case e1000_82576:
 246                 /* The queues are allocated for virtualization such that VF 0
 247                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 248                  * In order to avoid collision we start at the first free queue
 249                  * and continue consuming queues in the same sequence
 250                  */
 251                 for (i = 0; i < adapter->num_rx_queues; i++)
 252                         adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
 253                 for (i = 0; i < adapter->num_tx_queues; i++)
 254                         adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
 255                 break;
 256         case e1000_82575:
 257         default:
 258                 for (i = 0; i < adapter->num_rx_queues; i++)
 259                         adapter->rx_ring[i].reg_idx = i;
 260                 for (i = 0; i < adapter->num_tx_queues; i++)
 261                         adapter->tx_ring[i].reg_idx = i;
 262                 break;
 263         }
 264 }
 265
 266 /**
 267  * igb_alloc_queues - Allocate memory for all rings
 268  * @adapter: board private structure to initialize
 269  *
 270  * We allocate one ring per queue at run-time since we don't know the
 271  * number of queues at compile-time.
 272  **/
 273 static int igb_alloc_queues(struct igb_adapter *adapter)
 274 {
 275         int i;
 276
 277         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 278                                    sizeof(struct igb_ring), GFP_KERNEL);
 279         if (!adapter->tx_ring)
 280                 return -ENOMEM;
 281
 282         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 283                                    sizeof(struct igb_ring), GFP_KERNEL);
 284         if (!adapter->rx_ring) {
 285                 kfree(adapter->tx_ring);
 286                 return -ENOMEM;
 287         }
 288
 289         adapter->rx_ring->buddy = adapter->tx_ring;
 290
 291         for (i = 0; i < adapter->num_tx_queues; i++) {
 292                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 293                 ring->count = adapter->tx_ring_count;
 294                 ring->adapter = adapter;
 295                 ring->queue_index = i;
 296         }
 297         for (i = 0; i < adapter->num_rx_queues; i++) {
 298                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 299                 ring->count = adapter->rx_ring_count;
 300                 ring->adapter = adapter;
 301                 ring->queue_index = i;
 302                 ring->itr_register = E1000_ITR;
 303
 304                 /* set a default napi handler for each rx_ring */
 305                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 306         }
 307
 308         igb_cache_ring_register(adapter);
 309         return 0;
 310 }
 311
 312 static void igb_free_queues(struct igb_adapter *adapter)
 313 {
 314         int i;
 315
 316         for (i = 0; i < adapter->num_rx_queues; i++)
 317                 netif_napi_del(&adapter->rx_ring[i].napi);
 318
 319         kfree(adapter->tx_ring);
 320         kfree(adapter->rx_ring);
 321 }
 322
 323 #define IGB_N0_QUEUE -1
 324 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 325                               int tx_queue, int msix_vector)
 326 {
 327         u32 msixbm = 0;
 328         struct e1000_hw *hw = &adapter->hw;
 329         u32 ivar, index;
 330
 331         switch (hw->mac.type) {
 332         case e1000_82575:
 333                 /* The 82575 assigns vectors using a bitmask, which matches the
 334                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 335                    or more queues to a vector, we write the appropriate bits
 336                    into the MSIXBM register for that vector. */
 337                 if (rx_queue > IGB_N0_QUEUE) {
 338                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 339                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 340                 }
 341                 if (tx_queue > IGB_N0_QUEUE) {
 342                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 343                         adapter->tx_ring[tx_queue].eims_value =
 344                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 345                 }
 346                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 347                 break;
 348         case e1000_82576:
 349                 /* 82576 uses a table-based method for assigning vectors.
 350                    Each queue has a single entry in the table to which we write
 351                    a vector number along with a "valid" bit.  Sadly, the layout
 352                    of the table is somewhat counterintuitive. */
 353                 if (rx_queue > IGB_N0_QUEUE) {
 354                         index = (rx_queue >> 1);
 355                         ivar = array_rd32(E1000_IVAR0, index);
 356                         if (rx_queue & 0x1) {
 357                                 /* vector goes into third byte of register */
 358                                 ivar = ivar & 0xFF00FFFF;
 359                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 360                         } else {
 361                                 /* vector goes into low byte of register */
 362                                 ivar = ivar & 0xFFFFFF00;
 363                                 ivar |= msix_vector | E1000_IVAR_VALID;
 364                         }
 365                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 366                         array_wr32(E1000_IVAR0, index, ivar);
 367                 }
 368                 if (tx_queue > IGB_N0_QUEUE) {
 369                         index = (tx_queue >> 1);
 370                         ivar = array_rd32(E1000_IVAR0, index);
 371                         if (tx_queue & 0x1) {
 372                                 /* vector goes into high byte of register */
 373                                 ivar = ivar & 0x00FFFFFF;
 374                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 375                         } else {
 376                                 /* vector goes into second byte of register */
 377                                 ivar = ivar & 0xFFFF00FF;
 378                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 379                         }
 380                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 381                         array_wr32(E1000_IVAR0, index, ivar);
 382                 }
 383                 break;
 384         default:
 385                 BUG();
 386                 break;
 387         }
 388 }
 389
 390 /**
 391  * igb_configure_msix - Configure MSI-X hardware
 392  *
 393  * igb_configure_msix sets up the hardware to properly
 394  * generate MSI-X interrupts.
 395  **/
 396 static void igb_configure_msix(struct igb_adapter *adapter)
 397 {
 398         u32 tmp;
 399         int i, vector = 0;
 400         struct e1000_hw *hw = &adapter->hw;
 401
 402         adapter->eims_enable_mask = 0;
 403         if (hw->mac.type == e1000_82576)
 404                 /* Turn on MSI-X capability first, or our settings
 405                  * won't stick.  And it will take days to debug. */
 406                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 407                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 408                                    E1000_GPIE_NSICR);
 409
 410         for (i = 0; i < adapter->num_tx_queues; i++) {
 411                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 412                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 413                 adapter->eims_enable_mask |= tx_ring->eims_value;
 414                 if (tx_ring->itr_val)
 415                         writel(tx_ring->itr_val,
 416                                hw->hw_addr + tx_ring->itr_register);
 417                 else
 418                         writel(1, hw->hw_addr + tx_ring->itr_register);
 419         }
 420
 421         for (i = 0; i < adapter->num_rx_queues; i++) {
 422                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 423                 rx_ring->buddy = NULL;
 424                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 425                 adapter->eims_enable_mask |= rx_ring->eims_value;
 426                 if (rx_ring->itr_val)
 427                         writel(rx_ring->itr_val,
 428                                hw->hw_addr + rx_ring->itr_register);
 429                 else
 430                         writel(1, hw->hw_addr + rx_ring->itr_register);
 431         }
 432
 433
 434         /* set vector for other causes, i.e. link changes */
 435         switch (hw->mac.type) {
 436         case e1000_82575:
 437                 array_wr32(E1000_MSIXBM(0), vector++,
 438                                       E1000_EIMS_OTHER);
 439
 440                 tmp = rd32(E1000_CTRL_EXT);
 441                 /* enable MSI-X PBA support*/
 442                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 443
 444                 /* Auto-Mask interrupts upon ICR read. */
 445                 tmp |= E1000_CTRL_EXT_EIAME;
 446                 tmp |= E1000_CTRL_EXT_IRCA;
 447
 448                 wr32(E1000_CTRL_EXT, tmp);
 449                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 450                 adapter->eims_other = E1000_EIMS_OTHER;
 451
 452                 break;
 453
 454         case e1000_82576:
 455                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 456                 wr32(E1000_IVAR_MISC, tmp);
 457
 458                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 459                 adapter->eims_other = 1 << (vector - 1);
 460                 break;
 461         default:
 462                 /* do nothing, since nothing else supports MSI-X */
 463                 break;
 464         } /* switch (hw->mac.type) */
 465         wrfl();
 466 }
 467
 468 /**
 469  * igb_request_msix - Initialize MSI-X interrupts
 470  *
 471  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 472  * kernel.
 473  **/
 474 static int igb_request_msix(struct igb_adapter *adapter)
 475 {
 476         struct net_device *netdev = adapter->netdev;
 477         int i, err = 0, vector = 0;
 478
 479         vector = 0;
 480
 481         for (i = 0; i < adapter->num_tx_queues; i++) {
 482                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 483                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 484                 err = request_irq(adapter->msix_entries[vector].vector,
 485                                   &igb_msix_tx, 0, ring->name,
 486                                   &(adapter->tx_ring[i]));
 487                 if (err)
 488                         goto out;
 489                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 490                 ring->itr_val = 976; /* ~4000 ints/sec */
 491                 vector++;
 492         }
 493         for (i = 0; i < adapter->num_rx_queues; i++) {
 494                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 495                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 496                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 497                 else
 498                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 499                 err = request_irq(adapter->msix_entries[vector].vector,
 500                                   &igb_msix_rx, 0, ring->name,
 501                                   &(adapter->rx_ring[i]));
 502                 if (err)
 503                         goto out;
 504                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 505                 ring->itr_val = adapter->itr;
 506                 /* overwrite the poll routine for MSIX, we've already done
 507                  * netif_napi_add */
 508                 ring->napi.poll = &igb_clean_rx_ring_msix;
 509                 vector++;
 510         }
 511
 512         err = request_irq(adapter->msix_entries[vector].vector,
 513                           &igb_msix_other, 0, netdev->name, netdev);
 514         if (err)
 515                 goto out;
 516
 517         igb_configure_msix(adapter);
 518         return 0;
 519 out:
 520         return err;
 521 }
 522
 523 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 524 {
 525         if (adapter->msix_entries) {
 526                 pci_disable_msix(adapter->pdev);
 527                 kfree(adapter->msix_entries);
 528                 adapter->msix_entries = NULL;
 529         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 530                 pci_disable_msi(adapter->pdev);
 531         return;
 532 }
 533
 534
 535 /**
 536  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 537  *
 538  * Attempt to configure interrupts using the best available
 539  * capabilities of the hardware and kernel.
 540  **/
 541 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 542 {
 543         int err;
 544         int numvecs, i;
 545
 546         /* Number of supported queues. */
 547         /* Having more queues than CPUs doesn't make sense. */
 548         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 549         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 550
 551         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 552         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 553                                         GFP_KERNEL);
 554         if (!adapter->msix_entries)
 555                 goto msi_only;
 556
 557         for (i = 0; i < numvecs; i++)
 558                 adapter->msix_entries[i].entry = i;
 559
 560         err = pci_enable_msix(adapter->pdev,
 561                               adapter->msix_entries,
 562                               numvecs);
 563         if (err == 0)
 564                 goto out;
 565
 566         igb_reset_interrupt_capability(adapter);
 567
 568         /* If we can't do MSI-X, try MSI */
 569 msi_only:
 570         adapter->num_rx_queues = 1;
 571         adapter->num_tx_queues = 1;
 572         if (!pci_enable_msi(adapter->pdev))
 573                 adapter->flags |= IGB_FLAG_HAS_MSI;
 574 out:
 575         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 576         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 577         return;
 578 }
 579
 580 /**
 581  * igb_request_irq - initialize interrupts
 582  *
 583  * Attempts to configure interrupts using the best available
 584  * capabilities of the hardware and kernel.
 585  **/
 586 static int igb_request_irq(struct igb_adapter *adapter)
 587 {
 588         struct net_device *netdev = adapter->netdev;
 589         struct e1000_hw *hw = &adapter->hw;
 590         int err = 0;
 591
 592         if (adapter->msix_entries) {
 593                 err = igb_request_msix(adapter);
 594                 if (!err)
 595                         goto request_done;
 596                 /* fall back to MSI */
 597                 igb_reset_interrupt_capability(adapter);
 598                 if (!pci_enable_msi(adapter->pdev))
 599                         adapter->flags |= IGB_FLAG_HAS_MSI;
 600                 igb_free_all_tx_resources(adapter);
 601                 igb_free_all_rx_resources(adapter);
 602                 adapter->num_rx_queues = 1;
 603                 igb_alloc_queues(adapter);
 604         } else {
 605                 switch (hw->mac.type) {
 606                 case e1000_82575:
 607                         wr32(E1000_MSIXBM(0),
 608                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 609                         break;
 610                 case e1000_82576:
 611                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 612                         break;
 613                 default:
 614                         break;
 615                 }
 616         }
 617
 618         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 619                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 620                                   netdev->name, netdev);
 621                 if (!err)
 622                         goto request_done;
 623                 /* fall back to legacy interrupts */
 624                 igb_reset_interrupt_capability(adapter);
 625                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 626         }
 627
 628         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 629                           netdev->name, netdev);
 630
 631         if (err)
 632                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 633                         err);
 634
 635 request_done:
 636         return err;
 637 }
 638
 639 static void igb_free_irq(struct igb_adapter *adapter)
 640 {
 641         struct net_device *netdev = adapter->netdev;
 642
 643         if (adapter->msix_entries) {
 644                 int vector = 0, i;
 645
 646                 for (i = 0; i < adapter->num_tx_queues; i++)
 647                         free_irq(adapter->msix_entries[vector++].vector,
 648                                 &(adapter->tx_ring[i]));
 649                 for (i = 0; i < adapter->num_rx_queues; i++)
 650                         free_irq(adapter->msix_entries[vector++].vector,
 651                                 &(adapter->rx_ring[i]));
 652
 653                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 654                 return;
 655         }
 656
 657         free_irq(adapter->pdev->irq, netdev);
 658 }
 659
 660 /**
 661  * igb_irq_disable - Mask off interrupt generation on the NIC
 662  * @adapter: board private structure
 663  **/
 664 static void igb_irq_disable(struct igb_adapter *adapter)
 665 {
 666         struct e1000_hw *hw = &adapter->hw;
 667
 668         if (adapter->msix_entries) {
 669                 wr32(E1000_EIAM, 0);
 670                 wr32(E1000_EIMC, ~0);
 671                 wr32(E1000_EIAC, 0);
 672         }
 673
 674         wr32(E1000_IAM, 0);
 675         wr32(E1000_IMC, ~0);
 676         wrfl();
 677         synchronize_irq(adapter->pdev->irq);
 678 }
 679
 680 /**
 681  * igb_irq_enable - Enable default interrupt generation settings
 682  * @adapter: board private structure
 683  **/
 684 static void igb_irq_enable(struct igb_adapter *adapter)
 685 {
 686         struct e1000_hw *hw = &adapter->hw;
 687
 688         if (adapter->msix_entries) {
 689                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 690                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 691                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 692                 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
 693         } else {
 694                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 695                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 696         }
 697 }
 698
 699 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 700 {
 701         struct net_device *netdev = adapter->netdev;
 702         u16 vid = adapter->hw.mng_cookie.vlan_id;
 703         u16 old_vid = adapter->mng_vlan_id;
 704         if (adapter->vlgrp) {
 705                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 706                         if (adapter->hw.mng_cookie.status &
 707                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 708                                 igb_vlan_rx_add_vid(netdev, vid);
 709                                 adapter->mng_vlan_id = vid;
 710                         } else
 711                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 712
 713                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 714                                         (vid != old_vid) &&
 715                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 716                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 717                 } else
 718                         adapter->mng_vlan_id = vid;
 719         }
 720 }
 721
 722 /**
 723  * igb_release_hw_control - release control of the h/w to f/w
 724  * @adapter: address of board private structure
 725  *
 726  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 727  * For ASF and Pass Through versions of f/w this means that the
 728  * driver is no longer loaded.
 729  *
 730  **/
 731 static void igb_release_hw_control(struct igb_adapter *adapter)
 732 {
 733         struct e1000_hw *hw = &adapter->hw;
 734         u32 ctrl_ext;
 735
 736         /* Let firmware take over control of h/w */
 737         ctrl_ext = rd32(E1000_CTRL_EXT);
 738         wr32(E1000_CTRL_EXT,
 739                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 740 }
 741
 742
 743 /**
 744  * igb_get_hw_control - get control of the h/w from f/w
 745  * @adapter: address of board private structure
 746  *
 747  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 748  * For ASF and Pass Through versions of f/w this means that
 749  * the driver is loaded.
 750  *
 751  **/
 752 static void igb_get_hw_control(struct igb_adapter *adapter)
 753 {
 754         struct e1000_hw *hw = &adapter->hw;
 755         u32 ctrl_ext;
 756
 757         /* Let firmware know the driver has taken over */
 758         ctrl_ext = rd32(E1000_CTRL_EXT);
 759         wr32(E1000_CTRL_EXT,
 760                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 761 }
 762
 763 /**
 764  * igb_configure - configure the hardware for RX and TX
 765  * @adapter: private board structure
 766  **/
 767 static void igb_configure(struct igb_adapter *adapter)
 768 {
 769         struct net_device *netdev = adapter->netdev;
 770         int i;
 771
 772         igb_get_hw_control(adapter);
 773         igb_set_multi(netdev);
 774
 775         igb_restore_vlan(adapter);
 776
 777         igb_configure_tx(adapter);
 778         igb_setup_rctl(adapter);
 779         igb_configure_rx(adapter);
 780
 781         igb_rx_fifo_flush_82575(&adapter->hw);
 782
 783         /* call IGB_DESC_UNUSED which always leaves
 784          * at least 1 descriptor unused to make sure
 785          * next_to_use != next_to_clean */
 786         for (i = 0; i < adapter->num_rx_queues; i++) {
 787                 struct igb_ring *ring = &adapter->rx_ring[i];
 788                 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
 789         }
 790
 791
 792         adapter->tx_queue_len = netdev->tx_queue_len;
 793 }
 794
 795
 796 /**
 797  * igb_up - Open the interface and prepare it to handle traffic
 798  * @adapter: board private structure
 799  **/
 800
 801 int igb_up(struct igb_adapter *adapter)
 802 {
 803         struct e1000_hw *hw = &adapter->hw;
 804         int i;
 805
 806         /* hardware has been reset, we need to reload some things */
 807         igb_configure(adapter);
 808
 809         clear_bit(__IGB_DOWN, &adapter->state);
 810
 811         for (i = 0; i < adapter->num_rx_queues; i++)
 812                 napi_enable(&adapter->rx_ring[i].napi);
 813         if (adapter->msix_entries)
 814                 igb_configure_msix(adapter);
 815
 816         /* Clear any pending interrupts. */
 817         rd32(E1000_ICR);
 818         igb_irq_enable(adapter);
 819
 820         /* Fire a link change interrupt to start the watchdog. */
 821         wr32(E1000_ICS, E1000_ICS_LSC);
 822         return 0;
 823 }
 824
 825 void igb_down(struct igb_adapter *adapter)
 826 {
 827         struct e1000_hw *hw = &adapter->hw;
 828         struct net_device *netdev = adapter->netdev;
 829         u32 tctl, rctl;
 830         int i;
 831
 832         /* signal that we're down so the interrupt handler does not
 833          * reschedule our watchdog timer */
 834         set_bit(__IGB_DOWN, &adapter->state);
 835
 836         /* disable receives in the hardware */
 837         rctl = rd32(E1000_RCTL);
 838         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 839         /* flush and sleep below */
 840
 841         netif_tx_stop_all_queues(netdev);
 842
 843         /* disable transmits in the hardware */
 844         tctl = rd32(E1000_TCTL);
 845         tctl &= ~E1000_TCTL_EN;
 846         wr32(E1000_TCTL, tctl);
 847         /* flush both disables and wait for them to finish */
 848         wrfl();
 849         msleep(10);
 850
 851         for (i = 0; i < adapter->num_rx_queues; i++)
 852                 napi_disable(&adapter->rx_ring[i].napi);
 853
 854         igb_irq_disable(adapter);
 855
 856         del_timer_sync(&adapter->watchdog_timer);
 857         del_timer_sync(&adapter->phy_info_timer);
 858
 859         netdev->tx_queue_len = adapter->tx_queue_len;
 860         netif_carrier_off(netdev);
 861
 862         /* record the stats before reset*/
 863         igb_update_stats(adapter);
 864
 865         adapter->link_speed = 0;
 866         adapter->link_duplex = 0;
 867
 868         if (!pci_channel_offline(adapter->pdev))
 869                 igb_reset(adapter);
 870         igb_clean_all_tx_rings(adapter);
 871         igb_clean_all_rx_rings(adapter);
 872 }
 873
 874 void igb_reinit_locked(struct igb_adapter *adapter)
 875 {
 876         WARN_ON(in_interrupt());
 877         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 878                 msleep(1);
 879         igb_down(adapter);
 880         igb_up(adapter);
 881         clear_bit(__IGB_RESETTING, &adapter->state);
 882 }
 883
 884 void igb_reset(struct igb_adapter *adapter)
 885 {
 886         struct e1000_hw *hw = &adapter->hw;
 887         struct e1000_mac_info *mac = &hw->mac;
 888         struct e1000_fc_info *fc = &hw->fc;
 889         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
 890         u16 hwm;
 891
 892         /* Repartition Pba for greater than 9k mtu
 893          * To take effect CTRL.RST is required.
 894          */
 895         switch (mac->type) {
 896         case e1000_82576:
 897                 pba = E1000_PBA_64K;
 898                 break;
 899         case e1000_82575:
 900         default:
 901                 pba = E1000_PBA_34K;
 902                 break;
 903         }
 904
 905         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
 906             (mac->type < e1000_82576)) {
 907                 /* adjust PBA for jumbo frames */
 908                 wr32(E1000_PBA, pba);
 909
 910                 /* To maintain wire speed transmits, the Tx FIFO should be
 911                  * large enough to accommodate two full transmit packets,
 912                  * rounded up to the next 1KB and expressed in KB.  Likewise,
 913                  * the Rx FIFO should be large enough to accommodate at least
 914                  * one full receive packet and is similarly rounded up and
 915                  * expressed in KB. */
 916                 pba = rd32(E1000_PBA);
 917                 /* upper 16 bits has Tx packet buffer allocation size in KB */
 918                 tx_space = pba >> 16;
 919                 /* lower 16 bits has Rx packet buffer allocation size in KB */
 920                 pba &= 0xffff;
 921                 /* the tx fifo also stores 16 bytes of information about the tx
 922                  * but don't include ethernet FCS because hardware appends it */
 923                 min_tx_space = (adapter->max_frame_size +
 924                                 sizeof(struct e1000_tx_desc) -
 925                                 ETH_FCS_LEN) * 2;
 926                 min_tx_space = ALIGN(min_tx_space, 1024);
 927                 min_tx_space >>= 10;
 928                 /* software strips receive CRC, so leave room for it */
 929                 min_rx_space = adapter->max_frame_size;
 930                 min_rx_space = ALIGN(min_rx_space, 1024);
 931                 min_rx_space >>= 10;
 932
 933                 /* If current Tx allocation is less than the min Tx FIFO size,
 934                  * and the min Tx FIFO size is less than the current Rx FIFO
 935                  * allocation, take space away from current Rx allocation */
 936                 if (tx_space < min_tx_space &&
 937                     ((min_tx_space - tx_space) < pba)) {
 938                         pba = pba - (min_tx_space - tx_space);
 939
 940                         /* if short on rx space, rx wins and must trump tx
 941                          * adjustment */
 942                         if (pba < min_rx_space)
 943                                 pba = min_rx_space;
 944                 }
 945                 wr32(E1000_PBA, pba);
 946         }
 947
 948         /* flow control settings */
 949         /* The high water mark must be low enough to fit one full frame
 950          * (or the size used for early receive) above it in the Rx FIFO.
 951          * Set it to the lower of:
 952          * - 90% of the Rx FIFO size, or
 953          * - the full Rx FIFO size minus one full frame */
 954         hwm = min(((pba << 10) * 9 / 10),
 955                         ((pba << 10) - 2 * adapter->max_frame_size));
 956
 957         if (mac->type < e1000_82576) {
 958                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
 959                 fc->low_water = fc->high_water - 8;
 960         } else {
 961                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
 962                 fc->low_water = fc->high_water - 16;
 963         }
 964         fc->pause_time = 0xFFFF;
 965         fc->send_xon = 1;
 966         fc->type = fc->original_type;
 967
 968         /* Allow time for pending master requests to run */
 969         adapter->hw.mac.ops.reset_hw(&adapter->hw);
 970         wr32(E1000_WUC, 0);
 971
 972         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
 973                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
 974
 975         igb_update_mng_vlan(adapter);
 976
 977         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
 978         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
 979
 980         igb_reset_adaptive(&adapter->hw);
 981         igb_get_phy_info(&adapter->hw);
 982 }
 983
 984 static const struct net_device_ops igb_netdev_ops = {
 985         .ndo_open               = igb_open,
 986         .ndo_stop               = igb_close,
 987         .ndo_start_xmit         = igb_xmit_frame_adv,
 988         .ndo_get_stats          = igb_get_stats,
 989         .ndo_set_multicast_list = igb_set_multi,
 990         .ndo_set_mac_address    = igb_set_mac,
 991         .ndo_change_mtu         = igb_change_mtu,
 992         .ndo_do_ioctl           = igb_ioctl,
 993         .ndo_tx_timeout         = igb_tx_timeout,
 994         .ndo_validate_addr      = eth_validate_addr,
 995         .ndo_vlan_rx_register   = igb_vlan_rx_register,
 996         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
 997         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
 998 #ifdef CONFIG_NET_POLL_CONTROLLER
 999         .ndo_poll_controller    = igb_netpoll,
1000 #endif
1001 };
1002
1003 /**
1004  * igb_probe - Device Initialization Routine
1005  * @pdev: PCI device information struct
1006  * @ent: entry in igb_pci_tbl
1007  *
1008  * Returns 0 on success, negative on failure
1009  *
1010  * igb_probe initializes an adapter identified by a pci_dev structure.
1011  * The OS initialization, configuring of the adapter private structure,
1012  * and a hardware reset occur.
1013  **/
1014 static int __devinit igb_probe(struct pci_dev *pdev,
1015                                const struct pci_device_id *ent)
1016 {
1017         struct net_device *netdev;
1018         struct igb_adapter *adapter;
1019         struct e1000_hw *hw;
1020         struct pci_dev *us_dev;
1021         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1022         unsigned long mmio_start, mmio_len;
1023         int err, pci_using_dac, pos;
1024         u16 eeprom_data = 0, state = 0;
1025         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1026         u32 part_num;
1027
1028         err = pci_enable_device_mem(pdev);
1029         if (err)
1030                 return err;
1031
1032         pci_using_dac = 0;
1033         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1034         if (!err) {
1035                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1036                 if (!err)
1037                         pci_using_dac = 1;
1038         } else {
1039                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1040                 if (err) {
1041                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1042                         if (err) {
1043                                 dev_err(&pdev->dev, "No usable DMA "
1044                                         "configuration, aborting\n");
1045                                 goto err_dma;
1046                         }
1047                 }
1048         }
1049
1050         /* 82575 requires that the pci-e link partner disable the L0s state */
1051         switch (pdev->device) {
1052         case E1000_DEV_ID_82575EB_COPPER:
1053         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1054         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1055                 us_dev = pdev->bus->self;
1056                 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1057                 if (pos) {
1058                         pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1059                                              &state);
1060                         state &= ~PCIE_LINK_STATE_L0S;
1061                         pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1062                                               state);
1063                         dev_info(&pdev->dev,
1064                                  "Disabling ASPM L0s upstream switch port %s\n",
1065                                  pci_name(us_dev));
1066                 }
1067         default:
1068                 break;
1069         }
1070
1071         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1072                                            IORESOURCE_MEM),
1073                                            igb_driver_name);
1074         if (err)
1075                 goto err_pci_reg;
1076
1077         err = pci_enable_pcie_error_reporting(pdev);
1078         if (err) {
1079                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1080                         "0x%x\n", err);
1081                 /* non-fatal, continue */
1082         }
1083
1084         pci_set_master(pdev);
1085         pci_save_state(pdev);
1086
1087         err = -ENOMEM;
1088         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1089         if (!netdev)
1090                 goto err_alloc_etherdev;
1091
1092         SET_NETDEV_DEV(netdev, &pdev->dev);
1093
1094         pci_set_drvdata(pdev, netdev);
1095         adapter = netdev_priv(netdev);
1096         adapter->netdev = netdev;
1097         adapter->pdev = pdev;
1098         hw = &adapter->hw;
1099         hw->back = adapter;
1100         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1101
1102         mmio_start = pci_resource_start(pdev, 0);
1103         mmio_len = pci_resource_len(pdev, 0);
1104
1105         err = -EIO;
1106         hw->hw_addr = ioremap(mmio_start, mmio_len);
1107         if (!hw->hw_addr)
1108                 goto err_ioremap;
1109
1110         netdev->netdev_ops = &igb_netdev_ops;
1111         igb_set_ethtool_ops(netdev);
1112         netdev->watchdog_timeo = 5 * HZ;
1113
1114         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1115
1116         netdev->mem_start = mmio_start;
1117         netdev->mem_end = mmio_start + mmio_len;
1118
1119         /* PCI config space info */
1120         hw->vendor_id = pdev->vendor;
1121         hw->device_id = pdev->device;
1122         hw->revision_id = pdev->revision;
1123         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1124         hw->subsystem_device_id = pdev->subsystem_device;
1125
1126         /* setup the private structure */
1127         hw->back = adapter;
1128         /* Copy the default MAC, PHY and NVM function pointers */
1129         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1130         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1131         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1132         /* Initialize skew-specific constants */
1133         err = ei->get_invariants(hw);
1134         if (err)
1135                 goto err_sw_init;
1136
1137         /* setup the private structure */
1138         err = igb_sw_init(adapter);
1139         if (err)
1140                 goto err_sw_init;
1141
1142         igb_get_bus_info_pcie(hw);
1143
1144         /* set flags */
1145         switch (hw->mac.type) {
1146         case e1000_82575:
1147                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1148                 break;
1149         case e1000_82576:
1150         default:
1151                 break;
1152         }
1153
1154         hw->phy.autoneg_wait_to_complete = false;
1155         hw->mac.adaptive_ifs = true;
1156
1157         /* Copper options */
1158         if (hw->phy.media_type == e1000_media_type_copper) {
1159                 hw->phy.mdix = AUTO_ALL_MODES;
1160                 hw->phy.disable_polarity_correction = false;
1161                 hw->phy.ms_type = e1000_ms_hw_default;
1162         }
1163
1164         if (igb_check_reset_block(hw))
1165                 dev_info(&pdev->dev,
1166                         "PHY reset is blocked due to SOL/IDER session.\n");
1167
1168         netdev->features = NETIF_F_SG |
1169                            NETIF_F_IP_CSUM |
1170                            NETIF_F_HW_VLAN_TX |
1171                            NETIF_F_HW_VLAN_RX |
1172                            NETIF_F_HW_VLAN_FILTER;
1173
1174         netdev->features |= NETIF_F_IPV6_CSUM;
1175         netdev->features |= NETIF_F_TSO;
1176         netdev->features |= NETIF_F_TSO6;
1177
1178 #ifdef CONFIG_IGB_LRO
1179         netdev->features |= NETIF_F_GRO;
1180 #endif
1181
1182         netdev->vlan_features |= NETIF_F_TSO;
1183         netdev->vlan_features |= NETIF_F_TSO6;
1184         netdev->vlan_features |= NETIF_F_IP_CSUM;
1185         netdev->vlan_features |= NETIF_F_SG;
1186
1187         if (pci_using_dac)
1188                 netdev->features |= NETIF_F_HIGHDMA;
1189
1190         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1191
1192         /* before reading the NVM, reset the controller to put the device in a
1193          * known good starting state */
1194         hw->mac.ops.reset_hw(hw);
1195
1196         /* make sure the NVM is good */
1197         if (igb_validate_nvm_checksum(hw) < 0) {
1198                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1199                 err = -EIO;
1200                 goto err_eeprom;
1201         }
1202
1203         /* copy the MAC address out of the NVM */
1204         if (hw->mac.ops.read_mac_addr(hw))
1205                 dev_err(&pdev->dev, "NVM Read Error\n");
1206
1207         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1208         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1209
1210         if (!is_valid_ether_addr(netdev->perm_addr)) {
1211                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1212                 err = -EIO;
1213                 goto err_eeprom;
1214         }
1215
1216         init_timer(&adapter->watchdog_timer);
1217         adapter->watchdog_timer.function = &igb_watchdog;
1218         adapter->watchdog_timer.data = (unsigned long) adapter;
1219
1220         init_timer(&adapter->phy_info_timer);
1221         adapter->phy_info_timer.function = &igb_update_phy_info;
1222         adapter->phy_info_timer.data = (unsigned long) adapter;
1223
1224         INIT_WORK(&adapter->reset_task, igb_reset_task);
1225         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1226
1227         /* Initialize link properties that are user-changeable */
1228         adapter->fc_autoneg = true;
1229         hw->mac.autoneg = true;
1230         hw->phy.autoneg_advertised = 0x2f;
1231
1232         hw->fc.original_type = e1000_fc_default;
1233         hw->fc.type = e1000_fc_default;
1234
1235         adapter->itr_setting = 3;
1236         adapter->itr = IGB_START_ITR;
1237
1238         igb_validate_mdi_setting(hw);
1239
1240         adapter->rx_csum = 1;
1241
1242         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1243          * enable the ACPI Magic Packet filter
1244          */
1245
1246         if (hw->bus.func == 0 ||
1247             hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1248                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1249
1250         if (eeprom_data & eeprom_apme_mask)
1251                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1252
1253         /* now that we have the eeprom settings, apply the special cases where
1254          * the eeprom may be wrong or the board simply won't support wake on
1255          * lan on a particular port */
1256         switch (pdev->device) {
1257         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1258                 adapter->eeprom_wol = 0;
1259                 break;
1260         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1261         case E1000_DEV_ID_82576_FIBER:
1262         case E1000_DEV_ID_82576_SERDES:
1263                 /* Wake events only supported on port A for dual fiber
1264                  * regardless of eeprom setting */
1265                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1266                         adapter->eeprom_wol = 0;
1267                 break;
1268         }
1269
1270         /* initialize the wol settings based on the eeprom settings */
1271         adapter->wol = adapter->eeprom_wol;
1272         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1273
1274         /* reset the hardware with the new settings */
1275         igb_reset(adapter);
1276
1277         /* let the f/w know that the h/w is now under the control of the
1278          * driver. */
1279         igb_get_hw_control(adapter);
1280
1281         /* tell the stack to leave us alone until igb_open() is called */
1282         netif_carrier_off(netdev);
1283         netif_tx_stop_all_queues(netdev);
1284
1285         strcpy(netdev->name, "eth%d");
1286         err = register_netdev(netdev);
1287         if (err)
1288                 goto err_register;
1289
1290 #ifdef CONFIG_IGB_DCA
1291         if (dca_add_requester(&pdev->dev) == 0) {
1292                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1293                 dev_info(&pdev->dev, "DCA enabled\n");
1294                 /* Always use CB2 mode, difference is masked
1295                  * in the CB driver. */
1296                 wr32(E1000_DCA_CTRL, 2);
1297                 igb_setup_dca(adapter);
1298         }
1299 #endif
1300
1301         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1302         /* print bus type/speed/width info */
1303         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1304                  netdev->name,
1305                  ((hw->bus.speed == e1000_bus_speed_2500)
1306                   ? "2.5Gb/s" : "unknown"),
1307                  ((hw->bus.width == e1000_bus_width_pcie_x4)
1308                   ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1309                   ? "Width x1" : "unknown"),
1310                  netdev->dev_addr);
1311
1312         igb_read_part_num(hw, &part_num);
1313         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1314                 (part_num >> 8), (part_num & 0xff));
1315
1316         dev_info(&pdev->dev,
1317                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1318                 adapter->msix_entries ? "MSI-X" :
1319                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1320                 adapter->num_rx_queues, adapter->num_tx_queues);
1321
1322         return 0;
1323
1324 err_register:
1325         igb_release_hw_control(adapter);
1326 err_eeprom:
1327         if (!igb_check_reset_block(hw))
1328                 igb_reset_phy(hw);
1329
1330         if (hw->flash_address)
1331                 iounmap(hw->flash_address);
1332
1333         igb_free_queues(adapter);
1334 err_sw_init:
1335         iounmap(hw->hw_addr);
1336 err_ioremap:
1337         free_netdev(netdev);
1338 err_alloc_etherdev:
1339         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1340                                      IORESOURCE_MEM));
1341 err_pci_reg:
1342 err_dma:
1343         pci_disable_device(pdev);
1344         return err;
1345 }
1346
1347 /**
1348  * igb_remove - Device Removal Routine
1349  * @pdev: PCI device information struct
1350  *
1351  * igb_remove is called by the PCI subsystem to alert the driver
1352  * that it should release a PCI device.  The could be caused by a
1353  * Hot-Plug event, or because the driver is going to be removed from
1354  * memory.
1355  **/
1356 static void __devexit igb_remove(struct pci_dev *pdev)
1357 {
1358         struct net_device *netdev = pci_get_drvdata(pdev);
1359         struct igb_adapter *adapter = netdev_priv(netdev);
1360         struct e1000_hw *hw = &adapter->hw;
1361         int err;
1362
1363         /* flush_scheduled work may reschedule our watchdog task, so
1364          * explicitly disable watchdog tasks from being rescheduled  */
1365         set_bit(__IGB_DOWN, &adapter->state);
1366         del_timer_sync(&adapter->watchdog_timer);
1367         del_timer_sync(&adapter->phy_info_timer);
1368
1369         flush_scheduled_work();
1370
1371 #ifdef CONFIG_IGB_DCA
1372         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1373                 dev_info(&pdev->dev, "DCA disabled\n");
1374                 dca_remove_requester(&pdev->dev);
1375                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1376                 wr32(E1000_DCA_CTRL, 1);
1377         }
1378 #endif
1379
1380         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1381          * would have already happened in close and is redundant. */
1382         igb_release_hw_control(adapter);
1383
1384         unregister_netdev(netdev);
1385
1386         if (!igb_check_reset_block(&adapter->hw))
1387                 igb_reset_phy(&adapter->hw);
1388
1389         igb_reset_interrupt_capability(adapter);
1390
1391         igb_free_queues(adapter);
1392
1393         iounmap(hw->hw_addr);
1394         if (hw->flash_address)
1395                 iounmap(hw->flash_address);
1396         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1397                                      IORESOURCE_MEM));
1398
1399         free_netdev(netdev);
1400
1401         err = pci_disable_pcie_error_reporting(pdev);
1402         if (err)
1403                 dev_err(&pdev->dev,
1404                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1405
1406         pci_disable_device(pdev);
1407 }
1408
1409 /**
1410  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1411  * @adapter: board private structure to initialize
1412  *
1413  * igb_sw_init initializes the Adapter private data structure.
1414  * Fields are initialized based on PCI device information and
1415  * OS network device settings (MTU size).
1416  **/
1417 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1418 {
1419         struct e1000_hw *hw = &adapter->hw;
1420         struct net_device *netdev = adapter->netdev;
1421         struct pci_dev *pdev = adapter->pdev;
1422
1423         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1424
1425         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1426         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1427         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1428         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1429         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1430         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1431
1432         /* This call may decrease the number of queues depending on
1433          * interrupt mode. */
1434         igb_set_interrupt_capability(adapter);
1435
1436         if (igb_alloc_queues(adapter)) {
1437                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1438                 return -ENOMEM;
1439         }
1440
1441         /* Explicitly disable IRQ since the NIC can be in any state. */
1442         igb_irq_disable(adapter);
1443
1444         set_bit(__IGB_DOWN, &adapter->state);
1445         return 0;
1446 }
1447
1448 /**
1449  * igb_open - Called when a network interface is made active
1450  * @netdev: network interface device structure
1451  *
1452  * Returns 0 on success, negative value on failure
1453  *
1454  * The open entry point is called when a network interface is made
1455  * active by the system (IFF_UP).  At this point all resources needed
1456  * for transmit and receive operations are allocated, the interrupt
1457  * handler is registered with the OS, the watchdog timer is started,
1458  * and the stack is notified that the interface is ready.
1459  **/
1460 static int igb_open(struct net_device *netdev)
1461 {
1462         struct igb_adapter *adapter = netdev_priv(netdev);
1463         struct e1000_hw *hw = &adapter->hw;
1464         int err;
1465         int i;
1466
1467         /* disallow open during test */
1468         if (test_bit(__IGB_TESTING, &adapter->state))
1469                 return -EBUSY;
1470
1471         /* allocate transmit descriptors */
1472         err = igb_setup_all_tx_resources(adapter);
1473         if (err)
1474                 goto err_setup_tx;
1475
1476         /* allocate receive descriptors */
1477         err = igb_setup_all_rx_resources(adapter);
1478         if (err)
1479                 goto err_setup_rx;
1480
1481         /* e1000_power_up_phy(adapter); */
1482
1483         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1484         if ((adapter->hw.mng_cookie.status &
1485              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1486                 igb_update_mng_vlan(adapter);
1487
1488         /* before we allocate an interrupt, we must be ready to handle it.
1489          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1490          * as soon as we call pci_request_irq, so we have to setup our
1491          * clean_rx handler before we do so.  */
1492         igb_configure(adapter);
1493
1494         err = igb_request_irq(adapter);
1495         if (err)
1496                 goto err_req_irq;
1497
1498         /* From here on the code is the same as igb_up() */
1499         clear_bit(__IGB_DOWN, &adapter->state);
1500
1501         for (i = 0; i < adapter->num_rx_queues; i++)
1502                 napi_enable(&adapter->rx_ring[i].napi);
1503
1504         /* Clear any pending interrupts. */
1505         rd32(E1000_ICR);
1506
1507         igb_irq_enable(adapter);
1508
1509         netif_tx_start_all_queues(netdev);
1510
1511         /* Fire a link status change interrupt to start the watchdog. */
1512         wr32(E1000_ICS, E1000_ICS_LSC);
1513
1514         return 0;
1515
1516 err_req_irq:
1517         igb_release_hw_control(adapter);
1518         /* e1000_power_down_phy(adapter); */
1519         igb_free_all_rx_resources(adapter);
1520 err_setup_rx:
1521         igb_free_all_tx_resources(adapter);
1522 err_setup_tx:
1523         igb_reset(adapter);
1524
1525         return err;
1526 }
1527
1528 /**
1529  * igb_close - Disables a network interface
1530  * @netdev: network interface device structure
1531  *
1532  * Returns 0, this is not allowed to fail
1533  *
1534  * The close entry point is called when an interface is de-activated
1535  * by the OS.  The hardware is still under the driver's control, but
1536  * needs to be disabled.  A global MAC reset is issued to stop the
1537  * hardware, and all transmit and receive resources are freed.
1538  **/
1539 static int igb_close(struct net_device *netdev)
1540 {
1541         struct igb_adapter *adapter = netdev_priv(netdev);
1542
1543         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1544         igb_down(adapter);
1545
1546         igb_free_irq(adapter);
1547
1548         igb_free_all_tx_resources(adapter);
1549         igb_free_all_rx_resources(adapter);
1550
1551         /* kill manageability vlan ID if supported, but not if a vlan with
1552          * the same ID is registered on the host OS (let 8021q kill it) */
1553         if ((adapter->hw.mng_cookie.status &
1554                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1555              !(adapter->vlgrp &&
1556                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1557                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1558
1559         return 0;
1560 }
1561
1562 /**
1563  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1564  * @adapter: board private structure
1565  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1566  *
1567  * Return 0 on success, negative on failure
1568  **/
1569
1570 int igb_setup_tx_resources(struct igb_adapter *adapter,
1571                            struct igb_ring *tx_ring)
1572 {
1573         struct pci_dev *pdev = adapter->pdev;
1574         int size;
1575
1576         size = sizeof(struct igb_buffer) * tx_ring->count;
1577         tx_ring->buffer_info = vmalloc(size);
1578         if (!tx_ring->buffer_info)
1579                 goto err;
1580         memset(tx_ring->buffer_info, 0, size);
1581
1582         /* round up to nearest 4K */
1583         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1584         tx_ring->size = ALIGN(tx_ring->size, 4096);
1585
1586         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1587                                              &tx_ring->dma);
1588
1589         if (!tx_ring->desc)
1590                 goto err;
1591
1592         tx_ring->adapter = adapter;
1593         tx_ring->next_to_use = 0;
1594         tx_ring->next_to_clean = 0;
1595         return 0;
1596
1597 err:
1598         vfree(tx_ring->buffer_info);
1599         dev_err(&adapter->pdev->dev,
1600                 "Unable to allocate memory for the transmit descriptor ring\n");
1601         return -ENOMEM;
1602 }
1603
1604 /**
1605  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1606  *                                (Descriptors) for all queues
1607  * @adapter: board private structure
1608  *
1609  * Return 0 on success, negative on failure
1610  **/
1611 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1612 {
1613         int i, err = 0;
1614         int r_idx;
1615
1616         for (i = 0; i < adapter->num_tx_queues; i++) {
1617                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1618                 if (err) {
1619                         dev_err(&adapter->pdev->dev,
1620                                 "Allocation for Tx Queue %u failed\n", i);
1621                         for (i--; i >= 0; i--)
1622                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1623                         break;
1624                 }
1625         }
1626
1627         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1628                 r_idx = i % adapter->num_tx_queues;
1629                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1630         }
1631         return err;
1632 }
1633
1634 /**
1635  * igb_configure_tx - Configure transmit Unit after Reset
1636  * @adapter: board private structure
1637  *
1638  * Configure the Tx unit of the MAC after a reset.
1639  **/
1640 static void igb_configure_tx(struct igb_adapter *adapter)
1641 {
1642         u64 tdba;
1643         struct e1000_hw *hw = &adapter->hw;
1644         u32 tctl;
1645         u32 txdctl, txctrl;
1646         int i, j;
1647
1648         for (i = 0; i < adapter->num_tx_queues; i++) {
1649                 struct igb_ring *ring = &(adapter->tx_ring[i]);
1650                 j = ring->reg_idx;
1651                 wr32(E1000_TDLEN(j),
1652                                 ring->count * sizeof(struct e1000_tx_desc));
1653                 tdba = ring->dma;
1654                 wr32(E1000_TDBAL(j),
1655                                 tdba & 0x00000000ffffffffULL);
1656                 wr32(E1000_TDBAH(j), tdba >> 32);
1657
1658                 ring->head = E1000_TDH(j);
1659                 ring->tail = E1000_TDT(j);
1660                 writel(0, hw->hw_addr + ring->tail);
1661                 writel(0, hw->hw_addr + ring->head);
1662                 txdctl = rd32(E1000_TXDCTL(j));
1663                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1664                 wr32(E1000_TXDCTL(j), txdctl);
1665
1666                 /* Turn off Relaxed Ordering on head write-backs.  The
1667                  * writebacks MUST be delivered in order or it will
1668                  * completely screw up our bookeeping.
1669                  */
1670                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1671                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1672                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1673         }
1674
1675
1676
1677         /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1678
1679         /* Program the Transmit Control Register */
1680
1681         tctl = rd32(E1000_TCTL);
1682         tctl &= ~E1000_TCTL_CT;
1683         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1684                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1685
1686         igb_config_collision_dist(hw);
1687
1688         /* Setup Transmit Descriptor Settings for eop descriptor */
1689         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1690
1691         /* Enable transmits */
1692         tctl |= E1000_TCTL_EN;
1693
1694         wr32(E1000_TCTL, tctl);
1695 }
1696
1697 /**
1698  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1699  * @adapter: board private structure
1700  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1701  *
1702  * Returns 0 on success, negative on failure
1703  **/
1704
1705 int igb_setup_rx_resources(struct igb_adapter *adapter,
1706                            struct igb_ring *rx_ring)
1707 {
1708         struct pci_dev *pdev = adapter->pdev;
1709         int size, desc_len;
1710
1711         size = sizeof(struct igb_buffer) * rx_ring->count;
1712         rx_ring->buffer_info = vmalloc(size);
1713         if (!rx_ring->buffer_info)
1714                 goto err;
1715         memset(rx_ring->buffer_info, 0, size);
1716
1717         desc_len = sizeof(union e1000_adv_rx_desc);
1718
1719         /* Round up to nearest 4K */
1720         rx_ring->size = rx_ring->count * desc_len;
1721         rx_ring->size = ALIGN(rx_ring->size, 4096);
1722
1723         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1724                                              &rx_ring->dma);
1725
1726         if (!rx_ring->desc)
1727                 goto err;
1728
1729         rx_ring->next_to_clean = 0;
1730         rx_ring->next_to_use = 0;
1731
1732         rx_ring->adapter = adapter;
1733
1734         return 0;
1735
1736 err:
1737         vfree(rx_ring->buffer_info);
1738         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1739                 "the receive descriptor ring\n");
1740         return -ENOMEM;
1741 }
1742
1743 /**
1744  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1745  *                                (Descriptors) for all queues
1746  * @adapter: board private structure
1747  *
1748  * Return 0 on success, negative on failure
1749  **/
1750 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1751 {
1752         int i, err = 0;
1753
1754         for (i = 0; i < adapter->num_rx_queues; i++) {
1755                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1756                 if (err) {
1757                         dev_err(&adapter->pdev->dev,
1758                                 "Allocation for Rx Queue %u failed\n", i);
1759                         for (i--; i >= 0; i--)
1760                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1761                         break;
1762                 }
1763         }
1764
1765         return err;
1766 }
1767
1768 /**
1769  * igb_setup_rctl - configure the receive control registers
1770  * @adapter: Board private structure
1771  **/
1772 static void igb_setup_rctl(struct igb_adapter *adapter)
1773 {
1774         struct e1000_hw *hw = &adapter->hw;
1775         u32 rctl;
1776         u32 srrctl = 0;
1777         int i, j;
1778
1779         rctl = rd32(E1000_RCTL);
1780
1781         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1782         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1783
1784         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1785                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1786
1787         /*
1788          * enable stripping of CRC. It's unlikely this will break BMC
1789          * redirection as it did with e1000. Newer features require
1790          * that the HW strips the CRC.
1791         */
1792         rctl |= E1000_RCTL_SECRC;
1793
1794         /*
1795          * disable store bad packets and clear size bits.
1796          */
1797         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1798
1799         /* enable LPE when to prevent packets larger than max_frame_size */
1800                 rctl |= E1000_RCTL_LPE;
1801
1802         /* Setup buffer sizes */
1803         switch (adapter->rx_buffer_len) {
1804         case IGB_RXBUFFER_256:
1805                 rctl |= E1000_RCTL_SZ_256;
1806                 break;
1807         case IGB_RXBUFFER_512:
1808                 rctl |= E1000_RCTL_SZ_512;
1809                 break;
1810         default:
1811                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1812                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1813                 break;
1814         }
1815
1816         /* 82575 and greater support packet-split where the protocol
1817          * header is placed in skb->data and the packet data is
1818          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1819          * In the case of a non-split, skb->data is linearly filled,
1820          * followed by the page buffers.  Therefore, skb->data is
1821          * sized to hold the largest protocol header.
1822          */
1823         /* allocations using alloc_page take too long for regular MTU
1824          * so only enable packet split for jumbo frames */
1825         if (adapter->netdev->mtu > ETH_DATA_LEN) {
1826                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1827                 srrctl |= adapter->rx_ps_hdr_size <<
1828                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1829                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1830         } else {
1831                 adapter->rx_ps_hdr_size = 0;
1832                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1833         }
1834
1835         for (i = 0; i < adapter->num_rx_queues; i++) {
1836                 j = adapter->rx_ring[i].reg_idx;
1837                 wr32(E1000_SRRCTL(j), srrctl);
1838         }
1839
1840         wr32(E1000_RCTL, rctl);
1841 }
1842
1843 /**
1844  * igb_configure_rx - Configure receive Unit after Reset
1845  * @adapter: board private structure
1846  *
1847  * Configure the Rx unit of the MAC after a reset.
1848  **/
1849 static void igb_configure_rx(struct igb_adapter *adapter)
1850 {
1851         u64 rdba;
1852         struct e1000_hw *hw = &adapter->hw;
1853         u32 rctl, rxcsum;
1854         u32 rxdctl;
1855         int i, j;
1856
1857         /* disable receives while setting up the descriptors */
1858         rctl = rd32(E1000_RCTL);
1859         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1860         wrfl();
1861         mdelay(10);
1862
1863         if (adapter->itr_setting > 3)
1864                 wr32(E1000_ITR, adapter->itr);
1865
1866         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1867          * the Base and Length of the Rx Descriptor Ring */
1868         for (i = 0; i < adapter->num_rx_queues; i++) {
1869                 struct igb_ring *ring = &(adapter->rx_ring[i]);
1870                 j = ring->reg_idx;
1871                 rdba = ring->dma;
1872                 wr32(E1000_RDBAL(j),
1873                                 rdba & 0x00000000ffffffffULL);
1874                 wr32(E1000_RDBAH(j), rdba >> 32);
1875                 wr32(E1000_RDLEN(j),
1876                                ring->count * sizeof(union e1000_adv_rx_desc));
1877
1878                 ring->head = E1000_RDH(j);
1879                 ring->tail = E1000_RDT(j);
1880                 writel(0, hw->hw_addr + ring->tail);
1881                 writel(0, hw->hw_addr + ring->head);
1882
1883                 rxdctl = rd32(E1000_RXDCTL(j));
1884                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1885                 rxdctl &= 0xFFF00000;
1886                 rxdctl |= IGB_RX_PTHRESH;
1887                 rxdctl |= IGB_RX_HTHRESH << 8;
1888                 rxdctl |= IGB_RX_WTHRESH << 16;
1889                 wr32(E1000_RXDCTL(j), rxdctl);
1890         }
1891
1892         if (adapter->num_rx_queues > 1) {
1893                 u32 random[10];
1894                 u32 mrqc;
1895                 u32 j, shift;
1896                 union e1000_reta {
1897                         u32 dword;
1898                         u8  bytes[4];
1899                 } reta;
1900
1901                 get_random_bytes(&random[0], 40);
1902
1903                 if (hw->mac.type >= e1000_82576)
1904                         shift = 0;
1905                 else
1906                         shift = 6;
1907                 for (j = 0; j < (32 * 4); j++) {
1908                         reta.bytes[j & 3] =
1909                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
1910                         if ((j & 3) == 3)
1911                                 writel(reta.dword,
1912                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
1913                 }
1914                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1915
1916                 /* Fill out hash function seeds */
1917                 for (j = 0; j < 10; j++)
1918                         array_wr32(E1000_RSSRK(0), j, random[j]);
1919
1920                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1921                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
1922                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1923                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
1924                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1925                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
1926                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1927                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1928
1929
1930                 wr32(E1000_MRQC, mrqc);
1931
1932                 /* Multiqueue and raw packet checksumming are mutually
1933                  * exclusive.  Note that this not the same as TCP/IP
1934                  * checksumming, which works fine. */
1935                 rxcsum = rd32(E1000_RXCSUM);
1936                 rxcsum |= E1000_RXCSUM_PCSD;
1937                 wr32(E1000_RXCSUM, rxcsum);
1938         } else {
1939                 /* Enable Receive Checksum Offload for TCP and UDP */
1940                 rxcsum = rd32(E1000_RXCSUM);
1941                 if (adapter->rx_csum) {
1942                         rxcsum |= E1000_RXCSUM_TUOFL;
1943
1944                         /* Enable IPv4 payload checksum for UDP fragments
1945                          * Must be used in conjunction with packet-split. */
1946                         if (adapter->rx_ps_hdr_size)
1947                                 rxcsum |= E1000_RXCSUM_IPPCSE;
1948                 } else {
1949                         rxcsum &= ~E1000_RXCSUM_TUOFL;
1950                         /* don't need to clear IPPCSE as it defaults to 0 */
1951                 }
1952                 wr32(E1000_RXCSUM, rxcsum);
1953         }
1954
1955         if (adapter->vlgrp)
1956                 wr32(E1000_RLPML,
1957                                 adapter->max_frame_size + VLAN_TAG_SIZE);
1958         else
1959                 wr32(E1000_RLPML, adapter->max_frame_size);
1960
1961         /* Enable Receives */
1962         wr32(E1000_RCTL, rctl);
1963 }
1964
1965 /**
1966  * igb_free_tx_resources - Free Tx Resources per Queue
1967  * @tx_ring: Tx descriptor ring for a specific queue
1968  *
1969  * Free all transmit software resources
1970  **/
1971 void igb_free_tx_resources(struct igb_ring *tx_ring)
1972 {
1973         struct pci_dev *pdev = tx_ring->adapter->pdev;
1974
1975         igb_clean_tx_ring(tx_ring);
1976
1977         vfree(tx_ring->buffer_info);
1978         tx_ring->buffer_info = NULL;
1979
1980         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1981
1982         tx_ring->desc = NULL;
1983 }
1984
1985 /**
1986  * igb_free_all_tx_resources - Free Tx Resources for All Queues
1987  * @adapter: board private structure
1988  *
1989  * Free all transmit software resources
1990  **/
1991 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1992 {
1993         int i;
1994
1995         for (i = 0; i < adapter->num_tx_queues; i++)
1996                 igb_free_tx_resources(&adapter->tx_ring[i]);
1997 }
1998
1999 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2000                                            struct igb_buffer *buffer_info)
2001 {
2002         if (buffer_info->dma) {
2003                 pci_unmap_page(adapter->pdev,
2004                                 buffer_info->dma,
2005                                 buffer_info->length,
2006                                 PCI_DMA_TODEVICE);
2007                 buffer_info->dma = 0;
2008         }
2009         if (buffer_info->skb) {
2010                 dev_kfree_skb_any(buffer_info->skb);
2011                 buffer_info->skb = NULL;
2012         }
2013         buffer_info->time_stamp = 0;
2014         /* buffer_info must be completely set up in the transmit path */
2015 }
2016
2017 /**
2018  * igb_clean_tx_ring - Free Tx Buffers
2019  * @tx_ring: ring to be cleaned
2020  **/
2021 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2022 {
2023         struct igb_adapter *adapter = tx_ring->adapter;
2024         struct igb_buffer *buffer_info;
2025         unsigned long size;
2026         unsigned int i;
2027
2028         if (!tx_ring->buffer_info)
2029                 return;
2030         /* Free all the Tx ring sk_buffs */
2031
2032         for (i = 0; i < tx_ring->count; i++) {
2033                 buffer_info = &tx_ring->buffer_info[i];
2034                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2035         }
2036
2037         size = sizeof(struct igb_buffer) * tx_ring->count;
2038         memset(tx_ring->buffer_info, 0, size);
2039
2040         /* Zero out the descriptor ring */
2041
2042         memset(tx_ring->desc, 0, tx_ring->size);
2043
2044         tx_ring->next_to_use = 0;
2045         tx_ring->next_to_clean = 0;
2046
2047         writel(0, adapter->hw.hw_addr + tx_ring->head);
2048         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2049 }
2050
2051 /**
2052  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2053  * @adapter: board private structure
2054  **/
2055 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2056 {
2057         int i;
2058
2059         for (i = 0; i < adapter->num_tx_queues; i++)
2060                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2061 }
2062
2063 /**
2064  * igb_free_rx_resources - Free Rx Resources
2065  * @rx_ring: ring to clean the resources from
2066  *
2067  * Free all receive software resources
2068  **/
2069 void igb_free_rx_resources(struct igb_ring *rx_ring)
2070 {
2071         struct pci_dev *pdev = rx_ring->adapter->pdev;
2072
2073         igb_clean_rx_ring(rx_ring);
2074
2075         vfree(rx_ring->buffer_info);
2076         rx_ring->buffer_info = NULL;
2077
2078         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2079
2080         rx_ring->desc = NULL;
2081 }
2082
2083 /**
2084  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2085  * @adapter: board private structure
2086  *
2087  * Free all receive software resources
2088  **/
2089 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2090 {
2091         int i;
2092
2093         for (i = 0; i < adapter->num_rx_queues; i++)
2094                 igb_free_rx_resources(&adapter->rx_ring[i]);
2095 }
2096
2097 /**
2098  * igb_clean_rx_ring - Free Rx Buffers per Queue
2099  * @rx_ring: ring to free buffers from
2100  **/
2101 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2102 {
2103         struct igb_adapter *adapter = rx_ring->adapter;
2104         struct igb_buffer *buffer_info;
2105         struct pci_dev *pdev = adapter->pdev;
2106         unsigned long size;
2107         unsigned int i;
2108
2109         if (!rx_ring->buffer_info)
2110                 return;
2111         /* Free all the Rx ring sk_buffs */
2112         for (i = 0; i < rx_ring->count; i++) {
2113                 buffer_info = &rx_ring->buffer_info[i];
2114                 if (buffer_info->dma) {
2115                         if (adapter->rx_ps_hdr_size)
2116                                 pci_unmap_single(pdev, buffer_info->dma,
2117                                                  adapter->rx_ps_hdr_size,
2118                                                  PCI_DMA_FROMDEVICE);
2119                         else
2120                                 pci_unmap_single(pdev, buffer_info->dma,
2121                                                  adapter->rx_buffer_len,
2122                                                  PCI_DMA_FROMDEVICE);
2123                         buffer_info->dma = 0;
2124                 }
2125
2126                 if (buffer_info->skb) {
2127                         dev_kfree_skb(buffer_info->skb);
2128                         buffer_info->skb = NULL;
2129                 }
2130                 if (buffer_info->page) {
2131                         if (buffer_info->page_dma)
2132                                 pci_unmap_page(pdev, buffer_info->page_dma,
2133                                                PAGE_SIZE / 2,
2134                                                PCI_DMA_FROMDEVICE);
2135                         put_page(buffer_info->page);
2136                         buffer_info->page = NULL;
2137                         buffer_info->page_dma = 0;
2138                         buffer_info->page_offset = 0;
2139                 }
2140         }
2141
2142         size = sizeof(struct igb_buffer) * rx_ring->count;
2143         memset(rx_ring->buffer_info, 0, size);
2144
2145         /* Zero out the descriptor ring */
2146         memset(rx_ring->desc, 0, rx_ring->size);
2147
2148         rx_ring->next_to_clean = 0;
2149         rx_ring->next_to_use = 0;
2150
2151         writel(0, adapter->hw.hw_addr + rx_ring->head);
2152         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2153 }
2154
2155 /**
2156  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2157  * @adapter: board private structure
2158  **/
2159 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2160 {
2161         int i;
2162
2163         for (i = 0; i < adapter->num_rx_queues; i++)
2164                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2165 }
2166
2167 /**
2168  * igb_set_mac - Change the Ethernet Address of the NIC
2169  * @netdev: network interface device structure
2170  * @p: pointer to an address structure
2171  *
2172  * Returns 0 on success, negative on failure
2173  **/
2174 static int igb_set_mac(struct net_device *netdev, void *p)
2175 {
2176         struct igb_adapter *adapter = netdev_priv(netdev);
2177         struct e1000_hw *hw = &adapter->hw;
2178         struct sockaddr *addr = p;
2179
2180         if (!is_valid_ether_addr(addr->sa_data))
2181                 return -EADDRNOTAVAIL;
2182
2183         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2184         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2185
2186         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2187
2188         return 0;
2189 }
2190
2191 /**
2192  * igb_set_multi - Multicast and Promiscuous mode set
2193  * @netdev: network interface device structure
2194  *
2195  * The set_multi entry point is called whenever the multicast address
2196  * list or the network interface flags are updated.  This routine is
2197  * responsible for configuring the hardware for proper multicast,
2198  * promiscuous mode, and all-multi behavior.
2199  **/
2200 static void igb_set_multi(struct net_device *netdev)
2201 {
2202         struct igb_adapter *adapter = netdev_priv(netdev);
2203         struct e1000_hw *hw = &adapter->hw;
2204         struct e1000_mac_info *mac = &hw->mac;
2205         struct dev_mc_list *mc_ptr;
2206         u8  *mta_list;
2207         u32 rctl;
2208         int i;
2209
2210         /* Check for Promiscuous and All Multicast modes */
2211
2212         rctl = rd32(E1000_RCTL);
2213
2214         if (netdev->flags & IFF_PROMISC) {
2215                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2216                 rctl &= ~E1000_RCTL_VFE;
2217         } else {
2218                 if (netdev->flags & IFF_ALLMULTI) {
2219                         rctl |= E1000_RCTL_MPE;
2220                         rctl &= ~E1000_RCTL_UPE;
2221                 } else
2222                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2223                 rctl |= E1000_RCTL_VFE;
2224         }
2225         wr32(E1000_RCTL, rctl);
2226
2227         if (!netdev->mc_count) {
2228                 /* nothing to program, so clear mc list */
2229                 igb_update_mc_addr_list(hw, NULL, 0, 1,
2230                                         mac->rar_entry_count);
2231                 return;
2232         }
2233
2234         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2235         if (!mta_list)
2236                 return;
2237
2238         /* The shared function expects a packed array of only addresses. */
2239         mc_ptr = netdev->mc_list;
2240
2241         for (i = 0; i < netdev->mc_count; i++) {
2242                 if (!mc_ptr)
2243                         break;
2244                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2245                 mc_ptr = mc_ptr->next;
2246         }
2247         igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2248         kfree(mta_list);
2249 }
2250
2251 /* Need to wait a few seconds after link up to get diagnostic information from
2252  * the phy */
2253 static void igb_update_phy_info(unsigned long data)
2254 {
2255         struct igb_adapter *adapter = (struct igb_adapter *) data;
2256         igb_get_phy_info(&adapter->hw);
2257 }
2258
2259 /**
2260  * igb_has_link - check shared code for link and determine up/down
2261  * @adapter: pointer to driver private info
2262  **/
2263 static bool igb_has_link(struct igb_adapter *adapter)
2264 {
2265         struct e1000_hw *hw = &adapter->hw;
2266         bool link_active = false;
2267         s32 ret_val = 0;
2268
2269         /* get_link_status is set on LSC (link status) interrupt or
2270          * rx sequence error interrupt.  get_link_status will stay
2271          * false until the e1000_check_for_link establishes link
2272          * for copper adapters ONLY
2273          */
2274         switch (hw->phy.media_type) {
2275         case e1000_media_type_copper:
2276                 if (hw->mac.get_link_status) {
2277                         ret_val = hw->mac.ops.check_for_link(hw);
2278                         link_active = !hw->mac.get_link_status;
2279                 } else {
2280                         link_active = true;
2281                 }
2282                 break;
2283         case e1000_media_type_fiber:
2284                 ret_val = hw->mac.ops.check_for_link(hw);
2285                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2286                 break;
2287         case e1000_media_type_internal_serdes:
2288                 ret_val = hw->mac.ops.check_for_link(hw);
2289                 link_active = hw->mac.serdes_has_link;
2290                 break;
2291         default:
2292         case e1000_media_type_unknown:
2293                 break;
2294         }
2295
2296         return link_active;
2297 }
2298
2299 /**
2300  * igb_watchdog - Timer Call-back
2301  * @data: pointer to adapter cast into an unsigned long
2302  **/
2303 static void igb_watchdog(unsigned long data)
2304 {
2305         struct igb_adapter *adapter = (struct igb_adapter *)data;
2306         /* Do the rest outside of interrupt context */
2307         schedule_work(&adapter->watchdog_task);
2308 }
2309
2310 static void igb_watchdog_task(struct work_struct *work)
2311 {
2312         struct igb_adapter *adapter = container_of(work,
2313                                         struct igb_adapter, watchdog_task);
2314         struct e1000_hw *hw = &adapter->hw;
2315         struct net_device *netdev = adapter->netdev;
2316         struct igb_ring *tx_ring = adapter->tx_ring;
2317         u32 link;
2318         u32 eics = 0;
2319         int i;
2320
2321         link = igb_has_link(adapter);
2322         if ((netif_carrier_ok(netdev)) && link)
2323                 goto link_up;
2324
2325         if (link) {
2326                 if (!netif_carrier_ok(netdev)) {
2327                         u32 ctrl;
2328                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2329                                                    &adapter->link_speed,
2330                                                    &adapter->link_duplex);
2331
2332                         ctrl = rd32(E1000_CTRL);
2333                         /* Links status message must follow this format */
2334                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2335                                  "Flow Control: %s\n",
2336                                  netdev->name,
2337                                  adapter->link_speed,
2338                                  adapter->link_duplex == FULL_DUPLEX ?
2339                                  "Full Duplex" : "Half Duplex",
2340                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2341                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2342                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2343                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2344
2345                         /* tweak tx_queue_len according to speed/duplex and
2346                          * adjust the timeout factor */
2347                         netdev->tx_queue_len = adapter->tx_queue_len;
2348                         adapter->tx_timeout_factor = 1;
2349                         switch (adapter->link_speed) {
2350                         case SPEED_10:
2351                                 netdev->tx_queue_len = 10;
2352                                 adapter->tx_timeout_factor = 14;
2353                                 break;
2354                         case SPEED_100:
2355                                 netdev->tx_queue_len = 100;
2356                                 /* maybe add some timeout factor ? */
2357                                 break;
2358                         }
2359
2360                         netif_carrier_on(netdev);
2361                         netif_tx_wake_all_queues(netdev);
2362
2363                         /* link state has changed, schedule phy info update */
2364                         if (!test_bit(__IGB_DOWN, &adapter->state))
2365                                 mod_timer(&adapter->phy_info_timer,
2366                                           round_jiffies(jiffies + 2 * HZ));
2367                 }
2368         } else {
2369                 if (netif_carrier_ok(netdev)) {
2370                         adapter->link_speed = 0;
2371                         adapter->link_duplex = 0;
2372                         /* Links status message must follow this format */
2373                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2374                                netdev->name);
2375                         netif_carrier_off(netdev);
2376                         netif_tx_stop_all_queues(netdev);
2377
2378                         /* link state has changed, schedule phy info update */
2379                         if (!test_bit(__IGB_DOWN, &adapter->state))
2380                                 mod_timer(&adapter->phy_info_timer,
2381                                           round_jiffies(jiffies + 2 * HZ));
2382                 }
2383         }
2384
2385 link_up:
2386         igb_update_stats(adapter);
2387
2388         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2389         adapter->tpt_old = adapter->stats.tpt;
2390         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2391         adapter->colc_old = adapter->stats.colc;
2392
2393         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2394         adapter->gorc_old = adapter->stats.gorc;
2395         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2396         adapter->gotc_old = adapter->stats.gotc;
2397
2398         igb_update_adaptive(&adapter->hw);
2399
2400         if (!netif_carrier_ok(netdev)) {
2401                 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2402                         /* We've lost link, so the controller stops DMA,
2403                          * but we've got queued Tx work that's never going
2404                          * to get done, so reset controller to flush Tx.
2405                          * (Do the reset outside of interrupt context). */
2406                         adapter->tx_timeout_count++;
2407                         schedule_work(&adapter->reset_task);
2408                 }
2409         }
2410
2411         /* Cause software interrupt to ensure rx ring is cleaned */
2412         if (adapter->msix_entries) {
2413                 for (i = 0; i < adapter->num_rx_queues; i++)
2414                         eics |= adapter->rx_ring[i].eims_value;
2415                 wr32(E1000_EICS, eics);
2416         } else {
2417                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2418         }
2419
2420         /* Force detection of hung controller every watchdog period */
2421         tx_ring->detect_tx_hung = true;
2422
2423         /* Reset the timer */
2424         if (!test_bit(__IGB_DOWN, &adapter->state))
2425                 mod_timer(&adapter->watchdog_timer,
2426                           round_jiffies(jiffies + 2 * HZ));
2427 }
2428
2429 enum latency_range {
2430         lowest_latency = 0,
2431         low_latency = 1,
2432         bulk_latency = 2,
2433         latency_invalid = 255
2434 };
2435
2436
2437 /**
2438  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2439  *
2440  *      Stores a new ITR value based on strictly on packet size.  This
2441  *      algorithm is less sophisticated than that used in igb_update_itr,
2442  *      due to the difficulty of synchronizing statistics across multiple
2443  *      receive rings.  The divisors and thresholds used by this fuction
2444  *      were determined based on theoretical maximum wire speed and testing
2445  *      data, in order to minimize response time while increasing bulk
2446  *      throughput.
2447  *      This functionality is controlled by the InterruptThrottleRate module
2448  *      parameter (see igb_param.c)
2449  *      NOTE:  This function is called only when operating in a multiqueue
2450  *             receive environment.
2451  * @rx_ring: pointer to ring
2452  **/
2453 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2454 {
2455         int new_val = rx_ring->itr_val;
2456         int avg_wire_size = 0;
2457         struct igb_adapter *adapter = rx_ring->adapter;
2458
2459         if (!rx_ring->total_packets)
2460                 goto clear_counts; /* no packets, so don't do anything */
2461
2462         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2463          * ints/sec - ITR timer value of 120 ticks.
2464          */
2465         if (adapter->link_speed != SPEED_1000) {
2466                 new_val = 120;
2467                 goto set_itr_val;
2468         }
2469         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2470
2471         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2472         avg_wire_size += 24;
2473
2474         /* Don't starve jumbo frames */
2475         avg_wire_size = min(avg_wire_size, 3000);
2476
2477         /* Give a little boost to mid-size frames */
2478         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2479                 new_val = avg_wire_size / 3;
2480         else
2481                 new_val = avg_wire_size / 2;
2482
2483 set_itr_val:
2484         if (new_val != rx_ring->itr_val) {
2485                 rx_ring->itr_val = new_val;
2486                 rx_ring->set_itr = 1;
2487         }
2488 clear_counts:
2489         rx_ring->total_bytes = 0;
2490         rx_ring->total_packets = 0;
2491 }
2492
2493 /**
2494  * igb_update_itr - update the dynamic ITR value based on statistics
2495  *      Stores a new ITR value based on packets and byte
2496  *      counts during the last interrupt.  The advantage of per interrupt
2497  *      computation is faster updates and more accurate ITR for the current
2498  *      traffic pattern.  Constants in this function were computed
2499  *      based on theoretical maximum wire speed and thresholds were set based
2500  *      on testing data as well as attempting to minimize response time
2501  *      while increasing bulk throughput.
2502  *      this functionality is controlled by the InterruptThrottleRate module
2503  *      parameter (see igb_param.c)
2504  *      NOTE:  These calculations are only valid when operating in a single-
2505  *             queue environment.
2506  * @adapter: pointer to adapter
2507  * @itr_setting: current adapter->itr
2508  * @packets: the number of packets during this measurement interval
2509  * @bytes: the number of bytes during this measurement interval
2510  **/
2511 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2512                                    int packets, int bytes)
2513 {
2514         unsigned int retval = itr_setting;
2515
2516         if (packets == 0)
2517                 goto update_itr_done;
2518
2519         switch (itr_setting) {
2520         case lowest_latency:
2521                 /* handle TSO and jumbo frames */
2522                 if (bytes/packets > 8000)
2523                         retval = bulk_latency;
2524                 else if ((packets < 5) && (bytes > 512))
2525                         retval = low_latency;
2526                 break;
2527         case low_latency:  /* 50 usec aka 20000 ints/s */
2528                 if (bytes > 10000) {
2529                         /* this if handles the TSO accounting */
2530                         if (bytes/packets > 8000) {
2531                                 retval = bulk_latency;
2532                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2533                                 retval = bulk_latency;
2534                         } else if ((packets > 35)) {
2535                                 retval = lowest_latency;
2536                         }
2537                 } else if (bytes/packets > 2000) {
2538                         retval = bulk_latency;
2539                 } else if (packets <= 2 && bytes < 512) {
2540                         retval = lowest_latency;
2541                 }
2542                 break;
2543         case bulk_latency: /* 250 usec aka 4000 ints/s */
2544                 if (bytes > 25000) {
2545                         if (packets > 35)
2546                                 retval = low_latency;
2547                 } else if (bytes < 6000) {
2548                         retval = low_latency;
2549                 }
2550                 break;
2551         }
2552
2553 update_itr_done:
2554         return retval;
2555 }
2556
2557 static void igb_set_itr(struct igb_adapter *adapter)
2558 {
2559         u16 current_itr;
2560         u32 new_itr = adapter->itr;
2561
2562         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2563         if (adapter->link_speed != SPEED_1000) {
2564                 current_itr = 0;
2565                 new_itr = 4000;
2566                 goto set_itr_now;
2567         }
2568
2569         adapter->rx_itr = igb_update_itr(adapter,
2570                                     adapter->rx_itr,
2571                                     adapter->rx_ring->total_packets,
2572                                     adapter->rx_ring->total_bytes);
2573
2574         if (adapter->rx_ring->buddy) {
2575                 adapter->tx_itr = igb_update_itr(adapter,
2576                                             adapter->tx_itr,
2577                                             adapter->tx_ring->total_packets,
2578                                             adapter->tx_ring->total_bytes);
2579
2580                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2581         } else {
2582                 current_itr = adapter->rx_itr;
2583         }
2584
2585         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2586         if (adapter->itr_setting == 3 &&
2587             current_itr == lowest_latency)
2588                 current_itr = low_latency;
2589
2590         switch (current_itr) {
2591         /* counts and packets in update_itr are dependent on these numbers */
2592         case lowest_latency:
2593                 new_itr = 70000;
2594                 break;
2595         case low_latency:
2596                 new_itr = 20000; /* aka hwitr = ~200 */
2597                 break;
2598         case bulk_latency:
2599                 new_itr = 4000;
2600                 break;
2601         default:
2602                 break;
2603         }
2604
2605 set_itr_now:
2606         adapter->rx_ring->total_bytes = 0;
2607         adapter->rx_ring->total_packets = 0;
2608         if (adapter->rx_ring->buddy) {
2609                 adapter->rx_ring->buddy->total_bytes = 0;
2610                 adapter->rx_ring->buddy->total_packets = 0;
2611         }
2612
2613         if (new_itr != adapter->itr) {
2614                 /* this attempts to bias the interrupt rate towards Bulk
2615                  * by adding intermediate steps when interrupt rate is
2616                  * increasing */
2617                 new_itr = new_itr > adapter->itr ?
2618                              min(adapter->itr + (new_itr >> 2), new_itr) :
2619                              new_itr;
2620                 /* Don't write the value here; it resets the adapter's
2621                  * internal timer, and causes us to delay far longer than
2622                  * we should between interrupts.  Instead, we write the ITR
2623                  * value at the beginning of the next interrupt so the timing
2624                  * ends up being correct.
2625                  */
2626                 adapter->itr = new_itr;
2627                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2628                 adapter->rx_ring->set_itr = 1;
2629         }
2630
2631         return;
2632 }
2633
2634
2635 #define IGB_TX_FLAGS_CSUM               0x00000001
2636 #define IGB_TX_FLAGS_VLAN               0x00000002
2637 #define IGB_TX_FLAGS_TSO                0x00000004
2638 #define IGB_TX_FLAGS_IPV4               0x00000008
2639 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2640 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2641
2642 static inline int igb_tso_adv(struct igb_adapter *adapter,
2643                               struct igb_ring *tx_ring,
2644                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2645 {
2646         struct e1000_adv_tx_context_desc *context_desc;
2647         unsigned int i;
2648         int err;
2649         struct igb_buffer *buffer_info;
2650         u32 info = 0, tu_cmd = 0;
2651         u32 mss_l4len_idx, l4len;
2652         *hdr_len = 0;
2653
2654         if (skb_header_cloned(skb)) {
2655                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2656                 if (err)
2657                         return err;
2658         }
2659
2660         l4len = tcp_hdrlen(skb);
2661         *hdr_len += l4len;
2662
2663         if (skb->protocol == htons(ETH_P_IP)) {
2664                 struct iphdr *iph = ip_hdr(skb);
2665                 iph->tot_len = 0;
2666                 iph->check = 0;
2667                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2668                                                          iph->daddr, 0,
2669                                                          IPPROTO_TCP,
2670                                                          0);
2671         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2672                 ipv6_hdr(skb)->payload_len = 0;
2673                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2674                                                        &ipv6_hdr(skb)->daddr,
2675                                                        0, IPPROTO_TCP, 0);
2676         }
2677
2678         i = tx_ring->next_to_use;
2679
2680         buffer_info = &tx_ring->buffer_info[i];
2681         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2682         /* VLAN MACLEN IPLEN */
2683         if (tx_flags & IGB_TX_FLAGS_VLAN)
2684                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2685         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2686         *hdr_len += skb_network_offset(skb);
2687         info |= skb_network_header_len(skb);
2688         *hdr_len += skb_network_header_len(skb);
2689         context_desc->vlan_macip_lens = cpu_to_le32(info);
2690
2691         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2692         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2693
2694         if (skb->protocol == htons(ETH_P_IP))
2695                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2696         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2697
2698         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2699
2700         /* MSS L4LEN IDX */
2701         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2702         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2703
2704         /* Context index must be unique per ring. */
2705         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2706                 mss_l4len_idx |= tx_ring->queue_index << 4;
2707
2708         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2709         context_desc->seqnum_seed = 0;
2710
2711         buffer_info->time_stamp = jiffies;
2712         buffer_info->next_to_watch = i;
2713         buffer_info->dma = 0;
2714         i++;
2715         if (i == tx_ring->count)
2716                 i = 0;
2717
2718         tx_ring->next_to_use = i;
2719
2720         return true;
2721 }
2722
2723 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2724                                         struct igb_ring *tx_ring,
2725                                         struct sk_buff *skb, u32 tx_flags)
2726 {
2727         struct e1000_adv_tx_context_desc *context_desc;
2728         unsigned int i;
2729         struct igb_buffer *buffer_info;
2730         u32 info = 0, tu_cmd = 0;
2731
2732         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2733             (tx_flags & IGB_TX_FLAGS_VLAN)) {
2734                 i = tx_ring->next_to_use;
2735                 buffer_info = &tx_ring->buffer_info[i];
2736                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2737
2738                 if (tx_flags & IGB_TX_FLAGS_VLAN)
2739                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2740                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2741                 if (skb->ip_summed == CHECKSUM_PARTIAL)
2742                         info |= skb_network_header_len(skb);
2743
2744                 context_desc->vlan_macip_lens = cpu_to_le32(info);
2745
2746                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2747
2748                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2749                         switch (skb->protocol) {
2750                         case cpu_to_be16(ETH_P_IP):
2751                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2752                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2753                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2754                                 break;
2755                         case cpu_to_be16(ETH_P_IPV6):
2756                                 /* XXX what about other V6 headers?? */
2757                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2758                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2759                                 break;
2760                         default:
2761                                 if (unlikely(net_ratelimit()))
2762                                         dev_warn(&adapter->pdev->dev,
2763                                             "partial checksum but proto=%x!\n",
2764                                             skb->protocol);
2765                                 break;
2766                         }
2767                 }
2768
2769                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2770                 context_desc->seqnum_seed = 0;
2771                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2772                         context_desc->mss_l4len_idx =
2773                                 cpu_to_le32(tx_ring->queue_index << 4);
2774                 else
2775                         context_desc->mss_l4len_idx = 0;
2776
2777                 buffer_info->time_stamp = jiffies;
2778                 buffer_info->next_to_watch = i;
2779                 buffer_info->dma = 0;
2780
2781                 i++;
2782                 if (i == tx_ring->count)
2783                         i = 0;
2784                 tx_ring->next_to_use = i;
2785
2786                 return true;
2787         }
2788
2789
2790         return false;
2791 }
2792
2793 #define IGB_MAX_TXD_PWR 16
2794 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
2795
2796 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2797                                  struct igb_ring *tx_ring, struct sk_buff *skb,
2798                                  unsigned int first)
2799 {
2800         struct igb_buffer *buffer_info;
2801         unsigned int len = skb_headlen(skb);
2802         unsigned int count = 0, i;
2803         unsigned int f;
2804
2805         i = tx_ring->next_to_use;
2806
2807         buffer_info = &tx_ring->buffer_info[i];
2808         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2809         buffer_info->length = len;
2810         /* set time_stamp *before* dma to help avoid a possible race */
2811         buffer_info->time_stamp = jiffies;
2812         buffer_info->next_to_watch = i;
2813         buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2814                                           PCI_DMA_TODEVICE);
2815         count++;
2816         i++;
2817         if (i == tx_ring->count)
2818                 i = 0;
2819
2820         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2821                 struct skb_frag_struct *frag;
2822
2823                 frag = &skb_shinfo(skb)->frags[f];
2824                 len = frag->size;
2825
2826                 buffer_info = &tx_ring->buffer_info[i];
2827                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2828                 buffer_info->length = len;
2829                 buffer_info->time_stamp = jiffies;
2830                 buffer_info->next_to_watch = i;
2831                 buffer_info->dma = pci_map_page(adapter->pdev,
2832                                                 frag->page,
2833                                                 frag->page_offset,
2834                                                 len,
2835                                                 PCI_DMA_TODEVICE);
2836
2837                 count++;
2838                 i++;
2839                 if (i == tx_ring->count)
2840                         i = 0;
2841         }
2842
2843         i = ((i == 0) ? tx_ring->count - 1 : i - 1);
2844         tx_ring->buffer_info[i].skb = skb;
2845         tx_ring->buffer_info[first].next_to_watch = i;
2846
2847         return count;
2848 }
2849
2850 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2851                                     struct igb_ring *tx_ring,
2852                                     int tx_flags, int count, u32 paylen,
2853                                     u8 hdr_len)
2854 {
2855         union e1000_adv_tx_desc *tx_desc = NULL;
2856         struct igb_buffer *buffer_info;
2857         u32 olinfo_status = 0, cmd_type_len;
2858         unsigned int i;
2859
2860         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2861                         E1000_ADVTXD_DCMD_DEXT);
2862
2863         if (tx_flags & IGB_TX_FLAGS_VLAN)
2864                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2865
2866         if (tx_flags & IGB_TX_FLAGS_TSO) {
2867                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2868
2869                 /* insert tcp checksum */
2870                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2871
2872                 /* insert ip checksum */
2873                 if (tx_flags & IGB_TX_FLAGS_IPV4)
2874                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2875
2876         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2877                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2878         }
2879
2880         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2881             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2882                          IGB_TX_FLAGS_VLAN)))
2883                 olinfo_status |= tx_ring->queue_index << 4;
2884
2885         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2886
2887         i = tx_ring->next_to_use;
2888         while (count--) {
2889                 buffer_info = &tx_ring->buffer_info[i];
2890                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2891                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2892                 tx_desc->read.cmd_type_len =
2893                         cpu_to_le32(cmd_type_len | buffer_info->length);
2894                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2895                 i++;
2896                 if (i == tx_ring->count)
2897                         i = 0;
2898         }
2899
2900         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2901         /* Force memory writes to complete before letting h/w
2902          * know there are new descriptors to fetch.  (Only
2903          * applicable for weak-ordered memory model archs,
2904          * such as IA-64). */
2905         wmb();
2906
2907         tx_ring->next_to_use = i;
2908         writel(i, adapter->hw.hw_addr + tx_ring->tail);
2909         /* we need this if more than one processor can write to our tail
2910          * at a time, it syncronizes IO on IA64/Altix systems */
2911         mmiowb();
2912 }
2913
2914 static int __igb_maybe_stop_tx(struct net_device *netdev,
2915                                struct igb_ring *tx_ring, int size)
2916 {
2917         struct igb_adapter *adapter = netdev_priv(netdev);
2918
2919         netif_stop_subqueue(netdev, tx_ring->queue_index);
2920
2921         /* Herbert's original patch had:
2922          *  smp_mb__after_netif_stop_queue();
2923          * but since that doesn't exist yet, just open code it. */
2924         smp_mb();
2925
2926         /* We need to check again in a case another CPU has just
2927          * made room available. */
2928         if (IGB_DESC_UNUSED(tx_ring) < size)
2929                 return -EBUSY;
2930
2931         /* A reprieve! */
2932         netif_wake_subqueue(netdev, tx_ring->queue_index);
2933         ++adapter->restart_queue;
2934         return 0;
2935 }
2936
2937 static int igb_maybe_stop_tx(struct net_device *netdev,
2938                              struct igb_ring *tx_ring, int size)
2939 {
2940         if (IGB_DESC_UNUSED(tx_ring) >= size)
2941                 return 0;
2942         return __igb_maybe_stop_tx(netdev, tx_ring, size);
2943 }
2944
2945 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2946
2947 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2948                                    struct net_device *netdev,
2949                                    struct igb_ring *tx_ring)
2950 {
2951         struct igb_adapter *adapter = netdev_priv(netdev);
2952         unsigned int first;
2953         unsigned int tx_flags = 0;
2954         unsigned int len;
2955         u8 hdr_len = 0;
2956         int tso = 0;
2957
2958         len = skb_headlen(skb);
2959
2960         if (test_bit(__IGB_DOWN, &adapter->state)) {
2961                 dev_kfree_skb_any(skb);
2962                 return NETDEV_TX_OK;
2963         }
2964
2965         if (skb->len <= 0) {
2966                 dev_kfree_skb_any(skb);
2967                 return NETDEV_TX_OK;
2968         }
2969
2970         /* need: 1 descriptor per page,
2971          *       + 2 desc gap to keep tail from touching head,
2972          *       + 1 desc for skb->data,
2973          *       + 1 desc for context descriptor,
2974          * otherwise try next time */
2975         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2976                 /* this is a hard error */
2977                 return NETDEV_TX_BUSY;
2978         }
2979         skb_orphan(skb);
2980
2981         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2982                 tx_flags |= IGB_TX_FLAGS_VLAN;
2983                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2984         }
2985
2986         if (skb->protocol == htons(ETH_P_IP))
2987                 tx_flags |= IGB_TX_FLAGS_IPV4;
2988
2989         first = tx_ring->next_to_use;
2990
2991         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2992                                               &hdr_len) : 0;
2993
2994         if (tso < 0) {
2995                 dev_kfree_skb_any(skb);
2996                 return NETDEV_TX_OK;
2997         }
2998
2999         if (tso)
3000                 tx_flags |= IGB_TX_FLAGS_TSO;
3001         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3002                         if (skb->ip_summed == CHECKSUM_PARTIAL)
3003                                 tx_flags |= IGB_TX_FLAGS_CSUM;
3004
3005         igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3006                          igb_tx_map_adv(adapter, tx_ring, skb, first),
3007                          skb->len, hdr_len);
3008
3009         netdev->trans_start = jiffies;
3010
3011         /* Make sure there is space in the ring for the next send. */
3012         igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3013
3014         return NETDEV_TX_OK;
3015 }
3016
3017 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3018 {
3019         struct igb_adapter *adapter = netdev_priv(netdev);
3020         struct igb_ring *tx_ring;
3021
3022         int r_idx = 0;
3023         r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3024         tx_ring = adapter->multi_tx_table[r_idx];
3025
3026         /* This goes back to the question of how to logically map a tx queue
3027          * to a flow.  Right now, performance is impacted slightly negatively
3028          * if using multiple tx queues.  If the stack breaks away from a
3029          * single qdisc implementation, we can look at this again. */
3030         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3031 }
3032
3033 /**
3034  * igb_tx_timeout - Respond to a Tx Hang
3035  * @netdev: network interface device structure
3036  **/
3037 static void igb_tx_timeout(struct net_device *netdev)
3038 {
3039         struct igb_adapter *adapter = netdev_priv(netdev);
3040         struct e1000_hw *hw = &adapter->hw;
3041
3042         /* Do the reset outside of interrupt context */
3043         adapter->tx_timeout_count++;
3044         schedule_work(&adapter->reset_task);
3045         wr32(E1000_EICS,
3046              (adapter->eims_enable_mask & ~adapter->eims_other));
3047 }
3048
3049 static void igb_reset_task(struct work_struct *work)
3050 {
3051         struct igb_adapter *adapter;
3052         adapter = container_of(work, struct igb_adapter, reset_task);
3053
3054         igb_reinit_locked(adapter);
3055 }
3056
3057 /**
3058  * igb_get_stats - Get System Network Statistics
3059  * @netdev: network interface device structure
3060  *
3061  * Returns the address of the device statistics structure.
3062  * The statistics are actually updated from the timer callback.
3063  **/
3064 static struct net_device_stats *
3065 igb_get_stats(struct net_device *netdev)
3066 {
3067         struct igb_adapter *adapter = netdev_priv(netdev);
3068
3069         /* only return the current stats */
3070         return &adapter->net_stats;
3071 }
3072
3073 /**
3074  * igb_change_mtu - Change the Maximum Transfer Unit
3075  * @netdev: network interface device structure
3076  * @new_mtu: new value for maximum frame size
3077  *
3078  * Returns 0 on success, negative on failure
3079  **/
3080 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3081 {
3082         struct igb_adapter *adapter = netdev_priv(netdev);
3083         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3084
3085         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3086             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3087                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3088                 return -EINVAL;
3089         }
3090
3091 #define MAX_STD_JUMBO_FRAME_SIZE 9234
3092         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3093                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3094                 return -EINVAL;
3095         }
3096
3097         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3098                 msleep(1);
3099         /* igb_down has a dependency on max_frame_size */
3100         adapter->max_frame_size = max_frame;
3101         if (netif_running(netdev))
3102                 igb_down(adapter);
3103
3104         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3105          * means we reserve 2 more, this pushes us to allocate from the next
3106          * larger slab size.
3107          * i.e. RXBUFFER_2048 --> size-4096 slab
3108          */
3109
3110         if (max_frame <= IGB_RXBUFFER_256)
3111                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3112         else if (max_frame <= IGB_RXBUFFER_512)
3113                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3114         else if (max_frame <= IGB_RXBUFFER_1024)
3115                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3116         else if (max_frame <= IGB_RXBUFFER_2048)
3117                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3118         else
3119 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3120                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3121 #else
3122                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3123 #endif
3124         /* adjust allocation if LPE protects us, and we aren't using SBP */
3125         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3126              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3127                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3128
3129         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3130                  netdev->mtu, new_mtu);
3131         netdev->mtu = new_mtu;
3132
3133         if (netif_running(netdev))
3134                 igb_up(adapter);
3135         else
3136                 igb_reset(adapter);
3137
3138         clear_bit(__IGB_RESETTING, &adapter->state);
3139
3140         return 0;
3141 }
3142
3143 /**
3144  * igb_update_stats - Update the board statistics counters
3145  * @adapter: board private structure
3146  **/
3147
3148 void igb_update_stats(struct igb_adapter *adapter)
3149 {
3150         struct e1000_hw *hw = &adapter->hw;
3151         struct pci_dev *pdev = adapter->pdev;
3152         u16 phy_tmp;
3153
3154 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3155
3156         /*
3157          * Prevent stats update while adapter is being reset, or if the pci
3158          * connection is down.
3159          */
3160         if (adapter->link_speed == 0)
3161                 return;
3162         if (pci_channel_offline(pdev))
3163                 return;
3164
3165         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3166         adapter->stats.gprc += rd32(E1000_GPRC);
3167         adapter->stats.gorc += rd32(E1000_GORCL);
3168         rd32(E1000_GORCH); /* clear GORCL */
3169         adapter->stats.bprc += rd32(E1000_BPRC);
3170         adapter->stats.mprc += rd32(E1000_MPRC);
3171         adapter->stats.roc += rd32(E1000_ROC);
3172
3173         adapter->stats.prc64 += rd32(E1000_PRC64);
3174         adapter->stats.prc127 += rd32(E1000_PRC127);
3175         adapter->stats.prc255 += rd32(E1000_PRC255);
3176         adapter->stats.prc511 += rd32(E1000_PRC511);
3177         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3178         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3179         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3180         adapter->stats.sec += rd32(E1000_SEC);
3181
3182         adapter->stats.mpc += rd32(E1000_MPC);
3183         adapter->stats.scc += rd32(E1000_SCC);
3184         adapter->stats.ecol += rd32(E1000_ECOL);
3185         adapter->stats.mcc += rd32(E1000_MCC);
3186         adapter->stats.latecol += rd32(E1000_LATECOL);
3187         adapter->stats.dc += rd32(E1000_DC);
3188         adapter->stats.rlec += rd32(E1000_RLEC);
3189         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3190         adapter->stats.xontxc += rd32(E1000_XONTXC);
3191         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3192         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3193         adapter->stats.fcruc += rd32(E1000_FCRUC);
3194         adapter->stats.gptc += rd32(E1000_GPTC);
3195         adapter->stats.gotc += rd32(E1000_GOTCL);
3196         rd32(E1000_GOTCH); /* clear GOTCL */
3197         adapter->stats.rnbc += rd32(E1000_RNBC);
3198         adapter->stats.ruc += rd32(E1000_RUC);
3199         adapter->stats.rfc += rd32(E1000_RFC);
3200         adapter->stats.rjc += rd32(E1000_RJC);
3201         adapter->stats.tor += rd32(E1000_TORH);
3202         adapter->stats.tot += rd32(E1000_TOTH);
3203         adapter->stats.tpr += rd32(E1000_TPR);
3204
3205         adapter->stats.ptc64 += rd32(E1000_PTC64);
3206         adapter->stats.ptc127 += rd32(E1000_PTC127);
3207         adapter->stats.ptc255 += rd32(E1000_PTC255);
3208         adapter->stats.ptc511 += rd32(E1000_PTC511);
3209         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3210         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3211
3212         adapter->stats.mptc += rd32(E1000_MPTC);
3213         adapter->stats.bptc += rd32(E1000_BPTC);
3214
3215         /* used for adaptive IFS */
3216
3217         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3218         adapter->stats.tpt += hw->mac.tx_packet_delta;
3219         hw->mac.collision_delta = rd32(E1000_COLC);
3220         adapter->stats.colc += hw->mac.collision_delta;
3221
3222         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3223         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3224         adapter->stats.tncrs += rd32(E1000_TNCRS);
3225         adapter->stats.tsctc += rd32(E1000_TSCTC);
3226         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3227
3228         adapter->stats.iac += rd32(E1000_IAC);
3229         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3230         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3231         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3232         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3233         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3234         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3235         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3236         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3237
3238         /* Fill out the OS statistics structure */
3239         adapter->net_stats.multicast = adapter->stats.mprc;
3240         adapter->net_stats.collisions = adapter->stats.colc;
3241
3242         /* Rx Errors */
3243
3244         /* RLEC on some newer hardware can be incorrect so build
3245         * our own version based on RUC and ROC */
3246         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3247                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3248                 adapter->stats.ruc + adapter->stats.roc +
3249                 adapter->stats.cexterr;
3250         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3251                                               adapter->stats.roc;
3252         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3253         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3254         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3255
3256         /* Tx Errors */
3257         adapter->net_stats.tx_errors = adapter->stats.ecol +
3258                                        adapter->stats.latecol;
3259         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3260         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3261         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3262
3263         /* Tx Dropped needs to be maintained elsewhere */
3264
3265         /* Phy Stats */
3266         if (hw->phy.media_type == e1000_media_type_copper) {
3267                 if ((adapter->link_speed == SPEED_1000) &&
3268                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
3269                                               &phy_tmp))) {
3270                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3271                         adapter->phy_stats.idle_errors += phy_tmp;
3272                 }
3273         }
3274
3275         /* Management Stats */
3276         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3277         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3278         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3279 }
3280
3281
3282 static irqreturn_t igb_msix_other(int irq, void *data)
3283 {
3284         struct net_device *netdev = data;
3285         struct igb_adapter *adapter = netdev_priv(netdev);
3286         struct e1000_hw *hw = &adapter->hw;
3287         u32 icr = rd32(E1000_ICR);
3288
3289         /* reading ICR causes bit 31 of EICR to be cleared */
3290
3291         if(icr & E1000_ICR_DOUTSYNC) {
3292                 /* HW is reporting DMA is out of sync */
3293                 adapter->stats.doosync++;
3294         }
3295         if (!(icr & E1000_ICR_LSC))
3296                 goto no_link_interrupt;
3297         hw->mac.get_link_status = 1;
3298         /* guard against interrupt when we're going down */
3299         if (!test_bit(__IGB_DOWN, &adapter->state))
3300                 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3301
3302 no_link_interrupt:
3303         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
3304         wr32(E1000_EIMS, adapter->eims_other);
3305
3306         return IRQ_HANDLED;
3307 }
3308
3309 static irqreturn_t igb_msix_tx(int irq, void *data)
3310 {
3311         struct igb_ring *tx_ring = data;
3312         struct igb_adapter *adapter = tx_ring->adapter;
3313         struct e1000_hw *hw = &adapter->hw;
3314
3315 #ifdef CONFIG_IGB_DCA
3316         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3317                 igb_update_tx_dca(tx_ring);
3318 #endif
3319         tx_ring->total_bytes = 0;
3320         tx_ring->total_packets = 0;
3321
3322         /* auto mask will automatically reenable the interrupt when we write
3323          * EICS */
3324         if (!igb_clean_tx_irq(tx_ring))
3325                 /* Ring was not completely cleaned, so fire another interrupt */
3326                 wr32(E1000_EICS, tx_ring->eims_value);
3327         else
3328                 wr32(E1000_EIMS, tx_ring->eims_value);
3329
3330         return IRQ_HANDLED;
3331 }
3332
3333 static void igb_write_itr(struct igb_ring *ring)
3334 {
3335         struct e1000_hw *hw = &ring->adapter->hw;
3336         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3337                 switch (hw->mac.type) {
3338                 case e1000_82576:
3339                         wr32(ring->itr_register,
3340                              ring->itr_val |
3341                              0x80000000);
3342                         break;
3343                 default:
3344                         wr32(ring->itr_register,
3345                              ring->itr_val |
3346                              (ring->itr_val << 16));
3347                         break;
3348                 }
3349                 ring->set_itr = 0;
3350         }
3351 }
3352
3353 static irqreturn_t igb_msix_rx(int irq, void *data)
3354 {
3355         struct igb_ring *rx_ring = data;
3356
3357         /* Write the ITR value calculated at the end of the
3358          * previous interrupt.
3359          */
3360
3361         igb_write_itr(rx_ring);
3362
3363         if (napi_schedule_prep(&rx_ring->napi))
3364                 __napi_schedule(&rx_ring->napi);
3365
3366 #ifdef CONFIG_IGB_DCA
3367         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3368                 igb_update_rx_dca(rx_ring);
3369 #endif
3370                 return IRQ_HANDLED;
3371 }
3372
3373 #ifdef CONFIG_IGB_DCA
3374 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3375 {
3376         u32 dca_rxctrl;
3377         struct igb_adapter *adapter = rx_ring->adapter;
3378         struct e1000_hw *hw = &adapter->hw;
3379         int cpu = get_cpu();
3380         int q = rx_ring->reg_idx;
3381
3382         if (rx_ring->cpu != cpu) {
3383                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3384                 if (hw->mac.type == e1000_82576) {
3385                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3386                         dca_rxctrl |= dca_get_tag(cpu) <<
3387                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3388                 } else {
3389                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3390                         dca_rxctrl |= dca_get_tag(cpu);
3391                 }
3392                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3393                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3394                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3395                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3396                 rx_ring->cpu = cpu;
3397         }
3398         put_cpu();
3399 }
3400
3401 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3402 {
3403         u32 dca_txctrl;
3404         struct igb_adapter *adapter = tx_ring->adapter;
3405         struct e1000_hw *hw = &adapter->hw;
3406         int cpu = get_cpu();
3407         int q = tx_ring->reg_idx;
3408
3409         if (tx_ring->cpu != cpu) {
3410                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3411                 if (hw->mac.type == e1000_82576) {
3412                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3413                         dca_txctrl |= dca_get_tag(cpu) <<
3414                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3415                 } else {
3416                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3417                         dca_txctrl |= dca_get_tag(cpu);
3418                 }
3419                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3420                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3421                 tx_ring->cpu = cpu;
3422         }
3423         put_cpu();
3424 }
3425
3426 static void igb_setup_dca(struct igb_adapter *adapter)
3427 {
3428         int i;
3429
3430         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3431                 return;
3432
3433         for (i = 0; i < adapter->num_tx_queues; i++) {
3434                 adapter->tx_ring[i].cpu = -1;
3435                 igb_update_tx_dca(&adapter->tx_ring[i]);
3436         }
3437         for (i = 0; i < adapter->num_rx_queues; i++) {
3438                 adapter->rx_ring[i].cpu = -1;
3439                 igb_update_rx_dca(&adapter->rx_ring[i]);
3440         }
3441 }
3442
3443 static int __igb_notify_dca(struct device *dev, void *data)
3444 {
3445         struct net_device *netdev = dev_get_drvdata(dev);
3446         struct igb_adapter *adapter = netdev_priv(netdev);
3447         struct e1000_hw *hw = &adapter->hw;
3448         unsigned long event = *(unsigned long *)data;
3449
3450         switch (event) {
3451         case DCA_PROVIDER_ADD:
3452                 /* if already enabled, don't do it again */
3453                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3454                         break;
3455                 /* Always use CB2 mode, difference is masked
3456                  * in the CB driver. */
3457                 wr32(E1000_DCA_CTRL, 2);
3458                 if (dca_add_requester(dev) == 0) {
3459                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3460                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3461                         igb_setup_dca(adapter);
3462                         break;
3463                 }
3464                 /* Fall Through since DCA is disabled. */
3465         case DCA_PROVIDER_REMOVE:
3466                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3467                         /* without this a class_device is left
3468                          * hanging around in the sysfs model */
3469                         dca_remove_requester(dev);
3470                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3471                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3472                         wr32(E1000_DCA_CTRL, 1);
3473                 }
3474                 break;
3475         }
3476
3477         return 0;
3478 }
3479
3480 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3481                           void *p)
3482 {
3483         int ret_val;
3484
3485         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3486                                          __igb_notify_dca);
3487
3488         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3489 }
3490 #endif /* CONFIG_IGB_DCA */
3491
3492 /**
3493  * igb_intr_msi - Interrupt Handler
3494  * @irq: interrupt number
3495  * @data: pointer to a network interface device structure
3496  **/
3497 static irqreturn_t igb_intr_msi(int irq, void *data)
3498 {
3499         struct net_device *netdev = data;
3500         struct igb_adapter *adapter = netdev_priv(netdev);
3501         struct e1000_hw *hw = &adapter->hw;
3502         /* read ICR disables interrupts using IAM */
3503         u32 icr = rd32(E1000_ICR);
3504
3505         igb_write_itr(adapter->rx_ring);
3506
3507         if(icr & E1000_ICR_DOUTSYNC) {
3508                 /* HW is reporting DMA is out of sync */
3509                 adapter->stats.doosync++;
3510         }
3511
3512         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3513                 hw->mac.get_link_status = 1;
3514                 if (!test_bit(__IGB_DOWN, &adapter->state))
3515                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3516         }
3517
3518         napi_schedule(&adapter->rx_ring[0].napi);
3519
3520         return IRQ_HANDLED;
3521 }
3522
3523 /**
3524  * igb_intr - Legacy Interrupt Handler
3525  * @irq: interrupt number
3526  * @data: pointer to a network interface device structure
3527  **/
3528 static irqreturn_t igb_intr(int irq, void *data)
3529 {
3530         struct net_device *netdev = data;
3531         struct igb_adapter *adapter = netdev_priv(netdev);
3532         struct e1000_hw *hw = &adapter->hw;
3533         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
3534          * need for the IMC write */
3535         u32 icr = rd32(E1000_ICR);
3536         if (!icr)
3537                 return IRQ_NONE;  /* Not our interrupt */
3538
3539         igb_write_itr(adapter->rx_ring);
3540
3541         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3542          * not set, then the adapter didn't send an interrupt */
3543         if (!(icr & E1000_ICR_INT_ASSERTED))
3544                 return IRQ_NONE;
3545
3546         if(icr & E1000_ICR_DOUTSYNC) {
3547                 /* HW is reporting DMA is out of sync */
3548                 adapter->stats.doosync++;
3549         }
3550
3551         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3552                 hw->mac.get_link_status = 1;
3553                 /* guard against interrupt when we're going down */
3554                 if (!test_bit(__IGB_DOWN, &adapter->state))
3555                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3556         }
3557
3558         napi_schedule(&adapter->rx_ring[0].napi);
3559
3560         return IRQ_HANDLED;
3561 }
3562
3563 /**
3564  * igb_poll - NAPI Rx polling callback
3565  * @napi: napi polling structure
3566  * @budget: count of how many packets we should handle
3567  **/
3568 static int igb_poll(struct napi_struct *napi, int budget)
3569 {
3570         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3571         struct igb_adapter *adapter = rx_ring->adapter;
3572         struct net_device *netdev = adapter->netdev;
3573         int tx_clean_complete, work_done = 0;
3574
3575         /* this poll routine only supports one tx and one rx queue */
3576 #ifdef CONFIG_IGB_DCA
3577         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3578                 igb_update_tx_dca(&adapter->tx_ring[0]);
3579 #endif
3580         tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
3581
3582 #ifdef CONFIG_IGB_DCA
3583         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3584                 igb_update_rx_dca(&adapter->rx_ring[0]);
3585 #endif
3586         igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
3587
3588         /* If no Tx and not enough Rx work done, exit the polling mode */
3589         if ((tx_clean_complete && (work_done < budget)) ||
3590             !netif_running(netdev)) {
3591                 if (adapter->itr_setting & 3)
3592                         igb_set_itr(adapter);
3593                 napi_complete(napi);
3594                 if (!test_bit(__IGB_DOWN, &adapter->state))
3595                         igb_irq_enable(adapter);
3596                 return 0;
3597         }
3598
3599         return 1;
3600 }
3601
3602 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3603 {
3604         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3605         struct igb_adapter *adapter = rx_ring->adapter;
3606         struct e1000_hw *hw = &adapter->hw;
3607         struct net_device *netdev = adapter->netdev;
3608         int work_done = 0;
3609
3610 #ifdef CONFIG_IGB_DCA
3611         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3612                 igb_update_rx_dca(rx_ring);
3613 #endif
3614         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
3615
3616
3617         /* If not enough Rx work done, exit the polling mode */
3618         if ((work_done == 0) || !netif_running(netdev)) {
3619                 napi_complete(napi);
3620
3621                 if (adapter->itr_setting & 3) {
3622                         if (adapter->num_rx_queues == 1)
3623                                 igb_set_itr(adapter);
3624                         else
3625                                 igb_update_ring_itr(rx_ring);
3626                 }
3627
3628                 if (!test_bit(__IGB_DOWN, &adapter->state))
3629                         wr32(E1000_EIMS, rx_ring->eims_value);
3630
3631                 return 0;
3632         }
3633
3634         return 1;
3635 }
3636
3637 /**
3638  * igb_clean_tx_irq - Reclaim resources after transmit completes
3639  * @adapter: board private structure
3640  * returns true if ring is completely cleaned
3641  **/
3642 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
3643 {
3644         struct igb_adapter *adapter = tx_ring->adapter;
3645         struct net_device *netdev = adapter->netdev;
3646         struct e1000_hw *hw = &adapter->hw;
3647         struct igb_buffer *buffer_info;
3648         struct sk_buff *skb;
3649         union e1000_adv_tx_desc *tx_desc, *eop_desc;
3650         unsigned int total_bytes = 0, total_packets = 0;
3651         unsigned int i, eop, count = 0;
3652         bool cleaned = false;
3653
3654         i = tx_ring->next_to_clean;
3655         eop = tx_ring->buffer_info[i].next_to_watch;
3656         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3657
3658         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3659                (count < tx_ring->count)) {
3660                 for (cleaned = false; !cleaned; count++) {
3661                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3662                         buffer_info = &tx_ring->buffer_info[i];
3663                         cleaned = (i == eop);
3664                         skb = buffer_info->skb;
3665
3666                         if (skb) {
3667                                 unsigned int segs, bytecount;
3668                                 /* gso_segs is currently only valid for tcp */
3669                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
3670                                 /* multiply data chunks by size of headers */
3671                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
3672                                             skb->len;
3673                                 total_packets += segs;
3674                                 total_bytes += bytecount;
3675                         }
3676
3677                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
3678                         tx_desc->wb.status = 0;
3679
3680                         i++;
3681                         if (i == tx_ring->count)
3682                                 i = 0;
3683                 }
3684
3685                 eop = tx_ring->buffer_info[i].next_to_watch;
3686                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3687         }
3688
3689         tx_ring->next_to_clean = i;
3690
3691         if (unlikely(count &&
3692                      netif_carrier_ok(netdev) &&
3693                      IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3694                 /* Make sure that anybody stopping the queue after this
3695                  * sees the new next_to_clean.
3696                  */
3697                 smp_mb();
3698                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3699                     !(test_bit(__IGB_DOWN, &adapter->state))) {
3700                         netif_wake_subqueue(netdev, tx_ring->queue_index);
3701                         ++adapter->restart_queue;
3702                 }
3703         }
3704
3705         if (tx_ring->detect_tx_hung) {
3706                 /* Detect a transmit hang in hardware, this serializes the
3707                  * check with the clearing of time_stamp and movement of i */
3708                 tx_ring->detect_tx_hung = false;
3709                 if (tx_ring->buffer_info[i].time_stamp &&
3710                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3711                                (adapter->tx_timeout_factor * HZ))
3712                     && !(rd32(E1000_STATUS) &
3713                          E1000_STATUS_TXOFF)) {
3714
3715                         /* detected Tx unit hang */
3716                         dev_err(&adapter->pdev->dev,
3717                                 "Detected Tx Unit Hang\n"
3718                                 "  Tx Queue             <%d>\n"
3719                                 "  TDH                  <%x>\n"
3720                                 "  TDT                  <%x>\n"
3721                                 "  next_to_use          <%x>\n"
3722                                 "  next_to_clean        <%x>\n"
3723                                 "buffer_info[next_to_clean]\n"
3724                                 "  time_stamp           <%lx>\n"
3725                                 "  next_to_watch        <%x>\n"
3726                                 "  jiffies              <%lx>\n"
3727                                 "  desc.status          <%x>\n",
3728                                 tx_ring->queue_index,
3729                                 readl(adapter->hw.hw_addr + tx_ring->head),
3730                                 readl(adapter->hw.hw_addr + tx_ring->tail),
3731                                 tx_ring->next_to_use,
3732                                 tx_ring->next_to_clean,
3733                                 tx_ring->buffer_info[i].time_stamp,
3734                                 eop,
3735                                 jiffies,
3736                                 eop_desc->wb.status);
3737                         netif_stop_subqueue(netdev, tx_ring->queue_index);
3738                 }
3739         }
3740         tx_ring->total_bytes += total_bytes;
3741         tx_ring->total_packets += total_packets;
3742         tx_ring->tx_stats.bytes += total_bytes;
3743         tx_ring->tx_stats.packets += total_packets;
3744         adapter->net_stats.tx_bytes += total_bytes;
3745         adapter->net_stats.tx_packets += total_packets;
3746         return (count < tx_ring->count);
3747 }
3748
3749 /**
3750  * igb_receive_skb - helper function to handle rx indications
3751  * @ring: pointer to receive ring receving this packet
3752  * @status: descriptor status field as written by hardware
3753  * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3754  * @skb: pointer to sk_buff to be indicated to stack
3755  **/
3756 static void igb_receive_skb(struct igb_ring *ring, u8 status,
3757                             union e1000_adv_rx_desc * rx_desc,
3758                             struct sk_buff *skb)
3759 {
3760         struct igb_adapter * adapter = ring->adapter;
3761         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3762
3763         skb_record_rx_queue(skb, ring->queue_index);
3764         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
3765                 if (vlan_extracted)
3766                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
3767                                          le16_to_cpu(rx_desc->wb.upper.vlan),
3768                                          skb);
3769                 else
3770                         napi_gro_receive(&ring->napi, skb);
3771         } else {
3772                 if (vlan_extracted)
3773                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3774                                           le16_to_cpu(rx_desc->wb.upper.vlan));
3775                 else
3776                         netif_receive_skb(skb);
3777         }
3778 }
3779
3780
3781 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3782                                        u32 status_err, struct sk_buff *skb)
3783 {
3784         skb->ip_summed = CHECKSUM_NONE;
3785
3786         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3787         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3788                 return;
3789         /* TCP/UDP checksum error bit is set */
3790         if (status_err &
3791             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3792                 /* let the stack verify checksum errors */
3793                 adapter->hw_csum_err++;
3794                 return;
3795         }
3796         /* It must be a TCP or UDP packet with a valid checksum */
3797         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3798                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3799
3800         adapter->hw_csum_good++;
3801 }
3802
3803 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3804                                  int *work_done, int budget)
3805 {
3806         struct igb_adapter *adapter = rx_ring->adapter;
3807         struct net_device *netdev = adapter->netdev;
3808         struct pci_dev *pdev = adapter->pdev;
3809         union e1000_adv_rx_desc *rx_desc , *next_rxd;
3810         struct igb_buffer *buffer_info , *next_buffer;
3811         struct sk_buff *skb;
3812         unsigned int i;
3813         u32 length, hlen, staterr;
3814         bool cleaned = false;
3815         int cleaned_count = 0;
3816         unsigned int total_bytes = 0, total_packets = 0;
3817
3818         i = rx_ring->next_to_clean;
3819         buffer_info = &rx_ring->buffer_info[i];
3820         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3821         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3822
3823         while (staterr & E1000_RXD_STAT_DD) {
3824                 if (*work_done >= budget)
3825                         break;
3826                 (*work_done)++;
3827
3828                 skb = buffer_info->skb;
3829                 prefetch(skb->data - NET_IP_ALIGN);
3830                 buffer_info->skb = NULL;
3831
3832                 i++;
3833                 if (i == rx_ring->count)
3834                         i = 0;
3835                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3836                 prefetch(next_rxd);
3837                 next_buffer = &rx_ring->buffer_info[i];
3838
3839                 length = le16_to_cpu(rx_desc->wb.upper.length);
3840                 cleaned = true;
3841                 cleaned_count++;
3842
3843                 if (!adapter->rx_ps_hdr_size) {
3844                         pci_unmap_single(pdev, buffer_info->dma,
3845                                          adapter->rx_buffer_len +
3846                                            NET_IP_ALIGN,
3847                                          PCI_DMA_FROMDEVICE);
3848                         skb_put(skb, length);
3849                         goto send_up;
3850                 }
3851
3852                 /* HW will not DMA in data larger than the given buffer, even
3853                  * if it parses the (NFS, of course) header to be larger.  In
3854                  * that case, it fills the header buffer and spills the rest
3855                  * into the page.
3856                  */
3857                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3858                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3859                 if (hlen > adapter->rx_ps_hdr_size)
3860                         hlen = adapter->rx_ps_hdr_size;
3861
3862                 if (!skb_shinfo(skb)->nr_frags) {
3863                         pci_unmap_single(pdev, buffer_info->dma,
3864                                          adapter->rx_ps_hdr_size +
3865                                            NET_IP_ALIGN,
3866                                          PCI_DMA_FROMDEVICE);
3867                         skb_put(skb, hlen);
3868                 }
3869
3870                 if (length) {
3871                         pci_unmap_page(pdev, buffer_info->page_dma,
3872                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3873                         buffer_info->page_dma = 0;
3874
3875                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3876                                                 buffer_info->page,
3877                                                 buffer_info->page_offset,
3878                                                 length);
3879
3880                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3881                             (page_count(buffer_info->page) != 1))
3882                                 buffer_info->page = NULL;
3883                         else
3884                                 get_page(buffer_info->page);
3885
3886                         skb->len += length;
3887                         skb->data_len += length;
3888
3889                         skb->truesize += length;
3890                 }
3891
3892                 if (!(staterr & E1000_RXD_STAT_EOP)) {
3893                         buffer_info->skb = next_buffer->skb;
3894                         buffer_info->dma = next_buffer->dma;
3895                         next_buffer->skb = skb;
3896                         next_buffer->dma = 0;
3897                         goto next_desc;
3898                 }
3899 send_up:
3900                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3901                         dev_kfree_skb_irq(skb);
3902                         goto next_desc;
3903                 }
3904
3905                 total_bytes += skb->len;
3906                 total_packets++;
3907
3908                 igb_rx_checksum_adv(adapter, staterr, skb);
3909
3910                 skb->protocol = eth_type_trans(skb, netdev);
3911
3912                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
3913
3914 next_desc:
3915                 rx_desc->wb.upper.status_error = 0;
3916
3917                 /* return some buffers to hardware, one at a time is too slow */
3918                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3919                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3920                         cleaned_count = 0;
3921                 }
3922
3923                 /* use prefetched values */
3924                 rx_desc = next_rxd;
3925                 buffer_info = next_buffer;
3926                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3927         }
3928
3929         rx_ring->next_to_clean = i;
3930         cleaned_count = IGB_DESC_UNUSED(rx_ring);
3931
3932         if (cleaned_count)
3933                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
3934
3935         rx_ring->total_packets += total_packets;
3936         rx_ring->total_bytes += total_bytes;
3937         rx_ring->rx_stats.packets += total_packets;
3938         rx_ring->rx_stats.bytes += total_bytes;
3939         adapter->net_stats.rx_bytes += total_bytes;
3940         adapter->net_stats.rx_packets += total_packets;
3941         return cleaned;
3942 }
3943
3944
3945 /**
3946  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3947  * @adapter: address of board private structure
3948  **/
3949 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
3950                                      int cleaned_count)
3951 {
3952         struct igb_adapter *adapter = rx_ring->adapter;
3953         struct net_device *netdev = adapter->netdev;
3954         struct pci_dev *pdev = adapter->pdev;
3955         union e1000_adv_rx_desc *rx_desc;
3956         struct igb_buffer *buffer_info;
3957         struct sk_buff *skb;
3958         unsigned int i;
3959         int bufsz;
3960
3961         i = rx_ring->next_to_use;
3962         buffer_info = &rx_ring->buffer_info[i];
3963
3964         if (adapter->rx_ps_hdr_size)
3965                 bufsz = adapter->rx_ps_hdr_size;
3966         else
3967                 bufsz = adapter->rx_buffer_len;
3968         bufsz += NET_IP_ALIGN;
3969
3970         while (cleaned_count--) {
3971                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3972
3973                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
3974                         if (!buffer_info->page) {
3975                                 buffer_info->page = alloc_page(GFP_ATOMIC);
3976                                 if (!buffer_info->page) {
3977                                         adapter->alloc_rx_buff_failed++;
3978                                         goto no_buffers;
3979                                 }
3980                                 buffer_info->page_offset = 0;
3981                         } else {
3982                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
3983                         }
3984                         buffer_info->page_dma =
3985                                 pci_map_page(pdev, buffer_info->page,
3986                                              buffer_info->page_offset,
3987                                              PAGE_SIZE / 2,
3988                                              PCI_DMA_FROMDEVICE);
3989                 }
3990
3991                 if (!buffer_info->skb) {
3992                         skb = netdev_alloc_skb(netdev, bufsz);
3993                         if (!skb) {
3994                                 adapter->alloc_rx_buff_failed++;
3995                                 goto no_buffers;
3996                         }
3997
3998                         /* Make buffer alignment 2 beyond a 16 byte boundary
3999                          * this will result in a 16 byte aligned IP header after
4000                          * the 14 byte MAC header is removed
4001                          */
4002                         skb_reserve(skb, NET_IP_ALIGN);
4003
4004                         buffer_info->skb = skb;
4005                         buffer_info->dma = pci_map_single(pdev, skb->data,
4006                                                           bufsz,
4007                                                           PCI_DMA_FROMDEVICE);
4008                 }
4009                 /* Refresh the desc even if buffer_addrs didn't change because
4010                  * each write-back erases this info. */
4011                 if (adapter->rx_ps_hdr_size) {
4012                         rx_desc->read.pkt_addr =
4013                              cpu_to_le64(buffer_info->page_dma);
4014                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4015                 } else {
4016                         rx_desc->read.pkt_addr =
4017                              cpu_to_le64(buffer_info->dma);
4018                         rx_desc->read.hdr_addr = 0;
4019                 }
4020
4021                 i++;
4022                 if (i == rx_ring->count)
4023                         i = 0;
4024                 buffer_info = &rx_ring->buffer_info[i];
4025         }
4026
4027 no_buffers:
4028         if (rx_ring->next_to_use != i) {
4029                 rx_ring->next_to_use = i;
4030                 if (i == 0)
4031                         i = (rx_ring->count - 1);
4032                 else
4033                         i--;
4034
4035                 /* Force memory writes to complete before letting h/w
4036                  * know there are new descriptors to fetch.  (Only
4037                  * applicable for weak-ordered memory model archs,
4038                  * such as IA-64). */
4039                 wmb();
4040                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4041         }
4042 }
4043
4044 /**
4045  * igb_mii_ioctl -
4046  * @netdev:
4047  * @ifreq:
4048  * @cmd:
4049  **/
4050 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4051 {
4052         struct igb_adapter *adapter = netdev_priv(netdev);
4053         struct mii_ioctl_data *data = if_mii(ifr);
4054
4055         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4056                 return -EOPNOTSUPP;
4057
4058         switch (cmd) {
4059         case SIOCGMIIPHY:
4060                 data->phy_id = adapter->hw.phy.addr;
4061                 break;
4062         case SIOCGMIIREG:
4063                 if (!capable(CAP_NET_ADMIN))
4064                         return -EPERM;
4065                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4066                                      &data->val_out))
4067                         return -EIO;
4068                 break;
4069         case SIOCSMIIREG:
4070         default:
4071                 return -EOPNOTSUPP;
4072         }
4073         return 0;
4074 }
4075
4076 /**
4077  * igb_ioctl -
4078  * @netdev:
4079  * @ifreq:
4080  * @cmd:
4081  **/
4082 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4083 {
4084         switch (cmd) {
4085         case SIOCGMIIPHY:
4086         case SIOCGMIIREG:
4087         case SIOCSMIIREG:
4088                 return igb_mii_ioctl(netdev, ifr, cmd);
4089         default:
4090                 return -EOPNOTSUPP;
4091         }
4092 }
4093
4094 static void igb_vlan_rx_register(struct net_device *netdev,
4095                                  struct vlan_group *grp)
4096 {
4097         struct igb_adapter *adapter = netdev_priv(netdev);
4098         struct e1000_hw *hw = &adapter->hw;
4099         u32 ctrl, rctl;
4100
4101         igb_irq_disable(adapter);
4102         adapter->vlgrp = grp;
4103
4104         if (grp) {
4105                 /* enable VLAN tag insert/strip */
4106                 ctrl = rd32(E1000_CTRL);
4107                 ctrl |= E1000_CTRL_VME;
4108                 wr32(E1000_CTRL, ctrl);
4109
4110                 /* enable VLAN receive filtering */
4111                 rctl = rd32(E1000_RCTL);
4112                 rctl &= ~E1000_RCTL_CFIEN;
4113                 wr32(E1000_RCTL, rctl);
4114                 igb_update_mng_vlan(adapter);
4115                 wr32(E1000_RLPML,
4116                                 adapter->max_frame_size + VLAN_TAG_SIZE);
4117         } else {
4118                 /* disable VLAN tag insert/strip */
4119                 ctrl = rd32(E1000_CTRL);
4120                 ctrl &= ~E1000_CTRL_VME;
4121                 wr32(E1000_CTRL, ctrl);
4122
4123                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4124                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4125                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4126                 }
4127                 wr32(E1000_RLPML,
4128                                 adapter->max_frame_size);
4129         }
4130
4131         if (!test_bit(__IGB_DOWN, &adapter->state))
4132                 igb_irq_enable(adapter);
4133 }
4134
4135 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4136 {
4137         struct igb_adapter *adapter = netdev_priv(netdev);
4138         struct e1000_hw *hw = &adapter->hw;
4139         u32 vfta, index;
4140
4141         if ((hw->mng_cookie.status &
4142              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4143             (vid == adapter->mng_vlan_id))
4144                 return;
4145         /* add VID to filter table */
4146         index = (vid >> 5) & 0x7F;
4147         vfta = array_rd32(E1000_VFTA, index);
4148         vfta |= (1 << (vid & 0x1F));
4149         igb_write_vfta(&adapter->hw, index, vfta);
4150 }
4151
4152 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4153 {
4154         struct igb_adapter *adapter = netdev_priv(netdev);
4155         struct e1000_hw *hw = &adapter->hw;
4156         u32 vfta, index;
4157
4158         igb_irq_disable(adapter);
4159         vlan_group_set_device(adapter->vlgrp, vid, NULL);
4160
4161         if (!test_bit(__IGB_DOWN, &adapter->state))
4162                 igb_irq_enable(adapter);
4163
4164         if ((adapter->hw.mng_cookie.status &
4165              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4166             (vid == adapter->mng_vlan_id)) {
4167                 /* release control to f/w */
4168                 igb_release_hw_control(adapter);
4169                 return;
4170         }
4171
4172         /* remove VID from filter table */
4173         index = (vid >> 5) & 0x7F;
4174         vfta = array_rd32(E1000_VFTA, index);
4175         vfta &= ~(1 << (vid & 0x1F));
4176         igb_write_vfta(&adapter->hw, index, vfta);
4177 }
4178
4179 static void igb_restore_vlan(struct igb_adapter *adapter)
4180 {
4181         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4182
4183         if (adapter->vlgrp) {
4184                 u16 vid;
4185                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4186                         if (!vlan_group_get_device(adapter->vlgrp, vid))
4187                                 continue;
4188                         igb_vlan_rx_add_vid(adapter->netdev, vid);
4189                 }
4190         }
4191 }
4192
4193 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4194 {
4195         struct e1000_mac_info *mac = &adapter->hw.mac;
4196
4197         mac->autoneg = 0;
4198
4199         /* Fiber NICs only allow 1000 gbps Full duplex */
4200         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4201                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4202                 dev_err(&adapter->pdev->dev,
4203                         "Unsupported Speed/Duplex configuration\n");
4204                 return -EINVAL;
4205         }
4206
4207         switch (spddplx) {
4208         case SPEED_10 + DUPLEX_HALF:
4209                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4210                 break;
4211         case SPEED_10 + DUPLEX_FULL:
4212                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4213                 break;
4214         case SPEED_100 + DUPLEX_HALF:
4215                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4216                 break;
4217         case SPEED_100 + DUPLEX_FULL:
4218                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4219                 break;
4220         case SPEED_1000 + DUPLEX_FULL:
4221                 mac->autoneg = 1;
4222                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4223                 break;
4224         case SPEED_1000 + DUPLEX_HALF: /* not supported */
4225         default:
4226                 dev_err(&adapter->pdev->dev,
4227                         "Unsupported Speed/Duplex configuration\n");
4228                 return -EINVAL;
4229         }
4230         return 0;
4231 }
4232
4233
4234 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4235 {
4236         struct net_device *netdev = pci_get_drvdata(pdev);
4237         struct igb_adapter *adapter = netdev_priv(netdev);
4238         struct e1000_hw *hw = &adapter->hw;
4239         u32 ctrl, rctl, status;
4240         u32 wufc = adapter->wol;
4241 #ifdef CONFIG_PM
4242         int retval = 0;
4243 #endif
4244
4245         netif_device_detach(netdev);
4246
4247         if (netif_running(netdev))
4248                 igb_close(netdev);
4249
4250         igb_reset_interrupt_capability(adapter);
4251
4252         igb_free_queues(adapter);
4253
4254 #ifdef CONFIG_PM
4255         retval = pci_save_state(pdev);
4256         if (retval)
4257                 return retval;
4258 #endif
4259
4260         status = rd32(E1000_STATUS);
4261         if (status & E1000_STATUS_LU)
4262                 wufc &= ~E1000_WUFC_LNKC;
4263
4264         if (wufc) {
4265                 igb_setup_rctl(adapter);
4266                 igb_set_multi(netdev);
4267
4268                 /* turn on all-multi mode if wake on multicast is enabled */
4269                 if (wufc & E1000_WUFC_MC) {
4270                         rctl = rd32(E1000_RCTL);
4271                         rctl |= E1000_RCTL_MPE;
4272                         wr32(E1000_RCTL, rctl);
4273                 }
4274
4275                 ctrl = rd32(E1000_CTRL);
4276                 /* advertise wake from D3Cold */
4277                 #define E1000_CTRL_ADVD3WUC 0x00100000
4278                 /* phy power management enable */
4279                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4280                 ctrl |= E1000_CTRL_ADVD3WUC;
4281                 wr32(E1000_CTRL, ctrl);
4282
4283                 /* Allow time for pending master requests to run */
4284                 igb_disable_pcie_master(&adapter->hw);
4285
4286                 wr32(E1000_WUC, E1000_WUC_PME_EN);
4287                 wr32(E1000_WUFC, wufc);
4288         } else {
4289                 wr32(E1000_WUC, 0);
4290                 wr32(E1000_WUFC, 0);
4291         }
4292
4293         /* make sure adapter isn't asleep if manageability/wol is enabled */
4294         if (wufc || adapter->en_mng_pt) {
4295                 pci_enable_wake(pdev, PCI_D3hot, 1);
4296                 pci_enable_wake(pdev, PCI_D3cold, 1);
4297         } else {
4298                 igb_shutdown_fiber_serdes_link_82575(hw);
4299                 pci_enable_wake(pdev, PCI_D3hot, 0);
4300                 pci_enable_wake(pdev, PCI_D3cold, 0);
4301         }
4302
4303         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
4304          * would have already happened in close and is redundant. */
4305         igb_release_hw_control(adapter);
4306
4307         pci_disable_device(pdev);
4308
4309         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4310
4311         return 0;
4312 }
4313
4314 #ifdef CONFIG_PM
4315 static int igb_resume(struct pci_dev *pdev)
4316 {
4317         struct net_device *netdev = pci_get_drvdata(pdev);
4318         struct igb_adapter *adapter = netdev_priv(netdev);
4319         struct e1000_hw *hw = &adapter->hw;
4320         u32 err;
4321
4322         pci_set_power_state(pdev, PCI_D0);
4323         pci_restore_state(pdev);
4324
4325         err = pci_enable_device_mem(pdev);
4326         if (err) {
4327                 dev_err(&pdev->dev,
4328                         "igb: Cannot enable PCI device from suspend\n");
4329                 return err;
4330         }
4331         pci_set_master(pdev);
4332
4333         pci_enable_wake(pdev, PCI_D3hot, 0);
4334         pci_enable_wake(pdev, PCI_D3cold, 0);
4335
4336         igb_set_interrupt_capability(adapter);
4337
4338         if (igb_alloc_queues(adapter)) {
4339                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4340                 return -ENOMEM;
4341         }
4342
4343         /* e1000_power_up_phy(adapter); */
4344
4345         igb_reset(adapter);
4346
4347         /* let the f/w know that the h/w is now under the control of the
4348          * driver. */
4349         igb_get_hw_control(adapter);
4350
4351         wr32(E1000_WUS, ~0);
4352
4353         if (netif_running(netdev)) {
4354                 err = igb_open(netdev);
4355                 if (err)
4356                         return err;
4357         }
4358
4359         netif_device_attach(netdev);
4360
4361         return 0;
4362 }
4363 #endif
4364
4365 static void igb_shutdown(struct pci_dev *pdev)
4366 {
4367         igb_suspend(pdev, PMSG_SUSPEND);
4368 }
4369
4370 #ifdef CONFIG_NET_POLL_CONTROLLER
4371 /*
4372  * Polling 'interrupt' - used by things like netconsole to send skbs
4373  * without having to re-enable interrupts. It's not called while
4374  * the interrupt routine is executing.
4375  */
4376 static void igb_netpoll(struct net_device *netdev)
4377 {
4378         struct igb_adapter *adapter = netdev_priv(netdev);
4379         struct e1000_hw *hw = &adapter->hw;
4380         int i;
4381
4382         if (!adapter->msix_entries) {
4383                 igb_irq_disable(adapter);
4384                 napi_schedule(&adapter->rx_ring[0].napi);
4385                 return;
4386         }
4387
4388         for (i = 0; i < adapter->num_tx_queues; i++) {
4389                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4390                 wr32(E1000_EIMC, tx_ring->eims_value);
4391                 igb_clean_tx_irq(tx_ring);
4392                 wr32(E1000_EIMS, tx_ring->eims_value);
4393         }
4394
4395         for (i = 0; i < adapter->num_rx_queues; i++) {
4396                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4397                 wr32(E1000_EIMC, rx_ring->eims_value);
4398                 napi_schedule(&rx_ring->napi);
4399         }
4400 }
4401 #endif /* CONFIG_NET_POLL_CONTROLLER */
4402
4403 /**
4404  * igb_io_error_detected - called when PCI error is detected
4405  * @pdev: Pointer to PCI device
4406  * @state: The current pci connection state
4407  *
4408  * This function is called after a PCI bus error affecting
4409  * this device has been detected.
4410  */
4411 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4412                                               pci_channel_state_t state)
4413 {
4414         struct net_device *netdev = pci_get_drvdata(pdev);
4415         struct igb_adapter *adapter = netdev_priv(netdev);
4416
4417         netif_device_detach(netdev);
4418
4419         if (netif_running(netdev))
4420                 igb_down(adapter);
4421         pci_disable_device(pdev);
4422
4423         /* Request a slot slot reset. */
4424         return PCI_ERS_RESULT_NEED_RESET;
4425 }
4426
4427 /**
4428  * igb_io_slot_reset - called after the pci bus has been reset.
4429  * @pdev: Pointer to PCI device
4430  *
4431  * Restart the card from scratch, as if from a cold-boot. Implementation
4432  * resembles the first-half of the igb_resume routine.
4433  */
4434 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4435 {
4436         struct net_device *netdev = pci_get_drvdata(pdev);
4437         struct igb_adapter *adapter = netdev_priv(netdev);
4438         struct e1000_hw *hw = &adapter->hw;
4439         pci_ers_result_t result;
4440         int err;
4441
4442         if (pci_enable_device_mem(pdev)) {
4443                 dev_err(&pdev->dev,
4444                         "Cannot re-enable PCI device after reset.\n");
4445                 result = PCI_ERS_RESULT_DISCONNECT;
4446         } else {
4447                 pci_set_master(pdev);
4448                 pci_restore_state(pdev);
4449
4450                 pci_enable_wake(pdev, PCI_D3hot, 0);
4451                 pci_enable_wake(pdev, PCI_D3cold, 0);
4452
4453                 igb_reset(adapter);
4454                 wr32(E1000_WUS, ~0);
4455                 result = PCI_ERS_RESULT_RECOVERED;
4456         }
4457
4458         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4459         if (err) {
4460                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4461                         "failed 0x%0x\n", err);
4462                 /* non-fatal, continue */
4463         }
4464
4465         return result;
4466 }
4467
4468 /**
4469  * igb_io_resume - called when traffic can start flowing again.
4470  * @pdev: Pointer to PCI device
4471  *
4472  * This callback is called when the error recovery driver tells us that
4473  * its OK to resume normal operation. Implementation resembles the
4474  * second-half of the igb_resume routine.
4475  */
4476 static void igb_io_resume(struct pci_dev *pdev)
4477 {
4478         struct net_device *netdev = pci_get_drvdata(pdev);
4479         struct igb_adapter *adapter = netdev_priv(netdev);
4480
4481         if (netif_running(netdev)) {
4482                 if (igb_up(adapter)) {
4483                         dev_err(&pdev->dev, "igb_up failed after reset\n");
4484                         return;
4485                 }
4486         }
4487
4488         netif_device_attach(netdev);
4489
4490         /* let the f/w know that the h/w is now under the control of the
4491          * driver. */
4492         igb_get_hw_control(adapter);
4493 }
4494
4495 /* igb_main.c */