drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  *
  19  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  20  *  RA 11 31 24.2
  21  *  Dec +69 19 52
  22  *  V 3.84
  23  *  B-V +1.62
  24  *
  25  *  Theory of operation
  26  *
  27  *  The driver is initialized through platform_device.  Structures which
  28  *  define the configuration needed by the board are defined in a
  29  *  board structure in arch/ppc/platforms (though I do not
  30  *  discount the possibility that other architectures could one
  31  *  day be supported.
  32  *
  33  *  The Gianfar Ethernet Controller uses a ring of buffer
  34  *  descriptors.  The beginning is indicated by a register
  35  *  pointing to the physical address of the start of the ring.
  36  *  The end is determined by a "wrap" bit being set in the
  37  *  last descriptor of the ring.
  38  *
  39  *  When a packet is received, the RXF bit in the
  40  *  IEVENT register is set, triggering an interrupt when the
  41  *  corresponding bit in the IMASK register is also set (if
  42  *  interrupt coalescing is active, then the interrupt may not
  43  *  happen immediately, but will wait until either a set number
  44  *  of frames or amount of time have passed).  In NAPI, the
  45  *  interrupt handler will signal there is work to be done, and
  46  *  exit.  Without NAPI, the packet(s) will be handled
  47  *  immediately.  Both methods will start at the last known empty
  48  *  descriptor, and process every subsequent descriptor until there
  49  *  are none left with data (NAPI will stop after a set number of
  50  *  packets to give time to other tasks, but will eventually
  51  *  process all the packets).  The data arrives inside a
  52  *  pre-allocated skb, and so after the skb is passed up to the
  53  *  stack, a new skb must be allocated, and the address field in
  54  *  the buffer descriptor must be updated to indicate this new
  55  *  skb.
  56  *
  57  *  When the kernel requests that a packet be transmitted, the
  58  *  driver starts where it left off last time, and points the
  59  *  descriptor at the buffer which was passed in.  The driver
  60  *  then informs the DMA engine that there are packets ready to
  61  *  be transmitted.  Once the controller is finished transmitting
  62  *  the packet, an interrupt may be triggered (under the same
  63  *  conditions as for reception, but depending on the TXF bit).
  64  *  The driver then cleans up the buffer.
  65  */
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/platform_device.h>
  82 #include <linux/ip.h>
  83 #include <linux/tcp.h>
  84 #include <linux/udp.h>
  85 #include <linux/in.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95
  96 #include "gianfar.h"
  97 #include "gianfar_mii.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #define SKB_ALLOC_TIMEOUT 1000000
 101 #undef BRIEF_GFAR_ERRORS
 102 #undef VERBOSE_GFAR_ERRORS
 103
 104 #ifdef CONFIG_GFAR_NAPI
 105 #define RECEIVE(x) netif_receive_skb(x)
 106 #else
 107 #define RECEIVE(x) netif_rx(x)
 108 #endif
 109
 110 const char gfar_driver_name[] = "Gianfar Ethernet";
 111 const char gfar_driver_version[] = "1.3";
 112
 113 static int gfar_enet_open(struct net_device *dev);
 114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 115 static void gfar_timeout(struct net_device *dev);
 116 static int gfar_close(struct net_device *dev);
 117 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
 118 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
 119 static int gfar_set_mac_address(struct net_device *dev);
 120 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 121 static irqreturn_t gfar_error(int irq, void *dev_id);
 122 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 123 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 124 static void adjust_link(struct net_device *dev);
 125 static void init_registers(struct net_device *dev);
 126 static int init_phy(struct net_device *dev);
 127 static int gfar_probe(struct platform_device *pdev);
 128 static int gfar_remove(struct platform_device *pdev);
 129 static void free_skb_resources(struct gfar_private *priv);
 130 static void gfar_set_multi(struct net_device *dev);
 131 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 132 #ifdef CONFIG_GFAR_NAPI
 133 static int gfar_poll(struct net_device *dev, int *budget);
 134 #endif
 135 #ifdef CONFIG_NET_POLL_CONTROLLER
 136 static void gfar_netpoll(struct net_device *dev);
 137 #endif
 138 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 139 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 140 static void gfar_vlan_rx_register(struct net_device *netdev,
 141                                 struct vlan_group *grp);
 142 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
 143 void gfar_halt(struct net_device *dev);
 144 void gfar_start(struct net_device *dev);
 145 static void gfar_clear_exact_match(struct net_device *dev);
 146 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 147
 148 extern const struct ethtool_ops gfar_ethtool_ops;
 149
 150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 152 MODULE_LICENSE("GPL");
 153
 154 /* Returns 1 if incoming frames use an FCB */
 155 static inline int gfar_uses_fcb(struct gfar_private *priv)
 156 {
 157         return (priv->vlan_enable || priv->rx_csum_enable);
 158 }
 159
 160 /* Set up the ethernet device structure, private data,
 161  * and anything else we need before we start */
 162 static int gfar_probe(struct platform_device *pdev)
 163 {
 164         u32 tempval;
 165         struct net_device *dev = NULL;
 166         struct gfar_private *priv = NULL;
 167         struct gianfar_platform_data *einfo;
 168         struct resource *r;
 169         int idx;
 170         int err = 0;
 171
 172         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 173
 174         if (NULL == einfo) {
 175                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 176                        pdev->id);
 177
 178                 return -ENODEV;
 179         }
 180
 181         /* Create an ethernet device instance */
 182         dev = alloc_etherdev(sizeof (*priv));
 183
 184         if (NULL == dev)
 185                 return -ENOMEM;
 186
 187         priv = netdev_priv(dev);
 188
 189         /* Set the info in the priv to the current info */
 190         priv->einfo = einfo;
 191
 192         /* fill out IRQ fields */
 193         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 194                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 195                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 196                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 197                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 198                         goto regs_fail;
 199         } else {
 200                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 201                 if (priv->interruptTransmit < 0)
 202                         goto regs_fail;
 203         }
 204
 205         /* get a pointer to the register memory */
 206         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 207         priv->regs = ioremap(r->start, sizeof (struct gfar));
 208
 209         if (NULL == priv->regs) {
 210                 err = -ENOMEM;
 211                 goto regs_fail;
 212         }
 213
 214         spin_lock_init(&priv->txlock);
 215         spin_lock_init(&priv->rxlock);
 216
 217         platform_set_drvdata(pdev, dev);
 218
 219         /* Stop the DMA engine now, in case it was running before */
 220         /* (The firmware could have used it, and left it running). */
 221         /* To do this, we write Graceful Receive Stop and Graceful */
 222         /* Transmit Stop, and then wait until the corresponding bits */
 223         /* in IEVENT indicate the stops have completed. */
 224         tempval = gfar_read(&priv->regs->dmactrl);
 225         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 226         gfar_write(&priv->regs->dmactrl, tempval);
 227
 228         tempval = gfar_read(&priv->regs->dmactrl);
 229         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 230         gfar_write(&priv->regs->dmactrl, tempval);
 231
 232         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 233                 cpu_relax();
 234
 235         /* Reset MAC layer */
 236         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 237
 238         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 239         gfar_write(&priv->regs->maccfg1, tempval);
 240
 241         /* Initialize MACCFG2. */
 242         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 243
 244         /* Initialize ECNTRL */
 245         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 246
 247         /* Copy the station address into the dev structure, */
 248         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 249
 250         /* Set the dev->base_addr to the gfar reg region */
 251         dev->base_addr = (unsigned long) (priv->regs);
 252
 253         SET_MODULE_OWNER(dev);
 254         SET_NETDEV_DEV(dev, &pdev->dev);
 255
 256         /* Fill in the dev structure */
 257         dev->open = gfar_enet_open;
 258         dev->hard_start_xmit = gfar_start_xmit;
 259         dev->tx_timeout = gfar_timeout;
 260         dev->watchdog_timeo = TX_TIMEOUT;
 261 #ifdef CONFIG_GFAR_NAPI
 262         dev->poll = gfar_poll;
 263         dev->weight = GFAR_DEV_WEIGHT;
 264 #endif
 265 #ifdef CONFIG_NET_POLL_CONTROLLER
 266         dev->poll_controller = gfar_netpoll;
 267 #endif
 268         dev->stop = gfar_close;
 269         dev->get_stats = gfar_get_stats;
 270         dev->change_mtu = gfar_change_mtu;
 271         dev->mtu = 1500;
 272         dev->set_multicast_list = gfar_set_multi;
 273
 274         dev->ethtool_ops = &gfar_ethtool_ops;
 275
 276         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 277                 priv->rx_csum_enable = 1;
 278                 dev->features |= NETIF_F_IP_CSUM;
 279         } else
 280                 priv->rx_csum_enable = 0;
 281
 282         priv->vlgrp = NULL;
 283
 284         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 285                 dev->vlan_rx_register = gfar_vlan_rx_register;
 286                 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
 287
 288                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 289
 290                 priv->vlan_enable = 1;
 291         }
 292
 293         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 294                 priv->extended_hash = 1;
 295                 priv->hash_width = 9;
 296
 297                 priv->hash_regs[0] = &priv->regs->igaddr0;
 298                 priv->hash_regs[1] = &priv->regs->igaddr1;
 299                 priv->hash_regs[2] = &priv->regs->igaddr2;
 300                 priv->hash_regs[3] = &priv->regs->igaddr3;
 301                 priv->hash_regs[4] = &priv->regs->igaddr4;
 302                 priv->hash_regs[5] = &priv->regs->igaddr5;
 303                 priv->hash_regs[6] = &priv->regs->igaddr6;
 304                 priv->hash_regs[7] = &priv->regs->igaddr7;
 305                 priv->hash_regs[8] = &priv->regs->gaddr0;
 306                 priv->hash_regs[9] = &priv->regs->gaddr1;
 307                 priv->hash_regs[10] = &priv->regs->gaddr2;
 308                 priv->hash_regs[11] = &priv->regs->gaddr3;
 309                 priv->hash_regs[12] = &priv->regs->gaddr4;
 310                 priv->hash_regs[13] = &priv->regs->gaddr5;
 311                 priv->hash_regs[14] = &priv->regs->gaddr6;
 312                 priv->hash_regs[15] = &priv->regs->gaddr7;
 313
 314         } else {
 315                 priv->extended_hash = 0;
 316                 priv->hash_width = 8;
 317
 318                 priv->hash_regs[0] = &priv->regs->gaddr0;
 319                 priv->hash_regs[1] = &priv->regs->gaddr1;
 320                 priv->hash_regs[2] = &priv->regs->gaddr2;
 321                 priv->hash_regs[3] = &priv->regs->gaddr3;
 322                 priv->hash_regs[4] = &priv->regs->gaddr4;
 323                 priv->hash_regs[5] = &priv->regs->gaddr5;
 324                 priv->hash_regs[6] = &priv->regs->gaddr6;
 325                 priv->hash_regs[7] = &priv->regs->gaddr7;
 326         }
 327
 328         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 329                 priv->padding = DEFAULT_PADDING;
 330         else
 331                 priv->padding = 0;
 332
 333         if (dev->features & NETIF_F_IP_CSUM)
 334                 dev->hard_header_len += GMAC_FCB_LEN;
 335
 336         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 337         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 338         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 339
 340         priv->txcoalescing = DEFAULT_TX_COALESCE;
 341         priv->txcount = DEFAULT_TXCOUNT;
 342         priv->txtime = DEFAULT_TXTIME;
 343         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 344         priv->rxcount = DEFAULT_RXCOUNT;
 345         priv->rxtime = DEFAULT_RXTIME;
 346
 347         /* Enable most messages by default */
 348         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 349
 350         err = register_netdev(dev);
 351
 352         if (err) {
 353                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 354                                 dev->name);
 355                 goto register_fail;
 356         }
 357
 358         /* Create all the sysfs files */
 359         gfar_init_sysfs(dev);
 360
 361         /* Print out the device info */
 362         printk(KERN_INFO DEVICE_NAME, dev->name);
 363         for (idx = 0; idx < 6; idx++)
 364                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
 365         printk("\n");
 366
 367         /* Even more device info helps when determining which kernel */
 368         /* provided which set of benchmarks. */
 369 #ifdef CONFIG_GFAR_NAPI
 370         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 371 #else
 372         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
 373 #endif
 374         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 375                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 376
 377         return 0;
 378
 379 register_fail:
 380         iounmap(priv->regs);
 381 regs_fail:
 382         free_netdev(dev);
 383         return err;
 384 }
 385
 386 static int gfar_remove(struct platform_device *pdev)
 387 {
 388         struct net_device *dev = platform_get_drvdata(pdev);
 389         struct gfar_private *priv = netdev_priv(dev);
 390
 391         platform_set_drvdata(pdev, NULL);
 392
 393         iounmap(priv->regs);
 394         free_netdev(dev);
 395
 396         return 0;
 397 }
 398
 399
 400 /* Reads the controller's registers to determine what interface
 401  * connects it to the PHY.
 402  */
 403 static phy_interface_t gfar_get_interface(struct net_device *dev)
 404 {
 405         struct gfar_private *priv = netdev_priv(dev);
 406         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 407
 408         if (ecntrl & ECNTRL_SGMII_MODE)
 409                 return PHY_INTERFACE_MODE_SGMII;
 410
 411         if (ecntrl & ECNTRL_TBI_MODE) {
 412                 if (ecntrl & ECNTRL_REDUCED_MODE)
 413                         return PHY_INTERFACE_MODE_RTBI;
 414                 else
 415                         return PHY_INTERFACE_MODE_TBI;
 416         }
 417
 418         if (ecntrl & ECNTRL_REDUCED_MODE) {
 419                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 420                         return PHY_INTERFACE_MODE_RMII;
 421                 else
 422                         return PHY_INTERFACE_MODE_RGMII;
 423         }
 424
 425         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 426                 return PHY_INTERFACE_MODE_GMII;
 427
 428         return PHY_INTERFACE_MODE_MII;
 429 }
 430
 431
 432 /* Initializes driver's PHY state, and attaches to the PHY.
 433  * Returns 0 on success.
 434  */
 435 static int init_phy(struct net_device *dev)
 436 {
 437         struct gfar_private *priv = netdev_priv(dev);
 438         uint gigabit_support =
 439                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 440                 SUPPORTED_1000baseT_Full : 0;
 441         struct phy_device *phydev;
 442         char phy_id[BUS_ID_SIZE];
 443         phy_interface_t interface;
 444
 445         priv->oldlink = 0;
 446         priv->oldspeed = 0;
 447         priv->oldduplex = -1;
 448
 449         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 450
 451         interface = gfar_get_interface(dev);
 452
 453         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 454
 455         if (IS_ERR(phydev)) {
 456                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 457                 return PTR_ERR(phydev);
 458         }
 459
 460         /* Remove any features not supported by the controller */
 461         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 462         phydev->advertising = phydev->supported;
 463
 464         priv->phydev = phydev;
 465
 466         return 0;
 467 }
 468
 469 static void init_registers(struct net_device *dev)
 470 {
 471         struct gfar_private *priv = netdev_priv(dev);
 472
 473         /* Clear IEVENT */
 474         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 475
 476         /* Initialize IMASK */
 477         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 478
 479         /* Init hash registers to zero */
 480         gfar_write(&priv->regs->igaddr0, 0);
 481         gfar_write(&priv->regs->igaddr1, 0);
 482         gfar_write(&priv->regs->igaddr2, 0);
 483         gfar_write(&priv->regs->igaddr3, 0);
 484         gfar_write(&priv->regs->igaddr4, 0);
 485         gfar_write(&priv->regs->igaddr5, 0);
 486         gfar_write(&priv->regs->igaddr6, 0);
 487         gfar_write(&priv->regs->igaddr7, 0);
 488
 489         gfar_write(&priv->regs->gaddr0, 0);
 490         gfar_write(&priv->regs->gaddr1, 0);
 491         gfar_write(&priv->regs->gaddr2, 0);
 492         gfar_write(&priv->regs->gaddr3, 0);
 493         gfar_write(&priv->regs->gaddr4, 0);
 494         gfar_write(&priv->regs->gaddr5, 0);
 495         gfar_write(&priv->regs->gaddr6, 0);
 496         gfar_write(&priv->regs->gaddr7, 0);
 497
 498         /* Zero out the rmon mib registers if it has them */
 499         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 500                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 501
 502                 /* Mask off the CAM interrupts */
 503                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 504                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 505         }
 506
 507         /* Initialize the max receive buffer length */
 508         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 509
 510         /* Initialize the Minimum Frame Length Register */
 511         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 512
 513         /* Assign the TBI an address which won't conflict with the PHYs */
 514         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
 515 }
 516
 517
 518 /* Halt the receive and transmit queues */
 519 void gfar_halt(struct net_device *dev)
 520 {
 521         struct gfar_private *priv = netdev_priv(dev);
 522         struct gfar __iomem *regs = priv->regs;
 523         u32 tempval;
 524
 525         /* Mask all interrupts */
 526         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 527
 528         /* Clear all interrupts */
 529         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 530
 531         /* Stop the DMA, and wait for it to stop */
 532         tempval = gfar_read(&priv->regs->dmactrl);
 533         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 534             != (DMACTRL_GRS | DMACTRL_GTS)) {
 535                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 536                 gfar_write(&priv->regs->dmactrl, tempval);
 537
 538                 while (!(gfar_read(&priv->regs->ievent) &
 539                          (IEVENT_GRSC | IEVENT_GTSC)))
 540                         cpu_relax();
 541         }
 542
 543         /* Disable Rx and Tx */
 544         tempval = gfar_read(&regs->maccfg1);
 545         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 546         gfar_write(&regs->maccfg1, tempval);
 547 }
 548
 549 void stop_gfar(struct net_device *dev)
 550 {
 551         struct gfar_private *priv = netdev_priv(dev);
 552         struct gfar __iomem *regs = priv->regs;
 553         unsigned long flags;
 554
 555         phy_stop(priv->phydev);
 556
 557         /* Lock it down */
 558         spin_lock_irqsave(&priv->txlock, flags);
 559         spin_lock(&priv->rxlock);
 560
 561         gfar_halt(dev);
 562
 563         spin_unlock(&priv->rxlock);
 564         spin_unlock_irqrestore(&priv->txlock, flags);
 565
 566         /* Free the IRQs */
 567         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 568                 free_irq(priv->interruptError, dev);
 569                 free_irq(priv->interruptTransmit, dev);
 570                 free_irq(priv->interruptReceive, dev);
 571         } else {
 572                 free_irq(priv->interruptTransmit, dev);
 573         }
 574
 575         free_skb_resources(priv);
 576
 577         dma_free_coherent(NULL,
 578                         sizeof(struct txbd8)*priv->tx_ring_size
 579                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 580                         priv->tx_bd_base,
 581                         gfar_read(&regs->tbase0));
 582 }
 583
 584 /* If there are any tx skbs or rx skbs still around, free them.
 585  * Then free tx_skbuff and rx_skbuff */
 586 static void free_skb_resources(struct gfar_private *priv)
 587 {
 588         struct rxbd8 *rxbdp;
 589         struct txbd8 *txbdp;
 590         int i;
 591
 592         /* Go through all the buffer descriptors and free their data buffers */
 593         txbdp = priv->tx_bd_base;
 594
 595         for (i = 0; i < priv->tx_ring_size; i++) {
 596
 597                 if (priv->tx_skbuff[i]) {
 598                         dma_unmap_single(NULL, txbdp->bufPtr,
 599                                         txbdp->length,
 600                                         DMA_TO_DEVICE);
 601                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 602                         priv->tx_skbuff[i] = NULL;
 603                 }
 604         }
 605
 606         kfree(priv->tx_skbuff);
 607
 608         rxbdp = priv->rx_bd_base;
 609
 610         /* rx_skbuff is not guaranteed to be allocated, so only
 611          * free it and its contents if it is allocated */
 612         if(priv->rx_skbuff != NULL) {
 613                 for (i = 0; i < priv->rx_ring_size; i++) {
 614                         if (priv->rx_skbuff[i]) {
 615                                 dma_unmap_single(NULL, rxbdp->bufPtr,
 616                                                 priv->rx_buffer_size,
 617                                                 DMA_FROM_DEVICE);
 618
 619                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 620                                 priv->rx_skbuff[i] = NULL;
 621                         }
 622
 623                         rxbdp->status = 0;
 624                         rxbdp->length = 0;
 625                         rxbdp->bufPtr = 0;
 626
 627                         rxbdp++;
 628                 }
 629
 630                 kfree(priv->rx_skbuff);
 631         }
 632 }
 633
 634 void gfar_start(struct net_device *dev)
 635 {
 636         struct gfar_private *priv = netdev_priv(dev);
 637         struct gfar __iomem *regs = priv->regs;
 638         u32 tempval;
 639
 640         /* Enable Rx and Tx in MACCFG1 */
 641         tempval = gfar_read(&regs->maccfg1);
 642         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 643         gfar_write(&regs->maccfg1, tempval);
 644
 645         /* Initialize DMACTRL to have WWR and WOP */
 646         tempval = gfar_read(&priv->regs->dmactrl);
 647         tempval |= DMACTRL_INIT_SETTINGS;
 648         gfar_write(&priv->regs->dmactrl, tempval);
 649
 650         /* Make sure we aren't stopped */
 651         tempval = gfar_read(&priv->regs->dmactrl);
 652         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 653         gfar_write(&priv->regs->dmactrl, tempval);
 654
 655         /* Clear THLT/RHLT, so that the DMA starts polling now */
 656         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 657         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 658
 659         /* Unmask the interrupts we look for */
 660         gfar_write(&regs->imask, IMASK_DEFAULT);
 661 }
 662
 663 /* Bring the controller up and running */
 664 int startup_gfar(struct net_device *dev)
 665 {
 666         struct txbd8 *txbdp;
 667         struct rxbd8 *rxbdp;
 668         dma_addr_t addr;
 669         unsigned long vaddr;
 670         int i;
 671         struct gfar_private *priv = netdev_priv(dev);
 672         struct gfar __iomem *regs = priv->regs;
 673         int err = 0;
 674         u32 rctrl = 0;
 675         u32 attrs = 0;
 676
 677         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 678
 679         /* Allocate memory for the buffer descriptors */
 680         vaddr = (unsigned long) dma_alloc_coherent(NULL,
 681                         sizeof (struct txbd8) * priv->tx_ring_size +
 682                         sizeof (struct rxbd8) * priv->rx_ring_size,
 683                         &addr, GFP_KERNEL);
 684
 685         if (vaddr == 0) {
 686                 if (netif_msg_ifup(priv))
 687                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 688                                         dev->name);
 689                 return -ENOMEM;
 690         }
 691
 692         priv->tx_bd_base = (struct txbd8 *) vaddr;
 693
 694         /* enet DMA only understands physical addresses */
 695         gfar_write(&regs->tbase0, addr);
 696
 697         /* Start the rx descriptor ring where the tx ring leaves off */
 698         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 699         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 700         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 701         gfar_write(&regs->rbase0, addr);
 702
 703         /* Setup the skbuff rings */
 704         priv->tx_skbuff =
 705             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 706                                         priv->tx_ring_size, GFP_KERNEL);
 707
 708         if (NULL == priv->tx_skbuff) {
 709                 if (netif_msg_ifup(priv))
 710                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 711                                         dev->name);
 712                 err = -ENOMEM;
 713                 goto tx_skb_fail;
 714         }
 715
 716         for (i = 0; i < priv->tx_ring_size; i++)
 717                 priv->tx_skbuff[i] = NULL;
 718
 719         priv->rx_skbuff =
 720             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 721                                         priv->rx_ring_size, GFP_KERNEL);
 722
 723         if (NULL == priv->rx_skbuff) {
 724                 if (netif_msg_ifup(priv))
 725                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 726                                         dev->name);
 727                 err = -ENOMEM;
 728                 goto rx_skb_fail;
 729         }
 730
 731         for (i = 0; i < priv->rx_ring_size; i++)
 732                 priv->rx_skbuff[i] = NULL;
 733
 734         /* Initialize some variables in our dev structure */
 735         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 736         priv->cur_rx = priv->rx_bd_base;
 737         priv->skb_curtx = priv->skb_dirtytx = 0;
 738         priv->skb_currx = 0;
 739
 740         /* Initialize Transmit Descriptor Ring */
 741         txbdp = priv->tx_bd_base;
 742         for (i = 0; i < priv->tx_ring_size; i++) {
 743                 txbdp->status = 0;
 744                 txbdp->length = 0;
 745                 txbdp->bufPtr = 0;
 746                 txbdp++;
 747         }
 748
 749         /* Set the last descriptor in the ring to indicate wrap */
 750         txbdp--;
 751         txbdp->status |= TXBD_WRAP;
 752
 753         rxbdp = priv->rx_bd_base;
 754         for (i = 0; i < priv->rx_ring_size; i++) {
 755                 struct sk_buff *skb = NULL;
 756
 757                 rxbdp->status = 0;
 758
 759                 skb = gfar_new_skb(dev, rxbdp);
 760
 761                 priv->rx_skbuff[i] = skb;
 762
 763                 rxbdp++;
 764         }
 765
 766         /* Set the last descriptor in the ring to wrap */
 767         rxbdp--;
 768         rxbdp->status |= RXBD_WRAP;
 769
 770         /* If the device has multiple interrupts, register for
 771          * them.  Otherwise, only register for the one */
 772         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 773                 /* Install our interrupt handlers for Error,
 774                  * Transmit, and Receive */
 775                 if (request_irq(priv->interruptError, gfar_error,
 776                                 0, "enet_error", dev) < 0) {
 777                         if (netif_msg_intr(priv))
 778                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 779                                         dev->name, priv->interruptError);
 780
 781                         err = -1;
 782                         goto err_irq_fail;
 783                 }
 784
 785                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 786                                 0, "enet_tx", dev) < 0) {
 787                         if (netif_msg_intr(priv))
 788                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 789                                         dev->name, priv->interruptTransmit);
 790
 791                         err = -1;
 792
 793                         goto tx_irq_fail;
 794                 }
 795
 796                 if (request_irq(priv->interruptReceive, gfar_receive,
 797                                 0, "enet_rx", dev) < 0) {
 798                         if (netif_msg_intr(priv))
 799                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 800                                                 dev->name, priv->interruptReceive);
 801
 802                         err = -1;
 803                         goto rx_irq_fail;
 804                 }
 805         } else {
 806                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 807                                 0, "gfar_interrupt", dev) < 0) {
 808                         if (netif_msg_intr(priv))
 809                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 810                                         dev->name, priv->interruptError);
 811
 812                         err = -1;
 813                         goto err_irq_fail;
 814                 }
 815         }
 816
 817         phy_start(priv->phydev);
 818
 819         /* Configure the coalescing support */
 820         if (priv->txcoalescing)
 821                 gfar_write(&regs->txic,
 822                            mk_ic_value(priv->txcount, priv->txtime));
 823         else
 824                 gfar_write(&regs->txic, 0);
 825
 826         if (priv->rxcoalescing)
 827                 gfar_write(&regs->rxic,
 828                            mk_ic_value(priv->rxcount, priv->rxtime));
 829         else
 830                 gfar_write(&regs->rxic, 0);
 831
 832         if (priv->rx_csum_enable)
 833                 rctrl |= RCTRL_CHECKSUMMING;
 834
 835         if (priv->extended_hash) {
 836                 rctrl |= RCTRL_EXTHASH;
 837
 838                 gfar_clear_exact_match(dev);
 839                 rctrl |= RCTRL_EMEN;
 840         }
 841
 842         if (priv->vlan_enable)
 843                 rctrl |= RCTRL_VLAN;
 844
 845         if (priv->padding) {
 846                 rctrl &= ~RCTRL_PAL_MASK;
 847                 rctrl |= RCTRL_PADDING(priv->padding);
 848         }
 849
 850         /* Init rctrl based on our settings */
 851         gfar_write(&priv->regs->rctrl, rctrl);
 852
 853         if (dev->features & NETIF_F_IP_CSUM)
 854                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 855
 856         /* Set the extraction length and index */
 857         attrs = ATTRELI_EL(priv->rx_stash_size) |
 858                 ATTRELI_EI(priv->rx_stash_index);
 859
 860         gfar_write(&priv->regs->attreli, attrs);
 861
 862         /* Start with defaults, and add stashing or locking
 863          * depending on the approprate variables */
 864         attrs = ATTR_INIT_SETTINGS;
 865
 866         if (priv->bd_stash_en)
 867                 attrs |= ATTR_BDSTASH;
 868
 869         if (priv->rx_stash_size != 0)
 870                 attrs |= ATTR_BUFSTASH;
 871
 872         gfar_write(&priv->regs->attr, attrs);
 873
 874         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
 875         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
 876         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 877
 878         /* Start the controller */
 879         gfar_start(dev);
 880
 881         return 0;
 882
 883 rx_irq_fail:
 884         free_irq(priv->interruptTransmit, dev);
 885 tx_irq_fail:
 886         free_irq(priv->interruptError, dev);
 887 err_irq_fail:
 888 rx_skb_fail:
 889         free_skb_resources(priv);
 890 tx_skb_fail:
 891         dma_free_coherent(NULL,
 892                         sizeof(struct txbd8)*priv->tx_ring_size
 893                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 894                         priv->tx_bd_base,
 895                         gfar_read(&regs->tbase0));
 896
 897         return err;
 898 }
 899
 900 /* Called when something needs to use the ethernet device */
 901 /* Returns 0 for success. */
 902 static int gfar_enet_open(struct net_device *dev)
 903 {
 904         int err;
 905
 906         /* Initialize a bunch of registers */
 907         init_registers(dev);
 908
 909         gfar_set_mac_address(dev);
 910
 911         err = init_phy(dev);
 912
 913         if(err)
 914                 return err;
 915
 916         err = startup_gfar(dev);
 917
 918         netif_start_queue(dev);
 919
 920         return err;
 921 }
 922
 923 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
 924 {
 925         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
 926
 927         memset(fcb, 0, GMAC_FCB_LEN);
 928
 929         return fcb;
 930 }
 931
 932 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 933 {
 934         u8 flags = 0;
 935
 936         /* If we're here, it's a IP packet with a TCP or UDP
 937          * payload.  We set it to checksum, using a pseudo-header
 938          * we provide
 939          */
 940         flags = TXFCB_DEFAULT;
 941
 942         /* Tell the controller what the protocol is */
 943         /* And provide the already calculated phcs */
 944         if (skb->nh.iph->protocol == IPPROTO_UDP) {
 945                 flags |= TXFCB_UDP;
 946                 fcb->phcs = skb->h.uh->check;
 947         } else
 948                 fcb->phcs = skb->h.th->check;
 949
 950         /* l3os is the distance between the start of the
 951          * frame (skb->data) and the start of the IP hdr.
 952          * l4os is the distance between the start of the
 953          * l3 hdr and the l4 hdr */
 954         fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
 955         fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
 956
 957         fcb->flags = flags;
 958 }
 959
 960 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
 961 {
 962         fcb->flags |= TXFCB_VLN;
 963         fcb->vlctl = vlan_tx_tag_get(skb);
 964 }
 965
 966 /* This is called by the kernel when a frame is ready for transmission. */
 967 /* It is pointed to by the dev->hard_start_xmit function pointer */
 968 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
 969 {
 970         struct gfar_private *priv = netdev_priv(dev);
 971         struct txfcb *fcb = NULL;
 972         struct txbd8 *txbdp;
 973         u16 status;
 974         unsigned long flags;
 975
 976         /* Update transmit stats */
 977         priv->stats.tx_bytes += skb->len;
 978
 979         /* Lock priv now */
 980         spin_lock_irqsave(&priv->txlock, flags);
 981
 982         /* Point at the first free tx descriptor */
 983         txbdp = priv->cur_tx;
 984
 985         /* Clear all but the WRAP status flags */
 986         status = txbdp->status & TXBD_WRAP;
 987
 988         /* Set up checksumming */
 989         if (likely((dev->features & NETIF_F_IP_CSUM)
 990                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
 991                 fcb = gfar_add_fcb(skb, txbdp);
 992                 status |= TXBD_TOE;
 993                 gfar_tx_checksum(skb, fcb);
 994         }
 995
 996         if (priv->vlan_enable &&
 997                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
 998                 if (unlikely(NULL == fcb)) {
 999                         fcb = gfar_add_fcb(skb, txbdp);
1000                         status |= TXBD_TOE;
1001                 }
1002
1003                 gfar_tx_vlan(skb, fcb);
1004         }
1005
1006         /* Set buffer length and pointer */
1007         txbdp->length = skb->len;
1008         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1009                         skb->len, DMA_TO_DEVICE);
1010
1011         /* Save the skb pointer so we can free it later */
1012         priv->tx_skbuff[priv->skb_curtx] = skb;
1013
1014         /* Update the current skb pointer (wrapping if this was the last) */
1015         priv->skb_curtx =
1016             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1017
1018         /* Flag the BD as interrupt-causing */
1019         status |= TXBD_INTERRUPT;
1020
1021         /* Flag the BD as ready to go, last in frame, and  */
1022         /* in need of CRC */
1023         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1024
1025         dev->trans_start = jiffies;
1026
1027         txbdp->status = status;
1028
1029         /* If this was the last BD in the ring, the next one */
1030         /* is at the beginning of the ring */
1031         if (txbdp->status & TXBD_WRAP)
1032                 txbdp = priv->tx_bd_base;
1033         else
1034                 txbdp++;
1035
1036         /* If the next BD still needs to be cleaned up, then the bds
1037            are full.  We need to tell the kernel to stop sending us stuff. */
1038         if (txbdp == priv->dirty_tx) {
1039                 netif_stop_queue(dev);
1040
1041                 priv->stats.tx_fifo_errors++;
1042         }
1043
1044         /* Update the current txbd to the next one */
1045         priv->cur_tx = txbdp;
1046
1047         /* Tell the DMA to go go go */
1048         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1049
1050         /* Unlock priv */
1051         spin_unlock_irqrestore(&priv->txlock, flags);
1052
1053         return 0;
1054 }
1055
1056 /* Stops the kernel queue, and halts the controller */
1057 static int gfar_close(struct net_device *dev)
1058 {
1059         struct gfar_private *priv = netdev_priv(dev);
1060         stop_gfar(dev);
1061
1062         /* Disconnect from the PHY */
1063         phy_disconnect(priv->phydev);
1064         priv->phydev = NULL;
1065
1066         netif_stop_queue(dev);
1067
1068         return 0;
1069 }
1070
1071 /* returns a net_device_stats structure pointer */
1072 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1073 {
1074         struct gfar_private *priv = netdev_priv(dev);
1075
1076         return &(priv->stats);
1077 }
1078
1079 /* Changes the mac address if the controller is not running. */
1080 int gfar_set_mac_address(struct net_device *dev)
1081 {
1082         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1083
1084         return 0;
1085 }
1086
1087
1088 /* Enables and disables VLAN insertion/extraction */
1089 static void gfar_vlan_rx_register(struct net_device *dev,
1090                 struct vlan_group *grp)
1091 {
1092         struct gfar_private *priv = netdev_priv(dev);
1093         unsigned long flags;
1094         u32 tempval;
1095
1096         spin_lock_irqsave(&priv->rxlock, flags);
1097
1098         priv->vlgrp = grp;
1099
1100         if (grp) {
1101                 /* Enable VLAN tag insertion */
1102                 tempval = gfar_read(&priv->regs->tctrl);
1103                 tempval |= TCTRL_VLINS;
1104
1105                 gfar_write(&priv->regs->tctrl, tempval);
1106
1107                 /* Enable VLAN tag extraction */
1108                 tempval = gfar_read(&priv->regs->rctrl);
1109                 tempval |= RCTRL_VLEX;
1110                 gfar_write(&priv->regs->rctrl, tempval);
1111         } else {
1112                 /* Disable VLAN tag insertion */
1113                 tempval = gfar_read(&priv->regs->tctrl);
1114                 tempval &= ~TCTRL_VLINS;
1115                 gfar_write(&priv->regs->tctrl, tempval);
1116
1117                 /* Disable VLAN tag extraction */
1118                 tempval = gfar_read(&priv->regs->rctrl);
1119                 tempval &= ~RCTRL_VLEX;
1120                 gfar_write(&priv->regs->rctrl, tempval);
1121         }
1122
1123         spin_unlock_irqrestore(&priv->rxlock, flags);
1124 }
1125
1126
1127 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1128 {
1129         struct gfar_private *priv = netdev_priv(dev);
1130         unsigned long flags;
1131
1132         spin_lock_irqsave(&priv->rxlock, flags);
1133
1134         if (priv->vlgrp)
1135                 priv->vlgrp->vlan_devices[vid] = NULL;
1136
1137         spin_unlock_irqrestore(&priv->rxlock, flags);
1138 }
1139
1140
1141 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1142 {
1143         int tempsize, tempval;
1144         struct gfar_private *priv = netdev_priv(dev);
1145         int oldsize = priv->rx_buffer_size;
1146         int frame_size = new_mtu + ETH_HLEN;
1147
1148         if (priv->vlan_enable)
1149                 frame_size += VLAN_ETH_HLEN;
1150
1151         if (gfar_uses_fcb(priv))
1152                 frame_size += GMAC_FCB_LEN;
1153
1154         frame_size += priv->padding;
1155
1156         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1157                 if (netif_msg_drv(priv))
1158                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1159                                         dev->name);
1160                 return -EINVAL;
1161         }
1162
1163         tempsize =
1164             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1165             INCREMENTAL_BUFFER_SIZE;
1166
1167         /* Only stop and start the controller if it isn't already
1168          * stopped, and we changed something */
1169         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1170                 stop_gfar(dev);
1171
1172         priv->rx_buffer_size = tempsize;
1173
1174         dev->mtu = new_mtu;
1175
1176         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1177         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1178
1179         /* If the mtu is larger than the max size for standard
1180          * ethernet frames (ie, a jumbo frame), then set maccfg2
1181          * to allow huge frames, and to check the length */
1182         tempval = gfar_read(&priv->regs->maccfg2);
1183
1184         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1185                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1186         else
1187                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1188
1189         gfar_write(&priv->regs->maccfg2, tempval);
1190
1191         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1192                 startup_gfar(dev);
1193
1194         return 0;
1195 }
1196
1197 /* gfar_timeout gets called when a packet has not been
1198  * transmitted after a set amount of time.
1199  * For now, assume that clearing out all the structures, and
1200  * starting over will fix the problem. */
1201 static void gfar_timeout(struct net_device *dev)
1202 {
1203         struct gfar_private *priv = netdev_priv(dev);
1204
1205         priv->stats.tx_errors++;
1206
1207         if (dev->flags & IFF_UP) {
1208                 stop_gfar(dev);
1209                 startup_gfar(dev);
1210         }
1211
1212         netif_schedule(dev);
1213 }
1214
1215 /* Interrupt Handler for Transmit complete */
1216 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1217 {
1218         struct net_device *dev = (struct net_device *) dev_id;
1219         struct gfar_private *priv = netdev_priv(dev);
1220         struct txbd8 *bdp;
1221
1222         /* Clear IEVENT */
1223         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1224
1225         /* Lock priv */
1226         spin_lock(&priv->txlock);
1227         bdp = priv->dirty_tx;
1228         while ((bdp->status & TXBD_READY) == 0) {
1229                 /* If dirty_tx and cur_tx are the same, then either the */
1230                 /* ring is empty or full now (it could only be full in the beginning, */
1231                 /* obviously).  If it is empty, we are done. */
1232                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1233                         break;
1234
1235                 priv->stats.tx_packets++;
1236
1237                 /* Deferred means some collisions occurred during transmit, */
1238                 /* but we eventually sent the packet. */
1239                 if (bdp->status & TXBD_DEF)
1240                         priv->stats.collisions++;
1241
1242                 /* Free the sk buffer associated with this TxBD */
1243                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1244                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1245                 priv->skb_dirtytx =
1246                     (priv->skb_dirtytx +
1247                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1248
1249                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1250                 if (bdp->status & TXBD_WRAP)
1251                         bdp = priv->tx_bd_base;
1252                 else
1253                         bdp++;
1254
1255                 /* Move dirty_tx to be the next bd */
1256                 priv->dirty_tx = bdp;
1257
1258                 /* We freed a buffer, so now we can restart transmission */
1259                 if (netif_queue_stopped(dev))
1260                         netif_wake_queue(dev);
1261         } /* while ((bdp->status & TXBD_READY) == 0) */
1262
1263         /* If we are coalescing the interrupts, reset the timer */
1264         /* Otherwise, clear it */
1265         if (priv->txcoalescing)
1266                 gfar_write(&priv->regs->txic,
1267                            mk_ic_value(priv->txcount, priv->txtime));
1268         else
1269                 gfar_write(&priv->regs->txic, 0);
1270
1271         spin_unlock(&priv->txlock);
1272
1273         return IRQ_HANDLED;
1274 }
1275
1276 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1277 {
1278         unsigned int alignamount;
1279         struct gfar_private *priv = netdev_priv(dev);
1280         struct sk_buff *skb = NULL;
1281         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1282
1283         /* We have to allocate the skb, so keep trying till we succeed */
1284         while ((!skb) && timeout--)
1285                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1286
1287         if (NULL == skb)
1288                 return NULL;
1289
1290         alignamount = RXBUF_ALIGNMENT -
1291                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1292
1293         /* We need the data buffer to be aligned properly.  We will reserve
1294          * as many bytes as needed to align the data properly
1295          */
1296         skb_reserve(skb, alignamount);
1297
1298         skb->dev = dev;
1299
1300         bdp->bufPtr = dma_map_single(NULL, skb->data,
1301                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1302
1303         bdp->length = 0;
1304
1305         /* Mark the buffer empty */
1306         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1307
1308         return skb;
1309 }
1310
1311 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1312 {
1313         struct net_device_stats *stats = &priv->stats;
1314         struct gfar_extra_stats *estats = &priv->extra_stats;
1315
1316         /* If the packet was truncated, none of the other errors
1317          * matter */
1318         if (status & RXBD_TRUNCATED) {
1319                 stats->rx_length_errors++;
1320
1321                 estats->rx_trunc++;
1322
1323                 return;
1324         }
1325         /* Count the errors, if there were any */
1326         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1327                 stats->rx_length_errors++;
1328
1329                 if (status & RXBD_LARGE)
1330                         estats->rx_large++;
1331                 else
1332                         estats->rx_short++;
1333         }
1334         if (status & RXBD_NONOCTET) {
1335                 stats->rx_frame_errors++;
1336                 estats->rx_nonoctet++;
1337         }
1338         if (status & RXBD_CRCERR) {
1339                 estats->rx_crcerr++;
1340                 stats->rx_crc_errors++;
1341         }
1342         if (status & RXBD_OVERRUN) {
1343                 estats->rx_overrun++;
1344                 stats->rx_crc_errors++;
1345         }
1346 }
1347
1348 irqreturn_t gfar_receive(int irq, void *dev_id)
1349 {
1350         struct net_device *dev = (struct net_device *) dev_id;
1351         struct gfar_private *priv = netdev_priv(dev);
1352 #ifdef CONFIG_GFAR_NAPI
1353         u32 tempval;
1354 #else
1355         unsigned long flags;
1356 #endif
1357
1358         /* Clear IEVENT, so rx interrupt isn't called again
1359          * because of this interrupt */
1360         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1361
1362         /* support NAPI */
1363 #ifdef CONFIG_GFAR_NAPI
1364         if (netif_rx_schedule_prep(dev)) {
1365                 tempval = gfar_read(&priv->regs->imask);
1366                 tempval &= IMASK_RX_DISABLED;
1367                 gfar_write(&priv->regs->imask, tempval);
1368
1369                 __netif_rx_schedule(dev);
1370         } else {
1371                 if (netif_msg_rx_err(priv))
1372                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1373                                 dev->name, gfar_read(&priv->regs->ievent),
1374                                 gfar_read(&priv->regs->imask));
1375         }
1376 #else
1377
1378         spin_lock_irqsave(&priv->rxlock, flags);
1379         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1380
1381         /* If we are coalescing interrupts, update the timer */
1382         /* Otherwise, clear it */
1383         if (priv->rxcoalescing)
1384                 gfar_write(&priv->regs->rxic,
1385                            mk_ic_value(priv->rxcount, priv->rxtime));
1386         else
1387                 gfar_write(&priv->regs->rxic, 0);
1388
1389         spin_unlock_irqrestore(&priv->rxlock, flags);
1390 #endif
1391
1392         return IRQ_HANDLED;
1393 }
1394
1395 static inline int gfar_rx_vlan(struct sk_buff *skb,
1396                 struct vlan_group *vlgrp, unsigned short vlctl)
1397 {
1398 #ifdef CONFIG_GFAR_NAPI
1399         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1400 #else
1401         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1402 #endif
1403 }
1404
1405 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1406 {
1407         /* If valid headers were found, and valid sums
1408          * were verified, then we tell the kernel that no
1409          * checksumming is necessary.  Otherwise, it is */
1410         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1411                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1412         else
1413                 skb->ip_summed = CHECKSUM_NONE;
1414 }
1415
1416
1417 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1418 {
1419         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1420
1421         /* Remove the FCB from the skb */
1422         skb_pull(skb, GMAC_FCB_LEN);
1423
1424         return fcb;
1425 }
1426
1427 /* gfar_process_frame() -- handle one incoming packet if skb
1428  * isn't NULL.  */
1429 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1430                 int length)
1431 {
1432         struct gfar_private *priv = netdev_priv(dev);
1433         struct rxfcb *fcb = NULL;
1434
1435         if (NULL == skb) {
1436                 if (netif_msg_rx_err(priv))
1437                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1438                 priv->stats.rx_dropped++;
1439                 priv->extra_stats.rx_skbmissing++;
1440         } else {
1441                 int ret;
1442
1443                 /* Prep the skb for the packet */
1444                 skb_put(skb, length);
1445
1446                 /* Grab the FCB if there is one */
1447                 if (gfar_uses_fcb(priv))
1448                         fcb = gfar_get_fcb(skb);
1449
1450                 /* Remove the padded bytes, if there are any */
1451                 if (priv->padding)
1452                         skb_pull(skb, priv->padding);
1453
1454                 if (priv->rx_csum_enable)
1455                         gfar_rx_checksum(skb, fcb);
1456
1457                 /* Tell the skb what kind of packet this is */
1458                 skb->protocol = eth_type_trans(skb, dev);
1459
1460                 /* Send the packet up the stack */
1461                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1462                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1463                 else
1464                         ret = RECEIVE(skb);
1465
1466                 if (NET_RX_DROP == ret)
1467                         priv->extra_stats.kernel_dropped++;
1468         }
1469
1470         return 0;
1471 }
1472
1473 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1474  *   until the budget/quota has been reached. Returns the number
1475  *   of frames handled
1476  */
1477 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1478 {
1479         struct rxbd8 *bdp;
1480         struct sk_buff *skb;
1481         u16 pkt_len;
1482         int howmany = 0;
1483         struct gfar_private *priv = netdev_priv(dev);
1484
1485         /* Get the first full descriptor */
1486         bdp = priv->cur_rx;
1487
1488         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1489                 skb = priv->rx_skbuff[priv->skb_currx];
1490
1491                 if (!(bdp->status &
1492                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1493                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1494                         /* Increment the number of packets */
1495                         priv->stats.rx_packets++;
1496                         howmany++;
1497
1498                         /* Remove the FCS from the packet length */
1499                         pkt_len = bdp->length - 4;
1500
1501                         gfar_process_frame(dev, skb, pkt_len);
1502
1503                         priv->stats.rx_bytes += pkt_len;
1504                 } else {
1505                         count_errors(bdp->status, priv);
1506
1507                         if (skb)
1508                                 dev_kfree_skb_any(skb);
1509
1510                         priv->rx_skbuff[priv->skb_currx] = NULL;
1511                 }
1512
1513                 dev->last_rx = jiffies;
1514
1515                 /* Clear the status flags for this buffer */
1516                 bdp->status &= ~RXBD_STATS;
1517
1518                 /* Add another skb for the future */
1519                 skb = gfar_new_skb(dev, bdp);
1520                 priv->rx_skbuff[priv->skb_currx] = skb;
1521
1522                 /* Update to the next pointer */
1523                 if (bdp->status & RXBD_WRAP)
1524                         bdp = priv->rx_bd_base;
1525                 else
1526                         bdp++;
1527
1528                 /* update to point at the next skb */
1529                 priv->skb_currx =
1530                     (priv->skb_currx +
1531                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1532
1533         }
1534
1535         /* Update the current rxbd pointer to be the next one */
1536         priv->cur_rx = bdp;
1537
1538         return howmany;
1539 }
1540
1541 #ifdef CONFIG_GFAR_NAPI
1542 static int gfar_poll(struct net_device *dev, int *budget)
1543 {
1544         int howmany;
1545         struct gfar_private *priv = netdev_priv(dev);
1546         int rx_work_limit = *budget;
1547
1548         if (rx_work_limit > dev->quota)
1549                 rx_work_limit = dev->quota;
1550
1551         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1552
1553         dev->quota -= howmany;
1554         rx_work_limit -= howmany;
1555         *budget -= howmany;
1556
1557         if (rx_work_limit > 0) {
1558                 netif_rx_complete(dev);
1559
1560                 /* Clear the halt bit in RSTAT */
1561                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1562
1563                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1564
1565                 /* If we are coalescing interrupts, update the timer */
1566                 /* Otherwise, clear it */
1567                 if (priv->rxcoalescing)
1568                         gfar_write(&priv->regs->rxic,
1569                                    mk_ic_value(priv->rxcount, priv->rxtime));
1570                 else
1571                         gfar_write(&priv->regs->rxic, 0);
1572         }
1573
1574         /* Return 1 if there's more work to do */
1575         return (rx_work_limit > 0) ? 0 : 1;
1576 }
1577 #endif
1578
1579 #ifdef CONFIG_NET_POLL_CONTROLLER
1580 /*
1581  * Polling 'interrupt' - used by things like netconsole to send skbs
1582  * without having to re-enable interrupts. It's not called while
1583  * the interrupt routine is executing.
1584  */
1585 static void gfar_netpoll(struct net_device *dev)
1586 {
1587         struct gfar_private *priv = netdev_priv(dev);
1588
1589         /* If the device has multiple interrupts, run tx/rx */
1590         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1591                 disable_irq(priv->interruptTransmit);
1592                 disable_irq(priv->interruptReceive);
1593                 disable_irq(priv->interruptError);
1594                 gfar_interrupt(priv->interruptTransmit, dev);
1595                 enable_irq(priv->interruptError);
1596                 enable_irq(priv->interruptReceive);
1597                 enable_irq(priv->interruptTransmit);
1598         } else {
1599                 disable_irq(priv->interruptTransmit);
1600                 gfar_interrupt(priv->interruptTransmit, dev);
1601                 enable_irq(priv->interruptTransmit);
1602         }
1603 }
1604 #endif
1605
1606 /* The interrupt handler for devices with one interrupt */
1607 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1608 {
1609         struct net_device *dev = dev_id;
1610         struct gfar_private *priv = netdev_priv(dev);
1611
1612         /* Save ievent for future reference */
1613         u32 events = gfar_read(&priv->regs->ievent);
1614
1615         /* Clear IEVENT */
1616         gfar_write(&priv->regs->ievent, events);
1617
1618         /* Check for reception */
1619         if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1620                 gfar_receive(irq, dev_id);
1621
1622         /* Check for transmit completion */
1623         if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1624                 gfar_transmit(irq, dev_id);
1625
1626         /* Update error statistics */
1627         if (events & IEVENT_TXE) {
1628                 priv->stats.tx_errors++;
1629
1630                 if (events & IEVENT_LC)
1631                         priv->stats.tx_window_errors++;
1632                 if (events & IEVENT_CRL)
1633                         priv->stats.tx_aborted_errors++;
1634                 if (events & IEVENT_XFUN) {
1635                         if (netif_msg_tx_err(priv))
1636                                 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1637                         priv->stats.tx_dropped++;
1638                         priv->extra_stats.tx_underrun++;
1639
1640                         /* Reactivate the Tx Queues */
1641                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1642                 }
1643         }
1644         if (events & IEVENT_BSY) {
1645                 priv->stats.rx_errors++;
1646                 priv->extra_stats.rx_bsy++;
1647
1648                 gfar_receive(irq, dev_id);
1649
1650 #ifndef CONFIG_GFAR_NAPI
1651                 /* Clear the halt bit in RSTAT */
1652                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1653 #endif
1654
1655                 if (netif_msg_rx_err(priv))
1656                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1657                                         dev->name,
1658                                         gfar_read(&priv->regs->rstat));
1659         }
1660         if (events & IEVENT_BABR) {
1661                 priv->stats.rx_errors++;
1662                 priv->extra_stats.rx_babr++;
1663
1664                 if (netif_msg_rx_err(priv))
1665                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1666         }
1667         if (events & IEVENT_EBERR) {
1668                 priv->extra_stats.eberr++;
1669                 if (netif_msg_rx_err(priv))
1670                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1671         }
1672         if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1673                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1674
1675         if (events & IEVENT_BABT) {
1676                 priv->extra_stats.tx_babt++;
1677                 if (netif_msg_rx_err(priv))
1678                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1679         }
1680
1681         return IRQ_HANDLED;
1682 }
1683
1684 /* Called every time the controller might need to be made
1685  * aware of new link state.  The PHY code conveys this
1686  * information through variables in the phydev structure, and this
1687  * function converts those variables into the appropriate
1688  * register values, and can bring down the device if needed.
1689  */
1690 static void adjust_link(struct net_device *dev)
1691 {
1692         struct gfar_private *priv = netdev_priv(dev);
1693         struct gfar __iomem *regs = priv->regs;
1694         unsigned long flags;
1695         struct phy_device *phydev = priv->phydev;
1696         int new_state = 0;
1697
1698         spin_lock_irqsave(&priv->txlock, flags);
1699         if (phydev->link) {
1700                 u32 tempval = gfar_read(&regs->maccfg2);
1701                 u32 ecntrl = gfar_read(&regs->ecntrl);
1702
1703                 /* Now we make sure that we can be in full duplex mode.
1704                  * If not, we operate in half-duplex mode. */
1705                 if (phydev->duplex != priv->oldduplex) {
1706                         new_state = 1;
1707                         if (!(phydev->duplex))
1708                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1709                         else
1710                                 tempval |= MACCFG2_FULL_DUPLEX;
1711
1712                         priv->oldduplex = phydev->duplex;
1713                 }
1714
1715                 if (phydev->speed != priv->oldspeed) {
1716                         new_state = 1;
1717                         switch (phydev->speed) {
1718                         case 1000:
1719                                 tempval =
1720                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1721                                 break;
1722                         case 100:
1723                         case 10:
1724                                 tempval =
1725                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1726
1727                                 /* Reduced mode distinguishes
1728                                  * between 10 and 100 */
1729                                 if (phydev->speed == SPEED_100)
1730                                         ecntrl |= ECNTRL_R100;
1731                                 else
1732                                         ecntrl &= ~(ECNTRL_R100);
1733                                 break;
1734                         default:
1735                                 if (netif_msg_link(priv))
1736                                         printk(KERN_WARNING
1737                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1738                                                 dev->name, phydev->speed);
1739                                 break;
1740                         }
1741
1742                         priv->oldspeed = phydev->speed;
1743                 }
1744
1745                 gfar_write(&regs->maccfg2, tempval);
1746                 gfar_write(&regs->ecntrl, ecntrl);
1747
1748                 if (!priv->oldlink) {
1749                         new_state = 1;
1750                         priv->oldlink = 1;
1751                         netif_schedule(dev);
1752                 }
1753         } else if (priv->oldlink) {
1754                 new_state = 1;
1755                 priv->oldlink = 0;
1756                 priv->oldspeed = 0;
1757                 priv->oldduplex = -1;
1758         }
1759
1760         if (new_state && netif_msg_link(priv))
1761                 phy_print_status(phydev);
1762
1763         spin_unlock_irqrestore(&priv->txlock, flags);
1764 }
1765
1766 /* Update the hash table based on the current list of multicast
1767  * addresses we subscribe to.  Also, change the promiscuity of
1768  * the device based on the flags (this function is called
1769  * whenever dev->flags is changed */
1770 static void gfar_set_multi(struct net_device *dev)
1771 {
1772         struct dev_mc_list *mc_ptr;
1773         struct gfar_private *priv = netdev_priv(dev);
1774         struct gfar __iomem *regs = priv->regs;
1775         u32 tempval;
1776
1777         if(dev->flags & IFF_PROMISC) {
1778                 /* Set RCTRL to PROM */
1779                 tempval = gfar_read(&regs->rctrl);
1780                 tempval |= RCTRL_PROM;
1781                 gfar_write(&regs->rctrl, tempval);
1782         } else {
1783                 /* Set RCTRL to not PROM */
1784                 tempval = gfar_read(&regs->rctrl);
1785                 tempval &= ~(RCTRL_PROM);
1786                 gfar_write(&regs->rctrl, tempval);
1787         }
1788
1789         if(dev->flags & IFF_ALLMULTI) {
1790                 /* Set the hash to rx all multicast frames */
1791                 gfar_write(&regs->igaddr0, 0xffffffff);
1792                 gfar_write(&regs->igaddr1, 0xffffffff);
1793                 gfar_write(&regs->igaddr2, 0xffffffff);
1794                 gfar_write(&regs->igaddr3, 0xffffffff);
1795                 gfar_write(&regs->igaddr4, 0xffffffff);
1796                 gfar_write(&regs->igaddr5, 0xffffffff);
1797                 gfar_write(&regs->igaddr6, 0xffffffff);
1798                 gfar_write(&regs->igaddr7, 0xffffffff);
1799                 gfar_write(&regs->gaddr0, 0xffffffff);
1800                 gfar_write(&regs->gaddr1, 0xffffffff);
1801                 gfar_write(&regs->gaddr2, 0xffffffff);
1802                 gfar_write(&regs->gaddr3, 0xffffffff);
1803                 gfar_write(&regs->gaddr4, 0xffffffff);
1804                 gfar_write(&regs->gaddr5, 0xffffffff);
1805                 gfar_write(&regs->gaddr6, 0xffffffff);
1806                 gfar_write(&regs->gaddr7, 0xffffffff);
1807         } else {
1808                 int em_num;
1809                 int idx;
1810
1811                 /* zero out the hash */
1812                 gfar_write(&regs->igaddr0, 0x0);
1813                 gfar_write(&regs->igaddr1, 0x0);
1814                 gfar_write(&regs->igaddr2, 0x0);
1815                 gfar_write(&regs->igaddr3, 0x0);
1816                 gfar_write(&regs->igaddr4, 0x0);
1817                 gfar_write(&regs->igaddr5, 0x0);
1818                 gfar_write(&regs->igaddr6, 0x0);
1819                 gfar_write(&regs->igaddr7, 0x0);
1820                 gfar_write(&regs->gaddr0, 0x0);
1821                 gfar_write(&regs->gaddr1, 0x0);
1822                 gfar_write(&regs->gaddr2, 0x0);
1823                 gfar_write(&regs->gaddr3, 0x0);
1824                 gfar_write(&regs->gaddr4, 0x0);
1825                 gfar_write(&regs->gaddr5, 0x0);
1826                 gfar_write(&regs->gaddr6, 0x0);
1827                 gfar_write(&regs->gaddr7, 0x0);
1828
1829                 /* If we have extended hash tables, we need to
1830                  * clear the exact match registers to prepare for
1831                  * setting them */
1832                 if (priv->extended_hash) {
1833                         em_num = GFAR_EM_NUM + 1;
1834                         gfar_clear_exact_match(dev);
1835                         idx = 1;
1836                 } else {
1837                         idx = 0;
1838                         em_num = 0;
1839                 }
1840
1841                 if(dev->mc_count == 0)
1842                         return;
1843
1844                 /* Parse the list, and set the appropriate bits */
1845                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1846                         if (idx < em_num) {
1847                                 gfar_set_mac_for_addr(dev, idx,
1848                                                 mc_ptr->dmi_addr);
1849                                 idx++;
1850                         } else
1851                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1852                 }
1853         }
1854
1855         return;
1856 }
1857
1858
1859 /* Clears each of the exact match registers to zero, so they
1860  * don't interfere with normal reception */
1861 static void gfar_clear_exact_match(struct net_device *dev)
1862 {
1863         int idx;
1864         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1865
1866         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1867                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1868 }
1869
1870 /* Set the appropriate hash bit for the given addr */
1871 /* The algorithm works like so:
1872  * 1) Take the Destination Address (ie the multicast address), and
1873  * do a CRC on it (little endian), and reverse the bits of the
1874  * result.
1875  * 2) Use the 8 most significant bits as a hash into a 256-entry
1876  * table.  The table is controlled through 8 32-bit registers:
1877  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1878  * gaddr7.  This means that the 3 most significant bits in the
1879  * hash index which gaddr register to use, and the 5 other bits
1880  * indicate which bit (assuming an IBM numbering scheme, which
1881  * for PowerPC (tm) is usually the case) in the register holds
1882  * the entry. */
1883 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1884 {
1885         u32 tempval;
1886         struct gfar_private *priv = netdev_priv(dev);
1887         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1888         int width = priv->hash_width;
1889         u8 whichbit = (result >> (32 - width)) & 0x1f;
1890         u8 whichreg = result >> (32 - width + 5);
1891         u32 value = (1 << (31-whichbit));
1892
1893         tempval = gfar_read(priv->hash_regs[whichreg]);
1894         tempval |= value;
1895         gfar_write(priv->hash_regs[whichreg], tempval);
1896
1897         return;
1898 }
1899
1900
1901 /* There are multiple MAC Address register pairs on some controllers
1902  * This function sets the numth pair to a given address
1903  */
1904 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1905 {
1906         struct gfar_private *priv = netdev_priv(dev);
1907         int idx;
1908         char tmpbuf[MAC_ADDR_LEN];
1909         u32 tempval;
1910         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1911
1912         macptr += num*2;
1913
1914         /* Now copy it into the mac registers backwards, cuz */
1915         /* little endian is silly */
1916         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1917                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1918
1919         gfar_write(macptr, *((u32 *) (tmpbuf)));
1920
1921         tempval = *((u32 *) (tmpbuf + 4));
1922
1923         gfar_write(macptr+1, tempval);
1924 }
1925
1926 /* GFAR error interrupt handler */
1927 static irqreturn_t gfar_error(int irq, void *dev_id)
1928 {
1929         struct net_device *dev = dev_id;
1930         struct gfar_private *priv = netdev_priv(dev);
1931
1932         /* Save ievent for future reference */
1933         u32 events = gfar_read(&priv->regs->ievent);
1934
1935         /* Clear IEVENT */
1936         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1937
1938         /* Hmm... */
1939         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1940                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1941                                 dev->name, events, gfar_read(&priv->regs->imask));
1942
1943         /* Update the error counters */
1944         if (events & IEVENT_TXE) {
1945                 priv->stats.tx_errors++;
1946
1947                 if (events & IEVENT_LC)
1948                         priv->stats.tx_window_errors++;
1949                 if (events & IEVENT_CRL)
1950                         priv->stats.tx_aborted_errors++;
1951                 if (events & IEVENT_XFUN) {
1952                         if (netif_msg_tx_err(priv))
1953                                 printk(KERN_DEBUG "%s: underrun.  packet dropped.\n",
1954                                                 dev->name);
1955                         priv->stats.tx_dropped++;
1956                         priv->extra_stats.tx_underrun++;
1957
1958                         /* Reactivate the Tx Queues */
1959                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1960                 }
1961                 if (netif_msg_tx_err(priv))
1962                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1963         }
1964         if (events & IEVENT_BSY) {
1965                 priv->stats.rx_errors++;
1966                 priv->extra_stats.rx_bsy++;
1967
1968                 gfar_receive(irq, dev_id);
1969
1970 #ifndef CONFIG_GFAR_NAPI
1971                 /* Clear the halt bit in RSTAT */
1972                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1973 #endif
1974
1975                 if (netif_msg_rx_err(priv))
1976                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1977                                         dev->name,
1978                                         gfar_read(&priv->regs->rstat));
1979         }
1980         if (events & IEVENT_BABR) {
1981                 priv->stats.rx_errors++;
1982                 priv->extra_stats.rx_babr++;
1983
1984                 if (netif_msg_rx_err(priv))
1985                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1986         }
1987         if (events & IEVENT_EBERR) {
1988                 priv->extra_stats.eberr++;
1989                 if (netif_msg_rx_err(priv))
1990                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1991         }
1992         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1993                 if (netif_msg_rx_status(priv))
1994                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1995
1996         if (events & IEVENT_BABT) {
1997                 priv->extra_stats.tx_babt++;
1998                 if (netif_msg_tx_err(priv))
1999                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
2000         }
2001         return IRQ_HANDLED;
2002 }
2003
2004 /* Structure for a device driver */
2005 static struct platform_driver gfar_driver = {
2006         .probe = gfar_probe,
2007         .remove = gfar_remove,
2008         .driver = {
2009                 .name = "fsl-gianfar",
2010         },
2011 };
2012
2013 static int __init gfar_init(void)
2014 {
2015         int err = gfar_mdio_init();
2016
2017         if (err)
2018                 return err;
2019
2020         err = platform_driver_register(&gfar_driver);
2021
2022         if (err)
2023                 gfar_mdio_exit();
2024
2025         return err;
2026 }
2027
2028 static void __exit gfar_exit(void)
2029 {
2030         platform_driver_unregister(&gfar_driver);
2031         gfar_mdio_exit();
2032 }
2033
2034 module_init(gfar_init);
2035 module_exit(gfar_exit);
2036