drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  66 #define DEBUG
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/reg.h>
  92 #include <asm/irq.h>
  93 #include <asm/uaccess.h>
  94 #include <linux/module.h>
  95 #include <linux/dma-mapping.h>
  96 #include <linux/crc32.h>
  97 #include <linux/mii.h>
  98 #include <linux/phy.h>
  99 #include <linux/phy_fixed.h>
 100 #include <linux/of.h>
 101 #include <linux/of_net.h>
 102
 103 #include "gianfar.h"
 104 #include "fsl_pq_mdio.h"
 105
 106 #define TX_TIMEOUT      (1*HZ)
 107 #undef BRIEF_GFAR_ERRORS
 108 #undef VERBOSE_GFAR_ERRORS
 109
 110 const char gfar_driver_name[] = "Gianfar Ethernet";
 111 const char gfar_driver_version[] = "1.3";
 112
 113 static int gfar_enet_open(struct net_device *dev);
 114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 115 static void gfar_reset_task(struct work_struct *work);
 116 static void gfar_timeout(struct net_device *dev);
 117 static int gfar_close(struct net_device *dev);
 118 struct sk_buff *gfar_new_skb(struct net_device *dev);
 119 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 120                 struct sk_buff *skb);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static void init_registers(struct net_device *dev);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll(struct napi_struct *napi, int budget);
 136 #ifdef CONFIG_NET_POLL_CONTROLLER
 137 static void gfar_netpoll(struct net_device *dev);
 138 #endif
 139 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 140 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 141 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 142                               int amount_pull);
 143 static void gfar_vlan_rx_register(struct net_device *netdev,
 144                                 struct vlan_group *grp);
 145 void gfar_halt(struct net_device *dev);
 146 static void gfar_halt_nodisable(struct net_device *dev);
 147 void gfar_start(struct net_device *dev);
 148 static void gfar_clear_exact_match(struct net_device *dev);
 149 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 150                                   const u8 *addr);
 151 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 152
 153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 155 MODULE_LICENSE("GPL");
 156
 157 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 158                             dma_addr_t buf)
 159 {
 160         u32 lstatus;
 161
 162         bdp->bufPtr = buf;
 163
 164         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 165         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 166                 lstatus |= BD_LFLAG(RXBD_WRAP);
 167
 168         eieio();
 169
 170         bdp->lstatus = lstatus;
 171 }
 172
 173 static int gfar_init_bds(struct net_device *ndev)
 174 {
 175         struct gfar_private *priv = netdev_priv(ndev);
 176         struct gfar_priv_tx_q *tx_queue = NULL;
 177         struct gfar_priv_rx_q *rx_queue = NULL;
 178         struct txbd8 *txbdp;
 179         struct rxbd8 *rxbdp;
 180         int i, j;
 181
 182         for (i = 0; i < priv->num_tx_queues; i++) {
 183                 tx_queue = priv->tx_queue[i];
 184                 /* Initialize some variables in our dev structure */
 185                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 186                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 187                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 188                 tx_queue->skb_curtx = 0;
 189                 tx_queue->skb_dirtytx = 0;
 190
 191                 /* Initialize Transmit Descriptor Ring */
 192                 txbdp = tx_queue->tx_bd_base;
 193                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 194                         txbdp->lstatus = 0;
 195                         txbdp->bufPtr = 0;
 196                         txbdp++;
 197                 }
 198
 199                 /* Set the last descriptor in the ring to indicate wrap */
 200                 txbdp--;
 201                 txbdp->status |= TXBD_WRAP;
 202         }
 203
 204         for (i = 0; i < priv->num_rx_queues; i++) {
 205                 rx_queue = priv->rx_queue[i];
 206                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 207                 rx_queue->skb_currx = 0;
 208                 rxbdp = rx_queue->rx_bd_base;
 209
 210                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 211                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 212
 213                         if (skb) {
 214                                 gfar_init_rxbdp(rx_queue, rxbdp,
 215                                                 rxbdp->bufPtr);
 216                         } else {
 217                                 skb = gfar_new_skb(ndev);
 218                                 if (!skb) {
 219                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 220                                         goto err_rxalloc_fail;
 221                                 }
 222                                 rx_queue->rx_skbuff[j] = skb;
 223
 224                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 225                         }
 226
 227                         rxbdp++;
 228                 }
 229
 230         }
 231
 232         return 0;
 233
 234 err_rxalloc_fail:
 235         free_skb_resources(priv);
 236         return -ENOMEM;
 237 }
 238
 239 static int gfar_alloc_skb_resources(struct net_device *ndev)
 240 {
 241         void *vaddr;
 242         dma_addr_t addr;
 243         int i, j, k;
 244         struct gfar_private *priv = netdev_priv(ndev);
 245         struct device *dev = &priv->ofdev->dev;
 246         struct gfar_priv_tx_q *tx_queue = NULL;
 247         struct gfar_priv_rx_q *rx_queue = NULL;
 248
 249         priv->total_tx_ring_size = 0;
 250         for (i = 0; i < priv->num_tx_queues; i++)
 251                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 252
 253         priv->total_rx_ring_size = 0;
 254         for (i = 0; i < priv->num_rx_queues; i++)
 255                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 256
 257         /* Allocate memory for the buffer descriptors */
 258         vaddr = dma_alloc_coherent(dev,
 259                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 260                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 261                         &addr, GFP_KERNEL);
 262         if (!vaddr) {
 263                 netif_err(priv, ifup, ndev,
 264                           "Could not allocate buffer descriptors!\n");
 265                 return -ENOMEM;
 266         }
 267
 268         for (i = 0; i < priv->num_tx_queues; i++) {
 269                 tx_queue = priv->tx_queue[i];
 270                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 271                 tx_queue->tx_bd_dma_base = addr;
 272                 tx_queue->dev = ndev;
 273                 /* enet DMA only understands physical addresses */
 274                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 275                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 276         }
 277
 278         /* Start the rx descriptor ring where the tx ring leaves off */
 279         for (i = 0; i < priv->num_rx_queues; i++) {
 280                 rx_queue = priv->rx_queue[i];
 281                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 282                 rx_queue->rx_bd_dma_base = addr;
 283                 rx_queue->dev = ndev;
 284                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 285                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 286         }
 287
 288         /* Setup the skbuff rings */
 289         for (i = 0; i < priv->num_tx_queues; i++) {
 290                 tx_queue = priv->tx_queue[i];
 291                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 292                                   tx_queue->tx_ring_size, GFP_KERNEL);
 293                 if (!tx_queue->tx_skbuff) {
 294                         netif_err(priv, ifup, ndev,
 295                                   "Could not allocate tx_skbuff\n");
 296                         goto cleanup;
 297                 }
 298
 299                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 300                         tx_queue->tx_skbuff[k] = NULL;
 301         }
 302
 303         for (i = 0; i < priv->num_rx_queues; i++) {
 304                 rx_queue = priv->rx_queue[i];
 305                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 306                                   rx_queue->rx_ring_size, GFP_KERNEL);
 307
 308                 if (!rx_queue->rx_skbuff) {
 309                         netif_err(priv, ifup, ndev,
 310                                   "Could not allocate rx_skbuff\n");
 311                         goto cleanup;
 312                 }
 313
 314                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 315                         rx_queue->rx_skbuff[j] = NULL;
 316         }
 317
 318         if (gfar_init_bds(ndev))
 319                 goto cleanup;
 320
 321         return 0;
 322
 323 cleanup:
 324         free_skb_resources(priv);
 325         return -ENOMEM;
 326 }
 327
 328 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 329 {
 330         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 331         u32 __iomem *baddr;
 332         int i;
 333
 334         baddr = &regs->tbase0;
 335         for(i = 0; i < priv->num_tx_queues; i++) {
 336                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 337                 baddr   += 2;
 338         }
 339
 340         baddr = &regs->rbase0;
 341         for(i = 0; i < priv->num_rx_queues; i++) {
 342                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 343                 baddr   += 2;
 344         }
 345 }
 346
 347 static void gfar_init_mac(struct net_device *ndev)
 348 {
 349         struct gfar_private *priv = netdev_priv(ndev);
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352         u32 tctrl = 0;
 353         u32 attrs = 0;
 354
 355         /* write the tx/rx base registers */
 356         gfar_init_tx_rx_base(priv);
 357
 358         /* Configure the coalescing support */
 359         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 360
 361         if (priv->rx_filer_enable) {
 362                 rctrl |= RCTRL_FILREN;
 363                 /* Program the RIR0 reg with the required distribution */
 364                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 365         }
 366
 367         if (ndev->features & NETIF_F_RXCSUM)
 368                 rctrl |= RCTRL_CHECKSUMMING;
 369
 370         if (priv->extended_hash) {
 371                 rctrl |= RCTRL_EXTHASH;
 372
 373                 gfar_clear_exact_match(ndev);
 374                 rctrl |= RCTRL_EMEN;
 375         }
 376
 377         if (priv->padding) {
 378                 rctrl &= ~RCTRL_PAL_MASK;
 379                 rctrl |= RCTRL_PADDING(priv->padding);
 380         }
 381
 382         /* Insert receive time stamps into padding alignment bytes */
 383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 384                 rctrl &= ~RCTRL_PAL_MASK;
 385                 rctrl |= RCTRL_PADDING(8);
 386                 priv->padding = 8;
 387         }
 388
 389         /* Enable HW time stamping if requested from user space */
 390         if (priv->hwts_rx_en)
 391                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 392
 393         /* keep vlan related bits if it's enabled */
 394         if (priv->vlgrp) {
 395                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 396                 tctrl |= TCTRL_VLINS;
 397         }
 398
 399         /* Init rctrl based on our settings */
 400         gfar_write(&regs->rctrl, rctrl);
 401
 402         if (ndev->features & NETIF_F_IP_CSUM)
 403                 tctrl |= TCTRL_INIT_CSUM;
 404
 405         tctrl |= TCTRL_TXSCHED_PRIO;
 406
 407         gfar_write(&regs->tctrl, tctrl);
 408
 409         /* Set the extraction length and index */
 410         attrs = ATTRELI_EL(priv->rx_stash_size) |
 411                 ATTRELI_EI(priv->rx_stash_index);
 412
 413         gfar_write(&regs->attreli, attrs);
 414
 415         /* Start with defaults, and add stashing or locking
 416          * depending on the approprate variables */
 417         attrs = ATTR_INIT_SETTINGS;
 418
 419         if (priv->bd_stash_en)
 420                 attrs |= ATTR_BDSTASH;
 421
 422         if (priv->rx_stash_size != 0)
 423                 attrs |= ATTR_BUFSTASH;
 424
 425         gfar_write(&regs->attr, attrs);
 426
 427         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 428         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 429         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 430 }
 431
 432 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 433 {
 434         struct gfar_private *priv = netdev_priv(dev);
 435         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 436         unsigned long tx_packets = 0, tx_bytes = 0;
 437         int i = 0;
 438
 439         for (i = 0; i < priv->num_rx_queues; i++) {
 440                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 441                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 442                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 443         }
 444
 445         dev->stats.rx_packets = rx_packets;
 446         dev->stats.rx_bytes = rx_bytes;
 447         dev->stats.rx_dropped = rx_dropped;
 448
 449         for (i = 0; i < priv->num_tx_queues; i++) {
 450                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 451                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 452         }
 453
 454         dev->stats.tx_bytes = tx_bytes;
 455         dev->stats.tx_packets = tx_packets;
 456
 457         return &dev->stats;
 458 }
 459
 460 static const struct net_device_ops gfar_netdev_ops = {
 461         .ndo_open = gfar_enet_open,
 462         .ndo_start_xmit = gfar_start_xmit,
 463         .ndo_stop = gfar_close,
 464         .ndo_change_mtu = gfar_change_mtu,
 465         .ndo_set_features = gfar_set_features,
 466         .ndo_set_multicast_list = gfar_set_multi,
 467         .ndo_tx_timeout = gfar_timeout,
 468         .ndo_do_ioctl = gfar_ioctl,
 469         .ndo_get_stats = gfar_get_stats,
 470         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 471         .ndo_set_mac_address = eth_mac_addr,
 472         .ndo_validate_addr = eth_validate_addr,
 473 #ifdef CONFIG_NET_POLL_CONTROLLER
 474         .ndo_poll_controller = gfar_netpoll,
 475 #endif
 476 };
 477
 478 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 479 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 480
 481 void lock_rx_qs(struct gfar_private *priv)
 482 {
 483         int i = 0x0;
 484
 485         for (i = 0; i < priv->num_rx_queues; i++)
 486                 spin_lock(&priv->rx_queue[i]->rxlock);
 487 }
 488
 489 void lock_tx_qs(struct gfar_private *priv)
 490 {
 491         int i = 0x0;
 492
 493         for (i = 0; i < priv->num_tx_queues; i++)
 494                 spin_lock(&priv->tx_queue[i]->txlock);
 495 }
 496
 497 void unlock_rx_qs(struct gfar_private *priv)
 498 {
 499         int i = 0x0;
 500
 501         for (i = 0; i < priv->num_rx_queues; i++)
 502                 spin_unlock(&priv->rx_queue[i]->rxlock);
 503 }
 504
 505 void unlock_tx_qs(struct gfar_private *priv)
 506 {
 507         int i = 0x0;
 508
 509         for (i = 0; i < priv->num_tx_queues; i++)
 510                 spin_unlock(&priv->tx_queue[i]->txlock);
 511 }
 512
 513 /* Returns 1 if incoming frames use an FCB */
 514 static inline int gfar_uses_fcb(struct gfar_private *priv)
 515 {
 516         return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) ||
 517                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 518 }
 519
 520 static void free_tx_pointers(struct gfar_private *priv)
 521 {
 522         int i = 0;
 523
 524         for (i = 0; i < priv->num_tx_queues; i++)
 525                 kfree(priv->tx_queue[i]);
 526 }
 527
 528 static void free_rx_pointers(struct gfar_private *priv)
 529 {
 530         int i = 0;
 531
 532         for (i = 0; i < priv->num_rx_queues; i++)
 533                 kfree(priv->rx_queue[i]);
 534 }
 535
 536 static void unmap_group_regs(struct gfar_private *priv)
 537 {
 538         int i = 0;
 539
 540         for (i = 0; i < MAXGROUPS; i++)
 541                 if (priv->gfargrp[i].regs)
 542                         iounmap(priv->gfargrp[i].regs);
 543 }
 544
 545 static void disable_napi(struct gfar_private *priv)
 546 {
 547         int i = 0;
 548
 549         for (i = 0; i < priv->num_grps; i++)
 550                 napi_disable(&priv->gfargrp[i].napi);
 551 }
 552
 553 static void enable_napi(struct gfar_private *priv)
 554 {
 555         int i = 0;
 556
 557         for (i = 0; i < priv->num_grps; i++)
 558                 napi_enable(&priv->gfargrp[i].napi);
 559 }
 560
 561 static int gfar_parse_group(struct device_node *np,
 562                 struct gfar_private *priv, const char *model)
 563 {
 564         u32 *queue_mask;
 565
 566         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 567         if (!priv->gfargrp[priv->num_grps].regs)
 568                 return -ENOMEM;
 569
 570         priv->gfargrp[priv->num_grps].interruptTransmit =
 571                         irq_of_parse_and_map(np, 0);
 572
 573         /* If we aren't the FEC we have multiple interrupts */
 574         if (model && strcasecmp(model, "FEC")) {
 575                 priv->gfargrp[priv->num_grps].interruptReceive =
 576                         irq_of_parse_and_map(np, 1);
 577                 priv->gfargrp[priv->num_grps].interruptError =
 578                         irq_of_parse_and_map(np,2);
 579                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 580                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 581                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 582                         return -EINVAL;
 583         }
 584
 585         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 586         priv->gfargrp[priv->num_grps].priv = priv;
 587         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 588         if(priv->mode == MQ_MG_MODE) {
 589                 queue_mask = (u32 *)of_get_property(np,
 590                                         "fsl,rx-bit-map", NULL);
 591                 priv->gfargrp[priv->num_grps].rx_bit_map =
 592                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 593                 queue_mask = (u32 *)of_get_property(np,
 594                                         "fsl,tx-bit-map", NULL);
 595                 priv->gfargrp[priv->num_grps].tx_bit_map =
 596                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 597         } else {
 598                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 599                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 600         }
 601         priv->num_grps++;
 602
 603         return 0;
 604 }
 605
 606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 607 {
 608         const char *model;
 609         const char *ctype;
 610         const void *mac_addr;
 611         int err = 0, i;
 612         struct net_device *dev = NULL;
 613         struct gfar_private *priv = NULL;
 614         struct device_node *np = ofdev->dev.of_node;
 615         struct device_node *child = NULL;
 616         const u32 *stash;
 617         const u32 *stash_len;
 618         const u32 *stash_idx;
 619         unsigned int num_tx_qs, num_rx_qs;
 620         u32 *tx_queues, *rx_queues;
 621
 622         if (!np || !of_device_is_available(np))
 623                 return -ENODEV;
 624
 625         /* parse the num of tx and rx queues */
 626         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 627         num_tx_qs = tx_queues ? *tx_queues : 1;
 628
 629         if (num_tx_qs > MAX_TX_QS) {
 630                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 631                        num_tx_qs, MAX_TX_QS);
 632                 pr_err("Cannot do alloc_etherdev, aborting\n");
 633                 return -EINVAL;
 634         }
 635
 636         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 637         num_rx_qs = rx_queues ? *rx_queues : 1;
 638
 639         if (num_rx_qs > MAX_RX_QS) {
 640                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 641                        num_rx_qs, MAX_RX_QS);
 642                 pr_err("Cannot do alloc_etherdev, aborting\n");
 643                 return -EINVAL;
 644         }
 645
 646         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 647         dev = *pdev;
 648         if (NULL == dev)
 649                 return -ENOMEM;
 650
 651         priv = netdev_priv(dev);
 652         priv->node = ofdev->dev.of_node;
 653         priv->ndev = dev;
 654
 655         priv->num_tx_queues = num_tx_qs;
 656         netif_set_real_num_rx_queues(dev, num_rx_qs);
 657         priv->num_rx_queues = num_rx_qs;
 658         priv->num_grps = 0x0;
 659
 660         model = of_get_property(np, "model", NULL);
 661
 662         for (i = 0; i < MAXGROUPS; i++)
 663                 priv->gfargrp[i].regs = NULL;
 664
 665         /* Parse and initialize group specific information */
 666         if (of_device_is_compatible(np, "fsl,etsec2")) {
 667                 priv->mode = MQ_MG_MODE;
 668                 for_each_child_of_node(np, child) {
 669                         err = gfar_parse_group(child, priv, model);
 670                         if (err)
 671                                 goto err_grp_init;
 672                 }
 673         } else {
 674                 priv->mode = SQ_SG_MODE;
 675                 err = gfar_parse_group(np, priv, model);
 676                 if(err)
 677                         goto err_grp_init;
 678         }
 679
 680         for (i = 0; i < priv->num_tx_queues; i++)
 681                priv->tx_queue[i] = NULL;
 682         for (i = 0; i < priv->num_rx_queues; i++)
 683                 priv->rx_queue[i] = NULL;
 684
 685         for (i = 0; i < priv->num_tx_queues; i++) {
 686                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 687                                             GFP_KERNEL);
 688                 if (!priv->tx_queue[i]) {
 689                         err = -ENOMEM;
 690                         goto tx_alloc_failed;
 691                 }
 692                 priv->tx_queue[i]->tx_skbuff = NULL;
 693                 priv->tx_queue[i]->qindex = i;
 694                 priv->tx_queue[i]->dev = dev;
 695                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 696         }
 697
 698         for (i = 0; i < priv->num_rx_queues; i++) {
 699                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->rx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto rx_alloc_failed;
 704                 }
 705                 priv->rx_queue[i]->rx_skbuff = NULL;
 706                 priv->rx_queue[i]->qindex = i;
 707                 priv->rx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 709         }
 710
 711
 712         stash = of_get_property(np, "bd-stash", NULL);
 713
 714         if (stash) {
 715                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 716                 priv->bd_stash_en = 1;
 717         }
 718
 719         stash_len = of_get_property(np, "rx-stash-len", NULL);
 720
 721         if (stash_len)
 722                 priv->rx_stash_size = *stash_len;
 723
 724         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 725
 726         if (stash_idx)
 727                 priv->rx_stash_index = *stash_idx;
 728
 729         if (stash_len || stash_idx)
 730                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 731
 732         mac_addr = of_get_mac_address(np);
 733         if (mac_addr)
 734                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 735
 736         if (model && !strcasecmp(model, "TSEC"))
 737                 priv->device_flags =
 738                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 739                         FSL_GIANFAR_DEV_HAS_COALESCE |
 740                         FSL_GIANFAR_DEV_HAS_RMON |
 741                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 742         if (model && !strcasecmp(model, "eTSEC"))
 743                 priv->device_flags =
 744                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 745                         FSL_GIANFAR_DEV_HAS_COALESCE |
 746                         FSL_GIANFAR_DEV_HAS_RMON |
 747                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 748                         FSL_GIANFAR_DEV_HAS_PADDING |
 749                         FSL_GIANFAR_DEV_HAS_CSUM |
 750                         FSL_GIANFAR_DEV_HAS_VLAN |
 751                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 752                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 753                         FSL_GIANFAR_DEV_HAS_TIMER;
 754
 755         ctype = of_get_property(np, "phy-connection-type", NULL);
 756
 757         /* We only care about rgmii-id.  The rest are autodetected */
 758         if (ctype && !strcmp(ctype, "rgmii-id"))
 759                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 760         else
 761                 priv->interface = PHY_INTERFACE_MODE_MII;
 762
 763         if (of_get_property(np, "fsl,magic-packet", NULL))
 764                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 765
 766         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 767
 768         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 769         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 770
 771         return 0;
 772
 773 rx_alloc_failed:
 774         free_rx_pointers(priv);
 775 tx_alloc_failed:
 776         free_tx_pointers(priv);
 777 err_grp_init:
 778         unmap_group_regs(priv);
 779         free_netdev(dev);
 780         return err;
 781 }
 782
 783 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 784                         struct ifreq *ifr, int cmd)
 785 {
 786         struct hwtstamp_config config;
 787         struct gfar_private *priv = netdev_priv(netdev);
 788
 789         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 790                 return -EFAULT;
 791
 792         /* reserved for future extensions */
 793         if (config.flags)
 794                 return -EINVAL;
 795
 796         switch (config.tx_type) {
 797         case HWTSTAMP_TX_OFF:
 798                 priv->hwts_tx_en = 0;
 799                 break;
 800         case HWTSTAMP_TX_ON:
 801                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 802                         return -ERANGE;
 803                 priv->hwts_tx_en = 1;
 804                 break;
 805         default:
 806                 return -ERANGE;
 807         }
 808
 809         switch (config.rx_filter) {
 810         case HWTSTAMP_FILTER_NONE:
 811                 if (priv->hwts_rx_en) {
 812                         stop_gfar(netdev);
 813                         priv->hwts_rx_en = 0;
 814                         startup_gfar(netdev);
 815                 }
 816                 break;
 817         default:
 818                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 819                         return -ERANGE;
 820                 if (!priv->hwts_rx_en) {
 821                         stop_gfar(netdev);
 822                         priv->hwts_rx_en = 1;
 823                         startup_gfar(netdev);
 824                 }
 825                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 826                 break;
 827         }
 828
 829         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 830                 -EFAULT : 0;
 831 }
 832
 833 /* Ioctl MII Interface */
 834 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 835 {
 836         struct gfar_private *priv = netdev_priv(dev);
 837
 838         if (!netif_running(dev))
 839                 return -EINVAL;
 840
 841         if (cmd == SIOCSHWTSTAMP)
 842                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 843
 844         if (!priv->phydev)
 845                 return -ENODEV;
 846
 847         return phy_mii_ioctl(priv->phydev, rq, cmd);
 848 }
 849
 850 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 851 {
 852         unsigned int new_bit_map = 0x0;
 853         int mask = 0x1 << (max_qs - 1), i;
 854         for (i = 0; i < max_qs; i++) {
 855                 if (bit_map & mask)
 856                         new_bit_map = new_bit_map + (1 << i);
 857                 mask = mask >> 0x1;
 858         }
 859         return new_bit_map;
 860 }
 861
 862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 863                                    u32 class)
 864 {
 865         u32 rqfpr = FPR_FILER_MASK;
 866         u32 rqfcr = 0x0;
 867
 868         rqfar--;
 869         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 870         ftp_rqfpr[rqfar] = rqfpr;
 871         ftp_rqfcr[rqfar] = rqfcr;
 872         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CMP_NOMATCH;
 876         ftp_rqfpr[rqfar] = rqfpr;
 877         ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 882         rqfpr = class;
 883         ftp_rqfcr[rqfar] = rqfcr;
 884         ftp_rqfpr[rqfar] = rqfpr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 889         rqfpr = class;
 890         ftp_rqfcr[rqfar] = rqfcr;
 891         ftp_rqfpr[rqfar] = rqfpr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         return rqfar;
 895 }
 896
 897 static void gfar_init_filer_table(struct gfar_private *priv)
 898 {
 899         int i = 0x0;
 900         u32 rqfar = MAX_FILER_IDX;
 901         u32 rqfcr = 0x0;
 902         u32 rqfpr = FPR_FILER_MASK;
 903
 904         /* Default rule */
 905         rqfcr = RQFCR_CMP_MATCH;
 906         ftp_rqfcr[rqfar] = rqfcr;
 907         ftp_rqfpr[rqfar] = rqfpr;
 908         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 909
 910         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 911         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 916
 917         /* cur_filer_idx indicated the first non-masked rule */
 918         priv->cur_filer_idx = rqfar;
 919
 920         /* Rest are masked rules */
 921         rqfcr = RQFCR_CMP_NOMATCH;
 922         for (i = 0; i < rqfar; i++) {
 923                 ftp_rqfcr[i] = rqfcr;
 924                 ftp_rqfpr[i] = rqfpr;
 925                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 926         }
 927 }
 928
 929 static void gfar_detect_errata(struct gfar_private *priv)
 930 {
 931         struct device *dev = &priv->ofdev->dev;
 932         unsigned int pvr = mfspr(SPRN_PVR);
 933         unsigned int svr = mfspr(SPRN_SVR);
 934         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 935         unsigned int rev = svr & 0xffff;
 936
 937         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 938         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 939                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 940                 priv->errata |= GFAR_ERRATA_74;
 941
 942         /* MPC8313 and MPC837x all rev */
 943         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 944                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 945                 priv->errata |= GFAR_ERRATA_76;
 946
 947         /* MPC8313 and MPC837x all rev */
 948         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 949                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 950                 priv->errata |= GFAR_ERRATA_A002;
 951
 952         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 953         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 954                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 955                 priv->errata |= GFAR_ERRATA_12;
 956
 957         if (priv->errata)
 958                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 959                          priv->errata);
 960 }
 961
 962 /* Set up the ethernet device structure, private data,
 963  * and anything else we need before we start */
 964 static int gfar_probe(struct platform_device *ofdev)
 965 {
 966         u32 tempval;
 967         struct net_device *dev = NULL;
 968         struct gfar_private *priv = NULL;
 969         struct gfar __iomem *regs = NULL;
 970         int err = 0, i, grp_idx = 0;
 971         int len_devname;
 972         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 973         u32 isrg = 0;
 974         u32 __iomem *baddr;
 975
 976         err = gfar_of_init(ofdev, &dev);
 977
 978         if (err)
 979                 return err;
 980
 981         priv = netdev_priv(dev);
 982         priv->ndev = dev;
 983         priv->ofdev = ofdev;
 984         priv->node = ofdev->dev.of_node;
 985         SET_NETDEV_DEV(dev, &ofdev->dev);
 986
 987         spin_lock_init(&priv->bflock);
 988         INIT_WORK(&priv->reset_task, gfar_reset_task);
 989
 990         dev_set_drvdata(&ofdev->dev, priv);
 991         regs = priv->gfargrp[0].regs;
 992
 993         gfar_detect_errata(priv);
 994
 995         /* Stop the DMA engine now, in case it was running before */
 996         /* (The firmware could have used it, and left it running). */
 997         gfar_halt(dev);
 998
 999         /* Reset MAC layer */
1000         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1001
1002         /* We need to delay at least 3 TX clocks */
1003         udelay(2);
1004
1005         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1006         gfar_write(&regs->maccfg1, tempval);
1007
1008         /* Initialize MACCFG2. */
1009         tempval = MACCFG2_INIT_SETTINGS;
1010         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1011                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1012         gfar_write(&regs->maccfg2, tempval);
1013
1014         /* Initialize ECNTRL */
1015         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1016
1017         /* Set the dev->base_addr to the gfar reg region */
1018         dev->base_addr = (unsigned long) regs;
1019
1020         SET_NETDEV_DEV(dev, &ofdev->dev);
1021
1022         /* Fill in the dev structure */
1023         dev->watchdog_timeo = TX_TIMEOUT;
1024         dev->mtu = 1500;
1025         dev->netdev_ops = &gfar_netdev_ops;
1026         dev->ethtool_ops = &gfar_ethtool_ops;
1027
1028         /* Register for napi ...We are registering NAPI for each grp */
1029         for (i = 0; i < priv->num_grps; i++)
1030                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1031
1032         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1033                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1034                         NETIF_F_RXCSUM;
1035                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1036                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1037         }
1038
1039         priv->vlgrp = NULL;
1040
1041         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1042                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1043
1044         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1045                 priv->extended_hash = 1;
1046                 priv->hash_width = 9;
1047
1048                 priv->hash_regs[0] = &regs->igaddr0;
1049                 priv->hash_regs[1] = &regs->igaddr1;
1050                 priv->hash_regs[2] = &regs->igaddr2;
1051                 priv->hash_regs[3] = &regs->igaddr3;
1052                 priv->hash_regs[4] = &regs->igaddr4;
1053                 priv->hash_regs[5] = &regs->igaddr5;
1054                 priv->hash_regs[6] = &regs->igaddr6;
1055                 priv->hash_regs[7] = &regs->igaddr7;
1056                 priv->hash_regs[8] = &regs->gaddr0;
1057                 priv->hash_regs[9] = &regs->gaddr1;
1058                 priv->hash_regs[10] = &regs->gaddr2;
1059                 priv->hash_regs[11] = &regs->gaddr3;
1060                 priv->hash_regs[12] = &regs->gaddr4;
1061                 priv->hash_regs[13] = &regs->gaddr5;
1062                 priv->hash_regs[14] = &regs->gaddr6;
1063                 priv->hash_regs[15] = &regs->gaddr7;
1064
1065         } else {
1066                 priv->extended_hash = 0;
1067                 priv->hash_width = 8;
1068
1069                 priv->hash_regs[0] = &regs->gaddr0;
1070                 priv->hash_regs[1] = &regs->gaddr1;
1071                 priv->hash_regs[2] = &regs->gaddr2;
1072                 priv->hash_regs[3] = &regs->gaddr3;
1073                 priv->hash_regs[4] = &regs->gaddr4;
1074                 priv->hash_regs[5] = &regs->gaddr5;
1075                 priv->hash_regs[6] = &regs->gaddr6;
1076                 priv->hash_regs[7] = &regs->gaddr7;
1077         }
1078
1079         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1080                 priv->padding = DEFAULT_PADDING;
1081         else
1082                 priv->padding = 0;
1083
1084         if (dev->features & NETIF_F_IP_CSUM ||
1085                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1086                 dev->hard_header_len += GMAC_FCB_LEN;
1087
1088         /* Program the isrg regs only if number of grps > 1 */
1089         if (priv->num_grps > 1) {
1090                 baddr = &regs->isrg0;
1091                 for (i = 0; i < priv->num_grps; i++) {
1092                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1093                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1094                         gfar_write(baddr, isrg);
1095                         baddr++;
1096                         isrg = 0x0;
1097                 }
1098         }
1099
1100         /* Need to reverse the bit maps as  bit_map's MSB is q0
1101          * but, for_each_set_bit parses from right to left, which
1102          * basically reverses the queue numbers */
1103         for (i = 0; i< priv->num_grps; i++) {
1104                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1105                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1106                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1107                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1108         }
1109
1110         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1111          * also assign queues to groups */
1112         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1113                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1114                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1115                                 priv->num_rx_queues) {
1116                         priv->gfargrp[grp_idx].num_rx_queues++;
1117                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1118                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1119                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1120                 }
1121                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1122                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1123                                 priv->num_tx_queues) {
1124                         priv->gfargrp[grp_idx].num_tx_queues++;
1125                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1126                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1127                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1128                 }
1129                 priv->gfargrp[grp_idx].rstat = rstat;
1130                 priv->gfargrp[grp_idx].tstat = tstat;
1131                 rstat = tstat =0;
1132         }
1133
1134         gfar_write(&regs->rqueue, rqueue);
1135         gfar_write(&regs->tqueue, tqueue);
1136
1137         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1138
1139         /* Initializing some of the rx/tx queue level parameters */
1140         for (i = 0; i < priv->num_tx_queues; i++) {
1141                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1142                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1143                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1144                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1145         }
1146
1147         for (i = 0; i < priv->num_rx_queues; i++) {
1148                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1149                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1150                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1151         }
1152
1153         /* enable filer if using multiple RX queues*/
1154         if(priv->num_rx_queues > 1)
1155                 priv->rx_filer_enable = 1;
1156         /* Enable most messages by default */
1157         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1158
1159         /* Carrier starts down, phylib will bring it up */
1160         netif_carrier_off(dev);
1161
1162         err = register_netdev(dev);
1163
1164         if (err) {
1165                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1166                 goto register_fail;
1167         }
1168
1169         device_init_wakeup(&dev->dev,
1170                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1171
1172         /* fill out IRQ number and name fields */
1173         len_devname = strlen(dev->name);
1174         for (i = 0; i < priv->num_grps; i++) {
1175                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1176                                 len_devname);
1177                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1178                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1179                                 "_g", sizeof("_g"));
1180                         priv->gfargrp[i].int_name_tx[
1181                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1182                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1183                                 priv->gfargrp[i].int_name_tx)],
1184                                 "_tx", sizeof("_tx") + 1);
1185
1186                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1187                                         len_devname);
1188                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1189                                         "_g", sizeof("_g"));
1190                         priv->gfargrp[i].int_name_rx[
1191                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1192                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1193                                 priv->gfargrp[i].int_name_rx)],
1194                                 "_rx", sizeof("_rx") + 1);
1195
1196                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1197                                         len_devname);
1198                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1199                                 "_g", sizeof("_g"));
1200                         priv->gfargrp[i].int_name_er[strlen(
1201                                         priv->gfargrp[i].int_name_er)] = i+48;
1202                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1203                                 priv->gfargrp[i].int_name_er)],
1204                                 "_er", sizeof("_er") + 1);
1205                 } else
1206                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1207         }
1208
1209         /* Initialize the filer table */
1210         gfar_init_filer_table(priv);
1211
1212         /* Create all the sysfs files */
1213         gfar_init_sysfs(dev);
1214
1215         /* Print out the device info */
1216         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1217
1218         /* Even more device info helps when determining which kernel */
1219         /* provided which set of benchmarks. */
1220         netdev_info(dev, "Running with NAPI enabled\n");
1221         for (i = 0; i < priv->num_rx_queues; i++)
1222                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1223                             i, priv->rx_queue[i]->rx_ring_size);
1224         for(i = 0; i < priv->num_tx_queues; i++)
1225                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1226                             i, priv->tx_queue[i]->tx_ring_size);
1227
1228         return 0;
1229
1230 register_fail:
1231         unmap_group_regs(priv);
1232         free_tx_pointers(priv);
1233         free_rx_pointers(priv);
1234         if (priv->phy_node)
1235                 of_node_put(priv->phy_node);
1236         if (priv->tbi_node)
1237                 of_node_put(priv->tbi_node);
1238         free_netdev(dev);
1239         return err;
1240 }
1241
1242 static int gfar_remove(struct platform_device *ofdev)
1243 {
1244         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1245
1246         if (priv->phy_node)
1247                 of_node_put(priv->phy_node);
1248         if (priv->tbi_node)
1249                 of_node_put(priv->tbi_node);
1250
1251         dev_set_drvdata(&ofdev->dev, NULL);
1252
1253         unregister_netdev(priv->ndev);
1254         unmap_group_regs(priv);
1255         free_netdev(priv->ndev);
1256
1257         return 0;
1258 }
1259
1260 #ifdef CONFIG_PM
1261
1262 static int gfar_suspend(struct device *dev)
1263 {
1264         struct gfar_private *priv = dev_get_drvdata(dev);
1265         struct net_device *ndev = priv->ndev;
1266         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1267         unsigned long flags;
1268         u32 tempval;
1269
1270         int magic_packet = priv->wol_en &&
1271                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1272
1273         netif_device_detach(ndev);
1274
1275         if (netif_running(ndev)) {
1276
1277                 local_irq_save(flags);
1278                 lock_tx_qs(priv);
1279                 lock_rx_qs(priv);
1280
1281                 gfar_halt_nodisable(ndev);
1282
1283                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1284                 tempval = gfar_read(&regs->maccfg1);
1285
1286                 tempval &= ~MACCFG1_TX_EN;
1287
1288                 if (!magic_packet)
1289                         tempval &= ~MACCFG1_RX_EN;
1290
1291                 gfar_write(&regs->maccfg1, tempval);
1292
1293                 unlock_rx_qs(priv);
1294                 unlock_tx_qs(priv);
1295                 local_irq_restore(flags);
1296
1297                 disable_napi(priv);
1298
1299                 if (magic_packet) {
1300                         /* Enable interrupt on Magic Packet */
1301                         gfar_write(&regs->imask, IMASK_MAG);
1302
1303                         /* Enable Magic Packet mode */
1304                         tempval = gfar_read(&regs->maccfg2);
1305                         tempval |= MACCFG2_MPEN;
1306                         gfar_write(&regs->maccfg2, tempval);
1307                 } else {
1308                         phy_stop(priv->phydev);
1309                 }
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int gfar_resume(struct device *dev)
1316 {
1317         struct gfar_private *priv = dev_get_drvdata(dev);
1318         struct net_device *ndev = priv->ndev;
1319         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1320         unsigned long flags;
1321         u32 tempval;
1322         int magic_packet = priv->wol_en &&
1323                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1324
1325         if (!netif_running(ndev)) {
1326                 netif_device_attach(ndev);
1327                 return 0;
1328         }
1329
1330         if (!magic_packet && priv->phydev)
1331                 phy_start(priv->phydev);
1332
1333         /* Disable Magic Packet mode, in case something
1334          * else woke us up.
1335          */
1336         local_irq_save(flags);
1337         lock_tx_qs(priv);
1338         lock_rx_qs(priv);
1339
1340         tempval = gfar_read(&regs->maccfg2);
1341         tempval &= ~MACCFG2_MPEN;
1342         gfar_write(&regs->maccfg2, tempval);
1343
1344         gfar_start(ndev);
1345
1346         unlock_rx_qs(priv);
1347         unlock_tx_qs(priv);
1348         local_irq_restore(flags);
1349
1350         netif_device_attach(ndev);
1351
1352         enable_napi(priv);
1353
1354         return 0;
1355 }
1356
1357 static int gfar_restore(struct device *dev)
1358 {
1359         struct gfar_private *priv = dev_get_drvdata(dev);
1360         struct net_device *ndev = priv->ndev;
1361
1362         if (!netif_running(ndev))
1363                 return 0;
1364
1365         gfar_init_bds(ndev);
1366         init_registers(ndev);
1367         gfar_set_mac_address(ndev);
1368         gfar_init_mac(ndev);
1369         gfar_start(ndev);
1370
1371         priv->oldlink = 0;
1372         priv->oldspeed = 0;
1373         priv->oldduplex = -1;
1374
1375         if (priv->phydev)
1376                 phy_start(priv->phydev);
1377
1378         netif_device_attach(ndev);
1379         enable_napi(priv);
1380
1381         return 0;
1382 }
1383
1384 static struct dev_pm_ops gfar_pm_ops = {
1385         .suspend = gfar_suspend,
1386         .resume = gfar_resume,
1387         .freeze = gfar_suspend,
1388         .thaw = gfar_resume,
1389         .restore = gfar_restore,
1390 };
1391
1392 #define GFAR_PM_OPS (&gfar_pm_ops)
1393
1394 #else
1395
1396 #define GFAR_PM_OPS NULL
1397
1398 #endif
1399
1400 /* Reads the controller's registers to determine what interface
1401  * connects it to the PHY.
1402  */
1403 static phy_interface_t gfar_get_interface(struct net_device *dev)
1404 {
1405         struct gfar_private *priv = netdev_priv(dev);
1406         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1407         u32 ecntrl;
1408
1409         ecntrl = gfar_read(&regs->ecntrl);
1410
1411         if (ecntrl & ECNTRL_SGMII_MODE)
1412                 return PHY_INTERFACE_MODE_SGMII;
1413
1414         if (ecntrl & ECNTRL_TBI_MODE) {
1415                 if (ecntrl & ECNTRL_REDUCED_MODE)
1416                         return PHY_INTERFACE_MODE_RTBI;
1417                 else
1418                         return PHY_INTERFACE_MODE_TBI;
1419         }
1420
1421         if (ecntrl & ECNTRL_REDUCED_MODE) {
1422                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1423                         return PHY_INTERFACE_MODE_RMII;
1424                 else {
1425                         phy_interface_t interface = priv->interface;
1426
1427                         /*
1428                          * This isn't autodetected right now, so it must
1429                          * be set by the device tree or platform code.
1430                          */
1431                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1432                                 return PHY_INTERFACE_MODE_RGMII_ID;
1433
1434                         return PHY_INTERFACE_MODE_RGMII;
1435                 }
1436         }
1437
1438         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1439                 return PHY_INTERFACE_MODE_GMII;
1440
1441         return PHY_INTERFACE_MODE_MII;
1442 }
1443
1444
1445 /* Initializes driver's PHY state, and attaches to the PHY.
1446  * Returns 0 on success.
1447  */
1448 static int init_phy(struct net_device *dev)
1449 {
1450         struct gfar_private *priv = netdev_priv(dev);
1451         uint gigabit_support =
1452                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1453                 SUPPORTED_1000baseT_Full : 0;
1454         phy_interface_t interface;
1455
1456         priv->oldlink = 0;
1457         priv->oldspeed = 0;
1458         priv->oldduplex = -1;
1459
1460         interface = gfar_get_interface(dev);
1461
1462         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1463                                       interface);
1464         if (!priv->phydev)
1465                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1466                                                          interface);
1467         if (!priv->phydev) {
1468                 dev_err(&dev->dev, "could not attach to PHY\n");
1469                 return -ENODEV;
1470         }
1471
1472         if (interface == PHY_INTERFACE_MODE_SGMII)
1473                 gfar_configure_serdes(dev);
1474
1475         /* Remove any features not supported by the controller */
1476         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1477         priv->phydev->advertising = priv->phydev->supported;
1478
1479         return 0;
1480 }
1481
1482 /*
1483  * Initialize TBI PHY interface for communicating with the
1484  * SERDES lynx PHY on the chip.  We communicate with this PHY
1485  * through the MDIO bus on each controller, treating it as a
1486  * "normal" PHY at the address found in the TBIPA register.  We assume
1487  * that the TBIPA register is valid.  Either the MDIO bus code will set
1488  * it to a value that doesn't conflict with other PHYs on the bus, or the
1489  * value doesn't matter, as there are no other PHYs on the bus.
1490  */
1491 static void gfar_configure_serdes(struct net_device *dev)
1492 {
1493         struct gfar_private *priv = netdev_priv(dev);
1494         struct phy_device *tbiphy;
1495
1496         if (!priv->tbi_node) {
1497                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1498                                     "device tree specify a tbi-handle\n");
1499                 return;
1500         }
1501
1502         tbiphy = of_phy_find_device(priv->tbi_node);
1503         if (!tbiphy) {
1504                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1505                 return;
1506         }
1507
1508         /*
1509          * If the link is already up, we must already be ok, and don't need to
1510          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1511          * everything for us?  Resetting it takes the link down and requires
1512          * several seconds for it to come back.
1513          */
1514         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1515                 return;
1516
1517         /* Single clk mode, mii mode off(for serdes communication) */
1518         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1519
1520         phy_write(tbiphy, MII_ADVERTISE,
1521                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1522                         ADVERTISE_1000XPSE_ASYM);
1523
1524         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1525                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1526 }
1527
1528 static void init_registers(struct net_device *dev)
1529 {
1530         struct gfar_private *priv = netdev_priv(dev);
1531         struct gfar __iomem *regs = NULL;
1532         int i = 0;
1533
1534         for (i = 0; i < priv->num_grps; i++) {
1535                 regs = priv->gfargrp[i].regs;
1536                 /* Clear IEVENT */
1537                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1538
1539                 /* Initialize IMASK */
1540                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1541         }
1542
1543         regs = priv->gfargrp[0].regs;
1544         /* Init hash registers to zero */
1545         gfar_write(&regs->igaddr0, 0);
1546         gfar_write(&regs->igaddr1, 0);
1547         gfar_write(&regs->igaddr2, 0);
1548         gfar_write(&regs->igaddr3, 0);
1549         gfar_write(&regs->igaddr4, 0);
1550         gfar_write(&regs->igaddr5, 0);
1551         gfar_write(&regs->igaddr6, 0);
1552         gfar_write(&regs->igaddr7, 0);
1553
1554         gfar_write(&regs->gaddr0, 0);
1555         gfar_write(&regs->gaddr1, 0);
1556         gfar_write(&regs->gaddr2, 0);
1557         gfar_write(&regs->gaddr3, 0);
1558         gfar_write(&regs->gaddr4, 0);
1559         gfar_write(&regs->gaddr5, 0);
1560         gfar_write(&regs->gaddr6, 0);
1561         gfar_write(&regs->gaddr7, 0);
1562
1563         /* Zero out the rmon mib registers if it has them */
1564         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1565                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1566
1567                 /* Mask off the CAM interrupts */
1568                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1569                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1570         }
1571
1572         /* Initialize the max receive buffer length */
1573         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1574
1575         /* Initialize the Minimum Frame Length Register */
1576         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1577 }
1578
1579 static int __gfar_is_rx_idle(struct gfar_private *priv)
1580 {
1581         u32 res;
1582
1583         /*
1584          * Normaly TSEC should not hang on GRS commands, so we should
1585          * actually wait for IEVENT_GRSC flag.
1586          */
1587         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1588                 return 0;
1589
1590         /*
1591          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1592          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1593          * and the Rx can be safely reset.
1594          */
1595         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1596         res &= 0x7f807f80;
1597         if ((res & 0xffff) == (res >> 16))
1598                 return 1;
1599
1600         return 0;
1601 }
1602
1603 /* Halt the receive and transmit queues */
1604 static void gfar_halt_nodisable(struct net_device *dev)
1605 {
1606         struct gfar_private *priv = netdev_priv(dev);
1607         struct gfar __iomem *regs = NULL;
1608         u32 tempval;
1609         int i = 0;
1610
1611         for (i = 0; i < priv->num_grps; i++) {
1612                 regs = priv->gfargrp[i].regs;
1613                 /* Mask all interrupts */
1614                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1615
1616                 /* Clear all interrupts */
1617                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1618         }
1619
1620         regs = priv->gfargrp[0].regs;
1621         /* Stop the DMA, and wait for it to stop */
1622         tempval = gfar_read(&regs->dmactrl);
1623         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1624             != (DMACTRL_GRS | DMACTRL_GTS)) {
1625                 int ret;
1626
1627                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1628                 gfar_write(&regs->dmactrl, tempval);
1629
1630                 do {
1631                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1632                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1633                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1634                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1635                                 ret = __gfar_is_rx_idle(priv);
1636                 } while (!ret);
1637         }
1638 }
1639
1640 /* Halt the receive and transmit queues */
1641 void gfar_halt(struct net_device *dev)
1642 {
1643         struct gfar_private *priv = netdev_priv(dev);
1644         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1645         u32 tempval;
1646
1647         gfar_halt_nodisable(dev);
1648
1649         /* Disable Rx and Tx */
1650         tempval = gfar_read(&regs->maccfg1);
1651         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1652         gfar_write(&regs->maccfg1, tempval);
1653 }
1654
1655 static void free_grp_irqs(struct gfar_priv_grp *grp)
1656 {
1657         free_irq(grp->interruptError, grp);
1658         free_irq(grp->interruptTransmit, grp);
1659         free_irq(grp->interruptReceive, grp);
1660 }
1661
1662 void stop_gfar(struct net_device *dev)
1663 {
1664         struct gfar_private *priv = netdev_priv(dev);
1665         unsigned long flags;
1666         int i;
1667
1668         phy_stop(priv->phydev);
1669
1670
1671         /* Lock it down */
1672         local_irq_save(flags);
1673         lock_tx_qs(priv);
1674         lock_rx_qs(priv);
1675
1676         gfar_halt(dev);
1677
1678         unlock_rx_qs(priv);
1679         unlock_tx_qs(priv);
1680         local_irq_restore(flags);
1681
1682         /* Free the IRQs */
1683         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1684                 for (i = 0; i < priv->num_grps; i++)
1685                         free_grp_irqs(&priv->gfargrp[i]);
1686         } else {
1687                 for (i = 0; i < priv->num_grps; i++)
1688                         free_irq(priv->gfargrp[i].interruptTransmit,
1689                                         &priv->gfargrp[i]);
1690         }
1691
1692         free_skb_resources(priv);
1693 }
1694
1695 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1696 {
1697         struct txbd8 *txbdp;
1698         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1699         int i, j;
1700
1701         txbdp = tx_queue->tx_bd_base;
1702
1703         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1704                 if (!tx_queue->tx_skbuff[i])
1705                         continue;
1706
1707                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1708                                 txbdp->length, DMA_TO_DEVICE);
1709                 txbdp->lstatus = 0;
1710                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1711                                 j++) {
1712                         txbdp++;
1713                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1714                                         txbdp->length, DMA_TO_DEVICE);
1715                 }
1716                 txbdp++;
1717                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1718                 tx_queue->tx_skbuff[i] = NULL;
1719         }
1720         kfree(tx_queue->tx_skbuff);
1721 }
1722
1723 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1724 {
1725         struct rxbd8 *rxbdp;
1726         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1727         int i;
1728
1729         rxbdp = rx_queue->rx_bd_base;
1730
1731         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1732                 if (rx_queue->rx_skbuff[i]) {
1733                         dma_unmap_single(&priv->ofdev->dev,
1734                                         rxbdp->bufPtr, priv->rx_buffer_size,
1735                                         DMA_FROM_DEVICE);
1736                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1737                         rx_queue->rx_skbuff[i] = NULL;
1738                 }
1739                 rxbdp->lstatus = 0;
1740                 rxbdp->bufPtr = 0;
1741                 rxbdp++;
1742         }
1743         kfree(rx_queue->rx_skbuff);
1744 }
1745
1746 /* If there are any tx skbs or rx skbs still around, free them.
1747  * Then free tx_skbuff and rx_skbuff */
1748 static void free_skb_resources(struct gfar_private *priv)
1749 {
1750         struct gfar_priv_tx_q *tx_queue = NULL;
1751         struct gfar_priv_rx_q *rx_queue = NULL;
1752         int i;
1753
1754         /* Go through all the buffer descriptors and free their data buffers */
1755         for (i = 0; i < priv->num_tx_queues; i++) {
1756                 tx_queue = priv->tx_queue[i];
1757                 if(tx_queue->tx_skbuff)
1758                         free_skb_tx_queue(tx_queue);
1759         }
1760
1761         for (i = 0; i < priv->num_rx_queues; i++) {
1762                 rx_queue = priv->rx_queue[i];
1763                 if(rx_queue->rx_skbuff)
1764                         free_skb_rx_queue(rx_queue);
1765         }
1766
1767         dma_free_coherent(&priv->ofdev->dev,
1768                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1769                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1770                         priv->tx_queue[0]->tx_bd_base,
1771                         priv->tx_queue[0]->tx_bd_dma_base);
1772         skb_queue_purge(&priv->rx_recycle);
1773 }
1774
1775 void gfar_start(struct net_device *dev)
1776 {
1777         struct gfar_private *priv = netdev_priv(dev);
1778         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1779         u32 tempval;
1780         int i = 0;
1781
1782         /* Enable Rx and Tx in MACCFG1 */
1783         tempval = gfar_read(&regs->maccfg1);
1784         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1785         gfar_write(&regs->maccfg1, tempval);
1786
1787         /* Initialize DMACTRL to have WWR and WOP */
1788         tempval = gfar_read(&regs->dmactrl);
1789         tempval |= DMACTRL_INIT_SETTINGS;
1790         gfar_write(&regs->dmactrl, tempval);
1791
1792         /* Make sure we aren't stopped */
1793         tempval = gfar_read(&regs->dmactrl);
1794         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1795         gfar_write(&regs->dmactrl, tempval);
1796
1797         for (i = 0; i < priv->num_grps; i++) {
1798                 regs = priv->gfargrp[i].regs;
1799                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1800                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1801                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1802                 /* Unmask the interrupts we look for */
1803                 gfar_write(&regs->imask, IMASK_DEFAULT);
1804         }
1805
1806         dev->trans_start = jiffies; /* prevent tx timeout */
1807 }
1808
1809 void gfar_configure_coalescing(struct gfar_private *priv,
1810         unsigned long tx_mask, unsigned long rx_mask)
1811 {
1812         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1813         u32 __iomem *baddr;
1814         int i = 0;
1815
1816         /* Backward compatible case ---- even if we enable
1817          * multiple queues, there's only single reg to program
1818          */
1819         gfar_write(&regs->txic, 0);
1820         if(likely(priv->tx_queue[0]->txcoalescing))
1821                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1822
1823         gfar_write(&regs->rxic, 0);
1824         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1825                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1826
1827         if (priv->mode == MQ_MG_MODE) {
1828                 baddr = &regs->txic0;
1829                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1830                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1831                                 gfar_write(baddr + i, 0);
1832                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1833                         }
1834                 }
1835
1836                 baddr = &regs->rxic0;
1837                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1838                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1839                                 gfar_write(baddr + i, 0);
1840                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1841                         }
1842                 }
1843         }
1844 }
1845
1846 static int register_grp_irqs(struct gfar_priv_grp *grp)
1847 {
1848         struct gfar_private *priv = grp->priv;
1849         struct net_device *dev = priv->ndev;
1850         int err;
1851
1852         /* If the device has multiple interrupts, register for
1853          * them.  Otherwise, only register for the one */
1854         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1855                 /* Install our interrupt handlers for Error,
1856                  * Transmit, and Receive */
1857                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1858                                 grp->int_name_er,grp)) < 0) {
1859                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1860                                   grp->interruptError);
1861
1862                         goto err_irq_fail;
1863                 }
1864
1865                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1866                                 0, grp->int_name_tx, grp)) < 0) {
1867                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1868                                   grp->interruptTransmit);
1869                         goto tx_irq_fail;
1870                 }
1871
1872                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1873                                 grp->int_name_rx, grp)) < 0) {
1874                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1875                                   grp->interruptReceive);
1876                         goto rx_irq_fail;
1877                 }
1878         } else {
1879                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1880                                 grp->int_name_tx, grp)) < 0) {
1881                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1882                                   grp->interruptTransmit);
1883                         goto err_irq_fail;
1884                 }
1885         }
1886
1887         return 0;
1888
1889 rx_irq_fail:
1890         free_irq(grp->interruptTransmit, grp);
1891 tx_irq_fail:
1892         free_irq(grp->interruptError, grp);
1893 err_irq_fail:
1894         return err;
1895
1896 }
1897
1898 /* Bring the controller up and running */
1899 int startup_gfar(struct net_device *ndev)
1900 {
1901         struct gfar_private *priv = netdev_priv(ndev);
1902         struct gfar __iomem *regs = NULL;
1903         int err, i, j;
1904
1905         for (i = 0; i < priv->num_grps; i++) {
1906                 regs= priv->gfargrp[i].regs;
1907                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1908         }
1909
1910         regs= priv->gfargrp[0].regs;
1911         err = gfar_alloc_skb_resources(ndev);
1912         if (err)
1913                 return err;
1914
1915         gfar_init_mac(ndev);
1916
1917         for (i = 0; i < priv->num_grps; i++) {
1918                 err = register_grp_irqs(&priv->gfargrp[i]);
1919                 if (err) {
1920                         for (j = 0; j < i; j++)
1921                                 free_grp_irqs(&priv->gfargrp[j]);
1922                         goto irq_fail;
1923                 }
1924         }
1925
1926         /* Start the controller */
1927         gfar_start(ndev);
1928
1929         phy_start(priv->phydev);
1930
1931         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1932
1933         return 0;
1934
1935 irq_fail:
1936         free_skb_resources(priv);
1937         return err;
1938 }
1939
1940 /* Called when something needs to use the ethernet device */
1941 /* Returns 0 for success. */
1942 static int gfar_enet_open(struct net_device *dev)
1943 {
1944         struct gfar_private *priv = netdev_priv(dev);
1945         int err;
1946
1947         enable_napi(priv);
1948
1949         skb_queue_head_init(&priv->rx_recycle);
1950
1951         /* Initialize a bunch of registers */
1952         init_registers(dev);
1953
1954         gfar_set_mac_address(dev);
1955
1956         err = init_phy(dev);
1957
1958         if (err) {
1959                 disable_napi(priv);
1960                 return err;
1961         }
1962
1963         err = startup_gfar(dev);
1964         if (err) {
1965                 disable_napi(priv);
1966                 return err;
1967         }
1968
1969         netif_tx_start_all_queues(dev);
1970
1971         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1972
1973         return err;
1974 }
1975
1976 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1977 {
1978         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1979
1980         memset(fcb, 0, GMAC_FCB_LEN);
1981
1982         return fcb;
1983 }
1984
1985 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1986 {
1987         u8 flags = 0;
1988
1989         /* If we're here, it's a IP packet with a TCP or UDP
1990          * payload.  We set it to checksum, using a pseudo-header
1991          * we provide
1992          */
1993         flags = TXFCB_DEFAULT;
1994
1995         /* Tell the controller what the protocol is */
1996         /* And provide the already calculated phcs */
1997         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1998                 flags |= TXFCB_UDP;
1999                 fcb->phcs = udp_hdr(skb)->check;
2000         } else
2001                 fcb->phcs = tcp_hdr(skb)->check;
2002
2003         /* l3os is the distance between the start of the
2004          * frame (skb->data) and the start of the IP hdr.
2005          * l4os is the distance between the start of the
2006          * l3 hdr and the l4 hdr */
2007         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2008         fcb->l4os = skb_network_header_len(skb);
2009
2010         fcb->flags = flags;
2011 }
2012
2013 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2014 {
2015         fcb->flags |= TXFCB_VLN;
2016         fcb->vlctl = vlan_tx_tag_get(skb);
2017 }
2018
2019 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2020                                struct txbd8 *base, int ring_size)
2021 {
2022         struct txbd8 *new_bd = bdp + stride;
2023
2024         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2025 }
2026
2027 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2028                 int ring_size)
2029 {
2030         return skip_txbd(bdp, 1, base, ring_size);
2031 }
2032
2033 /* This is called by the kernel when a frame is ready for transmission. */
2034 /* It is pointed to by the dev->hard_start_xmit function pointer */
2035 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2036 {
2037         struct gfar_private *priv = netdev_priv(dev);
2038         struct gfar_priv_tx_q *tx_queue = NULL;
2039         struct netdev_queue *txq;
2040         struct gfar __iomem *regs = NULL;
2041         struct txfcb *fcb = NULL;
2042         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2043         u32 lstatus;
2044         int i, rq = 0, do_tstamp = 0;
2045         u32 bufaddr;
2046         unsigned long flags;
2047         unsigned int nr_frags, nr_txbds, length;
2048
2049         /*
2050          * TOE=1 frames larger than 2500 bytes may see excess delays
2051          * before start of transmission.
2052          */
2053         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2054                         skb->ip_summed == CHECKSUM_PARTIAL &&
2055                         skb->len > 2500)) {
2056                 int ret;
2057
2058                 ret = skb_checksum_help(skb);
2059                 if (ret)
2060                         return ret;
2061         }
2062
2063         rq = skb->queue_mapping;
2064         tx_queue = priv->tx_queue[rq];
2065         txq = netdev_get_tx_queue(dev, rq);
2066         base = tx_queue->tx_bd_base;
2067         regs = tx_queue->grp->regs;
2068
2069         /* check if time stamp should be generated */
2070         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2071                      priv->hwts_tx_en))
2072                 do_tstamp = 1;
2073
2074         /* make space for additional header when fcb is needed */
2075         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2076                         vlan_tx_tag_present(skb) ||
2077                         unlikely(do_tstamp)) &&
2078                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2079                 struct sk_buff *skb_new;
2080
2081                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2082                 if (!skb_new) {
2083                         dev->stats.tx_errors++;
2084                         kfree_skb(skb);
2085                         return NETDEV_TX_OK;
2086                 }
2087                 kfree_skb(skb);
2088                 skb = skb_new;
2089         }
2090
2091         /* total number of fragments in the SKB */
2092         nr_frags = skb_shinfo(skb)->nr_frags;
2093
2094         /* calculate the required number of TxBDs for this skb */
2095         if (unlikely(do_tstamp))
2096                 nr_txbds = nr_frags + 2;
2097         else
2098                 nr_txbds = nr_frags + 1;
2099
2100         /* check if there is space to queue this packet */
2101         if (nr_txbds > tx_queue->num_txbdfree) {
2102                 /* no space, stop the queue */
2103                 netif_tx_stop_queue(txq);
2104                 dev->stats.tx_fifo_errors++;
2105                 return NETDEV_TX_BUSY;
2106         }
2107
2108         /* Update transmit stats */
2109         tx_queue->stats.tx_bytes += skb->len;
2110         tx_queue->stats.tx_packets++;
2111
2112         txbdp = txbdp_start = tx_queue->cur_tx;
2113         lstatus = txbdp->lstatus;
2114
2115         /* Time stamp insertion requires one additional TxBD */
2116         if (unlikely(do_tstamp))
2117                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2118                                 tx_queue->tx_ring_size);
2119
2120         if (nr_frags == 0) {
2121                 if (unlikely(do_tstamp))
2122                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2123                                         TXBD_INTERRUPT);
2124                 else
2125                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2126         } else {
2127                 /* Place the fragment addresses and lengths into the TxBDs */
2128                 for (i = 0; i < nr_frags; i++) {
2129                         /* Point at the next BD, wrapping as needed */
2130                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2131
2132                         length = skb_shinfo(skb)->frags[i].size;
2133
2134                         lstatus = txbdp->lstatus | length |
2135                                 BD_LFLAG(TXBD_READY);
2136
2137                         /* Handle the last BD specially */
2138                         if (i == nr_frags - 1)
2139                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2140
2141                         bufaddr = dma_map_page(&priv->ofdev->dev,
2142                                         skb_shinfo(skb)->frags[i].page,
2143                                         skb_shinfo(skb)->frags[i].page_offset,
2144                                         length,
2145                                         DMA_TO_DEVICE);
2146
2147                         /* set the TxBD length and buffer pointer */
2148                         txbdp->bufPtr = bufaddr;
2149                         txbdp->lstatus = lstatus;
2150                 }
2151
2152                 lstatus = txbdp_start->lstatus;
2153         }
2154
2155         /* Set up checksumming */
2156         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2157                 fcb = gfar_add_fcb(skb);
2158                 /* as specified by errata */
2159                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2160                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2161                         __skb_pull(skb, GMAC_FCB_LEN);
2162                         skb_checksum_help(skb);
2163                 } else {
2164                         lstatus |= BD_LFLAG(TXBD_TOE);
2165                         gfar_tx_checksum(skb, fcb);
2166                 }
2167         }
2168
2169         if (vlan_tx_tag_present(skb)) {
2170                 if (unlikely(NULL == fcb)) {
2171                         fcb = gfar_add_fcb(skb);
2172                         lstatus |= BD_LFLAG(TXBD_TOE);
2173                 }
2174
2175                 gfar_tx_vlan(skb, fcb);
2176         }
2177
2178         /* Setup tx hardware time stamping if requested */
2179         if (unlikely(do_tstamp)) {
2180                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2181                 if (fcb == NULL)
2182                         fcb = gfar_add_fcb(skb);
2183                 fcb->ptp = 1;
2184                 lstatus |= BD_LFLAG(TXBD_TOE);
2185         }
2186
2187         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2188                         skb_headlen(skb), DMA_TO_DEVICE);
2189
2190         /*
2191          * If time stamping is requested one additional TxBD must be set up. The
2192          * first TxBD points to the FCB and must have a data length of
2193          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2194          * the full frame length.
2195          */
2196         if (unlikely(do_tstamp)) {
2197                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2198                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2199                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2200                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2201         } else {
2202                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2203         }
2204
2205         /*
2206          * We can work in parallel with gfar_clean_tx_ring(), except
2207          * when modifying num_txbdfree. Note that we didn't grab the lock
2208          * when we were reading the num_txbdfree and checking for available
2209          * space, that's because outside of this function it can only grow,
2210          * and once we've got needed space, it cannot suddenly disappear.
2211          *
2212          * The lock also protects us from gfar_error(), which can modify
2213          * regs->tstat and thus retrigger the transfers, which is why we
2214          * also must grab the lock before setting ready bit for the first
2215          * to be transmitted BD.
2216          */
2217         spin_lock_irqsave(&tx_queue->txlock, flags);
2218
2219         /*
2220          * The powerpc-specific eieio() is used, as wmb() has too strong
2221          * semantics (it requires synchronization between cacheable and
2222          * uncacheable mappings, which eieio doesn't provide and which we
2223          * don't need), thus requiring a more expensive sync instruction.  At
2224          * some point, the set of architecture-independent barrier functions
2225          * should be expanded to include weaker barriers.
2226          */
2227         eieio();
2228
2229         txbdp_start->lstatus = lstatus;
2230
2231         eieio(); /* force lstatus write before tx_skbuff */
2232
2233         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2234
2235         /* Update the current skb pointer to the next entry we will use
2236          * (wrapping if necessary) */
2237         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2238                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2239
2240         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2241
2242         /* reduce TxBD free count */
2243         tx_queue->num_txbdfree -= (nr_txbds);
2244
2245         /* If the next BD still needs to be cleaned up, then the bds
2246            are full.  We need to tell the kernel to stop sending us stuff. */
2247         if (!tx_queue->num_txbdfree) {
2248                 netif_tx_stop_queue(txq);
2249
2250                 dev->stats.tx_fifo_errors++;
2251         }
2252
2253         /* Tell the DMA to go go go */
2254         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2255
2256         /* Unlock priv */
2257         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2258
2259         return NETDEV_TX_OK;
2260 }
2261
2262 /* Stops the kernel queue, and halts the controller */
2263 static int gfar_close(struct net_device *dev)
2264 {
2265         struct gfar_private *priv = netdev_priv(dev);
2266
2267         disable_napi(priv);
2268
2269         cancel_work_sync(&priv->reset_task);
2270         stop_gfar(dev);
2271
2272         /* Disconnect from the PHY */
2273         phy_disconnect(priv->phydev);
2274         priv->phydev = NULL;
2275
2276         netif_tx_stop_all_queues(dev);
2277
2278         return 0;
2279 }
2280
2281 /* Changes the mac address if the controller is not running. */
2282 static int gfar_set_mac_address(struct net_device *dev)
2283 {
2284         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2285
2286         return 0;
2287 }
2288
2289
2290 /* Enables and disables VLAN insertion/extraction */
2291 static void gfar_vlan_rx_register(struct net_device *dev,
2292                 struct vlan_group *grp)
2293 {
2294         struct gfar_private *priv = netdev_priv(dev);
2295         struct gfar __iomem *regs = NULL;
2296         unsigned long flags;
2297         u32 tempval;
2298
2299         regs = priv->gfargrp[0].regs;
2300         local_irq_save(flags);
2301         lock_rx_qs(priv);
2302
2303         priv->vlgrp = grp;
2304
2305         if (grp) {
2306                 /* Enable VLAN tag insertion */
2307                 tempval = gfar_read(&regs->tctrl);
2308                 tempval |= TCTRL_VLINS;
2309
2310                 gfar_write(&regs->tctrl, tempval);
2311
2312                 /* Enable VLAN tag extraction */
2313                 tempval = gfar_read(&regs->rctrl);
2314                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2315                 gfar_write(&regs->rctrl, tempval);
2316         } else {
2317                 /* Disable VLAN tag insertion */
2318                 tempval = gfar_read(&regs->tctrl);
2319                 tempval &= ~TCTRL_VLINS;
2320                 gfar_write(&regs->tctrl, tempval);
2321
2322                 /* Disable VLAN tag extraction */
2323                 tempval = gfar_read(&regs->rctrl);
2324                 tempval &= ~RCTRL_VLEX;
2325                 /* If parse is no longer required, then disable parser */
2326                 if (tempval & RCTRL_REQ_PARSER)
2327                         tempval |= RCTRL_PRSDEP_INIT;
2328                 else
2329                         tempval &= ~RCTRL_PRSDEP_INIT;
2330                 gfar_write(&regs->rctrl, tempval);
2331         }
2332
2333         gfar_change_mtu(dev, dev->mtu);
2334
2335         unlock_rx_qs(priv);
2336         local_irq_restore(flags);
2337 }
2338
2339 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2340 {
2341         int tempsize, tempval;
2342         struct gfar_private *priv = netdev_priv(dev);
2343         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2344         int oldsize = priv->rx_buffer_size;
2345         int frame_size = new_mtu + ETH_HLEN;
2346
2347         if (priv->vlgrp)
2348                 frame_size += VLAN_HLEN;
2349
2350         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2351                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2352                 return -EINVAL;
2353         }
2354
2355         if (gfar_uses_fcb(priv))
2356                 frame_size += GMAC_FCB_LEN;
2357
2358         frame_size += priv->padding;
2359
2360         tempsize =
2361             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2362             INCREMENTAL_BUFFER_SIZE;
2363
2364         /* Only stop and start the controller if it isn't already
2365          * stopped, and we changed something */
2366         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2367                 stop_gfar(dev);
2368
2369         priv->rx_buffer_size = tempsize;
2370
2371         dev->mtu = new_mtu;
2372
2373         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2374         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2375
2376         /* If the mtu is larger than the max size for standard
2377          * ethernet frames (ie, a jumbo frame), then set maccfg2
2378          * to allow huge frames, and to check the length */
2379         tempval = gfar_read(&regs->maccfg2);
2380
2381         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2382                         gfar_has_errata(priv, GFAR_ERRATA_74))
2383                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2384         else
2385                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2386
2387         gfar_write(&regs->maccfg2, tempval);
2388
2389         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2390                 startup_gfar(dev);
2391
2392         return 0;
2393 }
2394
2395 /* gfar_reset_task gets scheduled when a packet has not been
2396  * transmitted after a set amount of time.
2397  * For now, assume that clearing out all the structures, and
2398  * starting over will fix the problem.
2399  */
2400 static void gfar_reset_task(struct work_struct *work)
2401 {
2402         struct gfar_private *priv = container_of(work, struct gfar_private,
2403                         reset_task);
2404         struct net_device *dev = priv->ndev;
2405
2406         if (dev->flags & IFF_UP) {
2407                 netif_tx_stop_all_queues(dev);
2408                 stop_gfar(dev);
2409                 startup_gfar(dev);
2410                 netif_tx_start_all_queues(dev);
2411         }
2412
2413         netif_tx_schedule_all(dev);
2414 }
2415
2416 static void gfar_timeout(struct net_device *dev)
2417 {
2418         struct gfar_private *priv = netdev_priv(dev);
2419
2420         dev->stats.tx_errors++;
2421         schedule_work(&priv->reset_task);
2422 }
2423
2424 static void gfar_align_skb(struct sk_buff *skb)
2425 {
2426         /* We need the data buffer to be aligned properly.  We will reserve
2427          * as many bytes as needed to align the data properly
2428          */
2429         skb_reserve(skb, RXBUF_ALIGNMENT -
2430                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2431 }
2432
2433 /* Interrupt Handler for Transmit complete */
2434 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2435 {
2436         struct net_device *dev = tx_queue->dev;
2437         struct gfar_private *priv = netdev_priv(dev);
2438         struct gfar_priv_rx_q *rx_queue = NULL;
2439         struct txbd8 *bdp, *next = NULL;
2440         struct txbd8 *lbdp = NULL;
2441         struct txbd8 *base = tx_queue->tx_bd_base;
2442         struct sk_buff *skb;
2443         int skb_dirtytx;
2444         int tx_ring_size = tx_queue->tx_ring_size;
2445         int frags = 0, nr_txbds = 0;
2446         int i;
2447         int howmany = 0;
2448         u32 lstatus;
2449         size_t buflen;
2450
2451         rx_queue = priv->rx_queue[tx_queue->qindex];
2452         bdp = tx_queue->dirty_tx;
2453         skb_dirtytx = tx_queue->skb_dirtytx;
2454
2455         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2456                 unsigned long flags;
2457
2458                 frags = skb_shinfo(skb)->nr_frags;
2459
2460                 /*
2461                  * When time stamping, one additional TxBD must be freed.
2462                  * Also, we need to dma_unmap_single() the TxPAL.
2463                  */
2464                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2465                         nr_txbds = frags + 2;
2466                 else
2467                         nr_txbds = frags + 1;
2468
2469                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2470
2471                 lstatus = lbdp->lstatus;
2472
2473                 /* Only clean completed frames */
2474                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2475                                 (lstatus & BD_LENGTH_MASK))
2476                         break;
2477
2478                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2479                         next = next_txbd(bdp, base, tx_ring_size);
2480                         buflen = next->length + GMAC_FCB_LEN;
2481                 } else
2482                         buflen = bdp->length;
2483
2484                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2485                                 buflen, DMA_TO_DEVICE);
2486
2487                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2488                         struct skb_shared_hwtstamps shhwtstamps;
2489                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2490                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2491                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2492                         skb_tstamp_tx(skb, &shhwtstamps);
2493                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2494                         bdp = next;
2495                 }
2496
2497                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2498                 bdp = next_txbd(bdp, base, tx_ring_size);
2499
2500                 for (i = 0; i < frags; i++) {
2501                         dma_unmap_page(&priv->ofdev->dev,
2502                                         bdp->bufPtr,
2503                                         bdp->length,
2504                                         DMA_TO_DEVICE);
2505                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2506                         bdp = next_txbd(bdp, base, tx_ring_size);
2507                 }
2508
2509                 /*
2510                  * If there's room in the queue (limit it to rx_buffer_size)
2511                  * we add this skb back into the pool, if it's the right size
2512                  */
2513                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2514                                 skb_recycle_check(skb, priv->rx_buffer_size +
2515                                         RXBUF_ALIGNMENT)) {
2516                         gfar_align_skb(skb);
2517                         skb_queue_head(&priv->rx_recycle, skb);
2518                 } else
2519                         dev_kfree_skb_any(skb);
2520
2521                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2522
2523                 skb_dirtytx = (skb_dirtytx + 1) &
2524                         TX_RING_MOD_MASK(tx_ring_size);
2525
2526                 howmany++;
2527                 spin_lock_irqsave(&tx_queue->txlock, flags);
2528                 tx_queue->num_txbdfree += nr_txbds;
2529                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2530         }
2531
2532         /* If we freed a buffer, we can restart transmission, if necessary */
2533         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2534                 netif_wake_subqueue(dev, tx_queue->qindex);
2535
2536         /* Update dirty indicators */
2537         tx_queue->skb_dirtytx = skb_dirtytx;
2538         tx_queue->dirty_tx = bdp;
2539
2540         return howmany;
2541 }
2542
2543 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2544 {
2545         unsigned long flags;
2546
2547         spin_lock_irqsave(&gfargrp->grplock, flags);
2548         if (napi_schedule_prep(&gfargrp->napi)) {
2549                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2550                 __napi_schedule(&gfargrp->napi);
2551         } else {
2552                 /*
2553                  * Clear IEVENT, so interrupts aren't called again
2554                  * because of the packets that have already arrived.
2555                  */
2556                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2557         }
2558         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2559
2560 }
2561
2562 /* Interrupt Handler for Transmit complete */
2563 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2564 {
2565         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2566         return IRQ_HANDLED;
2567 }
2568
2569 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2570                 struct sk_buff *skb)
2571 {
2572         struct net_device *dev = rx_queue->dev;
2573         struct gfar_private *priv = netdev_priv(dev);
2574         dma_addr_t buf;
2575
2576         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2577                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2578         gfar_init_rxbdp(rx_queue, bdp, buf);
2579 }
2580
2581 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2582 {
2583         struct gfar_private *priv = netdev_priv(dev);
2584         struct sk_buff *skb = NULL;
2585
2586         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2587         if (!skb)
2588                 return NULL;
2589
2590         gfar_align_skb(skb);
2591
2592         return skb;
2593 }
2594
2595 struct sk_buff * gfar_new_skb(struct net_device *dev)
2596 {
2597         struct gfar_private *priv = netdev_priv(dev);
2598         struct sk_buff *skb = NULL;
2599
2600         skb = skb_dequeue(&priv->rx_recycle);
2601         if (!skb)
2602                 skb = gfar_alloc_skb(dev);
2603
2604         return skb;
2605 }
2606
2607 static inline void count_errors(unsigned short status, struct net_device *dev)
2608 {
2609         struct gfar_private *priv = netdev_priv(dev);
2610         struct net_device_stats *stats = &dev->stats;
2611         struct gfar_extra_stats *estats = &priv->extra_stats;
2612
2613         /* If the packet was truncated, none of the other errors
2614          * matter */
2615         if (status & RXBD_TRUNCATED) {
2616                 stats->rx_length_errors++;
2617
2618                 estats->rx_trunc++;
2619
2620                 return;
2621         }
2622         /* Count the errors, if there were any */
2623         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2624                 stats->rx_length_errors++;
2625
2626                 if (status & RXBD_LARGE)
2627                         estats->rx_large++;
2628                 else
2629                         estats->rx_short++;
2630         }
2631         if (status & RXBD_NONOCTET) {
2632                 stats->rx_frame_errors++;
2633                 estats->rx_nonoctet++;
2634         }
2635         if (status & RXBD_CRCERR) {
2636                 estats->rx_crcerr++;
2637                 stats->rx_crc_errors++;
2638         }
2639         if (status & RXBD_OVERRUN) {
2640                 estats->rx_overrun++;
2641                 stats->rx_crc_errors++;
2642         }
2643 }
2644
2645 irqreturn_t gfar_receive(int irq, void *grp_id)
2646 {
2647         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2648         return IRQ_HANDLED;
2649 }
2650
2651 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2652 {
2653         /* If valid headers were found, and valid sums
2654          * were verified, then we tell the kernel that no
2655          * checksumming is necessary.  Otherwise, it is */
2656         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2657                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2658         else
2659                 skb_checksum_none_assert(skb);
2660 }
2661
2662
2663 /* gfar_process_frame() -- handle one incoming packet if skb
2664  * isn't NULL.  */
2665 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2666                               int amount_pull)
2667 {
2668         struct gfar_private *priv = netdev_priv(dev);
2669         struct rxfcb *fcb = NULL;
2670
2671         int ret;
2672
2673         /* fcb is at the beginning if exists */
2674         fcb = (struct rxfcb *)skb->data;
2675
2676         /* Remove the FCB from the skb */
2677         /* Remove the padded bytes, if there are any */
2678         if (amount_pull) {
2679                 skb_record_rx_queue(skb, fcb->rq);
2680                 skb_pull(skb, amount_pull);
2681         }
2682
2683         /* Get receive timestamp from the skb */
2684         if (priv->hwts_rx_en) {
2685                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2686                 u64 *ns = (u64 *) skb->data;
2687                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2688                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2689         }
2690
2691         if (priv->padding)
2692                 skb_pull(skb, priv->padding);
2693
2694         if (dev->features & NETIF_F_RXCSUM)
2695                 gfar_rx_checksum(skb, fcb);
2696
2697         /* Tell the skb what kind of packet this is */
2698         skb->protocol = eth_type_trans(skb, dev);
2699
2700         /* Send the packet up the stack */
2701         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2702                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2703         else
2704                 ret = netif_receive_skb(skb);
2705
2706         if (NET_RX_DROP == ret)
2707                 priv->extra_stats.kernel_dropped++;
2708
2709         return 0;
2710 }
2711
2712 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2713  *   until the budget/quota has been reached. Returns the number
2714  *   of frames handled
2715  */
2716 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2717 {
2718         struct net_device *dev = rx_queue->dev;
2719         struct rxbd8 *bdp, *base;
2720         struct sk_buff *skb;
2721         int pkt_len;
2722         int amount_pull;
2723         int howmany = 0;
2724         struct gfar_private *priv = netdev_priv(dev);
2725
2726         /* Get the first full descriptor */
2727         bdp = rx_queue->cur_rx;
2728         base = rx_queue->rx_bd_base;
2729
2730         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2731
2732         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2733                 struct sk_buff *newskb;
2734                 rmb();
2735
2736                 /* Add another skb for the future */
2737                 newskb = gfar_new_skb(dev);
2738
2739                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2740
2741                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2742                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2743
2744                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2745                                 bdp->length > priv->rx_buffer_size))
2746                         bdp->status = RXBD_LARGE;
2747
2748                 /* We drop the frame if we failed to allocate a new buffer */
2749                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2750                                  bdp->status & RXBD_ERR)) {
2751                         count_errors(bdp->status, dev);
2752
2753                         if (unlikely(!newskb))
2754                                 newskb = skb;
2755                         else if (skb)
2756                                 skb_queue_head(&priv->rx_recycle, skb);
2757                 } else {
2758                         /* Increment the number of packets */
2759                         rx_queue->stats.rx_packets++;
2760                         howmany++;
2761
2762                         if (likely(skb)) {
2763                                 pkt_len = bdp->length - ETH_FCS_LEN;
2764                                 /* Remove the FCS from the packet length */
2765                                 skb_put(skb, pkt_len);
2766                                 rx_queue->stats.rx_bytes += pkt_len;
2767                                 skb_record_rx_queue(skb, rx_queue->qindex);
2768                                 gfar_process_frame(dev, skb, amount_pull);
2769
2770                         } else {
2771                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2772                                 rx_queue->stats.rx_dropped++;
2773                                 priv->extra_stats.rx_skbmissing++;
2774                         }
2775
2776                 }
2777
2778                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2779
2780                 /* Setup the new bdp */
2781                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2782
2783                 /* Update to the next pointer */
2784                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2785
2786                 /* update to point at the next skb */
2787                 rx_queue->skb_currx =
2788                     (rx_queue->skb_currx + 1) &
2789                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2790         }
2791
2792         /* Update the current rxbd pointer to be the next one */
2793         rx_queue->cur_rx = bdp;
2794
2795         return howmany;
2796 }
2797
2798 static int gfar_poll(struct napi_struct *napi, int budget)
2799 {
2800         struct gfar_priv_grp *gfargrp = container_of(napi,
2801                         struct gfar_priv_grp, napi);
2802         struct gfar_private *priv = gfargrp->priv;
2803         struct gfar __iomem *regs = gfargrp->regs;
2804         struct gfar_priv_tx_q *tx_queue = NULL;
2805         struct gfar_priv_rx_q *rx_queue = NULL;
2806         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2807         int tx_cleaned = 0, i, left_over_budget = budget;
2808         unsigned long serviced_queues = 0;
2809         int num_queues = 0;
2810
2811         num_queues = gfargrp->num_rx_queues;
2812         budget_per_queue = budget/num_queues;
2813
2814         /* Clear IEVENT, so interrupts aren't called again
2815          * because of the packets that have already arrived */
2816         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2817
2818         while (num_queues && left_over_budget) {
2819
2820                 budget_per_queue = left_over_budget/num_queues;
2821                 left_over_budget = 0;
2822
2823                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2824                         if (test_bit(i, &serviced_queues))
2825                                 continue;
2826                         rx_queue = priv->rx_queue[i];
2827                         tx_queue = priv->tx_queue[rx_queue->qindex];
2828
2829                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2830                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2831                                                         budget_per_queue);
2832                         rx_cleaned += rx_cleaned_per_queue;
2833                         if(rx_cleaned_per_queue < budget_per_queue) {
2834                                 left_over_budget = left_over_budget +
2835                                         (budget_per_queue - rx_cleaned_per_queue);
2836                                 set_bit(i, &serviced_queues);
2837                                 num_queues--;
2838                         }
2839                 }
2840         }
2841
2842         if (tx_cleaned)
2843                 return budget;
2844
2845         if (rx_cleaned < budget) {
2846                 napi_complete(napi);
2847
2848                 /* Clear the halt bit in RSTAT */
2849                 gfar_write(&regs->rstat, gfargrp->rstat);
2850
2851                 gfar_write(&regs->imask, IMASK_DEFAULT);
2852
2853                 /* If we are coalescing interrupts, update the timer */
2854                 /* Otherwise, clear it */
2855                 gfar_configure_coalescing(priv,
2856                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2857         }
2858
2859         return rx_cleaned;
2860 }
2861
2862 #ifdef CONFIG_NET_POLL_CONTROLLER
2863 /*
2864  * Polling 'interrupt' - used by things like netconsole to send skbs
2865  * without having to re-enable interrupts. It's not called while
2866  * the interrupt routine is executing.
2867  */
2868 static void gfar_netpoll(struct net_device *dev)
2869 {
2870         struct gfar_private *priv = netdev_priv(dev);
2871         int i = 0;
2872
2873         /* If the device has multiple interrupts, run tx/rx */
2874         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2875                 for (i = 0; i < priv->num_grps; i++) {
2876                         disable_irq(priv->gfargrp[i].interruptTransmit);
2877                         disable_irq(priv->gfargrp[i].interruptReceive);
2878                         disable_irq(priv->gfargrp[i].interruptError);
2879                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2880                                                 &priv->gfargrp[i]);
2881                         enable_irq(priv->gfargrp[i].interruptError);
2882                         enable_irq(priv->gfargrp[i].interruptReceive);
2883                         enable_irq(priv->gfargrp[i].interruptTransmit);
2884                 }
2885         } else {
2886                 for (i = 0; i < priv->num_grps; i++) {
2887                         disable_irq(priv->gfargrp[i].interruptTransmit);
2888                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2889                                                 &priv->gfargrp[i]);
2890                         enable_irq(priv->gfargrp[i].interruptTransmit);
2891                 }
2892         }
2893 }
2894 #endif
2895
2896 /* The interrupt handler for devices with one interrupt */
2897 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2898 {
2899         struct gfar_priv_grp *gfargrp = grp_id;
2900
2901         /* Save ievent for future reference */
2902         u32 events = gfar_read(&gfargrp->regs->ievent);
2903
2904         /* Check for reception */
2905         if (events & IEVENT_RX_MASK)
2906                 gfar_receive(irq, grp_id);
2907
2908         /* Check for transmit completion */
2909         if (events & IEVENT_TX_MASK)
2910                 gfar_transmit(irq, grp_id);
2911
2912         /* Check for errors */
2913         if (events & IEVENT_ERR_MASK)
2914                 gfar_error(irq, grp_id);
2915
2916         return IRQ_HANDLED;
2917 }
2918
2919 /* Called every time the controller might need to be made
2920  * aware of new link state.  The PHY code conveys this
2921  * information through variables in the phydev structure, and this
2922  * function converts those variables into the appropriate
2923  * register values, and can bring down the device if needed.
2924  */
2925 static void adjust_link(struct net_device *dev)
2926 {
2927         struct gfar_private *priv = netdev_priv(dev);
2928         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2929         unsigned long flags;
2930         struct phy_device *phydev = priv->phydev;
2931         int new_state = 0;
2932
2933         local_irq_save(flags);
2934         lock_tx_qs(priv);
2935
2936         if (phydev->link) {
2937                 u32 tempval = gfar_read(&regs->maccfg2);
2938                 u32 ecntrl = gfar_read(&regs->ecntrl);
2939
2940                 /* Now we make sure that we can be in full duplex mode.
2941                  * If not, we operate in half-duplex mode. */
2942                 if (phydev->duplex != priv->oldduplex) {
2943                         new_state = 1;
2944                         if (!(phydev->duplex))
2945                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2946                         else
2947                                 tempval |= MACCFG2_FULL_DUPLEX;
2948
2949                         priv->oldduplex = phydev->duplex;
2950                 }
2951
2952                 if (phydev->speed != priv->oldspeed) {
2953                         new_state = 1;
2954                         switch (phydev->speed) {
2955                         case 1000:
2956                                 tempval =
2957                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2958
2959                                 ecntrl &= ~(ECNTRL_R100);
2960                                 break;
2961                         case 100:
2962                         case 10:
2963                                 tempval =
2964                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2965
2966                                 /* Reduced mode distinguishes
2967                                  * between 10 and 100 */
2968                                 if (phydev->speed == SPEED_100)
2969                                         ecntrl |= ECNTRL_R100;
2970                                 else
2971                                         ecntrl &= ~(ECNTRL_R100);
2972                                 break;
2973                         default:
2974                                 netif_warn(priv, link, dev,
2975                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2976                                            phydev->speed);
2977                                 break;
2978                         }
2979
2980                         priv->oldspeed = phydev->speed;
2981                 }
2982
2983                 gfar_write(&regs->maccfg2, tempval);
2984                 gfar_write(&regs->ecntrl, ecntrl);
2985
2986                 if (!priv->oldlink) {
2987                         new_state = 1;
2988                         priv->oldlink = 1;
2989                 }
2990         } else if (priv->oldlink) {
2991                 new_state = 1;
2992                 priv->oldlink = 0;
2993                 priv->oldspeed = 0;
2994                 priv->oldduplex = -1;
2995         }
2996
2997         if (new_state && netif_msg_link(priv))
2998                 phy_print_status(phydev);
2999         unlock_tx_qs(priv);
3000         local_irq_restore(flags);
3001 }
3002
3003 /* Update the hash table based on the current list of multicast
3004  * addresses we subscribe to.  Also, change the promiscuity of
3005  * the device based on the flags (this function is called
3006  * whenever dev->flags is changed */
3007 static void gfar_set_multi(struct net_device *dev)
3008 {
3009         struct netdev_hw_addr *ha;
3010         struct gfar_private *priv = netdev_priv(dev);
3011         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3012         u32 tempval;
3013
3014         if (dev->flags & IFF_PROMISC) {
3015                 /* Set RCTRL to PROM */
3016                 tempval = gfar_read(&regs->rctrl);
3017                 tempval |= RCTRL_PROM;
3018                 gfar_write(&regs->rctrl, tempval);
3019         } else {
3020                 /* Set RCTRL to not PROM */
3021                 tempval = gfar_read(&regs->rctrl);
3022                 tempval &= ~(RCTRL_PROM);
3023                 gfar_write(&regs->rctrl, tempval);
3024         }
3025
3026         if (dev->flags & IFF_ALLMULTI) {
3027                 /* Set the hash to rx all multicast frames */
3028                 gfar_write(&regs->igaddr0, 0xffffffff);
3029                 gfar_write(&regs->igaddr1, 0xffffffff);
3030                 gfar_write(&regs->igaddr2, 0xffffffff);
3031                 gfar_write(&regs->igaddr3, 0xffffffff);
3032                 gfar_write(&regs->igaddr4, 0xffffffff);
3033                 gfar_write(&regs->igaddr5, 0xffffffff);
3034                 gfar_write(&regs->igaddr6, 0xffffffff);
3035                 gfar_write(&regs->igaddr7, 0xffffffff);
3036                 gfar_write(&regs->gaddr0, 0xffffffff);
3037                 gfar_write(&regs->gaddr1, 0xffffffff);
3038                 gfar_write(&regs->gaddr2, 0xffffffff);
3039                 gfar_write(&regs->gaddr3, 0xffffffff);
3040                 gfar_write(&regs->gaddr4, 0xffffffff);
3041                 gfar_write(&regs->gaddr5, 0xffffffff);
3042                 gfar_write(&regs->gaddr6, 0xffffffff);
3043                 gfar_write(&regs->gaddr7, 0xffffffff);
3044         } else {
3045                 int em_num;
3046                 int idx;
3047
3048                 /* zero out the hash */
3049                 gfar_write(&regs->igaddr0, 0x0);
3050                 gfar_write(&regs->igaddr1, 0x0);
3051                 gfar_write(&regs->igaddr2, 0x0);
3052                 gfar_write(&regs->igaddr3, 0x0);
3053                 gfar_write(&regs->igaddr4, 0x0);
3054                 gfar_write(&regs->igaddr5, 0x0);
3055                 gfar_write(&regs->igaddr6, 0x0);
3056                 gfar_write(&regs->igaddr7, 0x0);
3057                 gfar_write(&regs->gaddr0, 0x0);
3058                 gfar_write(&regs->gaddr1, 0x0);
3059                 gfar_write(&regs->gaddr2, 0x0);
3060                 gfar_write(&regs->gaddr3, 0x0);
3061                 gfar_write(&regs->gaddr4, 0x0);
3062                 gfar_write(&regs->gaddr5, 0x0);
3063                 gfar_write(&regs->gaddr6, 0x0);
3064                 gfar_write(&regs->gaddr7, 0x0);
3065
3066                 /* If we have extended hash tables, we need to
3067                  * clear the exact match registers to prepare for
3068                  * setting them */
3069                 if (priv->extended_hash) {
3070                         em_num = GFAR_EM_NUM + 1;
3071                         gfar_clear_exact_match(dev);
3072                         idx = 1;
3073                 } else {
3074                         idx = 0;
3075                         em_num = 0;
3076                 }
3077
3078                 if (netdev_mc_empty(dev))
3079                         return;
3080
3081                 /* Parse the list, and set the appropriate bits */
3082                 netdev_for_each_mc_addr(ha, dev) {
3083                         if (idx < em_num) {
3084                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3085                                 idx++;
3086                         } else
3087                                 gfar_set_hash_for_addr(dev, ha->addr);
3088                 }
3089         }
3090 }
3091
3092
3093 /* Clears each of the exact match registers to zero, so they
3094  * don't interfere with normal reception */
3095 static void gfar_clear_exact_match(struct net_device *dev)
3096 {
3097         int idx;
3098         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3099
3100         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3101                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3102 }
3103
3104 /* Set the appropriate hash bit for the given addr */
3105 /* The algorithm works like so:
3106  * 1) Take the Destination Address (ie the multicast address), and
3107  * do a CRC on it (little endian), and reverse the bits of the
3108  * result.
3109  * 2) Use the 8 most significant bits as a hash into a 256-entry
3110  * table.  The table is controlled through 8 32-bit registers:
3111  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3112  * gaddr7.  This means that the 3 most significant bits in the
3113  * hash index which gaddr register to use, and the 5 other bits
3114  * indicate which bit (assuming an IBM numbering scheme, which
3115  * for PowerPC (tm) is usually the case) in the register holds
3116  * the entry. */
3117 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3118 {
3119         u32 tempval;
3120         struct gfar_private *priv = netdev_priv(dev);
3121         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3122         int width = priv->hash_width;
3123         u8 whichbit = (result >> (32 - width)) & 0x1f;
3124         u8 whichreg = result >> (32 - width + 5);
3125         u32 value = (1 << (31-whichbit));
3126
3127         tempval = gfar_read(priv->hash_regs[whichreg]);
3128         tempval |= value;
3129         gfar_write(priv->hash_regs[whichreg], tempval);
3130 }
3131
3132
3133 /* There are multiple MAC Address register pairs on some controllers
3134  * This function sets the numth pair to a given address
3135  */
3136 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3137                                   const u8 *addr)
3138 {
3139         struct gfar_private *priv = netdev_priv(dev);
3140         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3141         int idx;
3142         char tmpbuf[MAC_ADDR_LEN];
3143         u32 tempval;
3144         u32 __iomem *macptr = &regs->macstnaddr1;
3145
3146         macptr += num*2;
3147
3148         /* Now copy it into the mac registers backwards, cuz */
3149         /* little endian is silly */
3150         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3151                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3152
3153         gfar_write(macptr, *((u32 *) (tmpbuf)));
3154
3155         tempval = *((u32 *) (tmpbuf + 4));
3156
3157         gfar_write(macptr+1, tempval);
3158 }
3159
3160 /* GFAR error interrupt handler */
3161 static irqreturn_t gfar_error(int irq, void *grp_id)
3162 {
3163         struct gfar_priv_grp *gfargrp = grp_id;
3164         struct gfar __iomem *regs = gfargrp->regs;
3165         struct gfar_private *priv= gfargrp->priv;
3166         struct net_device *dev = priv->ndev;
3167
3168         /* Save ievent for future reference */
3169         u32 events = gfar_read(&regs->ievent);
3170
3171         /* Clear IEVENT */
3172         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3173
3174         /* Magic Packet is not an error. */
3175         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3176             (events & IEVENT_MAG))
3177                 events &= ~IEVENT_MAG;
3178
3179         /* Hmm... */
3180         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3181                 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3182                            events, gfar_read(&regs->imask));
3183
3184         /* Update the error counters */
3185         if (events & IEVENT_TXE) {
3186                 dev->stats.tx_errors++;
3187
3188                 if (events & IEVENT_LC)
3189                         dev->stats.tx_window_errors++;
3190                 if (events & IEVENT_CRL)
3191                         dev->stats.tx_aborted_errors++;
3192                 if (events & IEVENT_XFUN) {
3193                         unsigned long flags;
3194
3195                         netif_dbg(priv, tx_err, dev,
3196                                   "TX FIFO underrun, packet dropped\n");
3197                         dev->stats.tx_dropped++;
3198                         priv->extra_stats.tx_underrun++;
3199
3200                         local_irq_save(flags);
3201                         lock_tx_qs(priv);
3202
3203                         /* Reactivate the Tx Queues */
3204                         gfar_write(&regs->tstat, gfargrp->tstat);
3205
3206                         unlock_tx_qs(priv);
3207                         local_irq_restore(flags);
3208                 }
3209                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3210         }
3211         if (events & IEVENT_BSY) {
3212                 dev->stats.rx_errors++;
3213                 priv->extra_stats.rx_bsy++;
3214
3215                 gfar_receive(irq, grp_id);
3216
3217                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3218                           gfar_read(&regs->rstat));
3219         }
3220         if (events & IEVENT_BABR) {
3221                 dev->stats.rx_errors++;
3222                 priv->extra_stats.rx_babr++;
3223
3224                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3225         }
3226         if (events & IEVENT_EBERR) {
3227                 priv->extra_stats.eberr++;
3228                 netif_dbg(priv, rx_err, dev, "bus error\n");
3229         }
3230         if (events & IEVENT_RXC)
3231                 netif_dbg(priv, rx_status, dev, "control frame\n");
3232
3233         if (events & IEVENT_BABT) {
3234                 priv->extra_stats.tx_babt++;
3235                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3236         }
3237         return IRQ_HANDLED;
3238 }
3239
3240 static struct of_device_id gfar_match[] =
3241 {
3242         {
3243                 .type = "network",
3244                 .compatible = "gianfar",
3245         },
3246         {
3247                 .compatible = "fsl,etsec2",
3248         },
3249         {},
3250 };
3251 MODULE_DEVICE_TABLE(of, gfar_match);
3252
3253 /* Structure for a device driver */
3254 static struct platform_driver gfar_driver = {
3255         .driver = {
3256                 .name = "fsl-gianfar",
3257                 .owner = THIS_MODULE,
3258                 .pm = GFAR_PM_OPS,
3259                 .of_match_table = gfar_match,
3260         },
3261         .probe = gfar_probe,
3262         .remove = gfar_remove,
3263 };
3264
3265 static int __init gfar_init(void)
3266 {
3267         return platform_driver_register(&gfar_driver);
3268 }
3269
3270 static void __exit gfar_exit(void)
3271 {
3272         platform_driver_unregister(&gfar_driver);
3273 }
3274
3275 module_init(gfar_init);
3276 module_exit(gfar_exit);
3277