drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit.  Without NAPI, the packet(s) will be handled
  48  *  immediately.  Both methods will start at the last known empty
  49  *  descriptor, and process every subsequent descriptor until there
  50  *  are none left with data (NAPI will stop after a set number of
  51  *  packets to give time to other tasks, but will eventually
  52  *  process all the packets).  The data arrives inside a
  53  *  pre-allocated skb, and so after the skb is passed up to the
  54  *  stack, a new skb must be allocated, and the address field in
  55  *  the buffer descriptor must be updated to indicate this new
  56  *  skb.
  57  *
  58  *  When the kernel requests that a packet be transmitted, the
  59  *  driver starts where it left off last time, and points the
  60  *  descriptor at the buffer which was passed in.  The driver
  61  *  then informs the DMA engine that there are packets ready to
  62  *  be transmitted.  Once the controller is finished transmitting
  63  *  the packet, an interrupt may be triggered (under the same
  64  *  conditions as for reception, but depending on the TXF bit).
  65  *  The driver then cleans up the buffer.
  66  */
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/platform_device.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96
  97 #include "gianfar.h"
  98 #include "gianfar_mii.h"
  99
 100 #define TX_TIMEOUT      (1*HZ)
 101 #define SKB_ALLOC_TIMEOUT 1000000
 102 #undef BRIEF_GFAR_ERRORS
 103 #undef VERBOSE_GFAR_ERRORS
 104
 105 #ifdef CONFIG_GFAR_NAPI
 106 #define RECEIVE(x) netif_receive_skb(x)
 107 #else
 108 #define RECEIVE(x) netif_rx(x)
 109 #endif
 110
 111 const char gfar_driver_name[] = "Gianfar Ethernet";
 112 const char gfar_driver_version[] = "1.3";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_timeout(struct net_device *dev);
 117 static int gfar_close(struct net_device *dev);
 118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
 119 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
 120 static int gfar_set_mac_address(struct net_device *dev);
 121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 122 static irqreturn_t gfar_error(int irq, void *dev_id);
 123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 125 static void adjust_link(struct net_device *dev);
 126 static void init_registers(struct net_device *dev);
 127 static int init_phy(struct net_device *dev);
 128 static int gfar_probe(struct platform_device *pdev);
 129 static int gfar_remove(struct platform_device *pdev);
 130 static void free_skb_resources(struct gfar_private *priv);
 131 static void gfar_set_multi(struct net_device *dev);
 132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 133 static void gfar_configure_serdes(struct net_device *dev);
 134 extern int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id, int regnum, u16 value);
 135 extern int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum);
 136 #ifdef CONFIG_GFAR_NAPI
 137 static int gfar_poll(struct net_device *dev, int *budget);
 138 #endif
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 143 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 144 static void gfar_vlan_rx_register(struct net_device *netdev,
 145                                 struct vlan_group *grp);
 146 void gfar_halt(struct net_device *dev);
 147 void gfar_start(struct net_device *dev);
 148 static void gfar_clear_exact_match(struct net_device *dev);
 149 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 150
 151 extern const struct ethtool_ops gfar_ethtool_ops;
 152
 153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 155 MODULE_LICENSE("GPL");
 156
 157 /* Returns 1 if incoming frames use an FCB */
 158 static inline int gfar_uses_fcb(struct gfar_private *priv)
 159 {
 160         return (priv->vlan_enable || priv->rx_csum_enable);
 161 }
 162
 163 /* Set up the ethernet device structure, private data,
 164  * and anything else we need before we start */
 165 static int gfar_probe(struct platform_device *pdev)
 166 {
 167         u32 tempval;
 168         struct net_device *dev = NULL;
 169         struct gfar_private *priv = NULL;
 170         struct gianfar_platform_data *einfo;
 171         struct resource *r;
 172         int idx;
 173         int err = 0;
 174
 175         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 176
 177         if (NULL == einfo) {
 178                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 179                        pdev->id);
 180
 181                 return -ENODEV;
 182         }
 183
 184         /* Create an ethernet device instance */
 185         dev = alloc_etherdev(sizeof (*priv));
 186
 187         if (NULL == dev)
 188                 return -ENOMEM;
 189
 190         priv = netdev_priv(dev);
 191
 192         /* Set the info in the priv to the current info */
 193         priv->einfo = einfo;
 194
 195         /* fill out IRQ fields */
 196         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 197                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 198                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 199                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 200                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 201                         goto regs_fail;
 202         } else {
 203                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 204                 if (priv->interruptTransmit < 0)
 205                         goto regs_fail;
 206         }
 207
 208         /* get a pointer to the register memory */
 209         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 210         priv->regs = ioremap(r->start, sizeof (struct gfar));
 211
 212         if (NULL == priv->regs) {
 213                 err = -ENOMEM;
 214                 goto regs_fail;
 215         }
 216
 217         spin_lock_init(&priv->txlock);
 218         spin_lock_init(&priv->rxlock);
 219
 220         platform_set_drvdata(pdev, dev);
 221
 222         /* Stop the DMA engine now, in case it was running before */
 223         /* (The firmware could have used it, and left it running). */
 224         /* To do this, we write Graceful Receive Stop and Graceful */
 225         /* Transmit Stop, and then wait until the corresponding bits */
 226         /* in IEVENT indicate the stops have completed. */
 227         tempval = gfar_read(&priv->regs->dmactrl);
 228         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 229         gfar_write(&priv->regs->dmactrl, tempval);
 230
 231         tempval = gfar_read(&priv->regs->dmactrl);
 232         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 233         gfar_write(&priv->regs->dmactrl, tempval);
 234
 235         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 236                 cpu_relax();
 237
 238         /* Reset MAC layer */
 239         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 240
 241         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 242         gfar_write(&priv->regs->maccfg1, tempval);
 243
 244         /* Initialize MACCFG2. */
 245         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 246
 247         /* Initialize ECNTRL */
 248         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 249
 250         /* Copy the station address into the dev structure, */
 251         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 252
 253         /* Set the dev->base_addr to the gfar reg region */
 254         dev->base_addr = (unsigned long) (priv->regs);
 255
 256         SET_MODULE_OWNER(dev);
 257         SET_NETDEV_DEV(dev, &pdev->dev);
 258
 259         /* Fill in the dev structure */
 260         dev->open = gfar_enet_open;
 261         dev->hard_start_xmit = gfar_start_xmit;
 262         dev->tx_timeout = gfar_timeout;
 263         dev->watchdog_timeo = TX_TIMEOUT;
 264 #ifdef CONFIG_GFAR_NAPI
 265         dev->poll = gfar_poll;
 266         dev->weight = GFAR_DEV_WEIGHT;
 267 #endif
 268 #ifdef CONFIG_NET_POLL_CONTROLLER
 269         dev->poll_controller = gfar_netpoll;
 270 #endif
 271         dev->stop = gfar_close;
 272         dev->get_stats = gfar_get_stats;
 273         dev->change_mtu = gfar_change_mtu;
 274         dev->mtu = 1500;
 275         dev->set_multicast_list = gfar_set_multi;
 276
 277         dev->ethtool_ops = &gfar_ethtool_ops;
 278
 279         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 280                 priv->rx_csum_enable = 1;
 281                 dev->features |= NETIF_F_IP_CSUM;
 282         } else
 283                 priv->rx_csum_enable = 0;
 284
 285         priv->vlgrp = NULL;
 286
 287         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 288                 dev->vlan_rx_register = gfar_vlan_rx_register;
 289
 290                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 291
 292                 priv->vlan_enable = 1;
 293         }
 294
 295         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 296                 priv->extended_hash = 1;
 297                 priv->hash_width = 9;
 298
 299                 priv->hash_regs[0] = &priv->regs->igaddr0;
 300                 priv->hash_regs[1] = &priv->regs->igaddr1;
 301                 priv->hash_regs[2] = &priv->regs->igaddr2;
 302                 priv->hash_regs[3] = &priv->regs->igaddr3;
 303                 priv->hash_regs[4] = &priv->regs->igaddr4;
 304                 priv->hash_regs[5] = &priv->regs->igaddr5;
 305                 priv->hash_regs[6] = &priv->regs->igaddr6;
 306                 priv->hash_regs[7] = &priv->regs->igaddr7;
 307                 priv->hash_regs[8] = &priv->regs->gaddr0;
 308                 priv->hash_regs[9] = &priv->regs->gaddr1;
 309                 priv->hash_regs[10] = &priv->regs->gaddr2;
 310                 priv->hash_regs[11] = &priv->regs->gaddr3;
 311                 priv->hash_regs[12] = &priv->regs->gaddr4;
 312                 priv->hash_regs[13] = &priv->regs->gaddr5;
 313                 priv->hash_regs[14] = &priv->regs->gaddr6;
 314                 priv->hash_regs[15] = &priv->regs->gaddr7;
 315
 316         } else {
 317                 priv->extended_hash = 0;
 318                 priv->hash_width = 8;
 319
 320                 priv->hash_regs[0] = &priv->regs->gaddr0;
 321                 priv->hash_regs[1] = &priv->regs->gaddr1;
 322                 priv->hash_regs[2] = &priv->regs->gaddr2;
 323                 priv->hash_regs[3] = &priv->regs->gaddr3;
 324                 priv->hash_regs[4] = &priv->regs->gaddr4;
 325                 priv->hash_regs[5] = &priv->regs->gaddr5;
 326                 priv->hash_regs[6] = &priv->regs->gaddr6;
 327                 priv->hash_regs[7] = &priv->regs->gaddr7;
 328         }
 329
 330         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 331                 priv->padding = DEFAULT_PADDING;
 332         else
 333                 priv->padding = 0;
 334
 335         if (dev->features & NETIF_F_IP_CSUM)
 336                 dev->hard_header_len += GMAC_FCB_LEN;
 337
 338         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 339         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 340         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 341
 342         priv->txcoalescing = DEFAULT_TX_COALESCE;
 343         priv->txcount = DEFAULT_TXCOUNT;
 344         priv->txtime = DEFAULT_TXTIME;
 345         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 346         priv->rxcount = DEFAULT_RXCOUNT;
 347         priv->rxtime = DEFAULT_RXTIME;
 348
 349         /* Enable most messages by default */
 350         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 351
 352         err = register_netdev(dev);
 353
 354         if (err) {
 355                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 356                                 dev->name);
 357                 goto register_fail;
 358         }
 359
 360         /* Create all the sysfs files */
 361         gfar_init_sysfs(dev);
 362
 363         /* Print out the device info */
 364         printk(KERN_INFO DEVICE_NAME, dev->name);
 365         for (idx = 0; idx < 6; idx++)
 366                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
 367         printk("\n");
 368
 369         /* Even more device info helps when determining which kernel */
 370         /* provided which set of benchmarks. */
 371 #ifdef CONFIG_GFAR_NAPI
 372         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 373 #else
 374         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
 375 #endif
 376         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 377                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 378
 379         return 0;
 380
 381 register_fail:
 382         iounmap(priv->regs);
 383 regs_fail:
 384         free_netdev(dev);
 385         return err;
 386 }
 387
 388 static int gfar_remove(struct platform_device *pdev)
 389 {
 390         struct net_device *dev = platform_get_drvdata(pdev);
 391         struct gfar_private *priv = netdev_priv(dev);
 392
 393         platform_set_drvdata(pdev, NULL);
 394
 395         iounmap(priv->regs);
 396         free_netdev(dev);
 397
 398         return 0;
 399 }
 400
 401
 402 /* Reads the controller's registers to determine what interface
 403  * connects it to the PHY.
 404  */
 405 static phy_interface_t gfar_get_interface(struct net_device *dev)
 406 {
 407         struct gfar_private *priv = netdev_priv(dev);
 408         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 409
 410         if (ecntrl & ECNTRL_SGMII_MODE)
 411                 return PHY_INTERFACE_MODE_SGMII;
 412
 413         if (ecntrl & ECNTRL_TBI_MODE) {
 414                 if (ecntrl & ECNTRL_REDUCED_MODE)
 415                         return PHY_INTERFACE_MODE_RTBI;
 416                 else
 417                         return PHY_INTERFACE_MODE_TBI;
 418         }
 419
 420         if (ecntrl & ECNTRL_REDUCED_MODE) {
 421                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 422                         return PHY_INTERFACE_MODE_RMII;
 423                 else {
 424                         phy_interface_t interface = priv->einfo->interface;
 425
 426                         /*
 427                          * This isn't autodetected right now, so it must
 428                          * be set by the device tree or platform code.
 429                          */
 430                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 431                                 return PHY_INTERFACE_MODE_RGMII_ID;
 432
 433                         return PHY_INTERFACE_MODE_RGMII;
 434                 }
 435         }
 436
 437         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 438                 return PHY_INTERFACE_MODE_GMII;
 439
 440         return PHY_INTERFACE_MODE_MII;
 441 }
 442
 443
 444 /* Initializes driver's PHY state, and attaches to the PHY.
 445  * Returns 0 on success.
 446  */
 447 static int init_phy(struct net_device *dev)
 448 {
 449         struct gfar_private *priv = netdev_priv(dev);
 450         uint gigabit_support =
 451                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 452                 SUPPORTED_1000baseT_Full : 0;
 453         struct phy_device *phydev;
 454         char phy_id[BUS_ID_SIZE];
 455         phy_interface_t interface;
 456
 457         priv->oldlink = 0;
 458         priv->oldspeed = 0;
 459         priv->oldduplex = -1;
 460
 461         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 462
 463         interface = gfar_get_interface(dev);
 464
 465         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 466
 467         if (interface == PHY_INTERFACE_MODE_SGMII)
 468                 gfar_configure_serdes(dev);
 469
 470         if (IS_ERR(phydev)) {
 471                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 472                 return PTR_ERR(phydev);
 473         }
 474
 475         /* Remove any features not supported by the controller */
 476         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 477         phydev->advertising = phydev->supported;
 478
 479         priv->phydev = phydev;
 480
 481         return 0;
 482 }
 483
 484 static void gfar_configure_serdes(struct net_device *dev)
 485 {
 486         struct gfar_private *priv = netdev_priv(dev);
 487         struct gfar_mii __iomem *regs =
 488                         (void __iomem *)&priv->regs->gfar_mii_regs;
 489
 490         /* Initialise TBI i/f to communicate with serdes (lynx phy) */
 491
 492         /* Single clk mode, mii mode off(for aerdes communication) */
 493         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
 494
 495         /* Supported pause and full-duplex, no half-duplex */
 496         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
 497                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 498                         ADVERTISE_1000XPSE_ASYM);
 499
 500         /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
 501         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
 502                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 503 }
 504
 505 static void init_registers(struct net_device *dev)
 506 {
 507         struct gfar_private *priv = netdev_priv(dev);
 508
 509         /* Clear IEVENT */
 510         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 511
 512         /* Initialize IMASK */
 513         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 514
 515         /* Init hash registers to zero */
 516         gfar_write(&priv->regs->igaddr0, 0);
 517         gfar_write(&priv->regs->igaddr1, 0);
 518         gfar_write(&priv->regs->igaddr2, 0);
 519         gfar_write(&priv->regs->igaddr3, 0);
 520         gfar_write(&priv->regs->igaddr4, 0);
 521         gfar_write(&priv->regs->igaddr5, 0);
 522         gfar_write(&priv->regs->igaddr6, 0);
 523         gfar_write(&priv->regs->igaddr7, 0);
 524
 525         gfar_write(&priv->regs->gaddr0, 0);
 526         gfar_write(&priv->regs->gaddr1, 0);
 527         gfar_write(&priv->regs->gaddr2, 0);
 528         gfar_write(&priv->regs->gaddr3, 0);
 529         gfar_write(&priv->regs->gaddr4, 0);
 530         gfar_write(&priv->regs->gaddr5, 0);
 531         gfar_write(&priv->regs->gaddr6, 0);
 532         gfar_write(&priv->regs->gaddr7, 0);
 533
 534         /* Zero out the rmon mib registers if it has them */
 535         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 536                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 537
 538                 /* Mask off the CAM interrupts */
 539                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 540                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 541         }
 542
 543         /* Initialize the max receive buffer length */
 544         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 545
 546         /* Initialize the Minimum Frame Length Register */
 547         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 548
 549         /* Assign the TBI an address which won't conflict with the PHYs */
 550         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
 551 }
 552
 553
 554 /* Halt the receive and transmit queues */
 555 void gfar_halt(struct net_device *dev)
 556 {
 557         struct gfar_private *priv = netdev_priv(dev);
 558         struct gfar __iomem *regs = priv->regs;
 559         u32 tempval;
 560
 561         /* Mask all interrupts */
 562         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 563
 564         /* Clear all interrupts */
 565         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 566
 567         /* Stop the DMA, and wait for it to stop */
 568         tempval = gfar_read(&priv->regs->dmactrl);
 569         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 570             != (DMACTRL_GRS | DMACTRL_GTS)) {
 571                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 572                 gfar_write(&priv->regs->dmactrl, tempval);
 573
 574                 while (!(gfar_read(&priv->regs->ievent) &
 575                          (IEVENT_GRSC | IEVENT_GTSC)))
 576                         cpu_relax();
 577         }
 578
 579         /* Disable Rx and Tx */
 580         tempval = gfar_read(&regs->maccfg1);
 581         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 582         gfar_write(&regs->maccfg1, tempval);
 583 }
 584
 585 void stop_gfar(struct net_device *dev)
 586 {
 587         struct gfar_private *priv = netdev_priv(dev);
 588         struct gfar __iomem *regs = priv->regs;
 589         unsigned long flags;
 590
 591         phy_stop(priv->phydev);
 592
 593         /* Lock it down */
 594         spin_lock_irqsave(&priv->txlock, flags);
 595         spin_lock(&priv->rxlock);
 596
 597         gfar_halt(dev);
 598
 599         spin_unlock(&priv->rxlock);
 600         spin_unlock_irqrestore(&priv->txlock, flags);
 601
 602         /* Free the IRQs */
 603         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 604                 free_irq(priv->interruptError, dev);
 605                 free_irq(priv->interruptTransmit, dev);
 606                 free_irq(priv->interruptReceive, dev);
 607         } else {
 608                 free_irq(priv->interruptTransmit, dev);
 609         }
 610
 611         free_skb_resources(priv);
 612
 613         dma_free_coherent(NULL,
 614                         sizeof(struct txbd8)*priv->tx_ring_size
 615                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 616                         priv->tx_bd_base,
 617                         gfar_read(&regs->tbase0));
 618 }
 619
 620 /* If there are any tx skbs or rx skbs still around, free them.
 621  * Then free tx_skbuff and rx_skbuff */
 622 static void free_skb_resources(struct gfar_private *priv)
 623 {
 624         struct rxbd8 *rxbdp;
 625         struct txbd8 *txbdp;
 626         int i;
 627
 628         /* Go through all the buffer descriptors and free their data buffers */
 629         txbdp = priv->tx_bd_base;
 630
 631         for (i = 0; i < priv->tx_ring_size; i++) {
 632
 633                 if (priv->tx_skbuff[i]) {
 634                         dma_unmap_single(NULL, txbdp->bufPtr,
 635                                         txbdp->length,
 636                                         DMA_TO_DEVICE);
 637                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 638                         priv->tx_skbuff[i] = NULL;
 639                 }
 640         }
 641
 642         kfree(priv->tx_skbuff);
 643
 644         rxbdp = priv->rx_bd_base;
 645
 646         /* rx_skbuff is not guaranteed to be allocated, so only
 647          * free it and its contents if it is allocated */
 648         if(priv->rx_skbuff != NULL) {
 649                 for (i = 0; i < priv->rx_ring_size; i++) {
 650                         if (priv->rx_skbuff[i]) {
 651                                 dma_unmap_single(NULL, rxbdp->bufPtr,
 652                                                 priv->rx_buffer_size,
 653                                                 DMA_FROM_DEVICE);
 654
 655                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 656                                 priv->rx_skbuff[i] = NULL;
 657                         }
 658
 659                         rxbdp->status = 0;
 660                         rxbdp->length = 0;
 661                         rxbdp->bufPtr = 0;
 662
 663                         rxbdp++;
 664                 }
 665
 666                 kfree(priv->rx_skbuff);
 667         }
 668 }
 669
 670 void gfar_start(struct net_device *dev)
 671 {
 672         struct gfar_private *priv = netdev_priv(dev);
 673         struct gfar __iomem *regs = priv->regs;
 674         u32 tempval;
 675
 676         /* Enable Rx and Tx in MACCFG1 */
 677         tempval = gfar_read(&regs->maccfg1);
 678         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 679         gfar_write(&regs->maccfg1, tempval);
 680
 681         /* Initialize DMACTRL to have WWR and WOP */
 682         tempval = gfar_read(&priv->regs->dmactrl);
 683         tempval |= DMACTRL_INIT_SETTINGS;
 684         gfar_write(&priv->regs->dmactrl, tempval);
 685
 686         /* Make sure we aren't stopped */
 687         tempval = gfar_read(&priv->regs->dmactrl);
 688         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 689         gfar_write(&priv->regs->dmactrl, tempval);
 690
 691         /* Clear THLT/RHLT, so that the DMA starts polling now */
 692         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 693         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 694
 695         /* Unmask the interrupts we look for */
 696         gfar_write(&regs->imask, IMASK_DEFAULT);
 697 }
 698
 699 /* Bring the controller up and running */
 700 int startup_gfar(struct net_device *dev)
 701 {
 702         struct txbd8 *txbdp;
 703         struct rxbd8 *rxbdp;
 704         dma_addr_t addr;
 705         unsigned long vaddr;
 706         int i;
 707         struct gfar_private *priv = netdev_priv(dev);
 708         struct gfar __iomem *regs = priv->regs;
 709         int err = 0;
 710         u32 rctrl = 0;
 711         u32 attrs = 0;
 712
 713         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 714
 715         /* Allocate memory for the buffer descriptors */
 716         vaddr = (unsigned long) dma_alloc_coherent(NULL,
 717                         sizeof (struct txbd8) * priv->tx_ring_size +
 718                         sizeof (struct rxbd8) * priv->rx_ring_size,
 719                         &addr, GFP_KERNEL);
 720
 721         if (vaddr == 0) {
 722                 if (netif_msg_ifup(priv))
 723                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 724                                         dev->name);
 725                 return -ENOMEM;
 726         }
 727
 728         priv->tx_bd_base = (struct txbd8 *) vaddr;
 729
 730         /* enet DMA only understands physical addresses */
 731         gfar_write(&regs->tbase0, addr);
 732
 733         /* Start the rx descriptor ring where the tx ring leaves off */
 734         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 735         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 736         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 737         gfar_write(&regs->rbase0, addr);
 738
 739         /* Setup the skbuff rings */
 740         priv->tx_skbuff =
 741             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 742                                         priv->tx_ring_size, GFP_KERNEL);
 743
 744         if (NULL == priv->tx_skbuff) {
 745                 if (netif_msg_ifup(priv))
 746                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 747                                         dev->name);
 748                 err = -ENOMEM;
 749                 goto tx_skb_fail;
 750         }
 751
 752         for (i = 0; i < priv->tx_ring_size; i++)
 753                 priv->tx_skbuff[i] = NULL;
 754
 755         priv->rx_skbuff =
 756             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 757                                         priv->rx_ring_size, GFP_KERNEL);
 758
 759         if (NULL == priv->rx_skbuff) {
 760                 if (netif_msg_ifup(priv))
 761                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 762                                         dev->name);
 763                 err = -ENOMEM;
 764                 goto rx_skb_fail;
 765         }
 766
 767         for (i = 0; i < priv->rx_ring_size; i++)
 768                 priv->rx_skbuff[i] = NULL;
 769
 770         /* Initialize some variables in our dev structure */
 771         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 772         priv->cur_rx = priv->rx_bd_base;
 773         priv->skb_curtx = priv->skb_dirtytx = 0;
 774         priv->skb_currx = 0;
 775
 776         /* Initialize Transmit Descriptor Ring */
 777         txbdp = priv->tx_bd_base;
 778         for (i = 0; i < priv->tx_ring_size; i++) {
 779                 txbdp->status = 0;
 780                 txbdp->length = 0;
 781                 txbdp->bufPtr = 0;
 782                 txbdp++;
 783         }
 784
 785         /* Set the last descriptor in the ring to indicate wrap */
 786         txbdp--;
 787         txbdp->status |= TXBD_WRAP;
 788
 789         rxbdp = priv->rx_bd_base;
 790         for (i = 0; i < priv->rx_ring_size; i++) {
 791                 struct sk_buff *skb = NULL;
 792
 793                 rxbdp->status = 0;
 794
 795                 skb = gfar_new_skb(dev, rxbdp);
 796
 797                 priv->rx_skbuff[i] = skb;
 798
 799                 rxbdp++;
 800         }
 801
 802         /* Set the last descriptor in the ring to wrap */
 803         rxbdp--;
 804         rxbdp->status |= RXBD_WRAP;
 805
 806         /* If the device has multiple interrupts, register for
 807          * them.  Otherwise, only register for the one */
 808         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 809                 /* Install our interrupt handlers for Error,
 810                  * Transmit, and Receive */
 811                 if (request_irq(priv->interruptError, gfar_error,
 812                                 0, "enet_error", dev) < 0) {
 813                         if (netif_msg_intr(priv))
 814                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 815                                         dev->name, priv->interruptError);
 816
 817                         err = -1;
 818                         goto err_irq_fail;
 819                 }
 820
 821                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 822                                 0, "enet_tx", dev) < 0) {
 823                         if (netif_msg_intr(priv))
 824                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 825                                         dev->name, priv->interruptTransmit);
 826
 827                         err = -1;
 828
 829                         goto tx_irq_fail;
 830                 }
 831
 832                 if (request_irq(priv->interruptReceive, gfar_receive,
 833                                 0, "enet_rx", dev) < 0) {
 834                         if (netif_msg_intr(priv))
 835                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 836                                                 dev->name, priv->interruptReceive);
 837
 838                         err = -1;
 839                         goto rx_irq_fail;
 840                 }
 841         } else {
 842                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 843                                 0, "gfar_interrupt", dev) < 0) {
 844                         if (netif_msg_intr(priv))
 845                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 846                                         dev->name, priv->interruptError);
 847
 848                         err = -1;
 849                         goto err_irq_fail;
 850                 }
 851         }
 852
 853         phy_start(priv->phydev);
 854
 855         /* Configure the coalescing support */
 856         if (priv->txcoalescing)
 857                 gfar_write(&regs->txic,
 858                            mk_ic_value(priv->txcount, priv->txtime));
 859         else
 860                 gfar_write(&regs->txic, 0);
 861
 862         if (priv->rxcoalescing)
 863                 gfar_write(&regs->rxic,
 864                            mk_ic_value(priv->rxcount, priv->rxtime));
 865         else
 866                 gfar_write(&regs->rxic, 0);
 867
 868         if (priv->rx_csum_enable)
 869                 rctrl |= RCTRL_CHECKSUMMING;
 870
 871         if (priv->extended_hash) {
 872                 rctrl |= RCTRL_EXTHASH;
 873
 874                 gfar_clear_exact_match(dev);
 875                 rctrl |= RCTRL_EMEN;
 876         }
 877
 878         if (priv->vlan_enable)
 879                 rctrl |= RCTRL_VLAN;
 880
 881         if (priv->padding) {
 882                 rctrl &= ~RCTRL_PAL_MASK;
 883                 rctrl |= RCTRL_PADDING(priv->padding);
 884         }
 885
 886         /* Init rctrl based on our settings */
 887         gfar_write(&priv->regs->rctrl, rctrl);
 888
 889         if (dev->features & NETIF_F_IP_CSUM)
 890                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 891
 892         /* Set the extraction length and index */
 893         attrs = ATTRELI_EL(priv->rx_stash_size) |
 894                 ATTRELI_EI(priv->rx_stash_index);
 895
 896         gfar_write(&priv->regs->attreli, attrs);
 897
 898         /* Start with defaults, and add stashing or locking
 899          * depending on the approprate variables */
 900         attrs = ATTR_INIT_SETTINGS;
 901
 902         if (priv->bd_stash_en)
 903                 attrs |= ATTR_BDSTASH;
 904
 905         if (priv->rx_stash_size != 0)
 906                 attrs |= ATTR_BUFSTASH;
 907
 908         gfar_write(&priv->regs->attr, attrs);
 909
 910         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
 911         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
 912         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 913
 914         /* Start the controller */
 915         gfar_start(dev);
 916
 917         return 0;
 918
 919 rx_irq_fail:
 920         free_irq(priv->interruptTransmit, dev);
 921 tx_irq_fail:
 922         free_irq(priv->interruptError, dev);
 923 err_irq_fail:
 924 rx_skb_fail:
 925         free_skb_resources(priv);
 926 tx_skb_fail:
 927         dma_free_coherent(NULL,
 928                         sizeof(struct txbd8)*priv->tx_ring_size
 929                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 930                         priv->tx_bd_base,
 931                         gfar_read(&regs->tbase0));
 932
 933         return err;
 934 }
 935
 936 /* Called when something needs to use the ethernet device */
 937 /* Returns 0 for success. */
 938 static int gfar_enet_open(struct net_device *dev)
 939 {
 940         int err;
 941
 942         /* Initialize a bunch of registers */
 943         init_registers(dev);
 944
 945         gfar_set_mac_address(dev);
 946
 947         err = init_phy(dev);
 948
 949         if(err)
 950                 return err;
 951
 952         err = startup_gfar(dev);
 953
 954         netif_start_queue(dev);
 955
 956         return err;
 957 }
 958
 959 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
 960 {
 961         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
 962
 963         memset(fcb, 0, GMAC_FCB_LEN);
 964
 965         return fcb;
 966 }
 967
 968 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 969 {
 970         u8 flags = 0;
 971
 972         /* If we're here, it's a IP packet with a TCP or UDP
 973          * payload.  We set it to checksum, using a pseudo-header
 974          * we provide
 975          */
 976         flags = TXFCB_DEFAULT;
 977
 978         /* Tell the controller what the protocol is */
 979         /* And provide the already calculated phcs */
 980         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
 981                 flags |= TXFCB_UDP;
 982                 fcb->phcs = udp_hdr(skb)->check;
 983         } else
 984                 fcb->phcs = tcp_hdr(skb)->check;
 985
 986         /* l3os is the distance between the start of the
 987          * frame (skb->data) and the start of the IP hdr.
 988          * l4os is the distance between the start of the
 989          * l3 hdr and the l4 hdr */
 990         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
 991         fcb->l4os = skb_network_header_len(skb);
 992
 993         fcb->flags = flags;
 994 }
 995
 996 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
 997 {
 998         fcb->flags |= TXFCB_VLN;
 999         fcb->vlctl = vlan_tx_tag_get(skb);
1000 }
1001
1002 /* This is called by the kernel when a frame is ready for transmission. */
1003 /* It is pointed to by the dev->hard_start_xmit function pointer */
1004 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1005 {
1006         struct gfar_private *priv = netdev_priv(dev);
1007         struct txfcb *fcb = NULL;
1008         struct txbd8 *txbdp;
1009         u16 status;
1010         unsigned long flags;
1011
1012         /* Update transmit stats */
1013         priv->stats.tx_bytes += skb->len;
1014
1015         /* Lock priv now */
1016         spin_lock_irqsave(&priv->txlock, flags);
1017
1018         /* Point at the first free tx descriptor */
1019         txbdp = priv->cur_tx;
1020
1021         /* Clear all but the WRAP status flags */
1022         status = txbdp->status & TXBD_WRAP;
1023
1024         /* Set up checksumming */
1025         if (likely((dev->features & NETIF_F_IP_CSUM)
1026                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1027                 fcb = gfar_add_fcb(skb, txbdp);
1028                 status |= TXBD_TOE;
1029                 gfar_tx_checksum(skb, fcb);
1030         }
1031
1032         if (priv->vlan_enable &&
1033                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1034                 if (unlikely(NULL == fcb)) {
1035                         fcb = gfar_add_fcb(skb, txbdp);
1036                         status |= TXBD_TOE;
1037                 }
1038
1039                 gfar_tx_vlan(skb, fcb);
1040         }
1041
1042         /* Set buffer length and pointer */
1043         txbdp->length = skb->len;
1044         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1045                         skb->len, DMA_TO_DEVICE);
1046
1047         /* Save the skb pointer so we can free it later */
1048         priv->tx_skbuff[priv->skb_curtx] = skb;
1049
1050         /* Update the current skb pointer (wrapping if this was the last) */
1051         priv->skb_curtx =
1052             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1053
1054         /* Flag the BD as interrupt-causing */
1055         status |= TXBD_INTERRUPT;
1056
1057         /* Flag the BD as ready to go, last in frame, and  */
1058         /* in need of CRC */
1059         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1060
1061         dev->trans_start = jiffies;
1062
1063         /* The powerpc-specific eieio() is used, as wmb() has too strong
1064          * semantics (it requires synchronization between cacheable and
1065          * uncacheable mappings, which eieio doesn't provide and which we
1066          * don't need), thus requiring a more expensive sync instruction.  At
1067          * some point, the set of architecture-independent barrier functions
1068          * should be expanded to include weaker barriers.
1069          */
1070
1071         eieio();
1072         txbdp->status = status;
1073
1074         /* If this was the last BD in the ring, the next one */
1075         /* is at the beginning of the ring */
1076         if (txbdp->status & TXBD_WRAP)
1077                 txbdp = priv->tx_bd_base;
1078         else
1079                 txbdp++;
1080
1081         /* If the next BD still needs to be cleaned up, then the bds
1082            are full.  We need to tell the kernel to stop sending us stuff. */
1083         if (txbdp == priv->dirty_tx) {
1084                 netif_stop_queue(dev);
1085
1086                 priv->stats.tx_fifo_errors++;
1087         }
1088
1089         /* Update the current txbd to the next one */
1090         priv->cur_tx = txbdp;
1091
1092         /* Tell the DMA to go go go */
1093         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1094
1095         /* Unlock priv */
1096         spin_unlock_irqrestore(&priv->txlock, flags);
1097
1098         return 0;
1099 }
1100
1101 /* Stops the kernel queue, and halts the controller */
1102 static int gfar_close(struct net_device *dev)
1103 {
1104         struct gfar_private *priv = netdev_priv(dev);
1105         stop_gfar(dev);
1106
1107         /* Disconnect from the PHY */
1108         phy_disconnect(priv->phydev);
1109         priv->phydev = NULL;
1110
1111         netif_stop_queue(dev);
1112
1113         return 0;
1114 }
1115
1116 /* returns a net_device_stats structure pointer */
1117 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1118 {
1119         struct gfar_private *priv = netdev_priv(dev);
1120
1121         return &(priv->stats);
1122 }
1123
1124 /* Changes the mac address if the controller is not running. */
1125 int gfar_set_mac_address(struct net_device *dev)
1126 {
1127         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1128
1129         return 0;
1130 }
1131
1132
1133 /* Enables and disables VLAN insertion/extraction */
1134 static void gfar_vlan_rx_register(struct net_device *dev,
1135                 struct vlan_group *grp)
1136 {
1137         struct gfar_private *priv = netdev_priv(dev);
1138         unsigned long flags;
1139         u32 tempval;
1140
1141         spin_lock_irqsave(&priv->rxlock, flags);
1142
1143         priv->vlgrp = grp;
1144
1145         if (grp) {
1146                 /* Enable VLAN tag insertion */
1147                 tempval = gfar_read(&priv->regs->tctrl);
1148                 tempval |= TCTRL_VLINS;
1149
1150                 gfar_write(&priv->regs->tctrl, tempval);
1151
1152                 /* Enable VLAN tag extraction */
1153                 tempval = gfar_read(&priv->regs->rctrl);
1154                 tempval |= RCTRL_VLEX;
1155                 gfar_write(&priv->regs->rctrl, tempval);
1156         } else {
1157                 /* Disable VLAN tag insertion */
1158                 tempval = gfar_read(&priv->regs->tctrl);
1159                 tempval &= ~TCTRL_VLINS;
1160                 gfar_write(&priv->regs->tctrl, tempval);
1161
1162                 /* Disable VLAN tag extraction */
1163                 tempval = gfar_read(&priv->regs->rctrl);
1164                 tempval &= ~RCTRL_VLEX;
1165                 gfar_write(&priv->regs->rctrl, tempval);
1166         }
1167
1168         spin_unlock_irqrestore(&priv->rxlock, flags);
1169 }
1170
1171 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1172 {
1173         int tempsize, tempval;
1174         struct gfar_private *priv = netdev_priv(dev);
1175         int oldsize = priv->rx_buffer_size;
1176         int frame_size = new_mtu + ETH_HLEN;
1177
1178         if (priv->vlan_enable)
1179                 frame_size += VLAN_ETH_HLEN;
1180
1181         if (gfar_uses_fcb(priv))
1182                 frame_size += GMAC_FCB_LEN;
1183
1184         frame_size += priv->padding;
1185
1186         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1187                 if (netif_msg_drv(priv))
1188                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1189                                         dev->name);
1190                 return -EINVAL;
1191         }
1192
1193         tempsize =
1194             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1195             INCREMENTAL_BUFFER_SIZE;
1196
1197         /* Only stop and start the controller if it isn't already
1198          * stopped, and we changed something */
1199         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1200                 stop_gfar(dev);
1201
1202         priv->rx_buffer_size = tempsize;
1203
1204         dev->mtu = new_mtu;
1205
1206         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1207         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1208
1209         /* If the mtu is larger than the max size for standard
1210          * ethernet frames (ie, a jumbo frame), then set maccfg2
1211          * to allow huge frames, and to check the length */
1212         tempval = gfar_read(&priv->regs->maccfg2);
1213
1214         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1215                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1216         else
1217                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1218
1219         gfar_write(&priv->regs->maccfg2, tempval);
1220
1221         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1222                 startup_gfar(dev);
1223
1224         return 0;
1225 }
1226
1227 /* gfar_timeout gets called when a packet has not been
1228  * transmitted after a set amount of time.
1229  * For now, assume that clearing out all the structures, and
1230  * starting over will fix the problem. */
1231 static void gfar_timeout(struct net_device *dev)
1232 {
1233         struct gfar_private *priv = netdev_priv(dev);
1234
1235         priv->stats.tx_errors++;
1236
1237         if (dev->flags & IFF_UP) {
1238                 stop_gfar(dev);
1239                 startup_gfar(dev);
1240         }
1241
1242         netif_schedule(dev);
1243 }
1244
1245 /* Interrupt Handler for Transmit complete */
1246 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1247 {
1248         struct net_device *dev = (struct net_device *) dev_id;
1249         struct gfar_private *priv = netdev_priv(dev);
1250         struct txbd8 *bdp;
1251
1252         /* Clear IEVENT */
1253         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1254
1255         /* Lock priv */
1256         spin_lock(&priv->txlock);
1257         bdp = priv->dirty_tx;
1258         while ((bdp->status & TXBD_READY) == 0) {
1259                 /* If dirty_tx and cur_tx are the same, then either the */
1260                 /* ring is empty or full now (it could only be full in the beginning, */
1261                 /* obviously).  If it is empty, we are done. */
1262                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1263                         break;
1264
1265                 priv->stats.tx_packets++;
1266
1267                 /* Deferred means some collisions occurred during transmit, */
1268                 /* but we eventually sent the packet. */
1269                 if (bdp->status & TXBD_DEF)
1270                         priv->stats.collisions++;
1271
1272                 /* Free the sk buffer associated with this TxBD */
1273                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1274                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1275                 priv->skb_dirtytx =
1276                     (priv->skb_dirtytx +
1277                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1278
1279                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1280                 if (bdp->status & TXBD_WRAP)
1281                         bdp = priv->tx_bd_base;
1282                 else
1283                         bdp++;
1284
1285                 /* Move dirty_tx to be the next bd */
1286                 priv->dirty_tx = bdp;
1287
1288                 /* We freed a buffer, so now we can restart transmission */
1289                 if (netif_queue_stopped(dev))
1290                         netif_wake_queue(dev);
1291         } /* while ((bdp->status & TXBD_READY) == 0) */
1292
1293         /* If we are coalescing the interrupts, reset the timer */
1294         /* Otherwise, clear it */
1295         if (priv->txcoalescing)
1296                 gfar_write(&priv->regs->txic,
1297                            mk_ic_value(priv->txcount, priv->txtime));
1298         else
1299                 gfar_write(&priv->regs->txic, 0);
1300
1301         spin_unlock(&priv->txlock);
1302
1303         return IRQ_HANDLED;
1304 }
1305
1306 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1307 {
1308         unsigned int alignamount;
1309         struct gfar_private *priv = netdev_priv(dev);
1310         struct sk_buff *skb = NULL;
1311         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1312
1313         /* We have to allocate the skb, so keep trying till we succeed */
1314         while ((!skb) && timeout--)
1315                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1316
1317         if (NULL == skb)
1318                 return NULL;
1319
1320         alignamount = RXBUF_ALIGNMENT -
1321                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1322
1323         /* We need the data buffer to be aligned properly.  We will reserve
1324          * as many bytes as needed to align the data properly
1325          */
1326         skb_reserve(skb, alignamount);
1327
1328         bdp->bufPtr = dma_map_single(NULL, skb->data,
1329                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1330
1331         bdp->length = 0;
1332
1333         /* Mark the buffer empty */
1334         eieio();
1335         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1336
1337         return skb;
1338 }
1339
1340 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1341 {
1342         struct net_device_stats *stats = &priv->stats;
1343         struct gfar_extra_stats *estats = &priv->extra_stats;
1344
1345         /* If the packet was truncated, none of the other errors
1346          * matter */
1347         if (status & RXBD_TRUNCATED) {
1348                 stats->rx_length_errors++;
1349
1350                 estats->rx_trunc++;
1351
1352                 return;
1353         }
1354         /* Count the errors, if there were any */
1355         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1356                 stats->rx_length_errors++;
1357
1358                 if (status & RXBD_LARGE)
1359                         estats->rx_large++;
1360                 else
1361                         estats->rx_short++;
1362         }
1363         if (status & RXBD_NONOCTET) {
1364                 stats->rx_frame_errors++;
1365                 estats->rx_nonoctet++;
1366         }
1367         if (status & RXBD_CRCERR) {
1368                 estats->rx_crcerr++;
1369                 stats->rx_crc_errors++;
1370         }
1371         if (status & RXBD_OVERRUN) {
1372                 estats->rx_overrun++;
1373                 stats->rx_crc_errors++;
1374         }
1375 }
1376
1377 irqreturn_t gfar_receive(int irq, void *dev_id)
1378 {
1379         struct net_device *dev = (struct net_device *) dev_id;
1380         struct gfar_private *priv = netdev_priv(dev);
1381 #ifdef CONFIG_GFAR_NAPI
1382         u32 tempval;
1383 #else
1384         unsigned long flags;
1385 #endif
1386
1387         /* Clear IEVENT, so rx interrupt isn't called again
1388          * because of this interrupt */
1389         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1390
1391         /* support NAPI */
1392 #ifdef CONFIG_GFAR_NAPI
1393         if (netif_rx_schedule_prep(dev)) {
1394                 tempval = gfar_read(&priv->regs->imask);
1395                 tempval &= IMASK_RX_DISABLED;
1396                 gfar_write(&priv->regs->imask, tempval);
1397
1398                 __netif_rx_schedule(dev);
1399         } else {
1400                 if (netif_msg_rx_err(priv))
1401                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1402                                 dev->name, gfar_read(&priv->regs->ievent),
1403                                 gfar_read(&priv->regs->imask));
1404         }
1405 #else
1406
1407         spin_lock_irqsave(&priv->rxlock, flags);
1408         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1409
1410         /* If we are coalescing interrupts, update the timer */
1411         /* Otherwise, clear it */
1412         if (priv->rxcoalescing)
1413                 gfar_write(&priv->regs->rxic,
1414                            mk_ic_value(priv->rxcount, priv->rxtime));
1415         else
1416                 gfar_write(&priv->regs->rxic, 0);
1417
1418         spin_unlock_irqrestore(&priv->rxlock, flags);
1419 #endif
1420
1421         return IRQ_HANDLED;
1422 }
1423
1424 static inline int gfar_rx_vlan(struct sk_buff *skb,
1425                 struct vlan_group *vlgrp, unsigned short vlctl)
1426 {
1427 #ifdef CONFIG_GFAR_NAPI
1428         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1429 #else
1430         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1431 #endif
1432 }
1433
1434 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1435 {
1436         /* If valid headers were found, and valid sums
1437          * were verified, then we tell the kernel that no
1438          * checksumming is necessary.  Otherwise, it is */
1439         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1440                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1441         else
1442                 skb->ip_summed = CHECKSUM_NONE;
1443 }
1444
1445
1446 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1447 {
1448         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1449
1450         /* Remove the FCB from the skb */
1451         skb_pull(skb, GMAC_FCB_LEN);
1452
1453         return fcb;
1454 }
1455
1456 /* gfar_process_frame() -- handle one incoming packet if skb
1457  * isn't NULL.  */
1458 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1459                 int length)
1460 {
1461         struct gfar_private *priv = netdev_priv(dev);
1462         struct rxfcb *fcb = NULL;
1463
1464         if (NULL == skb) {
1465                 if (netif_msg_rx_err(priv))
1466                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1467                 priv->stats.rx_dropped++;
1468                 priv->extra_stats.rx_skbmissing++;
1469         } else {
1470                 int ret;
1471
1472                 /* Prep the skb for the packet */
1473                 skb_put(skb, length);
1474
1475                 /* Grab the FCB if there is one */
1476                 if (gfar_uses_fcb(priv))
1477                         fcb = gfar_get_fcb(skb);
1478
1479                 /* Remove the padded bytes, if there are any */
1480                 if (priv->padding)
1481                         skb_pull(skb, priv->padding);
1482
1483                 if (priv->rx_csum_enable)
1484                         gfar_rx_checksum(skb, fcb);
1485
1486                 /* Tell the skb what kind of packet this is */
1487                 skb->protocol = eth_type_trans(skb, dev);
1488
1489                 /* Send the packet up the stack */
1490                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1491                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1492                 else
1493                         ret = RECEIVE(skb);
1494
1495                 if (NET_RX_DROP == ret)
1496                         priv->extra_stats.kernel_dropped++;
1497         }
1498
1499         return 0;
1500 }
1501
1502 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1503  *   until the budget/quota has been reached. Returns the number
1504  *   of frames handled
1505  */
1506 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1507 {
1508         struct rxbd8 *bdp;
1509         struct sk_buff *skb;
1510         u16 pkt_len;
1511         int howmany = 0;
1512         struct gfar_private *priv = netdev_priv(dev);
1513
1514         /* Get the first full descriptor */
1515         bdp = priv->cur_rx;
1516
1517         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1518                 rmb();
1519                 skb = priv->rx_skbuff[priv->skb_currx];
1520
1521                 if (!(bdp->status &
1522                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1523                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1524                         /* Increment the number of packets */
1525                         priv->stats.rx_packets++;
1526                         howmany++;
1527
1528                         /* Remove the FCS from the packet length */
1529                         pkt_len = bdp->length - 4;
1530
1531                         gfar_process_frame(dev, skb, pkt_len);
1532
1533                         priv->stats.rx_bytes += pkt_len;
1534                 } else {
1535                         count_errors(bdp->status, priv);
1536
1537                         if (skb)
1538                                 dev_kfree_skb_any(skb);
1539
1540                         priv->rx_skbuff[priv->skb_currx] = NULL;
1541                 }
1542
1543                 dev->last_rx = jiffies;
1544
1545                 /* Clear the status flags for this buffer */
1546                 bdp->status &= ~RXBD_STATS;
1547
1548                 /* Add another skb for the future */
1549                 skb = gfar_new_skb(dev, bdp);
1550                 priv->rx_skbuff[priv->skb_currx] = skb;
1551
1552                 /* Update to the next pointer */
1553                 if (bdp->status & RXBD_WRAP)
1554                         bdp = priv->rx_bd_base;
1555                 else
1556                         bdp++;
1557
1558                 /* update to point at the next skb */
1559                 priv->skb_currx =
1560                     (priv->skb_currx +
1561                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1562
1563         }
1564
1565         /* Update the current rxbd pointer to be the next one */
1566         priv->cur_rx = bdp;
1567
1568         return howmany;
1569 }
1570
1571 #ifdef CONFIG_GFAR_NAPI
1572 static int gfar_poll(struct net_device *dev, int *budget)
1573 {
1574         int howmany;
1575         struct gfar_private *priv = netdev_priv(dev);
1576         int rx_work_limit = *budget;
1577
1578         if (rx_work_limit > dev->quota)
1579                 rx_work_limit = dev->quota;
1580
1581         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1582
1583         dev->quota -= howmany;
1584         rx_work_limit -= howmany;
1585         *budget -= howmany;
1586
1587         if (rx_work_limit > 0) {
1588                 netif_rx_complete(dev);
1589
1590                 /* Clear the halt bit in RSTAT */
1591                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1592
1593                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1594
1595                 /* If we are coalescing interrupts, update the timer */
1596                 /* Otherwise, clear it */
1597                 if (priv->rxcoalescing)
1598                         gfar_write(&priv->regs->rxic,
1599                                    mk_ic_value(priv->rxcount, priv->rxtime));
1600                 else
1601                         gfar_write(&priv->regs->rxic, 0);
1602         }
1603
1604         /* Return 1 if there's more work to do */
1605         return (rx_work_limit > 0) ? 0 : 1;
1606 }
1607 #endif
1608
1609 #ifdef CONFIG_NET_POLL_CONTROLLER
1610 /*
1611  * Polling 'interrupt' - used by things like netconsole to send skbs
1612  * without having to re-enable interrupts. It's not called while
1613  * the interrupt routine is executing.
1614  */
1615 static void gfar_netpoll(struct net_device *dev)
1616 {
1617         struct gfar_private *priv = netdev_priv(dev);
1618
1619         /* If the device has multiple interrupts, run tx/rx */
1620         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1621                 disable_irq(priv->interruptTransmit);
1622                 disable_irq(priv->interruptReceive);
1623                 disable_irq(priv->interruptError);
1624                 gfar_interrupt(priv->interruptTransmit, dev);
1625                 enable_irq(priv->interruptError);
1626                 enable_irq(priv->interruptReceive);
1627                 enable_irq(priv->interruptTransmit);
1628         } else {
1629                 disable_irq(priv->interruptTransmit);
1630                 gfar_interrupt(priv->interruptTransmit, dev);
1631                 enable_irq(priv->interruptTransmit);
1632         }
1633 }
1634 #endif
1635
1636 /* The interrupt handler for devices with one interrupt */
1637 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1638 {
1639         struct net_device *dev = dev_id;
1640         struct gfar_private *priv = netdev_priv(dev);
1641
1642         /* Save ievent for future reference */
1643         u32 events = gfar_read(&priv->regs->ievent);
1644
1645         /* Check for reception */
1646         if (events & IEVENT_RX_MASK)
1647                 gfar_receive(irq, dev_id);
1648
1649         /* Check for transmit completion */
1650         if (events & IEVENT_TX_MASK)
1651                 gfar_transmit(irq, dev_id);
1652
1653         /* Check for errors */
1654         if (events & IEVENT_ERR_MASK)
1655                 gfar_error(irq, dev_id);
1656
1657         return IRQ_HANDLED;
1658 }
1659
1660 /* Called every time the controller might need to be made
1661  * aware of new link state.  The PHY code conveys this
1662  * information through variables in the phydev structure, and this
1663  * function converts those variables into the appropriate
1664  * register values, and can bring down the device if needed.
1665  */
1666 static void adjust_link(struct net_device *dev)
1667 {
1668         struct gfar_private *priv = netdev_priv(dev);
1669         struct gfar __iomem *regs = priv->regs;
1670         unsigned long flags;
1671         struct phy_device *phydev = priv->phydev;
1672         int new_state = 0;
1673
1674         spin_lock_irqsave(&priv->txlock, flags);
1675         if (phydev->link) {
1676                 u32 tempval = gfar_read(&regs->maccfg2);
1677                 u32 ecntrl = gfar_read(&regs->ecntrl);
1678
1679                 /* Now we make sure that we can be in full duplex mode.
1680                  * If not, we operate in half-duplex mode. */
1681                 if (phydev->duplex != priv->oldduplex) {
1682                         new_state = 1;
1683                         if (!(phydev->duplex))
1684                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1685                         else
1686                                 tempval |= MACCFG2_FULL_DUPLEX;
1687
1688                         priv->oldduplex = phydev->duplex;
1689                 }
1690
1691                 if (phydev->speed != priv->oldspeed) {
1692                         new_state = 1;
1693                         switch (phydev->speed) {
1694                         case 1000:
1695                                 tempval =
1696                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1697                                 break;
1698                         case 100:
1699                         case 10:
1700                                 tempval =
1701                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1702
1703                                 /* Reduced mode distinguishes
1704                                  * between 10 and 100 */
1705                                 if (phydev->speed == SPEED_100)
1706                                         ecntrl |= ECNTRL_R100;
1707                                 else
1708                                         ecntrl &= ~(ECNTRL_R100);
1709                                 break;
1710                         default:
1711                                 if (netif_msg_link(priv))
1712                                         printk(KERN_WARNING
1713                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1714                                                 dev->name, phydev->speed);
1715                                 break;
1716                         }
1717
1718                         priv->oldspeed = phydev->speed;
1719                 }
1720
1721                 gfar_write(&regs->maccfg2, tempval);
1722                 gfar_write(&regs->ecntrl, ecntrl);
1723
1724                 if (!priv->oldlink) {
1725                         new_state = 1;
1726                         priv->oldlink = 1;
1727                         netif_schedule(dev);
1728                 }
1729         } else if (priv->oldlink) {
1730                 new_state = 1;
1731                 priv->oldlink = 0;
1732                 priv->oldspeed = 0;
1733                 priv->oldduplex = -1;
1734         }
1735
1736         if (new_state && netif_msg_link(priv))
1737                 phy_print_status(phydev);
1738
1739         spin_unlock_irqrestore(&priv->txlock, flags);
1740 }
1741
1742 /* Update the hash table based on the current list of multicast
1743  * addresses we subscribe to.  Also, change the promiscuity of
1744  * the device based on the flags (this function is called
1745  * whenever dev->flags is changed */
1746 static void gfar_set_multi(struct net_device *dev)
1747 {
1748         struct dev_mc_list *mc_ptr;
1749         struct gfar_private *priv = netdev_priv(dev);
1750         struct gfar __iomem *regs = priv->regs;
1751         u32 tempval;
1752
1753         if(dev->flags & IFF_PROMISC) {
1754                 /* Set RCTRL to PROM */
1755                 tempval = gfar_read(&regs->rctrl);
1756                 tempval |= RCTRL_PROM;
1757                 gfar_write(&regs->rctrl, tempval);
1758         } else {
1759                 /* Set RCTRL to not PROM */
1760                 tempval = gfar_read(&regs->rctrl);
1761                 tempval &= ~(RCTRL_PROM);
1762                 gfar_write(&regs->rctrl, tempval);
1763         }
1764
1765         if(dev->flags & IFF_ALLMULTI) {
1766                 /* Set the hash to rx all multicast frames */
1767                 gfar_write(&regs->igaddr0, 0xffffffff);
1768                 gfar_write(&regs->igaddr1, 0xffffffff);
1769                 gfar_write(&regs->igaddr2, 0xffffffff);
1770                 gfar_write(&regs->igaddr3, 0xffffffff);
1771                 gfar_write(&regs->igaddr4, 0xffffffff);
1772                 gfar_write(&regs->igaddr5, 0xffffffff);
1773                 gfar_write(&regs->igaddr6, 0xffffffff);
1774                 gfar_write(&regs->igaddr7, 0xffffffff);
1775                 gfar_write(&regs->gaddr0, 0xffffffff);
1776                 gfar_write(&regs->gaddr1, 0xffffffff);
1777                 gfar_write(&regs->gaddr2, 0xffffffff);
1778                 gfar_write(&regs->gaddr3, 0xffffffff);
1779                 gfar_write(&regs->gaddr4, 0xffffffff);
1780                 gfar_write(&regs->gaddr5, 0xffffffff);
1781                 gfar_write(&regs->gaddr6, 0xffffffff);
1782                 gfar_write(&regs->gaddr7, 0xffffffff);
1783         } else {
1784                 int em_num;
1785                 int idx;
1786
1787                 /* zero out the hash */
1788                 gfar_write(&regs->igaddr0, 0x0);
1789                 gfar_write(&regs->igaddr1, 0x0);
1790                 gfar_write(&regs->igaddr2, 0x0);
1791                 gfar_write(&regs->igaddr3, 0x0);
1792                 gfar_write(&regs->igaddr4, 0x0);
1793                 gfar_write(&regs->igaddr5, 0x0);
1794                 gfar_write(&regs->igaddr6, 0x0);
1795                 gfar_write(&regs->igaddr7, 0x0);
1796                 gfar_write(&regs->gaddr0, 0x0);
1797                 gfar_write(&regs->gaddr1, 0x0);
1798                 gfar_write(&regs->gaddr2, 0x0);
1799                 gfar_write(&regs->gaddr3, 0x0);
1800                 gfar_write(&regs->gaddr4, 0x0);
1801                 gfar_write(&regs->gaddr5, 0x0);
1802                 gfar_write(&regs->gaddr6, 0x0);
1803                 gfar_write(&regs->gaddr7, 0x0);
1804
1805                 /* If we have extended hash tables, we need to
1806                  * clear the exact match registers to prepare for
1807                  * setting them */
1808                 if (priv->extended_hash) {
1809                         em_num = GFAR_EM_NUM + 1;
1810                         gfar_clear_exact_match(dev);
1811                         idx = 1;
1812                 } else {
1813                         idx = 0;
1814                         em_num = 0;
1815                 }
1816
1817                 if(dev->mc_count == 0)
1818                         return;
1819
1820                 /* Parse the list, and set the appropriate bits */
1821                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1822                         if (idx < em_num) {
1823                                 gfar_set_mac_for_addr(dev, idx,
1824                                                 mc_ptr->dmi_addr);
1825                                 idx++;
1826                         } else
1827                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1828                 }
1829         }
1830
1831         return;
1832 }
1833
1834
1835 /* Clears each of the exact match registers to zero, so they
1836  * don't interfere with normal reception */
1837 static void gfar_clear_exact_match(struct net_device *dev)
1838 {
1839         int idx;
1840         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1841
1842         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1843                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1844 }
1845
1846 /* Set the appropriate hash bit for the given addr */
1847 /* The algorithm works like so:
1848  * 1) Take the Destination Address (ie the multicast address), and
1849  * do a CRC on it (little endian), and reverse the bits of the
1850  * result.
1851  * 2) Use the 8 most significant bits as a hash into a 256-entry
1852  * table.  The table is controlled through 8 32-bit registers:
1853  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1854  * gaddr7.  This means that the 3 most significant bits in the
1855  * hash index which gaddr register to use, and the 5 other bits
1856  * indicate which bit (assuming an IBM numbering scheme, which
1857  * for PowerPC (tm) is usually the case) in the register holds
1858  * the entry. */
1859 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1860 {
1861         u32 tempval;
1862         struct gfar_private *priv = netdev_priv(dev);
1863         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1864         int width = priv->hash_width;
1865         u8 whichbit = (result >> (32 - width)) & 0x1f;
1866         u8 whichreg = result >> (32 - width + 5);
1867         u32 value = (1 << (31-whichbit));
1868
1869         tempval = gfar_read(priv->hash_regs[whichreg]);
1870         tempval |= value;
1871         gfar_write(priv->hash_regs[whichreg], tempval);
1872
1873         return;
1874 }
1875
1876
1877 /* There are multiple MAC Address register pairs on some controllers
1878  * This function sets the numth pair to a given address
1879  */
1880 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1881 {
1882         struct gfar_private *priv = netdev_priv(dev);
1883         int idx;
1884         char tmpbuf[MAC_ADDR_LEN];
1885         u32 tempval;
1886         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1887
1888         macptr += num*2;
1889
1890         /* Now copy it into the mac registers backwards, cuz */
1891         /* little endian is silly */
1892         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1893                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1894
1895         gfar_write(macptr, *((u32 *) (tmpbuf)));
1896
1897         tempval = *((u32 *) (tmpbuf + 4));
1898
1899         gfar_write(macptr+1, tempval);
1900 }
1901
1902 /* GFAR error interrupt handler */
1903 static irqreturn_t gfar_error(int irq, void *dev_id)
1904 {
1905         struct net_device *dev = dev_id;
1906         struct gfar_private *priv = netdev_priv(dev);
1907
1908         /* Save ievent for future reference */
1909         u32 events = gfar_read(&priv->regs->ievent);
1910
1911         /* Clear IEVENT */
1912         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1913
1914         /* Hmm... */
1915         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1916                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1917                        dev->name, events, gfar_read(&priv->regs->imask));
1918
1919         /* Update the error counters */
1920         if (events & IEVENT_TXE) {
1921                 priv->stats.tx_errors++;
1922
1923                 if (events & IEVENT_LC)
1924                         priv->stats.tx_window_errors++;
1925                 if (events & IEVENT_CRL)
1926                         priv->stats.tx_aborted_errors++;
1927                 if (events & IEVENT_XFUN) {
1928                         if (netif_msg_tx_err(priv))
1929                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1930                                        "packet dropped.\n", dev->name);
1931                         priv->stats.tx_dropped++;
1932                         priv->extra_stats.tx_underrun++;
1933
1934                         /* Reactivate the Tx Queues */
1935                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1936                 }
1937                 if (netif_msg_tx_err(priv))
1938                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1939         }
1940         if (events & IEVENT_BSY) {
1941                 priv->stats.rx_errors++;
1942                 priv->extra_stats.rx_bsy++;
1943
1944                 gfar_receive(irq, dev_id);
1945
1946 #ifndef CONFIG_GFAR_NAPI
1947                 /* Clear the halt bit in RSTAT */
1948                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1949 #endif
1950
1951                 if (netif_msg_rx_err(priv))
1952                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1953                                dev->name, gfar_read(&priv->regs->rstat));
1954         }
1955         if (events & IEVENT_BABR) {
1956                 priv->stats.rx_errors++;
1957                 priv->extra_stats.rx_babr++;
1958
1959                 if (netif_msg_rx_err(priv))
1960                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1961         }
1962         if (events & IEVENT_EBERR) {
1963                 priv->extra_stats.eberr++;
1964                 if (netif_msg_rx_err(priv))
1965                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
1966         }
1967         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1968                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1969
1970         if (events & IEVENT_BABT) {
1971                 priv->extra_stats.tx_babt++;
1972                 if (netif_msg_tx_err(priv))
1973                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1974         }
1975         return IRQ_HANDLED;
1976 }
1977
1978 /* Structure for a device driver */
1979 static struct platform_driver gfar_driver = {
1980         .probe = gfar_probe,
1981         .remove = gfar_remove,
1982         .driver = {
1983                 .name = "fsl-gianfar",
1984         },
1985 };
1986
1987 static int __init gfar_init(void)
1988 {
1989         int err = gfar_mdio_init();
1990
1991         if (err)
1992                 return err;
1993
1994         err = platform_driver_register(&gfar_driver);
1995
1996         if (err)
1997                 gfar_mdio_exit();
1998
1999         return err;
2000 }
2001
2002 static void __exit gfar_exit(void)
2003 {
2004         platform_driver_unregister(&gfar_driver);
2005         gfar_mdio_exit();
2006 }
2007
2008 module_init(gfar_init);
2009 module_exit(gfar_exit);
2010