drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit. This method will start at the last known empty
  48  *  descriptor, and process every subsequent descriptor until there
  49  *  are none left with data (NAPI will stop after a set number of
  50  *  packets to give time to other tasks, but will eventually
  51  *  process all the packets).  The data arrives inside a
  52  *  pre-allocated skb, and so after the skb is passed up to the
  53  *  stack, a new skb must be allocated, and the address field in
  54  *  the buffer descriptor must be updated to indicate this new
  55  *  skb.
  56  *
  57  *  When the kernel requests that a packet be transmitted, the
  58  *  driver starts where it left off last time, and points the
  59  *  descriptor at the buffer which was passed in.  The driver
  60  *  then informs the DMA engine that there are packets ready to
  61  *  be transmitted.  Once the controller is finished transmitting
  62  *  the packet, an interrupt may be triggered (under the same
  63  *  conditions as for reception, but depending on the TXF bit).
  64  *  The driver then cleans up the buffer.
  65  */
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/platform_device.h>
  82 #include <linux/ip.h>
  83 #include <linux/tcp.h>
  84 #include <linux/udp.h>
  85 #include <linux/in.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95
  96 #include "gianfar.h"
  97 #include "gianfar_mii.h"
  98
  99 #define TX_TIMEOUT      (1*HZ)
 100 #undef BRIEF_GFAR_ERRORS
 101 #undef VERBOSE_GFAR_ERRORS
 102
 103 const char gfar_driver_name[] = "Gianfar Ethernet";
 104 const char gfar_driver_version[] = "1.3";
 105
 106 static int gfar_enet_open(struct net_device *dev);
 107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 108 static void gfar_timeout(struct net_device *dev);
 109 static int gfar_close(struct net_device *dev);
 110 struct sk_buff *gfar_new_skb(struct net_device *dev);
 111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 112                 struct sk_buff *skb);
 113 static int gfar_set_mac_address(struct net_device *dev);
 114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 115 static irqreturn_t gfar_error(int irq, void *dev_id);
 116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 118 static void adjust_link(struct net_device *dev);
 119 static void init_registers(struct net_device *dev);
 120 static int init_phy(struct net_device *dev);
 121 static int gfar_probe(struct platform_device *pdev);
 122 static int gfar_remove(struct platform_device *pdev);
 123 static void free_skb_resources(struct gfar_private *priv);
 124 static void gfar_set_multi(struct net_device *dev);
 125 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 126 static void gfar_configure_serdes(struct net_device *dev);
 127 static int gfar_poll(struct napi_struct *napi, int budget);
 128 #ifdef CONFIG_NET_POLL_CONTROLLER
 129 static void gfar_netpoll(struct net_device *dev);
 130 #endif
 131 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 132 static int gfar_clean_tx_ring(struct net_device *dev);
 133 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 134 static void gfar_vlan_rx_register(struct net_device *netdev,
 135                                 struct vlan_group *grp);
 136 void gfar_halt(struct net_device *dev);
 137 void gfar_start(struct net_device *dev);
 138 static void gfar_clear_exact_match(struct net_device *dev);
 139 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 140
 141 extern const struct ethtool_ops gfar_ethtool_ops;
 142
 143 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 144 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 145 MODULE_LICENSE("GPL");
 146
 147 /* Returns 1 if incoming frames use an FCB */
 148 static inline int gfar_uses_fcb(struct gfar_private *priv)
 149 {
 150         return (priv->vlan_enable || priv->rx_csum_enable);
 151 }
 152
 153 /* Set up the ethernet device structure, private data,
 154  * and anything else we need before we start */
 155 static int gfar_probe(struct platform_device *pdev)
 156 {
 157         u32 tempval;
 158         struct net_device *dev = NULL;
 159         struct gfar_private *priv = NULL;
 160         struct gianfar_platform_data *einfo;
 161         struct resource *r;
 162         int err = 0;
 163         DECLARE_MAC_BUF(mac);
 164
 165         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 166
 167         if (NULL == einfo) {
 168                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 169                        pdev->id);
 170
 171                 return -ENODEV;
 172         }
 173
 174         /* Create an ethernet device instance */
 175         dev = alloc_etherdev(sizeof (*priv));
 176
 177         if (NULL == dev)
 178                 return -ENOMEM;
 179
 180         priv = netdev_priv(dev);
 181         priv->dev = dev;
 182
 183         /* Set the info in the priv to the current info */
 184         priv->einfo = einfo;
 185
 186         /* fill out IRQ fields */
 187         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 188                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 189                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 190                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 191                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 192                         goto regs_fail;
 193         } else {
 194                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 195                 if (priv->interruptTransmit < 0)
 196                         goto regs_fail;
 197         }
 198
 199         /* get a pointer to the register memory */
 200         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 201         priv->regs = ioremap(r->start, sizeof (struct gfar));
 202
 203         if (NULL == priv->regs) {
 204                 err = -ENOMEM;
 205                 goto regs_fail;
 206         }
 207
 208         spin_lock_init(&priv->txlock);
 209         spin_lock_init(&priv->rxlock);
 210
 211         platform_set_drvdata(pdev, dev);
 212
 213         /* Stop the DMA engine now, in case it was running before */
 214         /* (The firmware could have used it, and left it running). */
 215         /* To do this, we write Graceful Receive Stop and Graceful */
 216         /* Transmit Stop, and then wait until the corresponding bits */
 217         /* in IEVENT indicate the stops have completed. */
 218         tempval = gfar_read(&priv->regs->dmactrl);
 219         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 220         gfar_write(&priv->regs->dmactrl, tempval);
 221
 222         tempval = gfar_read(&priv->regs->dmactrl);
 223         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 224         gfar_write(&priv->regs->dmactrl, tempval);
 225
 226         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 227                 cpu_relax();
 228
 229         /* Reset MAC layer */
 230         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 231
 232         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 233         gfar_write(&priv->regs->maccfg1, tempval);
 234
 235         /* Initialize MACCFG2. */
 236         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 237
 238         /* Initialize ECNTRL */
 239         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 240
 241         /* Copy the station address into the dev structure, */
 242         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 243
 244         /* Set the dev->base_addr to the gfar reg region */
 245         dev->base_addr = (unsigned long) (priv->regs);
 246
 247         SET_NETDEV_DEV(dev, &pdev->dev);
 248
 249         /* Fill in the dev structure */
 250         dev->open = gfar_enet_open;
 251         dev->hard_start_xmit = gfar_start_xmit;
 252         dev->tx_timeout = gfar_timeout;
 253         dev->watchdog_timeo = TX_TIMEOUT;
 254         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 255 #ifdef CONFIG_NET_POLL_CONTROLLER
 256         dev->poll_controller = gfar_netpoll;
 257 #endif
 258         dev->stop = gfar_close;
 259         dev->change_mtu = gfar_change_mtu;
 260         dev->mtu = 1500;
 261         dev->set_multicast_list = gfar_set_multi;
 262
 263         dev->ethtool_ops = &gfar_ethtool_ops;
 264
 265         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 266                 priv->rx_csum_enable = 1;
 267                 dev->features |= NETIF_F_IP_CSUM;
 268         } else
 269                 priv->rx_csum_enable = 0;
 270
 271         priv->vlgrp = NULL;
 272
 273         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 274                 dev->vlan_rx_register = gfar_vlan_rx_register;
 275
 276                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 277
 278                 priv->vlan_enable = 1;
 279         }
 280
 281         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 282                 priv->extended_hash = 1;
 283                 priv->hash_width = 9;
 284
 285                 priv->hash_regs[0] = &priv->regs->igaddr0;
 286                 priv->hash_regs[1] = &priv->regs->igaddr1;
 287                 priv->hash_regs[2] = &priv->regs->igaddr2;
 288                 priv->hash_regs[3] = &priv->regs->igaddr3;
 289                 priv->hash_regs[4] = &priv->regs->igaddr4;
 290                 priv->hash_regs[5] = &priv->regs->igaddr5;
 291                 priv->hash_regs[6] = &priv->regs->igaddr6;
 292                 priv->hash_regs[7] = &priv->regs->igaddr7;
 293                 priv->hash_regs[8] = &priv->regs->gaddr0;
 294                 priv->hash_regs[9] = &priv->regs->gaddr1;
 295                 priv->hash_regs[10] = &priv->regs->gaddr2;
 296                 priv->hash_regs[11] = &priv->regs->gaddr3;
 297                 priv->hash_regs[12] = &priv->regs->gaddr4;
 298                 priv->hash_regs[13] = &priv->regs->gaddr5;
 299                 priv->hash_regs[14] = &priv->regs->gaddr6;
 300                 priv->hash_regs[15] = &priv->regs->gaddr7;
 301
 302         } else {
 303                 priv->extended_hash = 0;
 304                 priv->hash_width = 8;
 305
 306                 priv->hash_regs[0] = &priv->regs->gaddr0;
 307                 priv->hash_regs[1] = &priv->regs->gaddr1;
 308                 priv->hash_regs[2] = &priv->regs->gaddr2;
 309                 priv->hash_regs[3] = &priv->regs->gaddr3;
 310                 priv->hash_regs[4] = &priv->regs->gaddr4;
 311                 priv->hash_regs[5] = &priv->regs->gaddr5;
 312                 priv->hash_regs[6] = &priv->regs->gaddr6;
 313                 priv->hash_regs[7] = &priv->regs->gaddr7;
 314         }
 315
 316         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 317                 priv->padding = DEFAULT_PADDING;
 318         else
 319                 priv->padding = 0;
 320
 321         if (dev->features & NETIF_F_IP_CSUM)
 322                 dev->hard_header_len += GMAC_FCB_LEN;
 323
 324         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 325         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 326         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 327
 328         priv->txcoalescing = DEFAULT_TX_COALESCE;
 329         priv->txcount = DEFAULT_TXCOUNT;
 330         priv->txtime = DEFAULT_TXTIME;
 331         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 332         priv->rxcount = DEFAULT_RXCOUNT;
 333         priv->rxtime = DEFAULT_RXTIME;
 334
 335         /* Enable most messages by default */
 336         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 337
 338         err = register_netdev(dev);
 339
 340         if (err) {
 341                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 342                                 dev->name);
 343                 goto register_fail;
 344         }
 345
 346         /* Create all the sysfs files */
 347         gfar_init_sysfs(dev);
 348
 349         /* Print out the device info */
 350         printk(KERN_INFO DEVICE_NAME "%s\n",
 351                dev->name, print_mac(mac, dev->dev_addr));
 352
 353         /* Even more device info helps when determining which kernel */
 354         /* provided which set of benchmarks. */
 355         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 356         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 357                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 358
 359         return 0;
 360
 361 register_fail:
 362         iounmap(priv->regs);
 363 regs_fail:
 364         free_netdev(dev);
 365         return err;
 366 }
 367
 368 static int gfar_remove(struct platform_device *pdev)
 369 {
 370         struct net_device *dev = platform_get_drvdata(pdev);
 371         struct gfar_private *priv = netdev_priv(dev);
 372
 373         platform_set_drvdata(pdev, NULL);
 374
 375         iounmap(priv->regs);
 376         free_netdev(dev);
 377
 378         return 0;
 379 }
 380
 381
 382 /* Reads the controller's registers to determine what interface
 383  * connects it to the PHY.
 384  */
 385 static phy_interface_t gfar_get_interface(struct net_device *dev)
 386 {
 387         struct gfar_private *priv = netdev_priv(dev);
 388         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 389
 390         if (ecntrl & ECNTRL_SGMII_MODE)
 391                 return PHY_INTERFACE_MODE_SGMII;
 392
 393         if (ecntrl & ECNTRL_TBI_MODE) {
 394                 if (ecntrl & ECNTRL_REDUCED_MODE)
 395                         return PHY_INTERFACE_MODE_RTBI;
 396                 else
 397                         return PHY_INTERFACE_MODE_TBI;
 398         }
 399
 400         if (ecntrl & ECNTRL_REDUCED_MODE) {
 401                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 402                         return PHY_INTERFACE_MODE_RMII;
 403                 else {
 404                         phy_interface_t interface = priv->einfo->interface;
 405
 406                         /*
 407                          * This isn't autodetected right now, so it must
 408                          * be set by the device tree or platform code.
 409                          */
 410                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 411                                 return PHY_INTERFACE_MODE_RGMII_ID;
 412
 413                         return PHY_INTERFACE_MODE_RGMII;
 414                 }
 415         }
 416
 417         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 418                 return PHY_INTERFACE_MODE_GMII;
 419
 420         return PHY_INTERFACE_MODE_MII;
 421 }
 422
 423
 424 /* Initializes driver's PHY state, and attaches to the PHY.
 425  * Returns 0 on success.
 426  */
 427 static int init_phy(struct net_device *dev)
 428 {
 429         struct gfar_private *priv = netdev_priv(dev);
 430         uint gigabit_support =
 431                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 432                 SUPPORTED_1000baseT_Full : 0;
 433         struct phy_device *phydev;
 434         char phy_id[BUS_ID_SIZE];
 435         phy_interface_t interface;
 436
 437         priv->oldlink = 0;
 438         priv->oldspeed = 0;
 439         priv->oldduplex = -1;
 440
 441         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 442
 443         interface = gfar_get_interface(dev);
 444
 445         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 446
 447         if (interface == PHY_INTERFACE_MODE_SGMII)
 448                 gfar_configure_serdes(dev);
 449
 450         if (IS_ERR(phydev)) {
 451                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 452                 return PTR_ERR(phydev);
 453         }
 454
 455         /* Remove any features not supported by the controller */
 456         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 457         phydev->advertising = phydev->supported;
 458
 459         priv->phydev = phydev;
 460
 461         return 0;
 462 }
 463
 464 /*
 465  * Initialize TBI PHY interface for communicating with the
 466  * SERDES lynx PHY on the chip.  We communicate with this PHY
 467  * through the MDIO bus on each controller, treating it as a
 468  * "normal" PHY at the address found in the TBIPA register.  We assume
 469  * that the TBIPA register is valid.  Either the MDIO bus code will set
 470  * it to a value that doesn't conflict with other PHYs on the bus, or the
 471  * value doesn't matter, as there are no other PHYs on the bus.
 472  */
 473 static void gfar_configure_serdes(struct net_device *dev)
 474 {
 475         struct gfar_private *priv = netdev_priv(dev);
 476         struct gfar_mii __iomem *regs =
 477                         (void __iomem *)&priv->regs->gfar_mii_regs;
 478         int tbipa = gfar_read(&priv->regs->tbipa);
 479
 480         /* Single clk mode, mii mode off(for serdes communication) */
 481         gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
 482
 483         gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
 484                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 485                         ADVERTISE_1000XPSE_ASYM);
 486
 487         gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
 488                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 489 }
 490
 491 static void init_registers(struct net_device *dev)
 492 {
 493         struct gfar_private *priv = netdev_priv(dev);
 494
 495         /* Clear IEVENT */
 496         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 497
 498         /* Initialize IMASK */
 499         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 500
 501         /* Init hash registers to zero */
 502         gfar_write(&priv->regs->igaddr0, 0);
 503         gfar_write(&priv->regs->igaddr1, 0);
 504         gfar_write(&priv->regs->igaddr2, 0);
 505         gfar_write(&priv->regs->igaddr3, 0);
 506         gfar_write(&priv->regs->igaddr4, 0);
 507         gfar_write(&priv->regs->igaddr5, 0);
 508         gfar_write(&priv->regs->igaddr6, 0);
 509         gfar_write(&priv->regs->igaddr7, 0);
 510
 511         gfar_write(&priv->regs->gaddr0, 0);
 512         gfar_write(&priv->regs->gaddr1, 0);
 513         gfar_write(&priv->regs->gaddr2, 0);
 514         gfar_write(&priv->regs->gaddr3, 0);
 515         gfar_write(&priv->regs->gaddr4, 0);
 516         gfar_write(&priv->regs->gaddr5, 0);
 517         gfar_write(&priv->regs->gaddr6, 0);
 518         gfar_write(&priv->regs->gaddr7, 0);
 519
 520         /* Zero out the rmon mib registers if it has them */
 521         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 522                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 523
 524                 /* Mask off the CAM interrupts */
 525                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 526                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 527         }
 528
 529         /* Initialize the max receive buffer length */
 530         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 531
 532         /* Initialize the Minimum Frame Length Register */
 533         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 534 }
 535
 536
 537 /* Halt the receive and transmit queues */
 538 void gfar_halt(struct net_device *dev)
 539 {
 540         struct gfar_private *priv = netdev_priv(dev);
 541         struct gfar __iomem *regs = priv->regs;
 542         u32 tempval;
 543
 544         /* Mask all interrupts */
 545         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 546
 547         /* Clear all interrupts */
 548         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 549
 550         /* Stop the DMA, and wait for it to stop */
 551         tempval = gfar_read(&priv->regs->dmactrl);
 552         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 553             != (DMACTRL_GRS | DMACTRL_GTS)) {
 554                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 555                 gfar_write(&priv->regs->dmactrl, tempval);
 556
 557                 while (!(gfar_read(&priv->regs->ievent) &
 558                          (IEVENT_GRSC | IEVENT_GTSC)))
 559                         cpu_relax();
 560         }
 561
 562         /* Disable Rx and Tx */
 563         tempval = gfar_read(&regs->maccfg1);
 564         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 565         gfar_write(&regs->maccfg1, tempval);
 566 }
 567
 568 void stop_gfar(struct net_device *dev)
 569 {
 570         struct gfar_private *priv = netdev_priv(dev);
 571         struct gfar __iomem *regs = priv->regs;
 572         unsigned long flags;
 573
 574         phy_stop(priv->phydev);
 575
 576         /* Lock it down */
 577         spin_lock_irqsave(&priv->txlock, flags);
 578         spin_lock(&priv->rxlock);
 579
 580         gfar_halt(dev);
 581
 582         spin_unlock(&priv->rxlock);
 583         spin_unlock_irqrestore(&priv->txlock, flags);
 584
 585         /* Free the IRQs */
 586         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 587                 free_irq(priv->interruptError, dev);
 588                 free_irq(priv->interruptTransmit, dev);
 589                 free_irq(priv->interruptReceive, dev);
 590         } else {
 591                 free_irq(priv->interruptTransmit, dev);
 592         }
 593
 594         free_skb_resources(priv);
 595
 596         dma_free_coherent(&dev->dev,
 597                         sizeof(struct txbd8)*priv->tx_ring_size
 598                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 599                         priv->tx_bd_base,
 600                         gfar_read(&regs->tbase0));
 601 }
 602
 603 /* If there are any tx skbs or rx skbs still around, free them.
 604  * Then free tx_skbuff and rx_skbuff */
 605 static void free_skb_resources(struct gfar_private *priv)
 606 {
 607         struct rxbd8 *rxbdp;
 608         struct txbd8 *txbdp;
 609         int i;
 610
 611         /* Go through all the buffer descriptors and free their data buffers */
 612         txbdp = priv->tx_bd_base;
 613
 614         for (i = 0; i < priv->tx_ring_size; i++) {
 615
 616                 if (priv->tx_skbuff[i]) {
 617                         dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
 618                                         txbdp->length,
 619                                         DMA_TO_DEVICE);
 620                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 621                         priv->tx_skbuff[i] = NULL;
 622                 }
 623
 624                 txbdp++;
 625         }
 626
 627         kfree(priv->tx_skbuff);
 628
 629         rxbdp = priv->rx_bd_base;
 630
 631         /* rx_skbuff is not guaranteed to be allocated, so only
 632          * free it and its contents if it is allocated */
 633         if(priv->rx_skbuff != NULL) {
 634                 for (i = 0; i < priv->rx_ring_size; i++) {
 635                         if (priv->rx_skbuff[i]) {
 636                                 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
 637                                                 priv->rx_buffer_size,
 638                                                 DMA_FROM_DEVICE);
 639
 640                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 641                                 priv->rx_skbuff[i] = NULL;
 642                         }
 643
 644                         rxbdp->status = 0;
 645                         rxbdp->length = 0;
 646                         rxbdp->bufPtr = 0;
 647
 648                         rxbdp++;
 649                 }
 650
 651                 kfree(priv->rx_skbuff);
 652         }
 653 }
 654
 655 void gfar_start(struct net_device *dev)
 656 {
 657         struct gfar_private *priv = netdev_priv(dev);
 658         struct gfar __iomem *regs = priv->regs;
 659         u32 tempval;
 660
 661         /* Enable Rx and Tx in MACCFG1 */
 662         tempval = gfar_read(&regs->maccfg1);
 663         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 664         gfar_write(&regs->maccfg1, tempval);
 665
 666         /* Initialize DMACTRL to have WWR and WOP */
 667         tempval = gfar_read(&priv->regs->dmactrl);
 668         tempval |= DMACTRL_INIT_SETTINGS;
 669         gfar_write(&priv->regs->dmactrl, tempval);
 670
 671         /* Make sure we aren't stopped */
 672         tempval = gfar_read(&priv->regs->dmactrl);
 673         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 674         gfar_write(&priv->regs->dmactrl, tempval);
 675
 676         /* Clear THLT/RHLT, so that the DMA starts polling now */
 677         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 678         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 679
 680         /* Unmask the interrupts we look for */
 681         gfar_write(&regs->imask, IMASK_DEFAULT);
 682 }
 683
 684 /* Bring the controller up and running */
 685 int startup_gfar(struct net_device *dev)
 686 {
 687         struct txbd8 *txbdp;
 688         struct rxbd8 *rxbdp;
 689         dma_addr_t addr = 0;
 690         unsigned long vaddr;
 691         int i;
 692         struct gfar_private *priv = netdev_priv(dev);
 693         struct gfar __iomem *regs = priv->regs;
 694         int err = 0;
 695         u32 rctrl = 0;
 696         u32 attrs = 0;
 697
 698         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 699
 700         /* Allocate memory for the buffer descriptors */
 701         vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
 702                         sizeof (struct txbd8) * priv->tx_ring_size +
 703                         sizeof (struct rxbd8) * priv->rx_ring_size,
 704                         &addr, GFP_KERNEL);
 705
 706         if (vaddr == 0) {
 707                 if (netif_msg_ifup(priv))
 708                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 709                                         dev->name);
 710                 return -ENOMEM;
 711         }
 712
 713         priv->tx_bd_base = (struct txbd8 *) vaddr;
 714
 715         /* enet DMA only understands physical addresses */
 716         gfar_write(&regs->tbase0, addr);
 717
 718         /* Start the rx descriptor ring where the tx ring leaves off */
 719         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 720         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 721         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 722         gfar_write(&regs->rbase0, addr);
 723
 724         /* Setup the skbuff rings */
 725         priv->tx_skbuff =
 726             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 727                                         priv->tx_ring_size, GFP_KERNEL);
 728
 729         if (NULL == priv->tx_skbuff) {
 730                 if (netif_msg_ifup(priv))
 731                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 732                                         dev->name);
 733                 err = -ENOMEM;
 734                 goto tx_skb_fail;
 735         }
 736
 737         for (i = 0; i < priv->tx_ring_size; i++)
 738                 priv->tx_skbuff[i] = NULL;
 739
 740         priv->rx_skbuff =
 741             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 742                                         priv->rx_ring_size, GFP_KERNEL);
 743
 744         if (NULL == priv->rx_skbuff) {
 745                 if (netif_msg_ifup(priv))
 746                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 747                                         dev->name);
 748                 err = -ENOMEM;
 749                 goto rx_skb_fail;
 750         }
 751
 752         for (i = 0; i < priv->rx_ring_size; i++)
 753                 priv->rx_skbuff[i] = NULL;
 754
 755         /* Initialize some variables in our dev structure */
 756         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 757         priv->cur_rx = priv->rx_bd_base;
 758         priv->skb_curtx = priv->skb_dirtytx = 0;
 759         priv->skb_currx = 0;
 760
 761         /* Initialize Transmit Descriptor Ring */
 762         txbdp = priv->tx_bd_base;
 763         for (i = 0; i < priv->tx_ring_size; i++) {
 764                 txbdp->status = 0;
 765                 txbdp->length = 0;
 766                 txbdp->bufPtr = 0;
 767                 txbdp++;
 768         }
 769
 770         /* Set the last descriptor in the ring to indicate wrap */
 771         txbdp--;
 772         txbdp->status |= TXBD_WRAP;
 773
 774         rxbdp = priv->rx_bd_base;
 775         for (i = 0; i < priv->rx_ring_size; i++) {
 776                 struct sk_buff *skb;
 777
 778                 skb = gfar_new_skb(dev);
 779
 780                 if (!skb) {
 781                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
 782                                         dev->name);
 783
 784                         goto err_rxalloc_fail;
 785                 }
 786
 787                 priv->rx_skbuff[i] = skb;
 788
 789                 gfar_new_rxbdp(dev, rxbdp, skb);
 790
 791                 rxbdp++;
 792         }
 793
 794         /* Set the last descriptor in the ring to wrap */
 795         rxbdp--;
 796         rxbdp->status |= RXBD_WRAP;
 797
 798         /* If the device has multiple interrupts, register for
 799          * them.  Otherwise, only register for the one */
 800         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 801                 /* Install our interrupt handlers for Error,
 802                  * Transmit, and Receive */
 803                 if (request_irq(priv->interruptError, gfar_error,
 804                                 0, "enet_error", dev) < 0) {
 805                         if (netif_msg_intr(priv))
 806                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 807                                         dev->name, priv->interruptError);
 808
 809                         err = -1;
 810                         goto err_irq_fail;
 811                 }
 812
 813                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 814                                 0, "enet_tx", dev) < 0) {
 815                         if (netif_msg_intr(priv))
 816                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 817                                         dev->name, priv->interruptTransmit);
 818
 819                         err = -1;
 820
 821                         goto tx_irq_fail;
 822                 }
 823
 824                 if (request_irq(priv->interruptReceive, gfar_receive,
 825                                 0, "enet_rx", dev) < 0) {
 826                         if (netif_msg_intr(priv))
 827                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 828                                                 dev->name, priv->interruptReceive);
 829
 830                         err = -1;
 831                         goto rx_irq_fail;
 832                 }
 833         } else {
 834                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 835                                 0, "gfar_interrupt", dev) < 0) {
 836                         if (netif_msg_intr(priv))
 837                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 838                                         dev->name, priv->interruptError);
 839
 840                         err = -1;
 841                         goto err_irq_fail;
 842                 }
 843         }
 844
 845         phy_start(priv->phydev);
 846
 847         /* Configure the coalescing support */
 848         if (priv->txcoalescing)
 849                 gfar_write(&regs->txic,
 850                            mk_ic_value(priv->txcount, priv->txtime));
 851         else
 852                 gfar_write(&regs->txic, 0);
 853
 854         if (priv->rxcoalescing)
 855                 gfar_write(&regs->rxic,
 856                            mk_ic_value(priv->rxcount, priv->rxtime));
 857         else
 858                 gfar_write(&regs->rxic, 0);
 859
 860         if (priv->rx_csum_enable)
 861                 rctrl |= RCTRL_CHECKSUMMING;
 862
 863         if (priv->extended_hash) {
 864                 rctrl |= RCTRL_EXTHASH;
 865
 866                 gfar_clear_exact_match(dev);
 867                 rctrl |= RCTRL_EMEN;
 868         }
 869
 870         if (priv->vlan_enable)
 871                 rctrl |= RCTRL_VLAN;
 872
 873         if (priv->padding) {
 874                 rctrl &= ~RCTRL_PAL_MASK;
 875                 rctrl |= RCTRL_PADDING(priv->padding);
 876         }
 877
 878         /* Init rctrl based on our settings */
 879         gfar_write(&priv->regs->rctrl, rctrl);
 880
 881         if (dev->features & NETIF_F_IP_CSUM)
 882                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 883
 884         /* Set the extraction length and index */
 885         attrs = ATTRELI_EL(priv->rx_stash_size) |
 886                 ATTRELI_EI(priv->rx_stash_index);
 887
 888         gfar_write(&priv->regs->attreli, attrs);
 889
 890         /* Start with defaults, and add stashing or locking
 891          * depending on the approprate variables */
 892         attrs = ATTR_INIT_SETTINGS;
 893
 894         if (priv->bd_stash_en)
 895                 attrs |= ATTR_BDSTASH;
 896
 897         if (priv->rx_stash_size != 0)
 898                 attrs |= ATTR_BUFSTASH;
 899
 900         gfar_write(&priv->regs->attr, attrs);
 901
 902         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
 903         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
 904         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 905
 906         /* Start the controller */
 907         gfar_start(dev);
 908
 909         return 0;
 910
 911 rx_irq_fail:
 912         free_irq(priv->interruptTransmit, dev);
 913 tx_irq_fail:
 914         free_irq(priv->interruptError, dev);
 915 err_irq_fail:
 916 err_rxalloc_fail:
 917 rx_skb_fail:
 918         free_skb_resources(priv);
 919 tx_skb_fail:
 920         dma_free_coherent(&dev->dev,
 921                         sizeof(struct txbd8)*priv->tx_ring_size
 922                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 923                         priv->tx_bd_base,
 924                         gfar_read(&regs->tbase0));
 925
 926         return err;
 927 }
 928
 929 /* Called when something needs to use the ethernet device */
 930 /* Returns 0 for success. */
 931 static int gfar_enet_open(struct net_device *dev)
 932 {
 933         struct gfar_private *priv = netdev_priv(dev);
 934         int err;
 935
 936         napi_enable(&priv->napi);
 937
 938         /* Initialize a bunch of registers */
 939         init_registers(dev);
 940
 941         gfar_set_mac_address(dev);
 942
 943         err = init_phy(dev);
 944
 945         if(err) {
 946                 napi_disable(&priv->napi);
 947                 return err;
 948         }
 949
 950         err = startup_gfar(dev);
 951         if (err) {
 952                 napi_disable(&priv->napi);
 953                 return err;
 954         }
 955
 956         netif_start_queue(dev);
 957
 958         return err;
 959 }
 960
 961 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
 962 {
 963         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
 964
 965         memset(fcb, 0, GMAC_FCB_LEN);
 966
 967         return fcb;
 968 }
 969
 970 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 971 {
 972         u8 flags = 0;
 973
 974         /* If we're here, it's a IP packet with a TCP or UDP
 975          * payload.  We set it to checksum, using a pseudo-header
 976          * we provide
 977          */
 978         flags = TXFCB_DEFAULT;
 979
 980         /* Tell the controller what the protocol is */
 981         /* And provide the already calculated phcs */
 982         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
 983                 flags |= TXFCB_UDP;
 984                 fcb->phcs = udp_hdr(skb)->check;
 985         } else
 986                 fcb->phcs = tcp_hdr(skb)->check;
 987
 988         /* l3os is the distance between the start of the
 989          * frame (skb->data) and the start of the IP hdr.
 990          * l4os is the distance between the start of the
 991          * l3 hdr and the l4 hdr */
 992         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
 993         fcb->l4os = skb_network_header_len(skb);
 994
 995         fcb->flags = flags;
 996 }
 997
 998 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
 999 {
1000         fcb->flags |= TXFCB_VLN;
1001         fcb->vlctl = vlan_tx_tag_get(skb);
1002 }
1003
1004 /* This is called by the kernel when a frame is ready for transmission. */
1005 /* It is pointed to by the dev->hard_start_xmit function pointer */
1006 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1007 {
1008         struct gfar_private *priv = netdev_priv(dev);
1009         struct txfcb *fcb = NULL;
1010         struct txbd8 *txbdp;
1011         u16 status;
1012         unsigned long flags;
1013
1014         /* Update transmit stats */
1015         dev->stats.tx_bytes += skb->len;
1016
1017         /* Lock priv now */
1018         spin_lock_irqsave(&priv->txlock, flags);
1019
1020         /* Point at the first free tx descriptor */
1021         txbdp = priv->cur_tx;
1022
1023         /* Clear all but the WRAP status flags */
1024         status = txbdp->status & TXBD_WRAP;
1025
1026         /* Set up checksumming */
1027         if (likely((dev->features & NETIF_F_IP_CSUM)
1028                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1029                 fcb = gfar_add_fcb(skb, txbdp);
1030                 status |= TXBD_TOE;
1031                 gfar_tx_checksum(skb, fcb);
1032         }
1033
1034         if (priv->vlan_enable &&
1035                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1036                 if (unlikely(NULL == fcb)) {
1037                         fcb = gfar_add_fcb(skb, txbdp);
1038                         status |= TXBD_TOE;
1039                 }
1040
1041                 gfar_tx_vlan(skb, fcb);
1042         }
1043
1044         /* Set buffer length and pointer */
1045         txbdp->length = skb->len;
1046         txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1047                         skb->len, DMA_TO_DEVICE);
1048
1049         /* Save the skb pointer so we can free it later */
1050         priv->tx_skbuff[priv->skb_curtx] = skb;
1051
1052         /* Update the current skb pointer (wrapping if this was the last) */
1053         priv->skb_curtx =
1054             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1055
1056         /* Flag the BD as interrupt-causing */
1057         status |= TXBD_INTERRUPT;
1058
1059         /* Flag the BD as ready to go, last in frame, and  */
1060         /* in need of CRC */
1061         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1062
1063         dev->trans_start = jiffies;
1064
1065         /* The powerpc-specific eieio() is used, as wmb() has too strong
1066          * semantics (it requires synchronization between cacheable and
1067          * uncacheable mappings, which eieio doesn't provide and which we
1068          * don't need), thus requiring a more expensive sync instruction.  At
1069          * some point, the set of architecture-independent barrier functions
1070          * should be expanded to include weaker barriers.
1071          */
1072
1073         eieio();
1074         txbdp->status = status;
1075
1076         /* If this was the last BD in the ring, the next one */
1077         /* is at the beginning of the ring */
1078         if (txbdp->status & TXBD_WRAP)
1079                 txbdp = priv->tx_bd_base;
1080         else
1081                 txbdp++;
1082
1083         /* If the next BD still needs to be cleaned up, then the bds
1084            are full.  We need to tell the kernel to stop sending us stuff. */
1085         if (txbdp == priv->dirty_tx) {
1086                 netif_stop_queue(dev);
1087
1088                 dev->stats.tx_fifo_errors++;
1089         }
1090
1091         /* Update the current txbd to the next one */
1092         priv->cur_tx = txbdp;
1093
1094         /* Tell the DMA to go go go */
1095         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1096
1097         /* Unlock priv */
1098         spin_unlock_irqrestore(&priv->txlock, flags);
1099
1100         return 0;
1101 }
1102
1103 /* Stops the kernel queue, and halts the controller */
1104 static int gfar_close(struct net_device *dev)
1105 {
1106         struct gfar_private *priv = netdev_priv(dev);
1107
1108         napi_disable(&priv->napi);
1109
1110         stop_gfar(dev);
1111
1112         /* Disconnect from the PHY */
1113         phy_disconnect(priv->phydev);
1114         priv->phydev = NULL;
1115
1116         netif_stop_queue(dev);
1117
1118         return 0;
1119 }
1120
1121 /* Changes the mac address if the controller is not running. */
1122 static int gfar_set_mac_address(struct net_device *dev)
1123 {
1124         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1125
1126         return 0;
1127 }
1128
1129
1130 /* Enables and disables VLAN insertion/extraction */
1131 static void gfar_vlan_rx_register(struct net_device *dev,
1132                 struct vlan_group *grp)
1133 {
1134         struct gfar_private *priv = netdev_priv(dev);
1135         unsigned long flags;
1136         u32 tempval;
1137
1138         spin_lock_irqsave(&priv->rxlock, flags);
1139
1140         priv->vlgrp = grp;
1141
1142         if (grp) {
1143                 /* Enable VLAN tag insertion */
1144                 tempval = gfar_read(&priv->regs->tctrl);
1145                 tempval |= TCTRL_VLINS;
1146
1147                 gfar_write(&priv->regs->tctrl, tempval);
1148
1149                 /* Enable VLAN tag extraction */
1150                 tempval = gfar_read(&priv->regs->rctrl);
1151                 tempval |= RCTRL_VLEX;
1152                 gfar_write(&priv->regs->rctrl, tempval);
1153         } else {
1154                 /* Disable VLAN tag insertion */
1155                 tempval = gfar_read(&priv->regs->tctrl);
1156                 tempval &= ~TCTRL_VLINS;
1157                 gfar_write(&priv->regs->tctrl, tempval);
1158
1159                 /* Disable VLAN tag extraction */
1160                 tempval = gfar_read(&priv->regs->rctrl);
1161                 tempval &= ~RCTRL_VLEX;
1162                 gfar_write(&priv->regs->rctrl, tempval);
1163         }
1164
1165         spin_unlock_irqrestore(&priv->rxlock, flags);
1166 }
1167
1168 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1169 {
1170         int tempsize, tempval;
1171         struct gfar_private *priv = netdev_priv(dev);
1172         int oldsize = priv->rx_buffer_size;
1173         int frame_size = new_mtu + ETH_HLEN;
1174
1175         if (priv->vlan_enable)
1176                 frame_size += VLAN_HLEN;
1177
1178         if (gfar_uses_fcb(priv))
1179                 frame_size += GMAC_FCB_LEN;
1180
1181         frame_size += priv->padding;
1182
1183         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1184                 if (netif_msg_drv(priv))
1185                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1186                                         dev->name);
1187                 return -EINVAL;
1188         }
1189
1190         tempsize =
1191             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1192             INCREMENTAL_BUFFER_SIZE;
1193
1194         /* Only stop and start the controller if it isn't already
1195          * stopped, and we changed something */
1196         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1197                 stop_gfar(dev);
1198
1199         priv->rx_buffer_size = tempsize;
1200
1201         dev->mtu = new_mtu;
1202
1203         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1204         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1205
1206         /* If the mtu is larger than the max size for standard
1207          * ethernet frames (ie, a jumbo frame), then set maccfg2
1208          * to allow huge frames, and to check the length */
1209         tempval = gfar_read(&priv->regs->maccfg2);
1210
1211         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1212                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1213         else
1214                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1215
1216         gfar_write(&priv->regs->maccfg2, tempval);
1217
1218         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1219                 startup_gfar(dev);
1220
1221         return 0;
1222 }
1223
1224 /* gfar_timeout gets called when a packet has not been
1225  * transmitted after a set amount of time.
1226  * For now, assume that clearing out all the structures, and
1227  * starting over will fix the problem. */
1228 static void gfar_timeout(struct net_device *dev)
1229 {
1230         dev->stats.tx_errors++;
1231
1232         if (dev->flags & IFF_UP) {
1233                 stop_gfar(dev);
1234                 startup_gfar(dev);
1235         }
1236
1237         netif_tx_schedule_all(dev);
1238 }
1239
1240 /* Interrupt Handler for Transmit complete */
1241 static int gfar_clean_tx_ring(struct net_device *dev)
1242 {
1243         struct txbd8 *bdp;
1244         struct gfar_private *priv = netdev_priv(dev);
1245         int howmany = 0;
1246
1247         bdp = priv->dirty_tx;
1248         while ((bdp->status & TXBD_READY) == 0) {
1249                 /* If dirty_tx and cur_tx are the same, then either the */
1250                 /* ring is empty or full now (it could only be full in the beginning, */
1251                 /* obviously).  If it is empty, we are done. */
1252                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1253                         break;
1254
1255                 howmany++;
1256
1257                 /* Deferred means some collisions occurred during transmit, */
1258                 /* but we eventually sent the packet. */
1259                 if (bdp->status & TXBD_DEF)
1260                         dev->stats.collisions++;
1261
1262                 /* Free the sk buffer associated with this TxBD */
1263                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1264
1265                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1266                 priv->skb_dirtytx =
1267                     (priv->skb_dirtytx +
1268                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1269
1270                 /* Clean BD length for empty detection */
1271                 bdp->length = 0;
1272
1273                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1274                 if (bdp->status & TXBD_WRAP)
1275                         bdp = priv->tx_bd_base;
1276                 else
1277                         bdp++;
1278
1279                 /* Move dirty_tx to be the next bd */
1280                 priv->dirty_tx = bdp;
1281
1282                 /* We freed a buffer, so now we can restart transmission */
1283                 if (netif_queue_stopped(dev))
1284                         netif_wake_queue(dev);
1285         } /* while ((bdp->status & TXBD_READY) == 0) */
1286
1287         dev->stats.tx_packets += howmany;
1288
1289         return howmany;
1290 }
1291
1292 /* Interrupt Handler for Transmit complete */
1293 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1294 {
1295         struct net_device *dev = (struct net_device *) dev_id;
1296         struct gfar_private *priv = netdev_priv(dev);
1297
1298         /* Clear IEVENT */
1299         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1300
1301         /* Lock priv */
1302         spin_lock(&priv->txlock);
1303
1304         gfar_clean_tx_ring(dev);
1305
1306         /* If we are coalescing the interrupts, reset the timer */
1307         /* Otherwise, clear it */
1308         if (likely(priv->txcoalescing)) {
1309                 gfar_write(&priv->regs->txic, 0);
1310                 gfar_write(&priv->regs->txic,
1311                            mk_ic_value(priv->txcount, priv->txtime));
1312         }
1313
1314         spin_unlock(&priv->txlock);
1315
1316         return IRQ_HANDLED;
1317 }
1318
1319 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1320                 struct sk_buff *skb)
1321 {
1322         struct gfar_private *priv = netdev_priv(dev);
1323         u32 * status_len = (u32 *)bdp;
1324         u16 flags;
1325
1326         bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1327                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1328
1329         flags = RXBD_EMPTY | RXBD_INTERRUPT;
1330
1331         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1332                 flags |= RXBD_WRAP;
1333
1334         eieio();
1335
1336         *status_len = (u32)flags << 16;
1337 }
1338
1339
1340 struct sk_buff * gfar_new_skb(struct net_device *dev)
1341 {
1342         unsigned int alignamount;
1343         struct gfar_private *priv = netdev_priv(dev);
1344         struct sk_buff *skb = NULL;
1345
1346         /* We have to allocate the skb, so keep trying till we succeed */
1347         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1348
1349         if (!skb)
1350                 return NULL;
1351
1352         alignamount = RXBUF_ALIGNMENT -
1353                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1354
1355         /* We need the data buffer to be aligned properly.  We will reserve
1356          * as many bytes as needed to align the data properly
1357          */
1358         skb_reserve(skb, alignamount);
1359
1360         return skb;
1361 }
1362
1363 static inline void count_errors(unsigned short status, struct net_device *dev)
1364 {
1365         struct gfar_private *priv = netdev_priv(dev);
1366         struct net_device_stats *stats = &dev->stats;
1367         struct gfar_extra_stats *estats = &priv->extra_stats;
1368
1369         /* If the packet was truncated, none of the other errors
1370          * matter */
1371         if (status & RXBD_TRUNCATED) {
1372                 stats->rx_length_errors++;
1373
1374                 estats->rx_trunc++;
1375
1376                 return;
1377         }
1378         /* Count the errors, if there were any */
1379         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1380                 stats->rx_length_errors++;
1381
1382                 if (status & RXBD_LARGE)
1383                         estats->rx_large++;
1384                 else
1385                         estats->rx_short++;
1386         }
1387         if (status & RXBD_NONOCTET) {
1388                 stats->rx_frame_errors++;
1389                 estats->rx_nonoctet++;
1390         }
1391         if (status & RXBD_CRCERR) {
1392                 estats->rx_crcerr++;
1393                 stats->rx_crc_errors++;
1394         }
1395         if (status & RXBD_OVERRUN) {
1396                 estats->rx_overrun++;
1397                 stats->rx_crc_errors++;
1398         }
1399 }
1400
1401 irqreturn_t gfar_receive(int irq, void *dev_id)
1402 {
1403         struct net_device *dev = (struct net_device *) dev_id;
1404         struct gfar_private *priv = netdev_priv(dev);
1405         u32 tempval;
1406
1407         /* support NAPI */
1408         /* Clear IEVENT, so interrupts aren't called again
1409          * because of the packets that have already arrived */
1410         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1411
1412         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1413                 tempval = gfar_read(&priv->regs->imask);
1414                 tempval &= IMASK_RTX_DISABLED;
1415                 gfar_write(&priv->regs->imask, tempval);
1416
1417                 __netif_rx_schedule(dev, &priv->napi);
1418         } else {
1419                 if (netif_msg_rx_err(priv))
1420                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1421                                 dev->name, gfar_read(&priv->regs->ievent),
1422                                 gfar_read(&priv->regs->imask));
1423         }
1424
1425         return IRQ_HANDLED;
1426 }
1427
1428 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1429 {
1430         /* If valid headers were found, and valid sums
1431          * were verified, then we tell the kernel that no
1432          * checksumming is necessary.  Otherwise, it is */
1433         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1434                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1435         else
1436                 skb->ip_summed = CHECKSUM_NONE;
1437 }
1438
1439
1440 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1441 {
1442         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1443
1444         /* Remove the FCB from the skb */
1445         skb_pull(skb, GMAC_FCB_LEN);
1446
1447         return fcb;
1448 }
1449
1450 /* gfar_process_frame() -- handle one incoming packet if skb
1451  * isn't NULL.  */
1452 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1453                 int length)
1454 {
1455         struct gfar_private *priv = netdev_priv(dev);
1456         struct rxfcb *fcb = NULL;
1457
1458         if (NULL == skb) {
1459                 if (netif_msg_rx_err(priv))
1460                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1461                 dev->stats.rx_dropped++;
1462                 priv->extra_stats.rx_skbmissing++;
1463         } else {
1464                 int ret;
1465
1466                 /* Prep the skb for the packet */
1467                 skb_put(skb, length);
1468
1469                 /* Grab the FCB if there is one */
1470                 if (gfar_uses_fcb(priv))
1471                         fcb = gfar_get_fcb(skb);
1472
1473                 /* Remove the padded bytes, if there are any */
1474                 if (priv->padding)
1475                         skb_pull(skb, priv->padding);
1476
1477                 if (priv->rx_csum_enable)
1478                         gfar_rx_checksum(skb, fcb);
1479
1480                 /* Tell the skb what kind of packet this is */
1481                 skb->protocol = eth_type_trans(skb, dev);
1482
1483                 /* Send the packet up the stack */
1484                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1485                         ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1486                                                        fcb->vlctl);
1487                 } else
1488                         ret = netif_receive_skb(skb);
1489
1490                 if (NET_RX_DROP == ret)
1491                         priv->extra_stats.kernel_dropped++;
1492         }
1493
1494         return 0;
1495 }
1496
1497 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1498  *   until the budget/quota has been reached. Returns the number
1499  *   of frames handled
1500  */
1501 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1502 {
1503         struct rxbd8 *bdp;
1504         struct sk_buff *skb;
1505         u16 pkt_len;
1506         int howmany = 0;
1507         struct gfar_private *priv = netdev_priv(dev);
1508
1509         /* Get the first full descriptor */
1510         bdp = priv->cur_rx;
1511
1512         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1513                 struct sk_buff *newskb;
1514                 rmb();
1515
1516                 /* Add another skb for the future */
1517                 newskb = gfar_new_skb(dev);
1518
1519                 skb = priv->rx_skbuff[priv->skb_currx];
1520
1521                 /* We drop the frame if we failed to allocate a new buffer */
1522                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1523                                  bdp->status & RXBD_ERR)) {
1524                         count_errors(bdp->status, dev);
1525
1526                         if (unlikely(!newskb))
1527                                 newskb = skb;
1528
1529                         if (skb) {
1530                                 dma_unmap_single(&priv->dev->dev,
1531                                                 bdp->bufPtr,
1532                                                 priv->rx_buffer_size,
1533                                                 DMA_FROM_DEVICE);
1534
1535                                 dev_kfree_skb_any(skb);
1536                         }
1537                 } else {
1538                         /* Increment the number of packets */
1539                         dev->stats.rx_packets++;
1540                         howmany++;
1541
1542                         /* Remove the FCS from the packet length */
1543                         pkt_len = bdp->length - 4;
1544
1545                         gfar_process_frame(dev, skb, pkt_len);
1546
1547                         dev->stats.rx_bytes += pkt_len;
1548                 }
1549
1550                 dev->last_rx = jiffies;
1551
1552                 priv->rx_skbuff[priv->skb_currx] = newskb;
1553
1554                 /* Setup the new bdp */
1555                 gfar_new_rxbdp(dev, bdp, newskb);
1556
1557                 /* Update to the next pointer */
1558                 if (bdp->status & RXBD_WRAP)
1559                         bdp = priv->rx_bd_base;
1560                 else
1561                         bdp++;
1562
1563                 /* update to point at the next skb */
1564                 priv->skb_currx =
1565                     (priv->skb_currx + 1) &
1566                     RX_RING_MOD_MASK(priv->rx_ring_size);
1567         }
1568
1569         /* Update the current rxbd pointer to be the next one */
1570         priv->cur_rx = bdp;
1571
1572         return howmany;
1573 }
1574
1575 static int gfar_poll(struct napi_struct *napi, int budget)
1576 {
1577         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1578         struct net_device *dev = priv->dev;
1579         int howmany;
1580         unsigned long flags;
1581
1582         /* If we fail to get the lock, don't bother with the TX BDs */
1583         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1584                 gfar_clean_tx_ring(dev);
1585                 spin_unlock_irqrestore(&priv->txlock, flags);
1586         }
1587
1588         howmany = gfar_clean_rx_ring(dev, budget);
1589
1590         if (howmany < budget) {
1591                 netif_rx_complete(dev, napi);
1592
1593                 /* Clear the halt bit in RSTAT */
1594                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1595
1596                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1597
1598                 /* If we are coalescing interrupts, update the timer */
1599                 /* Otherwise, clear it */
1600                 if (likely(priv->rxcoalescing)) {
1601                         gfar_write(&priv->regs->rxic, 0);
1602                         gfar_write(&priv->regs->rxic,
1603                                    mk_ic_value(priv->rxcount, priv->rxtime));
1604                 }
1605         }
1606
1607         return howmany;
1608 }
1609
1610 #ifdef CONFIG_NET_POLL_CONTROLLER
1611 /*
1612  * Polling 'interrupt' - used by things like netconsole to send skbs
1613  * without having to re-enable interrupts. It's not called while
1614  * the interrupt routine is executing.
1615  */
1616 static void gfar_netpoll(struct net_device *dev)
1617 {
1618         struct gfar_private *priv = netdev_priv(dev);
1619
1620         /* If the device has multiple interrupts, run tx/rx */
1621         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1622                 disable_irq(priv->interruptTransmit);
1623                 disable_irq(priv->interruptReceive);
1624                 disable_irq(priv->interruptError);
1625                 gfar_interrupt(priv->interruptTransmit, dev);
1626                 enable_irq(priv->interruptError);
1627                 enable_irq(priv->interruptReceive);
1628                 enable_irq(priv->interruptTransmit);
1629         } else {
1630                 disable_irq(priv->interruptTransmit);
1631                 gfar_interrupt(priv->interruptTransmit, dev);
1632                 enable_irq(priv->interruptTransmit);
1633         }
1634 }
1635 #endif
1636
1637 /* The interrupt handler for devices with one interrupt */
1638 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1639 {
1640         struct net_device *dev = dev_id;
1641         struct gfar_private *priv = netdev_priv(dev);
1642
1643         /* Save ievent for future reference */
1644         u32 events = gfar_read(&priv->regs->ievent);
1645
1646         /* Check for reception */
1647         if (events & IEVENT_RX_MASK)
1648                 gfar_receive(irq, dev_id);
1649
1650         /* Check for transmit completion */
1651         if (events & IEVENT_TX_MASK)
1652                 gfar_transmit(irq, dev_id);
1653
1654         /* Check for errors */
1655         if (events & IEVENT_ERR_MASK)
1656                 gfar_error(irq, dev_id);
1657
1658         return IRQ_HANDLED;
1659 }
1660
1661 /* Called every time the controller might need to be made
1662  * aware of new link state.  The PHY code conveys this
1663  * information through variables in the phydev structure, and this
1664  * function converts those variables into the appropriate
1665  * register values, and can bring down the device if needed.
1666  */
1667 static void adjust_link(struct net_device *dev)
1668 {
1669         struct gfar_private *priv = netdev_priv(dev);
1670         struct gfar __iomem *regs = priv->regs;
1671         unsigned long flags;
1672         struct phy_device *phydev = priv->phydev;
1673         int new_state = 0;
1674
1675         spin_lock_irqsave(&priv->txlock, flags);
1676         if (phydev->link) {
1677                 u32 tempval = gfar_read(&regs->maccfg2);
1678                 u32 ecntrl = gfar_read(&regs->ecntrl);
1679
1680                 /* Now we make sure that we can be in full duplex mode.
1681                  * If not, we operate in half-duplex mode. */
1682                 if (phydev->duplex != priv->oldduplex) {
1683                         new_state = 1;
1684                         if (!(phydev->duplex))
1685                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1686                         else
1687                                 tempval |= MACCFG2_FULL_DUPLEX;
1688
1689                         priv->oldduplex = phydev->duplex;
1690                 }
1691
1692                 if (phydev->speed != priv->oldspeed) {
1693                         new_state = 1;
1694                         switch (phydev->speed) {
1695                         case 1000:
1696                                 tempval =
1697                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1698                                 break;
1699                         case 100:
1700                         case 10:
1701                                 tempval =
1702                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1703
1704                                 /* Reduced mode distinguishes
1705                                  * between 10 and 100 */
1706                                 if (phydev->speed == SPEED_100)
1707                                         ecntrl |= ECNTRL_R100;
1708                                 else
1709                                         ecntrl &= ~(ECNTRL_R100);
1710                                 break;
1711                         default:
1712                                 if (netif_msg_link(priv))
1713                                         printk(KERN_WARNING
1714                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1715                                                 dev->name, phydev->speed);
1716                                 break;
1717                         }
1718
1719                         priv->oldspeed = phydev->speed;
1720                 }
1721
1722                 gfar_write(&regs->maccfg2, tempval);
1723                 gfar_write(&regs->ecntrl, ecntrl);
1724
1725                 if (!priv->oldlink) {
1726                         new_state = 1;
1727                         priv->oldlink = 1;
1728                         netif_tx_schedule_all(dev);
1729                 }
1730         } else if (priv->oldlink) {
1731                 new_state = 1;
1732                 priv->oldlink = 0;
1733                 priv->oldspeed = 0;
1734                 priv->oldduplex = -1;
1735         }
1736
1737         if (new_state && netif_msg_link(priv))
1738                 phy_print_status(phydev);
1739
1740         spin_unlock_irqrestore(&priv->txlock, flags);
1741 }
1742
1743 /* Update the hash table based on the current list of multicast
1744  * addresses we subscribe to.  Also, change the promiscuity of
1745  * the device based on the flags (this function is called
1746  * whenever dev->flags is changed */
1747 static void gfar_set_multi(struct net_device *dev)
1748 {
1749         struct dev_mc_list *mc_ptr;
1750         struct gfar_private *priv = netdev_priv(dev);
1751         struct gfar __iomem *regs = priv->regs;
1752         u32 tempval;
1753
1754         if(dev->flags & IFF_PROMISC) {
1755                 /* Set RCTRL to PROM */
1756                 tempval = gfar_read(&regs->rctrl);
1757                 tempval |= RCTRL_PROM;
1758                 gfar_write(&regs->rctrl, tempval);
1759         } else {
1760                 /* Set RCTRL to not PROM */
1761                 tempval = gfar_read(&regs->rctrl);
1762                 tempval &= ~(RCTRL_PROM);
1763                 gfar_write(&regs->rctrl, tempval);
1764         }
1765
1766         if(dev->flags & IFF_ALLMULTI) {
1767                 /* Set the hash to rx all multicast frames */
1768                 gfar_write(&regs->igaddr0, 0xffffffff);
1769                 gfar_write(&regs->igaddr1, 0xffffffff);
1770                 gfar_write(&regs->igaddr2, 0xffffffff);
1771                 gfar_write(&regs->igaddr3, 0xffffffff);
1772                 gfar_write(&regs->igaddr4, 0xffffffff);
1773                 gfar_write(&regs->igaddr5, 0xffffffff);
1774                 gfar_write(&regs->igaddr6, 0xffffffff);
1775                 gfar_write(&regs->igaddr7, 0xffffffff);
1776                 gfar_write(&regs->gaddr0, 0xffffffff);
1777                 gfar_write(&regs->gaddr1, 0xffffffff);
1778                 gfar_write(&regs->gaddr2, 0xffffffff);
1779                 gfar_write(&regs->gaddr3, 0xffffffff);
1780                 gfar_write(&regs->gaddr4, 0xffffffff);
1781                 gfar_write(&regs->gaddr5, 0xffffffff);
1782                 gfar_write(&regs->gaddr6, 0xffffffff);
1783                 gfar_write(&regs->gaddr7, 0xffffffff);
1784         } else {
1785                 int em_num;
1786                 int idx;
1787
1788                 /* zero out the hash */
1789                 gfar_write(&regs->igaddr0, 0x0);
1790                 gfar_write(&regs->igaddr1, 0x0);
1791                 gfar_write(&regs->igaddr2, 0x0);
1792                 gfar_write(&regs->igaddr3, 0x0);
1793                 gfar_write(&regs->igaddr4, 0x0);
1794                 gfar_write(&regs->igaddr5, 0x0);
1795                 gfar_write(&regs->igaddr6, 0x0);
1796                 gfar_write(&regs->igaddr7, 0x0);
1797                 gfar_write(&regs->gaddr0, 0x0);
1798                 gfar_write(&regs->gaddr1, 0x0);
1799                 gfar_write(&regs->gaddr2, 0x0);
1800                 gfar_write(&regs->gaddr3, 0x0);
1801                 gfar_write(&regs->gaddr4, 0x0);
1802                 gfar_write(&regs->gaddr5, 0x0);
1803                 gfar_write(&regs->gaddr6, 0x0);
1804                 gfar_write(&regs->gaddr7, 0x0);
1805
1806                 /* If we have extended hash tables, we need to
1807                  * clear the exact match registers to prepare for
1808                  * setting them */
1809                 if (priv->extended_hash) {
1810                         em_num = GFAR_EM_NUM + 1;
1811                         gfar_clear_exact_match(dev);
1812                         idx = 1;
1813                 } else {
1814                         idx = 0;
1815                         em_num = 0;
1816                 }
1817
1818                 if(dev->mc_count == 0)
1819                         return;
1820
1821                 /* Parse the list, and set the appropriate bits */
1822                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1823                         if (idx < em_num) {
1824                                 gfar_set_mac_for_addr(dev, idx,
1825                                                 mc_ptr->dmi_addr);
1826                                 idx++;
1827                         } else
1828                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1829                 }
1830         }
1831
1832         return;
1833 }
1834
1835
1836 /* Clears each of the exact match registers to zero, so they
1837  * don't interfere with normal reception */
1838 static void gfar_clear_exact_match(struct net_device *dev)
1839 {
1840         int idx;
1841         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1842
1843         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1844                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1845 }
1846
1847 /* Set the appropriate hash bit for the given addr */
1848 /* The algorithm works like so:
1849  * 1) Take the Destination Address (ie the multicast address), and
1850  * do a CRC on it (little endian), and reverse the bits of the
1851  * result.
1852  * 2) Use the 8 most significant bits as a hash into a 256-entry
1853  * table.  The table is controlled through 8 32-bit registers:
1854  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1855  * gaddr7.  This means that the 3 most significant bits in the
1856  * hash index which gaddr register to use, and the 5 other bits
1857  * indicate which bit (assuming an IBM numbering scheme, which
1858  * for PowerPC (tm) is usually the case) in the register holds
1859  * the entry. */
1860 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1861 {
1862         u32 tempval;
1863         struct gfar_private *priv = netdev_priv(dev);
1864         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1865         int width = priv->hash_width;
1866         u8 whichbit = (result >> (32 - width)) & 0x1f;
1867         u8 whichreg = result >> (32 - width + 5);
1868         u32 value = (1 << (31-whichbit));
1869
1870         tempval = gfar_read(priv->hash_regs[whichreg]);
1871         tempval |= value;
1872         gfar_write(priv->hash_regs[whichreg], tempval);
1873
1874         return;
1875 }
1876
1877
1878 /* There are multiple MAC Address register pairs on some controllers
1879  * This function sets the numth pair to a given address
1880  */
1881 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1882 {
1883         struct gfar_private *priv = netdev_priv(dev);
1884         int idx;
1885         char tmpbuf[MAC_ADDR_LEN];
1886         u32 tempval;
1887         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1888
1889         macptr += num*2;
1890
1891         /* Now copy it into the mac registers backwards, cuz */
1892         /* little endian is silly */
1893         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1894                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1895
1896         gfar_write(macptr, *((u32 *) (tmpbuf)));
1897
1898         tempval = *((u32 *) (tmpbuf + 4));
1899
1900         gfar_write(macptr+1, tempval);
1901 }
1902
1903 /* GFAR error interrupt handler */
1904 static irqreturn_t gfar_error(int irq, void *dev_id)
1905 {
1906         struct net_device *dev = dev_id;
1907         struct gfar_private *priv = netdev_priv(dev);
1908
1909         /* Save ievent for future reference */
1910         u32 events = gfar_read(&priv->regs->ievent);
1911
1912         /* Clear IEVENT */
1913         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1914
1915         /* Hmm... */
1916         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1917                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1918                        dev->name, events, gfar_read(&priv->regs->imask));
1919
1920         /* Update the error counters */
1921         if (events & IEVENT_TXE) {
1922                 dev->stats.tx_errors++;
1923
1924                 if (events & IEVENT_LC)
1925                         dev->stats.tx_window_errors++;
1926                 if (events & IEVENT_CRL)
1927                         dev->stats.tx_aborted_errors++;
1928                 if (events & IEVENT_XFUN) {
1929                         if (netif_msg_tx_err(priv))
1930                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1931                                        "packet dropped.\n", dev->name);
1932                         dev->stats.tx_dropped++;
1933                         priv->extra_stats.tx_underrun++;
1934
1935                         /* Reactivate the Tx Queues */
1936                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1937                 }
1938                 if (netif_msg_tx_err(priv))
1939                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1940         }
1941         if (events & IEVENT_BSY) {
1942                 dev->stats.rx_errors++;
1943                 priv->extra_stats.rx_bsy++;
1944
1945                 gfar_receive(irq, dev_id);
1946
1947                 if (netif_msg_rx_err(priv))
1948                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1949                                dev->name, gfar_read(&priv->regs->rstat));
1950         }
1951         if (events & IEVENT_BABR) {
1952                 dev->stats.rx_errors++;
1953                 priv->extra_stats.rx_babr++;
1954
1955                 if (netif_msg_rx_err(priv))
1956                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1957         }
1958         if (events & IEVENT_EBERR) {
1959                 priv->extra_stats.eberr++;
1960                 if (netif_msg_rx_err(priv))
1961                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
1962         }
1963         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1964                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1965
1966         if (events & IEVENT_BABT) {
1967                 priv->extra_stats.tx_babt++;
1968                 if (netif_msg_tx_err(priv))
1969                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1970         }
1971         return IRQ_HANDLED;
1972 }
1973
1974 /* work with hotplug and coldplug */
1975 MODULE_ALIAS("platform:fsl-gianfar");
1976
1977 /* Structure for a device driver */
1978 static struct platform_driver gfar_driver = {
1979         .probe = gfar_probe,
1980         .remove = gfar_remove,
1981         .driver = {
1982                 .name = "fsl-gianfar",
1983                 .owner = THIS_MODULE,
1984         },
1985 };
1986
1987 static int __init gfar_init(void)
1988 {
1989         int err = gfar_mdio_init();
1990
1991         if (err)
1992                 return err;
1993
1994         err = platform_driver_register(&gfar_driver);
1995
1996         if (err)
1997                 gfar_mdio_exit();
1998
1999         return err;
2000 }
2001
2002 static void __exit gfar_exit(void)
2003 {
2004         platform_driver_unregister(&gfar_driver);
2005         gfar_mdio_exit();
2006 }
2007
2008 module_init(gfar_init);
2009 module_exit(gfar_exit);
2010