drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #include <linux/kernel.h>
  65 #include <linux/string.h>
  66 #include <linux/errno.h>
  67 #include <linux/unistd.h>
  68 #include <linux/slab.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/spinlock.h>
  77 #include <linux/mm.h>
  78 #include <linux/of_platform.h>
  79 #include <linux/ip.h>
  80 #include <linux/tcp.h>
  81 #include <linux/udp.h>
  82 #include <linux/in.h>
  83
  84 #include <asm/io.h>
  85 #include <asm/irq.h>
  86 #include <asm/uaccess.h>
  87 #include <linux/module.h>
  88 #include <linux/dma-mapping.h>
  89 #include <linux/crc32.h>
  90 #include <linux/mii.h>
  91 #include <linux/phy.h>
  92 #include <linux/phy_fixed.h>
  93 #include <linux/of.h>
  94
  95 #include "gianfar.h"
  96 #include "fsl_pq_mdio.h"
  97
  98 #define TX_TIMEOUT      (1*HZ)
  99 #undef BRIEF_GFAR_ERRORS
 100 #undef VERBOSE_GFAR_ERRORS
 101
 102 const char gfar_driver_name[] = "Gianfar Ethernet";
 103 const char gfar_driver_version[] = "1.3";
 104
 105 static int gfar_enet_open(struct net_device *dev);
 106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 107 static void gfar_reset_task(struct work_struct *work);
 108 static void gfar_timeout(struct net_device *dev);
 109 static int gfar_close(struct net_device *dev);
 110 struct sk_buff *gfar_new_skb(struct net_device *dev);
 111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 112                 struct sk_buff *skb);
 113 static int gfar_set_mac_address(struct net_device *dev);
 114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 115 static irqreturn_t gfar_error(int irq, void *dev_id);
 116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 118 static void adjust_link(struct net_device *dev);
 119 static void init_registers(struct net_device *dev);
 120 static int init_phy(struct net_device *dev);
 121 static int gfar_probe(struct of_device *ofdev,
 122                 const struct of_device_id *match);
 123 static int gfar_remove(struct of_device *ofdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 135                               int amount_pull);
 136 static void gfar_vlan_rx_register(struct net_device *netdev,
 137                                 struct vlan_group *grp);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 143 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 144
 145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 147 MODULE_LICENSE("GPL");
 148
 149 static const struct net_device_ops gfar_netdev_ops = {
 150         .ndo_open = gfar_enet_open,
 151         .ndo_start_xmit = gfar_start_xmit,
 152         .ndo_stop = gfar_close,
 153         .ndo_change_mtu = gfar_change_mtu,
 154         .ndo_set_multicast_list = gfar_set_multi,
 155         .ndo_tx_timeout = gfar_timeout,
 156         .ndo_do_ioctl = gfar_ioctl,
 157         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 158 #ifdef CONFIG_NET_POLL_CONTROLLER
 159         .ndo_poll_controller = gfar_netpoll,
 160 #endif
 161 };
 162
 163 /* Returns 1 if incoming frames use an FCB */
 164 static inline int gfar_uses_fcb(struct gfar_private *priv)
 165 {
 166         return priv->vlgrp || priv->rx_csum_enable;
 167 }
 168
 169 static int gfar_of_init(struct net_device *dev)
 170 {
 171         struct device_node *phy, *mdio;
 172         const unsigned int *id;
 173         const char *model;
 174         const char *ctype;
 175         const void *mac_addr;
 176         const phandle *ph;
 177         u64 addr, size;
 178         int err = 0;
 179         struct gfar_private *priv = netdev_priv(dev);
 180         struct device_node *np = priv->node;
 181         char bus_name[MII_BUS_ID_SIZE];
 182         const u32 *stash;
 183         const u32 *stash_len;
 184         const u32 *stash_idx;
 185
 186         if (!np || !of_device_is_available(np))
 187                 return -ENODEV;
 188
 189         /* get a pointer to the register memory */
 190         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 191         priv->regs = ioremap(addr, size);
 192
 193         if (priv->regs == NULL)
 194                 return -ENOMEM;
 195
 196         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
 197
 198         model = of_get_property(np, "model", NULL);
 199
 200         /* If we aren't the FEC we have multiple interrupts */
 201         if (model && strcasecmp(model, "FEC")) {
 202                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
 203
 204                 priv->interruptError = irq_of_parse_and_map(np, 2);
 205
 206                 if (priv->interruptTransmit < 0 ||
 207                                 priv->interruptReceive < 0 ||
 208                                 priv->interruptError < 0) {
 209                         err = -EINVAL;
 210                         goto err_out;
 211                 }
 212         }
 213
 214         stash = of_get_property(np, "bd-stash", NULL);
 215
 216         if(stash) {
 217                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 218                 priv->bd_stash_en = 1;
 219         }
 220
 221         stash_len = of_get_property(np, "rx-stash-len", NULL);
 222
 223         if (stash_len)
 224                 priv->rx_stash_size = *stash_len;
 225
 226         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 227
 228         if (stash_idx)
 229                 priv->rx_stash_index = *stash_idx;
 230
 231         if (stash_len || stash_idx)
 232                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 233
 234         mac_addr = of_get_mac_address(np);
 235         if (mac_addr)
 236                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 237
 238         if (model && !strcasecmp(model, "TSEC"))
 239                 priv->device_flags =
 240                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 241                         FSL_GIANFAR_DEV_HAS_COALESCE |
 242                         FSL_GIANFAR_DEV_HAS_RMON |
 243                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 244         if (model && !strcasecmp(model, "eTSEC"))
 245                 priv->device_flags =
 246                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 247                         FSL_GIANFAR_DEV_HAS_COALESCE |
 248                         FSL_GIANFAR_DEV_HAS_RMON |
 249                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 250                         FSL_GIANFAR_DEV_HAS_PADDING |
 251                         FSL_GIANFAR_DEV_HAS_CSUM |
 252                         FSL_GIANFAR_DEV_HAS_VLAN |
 253                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 254                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 255
 256         ctype = of_get_property(np, "phy-connection-type", NULL);
 257
 258         /* We only care about rgmii-id.  The rest are autodetected */
 259         if (ctype && !strcmp(ctype, "rgmii-id"))
 260                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 261         else
 262                 priv->interface = PHY_INTERFACE_MODE_MII;
 263
 264         if (of_get_property(np, "fsl,magic-packet", NULL))
 265                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 266
 267         ph = of_get_property(np, "phy-handle", NULL);
 268         if (ph == NULL) {
 269                 u32 *fixed_link;
 270
 271                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
 272                 if (!fixed_link) {
 273                         err = -ENODEV;
 274                         goto err_out;
 275                 }
 276
 277                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
 278                                 PHY_ID_FMT, "0", fixed_link[0]);
 279         } else {
 280                 phy = of_find_node_by_phandle(*ph);
 281
 282                 if (phy == NULL) {
 283                         err = -ENODEV;
 284                         goto err_out;
 285                 }
 286
 287                 mdio = of_get_parent(phy);
 288
 289                 id = of_get_property(phy, "reg", NULL);
 290
 291                 of_node_put(phy);
 292                 of_node_put(mdio);
 293
 294                 fsl_pq_mdio_bus_name(bus_name, mdio);
 295                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
 296                                 bus_name, *id);
 297         }
 298
 299         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 300         ph = of_get_property(np, "tbi-handle", NULL);
 301         if (ph) {
 302                 struct device_node *tbi = of_find_node_by_phandle(*ph);
 303                 struct of_device *ofdev;
 304                 struct mii_bus *bus;
 305
 306                 if (!tbi)
 307                         return 0;
 308
 309                 mdio = of_get_parent(tbi);
 310                 if (!mdio)
 311                         return 0;
 312
 313                 ofdev = of_find_device_by_node(mdio);
 314
 315                 of_node_put(mdio);
 316
 317                 id = of_get_property(tbi, "reg", NULL);
 318                 if (!id)
 319                         return 0;
 320
 321                 of_node_put(tbi);
 322
 323                 bus = dev_get_drvdata(&ofdev->dev);
 324
 325                 priv->tbiphy = bus->phy_map[*id];
 326         }
 327
 328         return 0;
 329
 330 err_out:
 331         iounmap(priv->regs);
 332         return err;
 333 }
 334
 335 /* Ioctl MII Interface */
 336 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 337 {
 338         struct gfar_private *priv = netdev_priv(dev);
 339
 340         if (!netif_running(dev))
 341                 return -EINVAL;
 342
 343         if (!priv->phydev)
 344                 return -ENODEV;
 345
 346         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 347 }
 348
 349 /* Set up the ethernet device structure, private data,
 350  * and anything else we need before we start */
 351 static int gfar_probe(struct of_device *ofdev,
 352                 const struct of_device_id *match)
 353 {
 354         u32 tempval;
 355         struct net_device *dev = NULL;
 356         struct gfar_private *priv = NULL;
 357         DECLARE_MAC_BUF(mac);
 358         int err = 0;
 359         int len_devname;
 360
 361         /* Create an ethernet device instance */
 362         dev = alloc_etherdev(sizeof (*priv));
 363
 364         if (NULL == dev)
 365                 return -ENOMEM;
 366
 367         priv = netdev_priv(dev);
 368         priv->ndev = dev;
 369         priv->ofdev = ofdev;
 370         priv->node = ofdev->node;
 371         SET_NETDEV_DEV(dev, &ofdev->dev);
 372
 373         err = gfar_of_init(dev);
 374
 375         if (err)
 376                 goto regs_fail;
 377
 378         spin_lock_init(&priv->txlock);
 379         spin_lock_init(&priv->rxlock);
 380         spin_lock_init(&priv->bflock);
 381         INIT_WORK(&priv->reset_task, gfar_reset_task);
 382
 383         dev_set_drvdata(&ofdev->dev, priv);
 384
 385         /* Stop the DMA engine now, in case it was running before */
 386         /* (The firmware could have used it, and left it running). */
 387         gfar_halt(dev);
 388
 389         /* Reset MAC layer */
 390         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 391
 392         /* We need to delay at least 3 TX clocks */
 393         udelay(2);
 394
 395         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 396         gfar_write(&priv->regs->maccfg1, tempval);
 397
 398         /* Initialize MACCFG2. */
 399         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 400
 401         /* Initialize ECNTRL */
 402         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 403
 404         /* Set the dev->base_addr to the gfar reg region */
 405         dev->base_addr = (unsigned long) (priv->regs);
 406
 407         SET_NETDEV_DEV(dev, &ofdev->dev);
 408
 409         /* Fill in the dev structure */
 410         dev->watchdog_timeo = TX_TIMEOUT;
 411         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 412         dev->mtu = 1500;
 413
 414         dev->netdev_ops = &gfar_netdev_ops;
 415         dev->ethtool_ops = &gfar_ethtool_ops;
 416
 417         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 418                 priv->rx_csum_enable = 1;
 419                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 420         } else
 421                 priv->rx_csum_enable = 0;
 422
 423         priv->vlgrp = NULL;
 424
 425         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 426                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 427
 428         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 429                 priv->extended_hash = 1;
 430                 priv->hash_width = 9;
 431
 432                 priv->hash_regs[0] = &priv->regs->igaddr0;
 433                 priv->hash_regs[1] = &priv->regs->igaddr1;
 434                 priv->hash_regs[2] = &priv->regs->igaddr2;
 435                 priv->hash_regs[3] = &priv->regs->igaddr3;
 436                 priv->hash_regs[4] = &priv->regs->igaddr4;
 437                 priv->hash_regs[5] = &priv->regs->igaddr5;
 438                 priv->hash_regs[6] = &priv->regs->igaddr6;
 439                 priv->hash_regs[7] = &priv->regs->igaddr7;
 440                 priv->hash_regs[8] = &priv->regs->gaddr0;
 441                 priv->hash_regs[9] = &priv->regs->gaddr1;
 442                 priv->hash_regs[10] = &priv->regs->gaddr2;
 443                 priv->hash_regs[11] = &priv->regs->gaddr3;
 444                 priv->hash_regs[12] = &priv->regs->gaddr4;
 445                 priv->hash_regs[13] = &priv->regs->gaddr5;
 446                 priv->hash_regs[14] = &priv->regs->gaddr6;
 447                 priv->hash_regs[15] = &priv->regs->gaddr7;
 448
 449         } else {
 450                 priv->extended_hash = 0;
 451                 priv->hash_width = 8;
 452
 453                 priv->hash_regs[0] = &priv->regs->gaddr0;
 454                 priv->hash_regs[1] = &priv->regs->gaddr1;
 455                 priv->hash_regs[2] = &priv->regs->gaddr2;
 456                 priv->hash_regs[3] = &priv->regs->gaddr3;
 457                 priv->hash_regs[4] = &priv->regs->gaddr4;
 458                 priv->hash_regs[5] = &priv->regs->gaddr5;
 459                 priv->hash_regs[6] = &priv->regs->gaddr6;
 460                 priv->hash_regs[7] = &priv->regs->gaddr7;
 461         }
 462
 463         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 464                 priv->padding = DEFAULT_PADDING;
 465         else
 466                 priv->padding = 0;
 467
 468         if (dev->features & NETIF_F_IP_CSUM)
 469                 dev->hard_header_len += GMAC_FCB_LEN;
 470
 471         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 472         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 473         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 474         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
 475
 476         priv->txcoalescing = DEFAULT_TX_COALESCE;
 477         priv->txic = DEFAULT_TXIC;
 478         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 479         priv->rxic = DEFAULT_RXIC;
 480
 481         /* Enable most messages by default */
 482         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 483
 484         /* Carrier starts down, phylib will bring it up */
 485         netif_carrier_off(dev);
 486
 487         err = register_netdev(dev);
 488
 489         if (err) {
 490                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 491                                 dev->name);
 492                 goto register_fail;
 493         }
 494
 495         device_init_wakeup(&dev->dev,
 496                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 497
 498         /* fill out IRQ number and name fields */
 499         len_devname = strlen(dev->name);
 500         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
 501         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 502                 strncpy(&priv->int_name_tx[len_devname],
 503                         "_tx", sizeof("_tx") + 1);
 504
 505                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
 506                 strncpy(&priv->int_name_rx[len_devname],
 507                         "_rx", sizeof("_rx") + 1);
 508
 509                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
 510                 strncpy(&priv->int_name_er[len_devname],
 511                         "_er", sizeof("_er") + 1);
 512         } else
 513                 priv->int_name_tx[len_devname] = '\0';
 514
 515         /* Create all the sysfs files */
 516         gfar_init_sysfs(dev);
 517
 518         /* Print out the device info */
 519         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 520
 521         /* Even more device info helps when determining which kernel */
 522         /* provided which set of benchmarks. */
 523         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 524         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 525                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 526
 527         return 0;
 528
 529 register_fail:
 530         iounmap(priv->regs);
 531 regs_fail:
 532         free_netdev(dev);
 533         return err;
 534 }
 535
 536 static int gfar_remove(struct of_device *ofdev)
 537 {
 538         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 539
 540         dev_set_drvdata(&ofdev->dev, NULL);
 541
 542         iounmap(priv->regs);
 543         free_netdev(priv->ndev);
 544
 545         return 0;
 546 }
 547
 548 #ifdef CONFIG_PM
 549 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
 550 {
 551         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 552         struct net_device *dev = priv->ndev;
 553         unsigned long flags;
 554         u32 tempval;
 555
 556         int magic_packet = priv->wol_en &&
 557                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 558
 559         netif_device_detach(dev);
 560
 561         if (netif_running(dev)) {
 562                 spin_lock_irqsave(&priv->txlock, flags);
 563                 spin_lock(&priv->rxlock);
 564
 565                 gfar_halt_nodisable(dev);
 566
 567                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 568                 tempval = gfar_read(&priv->regs->maccfg1);
 569
 570                 tempval &= ~MACCFG1_TX_EN;
 571
 572                 if (!magic_packet)
 573                         tempval &= ~MACCFG1_RX_EN;
 574
 575                 gfar_write(&priv->regs->maccfg1, tempval);
 576
 577                 spin_unlock(&priv->rxlock);
 578                 spin_unlock_irqrestore(&priv->txlock, flags);
 579
 580                 napi_disable(&priv->napi);
 581
 582                 if (magic_packet) {
 583                         /* Enable interrupt on Magic Packet */
 584                         gfar_write(&priv->regs->imask, IMASK_MAG);
 585
 586                         /* Enable Magic Packet mode */
 587                         tempval = gfar_read(&priv->regs->maccfg2);
 588                         tempval |= MACCFG2_MPEN;
 589                         gfar_write(&priv->regs->maccfg2, tempval);
 590                 } else {
 591                         phy_stop(priv->phydev);
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int gfar_resume(struct of_device *ofdev)
 599 {
 600         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 601         struct net_device *dev = priv->ndev;
 602         unsigned long flags;
 603         u32 tempval;
 604         int magic_packet = priv->wol_en &&
 605                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 606
 607         if (!netif_running(dev)) {
 608                 netif_device_attach(dev);
 609                 return 0;
 610         }
 611
 612         if (!magic_packet && priv->phydev)
 613                 phy_start(priv->phydev);
 614
 615         /* Disable Magic Packet mode, in case something
 616          * else woke us up.
 617          */
 618
 619         spin_lock_irqsave(&priv->txlock, flags);
 620         spin_lock(&priv->rxlock);
 621
 622         tempval = gfar_read(&priv->regs->maccfg2);
 623         tempval &= ~MACCFG2_MPEN;
 624         gfar_write(&priv->regs->maccfg2, tempval);
 625
 626         gfar_start(dev);
 627
 628         spin_unlock(&priv->rxlock);
 629         spin_unlock_irqrestore(&priv->txlock, flags);
 630
 631         netif_device_attach(dev);
 632
 633         napi_enable(&priv->napi);
 634
 635         return 0;
 636 }
 637 #else
 638 #define gfar_suspend NULL
 639 #define gfar_resume NULL
 640 #endif
 641
 642 /* Reads the controller's registers to determine what interface
 643  * connects it to the PHY.
 644  */
 645 static phy_interface_t gfar_get_interface(struct net_device *dev)
 646 {
 647         struct gfar_private *priv = netdev_priv(dev);
 648         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 649
 650         if (ecntrl & ECNTRL_SGMII_MODE)
 651                 return PHY_INTERFACE_MODE_SGMII;
 652
 653         if (ecntrl & ECNTRL_TBI_MODE) {
 654                 if (ecntrl & ECNTRL_REDUCED_MODE)
 655                         return PHY_INTERFACE_MODE_RTBI;
 656                 else
 657                         return PHY_INTERFACE_MODE_TBI;
 658         }
 659
 660         if (ecntrl & ECNTRL_REDUCED_MODE) {
 661                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 662                         return PHY_INTERFACE_MODE_RMII;
 663                 else {
 664                         phy_interface_t interface = priv->interface;
 665
 666                         /*
 667                          * This isn't autodetected right now, so it must
 668                          * be set by the device tree or platform code.
 669                          */
 670                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 671                                 return PHY_INTERFACE_MODE_RGMII_ID;
 672
 673                         return PHY_INTERFACE_MODE_RGMII;
 674                 }
 675         }
 676
 677         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 678                 return PHY_INTERFACE_MODE_GMII;
 679
 680         return PHY_INTERFACE_MODE_MII;
 681 }
 682
 683
 684 /* Initializes driver's PHY state, and attaches to the PHY.
 685  * Returns 0 on success.
 686  */
 687 static int init_phy(struct net_device *dev)
 688 {
 689         struct gfar_private *priv = netdev_priv(dev);
 690         uint gigabit_support =
 691                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 692                 SUPPORTED_1000baseT_Full : 0;
 693         struct phy_device *phydev;
 694         phy_interface_t interface;
 695
 696         priv->oldlink = 0;
 697         priv->oldspeed = 0;
 698         priv->oldduplex = -1;
 699
 700         interface = gfar_get_interface(dev);
 701
 702         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
 703
 704         if (interface == PHY_INTERFACE_MODE_SGMII)
 705                 gfar_configure_serdes(dev);
 706
 707         if (IS_ERR(phydev)) {
 708                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 709                 return PTR_ERR(phydev);
 710         }
 711
 712         /* Remove any features not supported by the controller */
 713         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 714         phydev->advertising = phydev->supported;
 715
 716         priv->phydev = phydev;
 717
 718         return 0;
 719 }
 720
 721 /*
 722  * Initialize TBI PHY interface for communicating with the
 723  * SERDES lynx PHY on the chip.  We communicate with this PHY
 724  * through the MDIO bus on each controller, treating it as a
 725  * "normal" PHY at the address found in the TBIPA register.  We assume
 726  * that the TBIPA register is valid.  Either the MDIO bus code will set
 727  * it to a value that doesn't conflict with other PHYs on the bus, or the
 728  * value doesn't matter, as there are no other PHYs on the bus.
 729  */
 730 static void gfar_configure_serdes(struct net_device *dev)
 731 {
 732         struct gfar_private *priv = netdev_priv(dev);
 733
 734         if (!priv->tbiphy) {
 735                 printk(KERN_WARNING "SGMII mode requires that the device "
 736                                 "tree specify a tbi-handle\n");
 737                 return;
 738         }
 739
 740         /*
 741          * If the link is already up, we must already be ok, and don't need to
 742          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 743          * everything for us?  Resetting it takes the link down and requires
 744          * several seconds for it to come back.
 745          */
 746         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
 747                 return;
 748
 749         /* Single clk mode, mii mode off(for serdes communication) */
 750         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 751
 752         phy_write(priv->tbiphy, MII_ADVERTISE,
 753                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 754                         ADVERTISE_1000XPSE_ASYM);
 755
 756         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
 757                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 758 }
 759
 760 static void init_registers(struct net_device *dev)
 761 {
 762         struct gfar_private *priv = netdev_priv(dev);
 763
 764         /* Clear IEVENT */
 765         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 766
 767         /* Initialize IMASK */
 768         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 769
 770         /* Init hash registers to zero */
 771         gfar_write(&priv->regs->igaddr0, 0);
 772         gfar_write(&priv->regs->igaddr1, 0);
 773         gfar_write(&priv->regs->igaddr2, 0);
 774         gfar_write(&priv->regs->igaddr3, 0);
 775         gfar_write(&priv->regs->igaddr4, 0);
 776         gfar_write(&priv->regs->igaddr5, 0);
 777         gfar_write(&priv->regs->igaddr6, 0);
 778         gfar_write(&priv->regs->igaddr7, 0);
 779
 780         gfar_write(&priv->regs->gaddr0, 0);
 781         gfar_write(&priv->regs->gaddr1, 0);
 782         gfar_write(&priv->regs->gaddr2, 0);
 783         gfar_write(&priv->regs->gaddr3, 0);
 784         gfar_write(&priv->regs->gaddr4, 0);
 785         gfar_write(&priv->regs->gaddr5, 0);
 786         gfar_write(&priv->regs->gaddr6, 0);
 787         gfar_write(&priv->regs->gaddr7, 0);
 788
 789         /* Zero out the rmon mib registers if it has them */
 790         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 791                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 792
 793                 /* Mask off the CAM interrupts */
 794                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 795                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 796         }
 797
 798         /* Initialize the max receive buffer length */
 799         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 800
 801         /* Initialize the Minimum Frame Length Register */
 802         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 803 }
 804
 805
 806 /* Halt the receive and transmit queues */
 807 static void gfar_halt_nodisable(struct net_device *dev)
 808 {
 809         struct gfar_private *priv = netdev_priv(dev);
 810         struct gfar __iomem *regs = priv->regs;
 811         u32 tempval;
 812
 813         /* Mask all interrupts */
 814         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 815
 816         /* Clear all interrupts */
 817         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 818
 819         /* Stop the DMA, and wait for it to stop */
 820         tempval = gfar_read(&priv->regs->dmactrl);
 821         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 822             != (DMACTRL_GRS | DMACTRL_GTS)) {
 823                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 824                 gfar_write(&priv->regs->dmactrl, tempval);
 825
 826                 while (!(gfar_read(&priv->regs->ievent) &
 827                          (IEVENT_GRSC | IEVENT_GTSC)))
 828                         cpu_relax();
 829         }
 830 }
 831
 832 /* Halt the receive and transmit queues */
 833 void gfar_halt(struct net_device *dev)
 834 {
 835         struct gfar_private *priv = netdev_priv(dev);
 836         struct gfar __iomem *regs = priv->regs;
 837         u32 tempval;
 838
 839         gfar_halt_nodisable(dev);
 840
 841         /* Disable Rx and Tx */
 842         tempval = gfar_read(&regs->maccfg1);
 843         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 844         gfar_write(&regs->maccfg1, tempval);
 845 }
 846
 847 void stop_gfar(struct net_device *dev)
 848 {
 849         struct gfar_private *priv = netdev_priv(dev);
 850         struct gfar __iomem *regs = priv->regs;
 851         unsigned long flags;
 852
 853         phy_stop(priv->phydev);
 854
 855         /* Lock it down */
 856         spin_lock_irqsave(&priv->txlock, flags);
 857         spin_lock(&priv->rxlock);
 858
 859         gfar_halt(dev);
 860
 861         spin_unlock(&priv->rxlock);
 862         spin_unlock_irqrestore(&priv->txlock, flags);
 863
 864         /* Free the IRQs */
 865         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 866                 free_irq(priv->interruptError, dev);
 867                 free_irq(priv->interruptTransmit, dev);
 868                 free_irq(priv->interruptReceive, dev);
 869         } else {
 870                 free_irq(priv->interruptTransmit, dev);
 871         }
 872
 873         free_skb_resources(priv);
 874
 875         dma_free_coherent(&priv->ofdev->dev,
 876                         sizeof(struct txbd8)*priv->tx_ring_size
 877                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 878                         priv->tx_bd_base,
 879                         gfar_read(&regs->tbase0));
 880 }
 881
 882 /* If there are any tx skbs or rx skbs still around, free them.
 883  * Then free tx_skbuff and rx_skbuff */
 884 static void free_skb_resources(struct gfar_private *priv)
 885 {
 886         struct rxbd8 *rxbdp;
 887         struct txbd8 *txbdp;
 888         int i, j;
 889
 890         /* Go through all the buffer descriptors and free their data buffers */
 891         txbdp = priv->tx_bd_base;
 892
 893         for (i = 0; i < priv->tx_ring_size; i++) {
 894                 if (!priv->tx_skbuff[i])
 895                         continue;
 896
 897                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
 898                                 txbdp->length, DMA_TO_DEVICE);
 899                 txbdp->lstatus = 0;
 900                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
 901                         txbdp++;
 902                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
 903                                         txbdp->length, DMA_TO_DEVICE);
 904                 }
 905                 txbdp++;
 906                 dev_kfree_skb_any(priv->tx_skbuff[i]);
 907                 priv->tx_skbuff[i] = NULL;
 908         }
 909
 910         kfree(priv->tx_skbuff);
 911
 912         rxbdp = priv->rx_bd_base;
 913
 914         /* rx_skbuff is not guaranteed to be allocated, so only
 915          * free it and its contents if it is allocated */
 916         if(priv->rx_skbuff != NULL) {
 917                 for (i = 0; i < priv->rx_ring_size; i++) {
 918                         if (priv->rx_skbuff[i]) {
 919                                 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
 920                                                 priv->rx_buffer_size,
 921                                                 DMA_FROM_DEVICE);
 922
 923                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 924                                 priv->rx_skbuff[i] = NULL;
 925                         }
 926
 927                         rxbdp->lstatus = 0;
 928                         rxbdp->bufPtr = 0;
 929
 930                         rxbdp++;
 931                 }
 932
 933                 kfree(priv->rx_skbuff);
 934         }
 935 }
 936
 937 void gfar_start(struct net_device *dev)
 938 {
 939         struct gfar_private *priv = netdev_priv(dev);
 940         struct gfar __iomem *regs = priv->regs;
 941         u32 tempval;
 942
 943         /* Enable Rx and Tx in MACCFG1 */
 944         tempval = gfar_read(&regs->maccfg1);
 945         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 946         gfar_write(&regs->maccfg1, tempval);
 947
 948         /* Initialize DMACTRL to have WWR and WOP */
 949         tempval = gfar_read(&priv->regs->dmactrl);
 950         tempval |= DMACTRL_INIT_SETTINGS;
 951         gfar_write(&priv->regs->dmactrl, tempval);
 952
 953         /* Make sure we aren't stopped */
 954         tempval = gfar_read(&priv->regs->dmactrl);
 955         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 956         gfar_write(&priv->regs->dmactrl, tempval);
 957
 958         /* Clear THLT/RHLT, so that the DMA starts polling now */
 959         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 960         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 961
 962         /* Unmask the interrupts we look for */
 963         gfar_write(&regs->imask, IMASK_DEFAULT);
 964
 965         dev->trans_start = jiffies;
 966 }
 967
 968 /* Bring the controller up and running */
 969 int startup_gfar(struct net_device *dev)
 970 {
 971         struct txbd8 *txbdp;
 972         struct rxbd8 *rxbdp;
 973         dma_addr_t addr = 0;
 974         unsigned long vaddr;
 975         int i;
 976         struct gfar_private *priv = netdev_priv(dev);
 977         struct gfar __iomem *regs = priv->regs;
 978         int err = 0;
 979         u32 rctrl = 0;
 980         u32 attrs = 0;
 981
 982         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 983
 984         /* Allocate memory for the buffer descriptors */
 985         vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
 986                         sizeof (struct txbd8) * priv->tx_ring_size +
 987                         sizeof (struct rxbd8) * priv->rx_ring_size,
 988                         &addr, GFP_KERNEL);
 989
 990         if (vaddr == 0) {
 991                 if (netif_msg_ifup(priv))
 992                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 993                                         dev->name);
 994                 return -ENOMEM;
 995         }
 996
 997         priv->tx_bd_base = (struct txbd8 *) vaddr;
 998
 999         /* enet DMA only understands physical addresses */
1000         gfar_write(&regs->tbase0, addr);
1001
1002         /* Start the rx descriptor ring where the tx ring leaves off */
1003         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
1004         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
1005         priv->rx_bd_base = (struct rxbd8 *) vaddr;
1006         gfar_write(&regs->rbase0, addr);
1007
1008         /* Setup the skbuff rings */
1009         priv->tx_skbuff =
1010             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1011                                         priv->tx_ring_size, GFP_KERNEL);
1012
1013         if (NULL == priv->tx_skbuff) {
1014                 if (netif_msg_ifup(priv))
1015                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1016                                         dev->name);
1017                 err = -ENOMEM;
1018                 goto tx_skb_fail;
1019         }
1020
1021         for (i = 0; i < priv->tx_ring_size; i++)
1022                 priv->tx_skbuff[i] = NULL;
1023
1024         priv->rx_skbuff =
1025             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1026                                         priv->rx_ring_size, GFP_KERNEL);
1027
1028         if (NULL == priv->rx_skbuff) {
1029                 if (netif_msg_ifup(priv))
1030                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1031                                         dev->name);
1032                 err = -ENOMEM;
1033                 goto rx_skb_fail;
1034         }
1035
1036         for (i = 0; i < priv->rx_ring_size; i++)
1037                 priv->rx_skbuff[i] = NULL;
1038
1039         /* Initialize some variables in our dev structure */
1040         priv->num_txbdfree = priv->tx_ring_size;
1041         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1042         priv->cur_rx = priv->rx_bd_base;
1043         priv->skb_curtx = priv->skb_dirtytx = 0;
1044         priv->skb_currx = 0;
1045
1046         /* Initialize Transmit Descriptor Ring */
1047         txbdp = priv->tx_bd_base;
1048         for (i = 0; i < priv->tx_ring_size; i++) {
1049                 txbdp->lstatus = 0;
1050                 txbdp->bufPtr = 0;
1051                 txbdp++;
1052         }
1053
1054         /* Set the last descriptor in the ring to indicate wrap */
1055         txbdp--;
1056         txbdp->status |= TXBD_WRAP;
1057
1058         rxbdp = priv->rx_bd_base;
1059         for (i = 0; i < priv->rx_ring_size; i++) {
1060                 struct sk_buff *skb;
1061
1062                 skb = gfar_new_skb(dev);
1063
1064                 if (!skb) {
1065                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1066                                         dev->name);
1067
1068                         goto err_rxalloc_fail;
1069                 }
1070
1071                 priv->rx_skbuff[i] = skb;
1072
1073                 gfar_new_rxbdp(dev, rxbdp, skb);
1074
1075                 rxbdp++;
1076         }
1077
1078         /* Set the last descriptor in the ring to wrap */
1079         rxbdp--;
1080         rxbdp->status |= RXBD_WRAP;
1081
1082         /* If the device has multiple interrupts, register for
1083          * them.  Otherwise, only register for the one */
1084         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1085                 /* Install our interrupt handlers for Error,
1086                  * Transmit, and Receive */
1087                 if (request_irq(priv->interruptError, gfar_error,
1088                                 0, priv->int_name_er, dev) < 0) {
1089                         if (netif_msg_intr(priv))
1090                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1091                                         dev->name, priv->interruptError);
1092
1093                         err = -1;
1094                         goto err_irq_fail;
1095                 }
1096
1097                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1098                                 0, priv->int_name_tx, dev) < 0) {
1099                         if (netif_msg_intr(priv))
1100                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1101                                         dev->name, priv->interruptTransmit);
1102
1103                         err = -1;
1104
1105                         goto tx_irq_fail;
1106                 }
1107
1108                 if (request_irq(priv->interruptReceive, gfar_receive,
1109                                 0, priv->int_name_rx, dev) < 0) {
1110                         if (netif_msg_intr(priv))
1111                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1112                                                 dev->name, priv->interruptReceive);
1113
1114                         err = -1;
1115                         goto rx_irq_fail;
1116                 }
1117         } else {
1118                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1119                                 0, priv->int_name_tx, dev) < 0) {
1120                         if (netif_msg_intr(priv))
1121                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1122                                         dev->name, priv->interruptTransmit);
1123
1124                         err = -1;
1125                         goto err_irq_fail;
1126                 }
1127         }
1128
1129         phy_start(priv->phydev);
1130
1131         /* Configure the coalescing support */
1132         gfar_write(&regs->txic, 0);
1133         if (priv->txcoalescing)
1134                 gfar_write(&regs->txic, priv->txic);
1135
1136         gfar_write(&regs->rxic, 0);
1137         if (priv->rxcoalescing)
1138                 gfar_write(&regs->rxic, priv->rxic);
1139
1140         if (priv->rx_csum_enable)
1141                 rctrl |= RCTRL_CHECKSUMMING;
1142
1143         if (priv->extended_hash) {
1144                 rctrl |= RCTRL_EXTHASH;
1145
1146                 gfar_clear_exact_match(dev);
1147                 rctrl |= RCTRL_EMEN;
1148         }
1149
1150         if (priv->padding) {
1151                 rctrl &= ~RCTRL_PAL_MASK;
1152                 rctrl |= RCTRL_PADDING(priv->padding);
1153         }
1154
1155         /* Init rctrl based on our settings */
1156         gfar_write(&priv->regs->rctrl, rctrl);
1157
1158         if (dev->features & NETIF_F_IP_CSUM)
1159                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1160
1161         /* Set the extraction length and index */
1162         attrs = ATTRELI_EL(priv->rx_stash_size) |
1163                 ATTRELI_EI(priv->rx_stash_index);
1164
1165         gfar_write(&priv->regs->attreli, attrs);
1166
1167         /* Start with defaults, and add stashing or locking
1168          * depending on the approprate variables */
1169         attrs = ATTR_INIT_SETTINGS;
1170
1171         if (priv->bd_stash_en)
1172                 attrs |= ATTR_BDSTASH;
1173
1174         if (priv->rx_stash_size != 0)
1175                 attrs |= ATTR_BUFSTASH;
1176
1177         gfar_write(&priv->regs->attr, attrs);
1178
1179         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1180         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1181         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1182
1183         /* Start the controller */
1184         gfar_start(dev);
1185
1186         return 0;
1187
1188 rx_irq_fail:
1189         free_irq(priv->interruptTransmit, dev);
1190 tx_irq_fail:
1191         free_irq(priv->interruptError, dev);
1192 err_irq_fail:
1193 err_rxalloc_fail:
1194 rx_skb_fail:
1195         free_skb_resources(priv);
1196 tx_skb_fail:
1197         dma_free_coherent(&priv->ofdev->dev,
1198                         sizeof(struct txbd8)*priv->tx_ring_size
1199                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1200                         priv->tx_bd_base,
1201                         gfar_read(&regs->tbase0));
1202
1203         return err;
1204 }
1205
1206 /* Called when something needs to use the ethernet device */
1207 /* Returns 0 for success. */
1208 static int gfar_enet_open(struct net_device *dev)
1209 {
1210         struct gfar_private *priv = netdev_priv(dev);
1211         int err;
1212
1213         napi_enable(&priv->napi);
1214
1215         skb_queue_head_init(&priv->rx_recycle);
1216
1217         /* Initialize a bunch of registers */
1218         init_registers(dev);
1219
1220         gfar_set_mac_address(dev);
1221
1222         err = init_phy(dev);
1223
1224         if(err) {
1225                 napi_disable(&priv->napi);
1226                 return err;
1227         }
1228
1229         err = startup_gfar(dev);
1230         if (err) {
1231                 napi_disable(&priv->napi);
1232                 return err;
1233         }
1234
1235         netif_start_queue(dev);
1236
1237         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1238
1239         return err;
1240 }
1241
1242 static inline struct txfcb *gfar_add_fcb(struct sk_buff **skbp)
1243 {
1244         struct txfcb *fcb;
1245         struct sk_buff *skb = *skbp;
1246
1247         if (unlikely(skb_headroom(skb) < GMAC_FCB_LEN)) {
1248                 struct sk_buff *old_skb = skb;
1249                 skb = skb_realloc_headroom(old_skb, GMAC_FCB_LEN);
1250                 if (!skb)
1251                         return NULL;
1252                 dev_kfree_skb_any(old_skb);
1253         }
1254         fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1255         cacheable_memzero(fcb, GMAC_FCB_LEN);
1256
1257         return fcb;
1258 }
1259
1260 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1261 {
1262         u8 flags = 0;
1263
1264         /* If we're here, it's a IP packet with a TCP or UDP
1265          * payload.  We set it to checksum, using a pseudo-header
1266          * we provide
1267          */
1268         flags = TXFCB_DEFAULT;
1269
1270         /* Tell the controller what the protocol is */
1271         /* And provide the already calculated phcs */
1272         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1273                 flags |= TXFCB_UDP;
1274                 fcb->phcs = udp_hdr(skb)->check;
1275         } else
1276                 fcb->phcs = tcp_hdr(skb)->check;
1277
1278         /* l3os is the distance between the start of the
1279          * frame (skb->data) and the start of the IP hdr.
1280          * l4os is the distance between the start of the
1281          * l3 hdr and the l4 hdr */
1282         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1283         fcb->l4os = skb_network_header_len(skb);
1284
1285         fcb->flags = flags;
1286 }
1287
1288 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1289 {
1290         fcb->flags |= TXFCB_VLN;
1291         fcb->vlctl = vlan_tx_tag_get(skb);
1292 }
1293
1294 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1295                                struct txbd8 *base, int ring_size)
1296 {
1297         struct txbd8 *new_bd = bdp + stride;
1298
1299         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1300 }
1301
1302 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1303                 int ring_size)
1304 {
1305         return skip_txbd(bdp, 1, base, ring_size);
1306 }
1307
1308 /* This is called by the kernel when a frame is ready for transmission. */
1309 /* It is pointed to by the dev->hard_start_xmit function pointer */
1310 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1311 {
1312         struct gfar_private *priv = netdev_priv(dev);
1313         struct txfcb *fcb = NULL;
1314         struct txbd8 *txbdp, *txbdp_start, *base;
1315         u32 lstatus;
1316         int i;
1317         u32 bufaddr;
1318         unsigned long flags;
1319         unsigned int nr_frags, length;
1320
1321         base = priv->tx_bd_base;
1322
1323         /* total number of fragments in the SKB */
1324         nr_frags = skb_shinfo(skb)->nr_frags;
1325
1326         spin_lock_irqsave(&priv->txlock, flags);
1327
1328         /* check if there is space to queue this packet */
1329         if ((nr_frags+1) > priv->num_txbdfree) {
1330                 /* no space, stop the queue */
1331                 netif_stop_queue(dev);
1332                 dev->stats.tx_fifo_errors++;
1333                 spin_unlock_irqrestore(&priv->txlock, flags);
1334                 return NETDEV_TX_BUSY;
1335         }
1336
1337         /* Update transmit stats */
1338         dev->stats.tx_bytes += skb->len;
1339
1340         txbdp = txbdp_start = priv->cur_tx;
1341
1342         if (nr_frags == 0) {
1343                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1344         } else {
1345                 /* Place the fragment addresses and lengths into the TxBDs */
1346                 for (i = 0; i < nr_frags; i++) {
1347                         /* Point at the next BD, wrapping as needed */
1348                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1349
1350                         length = skb_shinfo(skb)->frags[i].size;
1351
1352                         lstatus = txbdp->lstatus | length |
1353                                 BD_LFLAG(TXBD_READY);
1354
1355                         /* Handle the last BD specially */
1356                         if (i == nr_frags - 1)
1357                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1358
1359                         bufaddr = dma_map_page(&priv->ofdev->dev,
1360                                         skb_shinfo(skb)->frags[i].page,
1361                                         skb_shinfo(skb)->frags[i].page_offset,
1362                                         length,
1363                                         DMA_TO_DEVICE);
1364
1365                         /* set the TxBD length and buffer pointer */
1366                         txbdp->bufPtr = bufaddr;
1367                         txbdp->lstatus = lstatus;
1368                 }
1369
1370                 lstatus = txbdp_start->lstatus;
1371         }
1372
1373         /* Set up checksumming */
1374         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1375                 fcb = gfar_add_fcb(&skb);
1376                 if (likely(fcb != NULL)) {
1377                         lstatus |= BD_LFLAG(TXBD_TOE);
1378                         gfar_tx_checksum(skb, fcb);
1379                 }
1380         }
1381
1382         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1383                 if (unlikely(NULL == fcb))
1384                         fcb = gfar_add_fcb(&skb);
1385                 if (likely(fcb != NULL)) {
1386                         lstatus |= BD_LFLAG(TXBD_TOE);
1387                         gfar_tx_vlan(skb, fcb);
1388                 }
1389         }
1390
1391         /* setup the TxBD length and buffer pointer for the first BD */
1392         priv->tx_skbuff[priv->skb_curtx] = skb;
1393         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1394                         skb_headlen(skb), DMA_TO_DEVICE);
1395
1396         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1397
1398         /*
1399          * The powerpc-specific eieio() is used, as wmb() has too strong
1400          * semantics (it requires synchronization between cacheable and
1401          * uncacheable mappings, which eieio doesn't provide and which we
1402          * don't need), thus requiring a more expensive sync instruction.  At
1403          * some point, the set of architecture-independent barrier functions
1404          * should be expanded to include weaker barriers.
1405          */
1406         eieio();
1407
1408         txbdp_start->lstatus = lstatus;
1409
1410         /* Update the current skb pointer to the next entry we will use
1411          * (wrapping if necessary) */
1412         priv->skb_curtx = (priv->skb_curtx + 1) &
1413                 TX_RING_MOD_MASK(priv->tx_ring_size);
1414
1415         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1416
1417         /* reduce TxBD free count */
1418         priv->num_txbdfree -= (nr_frags + 1);
1419
1420         dev->trans_start = jiffies;
1421
1422         /* If the next BD still needs to be cleaned up, then the bds
1423            are full.  We need to tell the kernel to stop sending us stuff. */
1424         if (!priv->num_txbdfree) {
1425                 netif_stop_queue(dev);
1426
1427                 dev->stats.tx_fifo_errors++;
1428         }
1429
1430         /* Tell the DMA to go go go */
1431         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1432
1433         /* Unlock priv */
1434         spin_unlock_irqrestore(&priv->txlock, flags);
1435
1436         return 0;
1437 }
1438
1439 /* Stops the kernel queue, and halts the controller */
1440 static int gfar_close(struct net_device *dev)
1441 {
1442         struct gfar_private *priv = netdev_priv(dev);
1443
1444         napi_disable(&priv->napi);
1445
1446         skb_queue_purge(&priv->rx_recycle);
1447         cancel_work_sync(&priv->reset_task);
1448         stop_gfar(dev);
1449
1450         /* Disconnect from the PHY */
1451         phy_disconnect(priv->phydev);
1452         priv->phydev = NULL;
1453
1454         netif_stop_queue(dev);
1455
1456         return 0;
1457 }
1458
1459 /* Changes the mac address if the controller is not running. */
1460 static int gfar_set_mac_address(struct net_device *dev)
1461 {
1462         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1463
1464         return 0;
1465 }
1466
1467
1468 /* Enables and disables VLAN insertion/extraction */
1469 static void gfar_vlan_rx_register(struct net_device *dev,
1470                 struct vlan_group *grp)
1471 {
1472         struct gfar_private *priv = netdev_priv(dev);
1473         unsigned long flags;
1474         u32 tempval;
1475
1476         spin_lock_irqsave(&priv->rxlock, flags);
1477
1478         priv->vlgrp = grp;
1479
1480         if (grp) {
1481                 /* Enable VLAN tag insertion */
1482                 tempval = gfar_read(&priv->regs->tctrl);
1483                 tempval |= TCTRL_VLINS;
1484
1485                 gfar_write(&priv->regs->tctrl, tempval);
1486
1487                 /* Enable VLAN tag extraction */
1488                 tempval = gfar_read(&priv->regs->rctrl);
1489                 tempval |= RCTRL_VLEX;
1490                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1491                 gfar_write(&priv->regs->rctrl, tempval);
1492         } else {
1493                 /* Disable VLAN tag insertion */
1494                 tempval = gfar_read(&priv->regs->tctrl);
1495                 tempval &= ~TCTRL_VLINS;
1496                 gfar_write(&priv->regs->tctrl, tempval);
1497
1498                 /* Disable VLAN tag extraction */
1499                 tempval = gfar_read(&priv->regs->rctrl);
1500                 tempval &= ~RCTRL_VLEX;
1501                 /* If parse is no longer required, then disable parser */
1502                 if (tempval & RCTRL_REQ_PARSER)
1503                         tempval |= RCTRL_PRSDEP_INIT;
1504                 else
1505                         tempval &= ~RCTRL_PRSDEP_INIT;
1506                 gfar_write(&priv->regs->rctrl, tempval);
1507         }
1508
1509         gfar_change_mtu(dev, dev->mtu);
1510
1511         spin_unlock_irqrestore(&priv->rxlock, flags);
1512 }
1513
1514 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1515 {
1516         int tempsize, tempval;
1517         struct gfar_private *priv = netdev_priv(dev);
1518         int oldsize = priv->rx_buffer_size;
1519         int frame_size = new_mtu + ETH_HLEN;
1520
1521         if (priv->vlgrp)
1522                 frame_size += VLAN_HLEN;
1523
1524         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1525                 if (netif_msg_drv(priv))
1526                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1527                                         dev->name);
1528                 return -EINVAL;
1529         }
1530
1531         if (gfar_uses_fcb(priv))
1532                 frame_size += GMAC_FCB_LEN;
1533
1534         frame_size += priv->padding;
1535
1536         tempsize =
1537             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1538             INCREMENTAL_BUFFER_SIZE;
1539
1540         /* Only stop and start the controller if it isn't already
1541          * stopped, and we changed something */
1542         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1543                 stop_gfar(dev);
1544
1545         priv->rx_buffer_size = tempsize;
1546
1547         dev->mtu = new_mtu;
1548
1549         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1550         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1551
1552         /* If the mtu is larger than the max size for standard
1553          * ethernet frames (ie, a jumbo frame), then set maccfg2
1554          * to allow huge frames, and to check the length */
1555         tempval = gfar_read(&priv->regs->maccfg2);
1556
1557         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1558                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1559         else
1560                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1561
1562         gfar_write(&priv->regs->maccfg2, tempval);
1563
1564         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1565                 startup_gfar(dev);
1566
1567         return 0;
1568 }
1569
1570 /* gfar_reset_task gets scheduled when a packet has not been
1571  * transmitted after a set amount of time.
1572  * For now, assume that clearing out all the structures, and
1573  * starting over will fix the problem.
1574  */
1575 static void gfar_reset_task(struct work_struct *work)
1576 {
1577         struct gfar_private *priv = container_of(work, struct gfar_private,
1578                         reset_task);
1579         struct net_device *dev = priv->ndev;
1580
1581         if (dev->flags & IFF_UP) {
1582                 stop_gfar(dev);
1583                 startup_gfar(dev);
1584         }
1585
1586         netif_tx_schedule_all(dev);
1587 }
1588
1589 static void gfar_timeout(struct net_device *dev)
1590 {
1591         struct gfar_private *priv = netdev_priv(dev);
1592
1593         dev->stats.tx_errors++;
1594         schedule_work(&priv->reset_task);
1595 }
1596
1597 /* Interrupt Handler for Transmit complete */
1598 static int gfar_clean_tx_ring(struct net_device *dev)
1599 {
1600         struct gfar_private *priv = netdev_priv(dev);
1601         struct txbd8 *bdp;
1602         struct txbd8 *lbdp = NULL;
1603         struct txbd8 *base = priv->tx_bd_base;
1604         struct sk_buff *skb;
1605         int skb_dirtytx;
1606         int tx_ring_size = priv->tx_ring_size;
1607         int frags = 0;
1608         int i;
1609         int howmany = 0;
1610         u32 lstatus;
1611
1612         bdp = priv->dirty_tx;
1613         skb_dirtytx = priv->skb_dirtytx;
1614
1615         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1616                 frags = skb_shinfo(skb)->nr_frags;
1617                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1618
1619                 lstatus = lbdp->lstatus;
1620
1621                 /* Only clean completed frames */
1622                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1623                                 (lstatus & BD_LENGTH_MASK))
1624                         break;
1625
1626                 dma_unmap_single(&priv->ofdev->dev,
1627                                 bdp->bufPtr,
1628                                 bdp->length,
1629                                 DMA_TO_DEVICE);
1630
1631                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1632                 bdp = next_txbd(bdp, base, tx_ring_size);
1633
1634                 for (i = 0; i < frags; i++) {
1635                         dma_unmap_page(&priv->ofdev->dev,
1636                                         bdp->bufPtr,
1637                                         bdp->length,
1638                                         DMA_TO_DEVICE);
1639                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1640                         bdp = next_txbd(bdp, base, tx_ring_size);
1641                 }
1642
1643                 /*
1644                  * If there's room in the queue (limit it to rx_buffer_size)
1645                  * we add this skb back into the pool, if it's the right size
1646                  */
1647                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1648                                 skb_recycle_check(skb, priv->rx_buffer_size +
1649                                         RXBUF_ALIGNMENT))
1650                         __skb_queue_head(&priv->rx_recycle, skb);
1651                 else
1652                         dev_kfree_skb_any(skb);
1653
1654                 priv->tx_skbuff[skb_dirtytx] = NULL;
1655
1656                 skb_dirtytx = (skb_dirtytx + 1) &
1657                         TX_RING_MOD_MASK(tx_ring_size);
1658
1659                 howmany++;
1660                 priv->num_txbdfree += frags + 1;
1661         }
1662
1663         /* If we freed a buffer, we can restart transmission, if necessary */
1664         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1665                 netif_wake_queue(dev);
1666
1667         /* Update dirty indicators */
1668         priv->skb_dirtytx = skb_dirtytx;
1669         priv->dirty_tx = bdp;
1670
1671         dev->stats.tx_packets += howmany;
1672
1673         return howmany;
1674 }
1675
1676 static void gfar_schedule_cleanup(struct net_device *dev)
1677 {
1678         struct gfar_private *priv = netdev_priv(dev);
1679         unsigned long flags;
1680
1681         spin_lock_irqsave(&priv->txlock, flags);
1682         spin_lock(&priv->rxlock);
1683
1684         if (napi_schedule_prep(&priv->napi)) {
1685                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1686                 __napi_schedule(&priv->napi);
1687         } else {
1688                 /*
1689                  * Clear IEVENT, so interrupts aren't called again
1690                  * because of the packets that have already arrived.
1691                  */
1692                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1693         }
1694
1695         spin_unlock(&priv->rxlock);
1696         spin_unlock_irqrestore(&priv->txlock, flags);
1697 }
1698
1699 /* Interrupt Handler for Transmit complete */
1700 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1701 {
1702         gfar_schedule_cleanup((struct net_device *)dev_id);
1703         return IRQ_HANDLED;
1704 }
1705
1706 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1707                 struct sk_buff *skb)
1708 {
1709         struct gfar_private *priv = netdev_priv(dev);
1710         u32 lstatus;
1711
1712         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1713                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1714
1715         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1716
1717         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1718                 lstatus |= BD_LFLAG(RXBD_WRAP);
1719
1720         eieio();
1721
1722         bdp->lstatus = lstatus;
1723 }
1724
1725
1726 struct sk_buff * gfar_new_skb(struct net_device *dev)
1727 {
1728         unsigned int alignamount;
1729         struct gfar_private *priv = netdev_priv(dev);
1730         struct sk_buff *skb = NULL;
1731
1732         skb = __skb_dequeue(&priv->rx_recycle);
1733         if (!skb)
1734                 skb = netdev_alloc_skb(dev,
1735                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1736
1737         if (!skb)
1738                 return NULL;
1739
1740         alignamount = RXBUF_ALIGNMENT -
1741                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1742
1743         /* We need the data buffer to be aligned properly.  We will reserve
1744          * as many bytes as needed to align the data properly
1745          */
1746         skb_reserve(skb, alignamount);
1747
1748         return skb;
1749 }
1750
1751 static inline void count_errors(unsigned short status, struct net_device *dev)
1752 {
1753         struct gfar_private *priv = netdev_priv(dev);
1754         struct net_device_stats *stats = &dev->stats;
1755         struct gfar_extra_stats *estats = &priv->extra_stats;
1756
1757         /* If the packet was truncated, none of the other errors
1758          * matter */
1759         if (status & RXBD_TRUNCATED) {
1760                 stats->rx_length_errors++;
1761
1762                 estats->rx_trunc++;
1763
1764                 return;
1765         }
1766         /* Count the errors, if there were any */
1767         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1768                 stats->rx_length_errors++;
1769
1770                 if (status & RXBD_LARGE)
1771                         estats->rx_large++;
1772                 else
1773                         estats->rx_short++;
1774         }
1775         if (status & RXBD_NONOCTET) {
1776                 stats->rx_frame_errors++;
1777                 estats->rx_nonoctet++;
1778         }
1779         if (status & RXBD_CRCERR) {
1780                 estats->rx_crcerr++;
1781                 stats->rx_crc_errors++;
1782         }
1783         if (status & RXBD_OVERRUN) {
1784                 estats->rx_overrun++;
1785                 stats->rx_crc_errors++;
1786         }
1787 }
1788
1789 irqreturn_t gfar_receive(int irq, void *dev_id)
1790 {
1791         gfar_schedule_cleanup((struct net_device *)dev_id);
1792         return IRQ_HANDLED;
1793 }
1794
1795 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1796 {
1797         /* If valid headers were found, and valid sums
1798          * were verified, then we tell the kernel that no
1799          * checksumming is necessary.  Otherwise, it is */
1800         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1801                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1802         else
1803                 skb->ip_summed = CHECKSUM_NONE;
1804 }
1805
1806
1807 /* gfar_process_frame() -- handle one incoming packet if skb
1808  * isn't NULL.  */
1809 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1810                               int amount_pull)
1811 {
1812         struct gfar_private *priv = netdev_priv(dev);
1813         struct rxfcb *fcb = NULL;
1814
1815         int ret;
1816
1817         /* fcb is at the beginning if exists */
1818         fcb = (struct rxfcb *)skb->data;
1819
1820         /* Remove the FCB from the skb */
1821         /* Remove the padded bytes, if there are any */
1822         if (amount_pull)
1823                 skb_pull(skb, amount_pull);
1824
1825         if (priv->rx_csum_enable)
1826                 gfar_rx_checksum(skb, fcb);
1827
1828         /* Tell the skb what kind of packet this is */
1829         skb->protocol = eth_type_trans(skb, dev);
1830
1831         /* Send the packet up the stack */
1832         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1833                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1834         else
1835                 ret = netif_receive_skb(skb);
1836
1837         if (NET_RX_DROP == ret)
1838                 priv->extra_stats.kernel_dropped++;
1839
1840         return 0;
1841 }
1842
1843 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1844  *   until the budget/quota has been reached. Returns the number
1845  *   of frames handled
1846  */
1847 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1848 {
1849         struct rxbd8 *bdp, *base;
1850         struct sk_buff *skb;
1851         int pkt_len;
1852         int amount_pull;
1853         int howmany = 0;
1854         struct gfar_private *priv = netdev_priv(dev);
1855
1856         /* Get the first full descriptor */
1857         bdp = priv->cur_rx;
1858         base = priv->rx_bd_base;
1859
1860         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1861                 priv->padding;
1862
1863         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1864                 struct sk_buff *newskb;
1865                 rmb();
1866
1867                 /* Add another skb for the future */
1868                 newskb = gfar_new_skb(dev);
1869
1870                 skb = priv->rx_skbuff[priv->skb_currx];
1871
1872                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1873                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1874
1875                 /* We drop the frame if we failed to allocate a new buffer */
1876                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1877                                  bdp->status & RXBD_ERR)) {
1878                         count_errors(bdp->status, dev);
1879
1880                         if (unlikely(!newskb))
1881                                 newskb = skb;
1882                         else if (skb)
1883                                 __skb_queue_head(&priv->rx_recycle, skb);
1884                 } else {
1885                         /* Increment the number of packets */
1886                         dev->stats.rx_packets++;
1887                         howmany++;
1888
1889                         if (likely(skb)) {
1890                                 pkt_len = bdp->length - ETH_FCS_LEN;
1891                                 /* Remove the FCS from the packet length */
1892                                 skb_put(skb, pkt_len);
1893                                 dev->stats.rx_bytes += pkt_len;
1894
1895                                 if (in_irq() || irqs_disabled())
1896                                         printk("Interrupt problem!\n");
1897                                 gfar_process_frame(dev, skb, amount_pull);
1898
1899                         } else {
1900                                 if (netif_msg_rx_err(priv))
1901                                         printk(KERN_WARNING
1902                                                "%s: Missing skb!\n", dev->name);
1903                                 dev->stats.rx_dropped++;
1904                                 priv->extra_stats.rx_skbmissing++;
1905                         }
1906
1907                 }
1908
1909                 priv->rx_skbuff[priv->skb_currx] = newskb;
1910
1911                 /* Setup the new bdp */
1912                 gfar_new_rxbdp(dev, bdp, newskb);
1913
1914                 /* Update to the next pointer */
1915                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1916
1917                 /* update to point at the next skb */
1918                 priv->skb_currx =
1919                     (priv->skb_currx + 1) &
1920                     RX_RING_MOD_MASK(priv->rx_ring_size);
1921         }
1922
1923         /* Update the current rxbd pointer to be the next one */
1924         priv->cur_rx = bdp;
1925
1926         return howmany;
1927 }
1928
1929 static int gfar_poll(struct napi_struct *napi, int budget)
1930 {
1931         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1932         struct net_device *dev = priv->ndev;
1933         int tx_cleaned = 0;
1934         int rx_cleaned = 0;
1935         unsigned long flags;
1936
1937         /* Clear IEVENT, so interrupts aren't called again
1938          * because of the packets that have already arrived */
1939         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1940
1941         /* If we fail to get the lock, don't bother with the TX BDs */
1942         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1943                 tx_cleaned = gfar_clean_tx_ring(dev);
1944                 spin_unlock_irqrestore(&priv->txlock, flags);
1945         }
1946
1947         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1948
1949         if (tx_cleaned)
1950                 return budget;
1951
1952         if (rx_cleaned < budget) {
1953                 napi_complete(napi);
1954
1955                 /* Clear the halt bit in RSTAT */
1956                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1957
1958                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1959
1960                 /* If we are coalescing interrupts, update the timer */
1961                 /* Otherwise, clear it */
1962                 if (likely(priv->rxcoalescing)) {
1963                         gfar_write(&priv->regs->rxic, 0);
1964                         gfar_write(&priv->regs->rxic, priv->rxic);
1965                 }
1966                 if (likely(priv->txcoalescing)) {
1967                         gfar_write(&priv->regs->txic, 0);
1968                         gfar_write(&priv->regs->txic, priv->txic);
1969                 }
1970         }
1971
1972         return rx_cleaned;
1973 }
1974
1975 #ifdef CONFIG_NET_POLL_CONTROLLER
1976 /*
1977  * Polling 'interrupt' - used by things like netconsole to send skbs
1978  * without having to re-enable interrupts. It's not called while
1979  * the interrupt routine is executing.
1980  */
1981 static void gfar_netpoll(struct net_device *dev)
1982 {
1983         struct gfar_private *priv = netdev_priv(dev);
1984
1985         /* If the device has multiple interrupts, run tx/rx */
1986         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1987                 disable_irq(priv->interruptTransmit);
1988                 disable_irq(priv->interruptReceive);
1989                 disable_irq(priv->interruptError);
1990                 gfar_interrupt(priv->interruptTransmit, dev);
1991                 enable_irq(priv->interruptError);
1992                 enable_irq(priv->interruptReceive);
1993                 enable_irq(priv->interruptTransmit);
1994         } else {
1995                 disable_irq(priv->interruptTransmit);
1996                 gfar_interrupt(priv->interruptTransmit, dev);
1997                 enable_irq(priv->interruptTransmit);
1998         }
1999 }
2000 #endif
2001
2002 /* The interrupt handler for devices with one interrupt */
2003 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
2004 {
2005         struct net_device *dev = dev_id;
2006         struct gfar_private *priv = netdev_priv(dev);
2007
2008         /* Save ievent for future reference */
2009         u32 events = gfar_read(&priv->regs->ievent);
2010
2011         /* Check for reception */
2012         if (events & IEVENT_RX_MASK)
2013                 gfar_receive(irq, dev_id);
2014
2015         /* Check for transmit completion */
2016         if (events & IEVENT_TX_MASK)
2017                 gfar_transmit(irq, dev_id);
2018
2019         /* Check for errors */
2020         if (events & IEVENT_ERR_MASK)
2021                 gfar_error(irq, dev_id);
2022
2023         return IRQ_HANDLED;
2024 }
2025
2026 /* Called every time the controller might need to be made
2027  * aware of new link state.  The PHY code conveys this
2028  * information through variables in the phydev structure, and this
2029  * function converts those variables into the appropriate
2030  * register values, and can bring down the device if needed.
2031  */
2032 static void adjust_link(struct net_device *dev)
2033 {
2034         struct gfar_private *priv = netdev_priv(dev);
2035         struct gfar __iomem *regs = priv->regs;
2036         unsigned long flags;
2037         struct phy_device *phydev = priv->phydev;
2038         int new_state = 0;
2039
2040         spin_lock_irqsave(&priv->txlock, flags);
2041         if (phydev->link) {
2042                 u32 tempval = gfar_read(&regs->maccfg2);
2043                 u32 ecntrl = gfar_read(&regs->ecntrl);
2044
2045                 /* Now we make sure that we can be in full duplex mode.
2046                  * If not, we operate in half-duplex mode. */
2047                 if (phydev->duplex != priv->oldduplex) {
2048                         new_state = 1;
2049                         if (!(phydev->duplex))
2050                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2051                         else
2052                                 tempval |= MACCFG2_FULL_DUPLEX;
2053
2054                         priv->oldduplex = phydev->duplex;
2055                 }
2056
2057                 if (phydev->speed != priv->oldspeed) {
2058                         new_state = 1;
2059                         switch (phydev->speed) {
2060                         case 1000:
2061                                 tempval =
2062                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2063
2064                                 ecntrl &= ~(ECNTRL_R100);
2065                                 break;
2066                         case 100:
2067                         case 10:
2068                                 tempval =
2069                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2070
2071                                 /* Reduced mode distinguishes
2072                                  * between 10 and 100 */
2073                                 if (phydev->speed == SPEED_100)
2074                                         ecntrl |= ECNTRL_R100;
2075                                 else
2076                                         ecntrl &= ~(ECNTRL_R100);
2077                                 break;
2078                         default:
2079                                 if (netif_msg_link(priv))
2080                                         printk(KERN_WARNING
2081                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2082                                                 dev->name, phydev->speed);
2083                                 break;
2084                         }
2085
2086                         priv->oldspeed = phydev->speed;
2087                 }
2088
2089                 gfar_write(&regs->maccfg2, tempval);
2090                 gfar_write(&regs->ecntrl, ecntrl);
2091
2092                 if (!priv->oldlink) {
2093                         new_state = 1;
2094                         priv->oldlink = 1;
2095                 }
2096         } else if (priv->oldlink) {
2097                 new_state = 1;
2098                 priv->oldlink = 0;
2099                 priv->oldspeed = 0;
2100                 priv->oldduplex = -1;
2101         }
2102
2103         if (new_state && netif_msg_link(priv))
2104                 phy_print_status(phydev);
2105
2106         spin_unlock_irqrestore(&priv->txlock, flags);
2107 }
2108
2109 /* Update the hash table based on the current list of multicast
2110  * addresses we subscribe to.  Also, change the promiscuity of
2111  * the device based on the flags (this function is called
2112  * whenever dev->flags is changed */
2113 static void gfar_set_multi(struct net_device *dev)
2114 {
2115         struct dev_mc_list *mc_ptr;
2116         struct gfar_private *priv = netdev_priv(dev);
2117         struct gfar __iomem *regs = priv->regs;
2118         u32 tempval;
2119
2120         if(dev->flags & IFF_PROMISC) {
2121                 /* Set RCTRL to PROM */
2122                 tempval = gfar_read(&regs->rctrl);
2123                 tempval |= RCTRL_PROM;
2124                 gfar_write(&regs->rctrl, tempval);
2125         } else {
2126                 /* Set RCTRL to not PROM */
2127                 tempval = gfar_read(&regs->rctrl);
2128                 tempval &= ~(RCTRL_PROM);
2129                 gfar_write(&regs->rctrl, tempval);
2130         }
2131
2132         if(dev->flags & IFF_ALLMULTI) {
2133                 /* Set the hash to rx all multicast frames */
2134                 gfar_write(&regs->igaddr0, 0xffffffff);
2135                 gfar_write(&regs->igaddr1, 0xffffffff);
2136                 gfar_write(&regs->igaddr2, 0xffffffff);
2137                 gfar_write(&regs->igaddr3, 0xffffffff);
2138                 gfar_write(&regs->igaddr4, 0xffffffff);
2139                 gfar_write(&regs->igaddr5, 0xffffffff);
2140                 gfar_write(&regs->igaddr6, 0xffffffff);
2141                 gfar_write(&regs->igaddr7, 0xffffffff);
2142                 gfar_write(&regs->gaddr0, 0xffffffff);
2143                 gfar_write(&regs->gaddr1, 0xffffffff);
2144                 gfar_write(&regs->gaddr2, 0xffffffff);
2145                 gfar_write(&regs->gaddr3, 0xffffffff);
2146                 gfar_write(&regs->gaddr4, 0xffffffff);
2147                 gfar_write(&regs->gaddr5, 0xffffffff);
2148                 gfar_write(&regs->gaddr6, 0xffffffff);
2149                 gfar_write(&regs->gaddr7, 0xffffffff);
2150         } else {
2151                 int em_num;
2152                 int idx;
2153
2154                 /* zero out the hash */
2155                 gfar_write(&regs->igaddr0, 0x0);
2156                 gfar_write(&regs->igaddr1, 0x0);
2157                 gfar_write(&regs->igaddr2, 0x0);
2158                 gfar_write(&regs->igaddr3, 0x0);
2159                 gfar_write(&regs->igaddr4, 0x0);
2160                 gfar_write(&regs->igaddr5, 0x0);
2161                 gfar_write(&regs->igaddr6, 0x0);
2162                 gfar_write(&regs->igaddr7, 0x0);
2163                 gfar_write(&regs->gaddr0, 0x0);
2164                 gfar_write(&regs->gaddr1, 0x0);
2165                 gfar_write(&regs->gaddr2, 0x0);
2166                 gfar_write(&regs->gaddr3, 0x0);
2167                 gfar_write(&regs->gaddr4, 0x0);
2168                 gfar_write(&regs->gaddr5, 0x0);
2169                 gfar_write(&regs->gaddr6, 0x0);
2170                 gfar_write(&regs->gaddr7, 0x0);
2171
2172                 /* If we have extended hash tables, we need to
2173                  * clear the exact match registers to prepare for
2174                  * setting them */
2175                 if (priv->extended_hash) {
2176                         em_num = GFAR_EM_NUM + 1;
2177                         gfar_clear_exact_match(dev);
2178                         idx = 1;
2179                 } else {
2180                         idx = 0;
2181                         em_num = 0;
2182                 }
2183
2184                 if(dev->mc_count == 0)
2185                         return;
2186
2187                 /* Parse the list, and set the appropriate bits */
2188                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2189                         if (idx < em_num) {
2190                                 gfar_set_mac_for_addr(dev, idx,
2191                                                 mc_ptr->dmi_addr);
2192                                 idx++;
2193                         } else
2194                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2195                 }
2196         }
2197
2198         return;
2199 }
2200
2201
2202 /* Clears each of the exact match registers to zero, so they
2203  * don't interfere with normal reception */
2204 static void gfar_clear_exact_match(struct net_device *dev)
2205 {
2206         int idx;
2207         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2208
2209         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2210                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2211 }
2212
2213 /* Set the appropriate hash bit for the given addr */
2214 /* The algorithm works like so:
2215  * 1) Take the Destination Address (ie the multicast address), and
2216  * do a CRC on it (little endian), and reverse the bits of the
2217  * result.
2218  * 2) Use the 8 most significant bits as a hash into a 256-entry
2219  * table.  The table is controlled through 8 32-bit registers:
2220  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2221  * gaddr7.  This means that the 3 most significant bits in the
2222  * hash index which gaddr register to use, and the 5 other bits
2223  * indicate which bit (assuming an IBM numbering scheme, which
2224  * for PowerPC (tm) is usually the case) in the register holds
2225  * the entry. */
2226 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2227 {
2228         u32 tempval;
2229         struct gfar_private *priv = netdev_priv(dev);
2230         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2231         int width = priv->hash_width;
2232         u8 whichbit = (result >> (32 - width)) & 0x1f;
2233         u8 whichreg = result >> (32 - width + 5);
2234         u32 value = (1 << (31-whichbit));
2235
2236         tempval = gfar_read(priv->hash_regs[whichreg]);
2237         tempval |= value;
2238         gfar_write(priv->hash_regs[whichreg], tempval);
2239
2240         return;
2241 }
2242
2243
2244 /* There are multiple MAC Address register pairs on some controllers
2245  * This function sets the numth pair to a given address
2246  */
2247 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2248 {
2249         struct gfar_private *priv = netdev_priv(dev);
2250         int idx;
2251         char tmpbuf[MAC_ADDR_LEN];
2252         u32 tempval;
2253         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2254
2255         macptr += num*2;
2256
2257         /* Now copy it into the mac registers backwards, cuz */
2258         /* little endian is silly */
2259         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2260                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2261
2262         gfar_write(macptr, *((u32 *) (tmpbuf)));
2263
2264         tempval = *((u32 *) (tmpbuf + 4));
2265
2266         gfar_write(macptr+1, tempval);
2267 }
2268
2269 /* GFAR error interrupt handler */
2270 static irqreturn_t gfar_error(int irq, void *dev_id)
2271 {
2272         struct net_device *dev = dev_id;
2273         struct gfar_private *priv = netdev_priv(dev);
2274
2275         /* Save ievent for future reference */
2276         u32 events = gfar_read(&priv->regs->ievent);
2277
2278         /* Clear IEVENT */
2279         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2280
2281         /* Magic Packet is not an error. */
2282         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2283             (events & IEVENT_MAG))
2284                 events &= ~IEVENT_MAG;
2285
2286         /* Hmm... */
2287         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2288                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2289                        dev->name, events, gfar_read(&priv->regs->imask));
2290
2291         /* Update the error counters */
2292         if (events & IEVENT_TXE) {
2293                 dev->stats.tx_errors++;
2294
2295                 if (events & IEVENT_LC)
2296                         dev->stats.tx_window_errors++;
2297                 if (events & IEVENT_CRL)
2298                         dev->stats.tx_aborted_errors++;
2299                 if (events & IEVENT_XFUN) {
2300                         if (netif_msg_tx_err(priv))
2301                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2302                                        "packet dropped.\n", dev->name);
2303                         dev->stats.tx_dropped++;
2304                         priv->extra_stats.tx_underrun++;
2305
2306                         /* Reactivate the Tx Queues */
2307                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2308                 }
2309                 if (netif_msg_tx_err(priv))
2310                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2311         }
2312         if (events & IEVENT_BSY) {
2313                 dev->stats.rx_errors++;
2314                 priv->extra_stats.rx_bsy++;
2315
2316                 gfar_receive(irq, dev_id);
2317
2318                 if (netif_msg_rx_err(priv))
2319                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2320                                dev->name, gfar_read(&priv->regs->rstat));
2321         }
2322         if (events & IEVENT_BABR) {
2323                 dev->stats.rx_errors++;
2324                 priv->extra_stats.rx_babr++;
2325
2326                 if (netif_msg_rx_err(priv))
2327                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2328         }
2329         if (events & IEVENT_EBERR) {
2330                 priv->extra_stats.eberr++;
2331                 if (netif_msg_rx_err(priv))
2332                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2333         }
2334         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2335                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2336
2337         if (events & IEVENT_BABT) {
2338                 priv->extra_stats.tx_babt++;
2339                 if (netif_msg_tx_err(priv))
2340                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2341         }
2342         return IRQ_HANDLED;
2343 }
2344
2345 /* work with hotplug and coldplug */
2346 MODULE_ALIAS("platform:fsl-gianfar");
2347
2348 static struct of_device_id gfar_match[] =
2349 {
2350         {
2351                 .type = "network",
2352                 .compatible = "gianfar",
2353         },
2354         {},
2355 };
2356
2357 /* Structure for a device driver */
2358 static struct of_platform_driver gfar_driver = {
2359         .name = "fsl-gianfar",
2360         .match_table = gfar_match,
2361
2362         .probe = gfar_probe,
2363         .remove = gfar_remove,
2364         .suspend = gfar_suspend,
2365         .resume = gfar_resume,
2366 };
2367
2368 static int __init gfar_init(void)
2369 {
2370         return of_register_platform_driver(&gfar_driver);
2371 }
2372
2373 static void __exit gfar_exit(void)
2374 {
2375         of_unregister_platform_driver(&gfar_driver);
2376 }
2377
2378 module_init(gfar_init);
2379 module_exit(gfar_exit);
2380