drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 113  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 114  *      0.59: 30 Oct 2006: Added support for recoverable error.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.59"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162
 163 /*
 164  * Hardware access:
 165  */
 166
 167 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 168 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 169 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 170 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 171 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 172 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 173 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 174 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 175 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 176 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 177 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 178 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 179 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
 180
 181 enum {
 182         NvRegIrqStatus = 0x000,
 183 #define NVREG_IRQSTAT_MIIEVENT  0x040
 184 #define NVREG_IRQSTAT_MASK              0x81ff
 185         NvRegIrqMask = 0x004,
 186 #define NVREG_IRQ_RX_ERROR              0x0001
 187 #define NVREG_IRQ_RX                    0x0002
 188 #define NVREG_IRQ_RX_NOBUF              0x0004
 189 #define NVREG_IRQ_TX_ERR                0x0008
 190 #define NVREG_IRQ_TX_OK                 0x0010
 191 #define NVREG_IRQ_TIMER                 0x0020
 192 #define NVREG_IRQ_LINK                  0x0040
 193 #define NVREG_IRQ_RX_FORCED             0x0080
 194 #define NVREG_IRQ_TX_FORCED             0x0100
 195 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 196 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 197 #define NVREG_IRQMASK_CPU               0x0040
 198 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 199 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 200 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 201
 202 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 203                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 204                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 205
 206         NvRegUnknownSetupReg6 = 0x008,
 207 #define NVREG_UNKSETUP6_VAL             3
 208
 209 /*
 210  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 211  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 212  */
 213         NvRegPollingInterval = 0x00c,
 214 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 215 #define NVREG_POLL_DEFAULT_CPU  13
 216         NvRegMSIMap0 = 0x020,
 217         NvRegMSIMap1 = 0x024,
 218         NvRegMSIIrqMask = 0x030,
 219 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 220         NvRegMisc1 = 0x080,
 221 #define NVREG_MISC1_PAUSE_TX    0x01
 222 #define NVREG_MISC1_HD          0x02
 223 #define NVREG_MISC1_FORCE       0x3b0f3c
 224
 225         NvRegMacReset = 0x3c,
 226 #define NVREG_MAC_RESET_ASSERT  0x0F3
 227         NvRegTransmitterControl = 0x084,
 228 #define NVREG_XMITCTL_START     0x01
 229 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 230 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 231 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 232 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 233 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 234 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 235 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 236 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 237 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 238         NvRegTransmitterStatus = 0x088,
 239 #define NVREG_XMITSTAT_BUSY     0x01
 240
 241         NvRegPacketFilterFlags = 0x8c,
 242 #define NVREG_PFF_PAUSE_RX      0x08
 243 #define NVREG_PFF_ALWAYS        0x7F0000
 244 #define NVREG_PFF_PROMISC       0x80
 245 #define NVREG_PFF_MYADDR        0x20
 246 #define NVREG_PFF_LOOPBACK      0x10
 247
 248         NvRegOffloadConfig = 0x90,
 249 #define NVREG_OFFLOAD_HOMEPHY   0x601
 250 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 251         NvRegReceiverControl = 0x094,
 252 #define NVREG_RCVCTL_START      0x01
 253         NvRegReceiverStatus = 0x98,
 254 #define NVREG_RCVSTAT_BUSY      0x01
 255
 256         NvRegRandomSeed = 0x9c,
 257 #define NVREG_RNDSEED_MASK      0x00ff
 258 #define NVREG_RNDSEED_FORCE     0x7f00
 259 #define NVREG_RNDSEED_FORCE2    0x2d00
 260 #define NVREG_RNDSEED_FORCE3    0x7400
 261
 262         NvRegTxDeferral = 0xA0,
 263 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 264 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 265 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 266         NvRegRxDeferral = 0xA4,
 267 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 268         NvRegMacAddrA = 0xA8,
 269         NvRegMacAddrB = 0xAC,
 270         NvRegMulticastAddrA = 0xB0,
 271 #define NVREG_MCASTADDRA_FORCE  0x01
 272         NvRegMulticastAddrB = 0xB4,
 273         NvRegMulticastMaskA = 0xB8,
 274         NvRegMulticastMaskB = 0xBC,
 275
 276         NvRegPhyInterface = 0xC0,
 277 #define PHY_RGMII               0x10000000
 278
 279         NvRegTxRingPhysAddr = 0x100,
 280         NvRegRxRingPhysAddr = 0x104,
 281         NvRegRingSizes = 0x108,
 282 #define NVREG_RINGSZ_TXSHIFT 0
 283 #define NVREG_RINGSZ_RXSHIFT 16
 284         NvRegTransmitPoll = 0x10c,
 285 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 286         NvRegLinkSpeed = 0x110,
 287 #define NVREG_LINKSPEED_FORCE 0x10000
 288 #define NVREG_LINKSPEED_10      1000
 289 #define NVREG_LINKSPEED_100     100
 290 #define NVREG_LINKSPEED_1000    50
 291 #define NVREG_LINKSPEED_MASK    (0xFFF)
 292         NvRegUnknownSetupReg5 = 0x130,
 293 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 294         NvRegTxWatermark = 0x13c,
 295 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 296 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 297 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 298         NvRegTxRxControl = 0x144,
 299 #define NVREG_TXRXCTL_KICK      0x0001
 300 #define NVREG_TXRXCTL_BIT1      0x0002
 301 #define NVREG_TXRXCTL_BIT2      0x0004
 302 #define NVREG_TXRXCTL_IDLE      0x0008
 303 #define NVREG_TXRXCTL_RESET     0x0010
 304 #define NVREG_TXRXCTL_RXCHECK   0x0400
 305 #define NVREG_TXRXCTL_DESC_1    0
 306 #define NVREG_TXRXCTL_DESC_2    0x02100
 307 #define NVREG_TXRXCTL_DESC_3    0x02200
 308 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 309 #define NVREG_TXRXCTL_VLANINS   0x00080
 310         NvRegTxRingPhysAddrHigh = 0x148,
 311         NvRegRxRingPhysAddrHigh = 0x14C,
 312         NvRegTxPauseFrame = 0x170,
 313 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 314 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 315         NvRegMIIStatus = 0x180,
 316 #define NVREG_MIISTAT_ERROR             0x0001
 317 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 318 #define NVREG_MIISTAT_MASK              0x000f
 319 #define NVREG_MIISTAT_MASK2             0x000f
 320         NvRegMIIMask = 0x184,
 321 #define NVREG_MII_LINKCHANGE            0x0008
 322
 323         NvRegAdapterControl = 0x188,
 324 #define NVREG_ADAPTCTL_START    0x02
 325 #define NVREG_ADAPTCTL_LINKUP   0x04
 326 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 327 #define NVREG_ADAPTCTL_RUNNING  0x100000
 328 #define NVREG_ADAPTCTL_PHYSHIFT 24
 329         NvRegMIISpeed = 0x18c,
 330 #define NVREG_MIISPEED_BIT8     (1<<8)
 331 #define NVREG_MIIDELAY  5
 332         NvRegMIIControl = 0x190,
 333 #define NVREG_MIICTL_INUSE      0x08000
 334 #define NVREG_MIICTL_WRITE      0x00400
 335 #define NVREG_MIICTL_ADDRSHIFT  5
 336         NvRegMIIData = 0x194,
 337         NvRegWakeUpFlags = 0x200,
 338 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 339 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 340 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 341 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 342 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 343 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 344 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 345 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 346 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 347 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 348 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 349
 350         NvRegPatternCRC = 0x204,
 351         NvRegPatternMask = 0x208,
 352         NvRegPowerCap = 0x268,
 353 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 354 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 355 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 356         NvRegPowerState = 0x26c,
 357 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 358 #define NVREG_POWERSTATE_VALID          0x0100
 359 #define NVREG_POWERSTATE_MASK           0x0003
 360 #define NVREG_POWERSTATE_D0             0x0000
 361 #define NVREG_POWERSTATE_D1             0x0001
 362 #define NVREG_POWERSTATE_D2             0x0002
 363 #define NVREG_POWERSTATE_D3             0x0003
 364         NvRegTxCnt = 0x280,
 365         NvRegTxZeroReXmt = 0x284,
 366         NvRegTxOneReXmt = 0x288,
 367         NvRegTxManyReXmt = 0x28c,
 368         NvRegTxLateCol = 0x290,
 369         NvRegTxUnderflow = 0x294,
 370         NvRegTxLossCarrier = 0x298,
 371         NvRegTxExcessDef = 0x29c,
 372         NvRegTxRetryErr = 0x2a0,
 373         NvRegRxFrameErr = 0x2a4,
 374         NvRegRxExtraByte = 0x2a8,
 375         NvRegRxLateCol = 0x2ac,
 376         NvRegRxRunt = 0x2b0,
 377         NvRegRxFrameTooLong = 0x2b4,
 378         NvRegRxOverflow = 0x2b8,
 379         NvRegRxFCSErr = 0x2bc,
 380         NvRegRxFrameAlignErr = 0x2c0,
 381         NvRegRxLenErr = 0x2c4,
 382         NvRegRxUnicast = 0x2c8,
 383         NvRegRxMulticast = 0x2cc,
 384         NvRegRxBroadcast = 0x2d0,
 385         NvRegTxDef = 0x2d4,
 386         NvRegTxFrame = 0x2d8,
 387         NvRegRxCnt = 0x2dc,
 388         NvRegTxPause = 0x2e0,
 389         NvRegRxPause = 0x2e4,
 390         NvRegRxDropFrame = 0x2e8,
 391         NvRegVlanControl = 0x300,
 392 #define NVREG_VLANCONTROL_ENABLE        0x2000
 393         NvRegMSIXMap0 = 0x3e0,
 394         NvRegMSIXMap1 = 0x3e4,
 395         NvRegMSIXIrqStatus = 0x3f0,
 396
 397         NvRegPowerState2 = 0x600,
 398 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 399 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 400 };
 401
 402 /* Big endian: should work, but is untested */
 403 struct ring_desc {
 404         __le32 buf;
 405         __le32 flaglen;
 406 };
 407
 408 struct ring_desc_ex {
 409         __le32 bufhigh;
 410         __le32 buflow;
 411         __le32 txvlan;
 412         __le32 flaglen;
 413 };
 414
 415 union ring_type {
 416         struct ring_desc* orig;
 417         struct ring_desc_ex* ex;
 418 };
 419
 420 #define FLAG_MASK_V1 0xffff0000
 421 #define FLAG_MASK_V2 0xffffc000
 422 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 423 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 424
 425 #define NV_TX_LASTPACKET        (1<<16)
 426 #define NV_TX_RETRYERROR        (1<<19)
 427 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 428 #define NV_TX_DEFERRED          (1<<26)
 429 #define NV_TX_CARRIERLOST       (1<<27)
 430 #define NV_TX_LATECOLLISION     (1<<28)
 431 #define NV_TX_UNDERFLOW         (1<<29)
 432 #define NV_TX_ERROR             (1<<30)
 433 #define NV_TX_VALID             (1<<31)
 434
 435 #define NV_TX2_LASTPACKET       (1<<29)
 436 #define NV_TX2_RETRYERROR       (1<<18)
 437 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 438 #define NV_TX2_DEFERRED         (1<<25)
 439 #define NV_TX2_CARRIERLOST      (1<<26)
 440 #define NV_TX2_LATECOLLISION    (1<<27)
 441 #define NV_TX2_UNDERFLOW        (1<<28)
 442 /* error and valid are the same for both */
 443 #define NV_TX2_ERROR            (1<<30)
 444 #define NV_TX2_VALID            (1<<31)
 445 #define NV_TX2_TSO              (1<<28)
 446 #define NV_TX2_TSO_SHIFT        14
 447 #define NV_TX2_TSO_MAX_SHIFT    14
 448 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 449 #define NV_TX2_CHECKSUM_L3      (1<<27)
 450 #define NV_TX2_CHECKSUM_L4      (1<<26)
 451
 452 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 453
 454 #define NV_RX_DESCRIPTORVALID   (1<<16)
 455 #define NV_RX_MISSEDFRAME       (1<<17)
 456 #define NV_RX_SUBSTRACT1        (1<<18)
 457 #define NV_RX_ERROR1            (1<<23)
 458 #define NV_RX_ERROR2            (1<<24)
 459 #define NV_RX_ERROR3            (1<<25)
 460 #define NV_RX_ERROR4            (1<<26)
 461 #define NV_RX_CRCERR            (1<<27)
 462 #define NV_RX_OVERFLOW          (1<<28)
 463 #define NV_RX_FRAMINGERR        (1<<29)
 464 #define NV_RX_ERROR             (1<<30)
 465 #define NV_RX_AVAIL             (1<<31)
 466
 467 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 468 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 469 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 470 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 471 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 472 #define NV_RX2_SUBSTRACT1       (1<<25)
 473 #define NV_RX2_ERROR1           (1<<18)
 474 #define NV_RX2_ERROR2           (1<<19)
 475 #define NV_RX2_ERROR3           (1<<20)
 476 #define NV_RX2_ERROR4           (1<<21)
 477 #define NV_RX2_CRCERR           (1<<22)
 478 #define NV_RX2_OVERFLOW         (1<<23)
 479 #define NV_RX2_FRAMINGERR       (1<<24)
 480 /* error and avail are the same for both */
 481 #define NV_RX2_ERROR            (1<<30)
 482 #define NV_RX2_AVAIL            (1<<31)
 483
 484 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 485 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 486
 487 /* Miscelaneous hardware related defines: */
 488 #define NV_PCI_REGSZ_VER1       0x270
 489 #define NV_PCI_REGSZ_VER2       0x604
 490
 491 /* various timeout delays: all in usec */
 492 #define NV_TXRX_RESET_DELAY     4
 493 #define NV_TXSTOP_DELAY1        10
 494 #define NV_TXSTOP_DELAY1MAX     500000
 495 #define NV_TXSTOP_DELAY2        100
 496 #define NV_RXSTOP_DELAY1        10
 497 #define NV_RXSTOP_DELAY1MAX     500000
 498 #define NV_RXSTOP_DELAY2        100
 499 #define NV_SETUP5_DELAY         5
 500 #define NV_SETUP5_DELAYMAX      50000
 501 #define NV_POWERUP_DELAY        5
 502 #define NV_POWERUP_DELAYMAX     5000
 503 #define NV_MIIBUSY_DELAY        50
 504 #define NV_MIIPHY_DELAY 10
 505 #define NV_MIIPHY_DELAYMAX      10000
 506 #define NV_MAC_RESET_DELAY      64
 507
 508 #define NV_WAKEUPPATTERNS       5
 509 #define NV_WAKEUPMASKENTRIES    4
 510
 511 /* General driver defaults */
 512 #define NV_WATCHDOG_TIMEO       (5*HZ)
 513
 514 #define RX_RING_DEFAULT         128
 515 #define TX_RING_DEFAULT         256
 516 #define RX_RING_MIN             128
 517 #define TX_RING_MIN             64
 518 #define RING_MAX_DESC_VER_1     1024
 519 #define RING_MAX_DESC_VER_2_3   16384
 520 /*
 521  * Difference between the get and put pointers for the tx ring.
 522  * This is used to throttle the amount of data outstanding in the
 523  * tx ring.
 524  */
 525 #define TX_LIMIT_DIFFERENCE     1
 526
 527 /* rx/tx mac addr + type + vlan + align + slack*/
 528 #define NV_RX_HEADERS           (64)
 529 /* even more slack. */
 530 #define NV_RX_ALLOC_PAD         (64)
 531
 532 /* maximum mtu size */
 533 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 534 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 535
 536 #define OOM_REFILL      (1+HZ/20)
 537 #define POLL_WAIT       (1+HZ/100)
 538 #define LINK_TIMEOUT    (3*HZ)
 539 #define STATS_INTERVAL  (10*HZ)
 540
 541 /*
 542  * desc_ver values:
 543  * The nic supports three different descriptor types:
 544  * - DESC_VER_1: Original
 545  * - DESC_VER_2: support for jumbo frames.
 546  * - DESC_VER_3: 64-bit format.
 547  */
 548 #define DESC_VER_1      1
 549 #define DESC_VER_2      2
 550 #define DESC_VER_3      3
 551
 552 /* PHY defines */
 553 #define PHY_OUI_MARVELL 0x5043
 554 #define PHY_OUI_CICADA  0x03f1
 555 #define PHYID1_OUI_MASK 0x03ff
 556 #define PHYID1_OUI_SHFT 6
 557 #define PHYID2_OUI_MASK 0xfc00
 558 #define PHYID2_OUI_SHFT 10
 559 #define PHYID2_MODEL_MASK               0x03f0
 560 #define PHY_MODEL_MARVELL_E3016         0x220
 561 #define PHY_MARVELL_E3016_INITMASK      0x0300
 562 #define PHY_INIT1       0x0f000
 563 #define PHY_INIT2       0x0e00
 564 #define PHY_INIT3       0x01000
 565 #define PHY_INIT4       0x0200
 566 #define PHY_INIT5       0x0004
 567 #define PHY_INIT6       0x02000
 568 #define PHY_GIGABIT     0x0100
 569
 570 #define PHY_TIMEOUT     0x1
 571 #define PHY_ERROR       0x2
 572
 573 #define PHY_100 0x1
 574 #define PHY_1000        0x2
 575 #define PHY_HALF        0x100
 576
 577 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 578 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 579 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 580 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 581 #define NV_PAUSEFRAME_RX_REQ     0x0010
 582 #define NV_PAUSEFRAME_TX_REQ     0x0020
 583 #define NV_PAUSEFRAME_AUTONEG    0x0040
 584
 585 /* MSI/MSI-X defines */
 586 #define NV_MSI_X_MAX_VECTORS  8
 587 #define NV_MSI_X_VECTORS_MASK 0x000f
 588 #define NV_MSI_CAPABLE        0x0010
 589 #define NV_MSI_X_CAPABLE      0x0020
 590 #define NV_MSI_ENABLED        0x0040
 591 #define NV_MSI_X_ENABLED      0x0080
 592
 593 #define NV_MSI_X_VECTOR_ALL   0x0
 594 #define NV_MSI_X_VECTOR_RX    0x0
 595 #define NV_MSI_X_VECTOR_TX    0x1
 596 #define NV_MSI_X_VECTOR_OTHER 0x2
 597
 598 /* statistics */
 599 struct nv_ethtool_str {
 600         char name[ETH_GSTRING_LEN];
 601 };
 602
 603 static const struct nv_ethtool_str nv_estats_str[] = {
 604         { "tx_bytes" },
 605         { "tx_zero_rexmt" },
 606         { "tx_one_rexmt" },
 607         { "tx_many_rexmt" },
 608         { "tx_late_collision" },
 609         { "tx_fifo_errors" },
 610         { "tx_carrier_errors" },
 611         { "tx_excess_deferral" },
 612         { "tx_retry_error" },
 613         { "tx_deferral" },
 614         { "tx_packets" },
 615         { "tx_pause" },
 616         { "rx_frame_error" },
 617         { "rx_extra_byte" },
 618         { "rx_late_collision" },
 619         { "rx_runt" },
 620         { "rx_frame_too_long" },
 621         { "rx_over_errors" },
 622         { "rx_crc_errors" },
 623         { "rx_frame_align_error" },
 624         { "rx_length_error" },
 625         { "rx_unicast" },
 626         { "rx_multicast" },
 627         { "rx_broadcast" },
 628         { "rx_bytes" },
 629         { "rx_pause" },
 630         { "rx_drop_frame" },
 631         { "rx_packets" },
 632         { "rx_errors_total" }
 633 };
 634
 635 struct nv_ethtool_stats {
 636         u64 tx_bytes;
 637         u64 tx_zero_rexmt;
 638         u64 tx_one_rexmt;
 639         u64 tx_many_rexmt;
 640         u64 tx_late_collision;
 641         u64 tx_fifo_errors;
 642         u64 tx_carrier_errors;
 643         u64 tx_excess_deferral;
 644         u64 tx_retry_error;
 645         u64 tx_deferral;
 646         u64 tx_packets;
 647         u64 tx_pause;
 648         u64 rx_frame_error;
 649         u64 rx_extra_byte;
 650         u64 rx_late_collision;
 651         u64 rx_runt;
 652         u64 rx_frame_too_long;
 653         u64 rx_over_errors;
 654         u64 rx_crc_errors;
 655         u64 rx_frame_align_error;
 656         u64 rx_length_error;
 657         u64 rx_unicast;
 658         u64 rx_multicast;
 659         u64 rx_broadcast;
 660         u64 rx_bytes;
 661         u64 rx_pause;
 662         u64 rx_drop_frame;
 663         u64 rx_packets;
 664         u64 rx_errors_total;
 665 };
 666
 667 /* diagnostics */
 668 #define NV_TEST_COUNT_BASE 3
 669 #define NV_TEST_COUNT_EXTENDED 4
 670
 671 static const struct nv_ethtool_str nv_etests_str[] = {
 672         { "link      (online/offline)" },
 673         { "register  (offline)       " },
 674         { "interrupt (offline)       " },
 675         { "loopback  (offline)       " }
 676 };
 677
 678 struct register_test {
 679         __le32 reg;
 680         __le32 mask;
 681 };
 682
 683 static const struct register_test nv_registers_test[] = {
 684         { NvRegUnknownSetupReg6, 0x01 },
 685         { NvRegMisc1, 0x03c },
 686         { NvRegOffloadConfig, 0x03ff },
 687         { NvRegMulticastAddrA, 0xffffffff },
 688         { NvRegTxWatermark, 0x0ff },
 689         { NvRegWakeUpFlags, 0x07777 },
 690         { 0,0 }
 691 };
 692
 693 /*
 694  * SMP locking:
 695  * All hardware access under dev->priv->lock, except the performance
 696  * critical parts:
 697  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 698  *      by the arch code for interrupts.
 699  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 700  *      needs dev->priv->lock :-(
 701  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 702  */
 703
 704 /* in dev: base, irq */
 705 struct fe_priv {
 706         spinlock_t lock;
 707
 708         /* General data:
 709          * Locking: spin_lock(&np->lock); */
 710         struct net_device_stats stats;
 711         struct nv_ethtool_stats estats;
 712         int in_shutdown;
 713         u32 linkspeed;
 714         int duplex;
 715         int autoneg;
 716         int fixed_mode;
 717         int phyaddr;
 718         int wolenabled;
 719         unsigned int phy_oui;
 720         unsigned int phy_model;
 721         u16 gigabit;
 722         int intr_test;
 723         int recover_error;
 724
 725         /* General data: RO fields */
 726         dma_addr_t ring_addr;
 727         struct pci_dev *pci_dev;
 728         u32 orig_mac[2];
 729         u32 irqmask;
 730         u32 desc_ver;
 731         u32 txrxctl_bits;
 732         u32 vlanctl_bits;
 733         u32 driver_data;
 734         u32 register_size;
 735         int rx_csum;
 736         u32 mac_in_use;
 737
 738         void __iomem *base;
 739
 740         /* rx specific fields.
 741          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 742          */
 743         union ring_type rx_ring;
 744         unsigned int cur_rx, refill_rx;
 745         struct sk_buff **rx_skbuff;
 746         dma_addr_t *rx_dma;
 747         unsigned int rx_buf_sz;
 748         unsigned int pkt_limit;
 749         struct timer_list oom_kick;
 750         struct timer_list nic_poll;
 751         struct timer_list stats_poll;
 752         u32 nic_poll_irq;
 753         int rx_ring_size;
 754
 755         /* media detection workaround.
 756          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 757          */
 758         int need_linktimer;
 759         unsigned long link_timeout;
 760         /*
 761          * tx specific fields.
 762          */
 763         union ring_type tx_ring;
 764         unsigned int next_tx, nic_tx;
 765         struct sk_buff **tx_skbuff;
 766         dma_addr_t *tx_dma;
 767         unsigned int *tx_dma_len;
 768         u32 tx_flags;
 769         int tx_ring_size;
 770         int tx_limit_start;
 771         int tx_limit_stop;
 772
 773         /* vlan fields */
 774         struct vlan_group *vlangrp;
 775
 776         /* msi/msi-x fields */
 777         u32 msi_flags;
 778         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 779
 780         /* flow control */
 781         u32 pause_flags;
 782 };
 783
 784 /*
 785  * Maximum number of loops until we assume that a bit in the irq mask
 786  * is stuck. Overridable with module param.
 787  */
 788 static int max_interrupt_work = 5;
 789
 790 /*
 791  * Optimization can be either throuput mode or cpu mode
 792  *
 793  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 794  * CPU Mode: Interrupts are controlled by a timer.
 795  */
 796 enum {
 797         NV_OPTIMIZATION_MODE_THROUGHPUT,
 798         NV_OPTIMIZATION_MODE_CPU
 799 };
 800 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 801
 802 /*
 803  * Poll interval for timer irq
 804  *
 805  * This interval determines how frequent an interrupt is generated.
 806  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 807  * Min = 0, and Max = 65535
 808  */
 809 static int poll_interval = -1;
 810
 811 /*
 812  * MSI interrupts
 813  */
 814 enum {
 815         NV_MSI_INT_DISABLED,
 816         NV_MSI_INT_ENABLED
 817 };
 818 static int msi = NV_MSI_INT_ENABLED;
 819
 820 /*
 821  * MSIX interrupts
 822  */
 823 enum {
 824         NV_MSIX_INT_DISABLED,
 825         NV_MSIX_INT_ENABLED
 826 };
 827 static int msix = NV_MSIX_INT_ENABLED;
 828
 829 /*
 830  * DMA 64bit
 831  */
 832 enum {
 833         NV_DMA_64BIT_DISABLED,
 834         NV_DMA_64BIT_ENABLED
 835 };
 836 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 837
 838 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 839 {
 840         return netdev_priv(dev);
 841 }
 842
 843 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 844 {
 845         return ((struct fe_priv *)netdev_priv(dev))->base;
 846 }
 847
 848 static inline void pci_push(u8 __iomem *base)
 849 {
 850         /* force out pending posted writes */
 851         readl(base);
 852 }
 853
 854 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 855 {
 856         return le32_to_cpu(prd->flaglen)
 857                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 858 }
 859
 860 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 861 {
 862         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 863 }
 864
 865 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 866                                 int delay, int delaymax, const char *msg)
 867 {
 868         u8 __iomem *base = get_hwbase(dev);
 869
 870         pci_push(base);
 871         do {
 872                 udelay(delay);
 873                 delaymax -= delay;
 874                 if (delaymax < 0) {
 875                         if (msg)
 876                                 printk(msg);
 877                         return 1;
 878                 }
 879         } while ((readl(base + offset) & mask) != target);
 880         return 0;
 881 }
 882
 883 #define NV_SETUP_RX_RING 0x01
 884 #define NV_SETUP_TX_RING 0x02
 885
 886 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 887 {
 888         struct fe_priv *np = get_nvpriv(dev);
 889         u8 __iomem *base = get_hwbase(dev);
 890
 891         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 892                 if (rxtx_flags & NV_SETUP_RX_RING) {
 893                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 894                 }
 895                 if (rxtx_flags & NV_SETUP_TX_RING) {
 896                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 897                 }
 898         } else {
 899                 if (rxtx_flags & NV_SETUP_RX_RING) {
 900                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 901                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 902                 }
 903                 if (rxtx_flags & NV_SETUP_TX_RING) {
 904                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 905                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 906                 }
 907         }
 908 }
 909
 910 static void free_rings(struct net_device *dev)
 911 {
 912         struct fe_priv *np = get_nvpriv(dev);
 913
 914         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 915                 if (np->rx_ring.orig)
 916                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 917                                             np->rx_ring.orig, np->ring_addr);
 918         } else {
 919                 if (np->rx_ring.ex)
 920                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 921                                             np->rx_ring.ex, np->ring_addr);
 922         }
 923         if (np->rx_skbuff)
 924                 kfree(np->rx_skbuff);
 925         if (np->rx_dma)
 926                 kfree(np->rx_dma);
 927         if (np->tx_skbuff)
 928                 kfree(np->tx_skbuff);
 929         if (np->tx_dma)
 930                 kfree(np->tx_dma);
 931         if (np->tx_dma_len)
 932                 kfree(np->tx_dma_len);
 933 }
 934
 935 static int using_multi_irqs(struct net_device *dev)
 936 {
 937         struct fe_priv *np = get_nvpriv(dev);
 938
 939         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 940             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 941              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 942                 return 0;
 943         else
 944                 return 1;
 945 }
 946
 947 static void nv_enable_irq(struct net_device *dev)
 948 {
 949         struct fe_priv *np = get_nvpriv(dev);
 950
 951         if (!using_multi_irqs(dev)) {
 952                 if (np->msi_flags & NV_MSI_X_ENABLED)
 953                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 954                 else
 955                         enable_irq(dev->irq);
 956         } else {
 957                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 958                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 959                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 960         }
 961 }
 962
 963 static void nv_disable_irq(struct net_device *dev)
 964 {
 965         struct fe_priv *np = get_nvpriv(dev);
 966
 967         if (!using_multi_irqs(dev)) {
 968                 if (np->msi_flags & NV_MSI_X_ENABLED)
 969                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 970                 else
 971                         disable_irq(dev->irq);
 972         } else {
 973                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 974                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 975                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 976         }
 977 }
 978
 979 /* In MSIX mode, a write to irqmask behaves as XOR */
 980 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 981 {
 982         u8 __iomem *base = get_hwbase(dev);
 983
 984         writel(mask, base + NvRegIrqMask);
 985 }
 986
 987 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 988 {
 989         struct fe_priv *np = get_nvpriv(dev);
 990         u8 __iomem *base = get_hwbase(dev);
 991
 992         if (np->msi_flags & NV_MSI_X_ENABLED) {
 993                 writel(mask, base + NvRegIrqMask);
 994         } else {
 995                 if (np->msi_flags & NV_MSI_ENABLED)
 996                         writel(0, base + NvRegMSIIrqMask);
 997                 writel(0, base + NvRegIrqMask);
 998         }
 999 }
1000
1001 #define MII_READ        (-1)
1002 /* mii_rw: read/write a register on the PHY.
1003  *
1004  * Caller must guarantee serialization
1005  */
1006 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1007 {
1008         u8 __iomem *base = get_hwbase(dev);
1009         u32 reg;
1010         int retval;
1011
1012         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1013
1014         reg = readl(base + NvRegMIIControl);
1015         if (reg & NVREG_MIICTL_INUSE) {
1016                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1017                 udelay(NV_MIIBUSY_DELAY);
1018         }
1019
1020         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1021         if (value != MII_READ) {
1022                 writel(value, base + NvRegMIIData);
1023                 reg |= NVREG_MIICTL_WRITE;
1024         }
1025         writel(reg, base + NvRegMIIControl);
1026
1027         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1028                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1029                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1030                                 dev->name, miireg, addr);
1031                 retval = -1;
1032         } else if (value != MII_READ) {
1033                 /* it was a write operation - fewer failures are detectable */
1034                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1035                                 dev->name, value, miireg, addr);
1036                 retval = 0;
1037         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1038                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1039                                 dev->name, miireg, addr);
1040                 retval = -1;
1041         } else {
1042                 retval = readl(base + NvRegMIIData);
1043                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1044                                 dev->name, miireg, addr, retval);
1045         }
1046
1047         return retval;
1048 }
1049
1050 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1051 {
1052         struct fe_priv *np = netdev_priv(dev);
1053         u32 miicontrol;
1054         unsigned int tries = 0;
1055
1056         miicontrol = BMCR_RESET | bmcr_setup;
1057         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1058                 return -1;
1059         }
1060
1061         /* wait for 500ms */
1062         msleep(500);
1063
1064         /* must wait till reset is deasserted */
1065         while (miicontrol & BMCR_RESET) {
1066                 msleep(10);
1067                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1068                 /* FIXME: 100 tries seem excessive */
1069                 if (tries++ > 100)
1070                         return -1;
1071         }
1072         return 0;
1073 }
1074
1075 static int phy_init(struct net_device *dev)
1076 {
1077         struct fe_priv *np = get_nvpriv(dev);
1078         u8 __iomem *base = get_hwbase(dev);
1079         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1080
1081         /* phy errata for E3016 phy */
1082         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1083                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1084                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1085                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1086                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1087                         return PHY_ERROR;
1088                 }
1089         }
1090
1091         /* set advertise register */
1092         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1093         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1094         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1095                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1096                 return PHY_ERROR;
1097         }
1098
1099         /* get phy interface type */
1100         phyinterface = readl(base + NvRegPhyInterface);
1101
1102         /* see if gigabit phy */
1103         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1104         if (mii_status & PHY_GIGABIT) {
1105                 np->gigabit = PHY_GIGABIT;
1106                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1107                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1108                 if (phyinterface & PHY_RGMII)
1109                         mii_control_1000 |= ADVERTISE_1000FULL;
1110                 else
1111                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1112
1113                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1114                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1115                         return PHY_ERROR;
1116                 }
1117         }
1118         else
1119                 np->gigabit = 0;
1120
1121         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1122         mii_control |= BMCR_ANENABLE;
1123
1124         /* reset the phy
1125          * (certain phys need bmcr to be setup with reset)
1126          */
1127         if (phy_reset(dev, mii_control)) {
1128                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1129                 return PHY_ERROR;
1130         }
1131
1132         /* phy vendor specific configuration */
1133         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1134                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1135                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1136                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1137                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1138                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1139                         return PHY_ERROR;
1140                 }
1141                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1142                 phy_reserved |= PHY_INIT5;
1143                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1144                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145                         return PHY_ERROR;
1146                 }
1147         }
1148         if (np->phy_oui == PHY_OUI_CICADA) {
1149                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1150                 phy_reserved |= PHY_INIT6;
1151                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1152                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1153                         return PHY_ERROR;
1154                 }
1155         }
1156         /* some phys clear out pause advertisment on reset, set it back */
1157         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1158
1159         /* restart auto negotiation */
1160         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1161         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1162         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1163                 return PHY_ERROR;
1164         }
1165
1166         return 0;
1167 }
1168
1169 static void nv_start_rx(struct net_device *dev)
1170 {
1171         struct fe_priv *np = netdev_priv(dev);
1172         u8 __iomem *base = get_hwbase(dev);
1173
1174         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1175         /* Already running? Stop it. */
1176         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1177                 writel(0, base + NvRegReceiverControl);
1178                 pci_push(base);
1179         }
1180         writel(np->linkspeed, base + NvRegLinkSpeed);
1181         pci_push(base);
1182         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1183         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1184                                 dev->name, np->duplex, np->linkspeed);
1185         pci_push(base);
1186 }
1187
1188 static void nv_stop_rx(struct net_device *dev)
1189 {
1190         u8 __iomem *base = get_hwbase(dev);
1191
1192         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1193         writel(0, base + NvRegReceiverControl);
1194         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1195                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1196                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1197
1198         udelay(NV_RXSTOP_DELAY2);
1199         writel(0, base + NvRegLinkSpeed);
1200 }
1201
1202 static void nv_start_tx(struct net_device *dev)
1203 {
1204         u8 __iomem *base = get_hwbase(dev);
1205
1206         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1207         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1208         pci_push(base);
1209 }
1210
1211 static void nv_stop_tx(struct net_device *dev)
1212 {
1213         u8 __iomem *base = get_hwbase(dev);
1214
1215         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1216         writel(0, base + NvRegTransmitterControl);
1217         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1218                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1219                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1220
1221         udelay(NV_TXSTOP_DELAY2);
1222         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1223 }
1224
1225 static void nv_txrx_reset(struct net_device *dev)
1226 {
1227         struct fe_priv *np = netdev_priv(dev);
1228         u8 __iomem *base = get_hwbase(dev);
1229
1230         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1231         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1232         pci_push(base);
1233         udelay(NV_TXRX_RESET_DELAY);
1234         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1235         pci_push(base);
1236 }
1237
1238 static void nv_mac_reset(struct net_device *dev)
1239 {
1240         struct fe_priv *np = netdev_priv(dev);
1241         u8 __iomem *base = get_hwbase(dev);
1242
1243         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1244         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1245         pci_push(base);
1246         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1247         pci_push(base);
1248         udelay(NV_MAC_RESET_DELAY);
1249         writel(0, base + NvRegMacReset);
1250         pci_push(base);
1251         udelay(NV_MAC_RESET_DELAY);
1252         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1253         pci_push(base);
1254 }
1255
1256 /*
1257  * nv_get_stats: dev->get_stats function
1258  * Get latest stats value from the nic.
1259  * Called with read_lock(&dev_base_lock) held for read -
1260  * only synchronized against unregister_netdevice.
1261  */
1262 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1263 {
1264         struct fe_priv *np = netdev_priv(dev);
1265
1266         /* It seems that the nic always generates interrupts and doesn't
1267          * accumulate errors internally. Thus the current values in np->stats
1268          * are already up to date.
1269          */
1270         return &np->stats;
1271 }
1272
1273 /*
1274  * nv_alloc_rx: fill rx ring entries.
1275  * Return 1 if the allocations for the skbs failed and the
1276  * rx engine is without Available descriptors
1277  */
1278 static int nv_alloc_rx(struct net_device *dev)
1279 {
1280         struct fe_priv *np = netdev_priv(dev);
1281         unsigned int refill_rx = np->refill_rx;
1282         int nr;
1283
1284         while (np->cur_rx != refill_rx) {
1285                 struct sk_buff *skb;
1286
1287                 nr = refill_rx % np->rx_ring_size;
1288                 if (np->rx_skbuff[nr] == NULL) {
1289
1290                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1291                         if (!skb)
1292                                 break;
1293
1294                         skb->dev = dev;
1295                         np->rx_skbuff[nr] = skb;
1296                 } else {
1297                         skb = np->rx_skbuff[nr];
1298                 }
1299                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1300                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1301                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1302                         np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1303                         wmb();
1304                         np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1305                 } else {
1306                         np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1307                         np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1308                         wmb();
1309                         np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1310                 }
1311                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1312                                         dev->name, refill_rx);
1313                 refill_rx++;
1314         }
1315         np->refill_rx = refill_rx;
1316         if (np->cur_rx - refill_rx == np->rx_ring_size)
1317                 return 1;
1318         return 0;
1319 }
1320
1321 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1322 #ifdef CONFIG_FORCEDETH_NAPI
1323 static void nv_do_rx_refill(unsigned long data)
1324 {
1325         struct net_device *dev = (struct net_device *) data;
1326
1327         /* Just reschedule NAPI rx processing */
1328         netif_rx_schedule(dev);
1329 }
1330 #else
1331 static void nv_do_rx_refill(unsigned long data)
1332 {
1333         struct net_device *dev = (struct net_device *) data;
1334         struct fe_priv *np = netdev_priv(dev);
1335
1336         if (!using_multi_irqs(dev)) {
1337                 if (np->msi_flags & NV_MSI_X_ENABLED)
1338                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1339                 else
1340                         disable_irq(dev->irq);
1341         } else {
1342                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1343         }
1344         if (nv_alloc_rx(dev)) {
1345                 spin_lock_irq(&np->lock);
1346                 if (!np->in_shutdown)
1347                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1348                 spin_unlock_irq(&np->lock);
1349         }
1350         if (!using_multi_irqs(dev)) {
1351                 if (np->msi_flags & NV_MSI_X_ENABLED)
1352                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1353                 else
1354                         enable_irq(dev->irq);
1355         } else {
1356                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1357         }
1358 }
1359 #endif
1360
1361 static void nv_init_rx(struct net_device *dev)
1362 {
1363         struct fe_priv *np = netdev_priv(dev);
1364         int i;
1365
1366         np->cur_rx = np->rx_ring_size;
1367         np->refill_rx = 0;
1368         for (i = 0; i < np->rx_ring_size; i++)
1369                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1370                         np->rx_ring.orig[i].flaglen = 0;
1371                 else
1372                         np->rx_ring.ex[i].flaglen = 0;
1373 }
1374
1375 static void nv_init_tx(struct net_device *dev)
1376 {
1377         struct fe_priv *np = netdev_priv(dev);
1378         int i;
1379
1380         np->next_tx = np->nic_tx = 0;
1381         for (i = 0; i < np->tx_ring_size; i++) {
1382                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1383                         np->tx_ring.orig[i].flaglen = 0;
1384                 else
1385                         np->tx_ring.ex[i].flaglen = 0;
1386                 np->tx_skbuff[i] = NULL;
1387                 np->tx_dma[i] = 0;
1388         }
1389 }
1390
1391 static int nv_init_ring(struct net_device *dev)
1392 {
1393         nv_init_tx(dev);
1394         nv_init_rx(dev);
1395         return nv_alloc_rx(dev);
1396 }
1397
1398 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1399 {
1400         struct fe_priv *np = netdev_priv(dev);
1401
1402         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1403                 dev->name, skbnr);
1404
1405         if (np->tx_dma[skbnr]) {
1406                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1407                                np->tx_dma_len[skbnr],
1408                                PCI_DMA_TODEVICE);
1409                 np->tx_dma[skbnr] = 0;
1410         }
1411
1412         if (np->tx_skbuff[skbnr]) {
1413                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1414                 np->tx_skbuff[skbnr] = NULL;
1415                 return 1;
1416         } else {
1417                 return 0;
1418         }
1419 }
1420
1421 static void nv_drain_tx(struct net_device *dev)
1422 {
1423         struct fe_priv *np = netdev_priv(dev);
1424         unsigned int i;
1425
1426         for (i = 0; i < np->tx_ring_size; i++) {
1427                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1428                         np->tx_ring.orig[i].flaglen = 0;
1429                 else
1430                         np->tx_ring.ex[i].flaglen = 0;
1431                 if (nv_release_txskb(dev, i))
1432                         np->stats.tx_dropped++;
1433         }
1434 }
1435
1436 static void nv_drain_rx(struct net_device *dev)
1437 {
1438         struct fe_priv *np = netdev_priv(dev);
1439         int i;
1440         for (i = 0; i < np->rx_ring_size; i++) {
1441                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1442                         np->rx_ring.orig[i].flaglen = 0;
1443                 else
1444                         np->rx_ring.ex[i].flaglen = 0;
1445                 wmb();
1446                 if (np->rx_skbuff[i]) {
1447                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1448                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1449                                                 PCI_DMA_FROMDEVICE);
1450                         dev_kfree_skb(np->rx_skbuff[i]);
1451                         np->rx_skbuff[i] = NULL;
1452                 }
1453         }
1454 }
1455
1456 static void drain_ring(struct net_device *dev)
1457 {
1458         nv_drain_tx(dev);
1459         nv_drain_rx(dev);
1460 }
1461
1462 /*
1463  * nv_start_xmit: dev->hard_start_xmit function
1464  * Called with netif_tx_lock held.
1465  */
1466 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1467 {
1468         struct fe_priv *np = netdev_priv(dev);
1469         u32 tx_flags = 0;
1470         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1471         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1472         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1473         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1474         unsigned int i;
1475         u32 offset = 0;
1476         u32 bcnt;
1477         u32 size = skb->len-skb->data_len;
1478         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1479         u32 tx_flags_vlan = 0;
1480
1481         /* add fragments to entries count */
1482         for (i = 0; i < fragments; i++) {
1483                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1484                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1485         }
1486
1487         spin_lock_irq(&np->lock);
1488
1489         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1490                 spin_unlock_irq(&np->lock);
1491                 netif_stop_queue(dev);
1492                 return NETDEV_TX_BUSY;
1493         }
1494
1495         /* setup the header buffer */
1496         do {
1497                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1498                 nr = (nr + 1) % np->tx_ring_size;
1499
1500                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1501                                                 PCI_DMA_TODEVICE);
1502                 np->tx_dma_len[nr] = bcnt;
1503
1504                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1505                         np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1506                         np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1507                 } else {
1508                         np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1509                         np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1510                         np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1511                 }
1512                 tx_flags = np->tx_flags;
1513                 offset += bcnt;
1514                 size -= bcnt;
1515         } while (size);
1516
1517         /* setup the fragments */
1518         for (i = 0; i < fragments; i++) {
1519                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1520                 u32 size = frag->size;
1521                 offset = 0;
1522
1523                 do {
1524                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1525                         nr = (nr + 1) % np->tx_ring_size;
1526
1527                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1528                                                       PCI_DMA_TODEVICE);
1529                         np->tx_dma_len[nr] = bcnt;
1530
1531                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1532                                 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1533                                 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1534                         } else {
1535                                 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1536                                 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1537                                 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1538                         }
1539                         offset += bcnt;
1540                         size -= bcnt;
1541                 } while (size);
1542         }
1543
1544         /* set last fragment flag  */
1545         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1546                 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1547         } else {
1548                 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1549         }
1550
1551         np->tx_skbuff[nr] = skb;
1552
1553 #ifdef NETIF_F_TSO
1554         if (skb_is_gso(skb))
1555                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1556         else
1557 #endif
1558         tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1559                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1560
1561         /* vlan tag */
1562         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1563                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1564         }
1565
1566         /* set tx flags */
1567         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1568                 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1569         } else {
1570                 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1571                 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1572         }
1573
1574         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1575                 dev->name, np->next_tx, entries, tx_flags_extra);
1576         {
1577                 int j;
1578                 for (j=0; j<64; j++) {
1579                         if ((j%16) == 0)
1580                                 dprintk("\n%03x:", j);
1581                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1582                 }
1583                 dprintk("\n");
1584         }
1585
1586         np->next_tx += entries;
1587
1588         dev->trans_start = jiffies;
1589         spin_unlock_irq(&np->lock);
1590         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1591         pci_push(get_hwbase(dev));
1592         return NETDEV_TX_OK;
1593 }
1594
1595 /*
1596  * nv_tx_done: check for completed packets, release the skbs.
1597  *
1598  * Caller must own np->lock.
1599  */
1600 static void nv_tx_done(struct net_device *dev)
1601 {
1602         struct fe_priv *np = netdev_priv(dev);
1603         u32 flags;
1604         unsigned int i;
1605         struct sk_buff *skb;
1606
1607         while (np->nic_tx != np->next_tx) {
1608                 i = np->nic_tx % np->tx_ring_size;
1609
1610                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1611                         flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1612                 else
1613                         flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1614
1615                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1616                                         dev->name, np->nic_tx, flags);
1617                 if (flags & NV_TX_VALID)
1618                         break;
1619                 if (np->desc_ver == DESC_VER_1) {
1620                         if (flags & NV_TX_LASTPACKET) {
1621                                 skb = np->tx_skbuff[i];
1622                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1623                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1624                                         if (flags & NV_TX_UNDERFLOW)
1625                                                 np->stats.tx_fifo_errors++;
1626                                         if (flags & NV_TX_CARRIERLOST)
1627                                                 np->stats.tx_carrier_errors++;
1628                                         np->stats.tx_errors++;
1629                                 } else {
1630                                         np->stats.tx_packets++;
1631                                         np->stats.tx_bytes += skb->len;
1632                                 }
1633                         }
1634                 } else {
1635                         if (flags & NV_TX2_LASTPACKET) {
1636                                 skb = np->tx_skbuff[i];
1637                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1638                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1639                                         if (flags & NV_TX2_UNDERFLOW)
1640                                                 np->stats.tx_fifo_errors++;
1641                                         if (flags & NV_TX2_CARRIERLOST)
1642                                                 np->stats.tx_carrier_errors++;
1643                                         np->stats.tx_errors++;
1644                                 } else {
1645                                         np->stats.tx_packets++;
1646                                         np->stats.tx_bytes += skb->len;
1647                                 }
1648                         }
1649                 }
1650                 nv_release_txskb(dev, i);
1651                 np->nic_tx++;
1652         }
1653         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1654                 netif_wake_queue(dev);
1655 }
1656
1657 /*
1658  * nv_tx_timeout: dev->tx_timeout function
1659  * Called with netif_tx_lock held.
1660  */
1661 static void nv_tx_timeout(struct net_device *dev)
1662 {
1663         struct fe_priv *np = netdev_priv(dev);
1664         u8 __iomem *base = get_hwbase(dev);
1665         u32 status;
1666
1667         if (np->msi_flags & NV_MSI_X_ENABLED)
1668                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1669         else
1670                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1671
1672         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1673
1674         {
1675                 int i;
1676
1677                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1678                                 dev->name, (unsigned long)np->ring_addr,
1679                                 np->next_tx, np->nic_tx);
1680                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1681                 for (i=0;i<=np->register_size;i+= 32) {
1682                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1683                                         i,
1684                                         readl(base + i + 0), readl(base + i + 4),
1685                                         readl(base + i + 8), readl(base + i + 12),
1686                                         readl(base + i + 16), readl(base + i + 20),
1687                                         readl(base + i + 24), readl(base + i + 28));
1688                 }
1689                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1690                 for (i=0;i<np->tx_ring_size;i+= 4) {
1691                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1692                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1693                                        i,
1694                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1695                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1696                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1697                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1698                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1699                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1700                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1701                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1702                         } else {
1703                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1704                                        i,
1705                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1706                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1707                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1708                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1709                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1710                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1711                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1712                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1713                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1714                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1715                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1716                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1717                         }
1718                 }
1719         }
1720
1721         spin_lock_irq(&np->lock);
1722
1723         /* 1) stop tx engine */
1724         nv_stop_tx(dev);
1725
1726         /* 2) check that the packets were not sent already: */
1727         nv_tx_done(dev);
1728
1729         /* 3) if there are dead entries: clear everything */
1730         if (np->next_tx != np->nic_tx) {
1731                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1732                 nv_drain_tx(dev);
1733                 np->next_tx = np->nic_tx = 0;
1734                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1735                 netif_wake_queue(dev);
1736         }
1737
1738         /* 4) restart tx engine */
1739         nv_start_tx(dev);
1740         spin_unlock_irq(&np->lock);
1741 }
1742
1743 /*
1744  * Called when the nic notices a mismatch between the actual data len on the
1745  * wire and the len indicated in the 802 header
1746  */
1747 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1748 {
1749         int hdrlen;     /* length of the 802 header */
1750         int protolen;   /* length as stored in the proto field */
1751
1752         /* 1) calculate len according to header */
1753         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1754                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1755                 hdrlen = VLAN_HLEN;
1756         } else {
1757                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1758                 hdrlen = ETH_HLEN;
1759         }
1760         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1761                                 dev->name, datalen, protolen, hdrlen);
1762         if (protolen > ETH_DATA_LEN)
1763                 return datalen; /* Value in proto field not a len, no checks possible */
1764
1765         protolen += hdrlen;
1766         /* consistency checks: */
1767         if (datalen > ETH_ZLEN) {
1768                 if (datalen >= protolen) {
1769                         /* more data on wire than in 802 header, trim of
1770                          * additional data.
1771                          */
1772                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1773                                         dev->name, protolen);
1774                         return protolen;
1775                 } else {
1776                         /* less data on wire than mentioned in header.
1777                          * Discard the packet.
1778                          */
1779                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1780                                         dev->name);
1781                         return -1;
1782                 }
1783         } else {
1784                 /* short packet. Accept only if 802 values are also short */
1785                 if (protolen > ETH_ZLEN) {
1786                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1787                                         dev->name);
1788                         return -1;
1789                 }
1790                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1791                                 dev->name, datalen);
1792                 return datalen;
1793         }
1794 }
1795
1796 static int nv_rx_process(struct net_device *dev, int limit)
1797 {
1798         struct fe_priv *np = netdev_priv(dev);
1799         u32 flags;
1800         u32 vlanflags = 0;
1801         int count;
1802
1803         for (count = 0; count < limit; ++count) {
1804                 struct sk_buff *skb;
1805                 int len;
1806                 int i;
1807                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1808                         break;  /* we scanned the whole ring - do not continue */
1809
1810                 i = np->cur_rx % np->rx_ring_size;
1811                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1812                         flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1813                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1814                 } else {
1815                         flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1816                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1817                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1818                 }
1819
1820                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1821                                         dev->name, np->cur_rx, flags);
1822
1823                 if (flags & NV_RX_AVAIL)
1824                         break;  /* still owned by hardware, */
1825
1826                 /*
1827                  * the packet is for us - immediately tear down the pci mapping.
1828                  * TODO: check if a prefetch of the first cacheline improves
1829                  * the performance.
1830                  */
1831                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1832                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1833                                 PCI_DMA_FROMDEVICE);
1834
1835                 {
1836                         int j;
1837                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1838                         for (j=0; j<64; j++) {
1839                                 if ((j%16) == 0)
1840                                         dprintk("\n%03x:", j);
1841                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1842                         }
1843                         dprintk("\n");
1844                 }
1845                 /* look at what we actually got: */
1846                 if (np->desc_ver == DESC_VER_1) {
1847                         if (!(flags & NV_RX_DESCRIPTORVALID))
1848                                 goto next_pkt;
1849
1850                         if (flags & NV_RX_ERROR) {
1851                                 if (flags & NV_RX_MISSEDFRAME) {
1852                                         np->stats.rx_missed_errors++;
1853                                         np->stats.rx_errors++;
1854                                         goto next_pkt;
1855                                 }
1856                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1857                                         np->stats.rx_errors++;
1858                                         goto next_pkt;
1859                                 }
1860                                 if (flags & NV_RX_CRCERR) {
1861                                         np->stats.rx_crc_errors++;
1862                                         np->stats.rx_errors++;
1863                                         goto next_pkt;
1864                                 }
1865                                 if (flags & NV_RX_OVERFLOW) {
1866                                         np->stats.rx_over_errors++;
1867                                         np->stats.rx_errors++;
1868                                         goto next_pkt;
1869                                 }
1870                                 if (flags & NV_RX_ERROR4) {
1871                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1872                                         if (len < 0) {
1873                                                 np->stats.rx_errors++;
1874                                                 goto next_pkt;
1875                                         }
1876                                 }
1877                                 /* framing errors are soft errors. */
1878                                 if (flags & NV_RX_FRAMINGERR) {
1879                                         if (flags & NV_RX_SUBSTRACT1) {
1880                                                 len--;
1881                                         }
1882                                 }
1883                         }
1884                 } else {
1885                         if (!(flags & NV_RX2_DESCRIPTORVALID))
1886                                 goto next_pkt;
1887
1888                         if (flags & NV_RX2_ERROR) {
1889                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1890                                         np->stats.rx_errors++;
1891                                         goto next_pkt;
1892                                 }
1893                                 if (flags & NV_RX2_CRCERR) {
1894                                         np->stats.rx_crc_errors++;
1895                                         np->stats.rx_errors++;
1896                                         goto next_pkt;
1897                                 }
1898                                 if (flags & NV_RX2_OVERFLOW) {
1899                                         np->stats.rx_over_errors++;
1900                                         np->stats.rx_errors++;
1901                                         goto next_pkt;
1902                                 }
1903                                 if (flags & NV_RX2_ERROR4) {
1904                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1905                                         if (len < 0) {
1906                                                 np->stats.rx_errors++;
1907                                                 goto next_pkt;
1908                                         }
1909                                 }
1910                                 /* framing errors are soft errors */
1911                                 if (flags & NV_RX2_FRAMINGERR) {
1912                                         if (flags & NV_RX2_SUBSTRACT1) {
1913                                                 len--;
1914                                         }
1915                                 }
1916                         }
1917                         if (np->rx_csum) {
1918                                 flags &= NV_RX2_CHECKSUMMASK;
1919                                 if (flags == NV_RX2_CHECKSUMOK1 ||
1920                                     flags == NV_RX2_CHECKSUMOK2 ||
1921                                     flags == NV_RX2_CHECKSUMOK3) {
1922                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1923                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1924                                 } else {
1925                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1926                                 }
1927                         }
1928                 }
1929                 /* got a valid packet - forward it to the network core */
1930                 skb = np->rx_skbuff[i];
1931                 np->rx_skbuff[i] = NULL;
1932
1933                 skb_put(skb, len);
1934                 skb->protocol = eth_type_trans(skb, dev);
1935                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1936                                         dev->name, np->cur_rx, len, skb->protocol);
1937 #ifdef CONFIG_FORCEDETH_NAPI
1938                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1939                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
1940                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
1941                 else
1942                         netif_receive_skb(skb);
1943 #else
1944                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1945                         vlan_hwaccel_rx(skb, np->vlangrp,
1946                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
1947                 else
1948                         netif_rx(skb);
1949 #endif
1950                 dev->last_rx = jiffies;
1951                 np->stats.rx_packets++;
1952                 np->stats.rx_bytes += len;
1953 next_pkt:
1954                 np->cur_rx++;
1955         }
1956
1957         return count;
1958 }
1959
1960 static void set_bufsize(struct net_device *dev)
1961 {
1962         struct fe_priv *np = netdev_priv(dev);
1963
1964         if (dev->mtu <= ETH_DATA_LEN)
1965                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1966         else
1967                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1968 }
1969
1970 /*
1971  * nv_change_mtu: dev->change_mtu function
1972  * Called with dev_base_lock held for read.
1973  */
1974 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1975 {
1976         struct fe_priv *np = netdev_priv(dev);
1977         int old_mtu;
1978
1979         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1980                 return -EINVAL;
1981
1982         old_mtu = dev->mtu;
1983         dev->mtu = new_mtu;
1984
1985         /* return early if the buffer sizes will not change */
1986         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1987                 return 0;
1988         if (old_mtu == new_mtu)
1989                 return 0;
1990
1991         /* synchronized against open : rtnl_lock() held by caller */
1992         if (netif_running(dev)) {
1993                 u8 __iomem *base = get_hwbase(dev);
1994                 /*
1995                  * It seems that the nic preloads valid ring entries into an
1996                  * internal buffer. The procedure for flushing everything is
1997                  * guessed, there is probably a simpler approach.
1998                  * Changing the MTU is a rare event, it shouldn't matter.
1999                  */
2000                 nv_disable_irq(dev);
2001                 netif_tx_lock_bh(dev);
2002                 spin_lock(&np->lock);
2003                 /* stop engines */
2004                 nv_stop_rx(dev);
2005                 nv_stop_tx(dev);
2006                 nv_txrx_reset(dev);
2007                 /* drain rx queue */
2008                 nv_drain_rx(dev);
2009                 nv_drain_tx(dev);
2010                 /* reinit driver view of the rx queue */
2011                 set_bufsize(dev);
2012                 if (nv_init_ring(dev)) {
2013                         if (!np->in_shutdown)
2014                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2015                 }
2016                 /* reinit nic view of the rx queue */
2017                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2018                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2019                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2020                         base + NvRegRingSizes);
2021                 pci_push(base);
2022                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2023                 pci_push(base);
2024
2025                 /* restart rx engine */
2026                 nv_start_rx(dev);
2027                 nv_start_tx(dev);
2028                 spin_unlock(&np->lock);
2029                 netif_tx_unlock_bh(dev);
2030                 nv_enable_irq(dev);
2031         }
2032         return 0;
2033 }
2034
2035 static void nv_copy_mac_to_hw(struct net_device *dev)
2036 {
2037         u8 __iomem *base = get_hwbase(dev);
2038         u32 mac[2];
2039
2040         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2041                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2042         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2043
2044         writel(mac[0], base + NvRegMacAddrA);
2045         writel(mac[1], base + NvRegMacAddrB);
2046 }
2047
2048 /*
2049  * nv_set_mac_address: dev->set_mac_address function
2050  * Called with rtnl_lock() held.
2051  */
2052 static int nv_set_mac_address(struct net_device *dev, void *addr)
2053 {
2054         struct fe_priv *np = netdev_priv(dev);
2055         struct sockaddr *macaddr = (struct sockaddr*)addr;
2056
2057         if (!is_valid_ether_addr(macaddr->sa_data))
2058                 return -EADDRNOTAVAIL;
2059
2060         /* synchronized against open : rtnl_lock() held by caller */
2061         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2062
2063         if (netif_running(dev)) {
2064                 netif_tx_lock_bh(dev);
2065                 spin_lock_irq(&np->lock);
2066
2067                 /* stop rx engine */
2068                 nv_stop_rx(dev);
2069
2070                 /* set mac address */
2071                 nv_copy_mac_to_hw(dev);
2072
2073                 /* restart rx engine */
2074                 nv_start_rx(dev);
2075                 spin_unlock_irq(&np->lock);
2076                 netif_tx_unlock_bh(dev);
2077         } else {
2078                 nv_copy_mac_to_hw(dev);
2079         }
2080         return 0;
2081 }
2082
2083 /*
2084  * nv_set_multicast: dev->set_multicast function
2085  * Called with netif_tx_lock held.
2086  */
2087 static void nv_set_multicast(struct net_device *dev)
2088 {
2089         struct fe_priv *np = netdev_priv(dev);
2090         u8 __iomem *base = get_hwbase(dev);
2091         u32 addr[2];
2092         u32 mask[2];
2093         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2094
2095         memset(addr, 0, sizeof(addr));
2096         memset(mask, 0, sizeof(mask));
2097
2098         if (dev->flags & IFF_PROMISC) {
2099                 pff |= NVREG_PFF_PROMISC;
2100         } else {
2101                 pff |= NVREG_PFF_MYADDR;
2102
2103                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2104                         u32 alwaysOff[2];
2105                         u32 alwaysOn[2];
2106
2107                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2108                         if (dev->flags & IFF_ALLMULTI) {
2109                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2110                         } else {
2111                                 struct dev_mc_list *walk;
2112
2113                                 walk = dev->mc_list;
2114                                 while (walk != NULL) {
2115                                         u32 a, b;
2116                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2117                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2118                                         alwaysOn[0] &= a;
2119                                         alwaysOff[0] &= ~a;
2120                                         alwaysOn[1] &= b;
2121                                         alwaysOff[1] &= ~b;
2122                                         walk = walk->next;
2123                                 }
2124                         }
2125                         addr[0] = alwaysOn[0];
2126                         addr[1] = alwaysOn[1];
2127                         mask[0] = alwaysOn[0] | alwaysOff[0];
2128                         mask[1] = alwaysOn[1] | alwaysOff[1];
2129                 }
2130         }
2131         addr[0] |= NVREG_MCASTADDRA_FORCE;
2132         pff |= NVREG_PFF_ALWAYS;
2133         spin_lock_irq(&np->lock);
2134         nv_stop_rx(dev);
2135         writel(addr[0], base + NvRegMulticastAddrA);
2136         writel(addr[1], base + NvRegMulticastAddrB);
2137         writel(mask[0], base + NvRegMulticastMaskA);
2138         writel(mask[1], base + NvRegMulticastMaskB);
2139         writel(pff, base + NvRegPacketFilterFlags);
2140         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2141                 dev->name);
2142         nv_start_rx(dev);
2143         spin_unlock_irq(&np->lock);
2144 }
2145
2146 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2147 {
2148         struct fe_priv *np = netdev_priv(dev);
2149         u8 __iomem *base = get_hwbase(dev);
2150
2151         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2152
2153         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2154                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2155                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2156                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2157                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2158                 } else {
2159                         writel(pff, base + NvRegPacketFilterFlags);
2160                 }
2161         }
2162         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2163                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2164                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2165                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2166                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2167                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2168                 } else {
2169                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2170                         writel(regmisc, base + NvRegMisc1);
2171                 }
2172         }
2173 }
2174
2175 /**
2176  * nv_update_linkspeed: Setup the MAC according to the link partner
2177  * @dev: Network device to be configured
2178  *
2179  * The function queries the PHY and checks if there is a link partner.
2180  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2181  * set to 10 MBit HD.
2182  *
2183  * The function returns 0 if there is no link partner and 1 if there is
2184  * a good link partner.
2185  */
2186 static int nv_update_linkspeed(struct net_device *dev)
2187 {
2188         struct fe_priv *np = netdev_priv(dev);
2189         u8 __iomem *base = get_hwbase(dev);
2190         int adv = 0;
2191         int lpa = 0;
2192         int adv_lpa, adv_pause, lpa_pause;
2193         int newls = np->linkspeed;
2194         int newdup = np->duplex;
2195         int mii_status;
2196         int retval = 0;
2197         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2198
2199         /* BMSR_LSTATUS is latched, read it twice:
2200          * we want the current value.
2201          */
2202         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2203         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2204
2205         if (!(mii_status & BMSR_LSTATUS)) {
2206                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2207                                 dev->name);
2208                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2209                 newdup = 0;
2210                 retval = 0;
2211                 goto set_speed;
2212         }
2213
2214         if (np->autoneg == 0) {
2215                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2216                                 dev->name, np->fixed_mode);
2217                 if (np->fixed_mode & LPA_100FULL) {
2218                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2219                         newdup = 1;
2220                 } else if (np->fixed_mode & LPA_100HALF) {
2221                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2222                         newdup = 0;
2223                 } else if (np->fixed_mode & LPA_10FULL) {
2224                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2225                         newdup = 1;
2226                 } else {
2227                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2228                         newdup = 0;
2229                 }
2230                 retval = 1;
2231                 goto set_speed;
2232         }
2233         /* check auto negotiation is complete */
2234         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2235                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2236                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2237                 newdup = 0;
2238                 retval = 0;
2239                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2240                 goto set_speed;
2241         }
2242
2243         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2244         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2245         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2246                                 dev->name, adv, lpa);
2247
2248         retval = 1;
2249         if (np->gigabit == PHY_GIGABIT) {
2250                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2251                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2252
2253                 if ((control_1000 & ADVERTISE_1000FULL) &&
2254                         (status_1000 & LPA_1000FULL)) {
2255                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2256                                 dev->name);
2257                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2258                         newdup = 1;
2259                         goto set_speed;
2260                 }
2261         }
2262
2263         /* FIXME: handle parallel detection properly */
2264         adv_lpa = lpa & adv;
2265         if (adv_lpa & LPA_100FULL) {
2266                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2267                 newdup = 1;
2268         } else if (adv_lpa & LPA_100HALF) {
2269                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2270                 newdup = 0;
2271         } else if (adv_lpa & LPA_10FULL) {
2272                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2273                 newdup = 1;
2274         } else if (adv_lpa & LPA_10HALF) {
2275                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2276                 newdup = 0;
2277         } else {
2278                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2279                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2280                 newdup = 0;
2281         }
2282
2283 set_speed:
2284         if (np->duplex == newdup && np->linkspeed == newls)
2285                 return retval;
2286
2287         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2288                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2289
2290         np->duplex = newdup;
2291         np->linkspeed = newls;
2292
2293         if (np->gigabit == PHY_GIGABIT) {
2294                 phyreg = readl(base + NvRegRandomSeed);
2295                 phyreg &= ~(0x3FF00);
2296                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2297                         phyreg |= NVREG_RNDSEED_FORCE3;
2298                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2299                         phyreg |= NVREG_RNDSEED_FORCE2;
2300                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2301                         phyreg |= NVREG_RNDSEED_FORCE;
2302                 writel(phyreg, base + NvRegRandomSeed);
2303         }
2304
2305         phyreg = readl(base + NvRegPhyInterface);
2306         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2307         if (np->duplex == 0)
2308                 phyreg |= PHY_HALF;
2309         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2310                 phyreg |= PHY_100;
2311         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2312                 phyreg |= PHY_1000;
2313         writel(phyreg, base + NvRegPhyInterface);
2314
2315         if (phyreg & PHY_RGMII) {
2316                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2317                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2318                 else
2319                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2320         } else {
2321                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2322         }
2323         writel(txreg, base + NvRegTxDeferral);
2324
2325         if (np->desc_ver == DESC_VER_1) {
2326                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2327         } else {
2328                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2329                         txreg = NVREG_TX_WM_DESC2_3_1000;
2330                 else
2331                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2332         }
2333         writel(txreg, base + NvRegTxWatermark);
2334
2335         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2336                 base + NvRegMisc1);
2337         pci_push(base);
2338         writel(np->linkspeed, base + NvRegLinkSpeed);
2339         pci_push(base);
2340
2341         pause_flags = 0;
2342         /* setup pause frame */
2343         if (np->duplex != 0) {
2344                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2345                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2346                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2347
2348                         switch (adv_pause) {
2349                         case ADVERTISE_PAUSE_CAP:
2350                                 if (lpa_pause & LPA_PAUSE_CAP) {
2351                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2352                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2353                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2354                                 }
2355                                 break;
2356                         case ADVERTISE_PAUSE_ASYM:
2357                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2358                                 {
2359                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2360                                 }
2361                                 break;
2362                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2363                                 if (lpa_pause & LPA_PAUSE_CAP)
2364                                 {
2365                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2366                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2367                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2368                                 }
2369                                 if (lpa_pause == LPA_PAUSE_ASYM)
2370                                 {
2371                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2372                                 }
2373                                 break;
2374                         }
2375                 } else {
2376                         pause_flags = np->pause_flags;
2377                 }
2378         }
2379         nv_update_pause(dev, pause_flags);
2380
2381         return retval;
2382 }
2383
2384 static void nv_linkchange(struct net_device *dev)
2385 {
2386         if (nv_update_linkspeed(dev)) {
2387                 if (!netif_carrier_ok(dev)) {
2388                         netif_carrier_on(dev);
2389                         printk(KERN_INFO "%s: link up.\n", dev->name);
2390                         nv_start_rx(dev);
2391                 }
2392         } else {
2393                 if (netif_carrier_ok(dev)) {
2394                         netif_carrier_off(dev);
2395                         printk(KERN_INFO "%s: link down.\n", dev->name);
2396                         nv_stop_rx(dev);
2397                 }
2398         }
2399 }
2400
2401 static void nv_link_irq(struct net_device *dev)
2402 {
2403         u8 __iomem *base = get_hwbase(dev);
2404         u32 miistat;
2405
2406         miistat = readl(base + NvRegMIIStatus);
2407         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2408         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2409
2410         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2411                 nv_linkchange(dev);
2412         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2413 }
2414
2415 static irqreturn_t nv_nic_irq(int foo, void *data)
2416 {
2417         struct net_device *dev = (struct net_device *) data;
2418         struct fe_priv *np = netdev_priv(dev);
2419         u8 __iomem *base = get_hwbase(dev);
2420         u32 events;
2421         int i;
2422
2423         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2424
2425         for (i=0; ; i++) {
2426                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2427                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2428                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2429                 } else {
2430                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2431                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2432                 }
2433                 pci_push(base);
2434                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2435                 if (!(events & np->irqmask))
2436                         break;
2437
2438                 spin_lock(&np->lock);
2439                 nv_tx_done(dev);
2440                 spin_unlock(&np->lock);
2441
2442                 if (events & NVREG_IRQ_LINK) {
2443                         spin_lock(&np->lock);
2444                         nv_link_irq(dev);
2445                         spin_unlock(&np->lock);
2446                 }
2447                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2448                         spin_lock(&np->lock);
2449                         nv_linkchange(dev);
2450                         spin_unlock(&np->lock);
2451                         np->link_timeout = jiffies + LINK_TIMEOUT;
2452                 }
2453                 if (events & (NVREG_IRQ_TX_ERR)) {
2454                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2455                                                 dev->name, events);
2456                 }
2457                 if (events & (NVREG_IRQ_UNKNOWN)) {
2458                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2459                                                 dev->name, events);
2460                 }
2461                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2462                         spin_lock(&np->lock);
2463                         /* disable interrupts on the nic */
2464                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2465                                 writel(0, base + NvRegIrqMask);
2466                         else
2467                                 writel(np->irqmask, base + NvRegIrqMask);
2468                         pci_push(base);
2469
2470                         if (!np->in_shutdown) {
2471                                 np->nic_poll_irq = np->irqmask;
2472                                 np->recover_error = 1;
2473                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2474                         }
2475                         spin_unlock(&np->lock);
2476                         break;
2477                 }
2478 #ifdef CONFIG_FORCEDETH_NAPI
2479                 if (events & NVREG_IRQ_RX_ALL) {
2480                         netif_rx_schedule(dev);
2481
2482                         /* Disable furthur receive irq's */
2483                         spin_lock(&np->lock);
2484                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2485
2486                         if (np->msi_flags & NV_MSI_X_ENABLED)
2487                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2488                         else
2489                                 writel(np->irqmask, base + NvRegIrqMask);
2490                         spin_unlock(&np->lock);
2491                 }
2492 #else
2493                 nv_rx_process(dev, dev->weight);
2494                 if (nv_alloc_rx(dev)) {
2495                         spin_lock(&np->lock);
2496                         if (!np->in_shutdown)
2497                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2498                         spin_unlock(&np->lock);
2499                 }
2500 #endif
2501                 if (i > max_interrupt_work) {
2502                         spin_lock(&np->lock);
2503                         /* disable interrupts on the nic */
2504                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2505                                 writel(0, base + NvRegIrqMask);
2506                         else
2507                                 writel(np->irqmask, base + NvRegIrqMask);
2508                         pci_push(base);
2509
2510                         if (!np->in_shutdown) {
2511                                 np->nic_poll_irq = np->irqmask;
2512                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2513                         }
2514                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2515                         spin_unlock(&np->lock);
2516                         break;
2517                 }
2518
2519         }
2520         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2521
2522         return IRQ_RETVAL(i);
2523 }
2524
2525 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2526 {
2527         struct net_device *dev = (struct net_device *) data;
2528         struct fe_priv *np = netdev_priv(dev);
2529         u8 __iomem *base = get_hwbase(dev);
2530         u32 events;
2531         int i;
2532         unsigned long flags;
2533
2534         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2535
2536         for (i=0; ; i++) {
2537                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2538                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2539                 pci_push(base);
2540                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2541                 if (!(events & np->irqmask))
2542                         break;
2543
2544                 spin_lock_irqsave(&np->lock, flags);
2545                 nv_tx_done(dev);
2546                 spin_unlock_irqrestore(&np->lock, flags);
2547
2548                 if (events & (NVREG_IRQ_TX_ERR)) {
2549                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2550                                                 dev->name, events);
2551                 }
2552                 if (i > max_interrupt_work) {
2553                         spin_lock_irqsave(&np->lock, flags);
2554                         /* disable interrupts on the nic */
2555                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2556                         pci_push(base);
2557
2558                         if (!np->in_shutdown) {
2559                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2560                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2561                         }
2562                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2563                         spin_unlock_irqrestore(&np->lock, flags);
2564                         break;
2565                 }
2566
2567         }
2568         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2569
2570         return IRQ_RETVAL(i);
2571 }
2572
2573 #ifdef CONFIG_FORCEDETH_NAPI
2574 static int nv_napi_poll(struct net_device *dev, int *budget)
2575 {
2576         int pkts, limit = min(*budget, dev->quota);
2577         struct fe_priv *np = netdev_priv(dev);
2578         u8 __iomem *base = get_hwbase(dev);
2579         unsigned long flags;
2580
2581         pkts = nv_rx_process(dev, limit);
2582
2583         if (nv_alloc_rx(dev)) {
2584                 spin_lock_irqsave(&np->lock, flags);
2585                 if (!np->in_shutdown)
2586                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2587                 spin_unlock_irqrestore(&np->lock, flags);
2588         }
2589
2590         if (pkts < limit) {
2591                 /* all done, no more packets present */
2592                 netif_rx_complete(dev);
2593
2594                 /* re-enable receive interrupts */
2595                 spin_lock_irqsave(&np->lock, flags);
2596
2597                 np->irqmask |= NVREG_IRQ_RX_ALL;
2598                 if (np->msi_flags & NV_MSI_X_ENABLED)
2599                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2600                 else
2601                         writel(np->irqmask, base + NvRegIrqMask);
2602
2603                 spin_unlock_irqrestore(&np->lock, flags);
2604                 return 0;
2605         } else {
2606                 /* used up our quantum, so reschedule */
2607                 dev->quota -= pkts;
2608                 *budget -= pkts;
2609                 return 1;
2610         }
2611 }
2612 #endif
2613
2614 #ifdef CONFIG_FORCEDETH_NAPI
2615 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2616 {
2617         struct net_device *dev = (struct net_device *) data;
2618         u8 __iomem *base = get_hwbase(dev);
2619         u32 events;
2620
2621         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2622         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2623
2624         if (events) {
2625                 netif_rx_schedule(dev);
2626                 /* disable receive interrupts on the nic */
2627                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2628                 pci_push(base);
2629         }
2630         return IRQ_HANDLED;
2631 }
2632 #else
2633 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2634 {
2635         struct net_device *dev = (struct net_device *) data;
2636         struct fe_priv *np = netdev_priv(dev);
2637         u8 __iomem *base = get_hwbase(dev);
2638         u32 events;
2639         int i;
2640         unsigned long flags;
2641
2642         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2643
2644         for (i=0; ; i++) {
2645                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2646                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2647                 pci_push(base);
2648                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2649                 if (!(events & np->irqmask))
2650                         break;
2651
2652                 nv_rx_process(dev, dev->weight);
2653                 if (nv_alloc_rx(dev)) {
2654                         spin_lock_irqsave(&np->lock, flags);
2655                         if (!np->in_shutdown)
2656                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2657                         spin_unlock_irqrestore(&np->lock, flags);
2658                 }
2659
2660                 if (i > max_interrupt_work) {
2661                         spin_lock_irqsave(&np->lock, flags);
2662                         /* disable interrupts on the nic */
2663                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2664                         pci_push(base);
2665
2666                         if (!np->in_shutdown) {
2667                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2668                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2669                         }
2670                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2671                         spin_unlock_irqrestore(&np->lock, flags);
2672                         break;
2673                 }
2674         }
2675         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2676
2677         return IRQ_RETVAL(i);
2678 }
2679 #endif
2680
2681 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2682 {
2683         struct net_device *dev = (struct net_device *) data;
2684         struct fe_priv *np = netdev_priv(dev);
2685         u8 __iomem *base = get_hwbase(dev);
2686         u32 events;
2687         int i;
2688         unsigned long flags;
2689
2690         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2691
2692         for (i=0; ; i++) {
2693                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2694                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2695                 pci_push(base);
2696                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2697                 if (!(events & np->irqmask))
2698                         break;
2699
2700                 if (events & NVREG_IRQ_LINK) {
2701                         spin_lock_irqsave(&np->lock, flags);
2702                         nv_link_irq(dev);
2703                         spin_unlock_irqrestore(&np->lock, flags);
2704                 }
2705                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2706                         spin_lock_irqsave(&np->lock, flags);
2707                         nv_linkchange(dev);
2708                         spin_unlock_irqrestore(&np->lock, flags);
2709                         np->link_timeout = jiffies + LINK_TIMEOUT;
2710                 }
2711                 if (events & NVREG_IRQ_RECOVER_ERROR) {
2712                         spin_lock_irq(&np->lock);
2713                         /* disable interrupts on the nic */
2714                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2715                         pci_push(base);
2716
2717                         if (!np->in_shutdown) {
2718                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2719                                 np->recover_error = 1;
2720                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2721                         }
2722                         spin_unlock_irq(&np->lock);
2723                         break;
2724                 }
2725                 if (events & (NVREG_IRQ_UNKNOWN)) {
2726                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2727                                                 dev->name, events);
2728                 }
2729                 if (i > max_interrupt_work) {
2730                         spin_lock_irqsave(&np->lock, flags);
2731                         /* disable interrupts on the nic */
2732                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2733                         pci_push(base);
2734
2735                         if (!np->in_shutdown) {
2736                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2737                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2738                         }
2739                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2740                         spin_unlock_irqrestore(&np->lock, flags);
2741                         break;
2742                 }
2743
2744         }
2745         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2746
2747         return IRQ_RETVAL(i);
2748 }
2749
2750 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2751 {
2752         struct net_device *dev = (struct net_device *) data;
2753         struct fe_priv *np = netdev_priv(dev);
2754         u8 __iomem *base = get_hwbase(dev);
2755         u32 events;
2756
2757         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2758
2759         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2760                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2761                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2762         } else {
2763                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2764                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2765         }
2766         pci_push(base);
2767         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2768         if (!(events & NVREG_IRQ_TIMER))
2769                 return IRQ_RETVAL(0);
2770
2771         spin_lock(&np->lock);
2772         np->intr_test = 1;
2773         spin_unlock(&np->lock);
2774
2775         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2776
2777         return IRQ_RETVAL(1);
2778 }
2779
2780 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2781 {
2782         u8 __iomem *base = get_hwbase(dev);
2783         int i;
2784         u32 msixmap = 0;
2785
2786         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2787          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2788          * the remaining 8 interrupts.
2789          */
2790         for (i = 0; i < 8; i++) {
2791                 if ((irqmask >> i) & 0x1) {
2792                         msixmap |= vector << (i << 2);
2793                 }
2794         }
2795         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2796
2797         msixmap = 0;
2798         for (i = 0; i < 8; i++) {
2799                 if ((irqmask >> (i + 8)) & 0x1) {
2800                         msixmap |= vector << (i << 2);
2801                 }
2802         }
2803         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2804 }
2805
2806 static int nv_request_irq(struct net_device *dev, int intr_test)
2807 {
2808         struct fe_priv *np = get_nvpriv(dev);
2809         u8 __iomem *base = get_hwbase(dev);
2810         int ret = 1;
2811         int i;
2812
2813         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2814                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2815                         np->msi_x_entry[i].entry = i;
2816                 }
2817                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2818                         np->msi_flags |= NV_MSI_X_ENABLED;
2819                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2820                                 /* Request irq for rx handling */
2821                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2822                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2823                                         pci_disable_msix(np->pci_dev);
2824                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2825                                         goto out_err;
2826                                 }
2827                                 /* Request irq for tx handling */
2828                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2829                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2830                                         pci_disable_msix(np->pci_dev);
2831                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2832                                         goto out_free_rx;
2833                                 }
2834                                 /* Request irq for link and timer handling */
2835                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2836                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2837                                         pci_disable_msix(np->pci_dev);
2838                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2839                                         goto out_free_tx;
2840                                 }
2841                                 /* map interrupts to their respective vector */
2842                                 writel(0, base + NvRegMSIXMap0);
2843                                 writel(0, base + NvRegMSIXMap1);
2844                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2845                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2846                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2847                         } else {
2848                                 /* Request irq for all interrupts */
2849                                 if ((!intr_test &&
2850                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2851                                     (intr_test &&
2852                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2853                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2854                                         pci_disable_msix(np->pci_dev);
2855                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2856                                         goto out_err;
2857                                 }
2858
2859                                 /* map interrupts to vector 0 */
2860                                 writel(0, base + NvRegMSIXMap0);
2861                                 writel(0, base + NvRegMSIXMap1);
2862                         }
2863                 }
2864         }
2865         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2866                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2867                         np->msi_flags |= NV_MSI_ENABLED;
2868                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2869                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2870                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2871                                 pci_disable_msi(np->pci_dev);
2872                                 np->msi_flags &= ~NV_MSI_ENABLED;
2873                                 goto out_err;
2874                         }
2875
2876                         /* map interrupts to vector 0 */
2877                         writel(0, base + NvRegMSIMap0);
2878                         writel(0, base + NvRegMSIMap1);
2879                         /* enable msi vector 0 */
2880                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2881                 }
2882         }
2883         if (ret != 0) {
2884                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2885                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2886                         goto out_err;
2887
2888         }
2889
2890         return 0;
2891 out_free_tx:
2892         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2893 out_free_rx:
2894         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2895 out_err:
2896         return 1;
2897 }
2898
2899 static void nv_free_irq(struct net_device *dev)
2900 {
2901         struct fe_priv *np = get_nvpriv(dev);
2902         int i;
2903
2904         if (np->msi_flags & NV_MSI_X_ENABLED) {
2905                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2906                         free_irq(np->msi_x_entry[i].vector, dev);
2907                 }
2908                 pci_disable_msix(np->pci_dev);
2909                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2910         } else {
2911                 free_irq(np->pci_dev->irq, dev);
2912                 if (np->msi_flags & NV_MSI_ENABLED) {
2913                         pci_disable_msi(np->pci_dev);
2914                         np->msi_flags &= ~NV_MSI_ENABLED;
2915                 }
2916         }
2917 }
2918
2919 static void nv_do_nic_poll(unsigned long data)
2920 {
2921         struct net_device *dev = (struct net_device *) data;
2922         struct fe_priv *np = netdev_priv(dev);
2923         u8 __iomem *base = get_hwbase(dev);
2924         u32 mask = 0;
2925
2926         /*
2927          * First disable irq(s) and then
2928          * reenable interrupts on the nic, we have to do this before calling
2929          * nv_nic_irq because that may decide to do otherwise
2930          */
2931
2932         if (!using_multi_irqs(dev)) {
2933                 if (np->msi_flags & NV_MSI_X_ENABLED)
2934                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2935                 else
2936                         disable_irq_lockdep(dev->irq);
2937                 mask = np->irqmask;
2938         } else {
2939                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2940                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2941                         mask |= NVREG_IRQ_RX_ALL;
2942                 }
2943                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2944                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2945                         mask |= NVREG_IRQ_TX_ALL;
2946                 }
2947                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2948                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2949                         mask |= NVREG_IRQ_OTHER;
2950                 }
2951         }
2952         np->nic_poll_irq = 0;
2953
2954         if (np->recover_error) {
2955                 np->recover_error = 0;
2956                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
2957                 if (netif_running(dev)) {
2958                         netif_tx_lock_bh(dev);
2959                         spin_lock(&np->lock);
2960                         /* stop engines */
2961                         nv_stop_rx(dev);
2962                         nv_stop_tx(dev);
2963                         nv_txrx_reset(dev);
2964                         /* drain rx queue */
2965                         nv_drain_rx(dev);
2966                         nv_drain_tx(dev);
2967                         /* reinit driver view of the rx queue */
2968                         set_bufsize(dev);
2969                         if (nv_init_ring(dev)) {
2970                                 if (!np->in_shutdown)
2971                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2972                         }
2973                         /* reinit nic view of the rx queue */
2974                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2975                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2976                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2977                                 base + NvRegRingSizes);
2978                         pci_push(base);
2979                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2980                         pci_push(base);
2981
2982                         /* restart rx engine */
2983                         nv_start_rx(dev);
2984                         nv_start_tx(dev);
2985                         spin_unlock(&np->lock);
2986                         netif_tx_unlock_bh(dev);
2987                 }
2988         }
2989
2990         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2991
2992         writel(mask, base + NvRegIrqMask);
2993         pci_push(base);
2994
2995         if (!using_multi_irqs(dev)) {
2996                 nv_nic_irq(0, dev);
2997                 if (np->msi_flags & NV_MSI_X_ENABLED)
2998                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2999                 else
3000                         enable_irq_lockdep(dev->irq);
3001         } else {
3002                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3003                         nv_nic_irq_rx(0, dev);
3004                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3005                 }
3006                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3007                         nv_nic_irq_tx(0, dev);
3008                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3009                 }
3010                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3011                         nv_nic_irq_other(0, dev);
3012                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3013                 }
3014         }
3015 }
3016
3017 #ifdef CONFIG_NET_POLL_CONTROLLER
3018 static void nv_poll_controller(struct net_device *dev)
3019 {
3020         nv_do_nic_poll((unsigned long) dev);
3021 }
3022 #endif
3023
3024 static void nv_do_stats_poll(unsigned long data)
3025 {
3026         struct net_device *dev = (struct net_device *) data;
3027         struct fe_priv *np = netdev_priv(dev);
3028         u8 __iomem *base = get_hwbase(dev);
3029
3030         np->estats.tx_bytes += readl(base + NvRegTxCnt);
3031         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3032         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3033         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3034         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3035         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3036         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3037         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3038         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3039         np->estats.tx_deferral += readl(base + NvRegTxDef);
3040         np->estats.tx_packets += readl(base + NvRegTxFrame);
3041         np->estats.tx_pause += readl(base + NvRegTxPause);
3042         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3043         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3044         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3045         np->estats.rx_runt += readl(base + NvRegRxRunt);
3046         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3047         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3048         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3049         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3050         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3051         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3052         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3053         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3054         np->estats.rx_bytes += readl(base + NvRegRxCnt);
3055         np->estats.rx_pause += readl(base + NvRegRxPause);
3056         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3057         np->estats.rx_packets =
3058                 np->estats.rx_unicast +
3059                 np->estats.rx_multicast +
3060                 np->estats.rx_broadcast;
3061         np->estats.rx_errors_total =
3062                 np->estats.rx_crc_errors +
3063                 np->estats.rx_over_errors +
3064                 np->estats.rx_frame_error +
3065                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3066                 np->estats.rx_late_collision +
3067                 np->estats.rx_runt +
3068                 np->estats.rx_frame_too_long;
3069
3070         if (!np->in_shutdown)
3071                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3072 }
3073
3074 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3075 {
3076         struct fe_priv *np = netdev_priv(dev);
3077         strcpy(info->driver, "forcedeth");
3078         strcpy(info->version, FORCEDETH_VERSION);
3079         strcpy(info->bus_info, pci_name(np->pci_dev));
3080 }
3081
3082 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3083 {
3084         struct fe_priv *np = netdev_priv(dev);
3085         wolinfo->supported = WAKE_MAGIC;
3086
3087         spin_lock_irq(&np->lock);
3088         if (np->wolenabled)
3089                 wolinfo->wolopts = WAKE_MAGIC;
3090         spin_unlock_irq(&np->lock);
3091 }
3092
3093 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3094 {
3095         struct fe_priv *np = netdev_priv(dev);
3096         u8 __iomem *base = get_hwbase(dev);
3097         u32 flags = 0;
3098
3099         if (wolinfo->wolopts == 0) {
3100                 np->wolenabled = 0;
3101         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3102                 np->wolenabled = 1;
3103                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3104         }
3105         if (netif_running(dev)) {
3106                 spin_lock_irq(&np->lock);
3107                 writel(flags, base + NvRegWakeUpFlags);
3108                 spin_unlock_irq(&np->lock);
3109         }
3110         return 0;
3111 }
3112
3113 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3114 {
3115         struct fe_priv *np = netdev_priv(dev);
3116         int adv;
3117
3118         spin_lock_irq(&np->lock);
3119         ecmd->port = PORT_MII;
3120         if (!netif_running(dev)) {
3121                 /* We do not track link speed / duplex setting if the
3122                  * interface is disabled. Force a link check */
3123                 if (nv_update_linkspeed(dev)) {
3124                         if (!netif_carrier_ok(dev))
3125                                 netif_carrier_on(dev);
3126                 } else {
3127                         if (netif_carrier_ok(dev))
3128                                 netif_carrier_off(dev);
3129                 }
3130         }
3131
3132         if (netif_carrier_ok(dev)) {
3133                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3134                 case NVREG_LINKSPEED_10:
3135                         ecmd->speed = SPEED_10;
3136                         break;
3137                 case NVREG_LINKSPEED_100:
3138                         ecmd->speed = SPEED_100;
3139                         break;
3140                 case NVREG_LINKSPEED_1000:
3141                         ecmd->speed = SPEED_1000;
3142                         break;
3143                 }
3144                 ecmd->duplex = DUPLEX_HALF;
3145                 if (np->duplex)
3146                         ecmd->duplex = DUPLEX_FULL;
3147         } else {
3148                 ecmd->speed = -1;
3149                 ecmd->duplex = -1;
3150         }
3151
3152         ecmd->autoneg = np->autoneg;
3153
3154         ecmd->advertising = ADVERTISED_MII;
3155         if (np->autoneg) {
3156                 ecmd->advertising |= ADVERTISED_Autoneg;
3157                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3158                 if (adv & ADVERTISE_10HALF)
3159                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3160                 if (adv & ADVERTISE_10FULL)
3161                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3162                 if (adv & ADVERTISE_100HALF)
3163                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3164                 if (adv & ADVERTISE_100FULL)
3165                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3166                 if (np->gigabit == PHY_GIGABIT) {
3167                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3168                         if (adv & ADVERTISE_1000FULL)
3169                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3170                 }
3171         }
3172         ecmd->supported = (SUPPORTED_Autoneg |
3173                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3174                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3175                 SUPPORTED_MII);
3176         if (np->gigabit == PHY_GIGABIT)
3177                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3178
3179         ecmd->phy_address = np->phyaddr;
3180         ecmd->transceiver = XCVR_EXTERNAL;
3181
3182         /* ignore maxtxpkt, maxrxpkt for now */
3183         spin_unlock_irq(&np->lock);
3184         return 0;
3185 }
3186
3187 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3188 {
3189         struct fe_priv *np = netdev_priv(dev);
3190
3191         if (ecmd->port != PORT_MII)
3192                 return -EINVAL;
3193         if (ecmd->transceiver != XCVR_EXTERNAL)
3194                 return -EINVAL;
3195         if (ecmd->phy_address != np->phyaddr) {
3196                 /* TODO: support switching between multiple phys. Should be
3197                  * trivial, but not enabled due to lack of test hardware. */
3198                 return -EINVAL;
3199         }
3200         if (ecmd->autoneg == AUTONEG_ENABLE) {
3201                 u32 mask;
3202
3203                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3204                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3205                 if (np->gigabit == PHY_GIGABIT)
3206                         mask |= ADVERTISED_1000baseT_Full;
3207
3208                 if ((ecmd->advertising & mask) == 0)
3209                         return -EINVAL;
3210
3211         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3212                 /* Note: autonegotiation disable, speed 1000 intentionally
3213                  * forbidden - noone should need that. */
3214
3215                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3216                         return -EINVAL;
3217                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3218                         return -EINVAL;
3219         } else {
3220                 return -EINVAL;
3221         }
3222
3223         netif_carrier_off(dev);
3224         if (netif_running(dev)) {
3225                 nv_disable_irq(dev);
3226                 netif_tx_lock_bh(dev);
3227                 spin_lock(&np->lock);
3228                 /* stop engines */
3229                 nv_stop_rx(dev);
3230                 nv_stop_tx(dev);
3231                 spin_unlock(&np->lock);
3232                 netif_tx_unlock_bh(dev);
3233         }
3234
3235         if (ecmd->autoneg == AUTONEG_ENABLE) {
3236                 int adv, bmcr;
3237
3238                 np->autoneg = 1;
3239
3240                 /* advertise only what has been requested */
3241                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3242                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3243                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3244                         adv |= ADVERTISE_10HALF;
3245                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3246                         adv |= ADVERTISE_10FULL;
3247                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3248                         adv |= ADVERTISE_100HALF;
3249                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3250                         adv |= ADVERTISE_100FULL;
3251                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3252                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3253                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3254                         adv |=  ADVERTISE_PAUSE_ASYM;
3255                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3256
3257                 if (np->gigabit == PHY_GIGABIT) {
3258                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3259                         adv &= ~ADVERTISE_1000FULL;
3260                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3261                                 adv |= ADVERTISE_1000FULL;
3262                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3263                 }
3264
3265                 if (netif_running(dev))
3266                         printk(KERN_INFO "%s: link down.\n", dev->name);
3267                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3268                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3269                         bmcr |= BMCR_ANENABLE;
3270                         /* reset the phy in order for settings to stick,
3271                          * and cause autoneg to start */
3272                         if (phy_reset(dev, bmcr)) {
3273                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3274                                 return -EINVAL;
3275                         }
3276                 } else {
3277                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3278                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3279                 }
3280         } else {
3281                 int adv, bmcr;
3282
3283                 np->autoneg = 0;
3284
3285                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3286                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3287                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3288                         adv |= ADVERTISE_10HALF;
3289                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3290                         adv |= ADVERTISE_10FULL;
3291                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3292                         adv |= ADVERTISE_100HALF;
3293                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3294                         adv |= ADVERTISE_100FULL;
3295                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3296                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3297                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3298                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3299                 }
3300                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3301                         adv |=  ADVERTISE_PAUSE_ASYM;
3302                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3303                 }
3304                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3305                 np->fixed_mode = adv;
3306
3307                 if (np->gigabit == PHY_GIGABIT) {
3308                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3309                         adv &= ~ADVERTISE_1000FULL;
3310                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3311                 }
3312
3313                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3314                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3315                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3316                         bmcr |= BMCR_FULLDPLX;
3317                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3318                         bmcr |= BMCR_SPEED100;
3319                 if (np->phy_oui == PHY_OUI_MARVELL) {
3320                         /* reset the phy in order for forced mode settings to stick */
3321                         if (phy_reset(dev, bmcr)) {
3322                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3323                                 return -EINVAL;
3324                         }
3325                 } else {
3326                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3327                         if (netif_running(dev)) {
3328                                 /* Wait a bit and then reconfigure the nic. */
3329                                 udelay(10);
3330                                 nv_linkchange(dev);
3331                         }
3332                 }
3333         }
3334
3335         if (netif_running(dev)) {
3336                 nv_start_rx(dev);
3337                 nv_start_tx(dev);
3338                 nv_enable_irq(dev);
3339         }
3340
3341         return 0;
3342 }
3343
3344 #define FORCEDETH_REGS_VER      1
3345
3346 static int nv_get_regs_len(struct net_device *dev)
3347 {
3348         struct fe_priv *np = netdev_priv(dev);
3349         return np->register_size;
3350 }
3351
3352 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3353 {
3354         struct fe_priv *np = netdev_priv(dev);
3355         u8 __iomem *base = get_hwbase(dev);
3356         u32 *rbuf = buf;
3357         int i;
3358
3359         regs->version = FORCEDETH_REGS_VER;
3360         spin_lock_irq(&np->lock);
3361         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3362                 rbuf[i] = readl(base + i*sizeof(u32));
3363         spin_unlock_irq(&np->lock);
3364 }
3365
3366 static int nv_nway_reset(struct net_device *dev)
3367 {
3368         struct fe_priv *np = netdev_priv(dev);
3369         int ret;
3370
3371         if (np->autoneg) {
3372                 int bmcr;
3373
3374                 netif_carrier_off(dev);
3375                 if (netif_running(dev)) {
3376                         nv_disable_irq(dev);
3377                         netif_tx_lock_bh(dev);
3378                         spin_lock(&np->lock);
3379                         /* stop engines */
3380                         nv_stop_rx(dev);
3381                         nv_stop_tx(dev);
3382                         spin_unlock(&np->lock);
3383                         netif_tx_unlock_bh(dev);
3384                         printk(KERN_INFO "%s: link down.\n", dev->name);
3385                 }
3386
3387                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3388                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3389                         bmcr |= BMCR_ANENABLE;
3390                         /* reset the phy in order for settings to stick*/
3391                         if (phy_reset(dev, bmcr)) {
3392                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3393                                 return -EINVAL;
3394                         }
3395                 } else {
3396                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3397                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3398                 }
3399
3400                 if (netif_running(dev)) {
3401                         nv_start_rx(dev);
3402                         nv_start_tx(dev);
3403                         nv_enable_irq(dev);
3404                 }
3405                 ret = 0;
3406         } else {
3407                 ret = -EINVAL;
3408         }
3409
3410         return ret;
3411 }
3412
3413 static int nv_set_tso(struct net_device *dev, u32 value)
3414 {
3415         struct fe_priv *np = netdev_priv(dev);
3416
3417         if ((np->driver_data & DEV_HAS_CHECKSUM))
3418                 return ethtool_op_set_tso(dev, value);
3419         else
3420                 return -EOPNOTSUPP;
3421 }
3422
3423 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3424 {
3425         struct fe_priv *np = netdev_priv(dev);
3426
3427         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3428         ring->rx_mini_max_pending = 0;
3429         ring->rx_jumbo_max_pending = 0;
3430         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3431
3432         ring->rx_pending = np->rx_ring_size;
3433         ring->rx_mini_pending = 0;
3434         ring->rx_jumbo_pending = 0;
3435         ring->tx_pending = np->tx_ring_size;
3436 }
3437
3438 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3439 {
3440         struct fe_priv *np = netdev_priv(dev);
3441         u8 __iomem *base = get_hwbase(dev);
3442         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3443         dma_addr_t ring_addr;
3444
3445         if (ring->rx_pending < RX_RING_MIN ||
3446             ring->tx_pending < TX_RING_MIN ||
3447             ring->rx_mini_pending != 0 ||
3448             ring->rx_jumbo_pending != 0 ||
3449             (np->desc_ver == DESC_VER_1 &&
3450              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3451               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3452             (np->desc_ver != DESC_VER_1 &&
3453              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3454               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3455                 return -EINVAL;
3456         }
3457
3458         /* allocate new rings */
3459         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3460                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3461                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3462                                             &ring_addr);
3463         } else {
3464                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3465                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3466                                             &ring_addr);
3467         }
3468         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3469         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3470         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3471         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3472         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3473         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3474                 /* fall back to old rings */
3475                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3476                         if (rxtx_ring)
3477                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3478                                                     rxtx_ring, ring_addr);
3479                 } else {
3480                         if (rxtx_ring)
3481                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3482                                                     rxtx_ring, ring_addr);
3483                 }
3484                 if (rx_skbuff)
3485                         kfree(rx_skbuff);
3486                 if (rx_dma)
3487                         kfree(rx_dma);
3488                 if (tx_skbuff)
3489                         kfree(tx_skbuff);
3490                 if (tx_dma)
3491                         kfree(tx_dma);
3492                 if (tx_dma_len)
3493                         kfree(tx_dma_len);
3494                 goto exit;
3495         }
3496
3497         if (netif_running(dev)) {
3498                 nv_disable_irq(dev);
3499                 netif_tx_lock_bh(dev);
3500                 spin_lock(&np->lock);
3501                 /* stop engines */
3502                 nv_stop_rx(dev);
3503                 nv_stop_tx(dev);
3504                 nv_txrx_reset(dev);
3505                 /* drain queues */
3506                 nv_drain_rx(dev);
3507                 nv_drain_tx(dev);
3508                 /* delete queues */
3509                 free_rings(dev);
3510         }
3511
3512         /* set new values */
3513         np->rx_ring_size = ring->rx_pending;
3514         np->tx_ring_size = ring->tx_pending;
3515         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3516         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3517         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3518                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3519                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3520         } else {
3521                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3522                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3523         }
3524         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3525         np->rx_dma = (dma_addr_t*)rx_dma;
3526         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3527         np->tx_dma = (dma_addr_t*)tx_dma;
3528         np->tx_dma_len = (unsigned int*)tx_dma_len;
3529         np->ring_addr = ring_addr;
3530
3531         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3532         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3533         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3534         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3535         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3536
3537         if (netif_running(dev)) {
3538                 /* reinit driver view of the queues */
3539                 set_bufsize(dev);
3540                 if (nv_init_ring(dev)) {
3541                         if (!np->in_shutdown)
3542                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3543                 }
3544
3545                 /* reinit nic view of the queues */
3546                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3547                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3548                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3549                         base + NvRegRingSizes);
3550                 pci_push(base);
3551                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3552                 pci_push(base);
3553
3554                 /* restart engines */
3555                 nv_start_rx(dev);
3556                 nv_start_tx(dev);
3557                 spin_unlock(&np->lock);
3558                 netif_tx_unlock_bh(dev);
3559                 nv_enable_irq(dev);
3560         }
3561         return 0;
3562 exit:
3563         return -ENOMEM;
3564 }
3565
3566 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3567 {
3568         struct fe_priv *np = netdev_priv(dev);
3569
3570         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3571         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3572         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3573 }
3574
3575 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3576 {
3577         struct fe_priv *np = netdev_priv(dev);
3578         int adv, bmcr;
3579
3580         if ((!np->autoneg && np->duplex == 0) ||
3581             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3582                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3583                        dev->name);
3584                 return -EINVAL;
3585         }
3586         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3587                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3588                 return -EINVAL;
3589         }
3590
3591         netif_carrier_off(dev);
3592         if (netif_running(dev)) {
3593                 nv_disable_irq(dev);
3594                 netif_tx_lock_bh(dev);
3595                 spin_lock(&np->lock);
3596                 /* stop engines */
3597                 nv_stop_rx(dev);
3598                 nv_stop_tx(dev);
3599                 spin_unlock(&np->lock);
3600                 netif_tx_unlock_bh(dev);
3601         }
3602
3603         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3604         if (pause->rx_pause)
3605                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3606         if (pause->tx_pause)
3607                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3608
3609         if (np->autoneg && pause->autoneg) {
3610                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3611
3612                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3613                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3614                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3615                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3616                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3617                         adv |=  ADVERTISE_PAUSE_ASYM;
3618                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3619
3620                 if (netif_running(dev))
3621                         printk(KERN_INFO "%s: link down.\n", dev->name);
3622                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3623                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3624                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3625         } else {
3626                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3627                 if (pause->rx_pause)
3628                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3629                 if (pause->tx_pause)
3630                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3631
3632                 if (!netif_running(dev))
3633                         nv_update_linkspeed(dev);
3634                 else
3635                         nv_update_pause(dev, np->pause_flags);
3636         }
3637
3638         if (netif_running(dev)) {
3639                 nv_start_rx(dev);
3640                 nv_start_tx(dev);
3641                 nv_enable_irq(dev);
3642         }
3643         return 0;
3644 }
3645
3646 static u32 nv_get_rx_csum(struct net_device *dev)
3647 {
3648         struct fe_priv *np = netdev_priv(dev);
3649         return (np->rx_csum) != 0;
3650 }
3651
3652 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3653 {
3654         struct fe_priv *np = netdev_priv(dev);
3655         u8 __iomem *base = get_hwbase(dev);
3656         int retcode = 0;
3657
3658         if (np->driver_data & DEV_HAS_CHECKSUM) {
3659                 if (data) {
3660                         np->rx_csum = 1;
3661                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3662                 } else {
3663                         np->rx_csum = 0;
3664                         /* vlan is dependent on rx checksum offload */
3665                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3666                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3667                 }
3668                 if (netif_running(dev)) {
3669                         spin_lock_irq(&np->lock);
3670                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3671                         spin_unlock_irq(&np->lock);
3672                 }
3673         } else {
3674                 return -EINVAL;
3675         }
3676
3677         return retcode;
3678 }
3679
3680 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3681 {
3682         struct fe_priv *np = netdev_priv(dev);
3683
3684         if (np->driver_data & DEV_HAS_CHECKSUM)
3685                 return ethtool_op_set_tx_hw_csum(dev, data);
3686         else
3687                 return -EOPNOTSUPP;
3688 }
3689
3690 static int nv_set_sg(struct net_device *dev, u32 data)
3691 {
3692         struct fe_priv *np = netdev_priv(dev);
3693
3694         if (np->driver_data & DEV_HAS_CHECKSUM)
3695                 return ethtool_op_set_sg(dev, data);
3696         else
3697                 return -EOPNOTSUPP;
3698 }
3699
3700 static int nv_get_stats_count(struct net_device *dev)
3701 {
3702         struct fe_priv *np = netdev_priv(dev);
3703
3704         if (np->driver_data & DEV_HAS_STATISTICS)
3705                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3706         else
3707                 return 0;
3708 }
3709
3710 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3711 {
3712         struct fe_priv *np = netdev_priv(dev);
3713
3714         /* update stats */
3715         nv_do_stats_poll((unsigned long)dev);
3716
3717         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3718 }
3719
3720 static int nv_self_test_count(struct net_device *dev)
3721 {
3722         struct fe_priv *np = netdev_priv(dev);
3723
3724         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3725                 return NV_TEST_COUNT_EXTENDED;
3726         else
3727                 return NV_TEST_COUNT_BASE;
3728 }
3729
3730 static int nv_link_test(struct net_device *dev)
3731 {
3732         struct fe_priv *np = netdev_priv(dev);
3733         int mii_status;
3734
3735         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3736         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3737
3738         /* check phy link status */
3739         if (!(mii_status & BMSR_LSTATUS))
3740                 return 0;
3741         else
3742                 return 1;
3743 }
3744
3745 static int nv_register_test(struct net_device *dev)
3746 {
3747         u8 __iomem *base = get_hwbase(dev);
3748         int i = 0;
3749         u32 orig_read, new_read;
3750
3751         do {
3752                 orig_read = readl(base + nv_registers_test[i].reg);
3753
3754                 /* xor with mask to toggle bits */
3755                 orig_read ^= nv_registers_test[i].mask;
3756
3757                 writel(orig_read, base + nv_registers_test[i].reg);
3758
3759                 new_read = readl(base + nv_registers_test[i].reg);
3760
3761                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3762                         return 0;
3763
3764                 /* restore original value */
3765                 orig_read ^= nv_registers_test[i].mask;
3766                 writel(orig_read, base + nv_registers_test[i].reg);
3767
3768         } while (nv_registers_test[++i].reg != 0);
3769
3770         return 1;
3771 }
3772
3773 static int nv_interrupt_test(struct net_device *dev)
3774 {
3775         struct fe_priv *np = netdev_priv(dev);
3776         u8 __iomem *base = get_hwbase(dev);
3777         int ret = 1;
3778         int testcnt;
3779         u32 save_msi_flags, save_poll_interval = 0;
3780
3781         if (netif_running(dev)) {
3782                 /* free current irq */
3783                 nv_free_irq(dev);
3784                 save_poll_interval = readl(base+NvRegPollingInterval);
3785         }
3786
3787         /* flag to test interrupt handler */
3788         np->intr_test = 0;
3789
3790         /* setup test irq */
3791         save_msi_flags = np->msi_flags;
3792         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3793         np->msi_flags |= 0x001; /* setup 1 vector */
3794         if (nv_request_irq(dev, 1))
3795                 return 0;
3796
3797         /* setup timer interrupt */
3798         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3799         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3800
3801         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3802
3803         /* wait for at least one interrupt */
3804         msleep(100);
3805
3806         spin_lock_irq(&np->lock);
3807
3808         /* flag should be set within ISR */
3809         testcnt = np->intr_test;
3810         if (!testcnt)
3811                 ret = 2;
3812
3813         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3814         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3815                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3816         else
3817                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3818
3819         spin_unlock_irq(&np->lock);
3820
3821         nv_free_irq(dev);
3822
3823         np->msi_flags = save_msi_flags;
3824
3825         if (netif_running(dev)) {
3826                 writel(save_poll_interval, base + NvRegPollingInterval);
3827                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3828                 /* restore original irq */
3829                 if (nv_request_irq(dev, 0))
3830                         return 0;
3831         }
3832
3833         return ret;
3834 }
3835
3836 static int nv_loopback_test(struct net_device *dev)
3837 {
3838         struct fe_priv *np = netdev_priv(dev);
3839         u8 __iomem *base = get_hwbase(dev);
3840         struct sk_buff *tx_skb, *rx_skb;
3841         dma_addr_t test_dma_addr;
3842         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3843         u32 flags;
3844         int len, i, pkt_len;
3845         u8 *pkt_data;
3846         u32 filter_flags = 0;
3847         u32 misc1_flags = 0;
3848         int ret = 1;
3849
3850         if (netif_running(dev)) {
3851                 nv_disable_irq(dev);
3852                 filter_flags = readl(base + NvRegPacketFilterFlags);
3853                 misc1_flags = readl(base + NvRegMisc1);
3854         } else {
3855                 nv_txrx_reset(dev);
3856         }
3857
3858         /* reinit driver view of the rx queue */
3859         set_bufsize(dev);
3860         nv_init_ring(dev);
3861
3862         /* setup hardware for loopback */
3863         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3864         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3865
3866         /* reinit nic view of the rx queue */
3867         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3868         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3869         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3870                 base + NvRegRingSizes);
3871         pci_push(base);
3872
3873         /* restart rx engine */
3874         nv_start_rx(dev);
3875         nv_start_tx(dev);
3876
3877         /* setup packet for tx */
3878         pkt_len = ETH_DATA_LEN;
3879         tx_skb = dev_alloc_skb(pkt_len);
3880         if (!tx_skb) {
3881                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3882                          " of %s\n", dev->name);
3883                 ret = 0;
3884                 goto out;
3885         }
3886         pkt_data = skb_put(tx_skb, pkt_len);
3887         for (i = 0; i < pkt_len; i++)
3888                 pkt_data[i] = (u8)(i & 0xff);
3889         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3890                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3891
3892         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3893                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3894                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3895         } else {
3896                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3897                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3898                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3899         }
3900         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3901         pci_push(get_hwbase(dev));
3902
3903         msleep(500);
3904
3905         /* check for rx of the packet */
3906         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3907                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3908                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3909
3910         } else {
3911                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3912                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3913         }
3914
3915         if (flags & NV_RX_AVAIL) {
3916                 ret = 0;
3917         } else if (np->desc_ver == DESC_VER_1) {
3918                 if (flags & NV_RX_ERROR)
3919                         ret = 0;
3920         } else {
3921                 if (flags & NV_RX2_ERROR) {
3922                         ret = 0;
3923                 }
3924         }
3925
3926         if (ret) {
3927                 if (len != pkt_len) {
3928                         ret = 0;
3929                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3930                                 dev->name, len, pkt_len);
3931                 } else {
3932                         rx_skb = np->rx_skbuff[0];
3933                         for (i = 0; i < pkt_len; i++) {
3934                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3935                                         ret = 0;
3936                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3937                                                 dev->name, i);
3938                                         break;
3939                                 }
3940                         }
3941                 }
3942         } else {
3943                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3944         }
3945
3946         pci_unmap_page(np->pci_dev, test_dma_addr,
3947                        tx_skb->end-tx_skb->data,
3948                        PCI_DMA_TODEVICE);
3949         dev_kfree_skb_any(tx_skb);
3950  out:
3951         /* stop engines */
3952         nv_stop_rx(dev);
3953         nv_stop_tx(dev);
3954         nv_txrx_reset(dev);
3955         /* drain rx queue */
3956         nv_drain_rx(dev);
3957         nv_drain_tx(dev);
3958
3959         if (netif_running(dev)) {
3960                 writel(misc1_flags, base + NvRegMisc1);
3961                 writel(filter_flags, base + NvRegPacketFilterFlags);
3962                 nv_enable_irq(dev);
3963         }
3964
3965         return ret;
3966 }
3967
3968 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3969 {
3970         struct fe_priv *np = netdev_priv(dev);
3971         u8 __iomem *base = get_hwbase(dev);
3972         int result;
3973         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3974
3975         if (!nv_link_test(dev)) {
3976                 test->flags |= ETH_TEST_FL_FAILED;
3977                 buffer[0] = 1;
3978         }
3979
3980         if (test->flags & ETH_TEST_FL_OFFLINE) {
3981                 if (netif_running(dev)) {
3982                         netif_stop_queue(dev);
3983                         netif_poll_disable(dev);
3984                         netif_tx_lock_bh(dev);
3985                         spin_lock_irq(&np->lock);
3986                         nv_disable_hw_interrupts(dev, np->irqmask);
3987                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3988                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3989                         } else {
3990                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3991                         }
3992                         /* stop engines */
3993                         nv_stop_rx(dev);
3994                         nv_stop_tx(dev);
3995                         nv_txrx_reset(dev);
3996                         /* drain rx queue */
3997                         nv_drain_rx(dev);
3998                         nv_drain_tx(dev);
3999                         spin_unlock_irq(&np->lock);
4000                         netif_tx_unlock_bh(dev);
4001                 }
4002
4003                 if (!nv_register_test(dev)) {
4004                         test->flags |= ETH_TEST_FL_FAILED;
4005                         buffer[1] = 1;
4006                 }
4007
4008                 result = nv_interrupt_test(dev);
4009                 if (result != 1) {
4010                         test->flags |= ETH_TEST_FL_FAILED;
4011                         buffer[2] = 1;
4012                 }
4013                 if (result == 0) {
4014                         /* bail out */
4015                         return;
4016                 }
4017
4018                 if (!nv_loopback_test(dev)) {
4019                         test->flags |= ETH_TEST_FL_FAILED;
4020                         buffer[3] = 1;
4021                 }
4022
4023                 if (netif_running(dev)) {
4024                         /* reinit driver view of the rx queue */
4025                         set_bufsize(dev);
4026                         if (nv_init_ring(dev)) {
4027                                 if (!np->in_shutdown)
4028                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4029                         }
4030                         /* reinit nic view of the rx queue */
4031                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4032                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4033                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4034                                 base + NvRegRingSizes);
4035                         pci_push(base);
4036                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4037                         pci_push(base);
4038                         /* restart rx engine */
4039                         nv_start_rx(dev);
4040                         nv_start_tx(dev);
4041                         netif_start_queue(dev);
4042                         netif_poll_enable(dev);
4043                         nv_enable_hw_interrupts(dev, np->irqmask);
4044                 }
4045         }
4046 }
4047
4048 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4049 {
4050         switch (stringset) {
4051         case ETH_SS_STATS:
4052                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4053                 break;
4054         case ETH_SS_TEST:
4055                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4056                 break;
4057         }
4058 }
4059
4060 static const struct ethtool_ops ops = {
4061         .get_drvinfo = nv_get_drvinfo,
4062         .get_link = ethtool_op_get_link,
4063         .get_wol = nv_get_wol,
4064         .set_wol = nv_set_wol,
4065         .get_settings = nv_get_settings,
4066         .set_settings = nv_set_settings,
4067         .get_regs_len = nv_get_regs_len,
4068         .get_regs = nv_get_regs,
4069         .nway_reset = nv_nway_reset,
4070         .get_perm_addr = ethtool_op_get_perm_addr,
4071         .get_tso = ethtool_op_get_tso,
4072         .set_tso = nv_set_tso,
4073         .get_ringparam = nv_get_ringparam,
4074         .set_ringparam = nv_set_ringparam,
4075         .get_pauseparam = nv_get_pauseparam,
4076         .set_pauseparam = nv_set_pauseparam,
4077         .get_rx_csum = nv_get_rx_csum,
4078         .set_rx_csum = nv_set_rx_csum,
4079         .get_tx_csum = ethtool_op_get_tx_csum,
4080         .set_tx_csum = nv_set_tx_csum,
4081         .get_sg = ethtool_op_get_sg,
4082         .set_sg = nv_set_sg,
4083         .get_strings = nv_get_strings,
4084         .get_stats_count = nv_get_stats_count,
4085         .get_ethtool_stats = nv_get_ethtool_stats,
4086         .self_test_count = nv_self_test_count,
4087         .self_test = nv_self_test,
4088 };
4089
4090 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4091 {
4092         struct fe_priv *np = get_nvpriv(dev);
4093
4094         spin_lock_irq(&np->lock);
4095
4096         /* save vlan group */
4097         np->vlangrp = grp;
4098
4099         if (grp) {
4100                 /* enable vlan on MAC */
4101                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4102         } else {
4103                 /* disable vlan on MAC */
4104                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4105                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4106         }
4107
4108         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4109
4110         spin_unlock_irq(&np->lock);
4111 };
4112
4113 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4114 {
4115         /* nothing to do */
4116 };
4117
4118 /* The mgmt unit and driver use a semaphore to access the phy during init */
4119 static int nv_mgmt_acquire_sema(struct net_device *dev)
4120 {
4121         u8 __iomem *base = get_hwbase(dev);
4122         int i;
4123         u32 tx_ctrl, mgmt_sema;
4124
4125         for (i = 0; i < 10; i++) {
4126                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4127                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4128                         break;
4129                 msleep(500);
4130         }
4131
4132         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4133                 return 0;
4134
4135         for (i = 0; i < 2; i++) {
4136                 tx_ctrl = readl(base + NvRegTransmitterControl);
4137                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4138                 writel(tx_ctrl, base + NvRegTransmitterControl);
4139
4140                 /* verify that semaphore was acquired */
4141                 tx_ctrl = readl(base + NvRegTransmitterControl);
4142                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4143                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4144                         return 1;
4145                 else
4146                         udelay(50);
4147         }
4148
4149         return 0;
4150 }
4151
4152 /* Indicate to mgmt unit whether driver is loaded or not */
4153 static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
4154 {
4155         u8 __iomem *base = get_hwbase(dev);
4156         u32 tx_ctrl;
4157
4158         tx_ctrl = readl(base + NvRegTransmitterControl);
4159         if (loaded)
4160                 tx_ctrl |= NVREG_XMITCTL_HOST_LOADED;
4161         else
4162                 tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
4163         writel(tx_ctrl, base + NvRegTransmitterControl);
4164 }
4165
4166 static int nv_open(struct net_device *dev)
4167 {
4168         struct fe_priv *np = netdev_priv(dev);
4169         u8 __iomem *base = get_hwbase(dev);
4170         int ret = 1;
4171         int oom, i;
4172
4173         dprintk(KERN_DEBUG "nv_open: begin\n");
4174
4175         /* erase previous misconfiguration */
4176         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4177                 nv_mac_reset(dev);
4178         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4179         writel(0, base + NvRegMulticastAddrB);
4180         writel(0, base + NvRegMulticastMaskA);
4181         writel(0, base + NvRegMulticastMaskB);
4182         writel(0, base + NvRegPacketFilterFlags);
4183
4184         writel(0, base + NvRegTransmitterControl);
4185         writel(0, base + NvRegReceiverControl);
4186
4187         writel(0, base + NvRegAdapterControl);
4188
4189         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4190                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4191
4192         /* initialize descriptor rings */
4193         set_bufsize(dev);
4194         oom = nv_init_ring(dev);
4195
4196         writel(0, base + NvRegLinkSpeed);
4197         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4198         nv_txrx_reset(dev);
4199         writel(0, base + NvRegUnknownSetupReg6);
4200
4201         np->in_shutdown = 0;
4202
4203         /* give hw rings */
4204         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4205         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4206                 base + NvRegRingSizes);
4207
4208         writel(np->linkspeed, base + NvRegLinkSpeed);
4209         if (np->desc_ver == DESC_VER_1)
4210                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4211         else
4212                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4213         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4214         writel(np->vlanctl_bits, base + NvRegVlanControl);
4215         pci_push(base);
4216         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4217         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4218                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4219                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4220
4221         writel(0, base + NvRegMIIMask);
4222         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4223         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4224
4225         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4226         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4227         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4228         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4229
4230         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4231         get_random_bytes(&i, sizeof(i));
4232         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4233         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4234         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4235         if (poll_interval == -1) {
4236                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4237                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4238                 else
4239                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4240         }
4241         else
4242                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4243         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4244         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4245                         base + NvRegAdapterControl);
4246         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4247         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4248         if (np->wolenabled)
4249                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4250
4251         i = readl(base + NvRegPowerState);
4252         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4253                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4254
4255         pci_push(base);
4256         udelay(10);
4257         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4258
4259         nv_disable_hw_interrupts(dev, np->irqmask);
4260         pci_push(base);
4261         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4262         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4263         pci_push(base);
4264
4265         if (nv_request_irq(dev, 0)) {
4266                 goto out_drain;
4267         }
4268
4269         /* ask for interrupts */
4270         nv_enable_hw_interrupts(dev, np->irqmask);
4271
4272         spin_lock_irq(&np->lock);
4273         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4274         writel(0, base + NvRegMulticastAddrB);
4275         writel(0, base + NvRegMulticastMaskA);
4276         writel(0, base + NvRegMulticastMaskB);
4277         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4278         /* One manual link speed update: Interrupts are enabled, future link
4279          * speed changes cause interrupts and are handled by nv_link_irq().
4280          */
4281         {
4282                 u32 miistat;
4283                 miistat = readl(base + NvRegMIIStatus);
4284                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4285                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4286         }
4287         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4288          * to init hw */
4289         np->linkspeed = 0;
4290         ret = nv_update_linkspeed(dev);
4291         nv_start_rx(dev);
4292         nv_start_tx(dev);
4293         netif_start_queue(dev);
4294         netif_poll_enable(dev);
4295
4296         if (ret) {
4297                 netif_carrier_on(dev);
4298         } else {
4299                 printk("%s: no link during initialization.\n", dev->name);
4300                 netif_carrier_off(dev);
4301         }
4302         if (oom)
4303                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4304
4305         /* start statistics timer */
4306         if (np->driver_data & DEV_HAS_STATISTICS)
4307                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4308
4309         spin_unlock_irq(&np->lock);
4310
4311         return 0;
4312 out_drain:
4313         drain_ring(dev);
4314         return ret;
4315 }
4316
4317 static int nv_close(struct net_device *dev)
4318 {
4319         struct fe_priv *np = netdev_priv(dev);
4320         u8 __iomem *base;
4321
4322         spin_lock_irq(&np->lock);
4323         np->in_shutdown = 1;
4324         spin_unlock_irq(&np->lock);
4325         netif_poll_disable(dev);
4326         synchronize_irq(dev->irq);
4327
4328         del_timer_sync(&np->oom_kick);
4329         del_timer_sync(&np->nic_poll);
4330         del_timer_sync(&np->stats_poll);
4331
4332         netif_stop_queue(dev);
4333         spin_lock_irq(&np->lock);
4334         nv_stop_tx(dev);
4335         nv_stop_rx(dev);
4336         nv_txrx_reset(dev);
4337
4338         /* disable interrupts on the nic or we will lock up */
4339         base = get_hwbase(dev);
4340         nv_disable_hw_interrupts(dev, np->irqmask);
4341         pci_push(base);
4342         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4343
4344         spin_unlock_irq(&np->lock);
4345
4346         nv_free_irq(dev);
4347
4348         drain_ring(dev);
4349
4350         if (np->wolenabled)
4351                 nv_start_rx(dev);
4352
4353         /* FIXME: power down nic */
4354
4355         return 0;
4356 }
4357
4358 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4359 {
4360         struct net_device *dev;
4361         struct fe_priv *np;
4362         unsigned long addr;
4363         u8 __iomem *base;
4364         int err, i;
4365         u32 powerstate, txreg;
4366         u32 phystate_orig = 0, phystate;
4367         int phyinitialized = 0;
4368
4369         dev = alloc_etherdev(sizeof(struct fe_priv));
4370         err = -ENOMEM;
4371         if (!dev)
4372                 goto out;
4373
4374         np = netdev_priv(dev);
4375         np->pci_dev = pci_dev;
4376         spin_lock_init(&np->lock);
4377         SET_MODULE_OWNER(dev);
4378         SET_NETDEV_DEV(dev, &pci_dev->dev);
4379
4380         init_timer(&np->oom_kick);
4381         np->oom_kick.data = (unsigned long) dev;
4382         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4383         init_timer(&np->nic_poll);
4384         np->nic_poll.data = (unsigned long) dev;
4385         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4386         init_timer(&np->stats_poll);
4387         np->stats_poll.data = (unsigned long) dev;
4388         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4389
4390         err = pci_enable_device(pci_dev);
4391         if (err) {
4392                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4393                                 err, pci_name(pci_dev));
4394                 goto out_free;
4395         }
4396
4397         pci_set_master(pci_dev);
4398
4399         err = pci_request_regions(pci_dev, DRV_NAME);
4400         if (err < 0)
4401                 goto out_disable;
4402
4403         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4404                 np->register_size = NV_PCI_REGSZ_VER2;
4405         else
4406                 np->register_size = NV_PCI_REGSZ_VER1;
4407
4408         err = -EINVAL;
4409         addr = 0;
4410         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4411                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4412                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4413                                 pci_resource_len(pci_dev, i),
4414                                 pci_resource_flags(pci_dev, i));
4415                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4416                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4417                         addr = pci_resource_start(pci_dev, i);
4418                         break;
4419                 }
4420         }
4421         if (i == DEVICE_COUNT_RESOURCE) {
4422                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4423                                         pci_name(pci_dev));
4424                 goto out_relreg;
4425         }
4426
4427         /* copy of driver data */
4428         np->driver_data = id->driver_data;
4429
4430         /* handle different descriptor versions */
4431         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4432                 /* packet format 3: supports 40-bit addressing */
4433                 np->desc_ver = DESC_VER_3;
4434                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4435                 if (dma_64bit) {
4436                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4437                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4438                                        pci_name(pci_dev));
4439                         } else {
4440                                 dev->features |= NETIF_F_HIGHDMA;
4441                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4442                         }
4443                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4444                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4445                                        pci_name(pci_dev));
4446                         }
4447                 }
4448         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4449                 /* packet format 2: supports jumbo frames */
4450                 np->desc_ver = DESC_VER_2;
4451                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4452         } else {
4453                 /* original packet format */
4454                 np->desc_ver = DESC_VER_1;
4455                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4456         }
4457
4458         np->pkt_limit = NV_PKTLIMIT_1;
4459         if (id->driver_data & DEV_HAS_LARGEDESC)
4460                 np->pkt_limit = NV_PKTLIMIT_2;
4461
4462         if (id->driver_data & DEV_HAS_CHECKSUM) {
4463                 np->rx_csum = 1;
4464                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4465                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4466 #ifdef NETIF_F_TSO
4467                 dev->features |= NETIF_F_TSO;
4468 #endif
4469         }
4470
4471         np->vlanctl_bits = 0;
4472         if (id->driver_data & DEV_HAS_VLAN) {
4473                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4474                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4475                 dev->vlan_rx_register = nv_vlan_rx_register;
4476                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4477         }
4478
4479         np->msi_flags = 0;
4480         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4481                 np->msi_flags |= NV_MSI_CAPABLE;
4482         }
4483         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4484                 np->msi_flags |= NV_MSI_X_CAPABLE;
4485         }
4486
4487         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4488         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4489                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4490         }
4491
4492
4493         err = -ENOMEM;
4494         np->base = ioremap(addr, np->register_size);
4495         if (!np->base)
4496                 goto out_relreg;
4497         dev->base_addr = (unsigned long)np->base;
4498
4499         dev->irq = pci_dev->irq;
4500
4501         np->rx_ring_size = RX_RING_DEFAULT;
4502         np->tx_ring_size = TX_RING_DEFAULT;
4503         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4504         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4505
4506         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4507                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4508                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4509                                         &np->ring_addr);
4510                 if (!np->rx_ring.orig)
4511                         goto out_unmap;
4512                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4513         } else {
4514                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4515                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4516                                         &np->ring_addr);
4517                 if (!np->rx_ring.ex)
4518                         goto out_unmap;
4519                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4520         }
4521         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4522         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4523         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4524         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4525         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4526         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4527                 goto out_freering;
4528         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4529         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4530         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4531         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4532         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4533
4534         dev->open = nv_open;
4535         dev->stop = nv_close;
4536         dev->hard_start_xmit = nv_start_xmit;
4537         dev->get_stats = nv_get_stats;
4538         dev->change_mtu = nv_change_mtu;
4539         dev->set_mac_address = nv_set_mac_address;
4540         dev->set_multicast_list = nv_set_multicast;
4541 #ifdef CONFIG_NET_POLL_CONTROLLER
4542         dev->poll_controller = nv_poll_controller;
4543 #endif
4544         dev->weight = 64;
4545 #ifdef CONFIG_FORCEDETH_NAPI
4546         dev->poll = nv_napi_poll;
4547 #endif
4548         SET_ETHTOOL_OPS(dev, &ops);
4549         dev->tx_timeout = nv_tx_timeout;
4550         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4551
4552         pci_set_drvdata(pci_dev, dev);
4553
4554         /* read the mac address */
4555         base = get_hwbase(dev);
4556         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4557         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4558
4559         /* check the workaround bit for correct mac address order */
4560         txreg = readl(base + NvRegTransmitPoll);
4561         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4562                 /* mac address is already in correct order */
4563                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4564                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4565                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4566                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4567                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4568                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4569         } else {
4570                 /* need to reverse mac address to correct order */
4571                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4572                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4573                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4574                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4575                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4576                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4577                 /* set permanent address to be correct aswell */
4578                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4579                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4580                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4581                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4582         }
4583         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4584
4585         if (!is_valid_ether_addr(dev->perm_addr)) {
4586                 /*
4587                  * Bad mac address. At least one bios sets the mac address
4588                  * to 01:23:45:67:89:ab
4589                  */
4590                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4591                         pci_name(pci_dev),
4592                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4593                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4594                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4595                 dev->dev_addr[0] = 0x00;
4596                 dev->dev_addr[1] = 0x00;
4597                 dev->dev_addr[2] = 0x6c;
4598                 get_random_bytes(&dev->dev_addr[3], 3);
4599         }
4600
4601         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4602                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4603                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4604
4605         /* set mac address */
4606         nv_copy_mac_to_hw(dev);
4607
4608         /* disable WOL */
4609         writel(0, base + NvRegWakeUpFlags);
4610         np->wolenabled = 0;
4611
4612         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4613                 u8 revision_id;
4614                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4615
4616                 /* take phy and nic out of low power mode */
4617                 powerstate = readl(base + NvRegPowerState2);
4618                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4619                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4620                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4621                     revision_id >= 0xA3)
4622                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4623                 writel(powerstate, base + NvRegPowerState2);
4624         }
4625
4626         if (np->desc_ver == DESC_VER_1) {
4627                 np->tx_flags = NV_TX_VALID;
4628         } else {
4629                 np->tx_flags = NV_TX2_VALID;
4630         }
4631         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4632                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4633                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4634                         np->msi_flags |= 0x0003;
4635         } else {
4636                 np->irqmask = NVREG_IRQMASK_CPU;
4637                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4638                         np->msi_flags |= 0x0001;
4639         }
4640
4641         if (id->driver_data & DEV_NEED_TIMERIRQ)
4642                 np->irqmask |= NVREG_IRQ_TIMER;
4643         if (id->driver_data & DEV_NEED_LINKTIMER) {
4644                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4645                 np->need_linktimer = 1;
4646                 np->link_timeout = jiffies + LINK_TIMEOUT;
4647         } else {
4648                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4649                 np->need_linktimer = 0;
4650         }
4651
4652         /* clear phy state and temporarily halt phy interrupts */
4653         writel(0, base + NvRegMIIMask);
4654         phystate = readl(base + NvRegAdapterControl);
4655         if (phystate & NVREG_ADAPTCTL_RUNNING) {
4656                 phystate_orig = 1;
4657                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4658                 writel(phystate, base + NvRegAdapterControl);
4659         }
4660         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4661
4662         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4663                 writel(0x1, base + 0x204); pci_push(base);
4664                 msleep(500);
4665                 /* management unit running on the mac? */
4666                 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4667                 if (np->mac_in_use) {
4668                         u32 mgmt_sync;
4669                         /* management unit setup the phy already? */
4670                         mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4671                         if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
4672                                 if (!nv_mgmt_acquire_sema(dev)) {
4673                                         for (i = 0; i < 5000; i++) {
4674                                                 msleep(1);
4675                                                 mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
4676                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
4677                                                         continue;
4678                                                 if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT)
4679                                                         phyinitialized = 1;
4680                                                 break;
4681                                         }
4682                                 } else {
4683                                         /* we need to init the phy */
4684                                 }
4685                         } else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
4686                                 /* phy is inited by SMU */
4687                                 phyinitialized = 1;
4688                         } else {
4689                                 /* we need to init the phy */
4690                         }
4691                 }
4692         }
4693
4694         /* find a suitable phy */
4695         for (i = 1; i <= 32; i++) {
4696                 int id1, id2;
4697                 int phyaddr = i & 0x1F;
4698
4699                 spin_lock_irq(&np->lock);
4700                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4701                 spin_unlock_irq(&np->lock);
4702                 if (id1 < 0 || id1 == 0xffff)
4703                         continue;
4704                 spin_lock_irq(&np->lock);
4705                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4706                 spin_unlock_irq(&np->lock);
4707                 if (id2 < 0 || id2 == 0xffff)
4708                         continue;
4709
4710                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4711                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4712                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4713                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4714                         pci_name(pci_dev), id1, id2, phyaddr);
4715                 np->phyaddr = phyaddr;
4716                 np->phy_oui = id1 | id2;
4717                 break;
4718         }
4719         if (i == 33) {
4720                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4721                        pci_name(pci_dev));
4722                 goto out_error;
4723         }
4724
4725         if (!phyinitialized) {
4726                 /* reset it */
4727                 phy_init(dev);
4728         }
4729
4730         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4731                 nv_mgmt_driver_loaded(dev, 1);
4732         }
4733
4734         /* set default link speed settings */
4735         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4736         np->duplex = 0;
4737         np->autoneg = 1;
4738
4739         err = register_netdev(dev);
4740         if (err) {
4741                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4742                 goto out_error;
4743         }
4744         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4745                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4746                         pci_name(pci_dev));
4747
4748         return 0;
4749
4750 out_error:
4751         if (phystate_orig)
4752                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4753         if (np->mac_in_use)
4754                 nv_mgmt_driver_loaded(dev, 0);
4755         pci_set_drvdata(pci_dev, NULL);
4756 out_freering:
4757         free_rings(dev);
4758 out_unmap:
4759         iounmap(get_hwbase(dev));
4760 out_relreg:
4761         pci_release_regions(pci_dev);
4762 out_disable:
4763         pci_disable_device(pci_dev);
4764 out_free:
4765         free_netdev(dev);
4766 out:
4767         return err;
4768 }
4769
4770 static void __devexit nv_remove(struct pci_dev *pci_dev)
4771 {
4772         struct net_device *dev = pci_get_drvdata(pci_dev);
4773         struct fe_priv *np = netdev_priv(dev);
4774         u8 __iomem *base = get_hwbase(dev);
4775
4776         unregister_netdev(dev);
4777
4778         /* special op: write back the misordered MAC address - otherwise
4779          * the next nv_probe would see a wrong address.
4780          */
4781         writel(np->orig_mac[0], base + NvRegMacAddrA);
4782         writel(np->orig_mac[1], base + NvRegMacAddrB);
4783
4784         if (np->mac_in_use)
4785                 nv_mgmt_driver_loaded(dev, 0);
4786
4787         /* free all structures */
4788         free_rings(dev);
4789         iounmap(get_hwbase(dev));
4790         pci_release_regions(pci_dev);
4791         pci_disable_device(pci_dev);
4792         free_netdev(dev);
4793         pci_set_drvdata(pci_dev, NULL);
4794 }
4795
4796 #ifdef CONFIG_PM
4797 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4798 {
4799         struct net_device *dev = pci_get_drvdata(pdev);
4800         struct fe_priv *np = netdev_priv(dev);
4801
4802         if (!netif_running(dev))
4803                 goto out;
4804
4805         netif_device_detach(dev);
4806
4807         // Gross.
4808         nv_close(dev);
4809
4810         pci_save_state(pdev);
4811         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4812         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4813 out:
4814         return 0;
4815 }
4816
4817 static int nv_resume(struct pci_dev *pdev)
4818 {
4819         struct net_device *dev = pci_get_drvdata(pdev);
4820         int rc = 0;
4821
4822         if (!netif_running(dev))
4823                 goto out;
4824
4825         netif_device_attach(dev);
4826
4827         pci_set_power_state(pdev, PCI_D0);
4828         pci_restore_state(pdev);
4829         pci_enable_wake(pdev, PCI_D0, 0);
4830
4831         rc = nv_open(dev);
4832 out:
4833         return rc;
4834 }
4835 #else
4836 #define nv_suspend NULL
4837 #define nv_resume NULL
4838 #endif /* CONFIG_PM */
4839
4840 static struct pci_device_id pci_tbl[] = {
4841         {       /* nForce Ethernet Controller */
4842                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4843                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4844         },
4845         {       /* nForce2 Ethernet Controller */
4846                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4847                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4848         },
4849         {       /* nForce3 Ethernet Controller */
4850                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4851                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4852         },
4853         {       /* nForce3 Ethernet Controller */
4854                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4855                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4856         },
4857         {       /* nForce3 Ethernet Controller */
4858                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4859                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4860         },
4861         {       /* nForce3 Ethernet Controller */
4862                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4863                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4864         },
4865         {       /* nForce3 Ethernet Controller */
4866                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4867                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4868         },
4869         {       /* CK804 Ethernet Controller */
4870                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4871                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4872         },
4873         {       /* CK804 Ethernet Controller */
4874                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4875                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4876         },
4877         {       /* MCP04 Ethernet Controller */
4878                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4879                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4880         },
4881         {       /* MCP04 Ethernet Controller */
4882                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4883                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4884         },
4885         {       /* MCP51 Ethernet Controller */
4886                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4887                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4888         },
4889         {       /* MCP51 Ethernet Controller */
4890                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4891                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4892         },
4893         {       /* MCP55 Ethernet Controller */
4894                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4895                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4896         },
4897         {       /* MCP55 Ethernet Controller */
4898                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4899                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4900         },
4901         {       /* MCP61 Ethernet Controller */
4902                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4903                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4904         },
4905         {       /* MCP61 Ethernet Controller */
4906                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4907                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4908         },
4909         {       /* MCP61 Ethernet Controller */
4910                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4911                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4912         },
4913         {       /* MCP61 Ethernet Controller */
4914                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4915                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4916         },
4917         {       /* MCP65 Ethernet Controller */
4918                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4919                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4920         },
4921         {       /* MCP65 Ethernet Controller */
4922                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4923                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4924         },
4925         {       /* MCP65 Ethernet Controller */
4926                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4927                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4928         },
4929         {       /* MCP65 Ethernet Controller */
4930                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4931                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4932         },
4933         {       /* MCP67 Ethernet Controller */
4934                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
4935                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4936         },
4937         {       /* MCP67 Ethernet Controller */
4938                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
4939                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4940         },
4941         {       /* MCP67 Ethernet Controller */
4942                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
4943                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4944         },
4945         {       /* MCP67 Ethernet Controller */
4946                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
4947                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4948         },
4949         {0,},
4950 };
4951
4952 static struct pci_driver driver = {
4953         .name = "forcedeth",
4954         .id_table = pci_tbl,
4955         .probe = nv_probe,
4956         .remove = __devexit_p(nv_remove),
4957         .suspend = nv_suspend,
4958         .resume = nv_resume,
4959 };
4960
4961 static int __init init_nic(void)
4962 {
4963         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4964         return pci_register_driver(&driver);
4965 }
4966
4967 static void __exit exit_nic(void)
4968 {
4969         pci_unregister_driver(&driver);
4970 }
4971
4972 module_param(max_interrupt_work, int, 0);
4973 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4974 module_param(optimization_mode, int, 0);
4975 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4976 module_param(poll_interval, int, 0);
4977 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4978 module_param(msi, int, 0);
4979 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4980 module_param(msix, int, 0);
4981 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4982 module_param(dma_64bit, int, 0);
4983 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4984
4985 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4986 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4987 MODULE_LICENSE("GPL");
4988
4989 MODULE_DEVICE_TABLE(pci, pci_tbl);
4990
4991 module_init(init_nic);
4992 module_exit(exit_nic);