drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.64"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/timer.h>
  55 #include <linux/skbuff.h>
  56 #include <linux/mii.h>
  57 #include <linux/random.h>
  58 #include <linux/init.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/dma-mapping.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/io.h>
  64 #include <asm/uaccess.h>
  65 #include <asm/system.h>
  66
  67 #if 0
  68 #define dprintk                 printk
  69 #else
  70 #define dprintk(x...)           do { } while (0)
  71 #endif
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  93 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  94 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  95 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
  99 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 100 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 101 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 102 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 103 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 104 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 105
 106 enum {
 107         NvRegIrqStatus = 0x000,
 108 #define NVREG_IRQSTAT_MIIEVENT  0x040
 109 #define NVREG_IRQSTAT_MASK              0x83ff
 110         NvRegIrqMask = 0x004,
 111 #define NVREG_IRQ_RX_ERROR              0x0001
 112 #define NVREG_IRQ_RX                    0x0002
 113 #define NVREG_IRQ_RX_NOBUF              0x0004
 114 #define NVREG_IRQ_TX_ERR                0x0008
 115 #define NVREG_IRQ_TX_OK                 0x0010
 116 #define NVREG_IRQ_TIMER                 0x0020
 117 #define NVREG_IRQ_LINK                  0x0040
 118 #define NVREG_IRQ_RX_FORCED             0x0080
 119 #define NVREG_IRQ_TX_FORCED             0x0100
 120 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 121 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 122 #define NVREG_IRQMASK_CPU               0x0060
 123 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 124 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 125 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 126
 127         NvRegUnknownSetupReg6 = 0x008,
 128 #define NVREG_UNKSETUP6_VAL             3
 129
 130 /*
 131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 133  */
 134         NvRegPollingInterval = 0x00c,
 135 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 136 #define NVREG_POLL_DEFAULT_CPU  13
 137         NvRegMSIMap0 = 0x020,
 138         NvRegMSIMap1 = 0x024,
 139         NvRegMSIIrqMask = 0x030,
 140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 141         NvRegMisc1 = 0x080,
 142 #define NVREG_MISC1_PAUSE_TX    0x01
 143 #define NVREG_MISC1_HD          0x02
 144 #define NVREG_MISC1_FORCE       0x3b0f3c
 145
 146         NvRegMacReset = 0x34,
 147 #define NVREG_MAC_RESET_ASSERT  0x0F3
 148         NvRegTransmitterControl = 0x084,
 149 #define NVREG_XMITCTL_START     0x01
 150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 160 #define NVREG_XMITCTL_DATA_START        0x00100000
 161 #define NVREG_XMITCTL_DATA_READY        0x00010000
 162 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 163         NvRegTransmitterStatus = 0x088,
 164 #define NVREG_XMITSTAT_BUSY     0x01
 165
 166         NvRegPacketFilterFlags = 0x8c,
 167 #define NVREG_PFF_PAUSE_RX      0x08
 168 #define NVREG_PFF_ALWAYS        0x7F0000
 169 #define NVREG_PFF_PROMISC       0x80
 170 #define NVREG_PFF_MYADDR        0x20
 171 #define NVREG_PFF_LOOPBACK      0x10
 172
 173         NvRegOffloadConfig = 0x90,
 174 #define NVREG_OFFLOAD_HOMEPHY   0x601
 175 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 176         NvRegReceiverControl = 0x094,
 177 #define NVREG_RCVCTL_START      0x01
 178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 179         NvRegReceiverStatus = 0x98,
 180 #define NVREG_RCVSTAT_BUSY      0x01
 181
 182         NvRegSlotTime = 0x9c,
 183 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 184 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 185 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 186 #define NVREG_SLOTTIME_HALF             0x0000ff00
 187 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 188 #define NVREG_SLOTTIME_MASK             0x000000ff
 189
 190         NvRegTxDeferral = 0xA0,
 191 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 192 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 193 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 196 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 197         NvRegRxDeferral = 0xA4,
 198 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 199         NvRegMacAddrA = 0xA8,
 200         NvRegMacAddrB = 0xAC,
 201         NvRegMulticastAddrA = 0xB0,
 202 #define NVREG_MCASTADDRA_FORCE  0x01
 203         NvRegMulticastAddrB = 0xB4,
 204         NvRegMulticastMaskA = 0xB8,
 205 #define NVREG_MCASTMASKA_NONE           0xffffffff
 206         NvRegMulticastMaskB = 0xBC,
 207 #define NVREG_MCASTMASKB_NONE           0xffff
 208
 209         NvRegPhyInterface = 0xC0,
 210 #define PHY_RGMII               0x10000000
 211         NvRegBackOffControl = 0xC4,
 212 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 213 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 214 #define NVREG_BKOFFCTRL_SELECT                  24
 215 #define NVREG_BKOFFCTRL_GEAR                    12
 216
 217         NvRegTxRingPhysAddr = 0x100,
 218         NvRegRxRingPhysAddr = 0x104,
 219         NvRegRingSizes = 0x108,
 220 #define NVREG_RINGSZ_TXSHIFT 0
 221 #define NVREG_RINGSZ_RXSHIFT 16
 222         NvRegTransmitPoll = 0x10c,
 223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 224         NvRegLinkSpeed = 0x110,
 225 #define NVREG_LINKSPEED_FORCE 0x10000
 226 #define NVREG_LINKSPEED_10      1000
 227 #define NVREG_LINKSPEED_100     100
 228 #define NVREG_LINKSPEED_1000    50
 229 #define NVREG_LINKSPEED_MASK    (0xFFF)
 230         NvRegUnknownSetupReg5 = 0x130,
 231 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 232         NvRegTxWatermark = 0x13c,
 233 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 234 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 235 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 236         NvRegTxRxControl = 0x144,
 237 #define NVREG_TXRXCTL_KICK      0x0001
 238 #define NVREG_TXRXCTL_BIT1      0x0002
 239 #define NVREG_TXRXCTL_BIT2      0x0004
 240 #define NVREG_TXRXCTL_IDLE      0x0008
 241 #define NVREG_TXRXCTL_RESET     0x0010
 242 #define NVREG_TXRXCTL_RXCHECK   0x0400
 243 #define NVREG_TXRXCTL_DESC_1    0
 244 #define NVREG_TXRXCTL_DESC_2    0x002100
 245 #define NVREG_TXRXCTL_DESC_3    0xc02200
 246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 247 #define NVREG_TXRXCTL_VLANINS   0x00080
 248         NvRegTxRingPhysAddrHigh = 0x148,
 249         NvRegRxRingPhysAddrHigh = 0x14C,
 250         NvRegTxPauseFrame = 0x170,
 251 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 255         NvRegTxPauseFrameLimit = 0x174,
 256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 257         NvRegMIIStatus = 0x180,
 258 #define NVREG_MIISTAT_ERROR             0x0001
 259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 260 #define NVREG_MIISTAT_MASK_RW           0x0007
 261 #define NVREG_MIISTAT_MASK_ALL          0x000f
 262         NvRegMIIMask = 0x184,
 263 #define NVREG_MII_LINKCHANGE            0x0008
 264
 265         NvRegAdapterControl = 0x188,
 266 #define NVREG_ADAPTCTL_START    0x02
 267 #define NVREG_ADAPTCTL_LINKUP   0x04
 268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 269 #define NVREG_ADAPTCTL_RUNNING  0x100000
 270 #define NVREG_ADAPTCTL_PHYSHIFT 24
 271         NvRegMIISpeed = 0x18c,
 272 #define NVREG_MIISPEED_BIT8     (1<<8)
 273 #define NVREG_MIIDELAY  5
 274         NvRegMIIControl = 0x190,
 275 #define NVREG_MIICTL_INUSE      0x08000
 276 #define NVREG_MIICTL_WRITE      0x00400
 277 #define NVREG_MIICTL_ADDRSHIFT  5
 278         NvRegMIIData = 0x194,
 279         NvRegTxUnicast = 0x1a0,
 280         NvRegTxMulticast = 0x1a4,
 281         NvRegTxBroadcast = 0x1a8,
 282         NvRegWakeUpFlags = 0x200,
 283 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 286 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 287 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 288 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 289 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 293 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 294
 295         NvRegMgmtUnitGetVersion = 0x204,
 296 #define NVREG_MGMTUNITGETVERSION        0x01
 297         NvRegMgmtUnitVersion = 0x208,
 298 #define NVREG_MGMTUNITVERSION           0x08
 299         NvRegPowerCap = 0x268,
 300 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 301 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 302 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 303         NvRegPowerState = 0x26c,
 304 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 305 #define NVREG_POWERSTATE_VALID          0x0100
 306 #define NVREG_POWERSTATE_MASK           0x0003
 307 #define NVREG_POWERSTATE_D0             0x0000
 308 #define NVREG_POWERSTATE_D1             0x0001
 309 #define NVREG_POWERSTATE_D2             0x0002
 310 #define NVREG_POWERSTATE_D3             0x0003
 311         NvRegMgmtUnitControl = 0x278,
 312 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 313         NvRegTxCnt = 0x280,
 314         NvRegTxZeroReXmt = 0x284,
 315         NvRegTxOneReXmt = 0x288,
 316         NvRegTxManyReXmt = 0x28c,
 317         NvRegTxLateCol = 0x290,
 318         NvRegTxUnderflow = 0x294,
 319         NvRegTxLossCarrier = 0x298,
 320         NvRegTxExcessDef = 0x29c,
 321         NvRegTxRetryErr = 0x2a0,
 322         NvRegRxFrameErr = 0x2a4,
 323         NvRegRxExtraByte = 0x2a8,
 324         NvRegRxLateCol = 0x2ac,
 325         NvRegRxRunt = 0x2b0,
 326         NvRegRxFrameTooLong = 0x2b4,
 327         NvRegRxOverflow = 0x2b8,
 328         NvRegRxFCSErr = 0x2bc,
 329         NvRegRxFrameAlignErr = 0x2c0,
 330         NvRegRxLenErr = 0x2c4,
 331         NvRegRxUnicast = 0x2c8,
 332         NvRegRxMulticast = 0x2cc,
 333         NvRegRxBroadcast = 0x2d0,
 334         NvRegTxDef = 0x2d4,
 335         NvRegTxFrame = 0x2d8,
 336         NvRegRxCnt = 0x2dc,
 337         NvRegTxPause = 0x2e0,
 338         NvRegRxPause = 0x2e4,
 339         NvRegRxDropFrame = 0x2e8,
 340         NvRegVlanControl = 0x300,
 341 #define NVREG_VLANCONTROL_ENABLE        0x2000
 342         NvRegMSIXMap0 = 0x3e0,
 343         NvRegMSIXMap1 = 0x3e4,
 344         NvRegMSIXIrqStatus = 0x3f0,
 345
 346         NvRegPowerState2 = 0x600,
 347 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 348 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 349 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 350 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 351 };
 352
 353 /* Big endian: should work, but is untested */
 354 struct ring_desc {
 355         __le32 buf;
 356         __le32 flaglen;
 357 };
 358
 359 struct ring_desc_ex {
 360         __le32 bufhigh;
 361         __le32 buflow;
 362         __le32 txvlan;
 363         __le32 flaglen;
 364 };
 365
 366 union ring_type {
 367         struct ring_desc* orig;
 368         struct ring_desc_ex* ex;
 369 };
 370
 371 #define FLAG_MASK_V1 0xffff0000
 372 #define FLAG_MASK_V2 0xffffc000
 373 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 374 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 375
 376 #define NV_TX_LASTPACKET        (1<<16)
 377 #define NV_TX_RETRYERROR        (1<<19)
 378 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 379 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 380 #define NV_TX_DEFERRED          (1<<26)
 381 #define NV_TX_CARRIERLOST       (1<<27)
 382 #define NV_TX_LATECOLLISION     (1<<28)
 383 #define NV_TX_UNDERFLOW         (1<<29)
 384 #define NV_TX_ERROR             (1<<30)
 385 #define NV_TX_VALID             (1<<31)
 386
 387 #define NV_TX2_LASTPACKET       (1<<29)
 388 #define NV_TX2_RETRYERROR       (1<<18)
 389 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 390 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 391 #define NV_TX2_DEFERRED         (1<<25)
 392 #define NV_TX2_CARRIERLOST      (1<<26)
 393 #define NV_TX2_LATECOLLISION    (1<<27)
 394 #define NV_TX2_UNDERFLOW        (1<<28)
 395 /* error and valid are the same for both */
 396 #define NV_TX2_ERROR            (1<<30)
 397 #define NV_TX2_VALID            (1<<31)
 398 #define NV_TX2_TSO              (1<<28)
 399 #define NV_TX2_TSO_SHIFT        14
 400 #define NV_TX2_TSO_MAX_SHIFT    14
 401 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 402 #define NV_TX2_CHECKSUM_L3      (1<<27)
 403 #define NV_TX2_CHECKSUM_L4      (1<<26)
 404
 405 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 406
 407 #define NV_RX_DESCRIPTORVALID   (1<<16)
 408 #define NV_RX_MISSEDFRAME       (1<<17)
 409 #define NV_RX_SUBSTRACT1        (1<<18)
 410 #define NV_RX_ERROR1            (1<<23)
 411 #define NV_RX_ERROR2            (1<<24)
 412 #define NV_RX_ERROR3            (1<<25)
 413 #define NV_RX_ERROR4            (1<<26)
 414 #define NV_RX_CRCERR            (1<<27)
 415 #define NV_RX_OVERFLOW          (1<<28)
 416 #define NV_RX_FRAMINGERR        (1<<29)
 417 #define NV_RX_ERROR             (1<<30)
 418 #define NV_RX_AVAIL             (1<<31)
 419 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 420
 421 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 422 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 423 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 424 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 425 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 426 #define NV_RX2_SUBSTRACT1       (1<<25)
 427 #define NV_RX2_ERROR1           (1<<18)
 428 #define NV_RX2_ERROR2           (1<<19)
 429 #define NV_RX2_ERROR3           (1<<20)
 430 #define NV_RX2_ERROR4           (1<<21)
 431 #define NV_RX2_CRCERR           (1<<22)
 432 #define NV_RX2_OVERFLOW         (1<<23)
 433 #define NV_RX2_FRAMINGERR       (1<<24)
 434 /* error and avail are the same for both */
 435 #define NV_RX2_ERROR            (1<<30)
 436 #define NV_RX2_AVAIL            (1<<31)
 437 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 438
 439 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 440 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 441
 442 /* Miscelaneous hardware related defines: */
 443 #define NV_PCI_REGSZ_VER1       0x270
 444 #define NV_PCI_REGSZ_VER2       0x2d4
 445 #define NV_PCI_REGSZ_VER3       0x604
 446 #define NV_PCI_REGSZ_MAX        0x604
 447
 448 /* various timeout delays: all in usec */
 449 #define NV_TXRX_RESET_DELAY     4
 450 #define NV_TXSTOP_DELAY1        10
 451 #define NV_TXSTOP_DELAY1MAX     500000
 452 #define NV_TXSTOP_DELAY2        100
 453 #define NV_RXSTOP_DELAY1        10
 454 #define NV_RXSTOP_DELAY1MAX     500000
 455 #define NV_RXSTOP_DELAY2        100
 456 #define NV_SETUP5_DELAY         5
 457 #define NV_SETUP5_DELAYMAX      50000
 458 #define NV_POWERUP_DELAY        5
 459 #define NV_POWERUP_DELAYMAX     5000
 460 #define NV_MIIBUSY_DELAY        50
 461 #define NV_MIIPHY_DELAY 10
 462 #define NV_MIIPHY_DELAYMAX      10000
 463 #define NV_MAC_RESET_DELAY      64
 464
 465 #define NV_WAKEUPPATTERNS       5
 466 #define NV_WAKEUPMASKENTRIES    4
 467
 468 /* General driver defaults */
 469 #define NV_WATCHDOG_TIMEO       (5*HZ)
 470
 471 #define RX_RING_DEFAULT         512
 472 #define TX_RING_DEFAULT         256
 473 #define RX_RING_MIN             128
 474 #define TX_RING_MIN             64
 475 #define RING_MAX_DESC_VER_1     1024
 476 #define RING_MAX_DESC_VER_2_3   16384
 477
 478 /* rx/tx mac addr + type + vlan + align + slack*/
 479 #define NV_RX_HEADERS           (64)
 480 /* even more slack. */
 481 #define NV_RX_ALLOC_PAD         (64)
 482
 483 /* maximum mtu size */
 484 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 485 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 486
 487 #define OOM_REFILL      (1+HZ/20)
 488 #define POLL_WAIT       (1+HZ/100)
 489 #define LINK_TIMEOUT    (3*HZ)
 490 #define STATS_INTERVAL  (10*HZ)
 491
 492 /*
 493  * desc_ver values:
 494  * The nic supports three different descriptor types:
 495  * - DESC_VER_1: Original
 496  * - DESC_VER_2: support for jumbo frames.
 497  * - DESC_VER_3: 64-bit format.
 498  */
 499 #define DESC_VER_1      1
 500 #define DESC_VER_2      2
 501 #define DESC_VER_3      3
 502
 503 /* PHY defines */
 504 #define PHY_OUI_MARVELL         0x5043
 505 #define PHY_OUI_CICADA          0x03f1
 506 #define PHY_OUI_VITESSE         0x01c1
 507 #define PHY_OUI_REALTEK         0x0732
 508 #define PHY_OUI_REALTEK2        0x0020
 509 #define PHYID1_OUI_MASK 0x03ff
 510 #define PHYID1_OUI_SHFT 6
 511 #define PHYID2_OUI_MASK 0xfc00
 512 #define PHYID2_OUI_SHFT 10
 513 #define PHYID2_MODEL_MASK               0x03f0
 514 #define PHY_MODEL_REALTEK_8211          0x0110
 515 #define PHY_REV_MASK                    0x0001
 516 #define PHY_REV_REALTEK_8211B           0x0000
 517 #define PHY_REV_REALTEK_8211C           0x0001
 518 #define PHY_MODEL_REALTEK_8201          0x0200
 519 #define PHY_MODEL_MARVELL_E3016         0x0220
 520 #define PHY_MARVELL_E3016_INITMASK      0x0300
 521 #define PHY_CICADA_INIT1        0x0f000
 522 #define PHY_CICADA_INIT2        0x0e00
 523 #define PHY_CICADA_INIT3        0x01000
 524 #define PHY_CICADA_INIT4        0x0200
 525 #define PHY_CICADA_INIT5        0x0004
 526 #define PHY_CICADA_INIT6        0x02000
 527 #define PHY_VITESSE_INIT_REG1   0x1f
 528 #define PHY_VITESSE_INIT_REG2   0x10
 529 #define PHY_VITESSE_INIT_REG3   0x11
 530 #define PHY_VITESSE_INIT_REG4   0x12
 531 #define PHY_VITESSE_INIT_MSK1   0xc
 532 #define PHY_VITESSE_INIT_MSK2   0x0180
 533 #define PHY_VITESSE_INIT1       0x52b5
 534 #define PHY_VITESSE_INIT2       0xaf8a
 535 #define PHY_VITESSE_INIT3       0x8
 536 #define PHY_VITESSE_INIT4       0x8f8a
 537 #define PHY_VITESSE_INIT5       0xaf86
 538 #define PHY_VITESSE_INIT6       0x8f86
 539 #define PHY_VITESSE_INIT7       0xaf82
 540 #define PHY_VITESSE_INIT8       0x0100
 541 #define PHY_VITESSE_INIT9       0x8f82
 542 #define PHY_VITESSE_INIT10      0x0
 543 #define PHY_REALTEK_INIT_REG1   0x1f
 544 #define PHY_REALTEK_INIT_REG2   0x19
 545 #define PHY_REALTEK_INIT_REG3   0x13
 546 #define PHY_REALTEK_INIT_REG4   0x14
 547 #define PHY_REALTEK_INIT_REG5   0x18
 548 #define PHY_REALTEK_INIT_REG6   0x11
 549 #define PHY_REALTEK_INIT_REG7   0x01
 550 #define PHY_REALTEK_INIT1       0x0000
 551 #define PHY_REALTEK_INIT2       0x8e00
 552 #define PHY_REALTEK_INIT3       0x0001
 553 #define PHY_REALTEK_INIT4       0xad17
 554 #define PHY_REALTEK_INIT5       0xfb54
 555 #define PHY_REALTEK_INIT6       0xf5c7
 556 #define PHY_REALTEK_INIT7       0x1000
 557 #define PHY_REALTEK_INIT8       0x0003
 558 #define PHY_REALTEK_INIT9       0x0008
 559 #define PHY_REALTEK_INIT10      0x0005
 560 #define PHY_REALTEK_INIT11      0x0200
 561 #define PHY_REALTEK_INIT_MSK1   0x0003
 562
 563 #define PHY_GIGABIT     0x0100
 564
 565 #define PHY_TIMEOUT     0x1
 566 #define PHY_ERROR       0x2
 567
 568 #define PHY_100 0x1
 569 #define PHY_1000        0x2
 570 #define PHY_HALF        0x100
 571
 572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 574 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 575 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 576 #define NV_PAUSEFRAME_RX_REQ     0x0010
 577 #define NV_PAUSEFRAME_TX_REQ     0x0020
 578 #define NV_PAUSEFRAME_AUTONEG    0x0040
 579
 580 /* MSI/MSI-X defines */
 581 #define NV_MSI_X_MAX_VECTORS  8
 582 #define NV_MSI_X_VECTORS_MASK 0x000f
 583 #define NV_MSI_CAPABLE        0x0010
 584 #define NV_MSI_X_CAPABLE      0x0020
 585 #define NV_MSI_ENABLED        0x0040
 586 #define NV_MSI_X_ENABLED      0x0080
 587
 588 #define NV_MSI_X_VECTOR_ALL   0x0
 589 #define NV_MSI_X_VECTOR_RX    0x0
 590 #define NV_MSI_X_VECTOR_TX    0x1
 591 #define NV_MSI_X_VECTOR_OTHER 0x2
 592
 593 #define NV_MSI_PRIV_OFFSET 0x68
 594 #define NV_MSI_PRIV_VALUE  0xffffffff
 595
 596 #define NV_RESTART_TX         0x1
 597 #define NV_RESTART_RX         0x2
 598
 599 #define NV_TX_LIMIT_COUNT     16
 600
 601 #define NV_DYNAMIC_THRESHOLD        4
 602 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 603
 604 /* statistics */
 605 struct nv_ethtool_str {
 606         char name[ETH_GSTRING_LEN];
 607 };
 608
 609 static const struct nv_ethtool_str nv_estats_str[] = {
 610         { "tx_bytes" },
 611         { "tx_zero_rexmt" },
 612         { "tx_one_rexmt" },
 613         { "tx_many_rexmt" },
 614         { "tx_late_collision" },
 615         { "tx_fifo_errors" },
 616         { "tx_carrier_errors" },
 617         { "tx_excess_deferral" },
 618         { "tx_retry_error" },
 619         { "rx_frame_error" },
 620         { "rx_extra_byte" },
 621         { "rx_late_collision" },
 622         { "rx_runt" },
 623         { "rx_frame_too_long" },
 624         { "rx_over_errors" },
 625         { "rx_crc_errors" },
 626         { "rx_frame_align_error" },
 627         { "rx_length_error" },
 628         { "rx_unicast" },
 629         { "rx_multicast" },
 630         { "rx_broadcast" },
 631         { "rx_packets" },
 632         { "rx_errors_total" },
 633         { "tx_errors_total" },
 634
 635         /* version 2 stats */
 636         { "tx_deferral" },
 637         { "tx_packets" },
 638         { "rx_bytes" },
 639         { "tx_pause" },
 640         { "rx_pause" },
 641         { "rx_drop_frame" },
 642
 643         /* version 3 stats */
 644         { "tx_unicast" },
 645         { "tx_multicast" },
 646         { "tx_broadcast" }
 647 };
 648
 649 struct nv_ethtool_stats {
 650         u64 tx_bytes;
 651         u64 tx_zero_rexmt;
 652         u64 tx_one_rexmt;
 653         u64 tx_many_rexmt;
 654         u64 tx_late_collision;
 655         u64 tx_fifo_errors;
 656         u64 tx_carrier_errors;
 657         u64 tx_excess_deferral;
 658         u64 tx_retry_error;
 659         u64 rx_frame_error;
 660         u64 rx_extra_byte;
 661         u64 rx_late_collision;
 662         u64 rx_runt;
 663         u64 rx_frame_too_long;
 664         u64 rx_over_errors;
 665         u64 rx_crc_errors;
 666         u64 rx_frame_align_error;
 667         u64 rx_length_error;
 668         u64 rx_unicast;
 669         u64 rx_multicast;
 670         u64 rx_broadcast;
 671         u64 rx_packets;
 672         u64 rx_errors_total;
 673         u64 tx_errors_total;
 674
 675         /* version 2 stats */
 676         u64 tx_deferral;
 677         u64 tx_packets;
 678         u64 rx_bytes;
 679         u64 tx_pause;
 680         u64 rx_pause;
 681         u64 rx_drop_frame;
 682
 683         /* version 3 stats */
 684         u64 tx_unicast;
 685         u64 tx_multicast;
 686         u64 tx_broadcast;
 687 };
 688
 689 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 690 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 691 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 692
 693 /* diagnostics */
 694 #define NV_TEST_COUNT_BASE 3
 695 #define NV_TEST_COUNT_EXTENDED 4
 696
 697 static const struct nv_ethtool_str nv_etests_str[] = {
 698         { "link      (online/offline)" },
 699         { "register  (offline)       " },
 700         { "interrupt (offline)       " },
 701         { "loopback  (offline)       " }
 702 };
 703
 704 struct register_test {
 705         __u32 reg;
 706         __u32 mask;
 707 };
 708
 709 static const struct register_test nv_registers_test[] = {
 710         { NvRegUnknownSetupReg6, 0x01 },
 711         { NvRegMisc1, 0x03c },
 712         { NvRegOffloadConfig, 0x03ff },
 713         { NvRegMulticastAddrA, 0xffffffff },
 714         { NvRegTxWatermark, 0x0ff },
 715         { NvRegWakeUpFlags, 0x07777 },
 716         { 0,0 }
 717 };
 718
 719 struct nv_skb_map {
 720         struct sk_buff *skb;
 721         dma_addr_t dma;
 722         unsigned int dma_len:31;
 723         unsigned int dma_single:1;
 724         struct ring_desc_ex *first_tx_desc;
 725         struct nv_skb_map *next_tx_ctx;
 726 };
 727
 728 /*
 729  * SMP locking:
 730  * All hardware access under netdev_priv(dev)->lock, except the performance
 731  * critical parts:
 732  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 733  *      by the arch code for interrupts.
 734  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 735  *      needs netdev_priv(dev)->lock :-(
 736  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 737  */
 738
 739 /* in dev: base, irq */
 740 struct fe_priv {
 741         spinlock_t lock;
 742
 743         struct net_device *dev;
 744         struct napi_struct napi;
 745
 746         /* General data:
 747          * Locking: spin_lock(&np->lock); */
 748         struct nv_ethtool_stats estats;
 749         int in_shutdown;
 750         u32 linkspeed;
 751         int duplex;
 752         int autoneg;
 753         int fixed_mode;
 754         int phyaddr;
 755         int wolenabled;
 756         unsigned int phy_oui;
 757         unsigned int phy_model;
 758         unsigned int phy_rev;
 759         u16 gigabit;
 760         int intr_test;
 761         int recover_error;
 762         int quiet_count;
 763
 764         /* General data: RO fields */
 765         dma_addr_t ring_addr;
 766         struct pci_dev *pci_dev;
 767         u32 orig_mac[2];
 768         u32 events;
 769         u32 irqmask;
 770         u32 desc_ver;
 771         u32 txrxctl_bits;
 772         u32 vlanctl_bits;
 773         u32 driver_data;
 774         u32 device_id;
 775         u32 register_size;
 776         int rx_csum;
 777         u32 mac_in_use;
 778         int mgmt_version;
 779         int mgmt_sema;
 780
 781         void __iomem *base;
 782
 783         /* rx specific fields.
 784          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 785          */
 786         union ring_type get_rx, put_rx, first_rx, last_rx;
 787         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 788         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 789         struct nv_skb_map *rx_skb;
 790
 791         union ring_type rx_ring;
 792         unsigned int rx_buf_sz;
 793         unsigned int pkt_limit;
 794         struct timer_list oom_kick;
 795         struct timer_list nic_poll;
 796         struct timer_list stats_poll;
 797         u32 nic_poll_irq;
 798         int rx_ring_size;
 799
 800         /* media detection workaround.
 801          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 802          */
 803         int need_linktimer;
 804         unsigned long link_timeout;
 805         /*
 806          * tx specific fields.
 807          */
 808         union ring_type get_tx, put_tx, first_tx, last_tx;
 809         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 810         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 811         struct nv_skb_map *tx_skb;
 812
 813         union ring_type tx_ring;
 814         u32 tx_flags;
 815         int tx_ring_size;
 816         int tx_limit;
 817         u32 tx_pkts_in_progress;
 818         struct nv_skb_map *tx_change_owner;
 819         struct nv_skb_map *tx_end_flip;
 820         int tx_stop;
 821
 822         /* vlan fields */
 823         struct vlan_group *vlangrp;
 824
 825         /* msi/msi-x fields */
 826         u32 msi_flags;
 827         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 828
 829         /* flow control */
 830         u32 pause_flags;
 831
 832         /* power saved state */
 833         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 834
 835         /* for different msi-x irq type */
 836         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 837         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 838         char name_other[IFNAMSIZ + 6];    /* -other */
 839 };
 840
 841 /*
 842  * Maximum number of loops until we assume that a bit in the irq mask
 843  * is stuck. Overridable with module param.
 844  */
 845 static int max_interrupt_work = 4;
 846
 847 /*
 848  * Optimization can be either throuput mode or cpu mode
 849  *
 850  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 851  * CPU Mode: Interrupts are controlled by a timer.
 852  */
 853 enum {
 854         NV_OPTIMIZATION_MODE_THROUGHPUT,
 855         NV_OPTIMIZATION_MODE_CPU,
 856         NV_OPTIMIZATION_MODE_DYNAMIC
 857 };
 858 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 859
 860 /*
 861  * Poll interval for timer irq
 862  *
 863  * This interval determines how frequent an interrupt is generated.
 864  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 865  * Min = 0, and Max = 65535
 866  */
 867 static int poll_interval = -1;
 868
 869 /*
 870  * MSI interrupts
 871  */
 872 enum {
 873         NV_MSI_INT_DISABLED,
 874         NV_MSI_INT_ENABLED
 875 };
 876 static int msi = NV_MSI_INT_ENABLED;
 877
 878 /*
 879  * MSIX interrupts
 880  */
 881 enum {
 882         NV_MSIX_INT_DISABLED,
 883         NV_MSIX_INT_ENABLED
 884 };
 885 static int msix = NV_MSIX_INT_ENABLED;
 886
 887 /*
 888  * DMA 64bit
 889  */
 890 enum {
 891         NV_DMA_64BIT_DISABLED,
 892         NV_DMA_64BIT_ENABLED
 893 };
 894 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 895
 896 /*
 897  * Crossover Detection
 898  * Realtek 8201 phy + some OEM boards do not work properly.
 899  */
 900 enum {
 901         NV_CROSSOVER_DETECTION_DISABLED,
 902         NV_CROSSOVER_DETECTION_ENABLED
 903 };
 904 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 905
 906 /*
 907  * Power down phy when interface is down (persists through reboot;
 908  * older Linux and other OSes may not power it up again)
 909  */
 910 static int phy_power_down = 0;
 911
 912 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 913 {
 914         return netdev_priv(dev);
 915 }
 916
 917 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 918 {
 919         return ((struct fe_priv *)netdev_priv(dev))->base;
 920 }
 921
 922 static inline void pci_push(u8 __iomem *base)
 923 {
 924         /* force out pending posted writes */
 925         readl(base);
 926 }
 927
 928 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 929 {
 930         return le32_to_cpu(prd->flaglen)
 931                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 932 }
 933
 934 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 935 {
 936         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 937 }
 938
 939 static bool nv_optimized(struct fe_priv *np)
 940 {
 941         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 942                 return false;
 943         return true;
 944 }
 945
 946 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 947                                 int delay, int delaymax, const char *msg)
 948 {
 949         u8 __iomem *base = get_hwbase(dev);
 950
 951         pci_push(base);
 952         do {
 953                 udelay(delay);
 954                 delaymax -= delay;
 955                 if (delaymax < 0) {
 956                         if (msg)
 957                                 printk("%s", msg);
 958                         return 1;
 959                 }
 960         } while ((readl(base + offset) & mask) != target);
 961         return 0;
 962 }
 963
 964 #define NV_SETUP_RX_RING 0x01
 965 #define NV_SETUP_TX_RING 0x02
 966
 967 static inline u32 dma_low(dma_addr_t addr)
 968 {
 969         return addr;
 970 }
 971
 972 static inline u32 dma_high(dma_addr_t addr)
 973 {
 974         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 975 }
 976
 977 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 978 {
 979         struct fe_priv *np = get_nvpriv(dev);
 980         u8 __iomem *base = get_hwbase(dev);
 981
 982         if (!nv_optimized(np)) {
 983                 if (rxtx_flags & NV_SETUP_RX_RING) {
 984                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 985                 }
 986                 if (rxtx_flags & NV_SETUP_TX_RING) {
 987                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 988                 }
 989         } else {
 990                 if (rxtx_flags & NV_SETUP_RX_RING) {
 991                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 992                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 993                 }
 994                 if (rxtx_flags & NV_SETUP_TX_RING) {
 995                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 996                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 997                 }
 998         }
 999 }
1000
1001 static void free_rings(struct net_device *dev)
1002 {
1003         struct fe_priv *np = get_nvpriv(dev);
1004
1005         if (!nv_optimized(np)) {
1006                 if (np->rx_ring.orig)
1007                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1008                                             np->rx_ring.orig, np->ring_addr);
1009         } else {
1010                 if (np->rx_ring.ex)
1011                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1012                                             np->rx_ring.ex, np->ring_addr);
1013         }
1014         if (np->rx_skb)
1015                 kfree(np->rx_skb);
1016         if (np->tx_skb)
1017                 kfree(np->tx_skb);
1018 }
1019
1020 static int using_multi_irqs(struct net_device *dev)
1021 {
1022         struct fe_priv *np = get_nvpriv(dev);
1023
1024         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1025             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1026              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1027                 return 0;
1028         else
1029                 return 1;
1030 }
1031
1032 static void nv_txrx_gate(struct net_device *dev, bool gate)
1033 {
1034         struct fe_priv *np = get_nvpriv(dev);
1035         u8 __iomem *base = get_hwbase(dev);
1036         u32 powerstate;
1037
1038         if (!np->mac_in_use &&
1039             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1040                 powerstate = readl(base + NvRegPowerState2);
1041                 if (gate)
1042                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1043                 else
1044                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1045                 writel(powerstate, base + NvRegPowerState2);
1046         }
1047 }
1048
1049 static void nv_enable_irq(struct net_device *dev)
1050 {
1051         struct fe_priv *np = get_nvpriv(dev);
1052
1053         if (!using_multi_irqs(dev)) {
1054                 if (np->msi_flags & NV_MSI_X_ENABLED)
1055                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1056                 else
1057                         enable_irq(np->pci_dev->irq);
1058         } else {
1059                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1060                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1061                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1062         }
1063 }
1064
1065 static void nv_disable_irq(struct net_device *dev)
1066 {
1067         struct fe_priv *np = get_nvpriv(dev);
1068
1069         if (!using_multi_irqs(dev)) {
1070                 if (np->msi_flags & NV_MSI_X_ENABLED)
1071                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1072                 else
1073                         disable_irq(np->pci_dev->irq);
1074         } else {
1075                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1076                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1077                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1078         }
1079 }
1080
1081 /* In MSIX mode, a write to irqmask behaves as XOR */
1082 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1083 {
1084         u8 __iomem *base = get_hwbase(dev);
1085
1086         writel(mask, base + NvRegIrqMask);
1087 }
1088
1089 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1090 {
1091         struct fe_priv *np = get_nvpriv(dev);
1092         u8 __iomem *base = get_hwbase(dev);
1093
1094         if (np->msi_flags & NV_MSI_X_ENABLED) {
1095                 writel(mask, base + NvRegIrqMask);
1096         } else {
1097                 if (np->msi_flags & NV_MSI_ENABLED)
1098                         writel(0, base + NvRegMSIIrqMask);
1099                 writel(0, base + NvRegIrqMask);
1100         }
1101 }
1102
1103 static void nv_napi_enable(struct net_device *dev)
1104 {
1105 #ifdef CONFIG_FORCEDETH_NAPI
1106         struct fe_priv *np = get_nvpriv(dev);
1107
1108         napi_enable(&np->napi);
1109 #endif
1110 }
1111
1112 static void nv_napi_disable(struct net_device *dev)
1113 {
1114 #ifdef CONFIG_FORCEDETH_NAPI
1115         struct fe_priv *np = get_nvpriv(dev);
1116
1117         napi_disable(&np->napi);
1118 #endif
1119 }
1120
1121 #define MII_READ        (-1)
1122 /* mii_rw: read/write a register on the PHY.
1123  *
1124  * Caller must guarantee serialization
1125  */
1126 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1127 {
1128         u8 __iomem *base = get_hwbase(dev);
1129         u32 reg;
1130         int retval;
1131
1132         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1133
1134         reg = readl(base + NvRegMIIControl);
1135         if (reg & NVREG_MIICTL_INUSE) {
1136                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1137                 udelay(NV_MIIBUSY_DELAY);
1138         }
1139
1140         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1141         if (value != MII_READ) {
1142                 writel(value, base + NvRegMIIData);
1143                 reg |= NVREG_MIICTL_WRITE;
1144         }
1145         writel(reg, base + NvRegMIIControl);
1146
1147         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1148                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1149                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1150                                 dev->name, miireg, addr);
1151                 retval = -1;
1152         } else if (value != MII_READ) {
1153                 /* it was a write operation - fewer failures are detectable */
1154                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1155                                 dev->name, value, miireg, addr);
1156                 retval = 0;
1157         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1158                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1159                                 dev->name, miireg, addr);
1160                 retval = -1;
1161         } else {
1162                 retval = readl(base + NvRegMIIData);
1163                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1164                                 dev->name, miireg, addr, retval);
1165         }
1166
1167         return retval;
1168 }
1169
1170 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1171 {
1172         struct fe_priv *np = netdev_priv(dev);
1173         u32 miicontrol;
1174         unsigned int tries = 0;
1175
1176         miicontrol = BMCR_RESET | bmcr_setup;
1177         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1178                 return -1;
1179         }
1180
1181         /* wait for 500ms */
1182         msleep(500);
1183
1184         /* must wait till reset is deasserted */
1185         while (miicontrol & BMCR_RESET) {
1186                 msleep(10);
1187                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1188                 /* FIXME: 100 tries seem excessive */
1189                 if (tries++ > 100)
1190                         return -1;
1191         }
1192         return 0;
1193 }
1194
1195 static int phy_init(struct net_device *dev)
1196 {
1197         struct fe_priv *np = get_nvpriv(dev);
1198         u8 __iomem *base = get_hwbase(dev);
1199         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1200
1201         /* phy errata for E3016 phy */
1202         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1203                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1204                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1205                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1206                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1207                         return PHY_ERROR;
1208                 }
1209         }
1210         if (np->phy_oui == PHY_OUI_REALTEK) {
1211                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1212                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1213                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1214                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1215                                 return PHY_ERROR;
1216                         }
1217                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1218                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219                                 return PHY_ERROR;
1220                         }
1221                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1222                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1223                                 return PHY_ERROR;
1224                         }
1225                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1226                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1227                                 return PHY_ERROR;
1228                         }
1229                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1230                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1231                                 return PHY_ERROR;
1232                         }
1233                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1234                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1235                                 return PHY_ERROR;
1236                         }
1237                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1238                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                                 return PHY_ERROR;
1240                         }
1241                 }
1242                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1243                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1244                         u32 powerstate = readl(base + NvRegPowerState2);
1245
1246                         /* need to perform hw phy reset */
1247                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1248                         writel(powerstate, base + NvRegPowerState2);
1249                         msleep(25);
1250
1251                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1252                         writel(powerstate, base + NvRegPowerState2);
1253                         msleep(25);
1254
1255                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1256                         reg |= PHY_REALTEK_INIT9;
1257                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1258                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259                                 return PHY_ERROR;
1260                         }
1261                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1262                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263                                 return PHY_ERROR;
1264                         }
1265                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1266                         if (!(reg & PHY_REALTEK_INIT11)) {
1267                                 reg |= PHY_REALTEK_INIT11;
1268                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1269                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                                         return PHY_ERROR;
1271                                 }
1272                         }
1273                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1274                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275                                 return PHY_ERROR;
1276                         }
1277                 }
1278                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1279                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1280                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1281                                 phy_reserved |= PHY_REALTEK_INIT7;
1282                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1283                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284                                         return PHY_ERROR;
1285                                 }
1286                         }
1287                 }
1288         }
1289
1290         /* set advertise register */
1291         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1292         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1293         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1294                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1295                 return PHY_ERROR;
1296         }
1297
1298         /* get phy interface type */
1299         phyinterface = readl(base + NvRegPhyInterface);
1300
1301         /* see if gigabit phy */
1302         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1303         if (mii_status & PHY_GIGABIT) {
1304                 np->gigabit = PHY_GIGABIT;
1305                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1306                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1307                 if (phyinterface & PHY_RGMII)
1308                         mii_control_1000 |= ADVERTISE_1000FULL;
1309                 else
1310                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1311
1312                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1313                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1314                         return PHY_ERROR;
1315                 }
1316         }
1317         else
1318                 np->gigabit = 0;
1319
1320         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1321         mii_control |= BMCR_ANENABLE;
1322
1323         if (np->phy_oui == PHY_OUI_REALTEK &&
1324             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1325             np->phy_rev == PHY_REV_REALTEK_8211C) {
1326                 /* start autoneg since we already performed hw reset above */
1327                 mii_control |= BMCR_ANRESTART;
1328                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1329                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1330                         return PHY_ERROR;
1331                 }
1332         } else {
1333                 /* reset the phy
1334                  * (certain phys need bmcr to be setup with reset)
1335                  */
1336                 if (phy_reset(dev, mii_control)) {
1337                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1338                         return PHY_ERROR;
1339                 }
1340         }
1341
1342         /* phy vendor specific configuration */
1343         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1344                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1345                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1346                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1347                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1348                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1349                         return PHY_ERROR;
1350                 }
1351                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1352                 phy_reserved |= PHY_CICADA_INIT5;
1353                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1354                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1355                         return PHY_ERROR;
1356                 }
1357         }
1358         if (np->phy_oui == PHY_OUI_CICADA) {
1359                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1360                 phy_reserved |= PHY_CICADA_INIT6;
1361                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1362                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363                         return PHY_ERROR;
1364                 }
1365         }
1366         if (np->phy_oui == PHY_OUI_VITESSE) {
1367                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1368                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369                         return PHY_ERROR;
1370                 }
1371                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1372                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1373                         return PHY_ERROR;
1374                 }
1375                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1376                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1377                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1378                         return PHY_ERROR;
1379                 }
1380                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1381                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1382                 phy_reserved |= PHY_VITESSE_INIT3;
1383                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1384                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1385                         return PHY_ERROR;
1386                 }
1387                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1388                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389                         return PHY_ERROR;
1390                 }
1391                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1392                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1393                         return PHY_ERROR;
1394                 }
1395                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1396                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1397                 phy_reserved |= PHY_VITESSE_INIT3;
1398                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1399                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400                         return PHY_ERROR;
1401                 }
1402                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1403                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1404                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405                         return PHY_ERROR;
1406                 }
1407                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1408                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409                         return PHY_ERROR;
1410                 }
1411                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1412                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1413                         return PHY_ERROR;
1414                 }
1415                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1416                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1417                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1418                         return PHY_ERROR;
1419                 }
1420                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1421                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1422                 phy_reserved |= PHY_VITESSE_INIT8;
1423                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1424                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1425                         return PHY_ERROR;
1426                 }
1427                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1428                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429                         return PHY_ERROR;
1430                 }
1431                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1432                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1433                         return PHY_ERROR;
1434                 }
1435         }
1436         if (np->phy_oui == PHY_OUI_REALTEK) {
1437                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1438                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1439                         /* reset could have cleared these out, set them back */
1440                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1441                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1442                                 return PHY_ERROR;
1443                         }
1444                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1445                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1446                                 return PHY_ERROR;
1447                         }
1448                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1449                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450                                 return PHY_ERROR;
1451                         }
1452                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1453                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1454                                 return PHY_ERROR;
1455                         }
1456                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1457                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1458                                 return PHY_ERROR;
1459                         }
1460                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1461                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1462                                 return PHY_ERROR;
1463                         }
1464                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1465                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1466                                 return PHY_ERROR;
1467                         }
1468                 }
1469                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1470                         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1471                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1472                                 phy_reserved |= PHY_REALTEK_INIT7;
1473                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1474                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1475                                         return PHY_ERROR;
1476                                 }
1477                         }
1478                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1479                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1480                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1481                                         return PHY_ERROR;
1482                                 }
1483                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1484                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1485                                 phy_reserved |= PHY_REALTEK_INIT3;
1486                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1487                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1488                                         return PHY_ERROR;
1489                                 }
1490                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1491                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1492                                         return PHY_ERROR;
1493                                 }
1494                         }
1495                 }
1496         }
1497
1498         /* some phys clear out pause advertisment on reset, set it back */
1499         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1500
1501         /* restart auto negotiation, power down phy */
1502         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1503         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1504         if (phy_power_down) {
1505                 mii_control |= BMCR_PDOWN;
1506         }
1507         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1508                 return PHY_ERROR;
1509         }
1510
1511         return 0;
1512 }
1513
1514 static void nv_start_rx(struct net_device *dev)
1515 {
1516         struct fe_priv *np = netdev_priv(dev);
1517         u8 __iomem *base = get_hwbase(dev);
1518         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1519
1520         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1521         /* Already running? Stop it. */
1522         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1523                 rx_ctrl &= ~NVREG_RCVCTL_START;
1524                 writel(rx_ctrl, base + NvRegReceiverControl);
1525                 pci_push(base);
1526         }
1527         writel(np->linkspeed, base + NvRegLinkSpeed);
1528         pci_push(base);
1529         rx_ctrl |= NVREG_RCVCTL_START;
1530         if (np->mac_in_use)
1531                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1532         writel(rx_ctrl, base + NvRegReceiverControl);
1533         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1534                                 dev->name, np->duplex, np->linkspeed);
1535         pci_push(base);
1536 }
1537
1538 static void nv_stop_rx(struct net_device *dev)
1539 {
1540         struct fe_priv *np = netdev_priv(dev);
1541         u8 __iomem *base = get_hwbase(dev);
1542         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1543
1544         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1545         if (!np->mac_in_use)
1546                 rx_ctrl &= ~NVREG_RCVCTL_START;
1547         else
1548                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1549         writel(rx_ctrl, base + NvRegReceiverControl);
1550         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1551                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1552                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1553
1554         udelay(NV_RXSTOP_DELAY2);
1555         if (!np->mac_in_use)
1556                 writel(0, base + NvRegLinkSpeed);
1557 }
1558
1559 static void nv_start_tx(struct net_device *dev)
1560 {
1561         struct fe_priv *np = netdev_priv(dev);
1562         u8 __iomem *base = get_hwbase(dev);
1563         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564
1565         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1566         tx_ctrl |= NVREG_XMITCTL_START;
1567         if (np->mac_in_use)
1568                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1569         writel(tx_ctrl, base + NvRegTransmitterControl);
1570         pci_push(base);
1571 }
1572
1573 static void nv_stop_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1580         if (!np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_START;
1582         else
1583                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584         writel(tx_ctrl, base + NvRegTransmitterControl);
1585         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1587                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1588
1589         udelay(NV_TXSTOP_DELAY2);
1590         if (!np->mac_in_use)
1591                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1592                        base + NvRegTransmitPoll);
1593 }
1594
1595 static void nv_start_rxtx(struct net_device *dev)
1596 {
1597         nv_start_rx(dev);
1598         nv_start_tx(dev);
1599 }
1600
1601 static void nv_stop_rxtx(struct net_device *dev)
1602 {
1603         nv_stop_rx(dev);
1604         nv_stop_tx(dev);
1605 }
1606
1607 static void nv_txrx_reset(struct net_device *dev)
1608 {
1609         struct fe_priv *np = netdev_priv(dev);
1610         u8 __iomem *base = get_hwbase(dev);
1611
1612         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1613         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1614         pci_push(base);
1615         udelay(NV_TXRX_RESET_DELAY);
1616         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1617         pci_push(base);
1618 }
1619
1620 static void nv_mac_reset(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624         u32 temp1, temp2, temp3;
1625
1626         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1627
1628         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1629         pci_push(base);
1630
1631         /* save registers since they will be cleared on reset */
1632         temp1 = readl(base + NvRegMacAddrA);
1633         temp2 = readl(base + NvRegMacAddrB);
1634         temp3 = readl(base + NvRegTransmitPoll);
1635
1636         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1637         pci_push(base);
1638         udelay(NV_MAC_RESET_DELAY);
1639         writel(0, base + NvRegMacReset);
1640         pci_push(base);
1641         udelay(NV_MAC_RESET_DELAY);
1642
1643         /* restore saved registers */
1644         writel(temp1, base + NvRegMacAddrA);
1645         writel(temp2, base + NvRegMacAddrB);
1646         writel(temp3, base + NvRegTransmitPoll);
1647
1648         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1649         pci_push(base);
1650 }
1651
1652 static void nv_get_hw_stats(struct net_device *dev)
1653 {
1654         struct fe_priv *np = netdev_priv(dev);
1655         u8 __iomem *base = get_hwbase(dev);
1656
1657         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1658         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1659         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1660         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1661         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1662         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1663         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1664         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1665         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1666         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1667         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1668         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1669         np->estats.rx_runt += readl(base + NvRegRxRunt);
1670         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1671         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1672         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1673         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1674         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1675         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1676         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1677         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1678         np->estats.rx_packets =
1679                 np->estats.rx_unicast +
1680                 np->estats.rx_multicast +
1681                 np->estats.rx_broadcast;
1682         np->estats.rx_errors_total =
1683                 np->estats.rx_crc_errors +
1684                 np->estats.rx_over_errors +
1685                 np->estats.rx_frame_error +
1686                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1687                 np->estats.rx_late_collision +
1688                 np->estats.rx_runt +
1689                 np->estats.rx_frame_too_long;
1690         np->estats.tx_errors_total =
1691                 np->estats.tx_late_collision +
1692                 np->estats.tx_fifo_errors +
1693                 np->estats.tx_carrier_errors +
1694                 np->estats.tx_excess_deferral +
1695                 np->estats.tx_retry_error;
1696
1697         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1698                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1699                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1700                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1701                 np->estats.tx_pause += readl(base + NvRegTxPause);
1702                 np->estats.rx_pause += readl(base + NvRegRxPause);
1703                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1704         }
1705
1706         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1707                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1708                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1709                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1710         }
1711 }
1712
1713 /*
1714  * nv_get_stats: dev->get_stats function
1715  * Get latest stats value from the nic.
1716  * Called with read_lock(&dev_base_lock) held for read -
1717  * only synchronized against unregister_netdevice.
1718  */
1719 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1720 {
1721         struct fe_priv *np = netdev_priv(dev);
1722
1723         /* If the nic supports hw counters then retrieve latest values */
1724         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1725                 nv_get_hw_stats(dev);
1726
1727                 /* copy to net_device stats */
1728                 dev->stats.tx_bytes = np->estats.tx_bytes;
1729                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1730                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1731                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1732                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1733                 dev->stats.rx_errors = np->estats.rx_errors_total;
1734                 dev->stats.tx_errors = np->estats.tx_errors_total;
1735         }
1736
1737         return &dev->stats;
1738 }
1739
1740 /*
1741  * nv_alloc_rx: fill rx ring entries.
1742  * Return 1 if the allocations for the skbs failed and the
1743  * rx engine is without Available descriptors
1744  */
1745 static int nv_alloc_rx(struct net_device *dev)
1746 {
1747         struct fe_priv *np = netdev_priv(dev);
1748         struct ring_desc* less_rx;
1749
1750         less_rx = np->get_rx.orig;
1751         if (less_rx-- == np->first_rx.orig)
1752                 less_rx = np->last_rx.orig;
1753
1754         while (np->put_rx.orig != less_rx) {
1755                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1756                 if (skb) {
1757                         np->put_rx_ctx->skb = skb;
1758                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1759                                                              skb->data,
1760                                                              skb_tailroom(skb),
1761                                                              PCI_DMA_FROMDEVICE);
1762                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1763                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1764                         wmb();
1765                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1766                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1767                                 np->put_rx.orig = np->first_rx.orig;
1768                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1769                                 np->put_rx_ctx = np->first_rx_ctx;
1770                 } else {
1771                         return 1;
1772                 }
1773         }
1774         return 0;
1775 }
1776
1777 static int nv_alloc_rx_optimized(struct net_device *dev)
1778 {
1779         struct fe_priv *np = netdev_priv(dev);
1780         struct ring_desc_ex* less_rx;
1781
1782         less_rx = np->get_rx.ex;
1783         if (less_rx-- == np->first_rx.ex)
1784                 less_rx = np->last_rx.ex;
1785
1786         while (np->put_rx.ex != less_rx) {
1787                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1788                 if (skb) {
1789                         np->put_rx_ctx->skb = skb;
1790                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1791                                                              skb->data,
1792                                                              skb_tailroom(skb),
1793                                                              PCI_DMA_FROMDEVICE);
1794                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1795                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1796                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1797                         wmb();
1798                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1799                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1800                                 np->put_rx.ex = np->first_rx.ex;
1801                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1802                                 np->put_rx_ctx = np->first_rx_ctx;
1803                 } else {
1804                         return 1;
1805                 }
1806         }
1807         return 0;
1808 }
1809
1810 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1811 #ifdef CONFIG_FORCEDETH_NAPI
1812 static void nv_do_rx_refill(unsigned long data)
1813 {
1814         struct net_device *dev = (struct net_device *) data;
1815         struct fe_priv *np = netdev_priv(dev);
1816
1817         /* Just reschedule NAPI rx processing */
1818         napi_schedule(&np->napi);
1819 }
1820 #else
1821 static void nv_do_rx_refill(unsigned long data)
1822 {
1823         struct net_device *dev = (struct net_device *) data;
1824         struct fe_priv *np = netdev_priv(dev);
1825         int retcode;
1826
1827         if (!using_multi_irqs(dev)) {
1828                 if (np->msi_flags & NV_MSI_X_ENABLED)
1829                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1830                 else
1831                         disable_irq(np->pci_dev->irq);
1832         } else {
1833                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1834         }
1835         if (!nv_optimized(np))
1836                 retcode = nv_alloc_rx(dev);
1837         else
1838                 retcode = nv_alloc_rx_optimized(dev);
1839         if (retcode) {
1840                 spin_lock_irq(&np->lock);
1841                 if (!np->in_shutdown)
1842                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1843                 spin_unlock_irq(&np->lock);
1844         }
1845         if (!using_multi_irqs(dev)) {
1846                 if (np->msi_flags & NV_MSI_X_ENABLED)
1847                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1848                 else
1849                         enable_irq(np->pci_dev->irq);
1850         } else {
1851                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1852         }
1853 }
1854 #endif
1855
1856 static void nv_init_rx(struct net_device *dev)
1857 {
1858         struct fe_priv *np = netdev_priv(dev);
1859         int i;
1860
1861         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1862
1863         if (!nv_optimized(np))
1864                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1865         else
1866                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1867         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1868         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1869
1870         for (i = 0; i < np->rx_ring_size; i++) {
1871                 if (!nv_optimized(np)) {
1872                         np->rx_ring.orig[i].flaglen = 0;
1873                         np->rx_ring.orig[i].buf = 0;
1874                 } else {
1875                         np->rx_ring.ex[i].flaglen = 0;
1876                         np->rx_ring.ex[i].txvlan = 0;
1877                         np->rx_ring.ex[i].bufhigh = 0;
1878                         np->rx_ring.ex[i].buflow = 0;
1879                 }
1880                 np->rx_skb[i].skb = NULL;
1881                 np->rx_skb[i].dma = 0;
1882         }
1883 }
1884
1885 static void nv_init_tx(struct net_device *dev)
1886 {
1887         struct fe_priv *np = netdev_priv(dev);
1888         int i;
1889
1890         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1891
1892         if (!nv_optimized(np))
1893                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1894         else
1895                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1896         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1897         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1898         np->tx_pkts_in_progress = 0;
1899         np->tx_change_owner = NULL;
1900         np->tx_end_flip = NULL;
1901         np->tx_stop = 0;
1902
1903         for (i = 0; i < np->tx_ring_size; i++) {
1904                 if (!nv_optimized(np)) {
1905                         np->tx_ring.orig[i].flaglen = 0;
1906                         np->tx_ring.orig[i].buf = 0;
1907                 } else {
1908                         np->tx_ring.ex[i].flaglen = 0;
1909                         np->tx_ring.ex[i].txvlan = 0;
1910                         np->tx_ring.ex[i].bufhigh = 0;
1911                         np->tx_ring.ex[i].buflow = 0;
1912                 }
1913                 np->tx_skb[i].skb = NULL;
1914                 np->tx_skb[i].dma = 0;
1915                 np->tx_skb[i].dma_len = 0;
1916                 np->tx_skb[i].dma_single = 0;
1917                 np->tx_skb[i].first_tx_desc = NULL;
1918                 np->tx_skb[i].next_tx_ctx = NULL;
1919         }
1920 }
1921
1922 static int nv_init_ring(struct net_device *dev)
1923 {
1924         struct fe_priv *np = netdev_priv(dev);
1925
1926         nv_init_tx(dev);
1927         nv_init_rx(dev);
1928
1929         if (!nv_optimized(np))
1930                 return nv_alloc_rx(dev);
1931         else
1932                 return nv_alloc_rx_optimized(dev);
1933 }
1934
1935 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1936 {
1937         if (tx_skb->dma) {
1938                 if (tx_skb->dma_single)
1939                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1940                                          tx_skb->dma_len,
1941                                          PCI_DMA_TODEVICE);
1942                 else
1943                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1944                                        tx_skb->dma_len,
1945                                        PCI_DMA_TODEVICE);
1946                 tx_skb->dma = 0;
1947         }
1948 }
1949
1950 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1951 {
1952         nv_unmap_txskb(np, tx_skb);
1953         if (tx_skb->skb) {
1954                 dev_kfree_skb_any(tx_skb->skb);
1955                 tx_skb->skb = NULL;
1956                 return 1;
1957         }
1958         return 0;
1959 }
1960
1961 static void nv_drain_tx(struct net_device *dev)
1962 {
1963         struct fe_priv *np = netdev_priv(dev);
1964         unsigned int i;
1965
1966         for (i = 0; i < np->tx_ring_size; i++) {
1967                 if (!nv_optimized(np)) {
1968                         np->tx_ring.orig[i].flaglen = 0;
1969                         np->tx_ring.orig[i].buf = 0;
1970                 } else {
1971                         np->tx_ring.ex[i].flaglen = 0;
1972                         np->tx_ring.ex[i].txvlan = 0;
1973                         np->tx_ring.ex[i].bufhigh = 0;
1974                         np->tx_ring.ex[i].buflow = 0;
1975                 }
1976                 if (nv_release_txskb(np, &np->tx_skb[i]))
1977                         dev->stats.tx_dropped++;
1978                 np->tx_skb[i].dma = 0;
1979                 np->tx_skb[i].dma_len = 0;
1980                 np->tx_skb[i].dma_single = 0;
1981                 np->tx_skb[i].first_tx_desc = NULL;
1982                 np->tx_skb[i].next_tx_ctx = NULL;
1983         }
1984         np->tx_pkts_in_progress = 0;
1985         np->tx_change_owner = NULL;
1986         np->tx_end_flip = NULL;
1987 }
1988
1989 static void nv_drain_rx(struct net_device *dev)
1990 {
1991         struct fe_priv *np = netdev_priv(dev);
1992         int i;
1993
1994         for (i = 0; i < np->rx_ring_size; i++) {
1995                 if (!nv_optimized(np)) {
1996                         np->rx_ring.orig[i].flaglen = 0;
1997                         np->rx_ring.orig[i].buf = 0;
1998                 } else {
1999                         np->rx_ring.ex[i].flaglen = 0;
2000                         np->rx_ring.ex[i].txvlan = 0;
2001                         np->rx_ring.ex[i].bufhigh = 0;
2002                         np->rx_ring.ex[i].buflow = 0;
2003                 }
2004                 wmb();
2005                 if (np->rx_skb[i].skb) {
2006                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2007                                          (skb_end_pointer(np->rx_skb[i].skb) -
2008                                           np->rx_skb[i].skb->data),
2009                                          PCI_DMA_FROMDEVICE);
2010                         dev_kfree_skb(np->rx_skb[i].skb);
2011                         np->rx_skb[i].skb = NULL;
2012                 }
2013         }
2014 }
2015
2016 static void nv_drain_rxtx(struct net_device *dev)
2017 {
2018         nv_drain_tx(dev);
2019         nv_drain_rx(dev);
2020 }
2021
2022 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2023 {
2024         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2025 }
2026
2027 static void nv_legacybackoff_reseed(struct net_device *dev)
2028 {
2029         u8 __iomem *base = get_hwbase(dev);
2030         u32 reg;
2031         u32 low;
2032         int tx_status = 0;
2033
2034         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2035         get_random_bytes(&low, sizeof(low));
2036         reg |= low & NVREG_SLOTTIME_MASK;
2037
2038         /* Need to stop tx before change takes effect.
2039          * Caller has already gained np->lock.
2040          */
2041         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2042         if (tx_status)
2043                 nv_stop_tx(dev);
2044         nv_stop_rx(dev);
2045         writel(reg, base + NvRegSlotTime);
2046         if (tx_status)
2047                 nv_start_tx(dev);
2048         nv_start_rx(dev);
2049 }
2050
2051 /* Gear Backoff Seeds */
2052 #define BACKOFF_SEEDSET_ROWS    8
2053 #define BACKOFF_SEEDSET_LFSRS   15
2054
2055 /* Known Good seed sets */
2056 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2057     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2058     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2059     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2060     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2061     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2062     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2063     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2064     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2065
2066 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2067     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2068     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2069     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2070     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2071     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2072     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2073     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2074     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2075
2076 static void nv_gear_backoff_reseed(struct net_device *dev)
2077 {
2078         u8 __iomem *base = get_hwbase(dev);
2079         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2080         u32 temp, seedset, combinedSeed;
2081         int i;
2082
2083         /* Setup seed for free running LFSR */
2084         /* We are going to read the time stamp counter 3 times
2085            and swizzle bits around to increase randomness */
2086         get_random_bytes(&miniseed1, sizeof(miniseed1));
2087         miniseed1 &= 0x0fff;
2088         if (miniseed1 == 0)
2089                 miniseed1 = 0xabc;
2090
2091         get_random_bytes(&miniseed2, sizeof(miniseed2));
2092         miniseed2 &= 0x0fff;
2093         if (miniseed2 == 0)
2094                 miniseed2 = 0xabc;
2095         miniseed2_reversed =
2096                 ((miniseed2 & 0xF00) >> 8) |
2097                  (miniseed2 & 0x0F0) |
2098                  ((miniseed2 & 0x00F) << 8);
2099
2100         get_random_bytes(&miniseed3, sizeof(miniseed3));
2101         miniseed3 &= 0x0fff;
2102         if (miniseed3 == 0)
2103                 miniseed3 = 0xabc;
2104         miniseed3_reversed =
2105                 ((miniseed3 & 0xF00) >> 8) |
2106                  (miniseed3 & 0x0F0) |
2107                  ((miniseed3 & 0x00F) << 8);
2108
2109         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2110                        (miniseed2 ^ miniseed3_reversed);
2111
2112         /* Seeds can not be zero */
2113         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2114                 combinedSeed |= 0x08;
2115         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2116                 combinedSeed |= 0x8000;
2117
2118         /* No need to disable tx here */
2119         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2120         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2121         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2122         writel(temp,base + NvRegBackOffControl);
2123
2124         /* Setup seeds for all gear LFSRs. */
2125         get_random_bytes(&seedset, sizeof(seedset));
2126         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2127         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2128         {
2129                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2130                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2131                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2132                 writel(temp, base + NvRegBackOffControl);
2133         }
2134 }
2135
2136 /*
2137  * nv_start_xmit: dev->hard_start_xmit function
2138  * Called with netif_tx_lock held.
2139  */
2140 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2141 {
2142         struct fe_priv *np = netdev_priv(dev);
2143         u32 tx_flags = 0;
2144         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2145         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2146         unsigned int i;
2147         u32 offset = 0;
2148         u32 bcnt;
2149         u32 size = skb->len-skb->data_len;
2150         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2151         u32 empty_slots;
2152         struct ring_desc* put_tx;
2153         struct ring_desc* start_tx;
2154         struct ring_desc* prev_tx;
2155         struct nv_skb_map* prev_tx_ctx;
2156         unsigned long flags;
2157
2158         /* add fragments to entries count */
2159         for (i = 0; i < fragments; i++) {
2160                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2161                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2162         }
2163
2164         spin_lock_irqsave(&np->lock, flags);
2165         empty_slots = nv_get_empty_tx_slots(np);
2166         if (unlikely(empty_slots <= entries)) {
2167                 netif_stop_queue(dev);
2168                 np->tx_stop = 1;
2169                 spin_unlock_irqrestore(&np->lock, flags);
2170                 return NETDEV_TX_BUSY;
2171         }
2172         spin_unlock_irqrestore(&np->lock, flags);
2173
2174         start_tx = put_tx = np->put_tx.orig;
2175
2176         /* setup the header buffer */
2177         do {
2178                 prev_tx = put_tx;
2179                 prev_tx_ctx = np->put_tx_ctx;
2180                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2181                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2182                                                 PCI_DMA_TODEVICE);
2183                 np->put_tx_ctx->dma_len = bcnt;
2184                 np->put_tx_ctx->dma_single = 1;
2185                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2186                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2187
2188                 tx_flags = np->tx_flags;
2189                 offset += bcnt;
2190                 size -= bcnt;
2191                 if (unlikely(put_tx++ == np->last_tx.orig))
2192                         put_tx = np->first_tx.orig;
2193                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2194                         np->put_tx_ctx = np->first_tx_ctx;
2195         } while (size);
2196
2197         /* setup the fragments */
2198         for (i = 0; i < fragments; i++) {
2199                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2200                 u32 size = frag->size;
2201                 offset = 0;
2202
2203                 do {
2204                         prev_tx = put_tx;
2205                         prev_tx_ctx = np->put_tx_ctx;
2206                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2207                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2208                                                            PCI_DMA_TODEVICE);
2209                         np->put_tx_ctx->dma_len = bcnt;
2210                         np->put_tx_ctx->dma_single = 0;
2211                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2212                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2213
2214                         offset += bcnt;
2215                         size -= bcnt;
2216                         if (unlikely(put_tx++ == np->last_tx.orig))
2217                                 put_tx = np->first_tx.orig;
2218                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2219                                 np->put_tx_ctx = np->first_tx_ctx;
2220                 } while (size);
2221         }
2222
2223         /* set last fragment flag  */
2224         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2225
2226         /* save skb in this slot's context area */
2227         prev_tx_ctx->skb = skb;
2228
2229         if (skb_is_gso(skb))
2230                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2231         else
2232                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2233                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2234
2235         spin_lock_irqsave(&np->lock, flags);
2236
2237         /* set tx flags */
2238         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2239         np->put_tx.orig = put_tx;
2240
2241         spin_unlock_irqrestore(&np->lock, flags);
2242
2243         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2244                 dev->name, entries, tx_flags_extra);
2245         {
2246                 int j;
2247                 for (j=0; j<64; j++) {
2248                         if ((j%16) == 0)
2249                                 dprintk("\n%03x:", j);
2250                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2251                 }
2252                 dprintk("\n");
2253         }
2254
2255         dev->trans_start = jiffies;
2256         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2257         return NETDEV_TX_OK;
2258 }
2259
2260 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2261 {
2262         struct fe_priv *np = netdev_priv(dev);
2263         u32 tx_flags = 0;
2264         u32 tx_flags_extra;
2265         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2266         unsigned int i;
2267         u32 offset = 0;
2268         u32 bcnt;
2269         u32 size = skb->len-skb->data_len;
2270         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2271         u32 empty_slots;
2272         struct ring_desc_ex* put_tx;
2273         struct ring_desc_ex* start_tx;
2274         struct ring_desc_ex* prev_tx;
2275         struct nv_skb_map* prev_tx_ctx;
2276         struct nv_skb_map* start_tx_ctx;
2277         unsigned long flags;
2278
2279         /* add fragments to entries count */
2280         for (i = 0; i < fragments; i++) {
2281                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2282                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2283         }
2284
2285         spin_lock_irqsave(&np->lock, flags);
2286         empty_slots = nv_get_empty_tx_slots(np);
2287         if (unlikely(empty_slots <= entries)) {
2288                 netif_stop_queue(dev);
2289                 np->tx_stop = 1;
2290                 spin_unlock_irqrestore(&np->lock, flags);
2291                 return NETDEV_TX_BUSY;
2292         }
2293         spin_unlock_irqrestore(&np->lock, flags);
2294
2295         start_tx = put_tx = np->put_tx.ex;
2296         start_tx_ctx = np->put_tx_ctx;
2297
2298         /* setup the header buffer */
2299         do {
2300                 prev_tx = put_tx;
2301                 prev_tx_ctx = np->put_tx_ctx;
2302                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2303                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2304                                                 PCI_DMA_TODEVICE);
2305                 np->put_tx_ctx->dma_len = bcnt;
2306                 np->put_tx_ctx->dma_single = 1;
2307                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2308                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2309                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2310
2311                 tx_flags = NV_TX2_VALID;
2312                 offset += bcnt;
2313                 size -= bcnt;
2314                 if (unlikely(put_tx++ == np->last_tx.ex))
2315                         put_tx = np->first_tx.ex;
2316                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2317                         np->put_tx_ctx = np->first_tx_ctx;
2318         } while (size);
2319
2320         /* setup the fragments */
2321         for (i = 0; i < fragments; i++) {
2322                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2323                 u32 size = frag->size;
2324                 offset = 0;
2325
2326                 do {
2327                         prev_tx = put_tx;
2328                         prev_tx_ctx = np->put_tx_ctx;
2329                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2330                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2331                                                            PCI_DMA_TODEVICE);
2332                         np->put_tx_ctx->dma_len = bcnt;
2333                         np->put_tx_ctx->dma_single = 0;
2334                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2335                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2336                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2337
2338                         offset += bcnt;
2339                         size -= bcnt;
2340                         if (unlikely(put_tx++ == np->last_tx.ex))
2341                                 put_tx = np->first_tx.ex;
2342                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2343                                 np->put_tx_ctx = np->first_tx_ctx;
2344                 } while (size);
2345         }
2346
2347         /* set last fragment flag  */
2348         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2349
2350         /* save skb in this slot's context area */
2351         prev_tx_ctx->skb = skb;
2352
2353         if (skb_is_gso(skb))
2354                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2355         else
2356                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2357                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2358
2359         /* vlan tag */
2360         if (likely(!np->vlangrp)) {
2361                 start_tx->txvlan = 0;
2362         } else {
2363                 if (vlan_tx_tag_present(skb))
2364                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2365                 else
2366                         start_tx->txvlan = 0;
2367         }
2368
2369         spin_lock_irqsave(&np->lock, flags);
2370
2371         if (np->tx_limit) {
2372                 /* Limit the number of outstanding tx. Setup all fragments, but
2373                  * do not set the VALID bit on the first descriptor. Save a pointer
2374                  * to that descriptor and also for next skb_map element.
2375                  */
2376
2377                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2378                         if (!np->tx_change_owner)
2379                                 np->tx_change_owner = start_tx_ctx;
2380
2381                         /* remove VALID bit */
2382                         tx_flags &= ~NV_TX2_VALID;
2383                         start_tx_ctx->first_tx_desc = start_tx;
2384                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2385                         np->tx_end_flip = np->put_tx_ctx;
2386                 } else {
2387                         np->tx_pkts_in_progress++;
2388                 }
2389         }
2390
2391         /* set tx flags */
2392         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2393         np->put_tx.ex = put_tx;
2394
2395         spin_unlock_irqrestore(&np->lock, flags);
2396
2397         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2398                 dev->name, entries, tx_flags_extra);
2399         {
2400                 int j;
2401                 for (j=0; j<64; j++) {
2402                         if ((j%16) == 0)
2403                                 dprintk("\n%03x:", j);
2404                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2405                 }
2406                 dprintk("\n");
2407         }
2408
2409         dev->trans_start = jiffies;
2410         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2411         return NETDEV_TX_OK;
2412 }
2413
2414 static inline void nv_tx_flip_ownership(struct net_device *dev)
2415 {
2416         struct fe_priv *np = netdev_priv(dev);
2417
2418         np->tx_pkts_in_progress--;
2419         if (np->tx_change_owner) {
2420                 np->tx_change_owner->first_tx_desc->flaglen |=
2421                         cpu_to_le32(NV_TX2_VALID);
2422                 np->tx_pkts_in_progress++;
2423
2424                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2425                 if (np->tx_change_owner == np->tx_end_flip)
2426                         np->tx_change_owner = NULL;
2427
2428                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2429         }
2430 }
2431
2432 /*
2433  * nv_tx_done: check for completed packets, release the skbs.
2434  *
2435  * Caller must own np->lock.
2436  */
2437 static int nv_tx_done(struct net_device *dev, int limit)
2438 {
2439         struct fe_priv *np = netdev_priv(dev);
2440         u32 flags;
2441         int tx_work = 0;
2442         struct ring_desc* orig_get_tx = np->get_tx.orig;
2443
2444         while ((np->get_tx.orig != np->put_tx.orig) &&
2445                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2446                (tx_work < limit)) {
2447
2448                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2449                                         dev->name, flags);
2450
2451                 nv_unmap_txskb(np, np->get_tx_ctx);
2452
2453                 if (np->desc_ver == DESC_VER_1) {
2454                         if (flags & NV_TX_LASTPACKET) {
2455                                 if (flags & NV_TX_ERROR) {
2456                                         if (flags & NV_TX_UNDERFLOW)
2457                                                 dev->stats.tx_fifo_errors++;
2458                                         if (flags & NV_TX_CARRIERLOST)
2459                                                 dev->stats.tx_carrier_errors++;
2460                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2461                                                 nv_legacybackoff_reseed(dev);
2462                                         dev->stats.tx_errors++;
2463                                 } else {
2464                                         dev->stats.tx_packets++;
2465                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2466                                 }
2467                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2468                                 np->get_tx_ctx->skb = NULL;
2469                                 tx_work++;
2470                         }
2471                 } else {
2472                         if (flags & NV_TX2_LASTPACKET) {
2473                                 if (flags & NV_TX2_ERROR) {
2474                                         if (flags & NV_TX2_UNDERFLOW)
2475                                                 dev->stats.tx_fifo_errors++;
2476                                         if (flags & NV_TX2_CARRIERLOST)
2477                                                 dev->stats.tx_carrier_errors++;
2478                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2479                                                 nv_legacybackoff_reseed(dev);
2480                                         dev->stats.tx_errors++;
2481                                 } else {
2482                                         dev->stats.tx_packets++;
2483                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2484                                 }
2485                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2486                                 np->get_tx_ctx->skb = NULL;
2487                                 tx_work++;
2488                         }
2489                 }
2490                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2491                         np->get_tx.orig = np->first_tx.orig;
2492                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2493                         np->get_tx_ctx = np->first_tx_ctx;
2494         }
2495         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2496                 np->tx_stop = 0;
2497                 netif_wake_queue(dev);
2498         }
2499         return tx_work;
2500 }
2501
2502 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2503 {
2504         struct fe_priv *np = netdev_priv(dev);
2505         u32 flags;
2506         int tx_work = 0;
2507         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2508
2509         while ((np->get_tx.ex != np->put_tx.ex) &&
2510                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2511                (tx_work < limit)) {
2512
2513                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2514                                         dev->name, flags);
2515
2516                 nv_unmap_txskb(np, np->get_tx_ctx);
2517
2518                 if (flags & NV_TX2_LASTPACKET) {
2519                         if (!(flags & NV_TX2_ERROR))
2520                                 dev->stats.tx_packets++;
2521                         else {
2522                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2523                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2524                                                 nv_gear_backoff_reseed(dev);
2525                                         else
2526                                                 nv_legacybackoff_reseed(dev);
2527                                 }
2528                         }
2529
2530                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2531                         np->get_tx_ctx->skb = NULL;
2532                         tx_work++;
2533
2534                         if (np->tx_limit) {
2535                                 nv_tx_flip_ownership(dev);
2536                         }
2537                 }
2538                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2539                         np->get_tx.ex = np->first_tx.ex;
2540                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2541                         np->get_tx_ctx = np->first_tx_ctx;
2542         }
2543         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2544                 np->tx_stop = 0;
2545                 netif_wake_queue(dev);
2546         }
2547         return tx_work;
2548 }
2549
2550 /*
2551  * nv_tx_timeout: dev->tx_timeout function
2552  * Called with netif_tx_lock held.
2553  */
2554 static void nv_tx_timeout(struct net_device *dev)
2555 {
2556         struct fe_priv *np = netdev_priv(dev);
2557         u8 __iomem *base = get_hwbase(dev);
2558         u32 status;
2559         union ring_type put_tx;
2560         int saved_tx_limit;
2561
2562         if (np->msi_flags & NV_MSI_X_ENABLED)
2563                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2564         else
2565                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2566
2567         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2568
2569         {
2570                 int i;
2571
2572                 printk(KERN_INFO "%s: Ring at %lx\n",
2573                        dev->name, (unsigned long)np->ring_addr);
2574                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2575                 for (i=0;i<=np->register_size;i+= 32) {
2576                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2577                                         i,
2578                                         readl(base + i + 0), readl(base + i + 4),
2579                                         readl(base + i + 8), readl(base + i + 12),
2580                                         readl(base + i + 16), readl(base + i + 20),
2581                                         readl(base + i + 24), readl(base + i + 28));
2582                 }
2583                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2584                 for (i=0;i<np->tx_ring_size;i+= 4) {
2585                         if (!nv_optimized(np)) {
2586                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2587                                        i,
2588                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2589                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2590                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2591                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2592                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2593                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2594                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2595                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2596                         } else {
2597                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2598                                        i,
2599                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2600                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2601                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2602                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2603                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2604                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2605                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2606                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2607                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2608                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2609                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2610                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2611                         }
2612                 }
2613         }
2614
2615         spin_lock_irq(&np->lock);
2616
2617         /* 1) stop tx engine */
2618         nv_stop_tx(dev);
2619
2620         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2621         saved_tx_limit = np->tx_limit;
2622         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2623         np->tx_stop = 0;  /* prevent waking tx queue */
2624         if (!nv_optimized(np))
2625                 nv_tx_done(dev, np->tx_ring_size);
2626         else
2627                 nv_tx_done_optimized(dev, np->tx_ring_size);
2628
2629         /* save current HW postion */
2630         if (np->tx_change_owner)
2631                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2632         else
2633                 put_tx = np->put_tx;
2634
2635         /* 3) clear all tx state */
2636         nv_drain_tx(dev);
2637         nv_init_tx(dev);
2638
2639         /* 4) restore state to current HW position */
2640         np->get_tx = np->put_tx = put_tx;
2641         np->tx_limit = saved_tx_limit;
2642
2643         /* 5) restart tx engine */
2644         nv_start_tx(dev);
2645         netif_wake_queue(dev);
2646         spin_unlock_irq(&np->lock);
2647 }
2648
2649 /*
2650  * Called when the nic notices a mismatch between the actual data len on the
2651  * wire and the len indicated in the 802 header
2652  */
2653 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2654 {
2655         int hdrlen;     /* length of the 802 header */
2656         int protolen;   /* length as stored in the proto field */
2657
2658         /* 1) calculate len according to header */
2659         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2660                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2661                 hdrlen = VLAN_HLEN;
2662         } else {
2663                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2664                 hdrlen = ETH_HLEN;
2665         }
2666         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2667                                 dev->name, datalen, protolen, hdrlen);
2668         if (protolen > ETH_DATA_LEN)
2669                 return datalen; /* Value in proto field not a len, no checks possible */
2670
2671         protolen += hdrlen;
2672         /* consistency checks: */
2673         if (datalen > ETH_ZLEN) {
2674                 if (datalen >= protolen) {
2675                         /* more data on wire than in 802 header, trim of
2676                          * additional data.
2677                          */
2678                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2679                                         dev->name, protolen);
2680                         return protolen;
2681                 } else {
2682                         /* less data on wire than mentioned in header.
2683                          * Discard the packet.
2684                          */
2685                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2686                                         dev->name);
2687                         return -1;
2688                 }
2689         } else {
2690                 /* short packet. Accept only if 802 values are also short */
2691                 if (protolen > ETH_ZLEN) {
2692                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2693                                         dev->name);
2694                         return -1;
2695                 }
2696                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2697                                 dev->name, datalen);
2698                 return datalen;
2699         }
2700 }
2701
2702 static int nv_rx_process(struct net_device *dev, int limit)
2703 {
2704         struct fe_priv *np = netdev_priv(dev);
2705         u32 flags;
2706         int rx_work = 0;
2707         struct sk_buff *skb;
2708         int len;
2709
2710         while((np->get_rx.orig != np->put_rx.orig) &&
2711               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2712                 (rx_work < limit)) {
2713
2714                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2715                                         dev->name, flags);
2716
2717                 /*
2718                  * the packet is for us - immediately tear down the pci mapping.
2719                  * TODO: check if a prefetch of the first cacheline improves
2720                  * the performance.
2721                  */
2722                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2723                                 np->get_rx_ctx->dma_len,
2724                                 PCI_DMA_FROMDEVICE);
2725                 skb = np->get_rx_ctx->skb;
2726                 np->get_rx_ctx->skb = NULL;
2727
2728                 {
2729                         int j;
2730                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2731                         for (j=0; j<64; j++) {
2732                                 if ((j%16) == 0)
2733                                         dprintk("\n%03x:", j);
2734                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2735                         }
2736                         dprintk("\n");
2737                 }
2738                 /* look at what we actually got: */
2739                 if (np->desc_ver == DESC_VER_1) {
2740                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2741                                 len = flags & LEN_MASK_V1;
2742                                 if (unlikely(flags & NV_RX_ERROR)) {
2743                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2744                                                 len = nv_getlen(dev, skb->data, len);
2745                                                 if (len < 0) {
2746                                                         dev->stats.rx_errors++;
2747                                                         dev_kfree_skb(skb);
2748                                                         goto next_pkt;
2749                                                 }
2750                                         }
2751                                         /* framing errors are soft errors */
2752                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2753                                                 if (flags & NV_RX_SUBSTRACT1) {
2754                                                         len--;
2755                                                 }
2756                                         }
2757                                         /* the rest are hard errors */
2758                                         else {
2759                                                 if (flags & NV_RX_MISSEDFRAME)
2760                                                         dev->stats.rx_missed_errors++;
2761                                                 if (flags & NV_RX_CRCERR)
2762                                                         dev->stats.rx_crc_errors++;
2763                                                 if (flags & NV_RX_OVERFLOW)
2764                                                         dev->stats.rx_over_errors++;
2765                                                 dev->stats.rx_errors++;
2766                                                 dev_kfree_skb(skb);
2767                                                 goto next_pkt;
2768                                         }
2769                                 }
2770                         } else {
2771                                 dev_kfree_skb(skb);
2772                                 goto next_pkt;
2773                         }
2774                 } else {
2775                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2776                                 len = flags & LEN_MASK_V2;
2777                                 if (unlikely(flags & NV_RX2_ERROR)) {
2778                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2779                                                 len = nv_getlen(dev, skb->data, len);
2780                                                 if (len < 0) {
2781                                                         dev->stats.rx_errors++;
2782                                                         dev_kfree_skb(skb);
2783                                                         goto next_pkt;
2784                                                 }
2785                                         }
2786                                         /* framing errors are soft errors */
2787                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2788                                                 if (flags & NV_RX2_SUBSTRACT1) {
2789                                                         len--;
2790                                                 }
2791                                         }
2792                                         /* the rest are hard errors */
2793                                         else {
2794                                                 if (flags & NV_RX2_CRCERR)
2795                                                         dev->stats.rx_crc_errors++;
2796                                                 if (flags & NV_RX2_OVERFLOW)
2797                                                         dev->stats.rx_over_errors++;
2798                                                 dev->stats.rx_errors++;
2799                                                 dev_kfree_skb(skb);
2800                                                 goto next_pkt;
2801                                         }
2802                                 }
2803                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2804                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2805                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2806                         } else {
2807                                 dev_kfree_skb(skb);
2808                                 goto next_pkt;
2809                         }
2810                 }
2811                 /* got a valid packet - forward it to the network core */
2812                 skb_put(skb, len);
2813                 skb->protocol = eth_type_trans(skb, dev);
2814                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2815                                         dev->name, len, skb->protocol);
2816 #ifdef CONFIG_FORCEDETH_NAPI
2817                 netif_receive_skb(skb);
2818 #else
2819                 netif_rx(skb);
2820 #endif
2821                 dev->stats.rx_packets++;
2822                 dev->stats.rx_bytes += len;
2823 next_pkt:
2824                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2825                         np->get_rx.orig = np->first_rx.orig;
2826                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2827                         np->get_rx_ctx = np->first_rx_ctx;
2828
2829                 rx_work++;
2830         }
2831
2832         return rx_work;
2833 }
2834
2835 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2836 {
2837         struct fe_priv *np = netdev_priv(dev);
2838         u32 flags;
2839         u32 vlanflags = 0;
2840         int rx_work = 0;
2841         struct sk_buff *skb;
2842         int len;
2843
2844         while((np->get_rx.ex != np->put_rx.ex) &&
2845               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2846               (rx_work < limit)) {
2847
2848                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2849                                         dev->name, flags);
2850
2851                 /*
2852                  * the packet is for us - immediately tear down the pci mapping.
2853                  * TODO: check if a prefetch of the first cacheline improves
2854                  * the performance.
2855                  */
2856                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2857                                 np->get_rx_ctx->dma_len,
2858                                 PCI_DMA_FROMDEVICE);
2859                 skb = np->get_rx_ctx->skb;
2860                 np->get_rx_ctx->skb = NULL;
2861
2862                 {
2863                         int j;
2864                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2865                         for (j=0; j<64; j++) {
2866                                 if ((j%16) == 0)
2867                                         dprintk("\n%03x:", j);
2868                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2869                         }
2870                         dprintk("\n");
2871                 }
2872                 /* look at what we actually got: */
2873                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2874                         len = flags & LEN_MASK_V2;
2875                         if (unlikely(flags & NV_RX2_ERROR)) {
2876                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2877                                         len = nv_getlen(dev, skb->data, len);
2878                                         if (len < 0) {
2879                                                 dev_kfree_skb(skb);
2880                                                 goto next_pkt;
2881                                         }
2882                                 }
2883                                 /* framing errors are soft errors */
2884                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2885                                         if (flags & NV_RX2_SUBSTRACT1) {
2886                                                 len--;
2887                                         }
2888                                 }
2889                                 /* the rest are hard errors */
2890                                 else {
2891                                         dev_kfree_skb(skb);
2892                                         goto next_pkt;
2893                                 }
2894                         }
2895
2896                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2897                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2898                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2899
2900                         /* got a valid packet - forward it to the network core */
2901                         skb_put(skb, len);
2902                         skb->protocol = eth_type_trans(skb, dev);
2903                         prefetch(skb->data);
2904
2905                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2906                                 dev->name, len, skb->protocol);
2907
2908                         if (likely(!np->vlangrp)) {
2909 #ifdef CONFIG_FORCEDETH_NAPI
2910                                 netif_receive_skb(skb);
2911 #else
2912                                 netif_rx(skb);
2913 #endif
2914                         } else {
2915                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2916                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2917 #ifdef CONFIG_FORCEDETH_NAPI
2918                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2919                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2920 #else
2921                                         vlan_hwaccel_rx(skb, np->vlangrp,
2922                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2923 #endif
2924                                 } else {
2925 #ifdef CONFIG_FORCEDETH_NAPI
2926                                         netif_receive_skb(skb);
2927 #else
2928                                         netif_rx(skb);
2929 #endif
2930                                 }
2931                         }
2932
2933                         dev->stats.rx_packets++;
2934                         dev->stats.rx_bytes += len;
2935                 } else {
2936                         dev_kfree_skb(skb);
2937                 }
2938 next_pkt:
2939                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2940                         np->get_rx.ex = np->first_rx.ex;
2941                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2942                         np->get_rx_ctx = np->first_rx_ctx;
2943
2944                 rx_work++;
2945         }
2946
2947         return rx_work;
2948 }
2949
2950 static void set_bufsize(struct net_device *dev)
2951 {
2952         struct fe_priv *np = netdev_priv(dev);
2953
2954         if (dev->mtu <= ETH_DATA_LEN)
2955                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2956         else
2957                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2958 }
2959
2960 /*
2961  * nv_change_mtu: dev->change_mtu function
2962  * Called with dev_base_lock held for read.
2963  */
2964 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2965 {
2966         struct fe_priv *np = netdev_priv(dev);
2967         int old_mtu;
2968
2969         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2970                 return -EINVAL;
2971
2972         old_mtu = dev->mtu;
2973         dev->mtu = new_mtu;
2974
2975         /* return early if the buffer sizes will not change */
2976         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2977                 return 0;
2978         if (old_mtu == new_mtu)
2979                 return 0;
2980
2981         /* synchronized against open : rtnl_lock() held by caller */
2982         if (netif_running(dev)) {
2983                 u8 __iomem *base = get_hwbase(dev);
2984                 /*
2985                  * It seems that the nic preloads valid ring entries into an
2986                  * internal buffer. The procedure for flushing everything is
2987                  * guessed, there is probably a simpler approach.
2988                  * Changing the MTU is a rare event, it shouldn't matter.
2989                  */
2990                 nv_disable_irq(dev);
2991                 nv_napi_disable(dev);
2992                 netif_tx_lock_bh(dev);
2993                 netif_addr_lock(dev);
2994                 spin_lock(&np->lock);
2995                 /* stop engines */
2996                 nv_stop_rxtx(dev);
2997                 nv_txrx_reset(dev);
2998                 /* drain rx queue */
2999                 nv_drain_rxtx(dev);
3000                 /* reinit driver view of the rx queue */
3001                 set_bufsize(dev);
3002                 if (nv_init_ring(dev)) {
3003                         if (!np->in_shutdown)
3004                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3005                 }
3006                 /* reinit nic view of the rx queue */
3007                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3008                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3009                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3010                         base + NvRegRingSizes);
3011                 pci_push(base);
3012                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3013                 pci_push(base);
3014
3015                 /* restart rx engine */
3016                 nv_start_rxtx(dev);
3017                 spin_unlock(&np->lock);
3018                 netif_addr_unlock(dev);
3019                 netif_tx_unlock_bh(dev);
3020                 nv_napi_enable(dev);
3021                 nv_enable_irq(dev);
3022         }
3023         return 0;
3024 }
3025
3026 static void nv_copy_mac_to_hw(struct net_device *dev)
3027 {
3028         u8 __iomem *base = get_hwbase(dev);
3029         u32 mac[2];
3030
3031         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3032                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3033         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3034
3035         writel(mac[0], base + NvRegMacAddrA);
3036         writel(mac[1], base + NvRegMacAddrB);
3037 }
3038
3039 /*
3040  * nv_set_mac_address: dev->set_mac_address function
3041  * Called with rtnl_lock() held.
3042  */
3043 static int nv_set_mac_address(struct net_device *dev, void *addr)
3044 {
3045         struct fe_priv *np = netdev_priv(dev);
3046         struct sockaddr *macaddr = (struct sockaddr*)addr;
3047
3048         if (!is_valid_ether_addr(macaddr->sa_data))
3049                 return -EADDRNOTAVAIL;
3050
3051         /* synchronized against open : rtnl_lock() held by caller */
3052         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3053
3054         if (netif_running(dev)) {
3055                 netif_tx_lock_bh(dev);
3056                 netif_addr_lock(dev);
3057                 spin_lock_irq(&np->lock);
3058
3059                 /* stop rx engine */
3060                 nv_stop_rx(dev);
3061
3062                 /* set mac address */
3063                 nv_copy_mac_to_hw(dev);
3064
3065                 /* restart rx engine */
3066                 nv_start_rx(dev);
3067                 spin_unlock_irq(&np->lock);
3068                 netif_addr_unlock(dev);
3069                 netif_tx_unlock_bh(dev);
3070         } else {
3071                 nv_copy_mac_to_hw(dev);
3072         }
3073         return 0;
3074 }
3075
3076 /*
3077  * nv_set_multicast: dev->set_multicast function
3078  * Called with netif_tx_lock held.
3079  */
3080 static void nv_set_multicast(struct net_device *dev)
3081 {
3082         struct fe_priv *np = netdev_priv(dev);
3083         u8 __iomem *base = get_hwbase(dev);
3084         u32 addr[2];
3085         u32 mask[2];
3086         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3087
3088         memset(addr, 0, sizeof(addr));
3089         memset(mask, 0, sizeof(mask));
3090
3091         if (dev->flags & IFF_PROMISC) {
3092                 pff |= NVREG_PFF_PROMISC;
3093         } else {
3094                 pff |= NVREG_PFF_MYADDR;
3095
3096                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3097                         u32 alwaysOff[2];
3098                         u32 alwaysOn[2];
3099
3100                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3101                         if (dev->flags & IFF_ALLMULTI) {
3102                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3103                         } else {
3104                                 struct dev_mc_list *walk;
3105
3106                                 walk = dev->mc_list;
3107                                 while (walk != NULL) {
3108                                         u32 a, b;
3109                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3110                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3111                                         alwaysOn[0] &= a;
3112                                         alwaysOff[0] &= ~a;
3113                                         alwaysOn[1] &= b;
3114                                         alwaysOff[1] &= ~b;
3115                                         walk = walk->next;
3116                                 }
3117                         }
3118                         addr[0] = alwaysOn[0];
3119                         addr[1] = alwaysOn[1];
3120                         mask[0] = alwaysOn[0] | alwaysOff[0];
3121                         mask[1] = alwaysOn[1] | alwaysOff[1];
3122                 } else {
3123                         mask[0] = NVREG_MCASTMASKA_NONE;
3124                         mask[1] = NVREG_MCASTMASKB_NONE;
3125                 }
3126         }
3127         addr[0] |= NVREG_MCASTADDRA_FORCE;
3128         pff |= NVREG_PFF_ALWAYS;
3129         spin_lock_irq(&np->lock);
3130         nv_stop_rx(dev);
3131         writel(addr[0], base + NvRegMulticastAddrA);
3132         writel(addr[1], base + NvRegMulticastAddrB);
3133         writel(mask[0], base + NvRegMulticastMaskA);
3134         writel(mask[1], base + NvRegMulticastMaskB);
3135         writel(pff, base + NvRegPacketFilterFlags);
3136         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3137                 dev->name);
3138         nv_start_rx(dev);
3139         spin_unlock_irq(&np->lock);
3140 }
3141
3142 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3143 {
3144         struct fe_priv *np = netdev_priv(dev);
3145         u8 __iomem *base = get_hwbase(dev);
3146
3147         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3148
3149         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3150                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3151                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3152                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3153                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3154                 } else {
3155                         writel(pff, base + NvRegPacketFilterFlags);
3156                 }
3157         }
3158         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3159                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3160                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3161                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3162                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3163                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3164                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3165                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3166                                 /* limit the number of tx pause frames to a default of 8 */
3167                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3168                         }
3169                         writel(pause_enable,  base + NvRegTxPauseFrame);
3170                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3171                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3172                 } else {
3173                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3174                         writel(regmisc, base + NvRegMisc1);
3175                 }
3176         }
3177 }
3178
3179 /**
3180  * nv_update_linkspeed: Setup the MAC according to the link partner
3181  * @dev: Network device to be configured
3182  *
3183  * The function queries the PHY and checks if there is a link partner.
3184  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3185  * set to 10 MBit HD.
3186  *
3187  * The function returns 0 if there is no link partner and 1 if there is
3188  * a good link partner.
3189  */
3190 static int nv_update_linkspeed(struct net_device *dev)
3191 {
3192         struct fe_priv *np = netdev_priv(dev);
3193         u8 __iomem *base = get_hwbase(dev);
3194         int adv = 0;
3195         int lpa = 0;
3196         int adv_lpa, adv_pause, lpa_pause;
3197         int newls = np->linkspeed;
3198         int newdup = np->duplex;
3199         int mii_status;
3200         int retval = 0;
3201         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3202         u32 txrxFlags = 0;
3203         u32 phy_exp;
3204
3205         /* BMSR_LSTATUS is latched, read it twice:
3206          * we want the current value.
3207          */
3208         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3209         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3210
3211         if (!(mii_status & BMSR_LSTATUS)) {
3212                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3213                                 dev->name);
3214                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3215                 newdup = 0;
3216                 retval = 0;
3217                 goto set_speed;
3218         }
3219
3220         if (np->autoneg == 0) {
3221                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3222                                 dev->name, np->fixed_mode);
3223                 if (np->fixed_mode & LPA_100FULL) {
3224                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3225                         newdup = 1;
3226                 } else if (np->fixed_mode & LPA_100HALF) {
3227                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3228                         newdup = 0;
3229                 } else if (np->fixed_mode & LPA_10FULL) {
3230                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3231                         newdup = 1;
3232                 } else {
3233                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3234                         newdup = 0;
3235                 }
3236                 retval = 1;
3237                 goto set_speed;
3238         }
3239         /* check auto negotiation is complete */
3240         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3241                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3242                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3243                 newdup = 0;
3244                 retval = 0;
3245                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3246                 goto set_speed;
3247         }
3248
3249         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3250         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3251         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3252                                 dev->name, adv, lpa);
3253
3254         retval = 1;
3255         if (np->gigabit == PHY_GIGABIT) {
3256                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3257                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3258
3259                 if ((control_1000 & ADVERTISE_1000FULL) &&
3260                         (status_1000 & LPA_1000FULL)) {
3261                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3262                                 dev->name);
3263                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3264                         newdup = 1;
3265                         goto set_speed;
3266                 }
3267         }
3268
3269         /* FIXME: handle parallel detection properly */
3270         adv_lpa = lpa & adv;
3271         if (adv_lpa & LPA_100FULL) {
3272                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3273                 newdup = 1;
3274         } else if (adv_lpa & LPA_100HALF) {
3275                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276                 newdup = 0;
3277         } else if (adv_lpa & LPA_10FULL) {
3278                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3279                 newdup = 1;
3280         } else if (adv_lpa & LPA_10HALF) {
3281                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282                 newdup = 0;
3283         } else {
3284                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3285                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3286                 newdup = 0;
3287         }
3288
3289 set_speed:
3290         if (np->duplex == newdup && np->linkspeed == newls)
3291                 return retval;
3292
3293         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3294                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3295
3296         np->duplex = newdup;
3297         np->linkspeed = newls;
3298
3299         /* The transmitter and receiver must be restarted for safe update */
3300         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3301                 txrxFlags |= NV_RESTART_TX;
3302                 nv_stop_tx(dev);
3303         }
3304         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3305                 txrxFlags |= NV_RESTART_RX;
3306                 nv_stop_rx(dev);
3307         }
3308
3309         if (np->gigabit == PHY_GIGABIT) {
3310                 phyreg = readl(base + NvRegSlotTime);
3311                 phyreg &= ~(0x3FF00);
3312                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3313                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3314                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3315                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3316                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3317                 writel(phyreg, base + NvRegSlotTime);
3318         }
3319
3320         phyreg = readl(base + NvRegPhyInterface);
3321         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3322         if (np->duplex == 0)
3323                 phyreg |= PHY_HALF;
3324         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3325                 phyreg |= PHY_100;
3326         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3327                 phyreg |= PHY_1000;
3328         writel(phyreg, base + NvRegPhyInterface);
3329
3330         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3331         if (phyreg & PHY_RGMII) {
3332                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3333                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3334                 } else {
3335                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3336                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3337                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3338                                 else
3339                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3340                         } else {
3341                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3342                         }
3343                 }
3344         } else {
3345                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3346                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3347                 else
3348                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3349         }
3350         writel(txreg, base + NvRegTxDeferral);
3351
3352         if (np->desc_ver == DESC_VER_1) {
3353                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3354         } else {
3355                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3356                         txreg = NVREG_TX_WM_DESC2_3_1000;
3357                 else
3358                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3359         }
3360         writel(txreg, base + NvRegTxWatermark);
3361
3362         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3363                 base + NvRegMisc1);
3364         pci_push(base);
3365         writel(np->linkspeed, base + NvRegLinkSpeed);
3366         pci_push(base);
3367
3368         pause_flags = 0;
3369         /* setup pause frame */
3370         if (np->duplex != 0) {
3371                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3372                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3373                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3374
3375                         switch (adv_pause) {
3376                         case ADVERTISE_PAUSE_CAP:
3377                                 if (lpa_pause & LPA_PAUSE_CAP) {
3378                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3379                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3380                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3381                                 }
3382                                 break;
3383                         case ADVERTISE_PAUSE_ASYM:
3384                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3385                                 {
3386                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3387                                 }
3388                                 break;
3389                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3390                                 if (lpa_pause & LPA_PAUSE_CAP)
3391                                 {
3392                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3393                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3394                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3395                                 }
3396                                 if (lpa_pause == LPA_PAUSE_ASYM)
3397                                 {
3398                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3399                                 }
3400                                 break;
3401                         }
3402                 } else {
3403                         pause_flags = np->pause_flags;
3404                 }
3405         }
3406         nv_update_pause(dev, pause_flags);
3407
3408         if (txrxFlags & NV_RESTART_TX)
3409                 nv_start_tx(dev);
3410         if (txrxFlags & NV_RESTART_RX)
3411                 nv_start_rx(dev);
3412
3413         return retval;
3414 }
3415
3416 static void nv_linkchange(struct net_device *dev)
3417 {
3418         if (nv_update_linkspeed(dev)) {
3419                 if (!netif_carrier_ok(dev)) {
3420                         netif_carrier_on(dev);
3421                         printk(KERN_INFO "%s: link up.\n", dev->name);
3422                         nv_txrx_gate(dev, false);
3423                         nv_start_rx(dev);
3424                 }
3425         } else {
3426                 if (netif_carrier_ok(dev)) {
3427                         netif_carrier_off(dev);
3428                         printk(KERN_INFO "%s: link down.\n", dev->name);
3429                         nv_txrx_gate(dev, true);
3430                         nv_stop_rx(dev);
3431                 }
3432         }
3433 }
3434
3435 static void nv_link_irq(struct net_device *dev)
3436 {
3437         u8 __iomem *base = get_hwbase(dev);
3438         u32 miistat;
3439
3440         miistat = readl(base + NvRegMIIStatus);
3441         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3442         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3443
3444         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3445                 nv_linkchange(dev);
3446         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3447 }
3448
3449 static void nv_msi_workaround(struct fe_priv *np)
3450 {
3451
3452         /* Need to toggle the msi irq mask within the ethernet device,
3453          * otherwise, future interrupts will not be detected.
3454          */
3455         if (np->msi_flags & NV_MSI_ENABLED) {
3456                 u8 __iomem *base = np->base;
3457
3458                 writel(0, base + NvRegMSIIrqMask);
3459                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3460         }
3461 }
3462
3463 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3464 {
3465         struct fe_priv *np = netdev_priv(dev);
3466
3467         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3468                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3469                         /* transition to poll based interrupts */
3470                         np->quiet_count = 0;
3471                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3472                                 np->irqmask = NVREG_IRQMASK_CPU;
3473                                 return 1;
3474                         }
3475                 } else {
3476                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3477                                 np->quiet_count++;
3478                         } else {
3479                                 /* reached a period of low activity, switch
3480                                    to per tx/rx packet interrupts */
3481                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3482                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3483                                         return 1;
3484                                 }
3485                         }
3486                 }
3487         }
3488         return 0;
3489 }
3490
3491 static irqreturn_t nv_nic_irq(int foo, void *data)
3492 {
3493         struct net_device *dev = (struct net_device *) data;
3494         struct fe_priv *np = netdev_priv(dev);
3495         u8 __iomem *base = get_hwbase(dev);
3496 #ifndef CONFIG_FORCEDETH_NAPI
3497         int total_work = 0;
3498         int loop_count = 0;
3499 #endif
3500
3501         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3502
3503         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3504                 np->events = readl(base + NvRegIrqStatus);
3505                 writel(np->events, base + NvRegIrqStatus);
3506         } else {
3507                 np->events = readl(base + NvRegMSIXIrqStatus);
3508                 writel(np->events, base + NvRegMSIXIrqStatus);
3509         }
3510         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3511         if (!(np->events & np->irqmask))
3512                 return IRQ_NONE;
3513
3514         nv_msi_workaround(np);
3515
3516 #ifdef CONFIG_FORCEDETH_NAPI
3517         napi_schedule(&np->napi);
3518
3519         /* Disable furthur irq's
3520            (msix not enabled with napi) */
3521         writel(0, base + NvRegIrqMask);
3522
3523 #else
3524         do
3525         {
3526                 int work = 0;
3527                 if ((work = nv_rx_process(dev, RX_WORK_PER_LOOP))) {
3528                         if (unlikely(nv_alloc_rx(dev))) {
3529                                 spin_lock(&np->lock);
3530                                 if (!np->in_shutdown)
3531                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3532                                 spin_unlock(&np->lock);
3533                         }
3534                 }
3535
3536                 spin_lock(&np->lock);
3537                 work += nv_tx_done(dev, TX_WORK_PER_LOOP);
3538                 spin_unlock(&np->lock);
3539
3540                 if (!work)
3541                         break;
3542
3543                 total_work += work;
3544
3545                 loop_count++;
3546         }
3547         while (loop_count < max_interrupt_work);
3548
3549         if (nv_change_interrupt_mode(dev, total_work)) {
3550                 /* setup new irq mask */
3551                 writel(np->irqmask, base + NvRegIrqMask);
3552         }
3553
3554         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3555                 spin_lock(&np->lock);
3556                 nv_link_irq(dev);
3557                 spin_unlock(&np->lock);
3558         }
3559         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3560                 spin_lock(&np->lock);
3561                 nv_linkchange(dev);
3562                 spin_unlock(&np->lock);
3563                 np->link_timeout = jiffies + LINK_TIMEOUT;
3564         }
3565         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3566                 spin_lock(&np->lock);
3567                 /* disable interrupts on the nic */
3568                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3569                         writel(0, base + NvRegIrqMask);
3570                 else
3571                         writel(np->irqmask, base + NvRegIrqMask);
3572                 pci_push(base);
3573
3574                 if (!np->in_shutdown) {
3575                         np->nic_poll_irq = np->irqmask;
3576                         np->recover_error = 1;
3577                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3578                 }
3579                 spin_unlock(&np->lock);
3580         }
3581 #endif
3582         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3583
3584         return IRQ_HANDLED;
3585 }
3586
3587 /**
3588  * All _optimized functions are used to help increase performance
3589  * (reduce CPU and increase throughput). They use descripter version 3,
3590  * compiler directives, and reduce memory accesses.
3591  */
3592 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3593 {
3594         struct net_device *dev = (struct net_device *) data;
3595         struct fe_priv *np = netdev_priv(dev);
3596         u8 __iomem *base = get_hwbase(dev);
3597 #ifndef CONFIG_FORCEDETH_NAPI
3598         int total_work = 0;
3599         int loop_count = 0;
3600 #endif
3601
3602         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3603
3604         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3605                 np->events = readl(base + NvRegIrqStatus);
3606                 writel(np->events, base + NvRegIrqStatus);
3607         } else {
3608                 np->events = readl(base + NvRegMSIXIrqStatus);
3609                 writel(np->events, base + NvRegMSIXIrqStatus);
3610         }
3611         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3612         if (!(np->events & np->irqmask))
3613                 return IRQ_NONE;
3614
3615         nv_msi_workaround(np);
3616
3617 #ifdef CONFIG_FORCEDETH_NAPI
3618         napi_schedule(&np->napi);
3619
3620         /* Disable furthur irq's
3621            (msix not enabled with napi) */
3622         writel(0, base + NvRegIrqMask);
3623
3624 #else
3625         do
3626         {
3627                 int work = 0;
3628                 if ((work = nv_rx_process_optimized(dev, RX_WORK_PER_LOOP))) {
3629                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3630                                 spin_lock(&np->lock);
3631                                 if (!np->in_shutdown)
3632                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3633                                 spin_unlock(&np->lock);
3634                         }
3635                 }
3636
3637                 spin_lock(&np->lock);
3638                 work += nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3639                 spin_unlock(&np->lock);
3640
3641                 if (!work)
3642                         break;
3643
3644                 total_work += work;
3645
3646                 loop_count++;
3647         }
3648         while (loop_count < max_interrupt_work);
3649
3650         if (nv_change_interrupt_mode(dev, total_work)) {
3651                 /* setup new irq mask */
3652                 writel(np->irqmask, base + NvRegIrqMask);
3653         }
3654
3655         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3656                 spin_lock(&np->lock);
3657                 nv_link_irq(dev);
3658                 spin_unlock(&np->lock);
3659         }
3660         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3661                 spin_lock(&np->lock);
3662                 nv_linkchange(dev);
3663                 spin_unlock(&np->lock);
3664                 np->link_timeout = jiffies + LINK_TIMEOUT;
3665         }
3666         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3667                 spin_lock(&np->lock);
3668                 /* disable interrupts on the nic */
3669                 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3670                         writel(0, base + NvRegIrqMask);
3671                 else
3672                         writel(np->irqmask, base + NvRegIrqMask);
3673                 pci_push(base);
3674
3675                 if (!np->in_shutdown) {
3676                         np->nic_poll_irq = np->irqmask;
3677                         np->recover_error = 1;
3678                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3679                 }
3680                 spin_unlock(&np->lock);
3681         }
3682
3683 #endif
3684         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3685
3686         return IRQ_HANDLED;
3687 }
3688
3689 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3690 {
3691         struct net_device *dev = (struct net_device *) data;
3692         struct fe_priv *np = netdev_priv(dev);
3693         u8 __iomem *base = get_hwbase(dev);
3694         u32 events;
3695         int i;
3696         unsigned long flags;
3697
3698         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3699
3700         for (i=0; ; i++) {
3701                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3702                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3703                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3704                 if (!(events & np->irqmask))
3705                         break;
3706
3707                 spin_lock_irqsave(&np->lock, flags);
3708                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3709                 spin_unlock_irqrestore(&np->lock, flags);
3710
3711                 if (unlikely(i > max_interrupt_work)) {
3712                         spin_lock_irqsave(&np->lock, flags);
3713                         /* disable interrupts on the nic */
3714                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3715                         pci_push(base);
3716
3717                         if (!np->in_shutdown) {
3718                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3719                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3720                         }
3721                         spin_unlock_irqrestore(&np->lock, flags);
3722                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3723                         break;
3724                 }
3725
3726         }
3727         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3728
3729         return IRQ_RETVAL(i);
3730 }
3731
3732 #ifdef CONFIG_FORCEDETH_NAPI
3733 static int nv_napi_poll(struct napi_struct *napi, int budget)
3734 {
3735         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3736         struct net_device *dev = np->dev;
3737         u8 __iomem *base = get_hwbase(dev);
3738         unsigned long flags;
3739         int retcode;
3740         int tx_work, rx_work;
3741
3742         if (!nv_optimized(np)) {
3743                 spin_lock_irqsave(&np->lock, flags);
3744                 tx_work = nv_tx_done(dev, np->tx_ring_size);
3745                 spin_unlock_irqrestore(&np->lock, flags);
3746
3747                 rx_work = nv_rx_process(dev, budget);
3748                 retcode = nv_alloc_rx(dev);
3749         } else {
3750                 spin_lock_irqsave(&np->lock, flags);
3751                 tx_work = nv_tx_done_optimized(dev, np->tx_ring_size);
3752                 spin_unlock_irqrestore(&np->lock, flags);
3753
3754                 rx_work = nv_rx_process_optimized(dev, budget);
3755                 retcode = nv_alloc_rx_optimized(dev);
3756         }
3757
3758         if (retcode) {
3759                 spin_lock_irqsave(&np->lock, flags);
3760                 if (!np->in_shutdown)
3761                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3762                 spin_unlock_irqrestore(&np->lock, flags);
3763         }
3764
3765         nv_change_interrupt_mode(dev, tx_work + rx_work);
3766
3767         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3768                 spin_lock_irqsave(&np->lock, flags);
3769                 nv_link_irq(dev);
3770                 spin_unlock_irqrestore(&np->lock, flags);
3771         }
3772         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3773                 spin_lock_irqsave(&np->lock, flags);
3774                 nv_linkchange(dev);
3775                 spin_unlock_irqrestore(&np->lock, flags);
3776                 np->link_timeout = jiffies + LINK_TIMEOUT;
3777         }
3778         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3779                 spin_lock_irqsave(&np->lock, flags);
3780                 if (!np->in_shutdown) {
3781                         np->nic_poll_irq = np->irqmask;
3782                         np->recover_error = 1;
3783                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3784                 }
3785                 spin_unlock_irqrestore(&np->lock, flags);
3786                 napi_complete(napi);
3787                 return rx_work;
3788         }
3789
3790         if (rx_work < budget) {
3791                 /* re-enable interrupts
3792                    (msix not enabled in napi) */
3793                 napi_complete(napi);
3794
3795                 writel(np->irqmask, base + NvRegIrqMask);
3796         }
3797         return rx_work;
3798 }
3799 #endif
3800
3801 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3802 {
3803         struct net_device *dev = (struct net_device *) data;
3804         struct fe_priv *np = netdev_priv(dev);
3805         u8 __iomem *base = get_hwbase(dev);
3806         u32 events;
3807         int i;
3808         unsigned long flags;
3809
3810         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3811
3812         for (i=0; ; i++) {
3813                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3814                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3815                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3816                 if (!(events & np->irqmask))
3817                         break;
3818
3819                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3820                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3821                                 spin_lock_irqsave(&np->lock, flags);
3822                                 if (!np->in_shutdown)
3823                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3824                                 spin_unlock_irqrestore(&np->lock, flags);
3825                         }
3826                 }
3827
3828                 if (unlikely(i > max_interrupt_work)) {
3829                         spin_lock_irqsave(&np->lock, flags);
3830                         /* disable interrupts on the nic */
3831                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3832                         pci_push(base);
3833
3834                         if (!np->in_shutdown) {
3835                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3836                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3837                         }
3838                         spin_unlock_irqrestore(&np->lock, flags);
3839                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3840                         break;
3841                 }
3842         }
3843         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3844
3845         return IRQ_RETVAL(i);
3846 }
3847
3848 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3849 {
3850         struct net_device *dev = (struct net_device *) data;
3851         struct fe_priv *np = netdev_priv(dev);
3852         u8 __iomem *base = get_hwbase(dev);
3853         u32 events;
3854         int i;
3855         unsigned long flags;
3856
3857         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3858
3859         for (i=0; ; i++) {
3860                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3861                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3862                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3863                 if (!(events & np->irqmask))
3864                         break;
3865
3866                 /* check tx in case we reached max loop limit in tx isr */
3867                 spin_lock_irqsave(&np->lock, flags);
3868                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3869                 spin_unlock_irqrestore(&np->lock, flags);
3870
3871                 if (events & NVREG_IRQ_LINK) {
3872                         spin_lock_irqsave(&np->lock, flags);
3873                         nv_link_irq(dev);
3874                         spin_unlock_irqrestore(&np->lock, flags);
3875                 }
3876                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3877                         spin_lock_irqsave(&np->lock, flags);
3878                         nv_linkchange(dev);
3879                         spin_unlock_irqrestore(&np->lock, flags);
3880                         np->link_timeout = jiffies + LINK_TIMEOUT;
3881                 }
3882                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3883                         spin_lock_irq(&np->lock);
3884                         /* disable interrupts on the nic */
3885                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3886                         pci_push(base);
3887
3888                         if (!np->in_shutdown) {
3889                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3890                                 np->recover_error = 1;
3891                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3892                         }
3893                         spin_unlock_irq(&np->lock);
3894                         break;
3895                 }
3896                 if (unlikely(i > max_interrupt_work)) {
3897                         spin_lock_irqsave(&np->lock, flags);
3898                         /* disable interrupts on the nic */
3899                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3900                         pci_push(base);
3901
3902                         if (!np->in_shutdown) {
3903                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3904                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3905                         }
3906                         spin_unlock_irqrestore(&np->lock, flags);
3907                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3908                         break;
3909                 }
3910
3911         }
3912         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3913
3914         return IRQ_RETVAL(i);
3915 }
3916
3917 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3918 {
3919         struct net_device *dev = (struct net_device *) data;
3920         struct fe_priv *np = netdev_priv(dev);
3921         u8 __iomem *base = get_hwbase(dev);
3922         u32 events;
3923
3924         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3925
3926         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3927                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3928                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3929         } else {
3930                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3931                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3932         }
3933         pci_push(base);
3934         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3935         if (!(events & NVREG_IRQ_TIMER))
3936                 return IRQ_RETVAL(0);
3937
3938         nv_msi_workaround(np);
3939
3940         spin_lock(&np->lock);
3941         np->intr_test = 1;
3942         spin_unlock(&np->lock);
3943
3944         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3945
3946         return IRQ_RETVAL(1);
3947 }
3948
3949 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3950 {
3951         u8 __iomem *base = get_hwbase(dev);
3952         int i;
3953         u32 msixmap = 0;
3954
3955         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3956          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3957          * the remaining 8 interrupts.
3958          */
3959         for (i = 0; i < 8; i++) {
3960                 if ((irqmask >> i) & 0x1) {
3961                         msixmap |= vector << (i << 2);
3962                 }
3963         }
3964         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3965
3966         msixmap = 0;
3967         for (i = 0; i < 8; i++) {
3968                 if ((irqmask >> (i + 8)) & 0x1) {
3969                         msixmap |= vector << (i << 2);
3970                 }
3971         }
3972         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3973 }
3974
3975 static int nv_request_irq(struct net_device *dev, int intr_test)
3976 {
3977         struct fe_priv *np = get_nvpriv(dev);
3978         u8 __iomem *base = get_hwbase(dev);
3979         int ret = 1;
3980         int i;
3981         irqreturn_t (*handler)(int foo, void *data);
3982
3983         if (intr_test) {
3984                 handler = nv_nic_irq_test;
3985         } else {
3986                 if (nv_optimized(np))
3987                         handler = nv_nic_irq_optimized;
3988                 else
3989                         handler = nv_nic_irq;
3990         }
3991
3992         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3993                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3994                         np->msi_x_entry[i].entry = i;
3995                 }
3996                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3997                         np->msi_flags |= NV_MSI_X_ENABLED;
3998                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3999                                 /* Request irq for rx handling */
4000                                 sprintf(np->name_rx, "%s-rx", dev->name);
4001                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
4002                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
4003                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
4004                                         pci_disable_msix(np->pci_dev);
4005                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4006                                         goto out_err;
4007                                 }
4008                                 /* Request irq for tx handling */
4009                                 sprintf(np->name_tx, "%s-tx", dev->name);
4010                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
4011                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
4012                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
4013                                         pci_disable_msix(np->pci_dev);
4014                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4015                                         goto out_free_rx;
4016                                 }
4017                                 /* Request irq for link and timer handling */
4018                                 sprintf(np->name_other, "%s-other", dev->name);
4019                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
4020                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
4021                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
4022                                         pci_disable_msix(np->pci_dev);
4023                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4024                                         goto out_free_tx;
4025                                 }
4026                                 /* map interrupts to their respective vector */
4027                                 writel(0, base + NvRegMSIXMap0);
4028                                 writel(0, base + NvRegMSIXMap1);
4029                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4030                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4031                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4032                         } else {
4033                                 /* Request irq for all interrupts */
4034                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
4035                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4036                                         pci_disable_msix(np->pci_dev);
4037                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4038                                         goto out_err;
4039                                 }
4040
4041                                 /* map interrupts to vector 0 */
4042                                 writel(0, base + NvRegMSIXMap0);
4043                                 writel(0, base + NvRegMSIXMap1);
4044                         }
4045                 }
4046         }
4047         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4048                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
4049                         np->msi_flags |= NV_MSI_ENABLED;
4050                         dev->irq = np->pci_dev->irq;
4051                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4052                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
4053                                 pci_disable_msi(np->pci_dev);
4054                                 np->msi_flags &= ~NV_MSI_ENABLED;
4055                                 dev->irq = np->pci_dev->irq;
4056                                 goto out_err;
4057                         }
4058
4059                         /* map interrupts to vector 0 */
4060                         writel(0, base + NvRegMSIMap0);
4061                         writel(0, base + NvRegMSIMap1);
4062                         /* enable msi vector 0 */
4063                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4064                 }
4065         }
4066         if (ret != 0) {
4067                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4068                         goto out_err;
4069
4070         }
4071
4072         return 0;
4073 out_free_tx:
4074         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4075 out_free_rx:
4076         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4077 out_err:
4078         return 1;
4079 }
4080
4081 static void nv_free_irq(struct net_device *dev)
4082 {
4083         struct fe_priv *np = get_nvpriv(dev);
4084         int i;
4085
4086         if (np->msi_flags & NV_MSI_X_ENABLED) {
4087                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4088                         free_irq(np->msi_x_entry[i].vector, dev);
4089                 }
4090                 pci_disable_msix(np->pci_dev);
4091                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4092         } else {
4093                 free_irq(np->pci_dev->irq, dev);
4094                 if (np->msi_flags & NV_MSI_ENABLED) {
4095                         pci_disable_msi(np->pci_dev);
4096                         np->msi_flags &= ~NV_MSI_ENABLED;
4097                 }
4098         }
4099 }
4100
4101 static void nv_do_nic_poll(unsigned long data)
4102 {
4103         struct net_device *dev = (struct net_device *) data;
4104         struct fe_priv *np = netdev_priv(dev);
4105         u8 __iomem *base = get_hwbase(dev);
4106         u32 mask = 0;
4107
4108         /*
4109          * First disable irq(s) and then
4110          * reenable interrupts on the nic, we have to do this before calling
4111          * nv_nic_irq because that may decide to do otherwise
4112          */
4113
4114         if (!using_multi_irqs(dev)) {
4115                 if (np->msi_flags & NV_MSI_X_ENABLED)
4116                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4117                 else
4118                         disable_irq_lockdep(np->pci_dev->irq);
4119                 mask = np->irqmask;
4120         } else {
4121                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4122                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4123                         mask |= NVREG_IRQ_RX_ALL;
4124                 }
4125                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4126                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4127                         mask |= NVREG_IRQ_TX_ALL;
4128                 }
4129                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4130                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4131                         mask |= NVREG_IRQ_OTHER;
4132                 }
4133         }
4134         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4135
4136         if (np->recover_error) {
4137                 np->recover_error = 0;
4138                 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
4139                 if (netif_running(dev)) {
4140                         netif_tx_lock_bh(dev);
4141                         netif_addr_lock(dev);
4142                         spin_lock(&np->lock);
4143                         /* stop engines */
4144                         nv_stop_rxtx(dev);
4145                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4146                                 nv_mac_reset(dev);
4147                         nv_txrx_reset(dev);
4148                         /* drain rx queue */
4149                         nv_drain_rxtx(dev);
4150                         /* reinit driver view of the rx queue */
4151                         set_bufsize(dev);
4152                         if (nv_init_ring(dev)) {
4153                                 if (!np->in_shutdown)
4154                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4155                         }
4156                         /* reinit nic view of the rx queue */
4157                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4158                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4159                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4160                                 base + NvRegRingSizes);
4161                         pci_push(base);
4162                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4163                         pci_push(base);
4164                         /* clear interrupts */
4165                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4166                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4167                         else
4168                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4169
4170                         /* restart rx engine */
4171                         nv_start_rxtx(dev);
4172                         spin_unlock(&np->lock);
4173                         netif_addr_unlock(dev);
4174                         netif_tx_unlock_bh(dev);
4175                 }
4176         }
4177
4178         writel(mask, base + NvRegIrqMask);
4179         pci_push(base);
4180
4181         if (!using_multi_irqs(dev)) {
4182                 np->nic_poll_irq = 0;
4183                 if (nv_optimized(np))
4184                         nv_nic_irq_optimized(0, dev);
4185                 else
4186                         nv_nic_irq(0, dev);
4187                 if (np->msi_flags & NV_MSI_X_ENABLED)
4188                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4189                 else
4190                         enable_irq_lockdep(np->pci_dev->irq);
4191         } else {
4192                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4193                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4194                         nv_nic_irq_rx(0, dev);
4195                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4196                 }
4197                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4198                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4199                         nv_nic_irq_tx(0, dev);
4200                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4201                 }
4202                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4203                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4204                         nv_nic_irq_other(0, dev);
4205                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4206                 }
4207         }
4208
4209 }
4210
4211 #ifdef CONFIG_NET_POLL_CONTROLLER
4212 static void nv_poll_controller(struct net_device *dev)
4213 {
4214         nv_do_nic_poll((unsigned long) dev);
4215 }
4216 #endif
4217
4218 static void nv_do_stats_poll(unsigned long data)
4219 {
4220         struct net_device *dev = (struct net_device *) data;
4221         struct fe_priv *np = netdev_priv(dev);
4222
4223         nv_get_hw_stats(dev);
4224
4225         if (!np->in_shutdown)
4226                 mod_timer(&np->stats_poll,
4227                         round_jiffies(jiffies + STATS_INTERVAL));
4228 }
4229
4230 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4231 {
4232         struct fe_priv *np = netdev_priv(dev);
4233         strcpy(info->driver, DRV_NAME);
4234         strcpy(info->version, FORCEDETH_VERSION);
4235         strcpy(info->bus_info, pci_name(np->pci_dev));
4236 }
4237
4238 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4239 {
4240         struct fe_priv *np = netdev_priv(dev);
4241         wolinfo->supported = WAKE_MAGIC;
4242
4243         spin_lock_irq(&np->lock);
4244         if (np->wolenabled)
4245                 wolinfo->wolopts = WAKE_MAGIC;
4246         spin_unlock_irq(&np->lock);
4247 }
4248
4249 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4250 {
4251         struct fe_priv *np = netdev_priv(dev);
4252         u8 __iomem *base = get_hwbase(dev);
4253         u32 flags = 0;
4254
4255         if (wolinfo->wolopts == 0) {
4256                 np->wolenabled = 0;
4257         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4258                 np->wolenabled = 1;
4259                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4260         }
4261         if (netif_running(dev)) {
4262                 spin_lock_irq(&np->lock);
4263                 writel(flags, base + NvRegWakeUpFlags);
4264                 spin_unlock_irq(&np->lock);
4265         }
4266         return 0;
4267 }
4268
4269 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4270 {
4271         struct fe_priv *np = netdev_priv(dev);
4272         int adv;
4273
4274         spin_lock_irq(&np->lock);
4275         ecmd->port = PORT_MII;
4276         if (!netif_running(dev)) {
4277                 /* We do not track link speed / duplex setting if the
4278                  * interface is disabled. Force a link check */
4279                 if (nv_update_linkspeed(dev)) {
4280                         if (!netif_carrier_ok(dev))
4281                                 netif_carrier_on(dev);
4282                 } else {
4283                         if (netif_carrier_ok(dev))
4284                                 netif_carrier_off(dev);
4285                 }
4286         }
4287
4288         if (netif_carrier_ok(dev)) {
4289                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4290                 case NVREG_LINKSPEED_10:
4291                         ecmd->speed = SPEED_10;
4292                         break;
4293                 case NVREG_LINKSPEED_100:
4294                         ecmd->speed = SPEED_100;
4295                         break;
4296                 case NVREG_LINKSPEED_1000:
4297                         ecmd->speed = SPEED_1000;
4298                         break;
4299                 }
4300                 ecmd->duplex = DUPLEX_HALF;
4301                 if (np->duplex)
4302                         ecmd->duplex = DUPLEX_FULL;
4303         } else {
4304                 ecmd->speed = -1;
4305                 ecmd->duplex = -1;
4306         }
4307
4308         ecmd->autoneg = np->autoneg;
4309
4310         ecmd->advertising = ADVERTISED_MII;
4311         if (np->autoneg) {
4312                 ecmd->advertising |= ADVERTISED_Autoneg;
4313                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4314                 if (adv & ADVERTISE_10HALF)
4315                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4316                 if (adv & ADVERTISE_10FULL)
4317                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4318                 if (adv & ADVERTISE_100HALF)
4319                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4320                 if (adv & ADVERTISE_100FULL)
4321                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4322                 if (np->gigabit == PHY_GIGABIT) {
4323                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4324                         if (adv & ADVERTISE_1000FULL)
4325                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4326                 }
4327         }
4328         ecmd->supported = (SUPPORTED_Autoneg |
4329                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4330                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4331                 SUPPORTED_MII);
4332         if (np->gigabit == PHY_GIGABIT)
4333                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4334
4335         ecmd->phy_address = np->phyaddr;
4336         ecmd->transceiver = XCVR_EXTERNAL;
4337
4338         /* ignore maxtxpkt, maxrxpkt for now */
4339         spin_unlock_irq(&np->lock);
4340         return 0;
4341 }
4342
4343 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4344 {
4345         struct fe_priv *np = netdev_priv(dev);
4346
4347         if (ecmd->port != PORT_MII)
4348                 return -EINVAL;
4349         if (ecmd->transceiver != XCVR_EXTERNAL)
4350                 return -EINVAL;
4351         if (ecmd->phy_address != np->phyaddr) {
4352                 /* TODO: support switching between multiple phys. Should be
4353                  * trivial, but not enabled due to lack of test hardware. */
4354                 return -EINVAL;
4355         }
4356         if (ecmd->autoneg == AUTONEG_ENABLE) {
4357                 u32 mask;
4358
4359                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4360                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4361                 if (np->gigabit == PHY_GIGABIT)
4362                         mask |= ADVERTISED_1000baseT_Full;
4363
4364                 if ((ecmd->advertising & mask) == 0)
4365                         return -EINVAL;
4366
4367         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4368                 /* Note: autonegotiation disable, speed 1000 intentionally
4369                  * forbidden - noone should need that. */
4370
4371                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4372                         return -EINVAL;
4373                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4374                         return -EINVAL;
4375         } else {
4376                 return -EINVAL;
4377         }
4378
4379         netif_carrier_off(dev);
4380         if (netif_running(dev)) {
4381                 unsigned long flags;
4382
4383                 nv_disable_irq(dev);
4384                 netif_tx_lock_bh(dev);
4385                 netif_addr_lock(dev);
4386                 /* with plain spinlock lockdep complains */
4387                 spin_lock_irqsave(&np->lock, flags);
4388                 /* stop engines */
4389                 /* FIXME:
4390                  * this can take some time, and interrupts are disabled
4391                  * due to spin_lock_irqsave, but let's hope no daemon
4392                  * is going to change the settings very often...
4393                  * Worst case:
4394                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4395                  * + some minor delays, which is up to a second approximately
4396                  */
4397                 nv_stop_rxtx(dev);
4398                 spin_unlock_irqrestore(&np->lock, flags);
4399                 netif_addr_unlock(dev);
4400                 netif_tx_unlock_bh(dev);
4401         }
4402
4403         if (ecmd->autoneg == AUTONEG_ENABLE) {
4404                 int adv, bmcr;
4405
4406                 np->autoneg = 1;
4407
4408                 /* advertise only what has been requested */
4409                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4410                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4411                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4412                         adv |= ADVERTISE_10HALF;
4413                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4414                         adv |= ADVERTISE_10FULL;
4415                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4416                         adv |= ADVERTISE_100HALF;
4417                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4418                         adv |= ADVERTISE_100FULL;
4419                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4420                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4421                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4422                         adv |=  ADVERTISE_PAUSE_ASYM;
4423                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4424
4425                 if (np->gigabit == PHY_GIGABIT) {
4426                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4427                         adv &= ~ADVERTISE_1000FULL;
4428                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4429                                 adv |= ADVERTISE_1000FULL;
4430                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4431                 }
4432
4433                 if (netif_running(dev))
4434                         printk(KERN_INFO "%s: link down.\n", dev->name);
4435                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4436                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4437                         bmcr |= BMCR_ANENABLE;
4438                         /* reset the phy in order for settings to stick,
4439                          * and cause autoneg to start */
4440                         if (phy_reset(dev, bmcr)) {
4441                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4442                                 return -EINVAL;
4443                         }
4444                 } else {
4445                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4446                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4447                 }
4448         } else {
4449                 int adv, bmcr;
4450
4451                 np->autoneg = 0;
4452
4453                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4454                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4455                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4456                         adv |= ADVERTISE_10HALF;
4457                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4458                         adv |= ADVERTISE_10FULL;
4459                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4460                         adv |= ADVERTISE_100HALF;
4461                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4462                         adv |= ADVERTISE_100FULL;
4463                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4464                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4465                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4466                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4467                 }
4468                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4469                         adv |=  ADVERTISE_PAUSE_ASYM;
4470                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4471                 }
4472                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4473                 np->fixed_mode = adv;
4474
4475                 if (np->gigabit == PHY_GIGABIT) {
4476                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4477                         adv &= ~ADVERTISE_1000FULL;
4478                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4479                 }
4480
4481                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4482                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4483                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4484                         bmcr |= BMCR_FULLDPLX;
4485                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4486                         bmcr |= BMCR_SPEED100;
4487                 if (np->phy_oui == PHY_OUI_MARVELL) {
4488                         /* reset the phy in order for forced mode settings to stick */
4489                         if (phy_reset(dev, bmcr)) {
4490                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4491                                 return -EINVAL;
4492                         }
4493                 } else {
4494                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4495                         if (netif_running(dev)) {
4496                                 /* Wait a bit and then reconfigure the nic. */
4497                                 udelay(10);
4498                                 nv_linkchange(dev);
4499                         }
4500                 }
4501         }
4502
4503         if (netif_running(dev)) {
4504                 nv_start_rxtx(dev);
4505                 nv_enable_irq(dev);
4506         }
4507
4508         return 0;
4509 }
4510
4511 #define FORCEDETH_REGS_VER      1
4512
4513 static int nv_get_regs_len(struct net_device *dev)
4514 {
4515         struct fe_priv *np = netdev_priv(dev);
4516         return np->register_size;
4517 }
4518
4519 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4520 {
4521         struct fe_priv *np = netdev_priv(dev);
4522         u8 __iomem *base = get_hwbase(dev);
4523         u32 *rbuf = buf;
4524         int i;
4525
4526         regs->version = FORCEDETH_REGS_VER;
4527         spin_lock_irq(&np->lock);
4528         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4529                 rbuf[i] = readl(base + i*sizeof(u32));
4530         spin_unlock_irq(&np->lock);
4531 }
4532
4533 static int nv_nway_reset(struct net_device *dev)
4534 {
4535         struct fe_priv *np = netdev_priv(dev);
4536         int ret;
4537
4538         if (np->autoneg) {
4539                 int bmcr;
4540
4541                 netif_carrier_off(dev);
4542                 if (netif_running(dev)) {
4543                         nv_disable_irq(dev);
4544                         netif_tx_lock_bh(dev);
4545                         netif_addr_lock(dev);
4546                         spin_lock(&np->lock);
4547                         /* stop engines */
4548                         nv_stop_rxtx(dev);
4549                         spin_unlock(&np->lock);
4550                         netif_addr_unlock(dev);
4551                         netif_tx_unlock_bh(dev);
4552                         printk(KERN_INFO "%s: link down.\n", dev->name);
4553                 }
4554
4555                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4556                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4557                         bmcr |= BMCR_ANENABLE;
4558                         /* reset the phy in order for settings to stick*/
4559                         if (phy_reset(dev, bmcr)) {
4560                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4561                                 return -EINVAL;
4562                         }
4563                 } else {
4564                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4565                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4566                 }
4567
4568                 if (netif_running(dev)) {
4569                         nv_start_rxtx(dev);
4570                         nv_enable_irq(dev);
4571                 }
4572                 ret = 0;
4573         } else {
4574                 ret = -EINVAL;
4575         }
4576
4577         return ret;
4578 }
4579
4580 static int nv_set_tso(struct net_device *dev, u32 value)
4581 {
4582         struct fe_priv *np = netdev_priv(dev);
4583
4584         if ((np->driver_data & DEV_HAS_CHECKSUM))
4585                 return ethtool_op_set_tso(dev, value);
4586         else
4587                 return -EOPNOTSUPP;
4588 }
4589
4590 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4591 {
4592         struct fe_priv *np = netdev_priv(dev);
4593
4594         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4595         ring->rx_mini_max_pending = 0;
4596         ring->rx_jumbo_max_pending = 0;
4597         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4598
4599         ring->rx_pending = np->rx_ring_size;
4600         ring->rx_mini_pending = 0;
4601         ring->rx_jumbo_pending = 0;
4602         ring->tx_pending = np->tx_ring_size;
4603 }
4604
4605 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4606 {
4607         struct fe_priv *np = netdev_priv(dev);
4608         u8 __iomem *base = get_hwbase(dev);
4609         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4610         dma_addr_t ring_addr;
4611
4612         if (ring->rx_pending < RX_RING_MIN ||
4613             ring->tx_pending < TX_RING_MIN ||
4614             ring->rx_mini_pending != 0 ||
4615             ring->rx_jumbo_pending != 0 ||
4616             (np->desc_ver == DESC_VER_1 &&
4617              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4618               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4619             (np->desc_ver != DESC_VER_1 &&
4620              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4621               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4622                 return -EINVAL;
4623         }
4624
4625         /* allocate new rings */
4626         if (!nv_optimized(np)) {
4627                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4628                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4629                                             &ring_addr);
4630         } else {
4631                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4632                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4633                                             &ring_addr);
4634         }
4635         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4636         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4637         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4638                 /* fall back to old rings */
4639                 if (!nv_optimized(np)) {
4640                         if (rxtx_ring)
4641                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4642                                                     rxtx_ring, ring_addr);
4643                 } else {
4644                         if (rxtx_ring)
4645                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4646                                                     rxtx_ring, ring_addr);
4647                 }
4648                 if (rx_skbuff)
4649                         kfree(rx_skbuff);
4650                 if (tx_skbuff)
4651                         kfree(tx_skbuff);
4652                 goto exit;
4653         }
4654
4655         if (netif_running(dev)) {
4656                 nv_disable_irq(dev);
4657                 nv_napi_disable(dev);
4658                 netif_tx_lock_bh(dev);
4659                 netif_addr_lock(dev);
4660                 spin_lock(&np->lock);
4661                 /* stop engines */
4662                 nv_stop_rxtx(dev);
4663                 nv_txrx_reset(dev);
4664                 /* drain queues */
4665                 nv_drain_rxtx(dev);
4666                 /* delete queues */
4667                 free_rings(dev);
4668         }
4669
4670         /* set new values */
4671         np->rx_ring_size = ring->rx_pending;
4672         np->tx_ring_size = ring->tx_pending;
4673
4674         if (!nv_optimized(np)) {
4675                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4676                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4677         } else {
4678                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4679                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4680         }
4681         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4682         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4683         np->ring_addr = ring_addr;
4684
4685         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4686         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4687
4688         if (netif_running(dev)) {
4689                 /* reinit driver view of the queues */
4690                 set_bufsize(dev);
4691                 if (nv_init_ring(dev)) {
4692                         if (!np->in_shutdown)
4693                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4694                 }
4695
4696                 /* reinit nic view of the queues */
4697                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4698                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4699                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4700                         base + NvRegRingSizes);
4701                 pci_push(base);
4702                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4703                 pci_push(base);
4704
4705                 /* restart engines */
4706                 nv_start_rxtx(dev);
4707                 spin_unlock(&np->lock);
4708                 netif_addr_unlock(dev);
4709                 netif_tx_unlock_bh(dev);
4710                 nv_napi_enable(dev);
4711                 nv_enable_irq(dev);
4712         }
4713         return 0;
4714 exit:
4715         return -ENOMEM;
4716 }
4717
4718 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4719 {
4720         struct fe_priv *np = netdev_priv(dev);
4721
4722         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4723         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4724         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4725 }
4726
4727 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4728 {
4729         struct fe_priv *np = netdev_priv(dev);
4730         int adv, bmcr;
4731
4732         if ((!np->autoneg && np->duplex == 0) ||
4733             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4734                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4735                        dev->name);
4736                 return -EINVAL;
4737         }
4738         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4739                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4740                 return -EINVAL;
4741         }
4742
4743         netif_carrier_off(dev);
4744         if (netif_running(dev)) {
4745                 nv_disable_irq(dev);
4746                 netif_tx_lock_bh(dev);
4747                 netif_addr_lock(dev);
4748                 spin_lock(&np->lock);
4749                 /* stop engines */
4750                 nv_stop_rxtx(dev);
4751                 spin_unlock(&np->lock);
4752                 netif_addr_unlock(dev);
4753                 netif_tx_unlock_bh(dev);
4754         }
4755
4756         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4757         if (pause->rx_pause)
4758                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4759         if (pause->tx_pause)
4760                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4761
4762         if (np->autoneg && pause->autoneg) {
4763                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4764
4765                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4766                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4767                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4768                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4769                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4770                         adv |=  ADVERTISE_PAUSE_ASYM;
4771                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4772
4773                 if (netif_running(dev))
4774                         printk(KERN_INFO "%s: link down.\n", dev->name);
4775                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4776                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4777                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4778         } else {
4779                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4780                 if (pause->rx_pause)
4781                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4782                 if (pause->tx_pause)
4783                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4784
4785                 if (!netif_running(dev))
4786                         nv_update_linkspeed(dev);
4787                 else
4788                         nv_update_pause(dev, np->pause_flags);
4789         }
4790
4791         if (netif_running(dev)) {
4792                 nv_start_rxtx(dev);
4793                 nv_enable_irq(dev);
4794         }
4795         return 0;
4796 }
4797
4798 static u32 nv_get_rx_csum(struct net_device *dev)
4799 {
4800         struct fe_priv *np = netdev_priv(dev);
4801         return (np->rx_csum) != 0;
4802 }
4803
4804 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4805 {
4806         struct fe_priv *np = netdev_priv(dev);
4807         u8 __iomem *base = get_hwbase(dev);
4808         int retcode = 0;
4809
4810         if (np->driver_data & DEV_HAS_CHECKSUM) {
4811                 if (data) {
4812                         np->rx_csum = 1;
4813                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4814                 } else {
4815                         np->rx_csum = 0;
4816                         /* vlan is dependent on rx checksum offload */
4817                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4818                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4819                 }
4820                 if (netif_running(dev)) {
4821                         spin_lock_irq(&np->lock);
4822                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4823                         spin_unlock_irq(&np->lock);
4824                 }
4825         } else {
4826                 return -EINVAL;
4827         }
4828
4829         return retcode;
4830 }
4831
4832 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4833 {
4834         struct fe_priv *np = netdev_priv(dev);
4835
4836         if (np->driver_data & DEV_HAS_CHECKSUM)
4837                 return ethtool_op_set_tx_csum(dev, data);
4838         else
4839                 return -EOPNOTSUPP;
4840 }
4841
4842 static int nv_set_sg(struct net_device *dev, u32 data)
4843 {
4844         struct fe_priv *np = netdev_priv(dev);
4845
4846         if (np->driver_data & DEV_HAS_CHECKSUM)
4847                 return ethtool_op_set_sg(dev, data);
4848         else
4849                 return -EOPNOTSUPP;
4850 }
4851
4852 static int nv_get_sset_count(struct net_device *dev, int sset)
4853 {
4854         struct fe_priv *np = netdev_priv(dev);
4855
4856         switch (sset) {
4857         case ETH_SS_TEST:
4858                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4859                         return NV_TEST_COUNT_EXTENDED;
4860                 else
4861                         return NV_TEST_COUNT_BASE;
4862         case ETH_SS_STATS:
4863                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4864                         return NV_DEV_STATISTICS_V3_COUNT;
4865                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4866                         return NV_DEV_STATISTICS_V2_COUNT;
4867                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4868                         return NV_DEV_STATISTICS_V1_COUNT;
4869                 else
4870                         return 0;
4871         default:
4872                 return -EOPNOTSUPP;
4873         }
4874 }
4875
4876 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4877 {
4878         struct fe_priv *np = netdev_priv(dev);
4879
4880         /* update stats */
4881         nv_do_stats_poll((unsigned long)dev);
4882
4883         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4884 }
4885
4886 static int nv_link_test(struct net_device *dev)
4887 {
4888         struct fe_priv *np = netdev_priv(dev);
4889         int mii_status;
4890
4891         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4892         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4893
4894         /* check phy link status */
4895         if (!(mii_status & BMSR_LSTATUS))
4896                 return 0;
4897         else
4898                 return 1;
4899 }
4900
4901 static int nv_register_test(struct net_device *dev)
4902 {
4903         u8 __iomem *base = get_hwbase(dev);
4904         int i = 0;
4905         u32 orig_read, new_read;
4906
4907         do {
4908                 orig_read = readl(base + nv_registers_test[i].reg);
4909
4910                 /* xor with mask to toggle bits */
4911                 orig_read ^= nv_registers_test[i].mask;
4912
4913                 writel(orig_read, base + nv_registers_test[i].reg);
4914
4915                 new_read = readl(base + nv_registers_test[i].reg);
4916
4917                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4918                         return 0;
4919
4920                 /* restore original value */
4921                 orig_read ^= nv_registers_test[i].mask;
4922                 writel(orig_read, base + nv_registers_test[i].reg);
4923
4924         } while (nv_registers_test[++i].reg != 0);
4925
4926         return 1;
4927 }
4928
4929 static int nv_interrupt_test(struct net_device *dev)
4930 {
4931         struct fe_priv *np = netdev_priv(dev);
4932         u8 __iomem *base = get_hwbase(dev);
4933         int ret = 1;
4934         int testcnt;
4935         u32 save_msi_flags, save_poll_interval = 0;
4936
4937         if (netif_running(dev)) {
4938                 /* free current irq */
4939                 nv_free_irq(dev);
4940                 save_poll_interval = readl(base+NvRegPollingInterval);
4941         }
4942
4943         /* flag to test interrupt handler */
4944         np->intr_test = 0;
4945
4946         /* setup test irq */
4947         save_msi_flags = np->msi_flags;
4948         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4949         np->msi_flags |= 0x001; /* setup 1 vector */
4950         if (nv_request_irq(dev, 1))
4951                 return 0;
4952
4953         /* setup timer interrupt */
4954         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4955         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4956
4957         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4958
4959         /* wait for at least one interrupt */
4960         msleep(100);
4961
4962         spin_lock_irq(&np->lock);
4963
4964         /* flag should be set within ISR */
4965         testcnt = np->intr_test;
4966         if (!testcnt)
4967                 ret = 2;
4968
4969         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4970         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4971                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4972         else
4973                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4974
4975         spin_unlock_irq(&np->lock);
4976
4977         nv_free_irq(dev);
4978
4979         np->msi_flags = save_msi_flags;
4980
4981         if (netif_running(dev)) {
4982                 writel(save_poll_interval, base + NvRegPollingInterval);
4983                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4984                 /* restore original irq */
4985                 if (nv_request_irq(dev, 0))
4986                         return 0;
4987         }
4988
4989         return ret;
4990 }
4991
4992 static int nv_loopback_test(struct net_device *dev)
4993 {
4994         struct fe_priv *np = netdev_priv(dev);
4995         u8 __iomem *base = get_hwbase(dev);
4996         struct sk_buff *tx_skb, *rx_skb;
4997         dma_addr_t test_dma_addr;
4998         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4999         u32 flags;
5000         int len, i, pkt_len;
5001         u8 *pkt_data;
5002         u32 filter_flags = 0;
5003         u32 misc1_flags = 0;
5004         int ret = 1;
5005
5006         if (netif_running(dev)) {
5007                 nv_disable_irq(dev);
5008                 filter_flags = readl(base + NvRegPacketFilterFlags);
5009                 misc1_flags = readl(base + NvRegMisc1);
5010         } else {
5011                 nv_txrx_reset(dev);
5012         }
5013
5014         /* reinit driver view of the rx queue */
5015         set_bufsize(dev);
5016         nv_init_ring(dev);
5017
5018         /* setup hardware for loopback */
5019         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5020         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5021
5022         /* reinit nic view of the rx queue */
5023         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5024         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5025         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5026                 base + NvRegRingSizes);
5027         pci_push(base);
5028
5029         /* restart rx engine */
5030         nv_start_rxtx(dev);
5031
5032         /* setup packet for tx */
5033         pkt_len = ETH_DATA_LEN;
5034         tx_skb = dev_alloc_skb(pkt_len);
5035         if (!tx_skb) {
5036                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
5037                          " of %s\n", dev->name);
5038                 ret = 0;
5039                 goto out;
5040         }
5041         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5042                                        skb_tailroom(tx_skb),
5043                                        PCI_DMA_FROMDEVICE);
5044         pkt_data = skb_put(tx_skb, pkt_len);
5045         for (i = 0; i < pkt_len; i++)
5046                 pkt_data[i] = (u8)(i & 0xff);
5047
5048         if (!nv_optimized(np)) {
5049                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5050                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5051         } else {
5052                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5053                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5054                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5055         }
5056         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5057         pci_push(get_hwbase(dev));
5058
5059         msleep(500);
5060
5061         /* check for rx of the packet */
5062         if (!nv_optimized(np)) {
5063                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5064                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5065
5066         } else {
5067                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5068                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5069         }
5070
5071         if (flags & NV_RX_AVAIL) {
5072                 ret = 0;
5073         } else if (np->desc_ver == DESC_VER_1) {
5074                 if (flags & NV_RX_ERROR)
5075                         ret = 0;
5076         } else {
5077                 if (flags & NV_RX2_ERROR) {
5078                         ret = 0;
5079                 }
5080         }
5081
5082         if (ret) {
5083                 if (len != pkt_len) {
5084                         ret = 0;
5085                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5086                                 dev->name, len, pkt_len);
5087                 } else {
5088                         rx_skb = np->rx_skb[0].skb;
5089                         for (i = 0; i < pkt_len; i++) {
5090                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5091                                         ret = 0;
5092                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5093                                                 dev->name, i);
5094                                         break;
5095                                 }
5096                         }
5097                 }
5098         } else {
5099                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5100         }
5101
5102         pci_unmap_single(np->pci_dev, test_dma_addr,
5103                        (skb_end_pointer(tx_skb) - tx_skb->data),
5104                        PCI_DMA_TODEVICE);
5105         dev_kfree_skb_any(tx_skb);
5106  out:
5107         /* stop engines */
5108         nv_stop_rxtx(dev);
5109         nv_txrx_reset(dev);
5110         /* drain rx queue */
5111         nv_drain_rxtx(dev);
5112
5113         if (netif_running(dev)) {
5114                 writel(misc1_flags, base + NvRegMisc1);
5115                 writel(filter_flags, base + NvRegPacketFilterFlags);
5116                 nv_enable_irq(dev);
5117         }
5118
5119         return ret;
5120 }
5121
5122 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5123 {
5124         struct fe_priv *np = netdev_priv(dev);
5125         u8 __iomem *base = get_hwbase(dev);
5126         int result;
5127         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5128
5129         if (!nv_link_test(dev)) {
5130                 test->flags |= ETH_TEST_FL_FAILED;
5131                 buffer[0] = 1;
5132         }
5133
5134         if (test->flags & ETH_TEST_FL_OFFLINE) {
5135                 if (netif_running(dev)) {
5136                         netif_stop_queue(dev);
5137                         nv_napi_disable(dev);
5138                         netif_tx_lock_bh(dev);
5139                         netif_addr_lock(dev);
5140                         spin_lock_irq(&np->lock);
5141                         nv_disable_hw_interrupts(dev, np->irqmask);
5142                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5143                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5144                         } else {
5145                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5146                         }
5147                         /* stop engines */
5148                         nv_stop_rxtx(dev);
5149                         nv_txrx_reset(dev);
5150                         /* drain rx queue */
5151                         nv_drain_rxtx(dev);
5152                         spin_unlock_irq(&np->lock);
5153                         netif_addr_unlock(dev);
5154                         netif_tx_unlock_bh(dev);
5155                 }
5156
5157                 if (!nv_register_test(dev)) {
5158                         test->flags |= ETH_TEST_FL_FAILED;
5159                         buffer[1] = 1;
5160                 }
5161
5162                 result = nv_interrupt_test(dev);
5163                 if (result != 1) {
5164                         test->flags |= ETH_TEST_FL_FAILED;
5165                         buffer[2] = 1;
5166                 }
5167                 if (result == 0) {
5168                         /* bail out */
5169                         return;
5170                 }
5171
5172                 if (!nv_loopback_test(dev)) {
5173                         test->flags |= ETH_TEST_FL_FAILED;
5174                         buffer[3] = 1;
5175                 }
5176
5177                 if (netif_running(dev)) {
5178                         /* reinit driver view of the rx queue */
5179                         set_bufsize(dev);
5180                         if (nv_init_ring(dev)) {
5181                                 if (!np->in_shutdown)
5182                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5183                         }
5184                         /* reinit nic view of the rx queue */
5185                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5186                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5187                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5188                                 base + NvRegRingSizes);
5189                         pci_push(base);
5190                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5191                         pci_push(base);
5192                         /* restart rx engine */
5193                         nv_start_rxtx(dev);
5194                         netif_start_queue(dev);
5195                         nv_napi_enable(dev);
5196                         nv_enable_hw_interrupts(dev, np->irqmask);
5197                 }
5198         }
5199 }
5200
5201 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5202 {
5203         switch (stringset) {
5204         case ETH_SS_STATS:
5205                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5206                 break;
5207         case ETH_SS_TEST:
5208                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5209                 break;
5210         }
5211 }
5212
5213 static const struct ethtool_ops ops = {
5214         .get_drvinfo = nv_get_drvinfo,
5215         .get_link = ethtool_op_get_link,
5216         .get_wol = nv_get_wol,
5217         .set_wol = nv_set_wol,
5218         .get_settings = nv_get_settings,
5219         .set_settings = nv_set_settings,
5220         .get_regs_len = nv_get_regs_len,
5221         .get_regs = nv_get_regs,
5222         .nway_reset = nv_nway_reset,
5223         .set_tso = nv_set_tso,
5224         .get_ringparam = nv_get_ringparam,
5225         .set_ringparam = nv_set_ringparam,
5226         .get_pauseparam = nv_get_pauseparam,
5227         .set_pauseparam = nv_set_pauseparam,
5228         .get_rx_csum = nv_get_rx_csum,
5229         .set_rx_csum = nv_set_rx_csum,
5230         .set_tx_csum = nv_set_tx_csum,
5231         .set_sg = nv_set_sg,
5232         .get_strings = nv_get_strings,
5233         .get_ethtool_stats = nv_get_ethtool_stats,
5234         .get_sset_count = nv_get_sset_count,
5235         .self_test = nv_self_test,
5236 };
5237
5238 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5239 {
5240         struct fe_priv *np = get_nvpriv(dev);
5241
5242         spin_lock_irq(&np->lock);
5243
5244         /* save vlan group */
5245         np->vlangrp = grp;
5246
5247         if (grp) {
5248                 /* enable vlan on MAC */
5249                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5250         } else {
5251                 /* disable vlan on MAC */
5252                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5253                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5254         }
5255
5256         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5257
5258         spin_unlock_irq(&np->lock);
5259 }
5260
5261 /* The mgmt unit and driver use a semaphore to access the phy during init */
5262 static int nv_mgmt_acquire_sema(struct net_device *dev)
5263 {
5264         struct fe_priv *np = netdev_priv(dev);
5265         u8 __iomem *base = get_hwbase(dev);
5266         int i;
5267         u32 tx_ctrl, mgmt_sema;
5268
5269         for (i = 0; i < 10; i++) {
5270                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5271                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5272                         break;
5273                 msleep(500);
5274         }
5275
5276         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5277                 return 0;
5278
5279         for (i = 0; i < 2; i++) {
5280                 tx_ctrl = readl(base + NvRegTransmitterControl);
5281                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5282                 writel(tx_ctrl, base + NvRegTransmitterControl);
5283
5284                 /* verify that semaphore was acquired */
5285                 tx_ctrl = readl(base + NvRegTransmitterControl);
5286                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5287                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5288                         np->mgmt_sema = 1;
5289                         return 1;
5290                 }
5291                 else
5292                         udelay(50);
5293         }
5294
5295         return 0;
5296 }
5297
5298 static void nv_mgmt_release_sema(struct net_device *dev)
5299 {
5300         struct fe_priv *np = netdev_priv(dev);
5301         u8 __iomem *base = get_hwbase(dev);
5302         u32 tx_ctrl;
5303
5304         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5305                 if (np->mgmt_sema) {
5306                         tx_ctrl = readl(base + NvRegTransmitterControl);
5307                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5308                         writel(tx_ctrl, base + NvRegTransmitterControl);
5309                 }
5310         }
5311 }
5312
5313
5314 static int nv_mgmt_get_version(struct net_device *dev)
5315 {
5316         struct fe_priv *np = netdev_priv(dev);
5317         u8 __iomem *base = get_hwbase(dev);
5318         u32 data_ready = readl(base + NvRegTransmitterControl);
5319         u32 data_ready2 = 0;
5320         unsigned long start;
5321         int ready = 0;
5322
5323         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5324         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5325         start = jiffies;
5326         while (time_before(jiffies, start + 5*HZ)) {
5327                 data_ready2 = readl(base + NvRegTransmitterControl);
5328                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5329                         ready = 1;
5330                         break;
5331                 }
5332                 schedule_timeout_uninterruptible(1);
5333         }
5334
5335         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5336                 return 0;
5337
5338         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5339
5340         return 1;
5341 }
5342
5343 static int nv_open(struct net_device *dev)
5344 {
5345         struct fe_priv *np = netdev_priv(dev);
5346         u8 __iomem *base = get_hwbase(dev);
5347         int ret = 1;
5348         int oom, i;
5349         u32 low;
5350
5351         dprintk(KERN_DEBUG "nv_open: begin\n");
5352
5353         /* power up phy */
5354         mii_rw(dev, np->phyaddr, MII_BMCR,
5355                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5356
5357         nv_txrx_gate(dev, false);
5358         /* erase previous misconfiguration */
5359         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5360                 nv_mac_reset(dev);
5361         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5362         writel(0, base + NvRegMulticastAddrB);
5363         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5364         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5365         writel(0, base + NvRegPacketFilterFlags);
5366
5367         writel(0, base + NvRegTransmitterControl);
5368         writel(0, base + NvRegReceiverControl);
5369
5370         writel(0, base + NvRegAdapterControl);
5371
5372         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5373                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5374
5375         /* initialize descriptor rings */
5376         set_bufsize(dev);
5377         oom = nv_init_ring(dev);
5378
5379         writel(0, base + NvRegLinkSpeed);
5380         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5381         nv_txrx_reset(dev);
5382         writel(0, base + NvRegUnknownSetupReg6);
5383
5384         np->in_shutdown = 0;
5385
5386         /* give hw rings */
5387         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5388         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5389                 base + NvRegRingSizes);
5390
5391         writel(np->linkspeed, base + NvRegLinkSpeed);
5392         if (np->desc_ver == DESC_VER_1)
5393                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5394         else
5395                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5396         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5397         writel(np->vlanctl_bits, base + NvRegVlanControl);
5398         pci_push(base);
5399         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5400         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5401                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5402                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5403
5404         writel(0, base + NvRegMIIMask);
5405         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5406         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5407
5408         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5409         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5410         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5411         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5412
5413         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5414
5415         get_random_bytes(&low, sizeof(low));
5416         low &= NVREG_SLOTTIME_MASK;
5417         if (np->desc_ver == DESC_VER_1) {
5418                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5419         } else {
5420                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5421                         /* setup legacy backoff */
5422                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5423                 } else {
5424                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5425                         nv_gear_backoff_reseed(dev);
5426                 }
5427         }
5428         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5429         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5430         if (poll_interval == -1) {
5431                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5432                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5433                 else
5434                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5435         }
5436         else
5437                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5438         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5439         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5440                         base + NvRegAdapterControl);
5441         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5442         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5443         if (np->wolenabled)
5444                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5445
5446         i = readl(base + NvRegPowerState);
5447         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5448                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5449
5450         pci_push(base);
5451         udelay(10);
5452         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5453
5454         nv_disable_hw_interrupts(dev, np->irqmask);
5455         pci_push(base);
5456         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5457         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5458         pci_push(base);
5459
5460         if (nv_request_irq(dev, 0)) {
5461                 goto out_drain;
5462         }
5463
5464         /* ask for interrupts */
5465         nv_enable_hw_interrupts(dev, np->irqmask);
5466
5467         spin_lock_irq(&np->lock);
5468         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5469         writel(0, base + NvRegMulticastAddrB);
5470         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5471         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5472         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5473         /* One manual link speed update: Interrupts are enabled, future link
5474          * speed changes cause interrupts and are handled by nv_link_irq().
5475          */
5476         {
5477                 u32 miistat;
5478                 miistat = readl(base + NvRegMIIStatus);
5479                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5480                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5481         }
5482         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5483          * to init hw */
5484         np->linkspeed = 0;
5485         ret = nv_update_linkspeed(dev);
5486         nv_start_rxtx(dev);
5487         netif_start_queue(dev);
5488         nv_napi_enable(dev);
5489
5490         if (ret) {
5491                 netif_carrier_on(dev);
5492         } else {
5493                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5494                 netif_carrier_off(dev);
5495         }
5496         if (oom)
5497                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5498
5499         /* start statistics timer */
5500         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5501                 mod_timer(&np->stats_poll,
5502                         round_jiffies(jiffies + STATS_INTERVAL));
5503
5504         spin_unlock_irq(&np->lock);
5505
5506         return 0;
5507 out_drain:
5508         nv_drain_rxtx(dev);
5509         return ret;
5510 }
5511
5512 static int nv_close(struct net_device *dev)
5513 {
5514         struct fe_priv *np = netdev_priv(dev);
5515         u8 __iomem *base;
5516
5517         spin_lock_irq(&np->lock);
5518         np->in_shutdown = 1;
5519         spin_unlock_irq(&np->lock);
5520         nv_napi_disable(dev);
5521         synchronize_irq(np->pci_dev->irq);
5522
5523         del_timer_sync(&np->oom_kick);
5524         del_timer_sync(&np->nic_poll);
5525         del_timer_sync(&np->stats_poll);
5526
5527         netif_stop_queue(dev);
5528         spin_lock_irq(&np->lock);
5529         nv_stop_rxtx(dev);
5530         nv_txrx_reset(dev);
5531
5532         /* disable interrupts on the nic or we will lock up */
5533         base = get_hwbase(dev);
5534         nv_disable_hw_interrupts(dev, np->irqmask);
5535         pci_push(base);
5536         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5537
5538         spin_unlock_irq(&np->lock);
5539
5540         nv_free_irq(dev);
5541
5542         nv_drain_rxtx(dev);
5543
5544         if (np->wolenabled || !phy_power_down) {
5545                 nv_txrx_gate(dev, false);
5546                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5547                 nv_start_rx(dev);
5548         } else {
5549                 /* power down phy */
5550                 mii_rw(dev, np->phyaddr, MII_BMCR,
5551                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5552                 nv_txrx_gate(dev, true);
5553         }
5554
5555         /* FIXME: power down nic */
5556
5557         return 0;
5558 }
5559
5560 static const struct net_device_ops nv_netdev_ops = {
5561         .ndo_open               = nv_open,
5562         .ndo_stop               = nv_close,
5563         .ndo_get_stats          = nv_get_stats,
5564         .ndo_start_xmit         = nv_start_xmit,
5565         .ndo_tx_timeout         = nv_tx_timeout,
5566         .ndo_change_mtu         = nv_change_mtu,
5567         .ndo_validate_addr      = eth_validate_addr,
5568         .ndo_set_mac_address    = nv_set_mac_address,
5569         .ndo_set_multicast_list = nv_set_multicast,
5570         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5571 #ifdef CONFIG_NET_POLL_CONTROLLER
5572         .ndo_poll_controller    = nv_poll_controller,
5573 #endif
5574 };
5575
5576 static const struct net_device_ops nv_netdev_ops_optimized = {
5577         .ndo_open               = nv_open,
5578         .ndo_stop               = nv_close,
5579         .ndo_get_stats          = nv_get_stats,
5580         .ndo_start_xmit         = nv_start_xmit_optimized,
5581         .ndo_tx_timeout         = nv_tx_timeout,
5582         .ndo_change_mtu         = nv_change_mtu,
5583         .ndo_validate_addr      = eth_validate_addr,
5584         .ndo_set_mac_address    = nv_set_mac_address,
5585         .ndo_set_multicast_list = nv_set_multicast,
5586         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5587 #ifdef CONFIG_NET_POLL_CONTROLLER
5588         .ndo_poll_controller    = nv_poll_controller,
5589 #endif
5590 };
5591
5592 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5593 {
5594         struct net_device *dev;
5595         struct fe_priv *np;
5596         unsigned long addr;
5597         u8 __iomem *base;
5598         int err, i;
5599         u32 powerstate, txreg;
5600         u32 phystate_orig = 0, phystate;
5601         int phyinitialized = 0;
5602         static int printed_version;
5603
5604         if (!printed_version++)
5605                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5606                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5607
5608         dev = alloc_etherdev(sizeof(struct fe_priv));
5609         err = -ENOMEM;
5610         if (!dev)
5611                 goto out;
5612
5613         np = netdev_priv(dev);
5614         np->dev = dev;
5615         np->pci_dev = pci_dev;
5616         spin_lock_init(&np->lock);
5617         SET_NETDEV_DEV(dev, &pci_dev->dev);
5618
5619         init_timer(&np->oom_kick);
5620         np->oom_kick.data = (unsigned long) dev;
5621         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5622         init_timer(&np->nic_poll);
5623         np->nic_poll.data = (unsigned long) dev;
5624         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5625         init_timer(&np->stats_poll);
5626         np->stats_poll.data = (unsigned long) dev;
5627         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5628
5629         err = pci_enable_device(pci_dev);
5630         if (err)
5631                 goto out_free;
5632
5633         pci_set_master(pci_dev);
5634
5635         err = pci_request_regions(pci_dev, DRV_NAME);
5636         if (err < 0)
5637                 goto out_disable;
5638
5639         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5640                 np->register_size = NV_PCI_REGSZ_VER3;
5641         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5642                 np->register_size = NV_PCI_REGSZ_VER2;
5643         else
5644                 np->register_size = NV_PCI_REGSZ_VER1;
5645
5646         err = -EINVAL;
5647         addr = 0;
5648         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5649                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5650                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5651                                 pci_resource_len(pci_dev, i),
5652                                 pci_resource_flags(pci_dev, i));
5653                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5654                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5655                         addr = pci_resource_start(pci_dev, i);
5656                         break;
5657                 }
5658         }
5659         if (i == DEVICE_COUNT_RESOURCE) {
5660                 dev_printk(KERN_INFO, &pci_dev->dev,
5661                            "Couldn't find register window\n");
5662                 goto out_relreg;
5663         }
5664
5665         /* copy of driver data */
5666         np->driver_data = id->driver_data;
5667         /* copy of device id */
5668         np->device_id = id->device;
5669
5670         /* handle different descriptor versions */
5671         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5672                 /* packet format 3: supports 40-bit addressing */
5673                 np->desc_ver = DESC_VER_3;
5674                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5675                 if (dma_64bit) {
5676                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5677                                 dev_printk(KERN_INFO, &pci_dev->dev,
5678                                         "64-bit DMA failed, using 32-bit addressing\n");
5679                         else
5680                                 dev->features |= NETIF_F_HIGHDMA;
5681                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5682                                 dev_printk(KERN_INFO, &pci_dev->dev,
5683                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5684                         }
5685                 }
5686         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5687                 /* packet format 2: supports jumbo frames */
5688                 np->desc_ver = DESC_VER_2;
5689                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5690         } else {
5691                 /* original packet format */
5692                 np->desc_ver = DESC_VER_1;
5693                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5694         }
5695
5696         np->pkt_limit = NV_PKTLIMIT_1;
5697         if (id->driver_data & DEV_HAS_LARGEDESC)
5698                 np->pkt_limit = NV_PKTLIMIT_2;
5699
5700         if (id->driver_data & DEV_HAS_CHECKSUM) {
5701                 np->rx_csum = 1;
5702                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5703                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5704                 dev->features |= NETIF_F_TSO;
5705         }
5706
5707         np->vlanctl_bits = 0;
5708         if (id->driver_data & DEV_HAS_VLAN) {
5709                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5710                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5711         }
5712
5713         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5714         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5715             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5716             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5717                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5718         }
5719
5720
5721         err = -ENOMEM;
5722         np->base = ioremap(addr, np->register_size);
5723         if (!np->base)
5724                 goto out_relreg;
5725         dev->base_addr = (unsigned long)np->base;
5726
5727         dev->irq = pci_dev->irq;
5728
5729         np->rx_ring_size = RX_RING_DEFAULT;
5730         np->tx_ring_size = TX_RING_DEFAULT;
5731
5732         if (!nv_optimized(np)) {
5733                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5734                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5735                                         &np->ring_addr);
5736                 if (!np->rx_ring.orig)
5737                         goto out_unmap;
5738                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5739         } else {
5740                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5741                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5742                                         &np->ring_addr);
5743                 if (!np->rx_ring.ex)
5744                         goto out_unmap;
5745                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5746         }
5747         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5748         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5749         if (!np->rx_skb || !np->tx_skb)
5750                 goto out_freering;
5751
5752         if (!nv_optimized(np))
5753                 dev->netdev_ops = &nv_netdev_ops;
5754         else
5755                 dev->netdev_ops = &nv_netdev_ops_optimized;
5756
5757 #ifdef CONFIG_FORCEDETH_NAPI
5758         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5759 #endif
5760         SET_ETHTOOL_OPS(dev, &ops);
5761         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5762
5763         pci_set_drvdata(pci_dev, dev);
5764
5765         /* read the mac address */
5766         base = get_hwbase(dev);
5767         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5768         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5769
5770         /* check the workaround bit for correct mac address order */
5771         txreg = readl(base + NvRegTransmitPoll);
5772         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5773                 /* mac address is already in correct order */
5774                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5775                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5776                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5777                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5778                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5779                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5780         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5781                 /* mac address is already in correct order */
5782                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5783                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5784                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5785                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5786                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5787                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5788                 /*
5789                  * Set orig mac address back to the reversed version.
5790                  * This flag will be cleared during low power transition.
5791                  * Therefore, we should always put back the reversed address.
5792                  */
5793                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5794                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5795                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5796         } else {
5797                 /* need to reverse mac address to correct order */
5798                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5799                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5800                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5801                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5802                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5803                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5804                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5805                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5806         }
5807         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5808
5809         if (!is_valid_ether_addr(dev->perm_addr)) {
5810                 /*
5811                  * Bad mac address. At least one bios sets the mac address
5812                  * to 01:23:45:67:89:ab
5813                  */
5814                 dev_printk(KERN_ERR, &pci_dev->dev,
5815                         "Invalid Mac address detected: %pM\n",
5816                         dev->dev_addr);
5817                 dev_printk(KERN_ERR, &pci_dev->dev,
5818                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5819                 dev->dev_addr[0] = 0x00;
5820                 dev->dev_addr[1] = 0x00;
5821                 dev->dev_addr[2] = 0x6c;
5822                 get_random_bytes(&dev->dev_addr[3], 3);
5823         }
5824
5825         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5826                 pci_name(pci_dev), dev->dev_addr);
5827
5828         /* set mac address */
5829         nv_copy_mac_to_hw(dev);
5830
5831         /* Workaround current PCI init glitch:  wakeup bits aren't
5832          * being set from PCI PM capability.
5833          */
5834         device_init_wakeup(&pci_dev->dev, 1);
5835
5836         /* disable WOL */
5837         writel(0, base + NvRegWakeUpFlags);
5838         np->wolenabled = 0;
5839
5840         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5841
5842                 /* take phy and nic out of low power mode */
5843                 powerstate = readl(base + NvRegPowerState2);
5844                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5845                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5846                     pci_dev->revision >= 0xA3)
5847                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5848                 writel(powerstate, base + NvRegPowerState2);
5849         }
5850
5851         if (np->desc_ver == DESC_VER_1) {
5852                 np->tx_flags = NV_TX_VALID;
5853         } else {
5854                 np->tx_flags = NV_TX2_VALID;
5855         }
5856
5857         np->msi_flags = 0;
5858         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5859                 np->msi_flags |= NV_MSI_CAPABLE;
5860         }
5861         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5862                 /* msix has had reported issues when modifying irqmask
5863                    as in the case of napi, therefore, disable for now
5864                 */
5865 #ifndef CONFIG_FORCEDETH_NAPI
5866                 np->msi_flags |= NV_MSI_X_CAPABLE;
5867 #endif
5868         }
5869
5870         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5871                 np->irqmask = NVREG_IRQMASK_CPU;
5872                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5873                         np->msi_flags |= 0x0001;
5874         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5875                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5876                 /* start off in throughput mode */
5877                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5878                 /* remove support for msix mode */
5879                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5880         } else {
5881                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5882                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5883                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5884                         np->msi_flags |= 0x0003;
5885         }
5886
5887         if (id->driver_data & DEV_NEED_TIMERIRQ)
5888                 np->irqmask |= NVREG_IRQ_TIMER;
5889         if (id->driver_data & DEV_NEED_LINKTIMER) {
5890                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5891                 np->need_linktimer = 1;
5892                 np->link_timeout = jiffies + LINK_TIMEOUT;
5893         } else {
5894                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5895                 np->need_linktimer = 0;
5896         }
5897
5898         /* Limit the number of tx's outstanding for hw bug */
5899         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5900                 np->tx_limit = 1;
5901                 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5902                     pci_dev->revision >= 0xA2)
5903                         np->tx_limit = 0;
5904         }
5905
5906         /* clear phy state and temporarily halt phy interrupts */
5907         writel(0, base + NvRegMIIMask);
5908         phystate = readl(base + NvRegAdapterControl);
5909         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5910                 phystate_orig = 1;
5911                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5912                 writel(phystate, base + NvRegAdapterControl);
5913         }
5914         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5915
5916         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5917                 /* management unit running on the mac? */
5918                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5919                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5920                     nv_mgmt_acquire_sema(dev) &&
5921                     nv_mgmt_get_version(dev)) {
5922                         np->mac_in_use = 1;
5923                         if (np->mgmt_version > 0) {
5924                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5925                         }
5926                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5927                                 pci_name(pci_dev), np->mac_in_use);
5928                         /* management unit setup the phy already? */
5929                         if (np->mac_in_use &&
5930                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5931                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5932                                 /* phy is inited by mgmt unit */
5933                                 phyinitialized = 1;
5934                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5935                                         pci_name(pci_dev));
5936                         } else {
5937                                 /* we need to init the phy */
5938                         }
5939                 }
5940         }
5941
5942         /* find a suitable phy */
5943         for (i = 1; i <= 32; i++) {
5944                 int id1, id2;
5945                 int phyaddr = i & 0x1F;
5946
5947                 spin_lock_irq(&np->lock);
5948                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5949                 spin_unlock_irq(&np->lock);
5950                 if (id1 < 0 || id1 == 0xffff)
5951                         continue;
5952                 spin_lock_irq(&np->lock);
5953                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5954                 spin_unlock_irq(&np->lock);
5955                 if (id2 < 0 || id2 == 0xffff)
5956                         continue;
5957
5958                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5959                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5960                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5961                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5962                         pci_name(pci_dev), id1, id2, phyaddr);
5963                 np->phyaddr = phyaddr;
5964                 np->phy_oui = id1 | id2;
5965
5966                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5967                 if (np->phy_oui == PHY_OUI_REALTEK2)
5968                         np->phy_oui = PHY_OUI_REALTEK;
5969                 /* Setup phy revision for Realtek */
5970                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5971                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5972
5973                 break;
5974         }
5975         if (i == 33) {
5976                 dev_printk(KERN_INFO, &pci_dev->dev,
5977                         "open: Could not find a valid PHY.\n");
5978                 goto out_error;
5979         }
5980
5981         if (!phyinitialized) {
5982                 /* reset it */
5983                 phy_init(dev);
5984         } else {
5985                 /* see if it is a gigabit phy */
5986                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5987                 if (mii_status & PHY_GIGABIT) {
5988                         np->gigabit = PHY_GIGABIT;
5989                 }
5990         }
5991
5992         /* set default link speed settings */
5993         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5994         np->duplex = 0;
5995         np->autoneg = 1;
5996
5997         err = register_netdev(dev);
5998         if (err) {
5999                 dev_printk(KERN_INFO, &pci_dev->dev,
6000                            "unable to register netdev: %d\n", err);
6001                 goto out_error;
6002         }
6003
6004         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
6005                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6006                    dev->name,
6007                    np->phy_oui,
6008                    np->phyaddr,
6009                    dev->dev_addr[0],
6010                    dev->dev_addr[1],
6011                    dev->dev_addr[2],
6012                    dev->dev_addr[3],
6013                    dev->dev_addr[4],
6014                    dev->dev_addr[5]);
6015
6016         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6017                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6018                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6019                         "csum " : "",
6020                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
6021                         "vlan " : "",
6022                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6023                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6024                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6025                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
6026                    np->need_linktimer ? "lnktim " : "",
6027                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6028                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6029                    np->desc_ver);
6030
6031         return 0;
6032
6033 out_error:
6034         if (phystate_orig)
6035                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6036         pci_set_drvdata(pci_dev, NULL);
6037 out_freering:
6038         free_rings(dev);
6039 out_unmap:
6040         iounmap(get_hwbase(dev));
6041 out_relreg:
6042         pci_release_regions(pci_dev);
6043 out_disable:
6044         pci_disable_device(pci_dev);
6045 out_free:
6046         free_netdev(dev);
6047 out:
6048         return err;
6049 }
6050
6051 static void nv_restore_phy(struct net_device *dev)
6052 {
6053         struct fe_priv *np = netdev_priv(dev);
6054         u16 phy_reserved, mii_control;
6055
6056         if (np->phy_oui == PHY_OUI_REALTEK &&
6057             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6058             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6059                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6060                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6061                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6062                 phy_reserved |= PHY_REALTEK_INIT8;
6063                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6064                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6065
6066                 /* restart auto negotiation */
6067                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6068                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6069                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6070         }
6071 }
6072
6073 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6074 {
6075         struct net_device *dev = pci_get_drvdata(pci_dev);
6076         struct fe_priv *np = netdev_priv(dev);
6077         u8 __iomem *base = get_hwbase(dev);
6078
6079         /* special op: write back the misordered MAC address - otherwise
6080          * the next nv_probe would see a wrong address.
6081          */
6082         writel(np->orig_mac[0], base + NvRegMacAddrA);
6083         writel(np->orig_mac[1], base + NvRegMacAddrB);
6084         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6085                base + NvRegTransmitPoll);
6086 }
6087
6088 static void __devexit nv_remove(struct pci_dev *pci_dev)
6089 {
6090         struct net_device *dev = pci_get_drvdata(pci_dev);
6091
6092         unregister_netdev(dev);
6093
6094         nv_restore_mac_addr(pci_dev);
6095
6096         /* restore any phy related changes */
6097         nv_restore_phy(dev);
6098
6099         nv_mgmt_release_sema(dev);
6100
6101         /* free all structures */
6102         free_rings(dev);
6103         iounmap(get_hwbase(dev));
6104         pci_release_regions(pci_dev);
6105         pci_disable_device(pci_dev);
6106         free_netdev(dev);
6107         pci_set_drvdata(pci_dev, NULL);
6108 }
6109
6110 #ifdef CONFIG_PM
6111 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6112 {
6113         struct net_device *dev = pci_get_drvdata(pdev);
6114         struct fe_priv *np = netdev_priv(dev);
6115         u8 __iomem *base = get_hwbase(dev);
6116         int i;
6117
6118         if (netif_running(dev)) {
6119                 // Gross.
6120                 nv_close(dev);
6121         }
6122         netif_device_detach(dev);
6123
6124         /* save non-pci configuration space */
6125         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6126                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6127
6128         pci_save_state(pdev);
6129         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6130         pci_disable_device(pdev);
6131         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6132         return 0;
6133 }
6134
6135 static int nv_resume(struct pci_dev *pdev)
6136 {
6137         struct net_device *dev = pci_get_drvdata(pdev);
6138         struct fe_priv *np = netdev_priv(dev);
6139         u8 __iomem *base = get_hwbase(dev);
6140         int i, rc = 0;
6141
6142         pci_set_power_state(pdev, PCI_D0);
6143         pci_restore_state(pdev);
6144         /* ack any pending wake events, disable PME */
6145         pci_enable_wake(pdev, PCI_D0, 0);
6146
6147         /* restore non-pci configuration space */
6148         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6149                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6150
6151         if (np->driver_data & DEV_NEED_MSI_FIX)
6152                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6153
6154         /* restore phy state, including autoneg */
6155         phy_init(dev);
6156
6157         netif_device_attach(dev);
6158         if (netif_running(dev)) {
6159                 rc = nv_open(dev);
6160                 nv_set_multicast(dev);
6161         }
6162         return rc;
6163 }
6164
6165 static void nv_shutdown(struct pci_dev *pdev)
6166 {
6167         struct net_device *dev = pci_get_drvdata(pdev);
6168         struct fe_priv *np = netdev_priv(dev);
6169
6170         if (netif_running(dev))
6171                 nv_close(dev);
6172
6173         /*
6174          * Restore the MAC so a kernel started by kexec won't get confused.
6175          * If we really go for poweroff, we must not restore the MAC,
6176          * otherwise the MAC for WOL will be reversed at least on some boards.
6177          */
6178         if (system_state != SYSTEM_POWER_OFF) {
6179                 nv_restore_mac_addr(pdev);
6180         }
6181
6182         pci_disable_device(pdev);
6183         /*
6184          * Apparently it is not possible to reinitialise from D3 hot,
6185          * only put the device into D3 if we really go for poweroff.
6186          */
6187         if (system_state == SYSTEM_POWER_OFF) {
6188                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6189                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6190                 pci_set_power_state(pdev, PCI_D3hot);
6191         }
6192 }
6193 #else
6194 #define nv_suspend NULL
6195 #define nv_shutdown NULL
6196 #define nv_resume NULL
6197 #endif /* CONFIG_PM */
6198
6199 static struct pci_device_id pci_tbl[] = {
6200         {       /* nForce Ethernet Controller */
6201                 PCI_DEVICE(0x10DE, 0x01C3),
6202                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6203         },
6204         {       /* nForce2 Ethernet Controller */
6205                 PCI_DEVICE(0x10DE, 0x0066),
6206                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6207         },
6208         {       /* nForce3 Ethernet Controller */
6209                 PCI_DEVICE(0x10DE, 0x00D6),
6210                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6211         },
6212         {       /* nForce3 Ethernet Controller */
6213                 PCI_DEVICE(0x10DE, 0x0086),
6214                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6215         },
6216         {       /* nForce3 Ethernet Controller */
6217                 PCI_DEVICE(0x10DE, 0x008C),
6218                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6219         },
6220         {       /* nForce3 Ethernet Controller */
6221                 PCI_DEVICE(0x10DE, 0x00E6),
6222                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6223         },
6224         {       /* nForce3 Ethernet Controller */
6225                 PCI_DEVICE(0x10DE, 0x00DF),
6226                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6227         },
6228         {       /* CK804 Ethernet Controller */
6229                 PCI_DEVICE(0x10DE, 0x0056),
6230                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6231         },
6232         {       /* CK804 Ethernet Controller */
6233                 PCI_DEVICE(0x10DE, 0x0057),
6234                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6235         },
6236         {       /* MCP04 Ethernet Controller */
6237                 PCI_DEVICE(0x10DE, 0x0037),
6238                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6239         },
6240         {       /* MCP04 Ethernet Controller */
6241                 PCI_DEVICE(0x10DE, 0x0038),
6242                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6243         },
6244         {       /* MCP51 Ethernet Controller */
6245                 PCI_DEVICE(0x10DE, 0x0268),
6246                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6247         },
6248         {       /* MCP51 Ethernet Controller */
6249                 PCI_DEVICE(0x10DE, 0x0269),
6250                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6251         },
6252         {       /* MCP55 Ethernet Controller */
6253                 PCI_DEVICE(0x10DE, 0x0372),
6254                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6255         },
6256         {       /* MCP55 Ethernet Controller */
6257                 PCI_DEVICE(0x10DE, 0x0373),
6258                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6259         },
6260         {       /* MCP61 Ethernet Controller */
6261                 PCI_DEVICE(0x10DE, 0x03E5),
6262                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6263         },
6264         {       /* MCP61 Ethernet Controller */
6265                 PCI_DEVICE(0x10DE, 0x03E6),
6266                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6267         },
6268         {       /* MCP61 Ethernet Controller */
6269                 PCI_DEVICE(0x10DE, 0x03EE),
6270                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6271         },
6272         {       /* MCP61 Ethernet Controller */
6273                 PCI_DEVICE(0x10DE, 0x03EF),
6274                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6275         },
6276         {       /* MCP65 Ethernet Controller */
6277                 PCI_DEVICE(0x10DE, 0x0450),
6278                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6279         },
6280         {       /* MCP65 Ethernet Controller */
6281                 PCI_DEVICE(0x10DE, 0x0451),
6282                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6283         },
6284         {       /* MCP65 Ethernet Controller */
6285                 PCI_DEVICE(0x10DE, 0x0452),
6286                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6287         },
6288         {       /* MCP65 Ethernet Controller */
6289                 PCI_DEVICE(0x10DE, 0x0453),
6290                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6291         },
6292         {       /* MCP67 Ethernet Controller */
6293                 PCI_DEVICE(0x10DE, 0x054C),
6294                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6295         },
6296         {       /* MCP67 Ethernet Controller */
6297                 PCI_DEVICE(0x10DE, 0x054D),
6298                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6299         },
6300         {       /* MCP67 Ethernet Controller */
6301                 PCI_DEVICE(0x10DE, 0x054E),
6302                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6303         },
6304         {       /* MCP67 Ethernet Controller */
6305                 PCI_DEVICE(0x10DE, 0x054F),
6306                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6307         },
6308         {       /* MCP73 Ethernet Controller */
6309                 PCI_DEVICE(0x10DE, 0x07DC),
6310                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6311         },
6312         {       /* MCP73 Ethernet Controller */
6313                 PCI_DEVICE(0x10DE, 0x07DD),
6314                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6315         },
6316         {       /* MCP73 Ethernet Controller */
6317                 PCI_DEVICE(0x10DE, 0x07DE),
6318                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6319         },
6320         {       /* MCP73 Ethernet Controller */
6321                 PCI_DEVICE(0x10DE, 0x07DF),
6322                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6323         },
6324         {       /* MCP77 Ethernet Controller */
6325                 PCI_DEVICE(0x10DE, 0x0760),
6326                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6327         },
6328         {       /* MCP77 Ethernet Controller */
6329                 PCI_DEVICE(0x10DE, 0x0761),
6330                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6331         },
6332         {       /* MCP77 Ethernet Controller */
6333                 PCI_DEVICE(0x10DE, 0x0762),
6334                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6335         },
6336         {       /* MCP77 Ethernet Controller */
6337                 PCI_DEVICE(0x10DE, 0x0763),
6338                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6339         },
6340         {       /* MCP79 Ethernet Controller */
6341                 PCI_DEVICE(0x10DE, 0x0AB0),
6342                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6343         },
6344         {       /* MCP79 Ethernet Controller */
6345                 PCI_DEVICE(0x10DE, 0x0AB1),
6346                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6347         },
6348         {       /* MCP79 Ethernet Controller */
6349                 PCI_DEVICE(0x10DE, 0x0AB2),
6350                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6351         },
6352         {       /* MCP79 Ethernet Controller */
6353                 PCI_DEVICE(0x10DE, 0x0AB3),
6354                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6355         },
6356         {       /* MCP89 Ethernet Controller */
6357                 PCI_DEVICE(0x10DE, 0x0D7D),
6358                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6359         },
6360         {0,},
6361 };
6362
6363 static struct pci_driver driver = {
6364         .name           = DRV_NAME,
6365         .id_table       = pci_tbl,
6366         .probe          = nv_probe,
6367         .remove         = __devexit_p(nv_remove),
6368         .suspend        = nv_suspend,
6369         .resume         = nv_resume,
6370         .shutdown       = nv_shutdown,
6371 };
6372
6373 static int __init init_nic(void)
6374 {
6375         return pci_register_driver(&driver);
6376 }
6377
6378 static void __exit exit_nic(void)
6379 {
6380         pci_unregister_driver(&driver);
6381 }
6382
6383 module_param(max_interrupt_work, int, 0);
6384 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6385 module_param(optimization_mode, int, 0);
6386 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6387 module_param(poll_interval, int, 0);
6388 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6389 module_param(msi, int, 0);
6390 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6391 module_param(msix, int, 0);
6392 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6393 module_param(dma_64bit, int, 0);
6394 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6395 module_param(phy_cross, int, 0);
6396 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6397 module_param(phy_power_down, int, 0);
6398 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6399
6400 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6401 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6402 MODULE_LICENSE("GPL");
6403
6404 MODULE_DEVICE_TABLE(pci, pci_tbl);
6405
6406 module_init(init_nic);
6407 module_exit(exit_nic);