2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
72 /* MAC address length */
73 #define MAC_ADDR_LEN 6
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
80 #define R8169_REGS_SIZE 256
81 #define R8169_NAPI_WEIGHT 64
82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
88 #define RTL8169_TX_TIMEOUT (6*HZ)
89 #define RTL8169_PHY_TIMEOUT (10*HZ)
91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
93 #define RTL_EEPROM_SIG_ADDR 0x0000
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01 = 0,
140 RTL_GIGA_MAC_NONE = 0xff,
143 enum rtl_tx_desc_version {
148 #define JUMBO_1K ETH_DATA_LEN
149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154 #define _R(NAME,TD,FW,SZ,B) { \
162 static const struct {
164 enum rtl_tx_desc_version txd_version;
168 } rtl_chip_infos[] = {
170 [RTL_GIGA_MAC_VER_01] =
171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
172 [RTL_GIGA_MAC_VER_02] =
173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
174 [RTL_GIGA_MAC_VER_03] =
175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
176 [RTL_GIGA_MAC_VER_04] =
177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_05] =
179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_06] =
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_07] =
184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
185 [RTL_GIGA_MAC_VER_08] =
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
187 [RTL_GIGA_MAC_VER_09] =
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
189 [RTL_GIGA_MAC_VER_10] =
190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
191 [RTL_GIGA_MAC_VER_11] =
192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
193 [RTL_GIGA_MAC_VER_12] =
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
195 [RTL_GIGA_MAC_VER_13] =
196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_14] =
198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_15] =
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
201 [RTL_GIGA_MAC_VER_16] =
202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
203 [RTL_GIGA_MAC_VER_17] =
204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
205 [RTL_GIGA_MAC_VER_18] =
206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
207 [RTL_GIGA_MAC_VER_19] =
208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
209 [RTL_GIGA_MAC_VER_20] =
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
211 [RTL_GIGA_MAC_VER_21] =
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
213 [RTL_GIGA_MAC_VER_22] =
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_23] =
216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_24] =
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_25] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
222 [RTL_GIGA_MAC_VER_26] =
223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
225 [RTL_GIGA_MAC_VER_27] =
226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
227 [RTL_GIGA_MAC_VER_28] =
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
229 [RTL_GIGA_MAC_VER_29] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 [RTL_GIGA_MAC_VER_30] =
233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
235 [RTL_GIGA_MAC_VER_31] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_32] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
240 [RTL_GIGA_MAC_VER_33] =
241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
243 [RTL_GIGA_MAC_VER_34] =
244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
246 [RTL_GIGA_MAC_VER_35] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
249 [RTL_GIGA_MAC_VER_36] =
250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 static void rtl_hw_start_8169(struct net_device *);
262 static void rtl_hw_start_8168(struct net_device *);
263 static void rtl_hw_start_8101(struct net_device *);
265 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
270 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
272 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
273 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
274 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
275 { PCI_VENDOR_ID_LINKSYS, 0x1032,
276 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
278 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
282 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
284 static int rx_buf_sz = 16383;
291 MAC0 = 0, /* Ethernet hardware address. */
293 MAR0 = 8, /* Multicast filter. */
294 CounterAddrLow = 0x10,
295 CounterAddrHigh = 0x14,
296 TxDescStartAddrLow = 0x20,
297 TxDescStartAddrHigh = 0x24,
298 TxHDescStartAddrLow = 0x28,
299 TxHDescStartAddrHigh = 0x2c,
308 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
309 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
312 #define RX128_INT_EN (1 << 15) /* 8111c and later */
313 #define RX_MULTI_EN (1 << 14) /* 8111c only */
314 #define RXCFG_FIFO_SHIFT 13
315 /* No threshold before first PCI xfer */
316 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
317 #define RXCFG_DMA_SHIFT 8
318 /* Unlimited maximum PCI burst. */
319 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
335 RxDescAddrLow = 0xe4,
336 RxDescAddrHigh = 0xe8,
337 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
339 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
341 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
343 #define TxPacketMax (8064 >> 7)
344 #define EarlySize 0x27
347 FuncEventMask = 0xf4,
348 FuncPresetState = 0xf8,
349 FuncForceEvent = 0xfc,
352 enum rtl8110_registers {
358 enum rtl8168_8101_registers {
361 #define CSIAR_FLAG 0x80000000
362 #define CSIAR_WRITE_CMD 0x80000000
363 #define CSIAR_BYTE_ENABLE 0x0f
364 #define CSIAR_BYTE_ENABLE_SHIFT 12
365 #define CSIAR_ADDR_MASK 0x0fff
368 #define EPHYAR_FLAG 0x80000000
369 #define EPHYAR_WRITE_CMD 0x80000000
370 #define EPHYAR_REG_MASK 0x1f
371 #define EPHYAR_REG_SHIFT 16
372 #define EPHYAR_DATA_MASK 0xffff
374 #define PFM_EN (1 << 6)
376 #define FIX_NAK_1 (1 << 4)
377 #define FIX_NAK_2 (1 << 3)
380 #define NOW_IS_OOB (1 << 7)
381 #define EN_NDP (1 << 3)
382 #define EN_OOB_RESET (1 << 2)
384 #define EFUSEAR_FLAG 0x80000000
385 #define EFUSEAR_WRITE_CMD 0x80000000
386 #define EFUSEAR_READ_CMD 0x00000000
387 #define EFUSEAR_REG_MASK 0x03ff
388 #define EFUSEAR_REG_SHIFT 8
389 #define EFUSEAR_DATA_MASK 0xff
392 enum rtl8168_registers {
397 #define ERIAR_FLAG 0x80000000
398 #define ERIAR_WRITE_CMD 0x80000000
399 #define ERIAR_READ_CMD 0x00000000
400 #define ERIAR_ADDR_BYTE_ALIGN 4
401 #define ERIAR_TYPE_SHIFT 16
402 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
403 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
404 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
405 #define ERIAR_MASK_SHIFT 12
406 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
407 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
408 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
409 EPHY_RXER_NUM = 0x7c,
410 OCPDR = 0xb0, /* OCP GPHY access */
411 #define OCPDR_WRITE_CMD 0x80000000
412 #define OCPDR_READ_CMD 0x00000000
413 #define OCPDR_REG_MASK 0x7f
414 #define OCPDR_GPHY_REG_SHIFT 16
415 #define OCPDR_DATA_MASK 0xffff
417 #define OCPAR_FLAG 0x80000000
418 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
419 #define OCPAR_GPHY_READ_CMD 0x0000f060
420 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
421 MISC = 0xf0, /* 8168e only. */
422 #define TXPLA_RST (1 << 29)
423 #define PWM_EN (1 << 22)
426 enum rtl_register_content {
427 /* InterruptStatusBits */
431 TxDescUnavail = 0x0080,
455 /* TXPoll register p.5 */
456 HPQ = 0x80, /* Poll cmd on the high prio queue */
457 NPQ = 0x40, /* Poll cmd on the low prio queue */
458 FSWInt = 0x01, /* Forced software interrupt */
462 Cfg9346_Unlock = 0xc0,
467 AcceptBroadcast = 0x08,
468 AcceptMulticast = 0x04,
470 AcceptAllPhys = 0x01,
471 #define RX_CONFIG_ACCEPT_MASK 0x3f
474 TxInterFrameGapShift = 24,
475 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
477 /* Config1 register p.24 */
480 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
481 Speed_down = (1 << 4),
485 PMEnable = (1 << 0), /* Power Management Enable */
487 /* Config2 register p. 25 */
488 PCI_Clock_66MHz = 0x01,
489 PCI_Clock_33MHz = 0x00,
491 /* Config3 register p.25 */
492 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
493 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
494 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
495 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
497 /* Config4 register */
498 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
500 /* Config5 register p.27 */
501 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
502 MWF = (1 << 5), /* Accept Multicast wakeup frame */
503 UWF = (1 << 4), /* Accept Unicast wakeup frame */
505 LanWake = (1 << 1), /* LanWake enable/disable */
506 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
509 TBIReset = 0x80000000,
510 TBILoopback = 0x40000000,
511 TBINwEnable = 0x20000000,
512 TBINwRestart = 0x10000000,
513 TBILinkOk = 0x02000000,
514 TBINwComplete = 0x01000000,
517 EnableBist = (1 << 15), // 8168 8101
518 Mac_dbgo_oe = (1 << 14), // 8168 8101
519 Normal_mode = (1 << 13), // unused
520 Force_half_dup = (1 << 12), // 8168 8101
521 Force_rxflow_en = (1 << 11), // 8168 8101
522 Force_txflow_en = (1 << 10), // 8168 8101
523 Cxpl_dbg_sel = (1 << 9), // 8168 8101
524 ASF = (1 << 8), // 8168 8101
525 PktCntrDisable = (1 << 7), // 8168 8101
526 Mac_dbgo_sel = 0x001c, // 8168
531 INTT_0 = 0x0000, // 8168
532 INTT_1 = 0x0001, // 8168
533 INTT_2 = 0x0002, // 8168
534 INTT_3 = 0x0003, // 8168
536 /* rtl8169_PHYstatus */
547 TBILinkOK = 0x02000000,
549 /* DumpCounterCommand */
554 /* First doubleword. */
555 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
556 RingEnd = (1 << 30), /* End of descriptor ring */
557 FirstFrag = (1 << 29), /* First segment of a packet */
558 LastFrag = (1 << 28), /* Final segment of a packet */
562 enum rtl_tx_desc_bit {
563 /* First doubleword. */
564 TD_LSO = (1 << 27), /* Large Send Offload */
565 #define TD_MSS_MAX 0x07ffu /* MSS value */
567 /* Second doubleword. */
568 TxVlanTag = (1 << 17), /* Add VLAN tag */
571 /* 8169, 8168b and 810x except 8102e. */
572 enum rtl_tx_desc_bit_0 {
573 /* First doubleword. */
574 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
575 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
576 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
577 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
580 /* 8102e, 8168c and beyond. */
581 enum rtl_tx_desc_bit_1 {
582 /* Second doubleword. */
583 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
584 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
585 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
586 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
589 static const struct rtl_tx_desc_info {
596 } tx_desc_info [] = {
599 .udp = TD0_IP_CS | TD0_UDP_CS,
600 .tcp = TD0_IP_CS | TD0_TCP_CS
602 .mss_shift = TD0_MSS_SHIFT,
607 .udp = TD1_IP_CS | TD1_UDP_CS,
608 .tcp = TD1_IP_CS | TD1_TCP_CS
610 .mss_shift = TD1_MSS_SHIFT,
615 enum rtl_rx_desc_bit {
617 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
618 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
620 #define RxProtoUDP (PID1)
621 #define RxProtoTCP (PID0)
622 #define RxProtoIP (PID1 | PID0)
623 #define RxProtoMask RxProtoIP
625 IPFail = (1 << 16), /* IP checksum failed */
626 UDPFail = (1 << 15), /* UDP/IP checksum failed */
627 TCPFail = (1 << 14), /* TCP/IP checksum failed */
628 RxVlanTag = (1 << 16), /* VLAN tag available */
631 #define RsvdMask 0x3fffc000
648 u8 __pad[sizeof(void *) - sizeof(u32)];
652 RTL_FEATURE_WOL = (1 << 0),
653 RTL_FEATURE_MSI = (1 << 1),
654 RTL_FEATURE_GMII = (1 << 2),
657 struct rtl8169_counters {
664 __le32 tx_one_collision;
665 __le32 tx_multi_collision;
673 struct rtl8169_private {
674 void __iomem *mmio_addr; /* memory map physical address */
675 struct pci_dev *pci_dev;
676 struct net_device *dev;
677 struct napi_struct napi;
682 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
683 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
686 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
687 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
688 dma_addr_t TxPhyAddr;
689 dma_addr_t RxPhyAddr;
690 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
691 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
692 struct timer_list timer;
699 void (*write)(void __iomem *, int, int);
700 int (*read)(void __iomem *, int);
703 struct pll_power_ops {
704 void (*down)(struct rtl8169_private *);
705 void (*up)(struct rtl8169_private *);
709 void (*enable)(struct rtl8169_private *);
710 void (*disable)(struct rtl8169_private *);
713 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
714 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
715 void (*phy_reset_enable)(struct rtl8169_private *tp);
716 void (*hw_start)(struct net_device *);
717 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
718 unsigned int (*link_ok)(void __iomem *);
719 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
720 struct delayed_work task;
723 struct mii_if_info mii;
724 struct rtl8169_counters counters;
729 const struct firmware *fw;
731 #define RTL_VER_SIZE 32
733 char version[RTL_VER_SIZE];
735 struct rtl_fw_phy_action {
740 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
745 module_param(use_dac, int, 0);
746 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
747 module_param_named(debug, debug.msg_enable, int, 0);
748 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
749 MODULE_LICENSE("GPL");
750 MODULE_VERSION(RTL8169_VERSION);
751 MODULE_FIRMWARE(FIRMWARE_8168D_1);
752 MODULE_FIRMWARE(FIRMWARE_8168D_2);
753 MODULE_FIRMWARE(FIRMWARE_8168E_1);
754 MODULE_FIRMWARE(FIRMWARE_8168E_2);
755 MODULE_FIRMWARE(FIRMWARE_8168E_3);
756 MODULE_FIRMWARE(FIRMWARE_8105E_1);
757 MODULE_FIRMWARE(FIRMWARE_8168F_1);
758 MODULE_FIRMWARE(FIRMWARE_8168F_2);
760 static int rtl8169_open(struct net_device *dev);
761 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
762 struct net_device *dev);
763 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
764 static int rtl8169_init_ring(struct net_device *dev);
765 static void rtl_hw_start(struct net_device *dev);
766 static int rtl8169_close(struct net_device *dev);
767 static void rtl_set_rx_mode(struct net_device *dev);
768 static void rtl8169_tx_timeout(struct net_device *dev);
769 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
770 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
771 void __iomem *, u32 budget);
772 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
773 static void rtl8169_down(struct net_device *dev);
774 static void rtl8169_rx_clear(struct rtl8169_private *tp);
775 static int rtl8169_poll(struct napi_struct *napi, int budget);
777 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
779 int cap = pci_pcie_cap(pdev);
784 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
785 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
786 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
790 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
792 void __iomem *ioaddr = tp->mmio_addr;
795 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
796 for (i = 0; i < 20; i++) {
798 if (RTL_R32(OCPAR) & OCPAR_FLAG)
801 return RTL_R32(OCPDR);
804 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
806 void __iomem *ioaddr = tp->mmio_addr;
809 RTL_W32(OCPDR, data);
810 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
811 for (i = 0; i < 20; i++) {
813 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
818 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
820 void __iomem *ioaddr = tp->mmio_addr;
824 RTL_W32(ERIAR, 0x800010e8);
826 for (i = 0; i < 5; i++) {
828 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
832 ocp_write(tp, 0x1, 0x30, 0x00000001);
835 #define OOB_CMD_RESET 0x00
836 #define OOB_CMD_DRIVER_START 0x05
837 #define OOB_CMD_DRIVER_STOP 0x06
839 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
841 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
844 static void rtl8168_driver_start(struct rtl8169_private *tp)
849 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
851 reg = rtl8168_get_ocp_reg(tp);
853 for (i = 0; i < 10; i++) {
855 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
860 static void rtl8168_driver_stop(struct rtl8169_private *tp)
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
867 reg = rtl8168_get_ocp_reg(tp);
869 for (i = 0; i < 10; i++) {
871 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
876 static int r8168dp_check_dash(struct rtl8169_private *tp)
878 u16 reg = rtl8168_get_ocp_reg(tp);
880 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
883 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
887 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
889 for (i = 20; i > 0; i--) {
891 * Check if the RTL8169 has completed writing to the specified
894 if (!(RTL_R32(PHYAR) & 0x80000000))
899 * According to hardware specs a 20us delay is required after write
900 * complete indication, but before sending next command.
905 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
909 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
911 for (i = 20; i > 0; i--) {
913 * Check if the RTL8169 has completed retrieving data from
914 * the specified MII register.
916 if (RTL_R32(PHYAR) & 0x80000000) {
917 value = RTL_R32(PHYAR) & 0xffff;
923 * According to hardware specs a 20us delay is required after read
924 * complete indication, but before sending next command.
931 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
935 RTL_W32(OCPDR, data |
936 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
937 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
938 RTL_W32(EPHY_RXER_NUM, 0);
940 for (i = 0; i < 100; i++) {
942 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
947 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
949 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
950 (value & OCPDR_DATA_MASK));
953 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
957 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
960 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
961 RTL_W32(EPHY_RXER_NUM, 0);
963 for (i = 0; i < 100; i++) {
965 if (RTL_R32(OCPAR) & OCPAR_FLAG)
969 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
972 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
974 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
976 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
979 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
981 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
984 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
986 r8168dp_2_mdio_start(ioaddr);
988 r8169_mdio_write(ioaddr, reg_addr, value);
990 r8168dp_2_mdio_stop(ioaddr);
993 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
997 r8168dp_2_mdio_start(ioaddr);
999 value = r8169_mdio_read(ioaddr, reg_addr);
1001 r8168dp_2_mdio_stop(ioaddr);
1006 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1008 tp->mdio_ops.write(tp->mmio_addr, location, val);
1011 static int rtl_readphy(struct rtl8169_private *tp, int location)
1013 return tp->mdio_ops.read(tp->mmio_addr, location);
1016 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1018 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1021 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1025 val = rtl_readphy(tp, reg_addr);
1026 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1029 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1032 struct rtl8169_private *tp = netdev_priv(dev);
1034 rtl_writephy(tp, location, val);
1037 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1039 struct rtl8169_private *tp = netdev_priv(dev);
1041 return rtl_readphy(tp, location);
1044 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1048 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051 for (i = 0; i < 100; i++) {
1052 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1058 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1063 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065 for (i = 0; i < 100; i++) {
1066 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1067 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1076 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1080 RTL_W32(CSIDR, value);
1081 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1082 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1084 for (i = 0; i < 100; i++) {
1085 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1091 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1096 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1097 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099 for (i = 0; i < 100; i++) {
1100 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1101 value = RTL_R32(CSIDR);
1111 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1115 BUG_ON((addr & 3) || (mask == 0));
1116 RTL_W32(ERIDR, val);
1117 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1119 for (i = 0; i < 100; i++) {
1120 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1131 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1133 for (i = 0; i < 100; i++) {
1134 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1135 value = RTL_R32(ERIDR);
1145 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1149 val = rtl_eri_read(ioaddr, addr, type);
1150 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1159 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1160 const struct exgmac_reg *r, int len)
1163 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1168 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1173 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1175 for (i = 0; i < 300; i++) {
1176 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1177 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1186 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1188 void __iomem *ioaddr = tp->mmio_addr;
1190 RTL_W16(IntrMask, 0x0000);
1191 RTL_W16(IntrStatus, tp->intr_event);
1195 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1197 void __iomem *ioaddr = tp->mmio_addr;
1199 return RTL_R32(TBICSR) & TBIReset;
1202 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1204 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1207 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1209 return RTL_R32(TBICSR) & TBILinkOk;
1212 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1214 return RTL_R8(PHYstatus) & LinkStatus;
1217 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1219 void __iomem *ioaddr = tp->mmio_addr;
1221 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1224 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1228 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1229 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1232 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1234 void __iomem *ioaddr = tp->mmio_addr;
1235 struct net_device *dev = tp->dev;
1237 if (!netif_running(dev))
1240 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1241 if (RTL_R8(PHYstatus) & _1000bpsF) {
1242 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1243 0x00000011, ERIAR_EXGMAC);
1244 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1245 0x00000005, ERIAR_EXGMAC);
1246 } else if (RTL_R8(PHYstatus) & _100bps) {
1247 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1248 0x0000001f, ERIAR_EXGMAC);
1249 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1250 0x00000005, ERIAR_EXGMAC);
1252 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1253 0x0000001f, ERIAR_EXGMAC);
1254 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1255 0x0000003f, ERIAR_EXGMAC);
1257 /* Reset packet filter */
1258 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1260 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1262 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1263 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1264 if (RTL_R8(PHYstatus) & _1000bpsF) {
1265 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1266 0x00000011, ERIAR_EXGMAC);
1267 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1268 0x00000005, ERIAR_EXGMAC);
1270 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1271 0x0000001f, ERIAR_EXGMAC);
1272 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1273 0x0000003f, ERIAR_EXGMAC);
1278 static void __rtl8169_check_link_status(struct net_device *dev,
1279 struct rtl8169_private *tp,
1280 void __iomem *ioaddr, bool pm)
1282 unsigned long flags;
1284 spin_lock_irqsave(&tp->lock, flags);
1285 if (tp->link_ok(ioaddr)) {
1286 rtl_link_chg_patch(tp);
1287 /* This is to cancel a scheduled suspend if there's one. */
1289 pm_request_resume(&tp->pci_dev->dev);
1290 netif_carrier_on(dev);
1291 if (net_ratelimit())
1292 netif_info(tp, ifup, dev, "link up\n");
1294 netif_carrier_off(dev);
1295 netif_info(tp, ifdown, dev, "link down\n");
1297 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1299 spin_unlock_irqrestore(&tp->lock, flags);
1302 static void rtl8169_check_link_status(struct net_device *dev,
1303 struct rtl8169_private *tp,
1304 void __iomem *ioaddr)
1306 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1309 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1311 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1313 void __iomem *ioaddr = tp->mmio_addr;
1317 options = RTL_R8(Config1);
1318 if (!(options & PMEnable))
1321 options = RTL_R8(Config3);
1322 if (options & LinkUp)
1323 wolopts |= WAKE_PHY;
1324 if (options & MagicPacket)
1325 wolopts |= WAKE_MAGIC;
1327 options = RTL_R8(Config5);
1329 wolopts |= WAKE_UCAST;
1331 wolopts |= WAKE_BCAST;
1333 wolopts |= WAKE_MCAST;
1338 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1340 struct rtl8169_private *tp = netdev_priv(dev);
1342 spin_lock_irq(&tp->lock);
1344 wol->supported = WAKE_ANY;
1345 wol->wolopts = __rtl8169_get_wol(tp);
1347 spin_unlock_irq(&tp->lock);
1350 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1352 void __iomem *ioaddr = tp->mmio_addr;
1354 static const struct {
1359 { WAKE_ANY, Config1, PMEnable },
1360 { WAKE_PHY, Config3, LinkUp },
1361 { WAKE_MAGIC, Config3, MagicPacket },
1362 { WAKE_UCAST, Config5, UWF },
1363 { WAKE_BCAST, Config5, BWF },
1364 { WAKE_MCAST, Config5, MWF },
1365 { WAKE_ANY, Config5, LanWake }
1368 RTL_W8(Cfg9346, Cfg9346_Unlock);
1370 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1371 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1372 if (wolopts & cfg[i].opt)
1373 options |= cfg[i].mask;
1374 RTL_W8(cfg[i].reg, options);
1377 RTL_W8(Cfg9346, Cfg9346_Lock);
1380 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1382 struct rtl8169_private *tp = netdev_priv(dev);
1384 spin_lock_irq(&tp->lock);
1387 tp->features |= RTL_FEATURE_WOL;
1389 tp->features &= ~RTL_FEATURE_WOL;
1390 __rtl8169_set_wol(tp, wol->wolopts);
1391 spin_unlock_irq(&tp->lock);
1393 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1398 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1400 return rtl_chip_infos[tp->mac_version].fw_name;
1403 static void rtl8169_get_drvinfo(struct net_device *dev,
1404 struct ethtool_drvinfo *info)
1406 struct rtl8169_private *tp = netdev_priv(dev);
1407 struct rtl_fw *rtl_fw = tp->rtl_fw;
1409 strcpy(info->driver, MODULENAME);
1410 strcpy(info->version, RTL8169_VERSION);
1411 strcpy(info->bus_info, pci_name(tp->pci_dev));
1412 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1413 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1417 static int rtl8169_get_regs_len(struct net_device *dev)
1419 return R8169_REGS_SIZE;
1422 static int rtl8169_set_speed_tbi(struct net_device *dev,
1423 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 void __iomem *ioaddr = tp->mmio_addr;
1430 reg = RTL_R32(TBICSR);
1431 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1432 (duplex == DUPLEX_FULL)) {
1433 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1434 } else if (autoneg == AUTONEG_ENABLE)
1435 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1437 netif_warn(tp, link, dev,
1438 "incorrect speed setting refused in TBI mode\n");
1445 static int rtl8169_set_speed_xmii(struct net_device *dev,
1446 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449 int giga_ctrl, bmcr;
1452 rtl_writephy(tp, 0x1f, 0x0000);
1454 if (autoneg == AUTONEG_ENABLE) {
1457 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1458 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1459 ADVERTISE_100HALF | ADVERTISE_100FULL);
1461 if (adv & ADVERTISED_10baseT_Half)
1462 auto_nego |= ADVERTISE_10HALF;
1463 if (adv & ADVERTISED_10baseT_Full)
1464 auto_nego |= ADVERTISE_10FULL;
1465 if (adv & ADVERTISED_100baseT_Half)
1466 auto_nego |= ADVERTISE_100HALF;
1467 if (adv & ADVERTISED_100baseT_Full)
1468 auto_nego |= ADVERTISE_100FULL;
1470 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1472 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1473 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1475 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1476 if (tp->mii.supports_gmii) {
1477 if (adv & ADVERTISED_1000baseT_Half)
1478 giga_ctrl |= ADVERTISE_1000HALF;
1479 if (adv & ADVERTISED_1000baseT_Full)
1480 giga_ctrl |= ADVERTISE_1000FULL;
1481 } else if (adv & (ADVERTISED_1000baseT_Half |
1482 ADVERTISED_1000baseT_Full)) {
1483 netif_info(tp, link, dev,
1484 "PHY does not support 1000Mbps\n");
1488 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1490 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1491 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1495 if (speed == SPEED_10)
1497 else if (speed == SPEED_100)
1498 bmcr = BMCR_SPEED100;
1502 if (duplex == DUPLEX_FULL)
1503 bmcr |= BMCR_FULLDPLX;
1506 rtl_writephy(tp, MII_BMCR, bmcr);
1508 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1509 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1510 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1511 rtl_writephy(tp, 0x17, 0x2138);
1512 rtl_writephy(tp, 0x0e, 0x0260);
1514 rtl_writephy(tp, 0x17, 0x2108);
1515 rtl_writephy(tp, 0x0e, 0x0000);
1524 static int rtl8169_set_speed(struct net_device *dev,
1525 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1527 struct rtl8169_private *tp = netdev_priv(dev);
1530 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1534 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1535 (advertising & ADVERTISED_1000baseT_Full)) {
1536 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1542 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1544 struct rtl8169_private *tp = netdev_priv(dev);
1545 unsigned long flags;
1548 del_timer_sync(&tp->timer);
1550 spin_lock_irqsave(&tp->lock, flags);
1551 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1552 cmd->duplex, cmd->advertising);
1553 spin_unlock_irqrestore(&tp->lock, flags);
1558 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1560 struct rtl8169_private *tp = netdev_priv(dev);
1562 if (dev->mtu > TD_MSS_MAX)
1563 features &= ~NETIF_F_ALL_TSO;
1565 if (dev->mtu > JUMBO_1K &&
1566 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1567 features &= ~NETIF_F_IP_CSUM;
1572 static int rtl8169_set_features(struct net_device *dev, u32 features)
1574 struct rtl8169_private *tp = netdev_priv(dev);
1575 void __iomem *ioaddr = tp->mmio_addr;
1576 unsigned long flags;
1578 spin_lock_irqsave(&tp->lock, flags);
1580 if (features & NETIF_F_RXCSUM)
1581 tp->cp_cmd |= RxChkSum;
1583 tp->cp_cmd &= ~RxChkSum;
1585 if (dev->features & NETIF_F_HW_VLAN_RX)
1586 tp->cp_cmd |= RxVlan;
1588 tp->cp_cmd &= ~RxVlan;
1590 RTL_W16(CPlusCmd, tp->cp_cmd);
1593 spin_unlock_irqrestore(&tp->lock, flags);
1598 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1599 struct sk_buff *skb)
1601 return (vlan_tx_tag_present(skb)) ?
1602 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1605 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1607 u32 opts2 = le32_to_cpu(desc->opts2);
1609 if (opts2 & RxVlanTag)
1610 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1615 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1617 struct rtl8169_private *tp = netdev_priv(dev);
1618 void __iomem *ioaddr = tp->mmio_addr;
1622 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1623 cmd->port = PORT_FIBRE;
1624 cmd->transceiver = XCVR_INTERNAL;
1626 status = RTL_R32(TBICSR);
1627 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1628 cmd->autoneg = !!(status & TBINwEnable);
1630 ethtool_cmd_speed_set(cmd, SPEED_1000);
1631 cmd->duplex = DUPLEX_FULL; /* Always set */
1636 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1638 struct rtl8169_private *tp = netdev_priv(dev);
1640 return mii_ethtool_gset(&tp->mii, cmd);
1643 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1645 struct rtl8169_private *tp = netdev_priv(dev);
1646 unsigned long flags;
1649 spin_lock_irqsave(&tp->lock, flags);
1651 rc = tp->get_settings(dev, cmd);
1653 spin_unlock_irqrestore(&tp->lock, flags);
1657 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1660 struct rtl8169_private *tp = netdev_priv(dev);
1661 unsigned long flags;
1663 if (regs->len > R8169_REGS_SIZE)
1664 regs->len = R8169_REGS_SIZE;
1666 spin_lock_irqsave(&tp->lock, flags);
1667 memcpy_fromio(p, tp->mmio_addr, regs->len);
1668 spin_unlock_irqrestore(&tp->lock, flags);
1671 static u32 rtl8169_get_msglevel(struct net_device *dev)
1673 struct rtl8169_private *tp = netdev_priv(dev);
1675 return tp->msg_enable;
1678 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1680 struct rtl8169_private *tp = netdev_priv(dev);
1682 tp->msg_enable = value;
1685 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1692 "tx_single_collisions",
1693 "tx_multi_collisions",
1701 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1705 return ARRAY_SIZE(rtl8169_gstrings);
1711 static void rtl8169_update_counters(struct net_device *dev)
1713 struct rtl8169_private *tp = netdev_priv(dev);
1714 void __iomem *ioaddr = tp->mmio_addr;
1715 struct device *d = &tp->pci_dev->dev;
1716 struct rtl8169_counters *counters;
1722 * Some chips are unable to dump tally counters when the receiver
1725 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1728 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1732 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1733 cmd = (u64)paddr & DMA_BIT_MASK(32);
1734 RTL_W32(CounterAddrLow, cmd);
1735 RTL_W32(CounterAddrLow, cmd | CounterDump);
1738 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1739 memcpy(&tp->counters, counters, sizeof(*counters));
1745 RTL_W32(CounterAddrLow, 0);
1746 RTL_W32(CounterAddrHigh, 0);
1748 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1751 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1752 struct ethtool_stats *stats, u64 *data)
1754 struct rtl8169_private *tp = netdev_priv(dev);
1758 rtl8169_update_counters(dev);
1760 data[0] = le64_to_cpu(tp->counters.tx_packets);
1761 data[1] = le64_to_cpu(tp->counters.rx_packets);
1762 data[2] = le64_to_cpu(tp->counters.tx_errors);
1763 data[3] = le32_to_cpu(tp->counters.rx_errors);
1764 data[4] = le16_to_cpu(tp->counters.rx_missed);
1765 data[5] = le16_to_cpu(tp->counters.align_errors);
1766 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1767 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1768 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1769 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1770 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1771 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1772 data[12] = le16_to_cpu(tp->counters.tx_underun);
1775 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1779 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1784 static const struct ethtool_ops rtl8169_ethtool_ops = {
1785 .get_drvinfo = rtl8169_get_drvinfo,
1786 .get_regs_len = rtl8169_get_regs_len,
1787 .get_link = ethtool_op_get_link,
1788 .get_settings = rtl8169_get_settings,
1789 .set_settings = rtl8169_set_settings,
1790 .get_msglevel = rtl8169_get_msglevel,
1791 .set_msglevel = rtl8169_set_msglevel,
1792 .get_regs = rtl8169_get_regs,
1793 .get_wol = rtl8169_get_wol,
1794 .set_wol = rtl8169_set_wol,
1795 .get_strings = rtl8169_get_strings,
1796 .get_sset_count = rtl8169_get_sset_count,
1797 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1800 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1801 struct net_device *dev, u8 default_version)
1803 void __iomem *ioaddr = tp->mmio_addr;
1805 * The driver currently handles the 8168Bf and the 8168Be identically
1806 * but they can be identified more specifically through the test below
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1811 * Same thing for the 8101Eb and the 8101Ec:
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1815 static const struct rtl_mac_info {
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1835 /* 8168DP family. */
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1874 /* FIXME: where did these entries come from ? -- FR */
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1889 const struct rtl_mac_info *p = mac_info;
1892 reg = RTL_R32(TxConfig);
1893 while ((reg & p->mask) != p->val)
1895 tp->mac_version = p->mac_version;
1897 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1898 netif_notice(tp, probe, dev,
1899 "unknown MAC, using family default\n");
1900 tp->mac_version = default_version;
1904 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1906 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1914 static void rtl_writephy_batch(struct rtl8169_private *tp,
1915 const struct phy_reg *regs, int len)
1918 rtl_writephy(tp, regs->reg, regs->val);
1923 #define PHY_READ 0x00000000
1924 #define PHY_DATA_OR 0x10000000
1925 #define PHY_DATA_AND 0x20000000
1926 #define PHY_BJMPN 0x30000000
1927 #define PHY_READ_EFUSE 0x40000000
1928 #define PHY_READ_MAC_BYTE 0x50000000
1929 #define PHY_WRITE_MAC_BYTE 0x60000000
1930 #define PHY_CLEAR_READCOUNT 0x70000000
1931 #define PHY_WRITE 0x80000000
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1935 #define PHY_WRITE_PREVIOUS 0xc0000000
1936 #define PHY_SKIPN 0xd0000000
1937 #define PHY_DELAY_MS 0xe0000000
1938 #define PHY_WRITE_ERI_WORD 0xf0000000
1942 char version[RTL_VER_SIZE];
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1950 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1952 const struct firmware *fw = rtl_fw->fw;
1953 struct fw_info *fw_info = (struct fw_info *)fw->data;
1954 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1955 char *version = rtl_fw->version;
1958 if (fw->size < FW_OPCODE_SIZE)
1961 if (!fw_info->magic) {
1962 size_t i, size, start;
1965 if (fw->size < sizeof(*fw_info))
1968 for (i = 0; i < fw->size; i++)
1969 checksum += fw->data[i];
1973 start = le32_to_cpu(fw_info->fw_start);
1974 if (start > fw->size)
1977 size = le32_to_cpu(fw_info->fw_len);
1978 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1981 memcpy(version, fw_info->version, RTL_VER_SIZE);
1983 pa->code = (__le32 *)(fw->data + start);
1986 if (fw->size % FW_OPCODE_SIZE)
1989 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1991 pa->code = (__le32 *)fw->data;
1992 pa->size = fw->size / FW_OPCODE_SIZE;
1994 version[RTL_VER_SIZE - 1] = 0;
2001 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2002 struct rtl_fw_phy_action *pa)
2007 for (index = 0; index < pa->size; index++) {
2008 u32 action = le32_to_cpu(pa->code[index]);
2009 u32 regno = (action & 0x0fff0000) >> 16;
2011 switch(action & 0xf0000000) {
2015 case PHY_READ_EFUSE:
2016 case PHY_CLEAR_READCOUNT:
2018 case PHY_WRITE_PREVIOUS:
2023 if (regno > index) {
2024 netif_err(tp, ifup, tp->dev,
2025 "Out of range of firmware\n");
2029 case PHY_READCOUNT_EQ_SKIP:
2030 if (index + 2 >= pa->size) {
2031 netif_err(tp, ifup, tp->dev,
2032 "Out of range of firmware\n");
2036 case PHY_COMP_EQ_SKIPN:
2037 case PHY_COMP_NEQ_SKIPN:
2039 if (index + 1 + regno >= pa->size) {
2040 netif_err(tp, ifup, tp->dev,
2041 "Out of range of firmware\n");
2046 case PHY_READ_MAC_BYTE:
2047 case PHY_WRITE_MAC_BYTE:
2048 case PHY_WRITE_ERI_WORD:
2050 netif_err(tp, ifup, tp->dev,
2051 "Invalid action 0x%08x\n", action);
2060 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2062 struct net_device *dev = tp->dev;
2065 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2066 netif_err(tp, ifup, dev, "invalid firwmare\n");
2070 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2076 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2078 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2082 predata = count = 0;
2084 for (index = 0; index < pa->size; ) {
2085 u32 action = le32_to_cpu(pa->code[index]);
2086 u32 data = action & 0x0000ffff;
2087 u32 regno = (action & 0x0fff0000) >> 16;
2092 switch(action & 0xf0000000) {
2094 predata = rtl_readphy(tp, regno);
2109 case PHY_READ_EFUSE:
2110 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2113 case PHY_CLEAR_READCOUNT:
2118 rtl_writephy(tp, regno, data);
2121 case PHY_READCOUNT_EQ_SKIP:
2122 index += (count == data) ? 2 : 1;
2124 case PHY_COMP_EQ_SKIPN:
2125 if (predata == data)
2129 case PHY_COMP_NEQ_SKIPN:
2130 if (predata != data)
2134 case PHY_WRITE_PREVIOUS:
2135 rtl_writephy(tp, regno, predata);
2146 case PHY_READ_MAC_BYTE:
2147 case PHY_WRITE_MAC_BYTE:
2148 case PHY_WRITE_ERI_WORD:
2155 static void rtl_release_firmware(struct rtl8169_private *tp)
2157 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2158 release_firmware(tp->rtl_fw->fw);
2161 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2164 static void rtl_apply_firmware(struct rtl8169_private *tp)
2166 struct rtl_fw *rtl_fw = tp->rtl_fw;
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2169 if (!IS_ERR_OR_NULL(rtl_fw))
2170 rtl_phy_write_fw(tp, rtl_fw);
2173 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2175 if (rtl_readphy(tp, reg) != val)
2176 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2178 rtl_apply_firmware(tp);
2181 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2183 static const struct phy_reg phy_reg_init[] = {
2245 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2248 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2250 static const struct phy_reg phy_reg_init[] = {
2256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2259 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2261 struct pci_dev *pdev = tp->pci_dev;
2263 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2264 (pdev->subsystem_device != 0xe000))
2267 rtl_writephy(tp, 0x1f, 0x0001);
2268 rtl_writephy(tp, 0x10, 0xf01b);
2269 rtl_writephy(tp, 0x1f, 0x0000);
2272 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2274 static const struct phy_reg phy_reg_init[] = {
2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2316 rtl8169scd_hw_phy_config_quirk(tp);
2319 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2321 static const struct phy_reg phy_reg_init[] = {
2369 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2372 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2374 static const struct phy_reg phy_reg_init[] = {
2379 rtl_writephy(tp, 0x1f, 0x0001);
2380 rtl_patchphy(tp, 0x16, 1 << 0);
2382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2385 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2387 static const struct phy_reg phy_reg_init[] = {
2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2396 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2398 static const struct phy_reg phy_reg_init[] = {
2406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2409 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2411 static const struct phy_reg phy_reg_init[] = {
2417 rtl_writephy(tp, 0x1f, 0x0000);
2418 rtl_patchphy(tp, 0x14, 1 << 5);
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
2421 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2424 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2426 static const struct phy_reg phy_reg_init[] = {
2446 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2448 rtl_patchphy(tp, 0x14, 1 << 5);
2449 rtl_patchphy(tp, 0x0d, 1 << 5);
2450 rtl_writephy(tp, 0x1f, 0x0000);
2453 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2455 static const struct phy_reg phy_reg_init[] = {
2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2475 rtl_patchphy(tp, 0x16, 1 << 0);
2476 rtl_patchphy(tp, 0x14, 1 << 5);
2477 rtl_patchphy(tp, 0x0d, 1 << 5);
2478 rtl_writephy(tp, 0x1f, 0x0000);
2481 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2483 static const struct phy_reg phy_reg_init[] = {
2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2497 rtl_patchphy(tp, 0x16, 1 << 0);
2498 rtl_patchphy(tp, 0x14, 1 << 5);
2499 rtl_patchphy(tp, 0x0d, 1 << 5);
2500 rtl_writephy(tp, 0x1f, 0x0000);
2503 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2505 rtl8168c_3_hw_phy_config(tp);
2508 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2510 static const struct phy_reg phy_reg_init_0[] = {
2511 /* Channel Estimation */
2532 * Enhance line driver power
2541 * Can not link to 1Gbps with bad cable
2542 * Decrease SNR threshold form 21.07dB to 19.04dB
2550 void __iomem *ioaddr = tp->mmio_addr;
2552 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2556 * Fine Tune Switching regulator parameter
2558 rtl_writephy(tp, 0x1f, 0x0002);
2559 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2560 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2562 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2563 static const struct phy_reg phy_reg_init[] = {
2573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2575 val = rtl_readphy(tp, 0x0d);
2577 if ((val & 0x00ff) != 0x006c) {
2578 static const u32 set[] = {
2579 0x0065, 0x0066, 0x0067, 0x0068,
2580 0x0069, 0x006a, 0x006b, 0x006c
2584 rtl_writephy(tp, 0x1f, 0x0002);
2587 for (i = 0; i < ARRAY_SIZE(set); i++)
2588 rtl_writephy(tp, 0x0d, val | set[i]);
2591 static const struct phy_reg phy_reg_init[] = {
2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2602 /* RSET couple improve */
2603 rtl_writephy(tp, 0x1f, 0x0002);
2604 rtl_patchphy(tp, 0x0d, 0x0300);
2605 rtl_patchphy(tp, 0x0f, 0x0010);
2607 /* Fine tune PLL performance */
2608 rtl_writephy(tp, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2612 rtl_writephy(tp, 0x1f, 0x0005);
2613 rtl_writephy(tp, 0x05, 0x001b);
2615 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2617 rtl_writephy(tp, 0x1f, 0x0000);
2620 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2622 static const struct phy_reg phy_reg_init_0[] = {
2623 /* Channel Estimation */
2644 * Enhance line driver power
2653 * Can not link to 1Gbps with bad cable
2654 * Decrease SNR threshold form 21.07dB to 19.04dB
2662 void __iomem *ioaddr = tp->mmio_addr;
2664 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2666 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2667 static const struct phy_reg phy_reg_init[] = {
2678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2680 val = rtl_readphy(tp, 0x0d);
2681 if ((val & 0x00ff) != 0x006c) {
2682 static const u32 set[] = {
2683 0x0065, 0x0066, 0x0067, 0x0068,
2684 0x0069, 0x006a, 0x006b, 0x006c
2688 rtl_writephy(tp, 0x1f, 0x0002);
2691 for (i = 0; i < ARRAY_SIZE(set); i++)
2692 rtl_writephy(tp, 0x0d, val | set[i]);
2695 static const struct phy_reg phy_reg_init[] = {
2703 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706 /* Fine tune PLL performance */
2707 rtl_writephy(tp, 0x1f, 0x0002);
2708 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2709 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2711 /* Switching regulator Slew rate */
2712 rtl_writephy(tp, 0x1f, 0x0002);
2713 rtl_patchphy(tp, 0x0f, 0x0017);
2715 rtl_writephy(tp, 0x1f, 0x0005);
2716 rtl_writephy(tp, 0x05, 0x001b);
2718 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2720 rtl_writephy(tp, 0x1f, 0x0000);
2723 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2725 static const struct phy_reg phy_reg_init[] = {
2781 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2784 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2786 static const struct phy_reg phy_reg_init[] = {
2796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2797 rtl_patchphy(tp, 0x0d, 1 << 5);
2800 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2802 static const struct phy_reg phy_reg_init[] = {
2803 /* Enable Delay cap */
2809 /* Channel estimation fine tune */
2818 /* Update PFM & 10M TX idle timer */
2830 rtl_apply_firmware(tp);
2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2834 /* DCO enable for 10M IDLE Power */
2835 rtl_writephy(tp, 0x1f, 0x0007);
2836 rtl_writephy(tp, 0x1e, 0x0023);
2837 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2838 rtl_writephy(tp, 0x1f, 0x0000);
2840 /* For impedance matching */
2841 rtl_writephy(tp, 0x1f, 0x0002);
2842 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2843 rtl_writephy(tp, 0x1f, 0x0000);
2845 /* PHY auto speed down */
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x002d);
2848 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2852 rtl_writephy(tp, 0x1f, 0x0005);
2853 rtl_writephy(tp, 0x05, 0x8b86);
2854 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2855 rtl_writephy(tp, 0x1f, 0x0000);
2857 rtl_writephy(tp, 0x1f, 0x0005);
2858 rtl_writephy(tp, 0x05, 0x8b85);
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2860 rtl_writephy(tp, 0x1f, 0x0007);
2861 rtl_writephy(tp, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2863 rtl_writephy(tp, 0x1f, 0x0006);
2864 rtl_writephy(tp, 0x00, 0x5a00);
2865 rtl_writephy(tp, 0x1f, 0x0000);
2866 rtl_writephy(tp, 0x0d, 0x0007);
2867 rtl_writephy(tp, 0x0e, 0x003c);
2868 rtl_writephy(tp, 0x0d, 0x4007);
2869 rtl_writephy(tp, 0x0e, 0x0000);
2870 rtl_writephy(tp, 0x0d, 0x0000);
2873 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2875 static const struct phy_reg phy_reg_init[] = {
2876 /* Enable Delay cap */
2885 /* Channel estimation fine tune */
2902 rtl_apply_firmware(tp);
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2906 /* For 4-corner performance improve */
2907 rtl_writephy(tp, 0x1f, 0x0005);
2908 rtl_writephy(tp, 0x05, 0x8b80);
2909 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2912 /* PHY auto speed down */
2913 rtl_writephy(tp, 0x1f, 0x0004);
2914 rtl_writephy(tp, 0x1f, 0x0007);
2915 rtl_writephy(tp, 0x1e, 0x002d);
2916 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0002);
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2921 /* improve 10M EEE waveform */
2922 rtl_writephy(tp, 0x1f, 0x0005);
2923 rtl_writephy(tp, 0x05, 0x8b86);
2924 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2925 rtl_writephy(tp, 0x1f, 0x0000);
2927 /* Improve 2-pair detection performance */
2928 rtl_writephy(tp, 0x1f, 0x0005);
2929 rtl_writephy(tp, 0x05, 0x8b85);
2930 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2931 rtl_writephy(tp, 0x1f, 0x0000);
2934 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2936 rtl_writephy(tp, 0x1f, 0x0005);
2937 rtl_writephy(tp, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp, 0x1f, 0x0004);
2940 rtl_writephy(tp, 0x1f, 0x0007);
2941 rtl_writephy(tp, 0x1e, 0x0020);
2942 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2943 rtl_writephy(tp, 0x1f, 0x0002);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_writephy(tp, 0x0d, 0x0007);
2946 rtl_writephy(tp, 0x0e, 0x003c);
2947 rtl_writephy(tp, 0x0d, 0x4007);
2948 rtl_writephy(tp, 0x0e, 0x0000);
2949 rtl_writephy(tp, 0x0d, 0x0000);
2952 rtl_writephy(tp, 0x1f, 0x0003);
2953 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2954 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2955 rtl_writephy(tp, 0x1f, 0x0000);
2958 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2960 static const struct phy_reg phy_reg_init[] = {
2961 /* Channel estimation fine tune */
2966 /* Modify green table for giga & fnet */
2983 /* Modify green table for 10M */
2989 /* Disable hiimpedance detection (RTCT) */
2995 rtl_apply_firmware(tp);
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2999 /* For 4-corner performance improve */
3000 rtl_writephy(tp, 0x1f, 0x0005);
3001 rtl_writephy(tp, 0x05, 0x8b80);
3002 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3003 rtl_writephy(tp, 0x1f, 0x0000);
3005 /* PHY auto speed down */
3006 rtl_writephy(tp, 0x1f, 0x0007);
3007 rtl_writephy(tp, 0x1e, 0x002d);
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3009 rtl_writephy(tp, 0x1f, 0x0000);
3010 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3012 /* Improve 10M EEE waveform */
3013 rtl_writephy(tp, 0x1f, 0x0005);
3014 rtl_writephy(tp, 0x05, 0x8b86);
3015 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3016 rtl_writephy(tp, 0x1f, 0x0000);
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp, 0x1f, 0x0005);
3020 rtl_writephy(tp, 0x05, 0x8b85);
3021 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3027 rtl_apply_firmware(tp);
3029 /* For 4-corner performance improve */
3030 rtl_writephy(tp, 0x1f, 0x0005);
3031 rtl_writephy(tp, 0x05, 0x8b80);
3032 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3035 /* PHY auto speed down */
3036 rtl_writephy(tp, 0x1f, 0x0007);
3037 rtl_writephy(tp, 0x1e, 0x002d);
3038 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp, 0x1f, 0x0000);
3040 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3042 /* Improve 10M EEE waveform */
3043 rtl_writephy(tp, 0x1f, 0x0005);
3044 rtl_writephy(tp, 0x05, 0x8b86);