drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
  51
  52 #ifdef RTL8169_DEBUG
  53 #define assert(expr) \
  54         if (!(expr)) {                                  \
  55                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  56                 #expr,__FILE__,__func__,__LINE__);              \
  57         }
  58 #define dprintk(fmt, args...) \
  59         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  60 #else
  61 #define assert(expr) do {} while (0)
  62 #define dprintk(fmt, args...)   do {} while (0)
  63 #endif /* RTL8169_DEBUG */
  64
  65 #define R8169_MSG_DEFAULT \
  66         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  67
  68 #define TX_SLOTS_AVAIL(tp) \
  69         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  70
  71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  73         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  74
  75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  76    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  77 static const int multicast_filter_limit = 32;
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  82
  83 #define R8169_REGS_SIZE         256
  84 #define R8169_NAPI_WEIGHT       64
  85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  86 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  89
  90 #define RTL8169_TX_TIMEOUT      (6*HZ)
  91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_VER_35,
 137         RTL_GIGA_MAC_VER_36,
 138         RTL_GIGA_MAC_VER_37,
 139         RTL_GIGA_MAC_VER_38,
 140         RTL_GIGA_MAC_VER_39,
 141         RTL_GIGA_MAC_VER_40,
 142         RTL_GIGA_MAC_VER_41,
 143         RTL_GIGA_MAC_NONE   = 0xff,
 144 };
 145
 146 enum rtl_tx_desc_version {
 147         RTL_TD_0        = 0,
 148         RTL_TD_1        = 1,
 149 };
 150
 151 #define JUMBO_1K        ETH_DATA_LEN
 152 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 153 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 154 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 155 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 156
 157 #define _R(NAME,TD,FW,SZ,B) {   \
 158         .name = NAME,           \
 159         .txd_version = TD,      \
 160         .fw_name = FW,          \
 161         .jumbo_max = SZ,        \
 162         .jumbo_tx_csum = B      \
 163 }
 164
 165 static const struct {
 166         const char *name;
 167         enum rtl_tx_desc_version txd_version;
 168         const char *fw_name;
 169         u16 jumbo_max;
 170         bool jumbo_tx_csum;
 171 } rtl_chip_infos[] = {
 172         /* PCI devices. */
 173         [RTL_GIGA_MAC_VER_01] =
 174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_02] =
 176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_03] =
 178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_04] =
 180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_05] =
 182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_06] =
 184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 185         /* PCI-E devices. */
 186         [RTL_GIGA_MAC_VER_07] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_08] =
 189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 190         [RTL_GIGA_MAC_VER_09] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_10] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_11] =
 195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 196         [RTL_GIGA_MAC_VER_12] =
 197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 198         [RTL_GIGA_MAC_VER_13] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_14] =
 201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 202         [RTL_GIGA_MAC_VER_15] =
 203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 204         [RTL_GIGA_MAC_VER_16] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_17] =
 207                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 208         [RTL_GIGA_MAC_VER_18] =
 209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_19] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_20] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_21] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_22] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_23] =
 219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_24] =
 221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_25] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_26] =
 226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 227                                                         JUMBO_9K, false),
 228         [RTL_GIGA_MAC_VER_27] =
 229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 230         [RTL_GIGA_MAC_VER_28] =
 231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_29] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_30] =
 236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 237                                                         JUMBO_1K, true),
 238         [RTL_GIGA_MAC_VER_31] =
 239                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_32] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_33] =
 244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_34] =
 247                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_35] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 251                                                         JUMBO_9K, false),
 252         [RTL_GIGA_MAC_VER_36] =
 253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 254                                                         JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_37] =
 256                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 257                                                         JUMBO_1K, true),
 258         [RTL_GIGA_MAC_VER_38] =
 259                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_39] =
 262                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 263                                                         JUMBO_1K, true),
 264         [RTL_GIGA_MAC_VER_40] =
 265                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_41] =
 268                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 269 };
 270 #undef _R
 271
 272 enum cfg_version {
 273         RTL_CFG_0 = 0x00,
 274         RTL_CFG_1,
 275         RTL_CFG_2
 276 };
 277
 278 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 282         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 283         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 284         { PCI_VENDOR_ID_DLINK,                  0x4300,
 285                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 286         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 289         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 290         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 291                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 292         { 0x0001,                               0x8168,
 293                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 294         {0,},
 295 };
 296
 297 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 298
 299 static int rx_buf_sz = 16383;
 300 static int use_dac;
 301 static struct {
 302         u32 msg_enable;
 303 } debug = { -1 };
 304
 305 enum rtl_registers {
 306         MAC0            = 0,    /* Ethernet hardware address. */
 307         MAC4            = 4,
 308         MAR0            = 8,    /* Multicast filter. */
 309         CounterAddrLow          = 0x10,
 310         CounterAddrHigh         = 0x14,
 311         TxDescStartAddrLow      = 0x20,
 312         TxDescStartAddrHigh     = 0x24,
 313         TxHDescStartAddrLow     = 0x28,
 314         TxHDescStartAddrHigh    = 0x2c,
 315         FLASH           = 0x30,
 316         ERSR            = 0x36,
 317         ChipCmd         = 0x37,
 318         TxPoll          = 0x38,
 319         IntrMask        = 0x3c,
 320         IntrStatus      = 0x3e,
 321
 322         TxConfig        = 0x40,
 323 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 324 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 325
 326         RxConfig        = 0x44,
 327 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 328 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 329 #define RXCFG_FIFO_SHIFT                13
 330                                         /* No threshold before first PCI xfer */
 331 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 332 #define RXCFG_DMA_SHIFT                 8
 333                                         /* Unlimited maximum PCI burst. */
 334 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 335
 336         RxMissed        = 0x4c,
 337         Cfg9346         = 0x50,
 338         Config0         = 0x51,
 339         Config1         = 0x52,
 340         Config2         = 0x53,
 341 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 342
 343         Config3         = 0x54,
 344         Config4         = 0x55,
 345         Config5         = 0x56,
 346         MultiIntr       = 0x5c,
 347         PHYAR           = 0x60,
 348         PHYstatus       = 0x6c,
 349         RxMaxSize       = 0xda,
 350         CPlusCmd        = 0xe0,
 351         IntrMitigate    = 0xe2,
 352         RxDescAddrLow   = 0xe4,
 353         RxDescAddrHigh  = 0xe8,
 354         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 355
 356 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 357
 358         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 359
 360 #define TxPacketMax     (8064 >> 7)
 361 #define EarlySize       0x27
 362
 363         FuncEvent       = 0xf0,
 364         FuncEventMask   = 0xf4,
 365         FuncPresetState = 0xf8,
 366         FuncForceEvent  = 0xfc,
 367 };
 368
 369 enum rtl8110_registers {
 370         TBICSR                  = 0x64,
 371         TBI_ANAR                = 0x68,
 372         TBI_LPAR                = 0x6a,
 373 };
 374
 375 enum rtl8168_8101_registers {
 376         CSIDR                   = 0x64,
 377         CSIAR                   = 0x68,
 378 #define CSIAR_FLAG                      0x80000000
 379 #define CSIAR_WRITE_CMD                 0x80000000
 380 #define CSIAR_BYTE_ENABLE               0x0f
 381 #define CSIAR_BYTE_ENABLE_SHIFT         12
 382 #define CSIAR_ADDR_MASK                 0x0fff
 383 #define CSIAR_FUNC_CARD                 0x00000000
 384 #define CSIAR_FUNC_SDIO                 0x00010000
 385 #define CSIAR_FUNC_NIC                  0x00020000
 386         PMCH                    = 0x6f,
 387         EPHYAR                  = 0x80,
 388 #define EPHYAR_FLAG                     0x80000000
 389 #define EPHYAR_WRITE_CMD                0x80000000
 390 #define EPHYAR_REG_MASK                 0x1f
 391 #define EPHYAR_REG_SHIFT                16
 392 #define EPHYAR_DATA_MASK                0xffff
 393         DLLPR                   = 0xd0,
 394 #define PFM_EN                          (1 << 6)
 395         DBG_REG                 = 0xd1,
 396 #define FIX_NAK_1                       (1 << 4)
 397 #define FIX_NAK_2                       (1 << 3)
 398         TWSI                    = 0xd2,
 399         MCU                     = 0xd3,
 400 #define NOW_IS_OOB                      (1 << 7)
 401 #define TX_EMPTY                        (1 << 5)
 402 #define RX_EMPTY                        (1 << 4)
 403 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 404 #define EN_NDP                          (1 << 3)
 405 #define EN_OOB_RESET                    (1 << 2)
 406 #define LINK_LIST_RDY                   (1 << 1)
 407         EFUSEAR                 = 0xdc,
 408 #define EFUSEAR_FLAG                    0x80000000
 409 #define EFUSEAR_WRITE_CMD               0x80000000
 410 #define EFUSEAR_READ_CMD                0x00000000
 411 #define EFUSEAR_REG_MASK                0x03ff
 412 #define EFUSEAR_REG_SHIFT               8
 413 #define EFUSEAR_DATA_MASK               0xff
 414 };
 415
 416 enum rtl8168_registers {
 417         LED_FREQ                = 0x1a,
 418         EEE_LED                 = 0x1b,
 419         ERIDR                   = 0x70,
 420         ERIAR                   = 0x74,
 421 #define ERIAR_FLAG                      0x80000000
 422 #define ERIAR_WRITE_CMD                 0x80000000
 423 #define ERIAR_READ_CMD                  0x00000000
 424 #define ERIAR_ADDR_BYTE_ALIGN           4
 425 #define ERIAR_TYPE_SHIFT                16
 426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 429 #define ERIAR_MASK_SHIFT                12
 430 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 431 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 432 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 433 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 434         EPHY_RXER_NUM           = 0x7c,
 435         OCPDR                   = 0xb0, /* OCP GPHY access */
 436 #define OCPDR_WRITE_CMD                 0x80000000
 437 #define OCPDR_READ_CMD                  0x00000000
 438 #define OCPDR_REG_MASK                  0x7f
 439 #define OCPDR_GPHY_REG_SHIFT            16
 440 #define OCPDR_DATA_MASK                 0xffff
 441         OCPAR                   = 0xb4,
 442 #define OCPAR_FLAG                      0x80000000
 443 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 444 #define OCPAR_GPHY_READ_CMD             0x0000f060
 445         GPHY_OCP                = 0xb8,
 446         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 447         MISC                    = 0xf0, /* 8168e only. */
 448 #define TXPLA_RST                       (1 << 29)
 449 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 450 #define PWM_EN                          (1 << 22)
 451 #define RXDV_GATED_EN                   (1 << 19)
 452 #define EARLY_TALLY_EN                  (1 << 16)
 453 };
 454
 455 enum rtl_register_content {
 456         /* InterruptStatusBits */
 457         SYSErr          = 0x8000,
 458         PCSTimeout      = 0x4000,
 459         SWInt           = 0x0100,
 460         TxDescUnavail   = 0x0080,
 461         RxFIFOOver      = 0x0040,
 462         LinkChg         = 0x0020,
 463         RxOverflow      = 0x0010,
 464         TxErr           = 0x0008,
 465         TxOK            = 0x0004,
 466         RxErr           = 0x0002,
 467         RxOK            = 0x0001,
 468
 469         /* RxStatusDesc */
 470         RxBOVF  = (1 << 24),
 471         RxFOVF  = (1 << 23),
 472         RxRWT   = (1 << 22),
 473         RxRES   = (1 << 21),
 474         RxRUNT  = (1 << 20),
 475         RxCRC   = (1 << 19),
 476
 477         /* ChipCmdBits */
 478         StopReq         = 0x80,
 479         CmdReset        = 0x10,
 480         CmdRxEnb        = 0x08,
 481         CmdTxEnb        = 0x04,
 482         RxBufEmpty      = 0x01,
 483
 484         /* TXPoll register p.5 */
 485         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 486         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 487         FSWInt          = 0x01,         /* Forced software interrupt */
 488
 489         /* Cfg9346Bits */
 490         Cfg9346_Lock    = 0x00,
 491         Cfg9346_Unlock  = 0xc0,
 492
 493         /* rx_mode_bits */
 494         AcceptErr       = 0x20,
 495         AcceptRunt      = 0x10,
 496         AcceptBroadcast = 0x08,
 497         AcceptMulticast = 0x04,
 498         AcceptMyPhys    = 0x02,
 499         AcceptAllPhys   = 0x01,
 500 #define RX_CONFIG_ACCEPT_MASK           0x3f
 501
 502         /* TxConfigBits */
 503         TxInterFrameGapShift = 24,
 504         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 505
 506         /* Config1 register p.24 */
 507         LEDS1           = (1 << 7),
 508         LEDS0           = (1 << 6),
 509         Speed_down      = (1 << 4),
 510         MEMMAP          = (1 << 3),
 511         IOMAP           = (1 << 2),
 512         VPD             = (1 << 1),
 513         PMEnable        = (1 << 0),     /* Power Management Enable */
 514
 515         /* Config2 register p. 25 */
 516         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 517         PCI_Clock_66MHz = 0x01,
 518         PCI_Clock_33MHz = 0x00,
 519
 520         /* Config3 register p.25 */
 521         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 522         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 523         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 524         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 525
 526         /* Config4 register */
 527         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 528
 529         /* Config5 register p.27 */
 530         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 531         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 532         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 533         Spi_en          = (1 << 3),
 534         LanWake         = (1 << 1),     /* LanWake enable/disable */
 535         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 536
 537         /* TBICSR p.28 */
 538         TBIReset        = 0x80000000,
 539         TBILoopback     = 0x40000000,
 540         TBINwEnable     = 0x20000000,
 541         TBINwRestart    = 0x10000000,
 542         TBILinkOk       = 0x02000000,
 543         TBINwComplete   = 0x01000000,
 544
 545         /* CPlusCmd p.31 */
 546         EnableBist      = (1 << 15),    // 8168 8101
 547         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 548         Normal_mode     = (1 << 13),    // unused
 549         Force_half_dup  = (1 << 12),    // 8168 8101
 550         Force_rxflow_en = (1 << 11),    // 8168 8101
 551         Force_txflow_en = (1 << 10),    // 8168 8101
 552         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 553         ASF             = (1 << 8),     // 8168 8101
 554         PktCntrDisable  = (1 << 7),     // 8168 8101
 555         Mac_dbgo_sel    = 0x001c,       // 8168
 556         RxVlan          = (1 << 6),
 557         RxChkSum        = (1 << 5),
 558         PCIDAC          = (1 << 4),
 559         PCIMulRW        = (1 << 3),
 560         INTT_0          = 0x0000,       // 8168
 561         INTT_1          = 0x0001,       // 8168
 562         INTT_2          = 0x0002,       // 8168
 563         INTT_3          = 0x0003,       // 8168
 564
 565         /* rtl8169_PHYstatus */
 566         TBI_Enable      = 0x80,
 567         TxFlowCtrl      = 0x40,
 568         RxFlowCtrl      = 0x20,
 569         _1000bpsF       = 0x10,
 570         _100bps         = 0x08,
 571         _10bps          = 0x04,
 572         LinkStatus      = 0x02,
 573         FullDup         = 0x01,
 574
 575         /* _TBICSRBit */
 576         TBILinkOK       = 0x02000000,
 577
 578         /* DumpCounterCommand */
 579         CounterDump     = 0x8,
 580 };
 581
 582 enum rtl_desc_bit {
 583         /* First doubleword. */
 584         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 585         RingEnd         = (1 << 30), /* End of descriptor ring */
 586         FirstFrag       = (1 << 29), /* First segment of a packet */
 587         LastFrag        = (1 << 28), /* Final segment of a packet */
 588 };
 589
 590 /* Generic case. */
 591 enum rtl_tx_desc_bit {
 592         /* First doubleword. */
 593         TD_LSO          = (1 << 27),            /* Large Send Offload */
 594 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 595
 596         /* Second doubleword. */
 597         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 598 };
 599
 600 /* 8169, 8168b and 810x except 8102e. */
 601 enum rtl_tx_desc_bit_0 {
 602         /* First doubleword. */
 603 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 604         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 605         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 606         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 607 };
 608
 609 /* 8102e, 8168c and beyond. */
 610 enum rtl_tx_desc_bit_1 {
 611         /* Second doubleword. */
 612 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 613         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 614         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 615         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 616 };
 617
 618 static const struct rtl_tx_desc_info {
 619         struct {
 620                 u32 udp;
 621                 u32 tcp;
 622         } checksum;
 623         u16 mss_shift;
 624         u16 opts_offset;
 625 } tx_desc_info [] = {
 626         [RTL_TD_0] = {
 627                 .checksum = {
 628                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 629                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 630                 },
 631                 .mss_shift      = TD0_MSS_SHIFT,
 632                 .opts_offset    = 0
 633         },
 634         [RTL_TD_1] = {
 635                 .checksum = {
 636                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 637                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 638                 },
 639                 .mss_shift      = TD1_MSS_SHIFT,
 640                 .opts_offset    = 1
 641         }
 642 };
 643
 644 enum rtl_rx_desc_bit {
 645         /* Rx private */
 646         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 647         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 648
 649 #define RxProtoUDP      (PID1)
 650 #define RxProtoTCP      (PID0)
 651 #define RxProtoIP       (PID1 | PID0)
 652 #define RxProtoMask     RxProtoIP
 653
 654         IPFail          = (1 << 16), /* IP checksum failed */
 655         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 656         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 657         RxVlanTag       = (1 << 16), /* VLAN tag available */
 658 };
 659
 660 #define RsvdMask        0x3fffc000
 661
 662 struct TxDesc {
 663         __le32 opts1;
 664         __le32 opts2;
 665         __le64 addr;
 666 };
 667
 668 struct RxDesc {
 669         __le32 opts1;
 670         __le32 opts2;
 671         __le64 addr;
 672 };
 673
 674 struct ring_info {
 675         struct sk_buff  *skb;
 676         u32             len;
 677         u8              __pad[sizeof(void *) - sizeof(u32)];
 678 };
 679
 680 enum features {
 681         RTL_FEATURE_WOL         = (1 << 0),
 682         RTL_FEATURE_MSI         = (1 << 1),
 683         RTL_FEATURE_GMII        = (1 << 2),
 684 };
 685
 686 struct rtl8169_counters {
 687         __le64  tx_packets;
 688         __le64  rx_packets;
 689         __le64  tx_errors;
 690         __le32  rx_errors;
 691         __le16  rx_missed;
 692         __le16  align_errors;
 693         __le32  tx_one_collision;
 694         __le32  tx_multi_collision;
 695         __le64  rx_unicast;
 696         __le64  rx_broadcast;
 697         __le32  rx_multicast;
 698         __le16  tx_aborted;
 699         __le16  tx_underun;
 700 };
 701
 702 enum rtl_flag {
 703         RTL_FLAG_TASK_ENABLED,
 704         RTL_FLAG_TASK_SLOW_PENDING,
 705         RTL_FLAG_TASK_RESET_PENDING,
 706         RTL_FLAG_TASK_PHY_PENDING,
 707         RTL_FLAG_MAX
 708 };
 709
 710 struct rtl8169_stats {
 711         u64                     packets;
 712         u64                     bytes;
 713         struct u64_stats_sync   syncp;
 714 };
 715
 716 struct rtl8169_private {
 717         void __iomem *mmio_addr;        /* memory map physical address */
 718         struct pci_dev *pci_dev;
 719         struct net_device *dev;
 720         struct napi_struct napi;
 721         u32 msg_enable;
 722         u16 txd_version;
 723         u16 mac_version;
 724         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 725         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 726         u32 dirty_tx;
 727         struct rtl8169_stats rx_stats;
 728         struct rtl8169_stats tx_stats;
 729         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 730         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 731         dma_addr_t TxPhyAddr;
 732         dma_addr_t RxPhyAddr;
 733         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 734         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 735         struct timer_list timer;
 736         u16 cp_cmd;
 737
 738         u16 event_slow;
 739
 740         struct mdio_ops {
 741                 void (*write)(struct rtl8169_private *, int, int);
 742                 int (*read)(struct rtl8169_private *, int);
 743         } mdio_ops;
 744
 745         struct pll_power_ops {
 746                 void (*down)(struct rtl8169_private *);
 747                 void (*up)(struct rtl8169_private *);
 748         } pll_power_ops;
 749
 750         struct jumbo_ops {
 751                 void (*enable)(struct rtl8169_private *);
 752                 void (*disable)(struct rtl8169_private *);
 753         } jumbo_ops;
 754
 755         struct csi_ops {
 756                 void (*write)(struct rtl8169_private *, int, int);
 757                 u32 (*read)(struct rtl8169_private *, int);
 758         } csi_ops;
 759
 760         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 761         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 762         void (*phy_reset_enable)(struct rtl8169_private *tp);
 763         void (*hw_start)(struct net_device *);
 764         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 765         unsigned int (*link_ok)(void __iomem *);
 766         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 767
 768         struct {
 769                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 770                 struct mutex mutex;
 771                 struct work_struct work;
 772         } wk;
 773
 774         unsigned features;
 775
 776         struct mii_if_info mii;
 777         struct rtl8169_counters counters;
 778         u32 saved_wolopts;
 779         u32 opts1_mask;
 780
 781         struct rtl_fw {
 782                 const struct firmware *fw;
 783
 784 #define RTL_VER_SIZE            32
 785
 786                 char version[RTL_VER_SIZE];
 787
 788                 struct rtl_fw_phy_action {
 789                         __le32 *code;
 790                         size_t size;
 791                 } phy_action;
 792         } *rtl_fw;
 793 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 794
 795         u32 ocp_base;
 796 };
 797
 798 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 799 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 800 module_param(use_dac, int, 0);
 801 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 802 module_param_named(debug, debug.msg_enable, int, 0);
 803 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 804 MODULE_LICENSE("GPL");
 805 MODULE_VERSION(RTL8169_VERSION);
 806 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 807 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 808 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 809 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 810 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 811 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 812 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 813 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 814 MODULE_FIRMWARE(FIRMWARE_8402_1);
 815 MODULE_FIRMWARE(FIRMWARE_8411_1);
 816 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 817 MODULE_FIRMWARE(FIRMWARE_8168G_1);
 818
 819 static void rtl_lock_work(struct rtl8169_private *tp)
 820 {
 821         mutex_lock(&tp->wk.mutex);
 822 }
 823
 824 static void rtl_unlock_work(struct rtl8169_private *tp)
 825 {
 826         mutex_unlock(&tp->wk.mutex);
 827 }
 828
 829 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 830 {
 831         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 832                                            PCI_EXP_DEVCTL_READRQ, force);
 833 }
 834
 835 struct rtl_cond {
 836         bool (*check)(struct rtl8169_private *);
 837         const char *msg;
 838 };
 839
 840 static void rtl_udelay(unsigned int d)
 841 {
 842         udelay(d);
 843 }
 844
 845 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 846                           void (*delay)(unsigned int), unsigned int d, int n,
 847                           bool high)
 848 {
 849         int i;
 850
 851         for (i = 0; i < n; i++) {
 852                 delay(d);
 853                 if (c->check(tp) == high)
 854                         return true;
 855         }
 856         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 857                   c->msg, !high, n, d);
 858         return false;
 859 }
 860
 861 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 862                                       const struct rtl_cond *c,
 863                                       unsigned int d, int n)
 864 {
 865         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 866 }
 867
 868 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 869                                      const struct rtl_cond *c,
 870                                      unsigned int d, int n)
 871 {
 872         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 873 }
 874
 875 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 876                                       const struct rtl_cond *c,
 877                                       unsigned int d, int n)
 878 {
 879         return rtl_loop_wait(tp, c, msleep, d, n, true);
 880 }
 881
 882 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 883                                      const struct rtl_cond *c,
 884                                      unsigned int d, int n)
 885 {
 886         return rtl_loop_wait(tp, c, msleep, d, n, false);
 887 }
 888
 889 #define DECLARE_RTL_COND(name)                          \
 890 static bool name ## _check(struct rtl8169_private *);   \
 891                                                         \
 892 static const struct rtl_cond name = {                   \
 893         .check  = name ## _check,                       \
 894         .msg    = #name                                 \
 895 };                                                      \
 896                                                         \
 897 static bool name ## _check(struct rtl8169_private *tp)
 898
 899 DECLARE_RTL_COND(rtl_ocpar_cond)
 900 {
 901         void __iomem *ioaddr = tp->mmio_addr;
 902
 903         return RTL_R32(OCPAR) & OCPAR_FLAG;
 904 }
 905
 906 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 907 {
 908         void __iomem *ioaddr = tp->mmio_addr;
 909
 910         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 911
 912         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 913                 RTL_R32(OCPDR) : ~0;
 914 }
 915
 916 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 917 {
 918         void __iomem *ioaddr = tp->mmio_addr;
 919
 920         RTL_W32(OCPDR, data);
 921         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 924 }
 925
 926 DECLARE_RTL_COND(rtl_eriar_cond)
 927 {
 928         void __iomem *ioaddr = tp->mmio_addr;
 929
 930         return RTL_R32(ERIAR) & ERIAR_FLAG;
 931 }
 932
 933 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 934 {
 935         void __iomem *ioaddr = tp->mmio_addr;
 936
 937         RTL_W8(ERIDR, cmd);
 938         RTL_W32(ERIAR, 0x800010e8);
 939         msleep(2);
 940
 941         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 942                 return;
 943
 944         ocp_write(tp, 0x1, 0x30, 0x00000001);
 945 }
 946
 947 #define OOB_CMD_RESET           0x00
 948 #define OOB_CMD_DRIVER_START    0x05
 949 #define OOB_CMD_DRIVER_STOP     0x06
 950
 951 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 952 {
 953         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 954 }
 955
 956 DECLARE_RTL_COND(rtl_ocp_read_cond)
 957 {
 958         u16 reg;
 959
 960         reg = rtl8168_get_ocp_reg(tp);
 961
 962         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 963 }
 964
 965 static void rtl8168_driver_start(struct rtl8169_private *tp)
 966 {
 967         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 968
 969         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 970 }
 971
 972 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 973 {
 974         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 975
 976         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 977 }
 978
 979 static int r8168dp_check_dash(struct rtl8169_private *tp)
 980 {
 981         u16 reg = rtl8168_get_ocp_reg(tp);
 982
 983         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 984 }
 985
 986 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 987 {
 988         if (reg & 0xffff0001) {
 989                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 990                 return true;
 991         }
 992         return false;
 993 }
 994
 995 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 996 {
 997         void __iomem *ioaddr = tp->mmio_addr;
 998
 999         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1000 }
1001
1002 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1003 {
1004         void __iomem *ioaddr = tp->mmio_addr;
1005
1006         if (rtl_ocp_reg_failure(tp, reg))
1007                 return;
1008
1009         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1010
1011         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1012 }
1013
1014 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1015 {
1016         void __iomem *ioaddr = tp->mmio_addr;
1017
1018         if (rtl_ocp_reg_failure(tp, reg))
1019                 return 0;
1020
1021         RTL_W32(GPHY_OCP, reg << 15);
1022
1023         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1024                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1025 }
1026
1027 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1028 {
1029         void __iomem *ioaddr = tp->mmio_addr;
1030
1031         if (rtl_ocp_reg_failure(tp, reg))
1032                 return;
1033
1034         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1035 }
1036
1037 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1038 {
1039         void __iomem *ioaddr = tp->mmio_addr;
1040
1041         if (rtl_ocp_reg_failure(tp, reg))
1042                 return 0;
1043
1044         RTL_W32(OCPDR, reg << 15);
1045
1046         return RTL_R32(OCPDR);
1047 }
1048
1049 #define OCP_STD_PHY_BASE        0xa400
1050
1051 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1052 {
1053         if (reg == 0x1f) {
1054                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1055                 return;
1056         }
1057
1058         if (tp->ocp_base != OCP_STD_PHY_BASE)
1059                 reg -= 0x10;
1060
1061         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1062 }
1063
1064 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1065 {
1066         if (tp->ocp_base != OCP_STD_PHY_BASE)
1067                 reg -= 0x10;
1068
1069         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1070 }
1071
1072 DECLARE_RTL_COND(rtl_phyar_cond)
1073 {
1074         void __iomem *ioaddr = tp->mmio_addr;
1075
1076         return RTL_R32(PHYAR) & 0x80000000;
1077 }
1078
1079 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1080 {
1081         void __iomem *ioaddr = tp->mmio_addr;
1082
1083         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1084
1085         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1086         /*
1087          * According to hardware specs a 20us delay is required after write
1088          * complete indication, but before sending next command.
1089          */
1090         udelay(20);
1091 }
1092
1093 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1094 {
1095         void __iomem *ioaddr = tp->mmio_addr;
1096         int value;
1097
1098         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1099
1100         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1101                 RTL_R32(PHYAR) & 0xffff : ~0;
1102
1103         /*
1104          * According to hardware specs a 20us delay is required after read
1105          * complete indication, but before sending next command.
1106          */
1107         udelay(20);
1108
1109         return value;
1110 }
1111
1112 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1113 {
1114         void __iomem *ioaddr = tp->mmio_addr;
1115
1116         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1117         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1118         RTL_W32(EPHY_RXER_NUM, 0);
1119
1120         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1121 }
1122
1123 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1124 {
1125         r8168dp_1_mdio_access(tp, reg,
1126                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1127 }
1128
1129 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1130 {
1131         void __iomem *ioaddr = tp->mmio_addr;
1132
1133         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1134
1135         mdelay(1);
1136         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1137         RTL_W32(EPHY_RXER_NUM, 0);
1138
1139         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1140                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1141 }
1142
1143 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1144
1145 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1146 {
1147         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1148 }
1149
1150 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1151 {
1152         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1153 }
1154
1155 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1156 {
1157         void __iomem *ioaddr = tp->mmio_addr;
1158
1159         r8168dp_2_mdio_start(ioaddr);
1160
1161         r8169_mdio_write(tp, reg, value);
1162
1163         r8168dp_2_mdio_stop(ioaddr);
1164 }
1165
1166 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1167 {
1168         void __iomem *ioaddr = tp->mmio_addr;
1169         int value;
1170
1171         r8168dp_2_mdio_start(ioaddr);
1172
1173         value = r8169_mdio_read(tp, reg);
1174
1175         r8168dp_2_mdio_stop(ioaddr);
1176
1177         return value;
1178 }
1179
1180 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1181 {
1182         tp->mdio_ops.write(tp, location, val);
1183 }
1184
1185 static int rtl_readphy(struct rtl8169_private *tp, int location)
1186 {
1187         return tp->mdio_ops.read(tp, location);
1188 }
1189
1190 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1191 {
1192         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1193 }
1194
1195 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1196 {
1197         int val;
1198
1199         val = rtl_readphy(tp, reg_addr);
1200         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1201 }
1202
1203 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1204                            int val)
1205 {
1206         struct rtl8169_private *tp = netdev_priv(dev);
1207
1208         rtl_writephy(tp, location, val);
1209 }
1210
1211 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1212 {
1213         struct rtl8169_private *tp = netdev_priv(dev);
1214
1215         return rtl_readphy(tp, location);
1216 }
1217
1218 DECLARE_RTL_COND(rtl_ephyar_cond)
1219 {
1220         void __iomem *ioaddr = tp->mmio_addr;
1221
1222         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1223 }
1224
1225 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1226 {
1227         void __iomem *ioaddr = tp->mmio_addr;
1228
1229         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1230                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1231
1232         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1233
1234         udelay(10);
1235 }
1236
1237 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1238 {
1239         void __iomem *ioaddr = tp->mmio_addr;
1240
1241         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1242
1243         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1244                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1245 }
1246
1247 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1248                           u32 val, int type)
1249 {
1250         void __iomem *ioaddr = tp->mmio_addr;
1251
1252         BUG_ON((addr & 3) || (mask == 0));
1253         RTL_W32(ERIDR, val);
1254         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1255
1256         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1257 }
1258
1259 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1260 {
1261         void __iomem *ioaddr = tp->mmio_addr;
1262
1263         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1264
1265         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1266                 RTL_R32(ERIDR) : ~0;
1267 }
1268
1269 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1270                          u32 m, int type)
1271 {
1272         u32 val;
1273
1274         val = rtl_eri_read(tp, addr, type);
1275         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1276 }
1277
1278 struct exgmac_reg {
1279         u16 addr;
1280         u16 mask;
1281         u32 val;
1282 };
1283
1284 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1285                                    const struct exgmac_reg *r, int len)
1286 {
1287         while (len-- > 0) {
1288                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1289                 r++;
1290         }
1291 }
1292
1293 DECLARE_RTL_COND(rtl_efusear_cond)
1294 {
1295         void __iomem *ioaddr = tp->mmio_addr;
1296
1297         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1298 }
1299
1300 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1301 {
1302         void __iomem *ioaddr = tp->mmio_addr;
1303
1304         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1305
1306         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1307                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1308 }
1309
1310 static u16 rtl_get_events(struct rtl8169_private *tp)
1311 {
1312         void __iomem *ioaddr = tp->mmio_addr;
1313
1314         return RTL_R16(IntrStatus);
1315 }
1316
1317 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1318 {
1319         void __iomem *ioaddr = tp->mmio_addr;
1320
1321         RTL_W16(IntrStatus, bits);
1322         mmiowb();
1323 }
1324
1325 static void rtl_irq_disable(struct rtl8169_private *tp)
1326 {
1327         void __iomem *ioaddr = tp->mmio_addr;
1328
1329         RTL_W16(IntrMask, 0);
1330         mmiowb();
1331 }
1332
1333 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1334 {
1335         void __iomem *ioaddr = tp->mmio_addr;
1336
1337         RTL_W16(IntrMask, bits);
1338 }
1339
1340 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1341 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1342 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1343
1344 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1345 {
1346         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1347 }
1348
1349 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1350 {
1351         void __iomem *ioaddr = tp->mmio_addr;
1352
1353         rtl_irq_disable(tp);
1354         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1355         RTL_R8(ChipCmd);
1356 }
1357
1358 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1359 {
1360         void __iomem *ioaddr = tp->mmio_addr;
1361
1362         return RTL_R32(TBICSR) & TBIReset;
1363 }
1364
1365 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1366 {
1367         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1368 }
1369
1370 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1371 {
1372         return RTL_R32(TBICSR) & TBILinkOk;
1373 }
1374
1375 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1376 {
1377         return RTL_R8(PHYstatus) & LinkStatus;
1378 }
1379
1380 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1381 {
1382         void __iomem *ioaddr = tp->mmio_addr;
1383
1384         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1385 }
1386
1387 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1388 {
1389         unsigned int val;
1390
1391         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1392         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1393 }
1394
1395 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1396 {
1397         void __iomem *ioaddr = tp->mmio_addr;
1398         struct net_device *dev = tp->dev;
1399
1400         if (!netif_running(dev))
1401                 return;
1402
1403         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1404             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1405                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1406                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1407                                       ERIAR_EXGMAC);
1408                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1409                                       ERIAR_EXGMAC);
1410                 } else if (RTL_R8(PHYstatus) & _100bps) {
1411                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1412                                       ERIAR_EXGMAC);
1413                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1414                                       ERIAR_EXGMAC);
1415                 } else {
1416                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1417                                       ERIAR_EXGMAC);
1418                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1419                                       ERIAR_EXGMAC);
1420                 }
1421                 /* Reset packet filter */
1422                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1423                              ERIAR_EXGMAC);
1424                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1425                              ERIAR_EXGMAC);
1426         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1427                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1428                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1429                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1430                                       ERIAR_EXGMAC);
1431                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1432                                       ERIAR_EXGMAC);
1433                 } else {
1434                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1435                                       ERIAR_EXGMAC);
1436                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1437                                       ERIAR_EXGMAC);
1438                 }
1439         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1440                 if (RTL_R8(PHYstatus) & _10bps) {
1441                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1442                                       ERIAR_EXGMAC);
1443                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1444                                       ERIAR_EXGMAC);
1445                 } else {
1446                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1447                                       ERIAR_EXGMAC);
1448                 }
1449         }
1450 }
1451
1452 static void __rtl8169_check_link_status(struct net_device *dev,
1453                                         struct rtl8169_private *tp,
1454                                         void __iomem *ioaddr, bool pm)
1455 {
1456         if (tp->link_ok(ioaddr)) {
1457                 rtl_link_chg_patch(tp);
1458                 /* This is to cancel a scheduled suspend if there's one. */
1459                 if (pm)
1460                         pm_request_resume(&tp->pci_dev->dev);
1461                 netif_carrier_on(dev);
1462                 if (net_ratelimit())
1463                         netif_info(tp, ifup, dev, "link up\n");
1464         } else {
1465                 netif_carrier_off(dev);
1466                 netif_info(tp, ifdown, dev, "link down\n");
1467                 if (pm)
1468                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1469         }
1470 }
1471
1472 static void rtl8169_check_link_status(struct net_device *dev,
1473                                       struct rtl8169_private *tp,
1474                                       void __iomem *ioaddr)
1475 {
1476         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1477 }
1478
1479 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1480
1481 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1482 {
1483         void __iomem *ioaddr = tp->mmio_addr;
1484         u8 options;
1485         u32 wolopts = 0;
1486
1487         options = RTL_R8(Config1);
1488         if (!(options & PMEnable))
1489                 return 0;
1490
1491         options = RTL_R8(Config3);
1492         if (options & LinkUp)
1493                 wolopts |= WAKE_PHY;
1494         if (options & MagicPacket)
1495                 wolopts |= WAKE_MAGIC;
1496
1497         options = RTL_R8(Config5);
1498         if (options & UWF)
1499                 wolopts |= WAKE_UCAST;
1500         if (options & BWF)
1501                 wolopts |= WAKE_BCAST;
1502         if (options & MWF)
1503                 wolopts |= WAKE_MCAST;
1504
1505         return wolopts;
1506 }
1507
1508 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1509 {
1510         struct rtl8169_private *tp = netdev_priv(dev);
1511
1512         rtl_lock_work(tp);
1513
1514         wol->supported = WAKE_ANY;
1515         wol->wolopts = __rtl8169_get_wol(tp);
1516
1517         rtl_unlock_work(tp);
1518 }
1519
1520 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1521 {
1522         void __iomem *ioaddr = tp->mmio_addr;
1523         unsigned int i;
1524         static const struct {
1525                 u32 opt;
1526                 u16 reg;
1527                 u8  mask;
1528         } cfg[] = {
1529                 { WAKE_PHY,   Config3, LinkUp },
1530                 { WAKE_MAGIC, Config3, MagicPacket },
1531                 { WAKE_UCAST, Config5, UWF },
1532                 { WAKE_BCAST, Config5, BWF },
1533                 { WAKE_MCAST, Config5, MWF },
1534                 { WAKE_ANY,   Config5, LanWake }
1535         };
1536         u8 options;
1537
1538         RTL_W8(Cfg9346, Cfg9346_Unlock);
1539
1540         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1541                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1542                 if (wolopts & cfg[i].opt)
1543                         options |= cfg[i].mask;
1544                 RTL_W8(cfg[i].reg, options);
1545         }
1546
1547         switch (tp->mac_version) {
1548         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1549                 options = RTL_R8(Config1) & ~PMEnable;
1550                 if (wolopts)
1551                         options |= PMEnable;
1552                 RTL_W8(Config1, options);
1553                 break;
1554         default:
1555                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1556                 if (wolopts)
1557                         options |= PME_SIGNAL;
1558                 RTL_W8(Config2, options);
1559                 break;
1560         }
1561
1562         RTL_W8(Cfg9346, Cfg9346_Lock);
1563 }
1564
1565 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1566 {
1567         struct rtl8169_private *tp = netdev_priv(dev);
1568
1569         rtl_lock_work(tp);
1570
1571         if (wol->wolopts)
1572                 tp->features |= RTL_FEATURE_WOL;
1573         else
1574                 tp->features &= ~RTL_FEATURE_WOL;
1575         __rtl8169_set_wol(tp, wol->wolopts);
1576
1577         rtl_unlock_work(tp);
1578
1579         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1580
1581         return 0;
1582 }
1583
1584 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1585 {
1586         return rtl_chip_infos[tp->mac_version].fw_name;
1587 }
1588
1589 static void rtl8169_get_drvinfo(struct net_device *dev,
1590                                 struct ethtool_drvinfo *info)
1591 {
1592         struct rtl8169_private *tp = netdev_priv(dev);
1593         struct rtl_fw *rtl_fw = tp->rtl_fw;
1594
1595         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1596         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1597         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1598         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1599         if (!IS_ERR_OR_NULL(rtl_fw))
1600                 strlcpy(info->fw_version, rtl_fw->version,
1601                         sizeof(info->fw_version));
1602 }
1603
1604 static int rtl8169_get_regs_len(struct net_device *dev)
1605 {
1606         return R8169_REGS_SIZE;
1607 }
1608
1609 static int rtl8169_set_speed_tbi(struct net_device *dev,
1610                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1611 {
1612         struct rtl8169_private *tp = netdev_priv(dev);
1613         void __iomem *ioaddr = tp->mmio_addr;
1614         int ret = 0;
1615         u32 reg;
1616
1617         reg = RTL_R32(TBICSR);
1618         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1619             (duplex == DUPLEX_FULL)) {
1620                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1621         } else if (autoneg == AUTONEG_ENABLE)
1622                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1623         else {
1624                 netif_warn(tp, link, dev,
1625                            "incorrect speed setting refused in TBI mode\n");
1626                 ret = -EOPNOTSUPP;
1627         }
1628
1629         return ret;
1630 }
1631
1632 static int rtl8169_set_speed_xmii(struct net_device *dev,
1633                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1634 {
1635         struct rtl8169_private *tp = netdev_priv(dev);
1636         int giga_ctrl, bmcr;
1637         int rc = -EINVAL;
1638
1639         rtl_writephy(tp, 0x1f, 0x0000);
1640
1641         if (autoneg == AUTONEG_ENABLE) {
1642                 int auto_nego;
1643
1644                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1645                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1646                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1647
1648                 if (adv & ADVERTISED_10baseT_Half)
1649                         auto_nego |= ADVERTISE_10HALF;
1650                 if (adv & ADVERTISED_10baseT_Full)
1651                         auto_nego |= ADVERTISE_10FULL;
1652                 if (adv & ADVERTISED_100baseT_Half)
1653                         auto_nego |= ADVERTISE_100HALF;
1654                 if (adv & ADVERTISED_100baseT_Full)
1655                         auto_nego |= ADVERTISE_100FULL;
1656
1657                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1658
1659                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1660                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1661
1662                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1663                 if (tp->mii.supports_gmii) {
1664                         if (adv & ADVERTISED_1000baseT_Half)
1665                                 giga_ctrl |= ADVERTISE_1000HALF;
1666                         if (adv & ADVERTISED_1000baseT_Full)
1667                                 giga_ctrl |= ADVERTISE_1000FULL;
1668                 } else if (adv & (ADVERTISED_1000baseT_Half |
1669                                   ADVERTISED_1000baseT_Full)) {
1670                         netif_info(tp, link, dev,
1671                                    "PHY does not support 1000Mbps\n");
1672                         goto out;
1673                 }
1674
1675                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1676
1677                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1678                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1679         } else {
1680                 giga_ctrl = 0;
1681
1682                 if (speed == SPEED_10)
1683                         bmcr = 0;
1684                 else if (speed == SPEED_100)
1685                         bmcr = BMCR_SPEED100;
1686                 else
1687                         goto out;
1688
1689                 if (duplex == DUPLEX_FULL)
1690                         bmcr |= BMCR_FULLDPLX;
1691         }
1692
1693         rtl_writephy(tp, MII_BMCR, bmcr);
1694
1695         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1696             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1697                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1698                         rtl_writephy(tp, 0x17, 0x2138);
1699                         rtl_writephy(tp, 0x0e, 0x0260);
1700                 } else {
1701                         rtl_writephy(tp, 0x17, 0x2108);
1702                         rtl_writephy(tp, 0x0e, 0x0000);
1703                 }
1704         }
1705
1706         rc = 0;
1707 out:
1708         return rc;
1709 }
1710
1711 static int rtl8169_set_speed(struct net_device *dev,
1712                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1713 {
1714         struct rtl8169_private *tp = netdev_priv(dev);
1715         int ret;
1716
1717         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1718         if (ret < 0)
1719                 goto out;
1720
1721         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1722             (advertising & ADVERTISED_1000baseT_Full)) {
1723                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1724         }
1725 out:
1726         return ret;
1727 }
1728
1729 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1730 {
1731         struct rtl8169_private *tp = netdev_priv(dev);
1732         int ret;
1733
1734         del_timer_sync(&tp->timer);
1735
1736         rtl_lock_work(tp);
1737         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1738                                 cmd->duplex, cmd->advertising);
1739         rtl_unlock_work(tp);
1740
1741         return ret;
1742 }
1743
1744 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1745         netdev_features_t features)
1746 {
1747         struct rtl8169_private *tp = netdev_priv(dev);
1748
1749         if (dev->mtu > TD_MSS_MAX)
1750                 features &= ~NETIF_F_ALL_TSO;
1751
1752         if (dev->mtu > JUMBO_1K &&
1753             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1754                 features &= ~NETIF_F_IP_CSUM;
1755
1756         return features;
1757 }
1758
1759 static void __rtl8169_set_features(struct net_device *dev,
1760                                    netdev_features_t features)
1761 {
1762         struct rtl8169_private *tp = netdev_priv(dev);
1763         netdev_features_t changed = features ^ dev->features;
1764         void __iomem *ioaddr = tp->mmio_addr;
1765
1766         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1767                 return;
1768
1769         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1770                 if (features & NETIF_F_RXCSUM)
1771                         tp->cp_cmd |= RxChkSum;
1772                 else
1773                         tp->cp_cmd &= ~RxChkSum;
1774
1775                 if (dev->features & NETIF_F_HW_VLAN_RX)
1776                         tp->cp_cmd |= RxVlan;
1777                 else
1778                         tp->cp_cmd &= ~RxVlan;
1779
1780                 RTL_W16(CPlusCmd, tp->cp_cmd);
1781                 RTL_R16(CPlusCmd);
1782         }
1783         if (changed & NETIF_F_RXALL) {
1784                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1785                 if (features & NETIF_F_RXALL)
1786                         tmp |= (AcceptErr | AcceptRunt);
1787                 RTL_W32(RxConfig, tmp);
1788         }
1789 }
1790
1791 static int rtl8169_set_features(struct net_device *dev,
1792                                 netdev_features_t features)
1793 {
1794         struct rtl8169_private *tp = netdev_priv(dev);
1795
1796         rtl_lock_work(tp);
1797         __rtl8169_set_features(dev, features);
1798         rtl_unlock_work(tp);
1799
1800         return 0;
1801 }
1802
1803
1804 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1805 {
1806         return (vlan_tx_tag_present(skb)) ?
1807                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1808 }
1809
1810 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1811 {
1812         u32 opts2 = le32_to_cpu(desc->opts2);
1813
1814         if (opts2 & RxVlanTag)
1815                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1816 }
1817
1818 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1819 {
1820         struct rtl8169_private *tp = netdev_priv(dev);
1821         void __iomem *ioaddr = tp->mmio_addr;
1822         u32 status;
1823
1824         cmd->supported =
1825                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1826         cmd->port = PORT_FIBRE;
1827         cmd->transceiver = XCVR_INTERNAL;
1828
1829         status = RTL_R32(TBICSR);
1830         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1831         cmd->autoneg = !!(status & TBINwEnable);
1832
1833         ethtool_cmd_speed_set(cmd, SPEED_1000);
1834         cmd->duplex = DUPLEX_FULL; /* Always set */
1835
1836         return 0;
1837 }
1838
1839 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1840 {
1841         struct rtl8169_private *tp = netdev_priv(dev);
1842
1843         return mii_ethtool_gset(&tp->mii, cmd);
1844 }
1845
1846 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1847 {
1848         struct rtl8169_private *tp = netdev_priv(dev);
1849         int rc;
1850
1851         rtl_lock_work(tp);
1852         rc = tp->get_settings(dev, cmd);
1853         rtl_unlock_work(tp);
1854
1855         return rc;
1856 }
1857
1858 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1859                              void *p)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862
1863         if (regs->len > R8169_REGS_SIZE)
1864                 regs->len = R8169_REGS_SIZE;
1865
1866         rtl_lock_work(tp);
1867         memcpy_fromio(p, tp->mmio_addr, regs->len);
1868         rtl_unlock_work(tp);
1869 }
1870
1871 static u32 rtl8169_get_msglevel(struct net_device *dev)
1872 {
1873         struct rtl8169_private *tp = netdev_priv(dev);
1874
1875         return tp->msg_enable;
1876 }
1877
1878 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1879 {
1880         struct rtl8169_private *tp = netdev_priv(dev);
1881
1882         tp->msg_enable = value;
1883 }
1884
1885 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1886         "tx_packets",
1887         "rx_packets",
1888         "tx_errors",
1889         "rx_errors",
1890         "rx_missed",
1891         "align_errors",
1892         "tx_single_collisions",
1893         "tx_multi_collisions",
1894         "unicast",
1895         "broadcast",
1896         "multicast",
1897         "tx_aborted",
1898         "tx_underrun",
1899 };
1900
1901 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1902 {
1903         switch (sset) {
1904         case ETH_SS_STATS:
1905                 return ARRAY_SIZE(rtl8169_gstrings);
1906         default:
1907                 return -EOPNOTSUPP;
1908         }
1909 }
1910
1911 DECLARE_RTL_COND(rtl_counters_cond)
1912 {
1913         void __iomem *ioaddr = tp->mmio_addr;
1914
1915         return RTL_R32(CounterAddrLow) & CounterDump;
1916 }
1917
1918 static void rtl8169_update_counters(struct net_device *dev)
1919 {
1920         struct rtl8169_private *tp = netdev_priv(dev);
1921         void __iomem *ioaddr = tp->mmio_addr;
1922         struct device *d = &tp->pci_dev->dev;
1923         struct rtl8169_counters *counters;
1924         dma_addr_t paddr;
1925         u32 cmd;
1926
1927         /*
1928          * Some chips are unable to dump tally counters when the receiver
1929          * is disabled.
1930          */
1931         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1932                 return;
1933
1934         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1935         if (!counters)
1936                 return;
1937
1938         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1939         cmd = (u64)paddr & DMA_BIT_MASK(32);
1940         RTL_W32(CounterAddrLow, cmd);
1941         RTL_W32(CounterAddrLow, cmd | CounterDump);
1942
1943         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1944                 memcpy(&tp->counters, counters, sizeof(*counters));
1945
1946         RTL_W32(CounterAddrLow, 0);
1947         RTL_W32(CounterAddrHigh, 0);
1948
1949         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1950 }
1951
1952 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1953                                       struct ethtool_stats *stats, u64 *data)
1954 {
1955         struct rtl8169_private *tp = netdev_priv(dev);
1956
1957         ASSERT_RTNL();
1958
1959         rtl8169_update_counters(dev);
1960
1961         data[0] = le64_to_cpu(tp->counters.tx_packets);
1962         data[1] = le64_to_cpu(tp->counters.rx_packets);
1963         data[2] = le64_to_cpu(tp->counters.tx_errors);
1964         data[3] = le32_to_cpu(tp->counters.rx_errors);
1965         data[4] = le16_to_cpu(tp->counters.rx_missed);
1966         data[5] = le16_to_cpu(tp->counters.align_errors);
1967         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1968         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1969         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1970         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1971         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1972         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1973         data[12] = le16_to_cpu(tp->counters.tx_underun);
1974 }
1975
1976 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1977 {
1978         switch(stringset) {
1979         case ETH_SS_STATS:
1980                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1981                 break;
1982         }
1983 }
1984
1985 static const struct ethtool_ops rtl8169_ethtool_ops = {
1986         .get_drvinfo            = rtl8169_get_drvinfo,
1987         .get_regs_len           = rtl8169_get_regs_len,
1988         .get_link               = ethtool_op_get_link,
1989         .get_settings           = rtl8169_get_settings,
1990         .set_settings           = rtl8169_set_settings,
1991         .get_msglevel           = rtl8169_get_msglevel,
1992         .set_msglevel           = rtl8169_set_msglevel,
1993         .get_regs               = rtl8169_get_regs,
1994         .get_wol                = rtl8169_get_wol,
1995         .set_wol                = rtl8169_set_wol,
1996         .get_strings            = rtl8169_get_strings,
1997         .get_sset_count         = rtl8169_get_sset_count,
1998         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1999         .get_ts_info            = ethtool_op_get_ts_info,
2000 };
2001
2002 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2003                                     struct net_device *dev, u8 default_version)
2004 {
2005         void __iomem *ioaddr = tp->mmio_addr;
2006         /*
2007          * The driver currently handles the 8168Bf and the 8168Be identically
2008          * but they can be identified more specifically through the test below
2009          * if needed:
2010          *
2011          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2012          *
2013          * Same thing for the 8101Eb and the 8101Ec:
2014          *
2015          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2016          */
2017         static const struct rtl_mac_info {
2018                 u32 mask;
2019                 u32 val;
2020                 int mac_version;
2021         } mac_info[] = {
2022                 /* 8168G family. */
2023                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2024                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2025
2026                 /* 8168F family. */
2027                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2028                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2029                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2030
2031                 /* 8168E family. */
2032                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2033                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2034                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2035                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2036
2037                 /* 8168D family. */
2038                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2039                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2040                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2041
2042                 /* 8168DP family. */
2043                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2044                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2045                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2046
2047                 /* 8168C family. */
2048                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2049                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2050                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2051                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2052                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2053                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2054                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2055                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2056                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2057
2058                 /* 8168B family. */
2059                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2060                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2061                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2062                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2063
2064                 /* 8101 family. */
2065                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2066                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2067                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2068                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2069                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2070                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2071                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2072                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2073                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2074                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2075                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2076                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2077                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2078                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2079                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2080                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2081                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2082                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2083                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2084                 /* FIXME: where did these entries come from ? -- FR */
2085                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2086                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2087
2088                 /* 8110 family. */
2089                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2090                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2091                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2092                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2093                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2094                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2095
2096                 /* Catch-all */
2097                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2098         };
2099         const struct rtl_mac_info *p = mac_info;
2100         u32 reg;
2101
2102         reg = RTL_R32(TxConfig);
2103         while ((reg & p->mask) != p->val)
2104                 p++;
2105         tp->mac_version = p->mac_version;
2106
2107         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2108                 netif_notice(tp, probe, dev,
2109                              "unknown MAC, using family default\n");
2110                 tp->mac_version = default_version;
2111         }
2112 }
2113
2114 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2115 {
2116         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2117 }
2118
2119 struct phy_reg {
2120         u16 reg;
2121         u16 val;
2122 };
2123
2124 static void rtl_writephy_batch(struct rtl8169_private *tp,
2125                                const struct phy_reg *regs, int len)
2126 {
2127         while (len-- > 0) {
2128                 rtl_writephy(tp, regs->reg, regs->val);
2129                 regs++;
2130         }
2131 }
2132
2133 #define PHY_READ                0x00000000
2134 #define PHY_DATA_OR             0x10000000
2135 #define PHY_DATA_AND            0x20000000
2136 #define PHY_BJMPN               0x30000000
2137 #define PHY_READ_EFUSE          0x40000000
2138 #define PHY_READ_MAC_BYTE       0x50000000
2139 #define PHY_WRITE_MAC_BYTE      0x60000000
2140 #define PHY_CLEAR_READCOUNT     0x70000000
2141 #define PHY_WRITE               0x80000000
2142 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2143 #define PHY_COMP_EQ_SKIPN       0xa0000000
2144 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2145 #define PHY_WRITE_PREVIOUS      0xc0000000
2146 #define PHY_SKIPN               0xd0000000
2147 #define PHY_DELAY_MS            0xe0000000
2148 #define PHY_WRITE_ERI_WORD      0xf0000000
2149
2150 struct fw_info {
2151         u32     magic;
2152         char    version[RTL_VER_SIZE];
2153         __le32  fw_start;
2154         __le32  fw_len;
2155         u8      chksum;
2156 } __packed;
2157
2158 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2159
2160 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2161 {
2162         const struct firmware *fw = rtl_fw->fw;
2163         struct fw_info *fw_info = (struct fw_info *)fw->data;
2164         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2165         char *version = rtl_fw->version;
2166         bool rc = false;
2167
2168         if (fw->size < FW_OPCODE_SIZE)
2169                 goto out;
2170
2171         if (!fw_info->magic) {
2172                 size_t i, size, start;
2173                 u8 checksum = 0;
2174
2175                 if (fw->size < sizeof(*fw_info))
2176                         goto out;
2177
2178                 for (i = 0; i < fw->size; i++)
2179                         checksum += fw->data[i];
2180                 if (checksum != 0)
2181                         goto out;
2182
2183                 start = le32_to_cpu(fw_info->fw_start);
2184                 if (start > fw->size)
2185                         goto out;
2186
2187                 size = le32_to_cpu(fw_info->fw_len);
2188                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2189                         goto out;
2190
2191                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2192
2193                 pa->code = (__le32 *)(fw->data + start);
2194                 pa->size = size;
2195         } else {
2196                 if (fw->size % FW_OPCODE_SIZE)
2197                         goto out;
2198
2199                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2200
2201                 pa->code = (__le32 *)fw->data;
2202                 pa->size = fw->size / FW_OPCODE_SIZE;
2203         }
2204         version[RTL_VER_SIZE - 1] = 0;
2205
2206         rc = true;
2207 out:
2208         return rc;
2209 }
2210
2211 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2212                            struct rtl_fw_phy_action *pa)
2213 {
2214         bool rc = false;
2215         size_t index;
2216
2217         for (index = 0; index < pa->size; index++) {
2218                 u32 action = le32_to_cpu(pa->code[index]);
2219                 u32 regno = (action & 0x0fff0000) >> 16;
2220
2221                 switch(action & 0xf0000000) {
2222                 case PHY_READ:
2223                 case PHY_DATA_OR:
2224                 case PHY_DATA_AND:
2225                 case PHY_READ_EFUSE:
2226                 case PHY_CLEAR_READCOUNT:
2227                 case PHY_WRITE:
2228                 case PHY_WRITE_PREVIOUS:
2229                 case PHY_DELAY_MS:
2230                         break;
2231
2232                 case PHY_BJMPN:
2233                         if (regno > index) {
2234                                 netif_err(tp, ifup, tp->dev,
2235                                           "Out of range of firmware\n");
2236                                 goto out;
2237                         }
2238                         break;
2239                 case PHY_READCOUNT_EQ_SKIP:
2240                         if (index + 2 >= pa->size) {
2241                                 netif_err(tp, ifup, tp->dev,
2242                                           "Out of range of firmware\n");
2243                                 goto out;
2244                         }
2245                         break;
2246                 case PHY_COMP_EQ_SKIPN:
2247                 case PHY_COMP_NEQ_SKIPN:
2248                 case PHY_SKIPN:
2249                         if (index + 1 + regno >= pa->size) {
2250                                 netif_err(tp, ifup, tp->dev,
2251                                           "Out of range of firmware\n");
2252                                 goto out;
2253                         }
2254                         break;
2255
2256                 case PHY_READ_MAC_BYTE:
2257                 case PHY_WRITE_MAC_BYTE:
2258                 case PHY_WRITE_ERI_WORD:
2259                 default:
2260                         netif_err(tp, ifup, tp->dev,
2261                                   "Invalid action 0x%08x\n", action);
2262                         goto out;
2263                 }
2264         }
2265         rc = true;
2266 out:
2267         return rc;
2268 }
2269
2270 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2271 {
2272         struct net_device *dev = tp->dev;
2273         int rc = -EINVAL;
2274
2275         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2276                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2277                 goto out;
2278         }
2279
2280         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2281                 rc = 0;
2282 out:
2283         return rc;
2284 }
2285
2286 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2287 {
2288         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2289         u32 predata, count;
2290         size_t index;
2291
2292         predata = count = 0;
2293
2294         for (index = 0; index < pa->size; ) {
2295                 u32 action = le32_to_cpu(pa->code[index]);
2296                 u32 data = action & 0x0000ffff;
2297                 u32 regno = (action & 0x0fff0000) >> 16;
2298
2299                 if (!action)
2300                         break;
2301
2302                 switch(action & 0xf0000000) {
2303                 case PHY_READ:
2304                         predata = rtl_readphy(tp, regno);
2305                         count++;
2306                         index++;
2307                         break;
2308                 case PHY_DATA_OR:
2309                         predata |= data;
2310                         index++;
2311                         break;
2312                 case PHY_DATA_AND:
2313                         predata &= data;
2314                         index++;
2315                         break;
2316                 case PHY_BJMPN:
2317                         index -= regno;
2318                         break;
2319                 case PHY_READ_EFUSE:
2320                         predata = rtl8168d_efuse_read(tp, regno);
2321                         index++;
2322                         break;
2323                 case PHY_CLEAR_READCOUNT:
2324                         count = 0;
2325                         index++;
2326                         break;
2327                 case PHY_WRITE:
2328                         rtl_writephy(tp, regno, data);
2329                         index++;
2330                         break;
2331                 case PHY_READCOUNT_EQ_SKIP:
2332                         index += (count == data) ? 2 : 1;
2333                         break;
2334                 case PHY_COMP_EQ_SKIPN:
2335                         if (predata == data)
2336                                 index += regno;
2337                         index++;
2338                         break;
2339                 case PHY_COMP_NEQ_SKIPN:
2340                         if (predata != data)
2341                                 index += regno;
2342                         index++;
2343                         break;
2344                 case PHY_WRITE_PREVIOUS:
2345                         rtl_writephy(tp, regno, predata);
2346                         index++;
2347                         break;
2348                 case PHY_SKIPN:
2349                         index += regno + 1;
2350                         break;
2351                 case PHY_DELAY_MS:
2352                         mdelay(data);
2353                         index++;
2354                         break;
2355
2356                 case PHY_READ_MAC_BYTE:
2357                 case PHY_WRITE_MAC_BYTE:
2358                 case PHY_WRITE_ERI_WORD:
2359                 default:
2360                         BUG();
2361                 }
2362         }
2363 }
2364
2365 static void rtl_release_firmware(struct rtl8169_private *tp)
2366 {
2367         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2368                 release_firmware(tp->rtl_fw->fw);
2369                 kfree(tp->rtl_fw);
2370         }
2371         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2372 }
2373
2374 static void rtl_apply_firmware(struct rtl8169_private *tp)
2375 {
2376         struct rtl_fw *rtl_fw = tp->rtl_fw;
2377
2378         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2379         if (!IS_ERR_OR_NULL(rtl_fw))
2380                 rtl_phy_write_fw(tp, rtl_fw);
2381 }
2382
2383 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2384 {
2385         if (rtl_readphy(tp, reg) != val)
2386                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2387         else
2388                 rtl_apply_firmware(tp);
2389 }
2390
2391 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2392 {
2393         static const struct phy_reg phy_reg_init[] = {
2394                 { 0x1f, 0x0001 },
2395                 { 0x06, 0x006e },
2396                 { 0x08, 0x0708 },
2397                 { 0x15, 0x4000 },
2398                 { 0x18, 0x65c7 },
2399
2400                 { 0x1f, 0x0001 },
2401                 { 0x03, 0x00a1 },
2402                 { 0x02, 0x0008 },
2403                 { 0x01, 0x0120 },
2404                 { 0x00, 0x1000 },
2405                 { 0x04, 0x0800 },
2406                 { 0x04, 0x0000 },
2407
2408                 { 0x03, 0xff41 },
2409                 { 0x02, 0xdf60 },
2410                 { 0x01, 0x0140 },
2411                 { 0x00, 0x0077 },
2412                 { 0x04, 0x7800 },
2413                 { 0x04, 0x7000 },
2414
2415                 { 0x03, 0x802f },
2416                 { 0x02, 0x4f02 },
2417                 { 0x01, 0x0409 },
2418                 { 0x00, 0xf0f9 },
2419                 { 0x04, 0x9800 },
2420                 { 0x04, 0x9000 },
2421
2422                 { 0x03, 0xdf01 },
2423                 { 0x02, 0xdf20 },
2424                 { 0x01, 0xff95 },
2425                 { 0x00, 0xba00 },
2426                 { 0x04, 0xa800 },
2427                 { 0x04, 0xa000 },
2428
2429                 { 0x03, 0xff41 },
2430                 { 0x02, 0xdf20 },
2431                 { 0x01, 0x0140 },
2432                 { 0x00, 0x00bb },
2433                 { 0x04, 0xb800 },
2434                 { 0x04, 0xb000 },
2435
2436                 { 0x03, 0xdf41 },
2437                 { 0x02, 0xdc60 },
2438                 { 0x01, 0x6340 },
2439                 { 0x00, 0x007d },
2440                 { 0x04, 0xd800 },
2441                 { 0x04, 0xd000 },
2442
2443                 { 0x03, 0xdf01 },
2444                 { 0x02, 0xdf20 },
2445                 { 0x01, 0x100a },
2446                 { 0x00, 0xa0ff },
2447                 { 0x04, 0xf800 },
2448                 { 0x04, 0xf000 },
2449
2450                 { 0x1f, 0x0000 },
2451                 { 0x0b, 0x0000 },
2452                 { 0x00, 0x9200 }
2453         };
2454
2455         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2456 }
2457
2458 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2459 {
2460         static const struct phy_reg phy_reg_init[] = {
2461                 { 0x1f, 0x0002 },
2462                 { 0x01, 0x90d0 },
2463                 { 0x1f, 0x0000 }
2464         };
2465
2466         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2467 }
2468
2469 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2470 {
2471         struct pci_dev *pdev = tp->pci_dev;
2472
2473         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2474             (pdev->subsystem_device != 0xe000))
2475                 return;
2476
2477         rtl_writephy(tp, 0x1f, 0x0001);
2478         rtl_writephy(tp, 0x10, 0xf01b);
2479         rtl_writephy(tp, 0x1f, 0x0000);
2480 }
2481
2482 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2483 {
2484         static const struct phy_reg phy_reg_init[] = {
2485                 { 0x1f, 0x0001 },
2486                 { 0x04, 0x0000 },
2487                 { 0x03, 0x00a1 },
2488                 { 0x02, 0x0008 },
2489                 { 0x01, 0x0120 },
2490                 { 0x00, 0x1000 },
2491                 { 0x04, 0x0800 },
2492                 { 0x04, 0x9000 },
2493                 { 0x03, 0x802f },
2494                 { 0x02, 0x4f02 },
2495                 { 0x01, 0x0409 },
2496                 { 0x00, 0xf099 },
2497                 { 0x04, 0x9800 },
2498                 { 0x04, 0xa000 },
2499                 { 0x03, 0xdf01 },
2500                 { 0x02, 0xdf20 },
2501                 { 0x01, 0xff95 },
2502                 { 0x00, 0xba00 },
2503                 { 0x04, 0xa800 },
2504                 { 0x04, 0xf000 },
2505                 { 0x03, 0xdf01 },
2506                 { 0x02, 0xdf20 },
2507                 { 0x01, 0x101a },
2508                 { 0x00, 0xa0ff },
2509                 { 0x04, 0xf800 },
2510                 { 0x04, 0x0000 },
2511                 { 0x1f, 0x0000 },
2512
2513                 { 0x1f, 0x0001 },
2514                 { 0x10, 0xf41b },
2515                 { 0x14, 0xfb54 },
2516                 { 0x18, 0xf5c7 },
2517                 { 0x1f, 0x0000 },
2518
2519                 { 0x1f, 0x0001 },
2520                 { 0x17, 0x0cc0 },
2521                 { 0x1f, 0x0000 }
2522         };
2523
2524         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525
2526         rtl8169scd_hw_phy_config_quirk(tp);
2527 }
2528
2529 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2530 {
2531         static const struct phy_reg phy_reg_init[] = {
2532                 { 0x1f, 0x0001 },
2533                 { 0x04, 0x0000 },
2534                 { 0x03, 0x00a1 },
2535                 { 0x02, 0x0008 },
2536                 { 0x01, 0x0120 },
2537                 { 0x00, 0x1000 },
2538                 { 0x04, 0x0800 },
2539                 { 0x04, 0x9000 },
2540                 { 0x03, 0x802f },
2541                 { 0x02, 0x4f02 },
2542                 { 0x01, 0x0409 },
2543                 { 0x00, 0xf099 },
2544                 { 0x04, 0x9800 },
2545                 { 0x04, 0xa000 },
2546                 { 0x03, 0xdf01 },
2547                 { 0x02, 0xdf20 },
2548                 { 0x01, 0xff95 },
2549                 { 0x00, 0xba00 },
2550                 { 0x04, 0xa800 },
2551                 { 0x04, 0xf000 },
2552                 { 0x03, 0xdf01 },
2553                 { 0x02, 0xdf20 },
2554                 { 0x01, 0x101a },
2555                 { 0x00, 0xa0ff },
2556                 { 0x04, 0xf800 },
2557                 { 0x04, 0x0000 },
2558                 { 0x1f, 0x0000 },
2559
2560                 { 0x1f, 0x0001 },
2561                 { 0x0b, 0x8480 },
2562                 { 0x1f, 0x0000 },
2563
2564                 { 0x1f, 0x0001 },
2565                 { 0x18, 0x67c7 },
2566                 { 0x04, 0x2000 },
2567                 { 0x03, 0x002f },
2568                 { 0x02, 0x4360 },
2569                 { 0x01, 0x0109 },
2570                 { 0x00, 0x3022 },
2571                 { 0x04, 0x2800 },
2572                 { 0x1f, 0x0000 },
2573
2574                 { 0x1f, 0x0001 },
2575                 { 0x17, 0x0cc0 },
2576                 { 0x1f, 0x0000 }
2577         };
2578
2579         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2580 }
2581
2582 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2583 {
2584         static const struct phy_reg phy_reg_init[] = {
2585                 { 0x10, 0xf41b },
2586                 { 0x1f, 0x0000 }
2587         };
2588
2589         rtl_writephy(tp, 0x1f, 0x0001);
2590         rtl_patchphy(tp, 0x16, 1 << 0);
2591
2592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 }
2594
2595 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2596 {
2597         static const struct phy_reg phy_reg_init[] = {
2598                 { 0x1f, 0x0001 },
2599                 { 0x10, 0xf41b },
2600                 { 0x1f, 0x0000 }
2601         };
2602
2603         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2604 }
2605
2606 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2607 {
2608         static const struct phy_reg phy_reg_init[] = {
2609                 { 0x1f, 0x0000 },
2610                 { 0x1d, 0x0f00 },
2611                 { 0x1f, 0x0002 },
2612                 { 0x0c, 0x1ec8 },
2613                 { 0x1f, 0x0000 }
2614         };
2615
2616         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2617 }
2618
2619 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2620 {
2621         static const struct phy_reg phy_reg_init[] = {
2622                 { 0x1f, 0x0001 },
2623                 { 0x1d, 0x3d98 },
2624                 { 0x1f, 0x0000 }
2625         };
2626
2627         rtl_writephy(tp, 0x1f, 0x0000);
2628         rtl_patchphy(tp, 0x14, 1 << 5);
2629         rtl_patchphy(tp, 0x0d, 1 << 5);
2630
2631         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2632 }
2633
2634 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2635 {
2636         static const struct phy_reg phy_reg_init[] = {
2637                 { 0x1f, 0x0001 },
2638                 { 0x12, 0x2300 },
2639                 { 0x1f, 0x0002 },
2640                 { 0x00, 0x88d4 },
2641                 { 0x01, 0x82b1 },
2642                 { 0x03, 0x7002 },
2643                 { 0x08, 0x9e30 },
2644                 { 0x09, 0x01f0 },
2645                 { 0x0a, 0x5500 },
2646                 { 0x0c, 0x00c8 },
2647                 { 0x1f, 0x0003 },
2648                 { 0x12, 0xc096 },
2649                 { 0x16, 0x000a },
2650                 { 0x1f, 0x0000 },
2651                 { 0x1f, 0x0000 },
2652                 { 0x09, 0x2000 },
2653                 { 0x09, 0x0000 }
2654         };
2655
2656         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657
2658         rtl_patchphy(tp, 0x14, 1 << 5);
2659         rtl_patchphy(tp, 0x0d, 1 << 5);
2660         rtl_writephy(tp, 0x1f, 0x0000);
2661 }
2662
2663 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2664 {
2665         static const struct phy_reg phy_reg_init[] = {
2666                 { 0x1f, 0x0001 },
2667                 { 0x12, 0x2300 },
2668                 { 0x03, 0x802f },
2669                 { 0x02, 0x4f02 },
2670                 { 0x01, 0x0409 },
2671                 { 0x00, 0xf099 },
2672                 { 0x04, 0x9800 },
2673                 { 0x04, 0x9000 },
2674                 { 0x1d, 0x3d98 },
2675                 { 0x1f, 0x0002 },
2676                 { 0x0c, 0x7eb8 },
2677                 { 0x06, 0x0761 },
2678                 { 0x1f, 0x0003 },
2679                 { 0x16, 0x0f0a },
2680                 { 0x1f, 0x0000 }
2681         };
2682
2683         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2684
2685         rtl_patchphy(tp, 0x16, 1 << 0);
2686         rtl_patchphy(tp, 0x14, 1 << 5);
2687         rtl_patchphy(tp, 0x0d, 1 << 5);
2688         rtl_writephy(tp, 0x1f, 0x0000);
2689 }
2690
2691 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2692 {
2693         static const struct phy_reg phy_reg_init[] = {
2694                 { 0x1f, 0x0001 },
2695                 { 0x12, 0x2300 },
2696                 { 0x1d, 0x3d98 },
2697                 { 0x1f, 0x0002 },
2698                 { 0x0c, 0x7eb8 },
2699                 { 0x06, 0x5461 },
2700                 { 0x1f, 0x0003 },
2701                 { 0x16, 0x0f0a },
2702                 { 0x1f, 0x0000 }
2703         };
2704
2705         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2706
2707         rtl_patchphy(tp, 0x16, 1 << 0);
2708         rtl_patchphy(tp, 0x14, 1 << 5);
2709         rtl_patchphy(tp, 0x0d, 1 << 5);
2710         rtl_writephy(tp, 0x1f, 0x0000);
2711 }
2712
2713 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2714 {
2715         rtl8168c_3_hw_phy_config(tp);
2716 }
2717
2718 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init_0[] = {
2721                 /* Channel Estimation */
2722                 { 0x1f, 0x0001 },
2723                 { 0x06, 0x4064 },
2724                 { 0x07, 0x2863 },
2725                 { 0x08, 0x059c },
2726                 { 0x09, 0x26b4 },
2727                 { 0x0a, 0x6a19 },
2728                 { 0x0b, 0xdcc8 },
2729                 { 0x10, 0xf06d },
2730                 { 0x14, 0x7f68 },
2731                 { 0x18, 0x7fd9 },
2732                 { 0x1c, 0xf0ff },
2733                 { 0x1d, 0x3d9c },
2734                 { 0x1f, 0x0003 },
2735                 { 0x12, 0xf49f },
2736                 { 0x13, 0x070b },
2737                 { 0x1a, 0x05ad },
2738                 { 0x14, 0x94c0 },
2739
2740                 /*
2741                  * Tx Error Issue
2742                  * Enhance line driver power
2743                  */
2744                 { 0x1f, 0x0002 },
2745                 { 0x06, 0x5561 },
2746                 { 0x1f, 0x0005 },
2747                 { 0x05, 0x8332 },
2748                 { 0x06, 0x5561 },
2749
2750                 /*
2751                  * Can not link to 1Gbps with bad cable
2752                  * Decrease SNR threshold form 21.07dB to 19.04dB
2753                  */
2754                 { 0x1f, 0x0001 },
2755                 { 0x17, 0x0cc0 },
2756
2757                 { 0x1f, 0x0000 },
2758                 { 0x0d, 0xf880 }
2759         };
2760
2761         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2762
2763         /*
2764          * Rx Error Issue
2765          * Fine Tune Switching regulator parameter
2766          */
2767         rtl_writephy(tp, 0x1f, 0x0002);
2768         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2769         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2770
2771         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2772                 static const struct phy_reg phy_reg_init[] = {
2773                         { 0x1f, 0x0002 },
2774                         { 0x05, 0x669a },
2775                         { 0x1f, 0x0005 },
2776                         { 0x05, 0x8330 },
2777                         { 0x06, 0x669a },
2778                         { 0x1f, 0x0002 }
2779                 };
2780                 int val;
2781
2782                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2783
2784                 val = rtl_readphy(tp, 0x0d);
2785
2786                 if ((val & 0x00ff) != 0x006c) {
2787                         static const u32 set[] = {
2788                                 0x0065, 0x0066, 0x0067, 0x0068,
2789                                 0x0069, 0x006a, 0x006b, 0x006c
2790                         };
2791                         int i;
2792
2793                         rtl_writephy(tp, 0x1f, 0x0002);
2794
2795                         val &= 0xff00;
2796                         for (i = 0; i < ARRAY_SIZE(set); i++)
2797                                 rtl_writephy(tp, 0x0d, val | set[i]);
2798                 }
2799         } else {
2800                 static const struct phy_reg phy_reg_init[] = {
2801                         { 0x1f, 0x0002 },
2802                         { 0x05, 0x6662 },
2803                         { 0x1f, 0x0005 },
2804                         { 0x05, 0x8330 },
2805                         { 0x06, 0x6662 }
2806                 };
2807
2808                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2809         }
2810
2811         /* RSET couple improve */
2812         rtl_writephy(tp, 0x1f, 0x0002);
2813         rtl_patchphy(tp, 0x0d, 0x0300);
2814         rtl_patchphy(tp, 0x0f, 0x0010);
2815
2816         /* Fine tune PLL performance */
2817         rtl_writephy(tp, 0x1f, 0x0002);
2818         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2819         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2820
2821         rtl_writephy(tp, 0x1f, 0x0005);
2822         rtl_writephy(tp, 0x05, 0x001b);
2823
2824         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2825
2826         rtl_writephy(tp, 0x1f, 0x0000);
2827 }
2828
2829 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2830 {
2831         static const struct phy_reg phy_reg_init_0[] = {
2832                 /* Channel Estimation */
2833                 { 0x1f, 0x0001 },
2834                 { 0x06, 0x4064 },
2835                 { 0x07, 0x2863 },
2836                 { 0x08, 0x059c },
2837                 { 0x09, 0x26b4 },
2838                 { 0x0a, 0x6a19 },
2839                 { 0x0b, 0xdcc8 },
2840                 { 0x10, 0xf06d },
2841                 { 0x14, 0x7f68 },
2842                 { 0x18, 0x7fd9 },
2843                 { 0x1c, 0xf0ff },
2844                 { 0x1d, 0x3d9c },
2845                 { 0x1f, 0x0003 },
2846                 { 0x12, 0xf49f },
2847                 { 0x13, 0x070b },
2848                 { 0x1a, 0x05ad },
2849                 { 0x14, 0x94c0 },
2850
2851                 /*
2852                  * Tx Error Issue
2853                  * Enhance line driver power
2854                  */
2855                 { 0x1f, 0x0002 },
2856                 { 0x06, 0x5561 },
2857                 { 0x1f, 0x0005 },
2858                 { 0x05, 0x8332 },
2859                 { 0x06, 0x5561 },
2860
2861                 /*
2862                  * Can not link to 1Gbps with bad cable
2863                  * Decrease SNR threshold form 21.07dB to 19.04dB
2864                  */
2865                 { 0x1f, 0x0001 },
2866                 { 0x17, 0x0cc0 },
2867
2868                 { 0x1f, 0x0000 },
2869                 { 0x0d, 0xf880 }
2870         };
2871
2872         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2873
2874         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2875                 static const struct phy_reg phy_reg_init[] = {
2876                         { 0x1f, 0x0002 },
2877                         { 0x05, 0x669a },
2878                         { 0x1f, 0x0005 },
2879                         { 0x05, 0x8330 },
2880                         { 0x06, 0x669a },
2881
2882                         { 0x1f, 0x0002 }
2883                 };
2884                 int val;
2885
2886                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2887
2888                 val = rtl_readphy(tp, 0x0d);
2889                 if ((val & 0x00ff) != 0x006c) {
2890                         static const u32 set[] = {
2891                                 0x0065, 0x0066, 0x0067, 0x0068,
2892                                 0x0069, 0x006a, 0x006b, 0x006c
2893                         };
2894                         int i;
2895
2896                         rtl_writephy(tp, 0x1f, 0x0002);
2897
2898                         val &= 0xff00;
2899                         for (i = 0; i < ARRAY_SIZE(set); i++)
2900                                 rtl_writephy(tp, 0x0d, val | set[i]);
2901                 }
2902         } else {
2903                 static const struct phy_reg phy_reg_init[] = {
2904                         { 0x1f, 0x0002 },
2905                         { 0x05, 0x2642 },
2906                         { 0x1f, 0x0005 },
2907                         { 0x05, 0x8330 },
2908                         { 0x06, 0x2642 }
2909                 };
2910
2911                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2912         }
2913
2914         /* Fine tune PLL performance */
2915         rtl_writephy(tp, 0x1f, 0x0002);
2916         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2917         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2918
2919         /* Switching regulator Slew rate */
2920         rtl_writephy(tp, 0x1f, 0x0002);
2921         rtl_patchphy(tp, 0x0f, 0x0017);
2922
2923         rtl_writephy(tp, 0x1f, 0x0005);
2924         rtl_writephy(tp, 0x05, 0x001b);
2925
2926         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2927
2928         rtl_writephy(tp, 0x1f, 0x0000);
2929 }
2930
2931 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2932 {
2933         static const struct phy_reg phy_reg_init[] = {
2934                 { 0x1f, 0x0002 },
2935                 { 0x10, 0x0008 },
2936                 { 0x0d, 0x006c },
2937
2938                 { 0x1f, 0x0000 },
2939                 { 0x0d, 0xf880 },
2940
2941                 { 0x1f, 0x0001 },
2942                 { 0x17, 0x0cc0 },
2943
2944                 { 0x1f, 0x0001 },
2945                 { 0x0b, 0xa4d8 },
2946                 { 0x09, 0x281c },
2947                 { 0x07, 0x2883 },
2948                 { 0x0a, 0x6b35 },
2949                 { 0x1d, 0x3da4 },
2950                 { 0x1c, 0xeffd },
2951                 { 0x14, 0x7f52 },
2952                 { 0x18, 0x7fc6 },
2953                 { 0x08, 0x0601 },
2954                 { 0x06, 0x4063 },
2955                 { 0x10, 0xf074 },
2956                 { 0x1f, 0x0003 },
2957                 { 0x13, 0x0789 },
2958                 { 0x12, 0xf4bd },
2959                 { 0x1a, 0x04fd },
2960                 { 0x14, 0x84b0 },
2961                 { 0x1f, 0x0000 },
2962                 { 0x00, 0x9200 },
2963
2964                 { 0x1f, 0x0005 },
2965                 { 0x01, 0x0340 },
2966                 { 0x1f, 0x0001 },
2967                 { 0x04, 0x4000 },
2968                 { 0x03, 0x1d21 },
2969                 { 0x02, 0x0c32 },
2970                 { 0x01, 0x0200 },
2971                 { 0x00, 0x5554 },
2972                 { 0x04, 0x4800 },
2973                 { 0x04, 0x4000 },
2974                 { 0x04, 0xf000 },
2975                 { 0x03, 0xdf01 },
2976                 { 0x02, 0xdf20 },
2977                 { 0x01, 0x101a },
2978                 { 0x00, 0xa0ff },
2979                 { 0x04, 0xf800 },
2980                 { 0x04, 0xf000 },
2981                 { 0x1f, 0x0000 },
2982
2983                 { 0x1f, 0x0007 },
2984                 { 0x1e, 0x0023 },
2985                 { 0x16, 0x0000 },
2986                 { 0x1f, 0x0000 }
2987         };
2988
2989         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2990 }
2991
2992 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2993 {
2994         static const struct phy_reg phy_reg_init[] = {
2995                 { 0x1f, 0x0001 },
2996                 { 0x17, 0x0cc0 },
2997
2998                 { 0x1f, 0x0007 },
2999                 { 0x1e, 0x002d },
3000                 { 0x18, 0x0040 },
3001                 { 0x1f, 0x0000 }
3002         };
3003
3004         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3005         rtl_patchphy(tp, 0x0d, 1 << 5);
3006 }
3007
3008 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3009 {
3010         static const struct phy_reg phy_reg_init[] = {
3011                 /* Enable Delay cap */
3012                 { 0x1f, 0x0005 },
3013                 { 0x05, 0x8b80 },
3014                 { 0x06, 0xc896 },
3015                 { 0x1f, 0x0000 },
3016
3017                 /* Channel estimation fine tune */
3018                 { 0x1f, 0x0001 },
3019                 { 0x0b, 0x6c20 },
3020                 { 0x07, 0x2872 },
3021                 { 0x1c, 0xefff },
3022                 { 0x1f, 0x0003 },
3023                 { 0x14, 0x6420 },
3024                 { 0x1f, 0x0000 },
3025
3026                 /* Update PFM & 10M TX idle timer */
3027                 { 0x1f, 0x0007 },
3028                 { 0x1e, 0x002f },
3029                 { 0x15, 0x1919 },
3030                 { 0x1f, 0x0000 },
3031
3032                 { 0x1f, 0x0007 },
3033                 { 0x1e, 0x00ac },
3034                 { 0x18, 0x0006 },
3035                 { 0x1f, 0x0000 }
3036         };
3037
3038         rtl_apply_firmware(tp);
3039
3040         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041
3042         /* DCO enable for 10M IDLE Power */
3043         rtl_writephy(tp, 0x1f, 0x0007);
3044         rtl_writephy(tp, 0x1e, 0x0023);
3045         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3046         rtl_writephy(tp, 0x1f, 0x0000);
3047
3048         /* For impedance matching */
3049         rtl_writephy(tp, 0x1f, 0x0002);
3050         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3051         rtl_writephy(tp, 0x1f, 0x0000);
3052
3053         /* PHY auto speed down */
3054         rtl_writephy(tp, 0x1f, 0x0007);
3055         rtl_writephy(tp, 0x1e, 0x002d);
3056         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3057         rtl_writephy(tp, 0x1f, 0x0000);
3058         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3059
3060         rtl_writephy(tp, 0x1f, 0x0005);
3061         rtl_writephy(tp, 0x05, 0x8b86);
3062         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3063         rtl_writephy(tp, 0x1f, 0x0000);
3064
3065         rtl_writephy(tp, 0x1f, 0x0005);
3066         rtl_writephy(tp, 0x05, 0x8b85);
3067         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3068         rtl_writephy(tp, 0x1f, 0x0007);
3069         rtl_writephy(tp, 0x1e, 0x0020);
3070         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3071         rtl_writephy(tp, 0x1f, 0x0006);
3072         rtl_writephy(tp, 0x00, 0x5a00);
3073         rtl_writephy(tp, 0x1f, 0x0000);
3074         rtl_writephy(tp, 0x0d, 0x0007);
3075         rtl_writephy(tp, 0x0e, 0x003c);
3076         rtl_writephy(tp, 0x0d, 0x4007);
3077         rtl_writephy(tp, 0x0e, 0x0000);
3078         rtl_writephy(tp, 0x0d, 0x0000);
3079 }
3080
3081 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3082 {
3083         const u16 w[] = {
3084                 addr[0] | (addr[1] << 8),
3085                 addr[2] | (addr[3] << 8),
3086                 addr[4] | (addr[5] << 8)
3087         };
3088         const struct exgmac_reg e[] = {
3089                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3090                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3091                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3092                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3093         };
3094
3095         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3096 }
3097
3098 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3099 {
3100         static const struct phy_reg phy_reg_init[] = {
3101                 /* Enable Delay cap */
3102                 { 0x1f, 0x0004 },
3103                 { 0x1f, 0x0007 },
3104                 { 0x1e, 0x00ac },
3105                 { 0x18, 0x0006 },
3106                 { 0x1f, 0x0002 },
3107                 { 0x1f, 0x0000 },
3108                 { 0x1f, 0x0000 },
3109
3110                 /* Channel estimation fine tune */
3111                 { 0x1f, 0x0003 },
3112                 { 0x09, 0xa20f },
3113                 { 0x1f, 0x0000 },
3114                 { 0x1f, 0x0000 },
3115
3116                 /* Green Setting */
3117                 { 0x1f, 0x0005 },
3118                 { 0x05, 0x8b5b },
3119                 { 0x06, 0x9222 },
3120                 { 0x05, 0x8b6d },
3121                 { 0x06, 0x8000 },
3122                 { 0x05, 0x8b76 },
3123                 { 0x06, 0x8000 },
3124                 { 0x1f, 0x0000 }
3125         };
3126
3127         rtl_apply_firmware(tp);
3128
3129         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3130
3131         /* For 4-corner performance improve */
3132         rtl_writephy(tp, 0x1f, 0x0005);
3133         rtl_writephy(tp, 0x05, 0x8b80);
3134         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3135         rtl_writephy(tp, 0x1f, 0x0000);
3136
3137         /* PHY auto speed down */
3138         rtl_writephy(tp, 0x1f, 0x0004);
3139         rtl_writephy(tp, 0x1f, 0x0007);
3140         rtl_writephy(tp, 0x1e, 0x002d);
3141         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3142         rtl_writephy(tp, 0x1f, 0x0002);
3143         rtl_writephy(tp, 0x1f, 0x0000);
3144         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3145
3146         /* improve 10M EEE waveform */
3147         rtl_writephy(tp, 0x1f, 0x0005);
3148         rtl_writephy(tp, 0x05, 0x8b86);
3149         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3150         rtl_writephy(tp, 0x1f, 0x0000);
3151
3152         /* Improve 2-pair detection performance */
3153         rtl_writephy(tp, 0x1f, 0x0005);
3154         rtl_writephy(tp, 0x05, 0x8b85);
3155         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3156         rtl_writephy(tp, 0x1f, 0x0000);
3157
3158         /* EEE setting */
3159         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3160         rtl_writephy(tp, 0x1f, 0x0005);
3161         rtl_writephy(tp, 0x05, 0x8b85);
3162         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3163         rtl_writephy(tp, 0x1f, 0x0004);
3164         rtl_writephy(tp, 0x1f, 0x0007);
3165         rtl_writephy(tp, 0x1e, 0x0020);
3166         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3167         rtl_writephy(tp, 0x1f, 0x0002);
3168         rtl_writephy(tp, 0x1f, 0x0000);
3169         rtl_writephy(tp, 0x0d, 0x0007);
3170         rtl_writephy(tp, 0x0e, 0x003c);
3171         rtl_writephy(tp, 0x0d, 0x4007);
3172         rtl_writephy(tp, 0x0e, 0x0000);
3173         rtl_writephy(tp, 0x0d, 0x0000);
3174
3175         /* Green feature */
3176         rtl_writephy(tp, 0x1f, 0x0003);
3177         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3178         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3179         rtl_writephy(tp, 0x1f, 0x0000);
3180
3181         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3182         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3183 }
3184
3185 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3186 {
3187         /* For 4-corner performance improve */
3188         rtl_writephy(tp, 0x1f, 0x0005);
3189         rtl_writephy(tp, 0x05, 0x8b80);
3190         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3191         rtl_writephy(tp, 0x1f, 0x0000);
3192
3193         /* PHY auto speed down */
3194         rtl_writephy(tp, 0x1f, 0x0007);
3195         rtl_writephy(tp, 0x1e, 0x002d);
3196         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3197         rtl_writephy(tp, 0x1f, 0x0000);
3198         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3199
3200         /* Improve 10M EEE waveform */
3201         rtl_writephy(tp, 0x1f, 0x0005);
3202         rtl_writephy(tp, 0x05, 0x8b86);
3203         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205 }
3206
3207 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3208 {
3209         static const struct phy_reg phy_reg_init[] = {
3210                 /* Channel estimation fine tune */
3211                 { 0x1f, 0x0003 },
3212                 { 0x09, 0xa20f },
3213                 { 0x1f, 0x0000 },
3214
3215                 /* Modify green table for giga & fnet */
3216                 { 0x1f, 0x0005 },
3217                 { 0x05, 0x8b55 },
3218                 { 0x06, 0x0000 },
3219                 { 0x05, 0x8b5e },
3220                 { 0x06, 0x0000 },
3221                 { 0x05, 0x8b67 },
3222                 { 0x06, 0x0000 },
3223                 { 0x05, 0x8b70 },
3224                 { 0x06, 0x0000 },
3225                 { 0x1f, 0x0000 },
3226                 { 0x1f, 0x0007 },
3227                 { 0x1e, 0x0078 },
3228                 { 0x17, 0x0000 },
3229                 { 0x19, 0x00fb },
3230                 { 0x1f, 0x0000 },
3231
3232                 /* Modify green table for 10M */
3233                 { 0x1f, 0x0005 },
3234                 { 0x05, 0x8b79 },
3235                 { 0x06, 0xaa00 },
3236                 { 0x1f, 0x0000 },
3237
3238                 /* Disable hiimpedance detection (RTCT) */
3239                 { 0x1f, 0x0003 },
3240                 { 0x01, 0x328a },
3241                 { 0x1f, 0x0000 }
3242         };
3243
3244         rtl_apply_firmware(tp);
3245
3246         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3247
3248         rtl8168f_hw_phy_config(tp);
3249
3250         /* Improve 2-pair detection performance */
3251         rtl_writephy(tp, 0x1f, 0x0005);
3252         rtl_writephy(tp, 0x05, 0x8b85);
3253         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3254         rtl_writephy(tp, 0x1f, 0x0000);
3255 }
3256
3257 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3258 {
3259         rtl_apply_firmware(tp);
3260
3261         rtl8168f_hw_phy_config(tp);
3262 }
3263
3264 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3265 {
3266         static const struct phy_reg phy_reg_init[] = {
3267                 /* Channel estimation fine tune */
3268                 { 0x1f, 0x0003 },
3269                 { 0x09, 0xa20f },
3270                 { 0x1f, 0x0000 },
3271
3272                 /* Modify green table for giga & fnet */
3273                 { 0x1f, 0x0005 },
3274                 { 0x05, 0x8b55 },
3275                 { 0x06, 0x0000 },
3276                 { 0x05, 0x8b5e },
3277                 { 0x06, 0x0000 },
3278                 { 0x05, 0x8b67 },
3279                 { 0x06, 0x0000 },
3280                 { 0x05, 0x8b70 },
3281                 { 0x06, 0x0000 },
3282                 { 0x1f, 0x0000 },
3283                 { 0x1f, 0x0007 },
3284                 { 0x1e, 0x0078 },
3285                 { 0x17, 0x0000 },
3286                 { 0x19, 0x00aa },
3287                 { 0x1f, 0x0000 },
3288
3289                 /* Modify green table for 10M */
3290                 { 0x1f, 0x0005 },
3291                 { 0x05, 0x8b79 },
3292                 { 0x06, 0xaa00 },
3293                 { 0x1f, 0x0000 },
3294
3295                 /* Disable hiimpedance detection (RTCT) */
3296                 { 0x1f, 0x0003 },
3297                 { 0x01, 0x328a },
3298                 { 0x1f, 0x0000 }
3299         };
3300
3301
3302         rtl_apply_firmware(tp);
3303
3304         rtl8168f_hw_phy_config(tp);
3305
3306         /* Improve 2-pair detection performance */
3307         rtl_writephy(tp, 0x1f, 0x0005);
3308         rtl_writephy(tp, 0x05, 0x8b85);
3309         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3310         rtl_writephy(tp, 0x1f, 0x0000);
3311
3312         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3313
3314         /* Modify green table for giga */
3315         rtl_writephy(tp, 0x1f, 0x0005);
3316         rtl_writephy(tp, 0x05, 0x8b54);
3317         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3318         rtl_writephy(tp, 0x05, 0x8b5d);
3319         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3320         rtl_writephy(tp, 0x05, 0x8a7c);
3321         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3322         rtl_writephy(tp, 0x05, 0x8a7f);
3323         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3324         rtl_writephy(tp, 0x05, 0x8a82);
3325         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3326         rtl_writephy(tp, 0x05, 0x8a85);
3327         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3328         rtl_writephy(tp, 0x05, 0x8a88);
3329         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3330         rtl_writephy(tp, 0x1f, 0x0000);
3331
3332         /* uc same-seed solution */
3333         rtl_writephy(tp, 0x1f, 0x0005);
3334         rtl_writephy(tp, 0x05, 0x8b85);
3335         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3336         rtl_writephy(tp, 0x1f, 0x0000);
3337
3338         /* eee setting */
3339         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3340         rtl_writephy(tp, 0x1f, 0x0005);
3341         rtl_writephy(tp, 0x05, 0x8b85);
3342         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3343         rtl_writephy(tp, 0x1f, 0x0004);
3344         rtl_writephy(tp, 0x1f, 0x0007);
3345         rtl_writephy(tp, 0x1e, 0x0020);
3346         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3347         rtl_writephy(tp, 0x1f, 0x0000);
3348         rtl_writephy(tp, 0x0d, 0x0007);
3349         rtl_writephy(tp, 0x0e, 0x003c);
3350         rtl_writephy(tp, 0x0d, 0x4007);
3351         rtl_writephy(tp, 0x0e, 0x0000);
3352         rtl_writephy(tp, 0x0d, 0x0000);
3353
3354         /* Green feature */
3355         rtl_writephy(tp, 0x1f, 0x0003);
3356         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3357         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3358         rtl_writephy(tp, 0x1f, 0x0000);
3359 }
3360
3361 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3362 {
3363         rtl_apply_firmware(tp);
3364
3365         rtl_writephy(tp, 0x1f, 0x0a46);
3366         if (rtl_readphy(tp, 0x10) & 0x0100) {
3367                 rtl_writephy(tp, 0x1f, 0x0bcc);
3368                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3369         } else {
3370                 rtl_writephy(tp, 0x1f, 0x0bcc);
3371                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3372         }
3373
3374         rtl_writephy(tp, 0x1f, 0x0a46);
3375         if (rtl_readphy(tp, 0x13) & 0x0100) {
3376                 rtl_writephy(tp, 0x1f, 0x0c41);
3377                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3378         } else {
3379                 rtl_writephy(tp, 0x1f, 0x0bcc);
3380                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x0002);
3381         }
3382
3383         /* Enable PHY auto speed down */
3384         rtl_writephy(tp, 0x1f, 0x0a44);
3385         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3386
3387         /* EEE auto-fallback function */
3388         rtl_writephy(tp, 0x1f, 0x0a4b);
3389         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3390
3391         /* Enable UC LPF tune function */
3392         rtl_writephy(tp, 0x1f, 0x0a43);
3393         rtl_writephy(tp, 0x13, 0x8012);
3394         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3395
3396         rtl_writephy(tp, 0x1f, 0x0c42);
3397         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3398
3399         rtl_writephy(tp, 0x1f, 0x0000);
3400 }
3401
3402 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3403 {
3404         static const struct phy_reg phy_reg_init[] = {
3405                 { 0x1f, 0x0003 },
3406                 { 0x08, 0x441d },
3407                 { 0x01, 0x9100 },
3408                 { 0x1f, 0x0000 }
3409         };
3410
3411         rtl_writephy(tp, 0x1f, 0x0000);
3412         rtl_patchphy(tp, 0x11, 1 << 12);
3413         rtl_patchphy(tp, 0x19, 1 << 13);
3414         rtl_patchphy(tp, 0x10, 1 << 15);
3415
3416         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3417 }
3418
3419 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3420 {
3421         static const struct phy_reg phy_reg_init[] = {
3422                 { 0x1f, 0x0005 },
3423                 { 0x1a, 0x0000 },
3424                 { 0x1f, 0x0000 },
3425
3426                 { 0x1f, 0x0004 },
3427                 { 0x1c, 0x0000 },
3428                 { 0x1f, 0x0000 },
3429
3430                 { 0x1f, 0x0001 },
3431                 { 0x15, 0x7701 },
3432                 { 0x1f, 0x0000 }
3433         };
3434
3435         /* Disable ALDPS before ram code */
3436         rtl_writephy(tp, 0x1f, 0x0000);
3437         rtl_writephy(tp, 0x18, 0x0310);
3438         msleep(100);
3439
3440         rtl_apply_firmware(tp);
3441
3442         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3443 }
3444
3445 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3446 {
3447         /* Disable ALDPS before setting firmware */
3448         rtl_writephy(tp, 0x1f, 0x0000);
3449         rtl_writephy(tp, 0x18, 0x0310);
3450         msleep(20);
3451
3452         rtl_apply_firmware(tp);
3453
3454         /* EEE setting */
3455         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3456         rtl_writephy(tp, 0x1f, 0x0004);
3457         rtl_writephy(tp, 0x10, 0x401f);
3458         rtl_writephy(tp, 0x19, 0x7030);
3459         rtl_writephy(tp, 0x1f, 0x0000);
3460 }
3461
3462 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3463 {
3464         static const struct phy_reg phy_reg_init[] = {
3465                 { 0x1f, 0x0004 },
3466                 { 0x10, 0xc07f },
3467                 { 0x19, 0x7030 },
3468                 { 0x1f, 0x0000 }
3469         };
3470
3471         /* Disable ALDPS before ram code */
3472         rtl_writephy(tp, 0x1f, 0x0000);
3473         rtl_writephy(tp, 0x18, 0x0310);
3474         msleep(100);
3475
3476         rtl_apply_firmware(tp);
3477
3478         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3479         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3480
3481         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3482 }
3483
3484 static void rtl_hw_phy_config(struct net_device *dev)
3485 {
3486         struct rtl8169_private *tp = netdev_priv(dev);
3487
3488         rtl8169_print_mac_version(tp);
3489
3490         switch (tp->mac_version) {
3491         case RTL_GIGA_MAC_VER_01:
3492                 break;
3493         case RTL_GIGA_MAC_VER_02:
3494         case RTL_GIGA_MAC_VER_03:
3495                 rtl8169s_hw_phy_config(tp);
3496                 break;
3497         case RTL_GIGA_MAC_VER_04:
3498                 rtl8169sb_hw_phy_config(tp);
3499                 break;
3500         case RTL_GIGA_MAC_VER_05:
3501                 rtl8169scd_hw_phy_config(tp);
3502                 break;
3503         case RTL_GIGA_MAC_VER_06:
3504                 rtl8169sce_hw_phy_config(tp);
3505                 break;
3506         case RTL_GIGA_MAC_VER_07:
3507         case RTL_GIGA_MAC_VER_08:
3508         case RTL_GIGA_MAC_VER_09:
3509                 rtl8102e_hw_phy_config(tp);
3510                 break;
3511         case RTL_GIGA_MAC_VER_11:
3512                 rtl8168bb_hw_phy_config(tp);
3513                 break;
3514         case RTL_GIGA_MAC_VER_12:
3515                 rtl8168bef_hw_phy_config(tp);
3516                 break;
3517         case RTL_GIGA_MAC_VER_17:
3518                 rtl8168bef_hw_phy_config(tp);
3519                 break;
3520         case RTL_GIGA_MAC_VER_18:
3521                 rtl8168cp_1_hw_phy_config(tp);
3522                 break;
3523         case RTL_GIGA_MAC_VER_19:
3524                 rtl8168c_1_hw_phy_config(tp);
3525                 break;
3526         case RTL_GIGA_MAC_VER_20:
3527                 rtl8168c_2_hw_phy_config(tp);
3528                 break;
3529         case RTL_GIGA_MAC_VER_21:
3530                 rtl8168c_3_hw_phy_config(tp);
3531                 break;
3532         case RTL_GIGA_MAC_VER_22:
3533                 rtl8168c_4_hw_phy_config(tp);
3534                 break;
3535         case RTL_GIGA_MAC_VER_23:
3536         case RTL_GIGA_MAC_VER_24:
3537                 rtl8168cp_2_hw_phy_config(tp);
3538                 break;
3539         case RTL_GIGA_MAC_VER_25:
3540                 rtl8168d_1_hw_phy_config(tp);
3541                 break;
3542         case RTL_GIGA_MAC_VER_26:
3543                 rtl8168d_2_hw_phy_config(tp);
3544                 break;
3545         case RTL_GIGA_MAC_VER_27:
3546                 rtl8168d_3_hw_phy_config(tp);
3547                 break;
3548         case RTL_GIGA_MAC_VER_28:
3549                 rtl8168d_4_hw_phy_config(tp);
3550                 break;
3551         case RTL_GIGA_MAC_VER_29:
3552         case RTL_GIGA_MAC_VER_30:
3553                 rtl8105e_hw_phy_config(tp);
3554                 break;
3555         case RTL_GIGA_MAC_VER_31:
3556                 /* None. */
3557                 break;
3558         case RTL_GIGA_MAC_VER_32:
3559         case RTL_GIGA_MAC_VER_33:
3560                 rtl8168e_1_hw_phy_config(tp);
3561                 break;
3562         case RTL_GIGA_MAC_VER_34:
3563                 rtl8168e_2_hw_phy_config(tp);
3564                 break;
3565         case RTL_GIGA_MAC_VER_35:
3566                 rtl8168f_1_hw_phy_config(tp);
3567                 break;
3568         case RTL_GIGA_MAC_VER_36:
3569                 rtl8168f_2_hw_phy_config(tp);
3570                 break;
3571
3572         case RTL_GIGA_MAC_VER_37:
3573                 rtl8402_hw_phy_config(tp);
3574                 break;
3575
3576         case RTL_GIGA_MAC_VER_38:
3577                 rtl8411_hw_phy_config(tp);
3578                 break;
3579
3580         case RTL_GIGA_MAC_VER_39:
3581                 rtl8106e_hw_phy_config(tp);
3582                 break;
3583
3584         case RTL_GIGA_MAC_VER_40:
3585                 rtl8168g_1_hw_phy_config(tp);
3586                 break;
3587
3588         case RTL_GIGA_MAC_VER_41:
3589         default:
3590                 break;
3591         }
3592 }
3593
3594 static void rtl_phy_work(struct rtl8169_private *tp)
3595 {
3596         struct timer_list *timer = &tp->timer;
3597         void __iomem *ioaddr = tp->mmio_addr;
3598         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3599
3600         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3601
3602         if (tp->phy_reset_pending(tp)) {
3603                 /*
3604                  * A busy loop could burn quite a few cycles on nowadays CPU.
3605                  * Let's delay the execution of the timer for a few ticks.
3606                  */
3607                 timeout = HZ/10;
3608                 goto out_mod_timer;
3609         }
3610
3611         if (tp->link_ok(ioaddr))
3612                 return;
3613
3614         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3615
3616         tp->phy_reset_enable(tp);
3617
3618 out_mod_timer:
3619         mod_timer(timer, jiffies + timeout);
3620 }
3621
3622 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3623 {
3624         if (!test_and_set_bit(flag, tp->wk.flags))
3625                 schedule_work(&tp->wk.work);
3626 }
3627
3628 static void rtl8169_phy_timer(unsigned long __opaque)
3629 {
3630         struct net_device *dev = (struct net_device *)__opaque;
3631         struct rtl8169_private *tp = netdev_priv(dev);
3632
3633         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3634 }
3635
3636 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3637                                   void __iomem *ioaddr)
3638 {
3639         iounmap(ioaddr);
3640         pci_release_regions(pdev);
3641         pci_clear_mwi(pdev);
3642         pci_disable_device(pdev);
3643         free_netdev(dev);
3644 }
3645
3646 DECLARE_RTL_COND(rtl_phy_reset_cond)
3647 {
3648         return tp->phy_reset_pending(tp);
3649 }
3650
3651 static void rtl8169_phy_reset(struct net_device *dev,
3652                               struct rtl8169_private *tp)
3653 {
3654         tp->phy_reset_enable(tp);
3655         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3656 }
3657
3658 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3659 {
3660         void __iomem *ioaddr = tp->mmio_addr;
3661
3662         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3663             (RTL_R8(PHYstatus) & TBI_Enable);
3664 }
3665
3666 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3667 {
3668         void __iomem *ioaddr = tp->mmio_addr;
3669
3670         rtl_hw_phy_config(dev);
3671
3672         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3673                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3674                 RTL_W8(0x82, 0x01);
3675         }
3676
3677         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3678
3679         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3680                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3681
3682         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3683                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3684                 RTL_W8(0x82, 0x01);
3685                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3686                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3687         }
3688
3689         rtl8169_phy_reset(dev, tp);
3690
3691         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3692                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3693                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3694                           (tp->mii.supports_gmii ?
3695                            ADVERTISED_1000baseT_Half |
3696                            ADVERTISED_1000baseT_Full : 0));
3697
3698         if (rtl_tbi_enabled(tp))
3699                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3700 }
3701
3702 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3703 {
3704         void __iomem *ioaddr = tp->mmio_addr;
3705
3706         rtl_lock_work(tp);
3707
3708         RTL_W8(Cfg9346, Cfg9346_Unlock);
3709
3710         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3711         RTL_R32(MAC4);
3712
3713         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3714         RTL_R32(MAC0);
3715
3716         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3717                 rtl_rar_exgmac_set(tp, addr);
3718
3719         RTL_W8(Cfg9346, Cfg9346_Lock);
3720
3721         rtl_unlock_work(tp);
3722 }
3723
3724 static int rtl_set_mac_address(struct net_device *dev, void *p)
3725 {
3726         struct rtl8169_private *tp = netdev_priv(dev);
3727         struct sockaddr *addr = p;
3728
3729         if (!is_valid_ether_addr(addr->sa_data))
3730                 return -EADDRNOTAVAIL;
3731
3732         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3733
3734         rtl_rar_set(tp, dev->dev_addr);
3735
3736         return 0;
3737 }
3738
3739 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3740 {
3741         struct rtl8169_private *tp = netdev_priv(dev);
3742         struct mii_ioctl_data *data = if_mii(ifr);
3743
3744         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3745 }
3746
3747 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3748                           struct mii_ioctl_data *data, int cmd)
3749 {
3750         switch (cmd) {
3751         case SIOCGMIIPHY:
3752                 data->phy_id = 32; /* Internal PHY */
3753                 return 0;
3754
3755         case SIOCGMIIREG:
3756                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3757                 return 0;
3758
3759         case SIOCSMIIREG:
3760                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3761                 return 0;
3762         }
3763         return -EOPNOTSUPP;
3764 }
3765
3766 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3767 {
3768         return -EOPNOTSUPP;
3769 }
3770
3771 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3772 {
3773         if (tp->features & RTL_FEATURE_MSI) {
3774                 pci_disable_msi(pdev);
3775                 tp->features &= ~RTL_FEATURE_MSI;
3776         }
3777 }
3778
3779 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3780 {
3781         struct mdio_ops *ops = &tp->mdio_ops;
3782
3783         switch (tp->mac_version) {
3784         case RTL_GIGA_MAC_VER_27:
3785                 ops->write      = r8168dp_1_mdio_write;
3786                 ops->read       = r8168dp_1_mdio_read;
3787                 break;
3788         case RTL_GIGA_MAC_VER_28:
3789         case RTL_GIGA_MAC_VER_31:
3790                 ops->write      = r8168dp_2_mdio_write;
3791                 ops->read       = r8168dp_2_mdio_read;
3792                 break;
3793         case RTL_GIGA_MAC_VER_40:
3794         case RTL_GIGA_MAC_VER_41:
3795                 ops->write      = r8168g_mdio_write;
3796                 ops->read       = r8168g_mdio_read;
3797                 break;
3798         default:
3799                 ops->write      = r8169_mdio_write;
3800                 ops->read       = r8169_mdio_read;
3801                 break;
3802         }
3803 }
3804
3805 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3806 {
3807         void __iomem *ioaddr = tp->mmio_addr;
3808
3809         switch (tp->mac_version) {
3810         case RTL_GIGA_MAC_VER_25:
3811         case RTL_GIGA_MAC_VER_26:
3812         case RTL_GIGA_MAC_VER_29:
3813         case RTL_GIGA_MAC_VER_30:
3814         case RTL_GIGA_MAC_VER_32:
3815         case RTL_GIGA_MAC_VER_33:
3816         case RTL_GIGA_MAC_VER_34:
3817         case RTL_GIGA_MAC_VER_37:
3818         case RTL_GIGA_MAC_VER_38:
3819         case RTL_GIGA_MAC_VER_39:
3820         case RTL_GIGA_MAC_VER_40:
3821         case RTL_GIGA_MAC_VER_41:
3822                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3823                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3824                 break;
3825         default:
3826                 break;
3827         }
3828 }
3829
3830 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3831 {
3832         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3833                 return false;
3834
3835         rtl_writephy(tp, 0x1f, 0x0000);
3836         rtl_writephy(tp, MII_BMCR, 0x0000);
3837
3838         rtl_wol_suspend_quirk(tp);
3839
3840         return true;
3841 }
3842
3843 static void r810x_phy_power_down(struct rtl8169_private *tp)
3844 {
3845         rtl_writephy(tp, 0x1f, 0x0000);
3846         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3847 }
3848
3849 static void r810x_phy_power_up(struct rtl8169_private *tp)
3850 {
3851         rtl_writephy(tp, 0x1f, 0x0000);
3852         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3853 }
3854
3855 static void r810x_pll_power_down(struct rtl8169_private *tp)
3856 {
3857         void __iomem *ioaddr = tp->mmio_addr;
3858
3859         if (rtl_wol_pll_power_down(tp))
3860                 return;
3861
3862         r810x_phy_power_down(tp);
3863
3864         switch (tp->mac_version) {
3865         case RTL_GIGA_MAC_VER_07:
3866         case RTL_GIGA_MAC_VER_08:
3867         case RTL_GIGA_MAC_VER_09:
3868         case RTL_GIGA_MAC_VER_10:
3869         case RTL_GIGA_MAC_VER_13:
3870         case RTL_GIGA_MAC_VER_16:
3871                 break;
3872         default:
3873                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3874                 break;
3875         }
3876 }
3877
3878 static void r810x_pll_power_up(struct rtl8169_private *tp)
3879 {
3880         void __iomem *ioaddr = tp->mmio_addr;
3881
3882         r810x_phy_power_up(tp);
3883
3884         switch (tp->mac_version) {
3885         case RTL_GIGA_MAC_VER_07:
3886         case RTL_GIGA_MAC_VER_08:
3887         case RTL_GIGA_MAC_VER_09:
3888         case RTL_GIGA_MAC_VER_10:
3889         case RTL_GIGA_MAC_VER_13:
3890         case RTL_GIGA_MAC_VER_16:
3891                 break;
3892         default:
3893                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3894                 break;
3895         }
3896 }
3897
3898 static void r8168_phy_power_up(struct rtl8169_private *tp)
3899 {
3900         rtl_writephy(tp, 0x1f, 0x0000);
3901         switch (tp->mac_version) {
3902         case RTL_GIGA_MAC_VER_11:
3903         case RTL_GIGA_MAC_VER_12:
3904         case RTL_GIGA_MAC_VER_17:
3905         case RTL_GIGA_MAC_VER_18:
3906         case RTL_GIGA_MAC_VER_19:
3907         case RTL_GIGA_MAC_VER_20:
3908         case RTL_GIGA_MAC_VER_21:
3909         case RTL_GIGA_MAC_VER_22:
3910         case RTL_GIGA_MAC_VER_23:
3911         case RTL_GIGA_MAC_VER_24:
3912         case RTL_GIGA_MAC_VER_25:
3913         case RTL_GIGA_MAC_VER_26:
3914         case RTL_GIGA_MAC_VER_27:
3915         case RTL_GIGA_MAC_VER_28:
3916         case RTL_GIGA_MAC_VER_31:
3917                 rtl_writephy(tp, 0x0e, 0x0000);
3918                 break;
3919         default:
3920                 break;
3921         }
3922         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3923 }
3924
3925 static void r8168_phy_power_down(struct rtl8169_private *tp)
3926 {
3927         rtl_writephy(tp, 0x1f, 0x0000);
3928         switch (tp->mac_version) {
3929         case RTL_GIGA_MAC_VER_32:
3930         case RTL_GIGA_MAC_VER_33:
3931                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3932                 break;
3933
3934         case RTL_GIGA_MAC_VER_11:
3935         case RTL_GIGA_MAC_VER_12:
3936         case RTL_GIGA_MAC_VER_17:
3937         case RTL_GIGA_MAC_VER_18:
3938         case RTL_GIGA_MAC_VER_19:
3939         case RTL_GIGA_MAC_VER_20:
3940         case RTL_GIGA_MAC_VER_21:
3941         case RTL_GIGA_MAC_VER_22:
3942         case RTL_GIGA_MAC_VER_23:
3943         case RTL_GIGA_MAC_VER_24:
3944         case RTL_GIGA_MAC_VER_25:
3945         case RTL_GIGA_MAC_VER_26:
3946         case RTL_GIGA_MAC_VER_27:
3947         case RTL_GIGA_MAC_VER_28:
3948         case RTL_GIGA_MAC_VER_31:
3949                 rtl_writephy(tp, 0x0e, 0x0200);
3950         default:
3951                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3952                 break;
3953         }
3954 }
3955
3956 static void r8168_pll_power_down(struct rtl8169_private *tp)
3957 {
3958         void __iomem *ioaddr = tp->mmio_addr;
3959
3960         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3961              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3962              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3963             r8168dp_check_dash(tp)) {
3964                 return;
3965         }
3966
3967         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3968              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3969             (RTL_R16(CPlusCmd) & ASF)) {
3970                 return;
3971         }
3972
3973         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3974             tp->mac_version == RTL_GIGA_MAC_VER_33)
3975                 rtl_ephy_write(tp, 0x19, 0xff64);
3976
3977         if (rtl_wol_pll_power_down(tp))
3978                 return;
3979
3980         r8168_phy_power_down(tp);
3981
3982         switch (tp->mac_version) {
3983         case RTL_GIGA_MAC_VER_25:
3984         case RTL_GIGA_MAC_VER_26:
3985         case RTL_GIGA_MAC_VER_27:
3986         case RTL_GIGA_MAC_VER_28:
3987         case RTL_GIGA_MAC_VER_31:
3988         case RTL_GIGA_MAC_VER_32:
3989         case RTL_GIGA_MAC_VER_33:
3990                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3991                 break;
3992         }
3993 }
3994
3995 static void r8168_pll_power_up(struct rtl8169_private *tp)
3996 {
3997         void __iomem *ioaddr = tp->mmio_addr;
3998
3999         switch (tp->mac_version) {
4000         case RTL_GIGA_MAC_VER_25:
4001         case RTL_GIGA_MAC_VER_26:
4002         case RTL_GIGA_MAC_VER_27:
4003         case RTL_GIGA_MAC_VER_28:
4004         case RTL_GIGA_MAC_VER_31:
4005         case RTL_GIGA_MAC_VER_32:
4006         case RTL_GIGA_MAC_VER_33:
4007                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4008                 break;
4009         }
4010
4011         r8168_phy_power_up(tp);
4012 }
4013
4014 static void rtl_generic_op(struct rtl8169_private *tp,
4015                            void (*op)(struct rtl8169_private *))
4016 {
4017         if (op)
4018                 op(tp);
4019 }
4020
4021 static void rtl_pll_power_down(struct rtl8169_private *tp)
4022 {
4023         rtl_generic_op(tp, tp->pll_power_ops.down);
4024 }
4025
4026 static void rtl_pll_power_up(struct rtl8169_private *tp)
4027 {
4028         rtl_generic_op(tp, tp->pll_power_ops.up);
4029 }
4030
4031 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4032 {
4033         struct pll_power_ops *ops = &tp->pll_power_ops;
4034
4035         switch (tp->mac_version) {
4036         case RTL_GIGA_MAC_VER_07:
4037         case RTL_GIGA_MAC_VER_08:
4038         case RTL_GIGA_MAC_VER_09:
4039         case RTL_GIGA_MAC_VER_10:
4040         case RTL_GIGA_MAC_VER_16:
4041         case RTL_GIGA_MAC_VER_29:
4042         case RTL_GIGA_MAC_VER_30:
4043         case RTL_GIGA_MAC_VER_37:
4044         case RTL_GIGA_MAC_VER_39:
4045                 ops->down       = r810x_pll_power_down;
4046                 ops->up         = r810x_pll_power_up;
4047                 break;
4048
4049         case RTL_GIGA_MAC_VER_11:
4050         case RTL_GIGA_MAC_VER_12:
4051         case RTL_GIGA_MAC_VER_17:
4052         case RTL_GIGA_MAC_VER_18:
4053         case RTL_GIGA_MAC_VER_19:
4054         case RTL_GIGA_MAC_VER_20:
4055         case RTL_GIGA_MAC_VER_21:
4056         case RTL_GIGA_MAC_VER_22:
4057         case RTL_GIGA_MAC_VER_23:
4058         case RTL_GIGA_MAC_VER_24:
4059         case RTL_GIGA_MAC_VER_25:
4060         case RTL_GIGA_MAC_VER_26:
4061         case RTL_GIGA_MAC_VER_27:
4062         case RTL_GIGA_MAC_VER_28:
4063         case RTL_GIGA_MAC_VER_31:
4064         case RTL_GIGA_MAC_VER_32:
4065         case RTL_GIGA_MAC_VER_33:
4066         case RTL_GIGA_MAC_VER_34:
4067         case RTL_GIGA_MAC_VER_35:
4068         case RTL_GIGA_MAC_VER_36:
4069         case RTL_GIGA_MAC_VER_38:
4070         case RTL_GIGA_MAC_VER_40:
4071         case RTL_GIGA_MAC_VER_41:
4072                 ops->down       = r8168_pll_power_down;
4073                 ops->up         = r8168_pll_power_up;
4074                 break;
4075
4076         default:
4077                 ops->down       = NULL;
4078                 ops->up         = NULL;
4079                 break;
4080         }
4081 }
4082
4083 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4084 {
4085         void __iomem *ioaddr = tp->mmio_addr;
4086
4087         switch (tp->mac_version) {
4088         case RTL_GIGA_MAC_VER_01:
4089         case RTL_GIGA_MAC_VER_02:
4090         case RTL_GIGA_MAC_VER_03:
4091         case RTL_GIGA_MAC_VER_04:
4092         case RTL_GIGA_MAC_VER_05:
4093         case RTL_GIGA_MAC_VER_06:
4094         case RTL_GIGA_MAC_VER_10:
4095         case RTL_GIGA_MAC_VER_11:
4096         case RTL_GIGA_MAC_VER_12:
4097         case RTL_GIGA_MAC_VER_13:
4098         case RTL_GIGA_MAC_VER_14:
4099         case RTL_GIGA_MAC_VER_15:
4100         case RTL_GIGA_MAC_VER_16:
4101         case RTL_GIGA_MAC_VER_17:
4102                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4103                 break;
4104         case RTL_GIGA_MAC_VER_18:
4105         case RTL_GIGA_MAC_VER_19:
4106         case RTL_GIGA_MAC_VER_20:
4107         case RTL_GIGA_MAC_VER_21:
4108         case RTL_GIGA_MAC_VER_22:
4109         case RTL_GIGA_MAC_VER_23:
4110         case RTL_GIGA_MAC_VER_24:
4111         case RTL_GIGA_MAC_VER_34:
4112                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4113                 break;
4114         default:
4115                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4116                 break;
4117         }
4118 }
4119
4120 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4121 {
4122         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4123 }
4124
4125 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4126 {
4127         void __iomem *ioaddr = tp->mmio_addr;
4128
4129         RTL_W8(Cfg9346, Cfg9346_Unlock);
4130         rtl_generic_op(tp, tp->jumbo_ops.enable);
4131         RTL_W8(Cfg9346, Cfg9346_Lock);
4132 }
4133
4134 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4135 {
4136         void __iomem *ioaddr = tp->mmio_addr;
4137
4138         RTL_W8(Cfg9346, Cfg9346_Unlock);
4139         rtl_generic_op(tp, tp->jumbo_ops.disable);
4140         RTL_W8(Cfg9346, Cfg9346_Lock);
4141 }
4142
4143 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4144 {
4145         void __iomem *ioaddr = tp->mmio_addr;
4146
4147         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4148         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4149         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4150 }
4151
4152 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4153 {
4154         void __iomem *ioaddr = tp->mmio_addr;
4155
4156         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4157         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4158         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4159 }
4160
4161 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4162 {
4163         void __iomem *ioaddr = tp->mmio_addr;
4164
4165         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4166 }
4167
4168 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4169 {
4170         void __iomem *ioaddr = tp->mmio_addr;
4171
4172         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4173 }
4174
4175 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4176 {
4177         void __iomem *ioaddr = tp->mmio_addr;
4178
4179         RTL_W8(MaxTxPacketSize, 0x3f);
4180         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4181         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4182         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4183 }
4184
4185 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4186 {
4187         void __iomem *ioaddr = tp->mmio_addr;
4188
4189         RTL_W8(MaxTxPacketSize, 0x0c);
4190         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4191         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4192         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4193 }
4194
4195 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4196 {
4197         rtl_tx_performance_tweak(tp->pci_dev,
4198                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4199 }
4200
4201 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4202 {
4203         rtl_tx_performance_tweak(tp->pci_dev,
4204                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4205 }
4206
4207 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4208 {
4209         void __iomem *ioaddr = tp->mmio_addr;
4210
4211         r8168b_0_hw_jumbo_enable(tp);
4212
4213         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4214 }
4215
4216 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4217 {
4218         void __iomem *ioaddr = tp->mmio_addr;
4219
4220         r8168b_0_hw_jumbo_disable(tp);
4221
4222         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4223 }
4224
4225 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4226 {
4227         struct jumbo_ops *ops = &tp->jumbo_ops;
4228
4229         switch (tp->mac_version) {
4230         case RTL_GIGA_MAC_VER_11:
4231                 ops->disable    = r8168b_0_hw_jumbo_disable;
4232                 ops->enable     = r8168b_0_hw_jumbo_enable;
4233                 break;
4234         case RTL_GIGA_MAC_VER_12:
4235         case RTL_GIGA_MAC_VER_17:
4236                 ops->disable    = r8168b_1_hw_jumbo_disable;
4237                 ops->enable     = r8168b_1_hw_jumbo_enable;
4238                 break;
4239         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4240         case RTL_GIGA_MAC_VER_19:
4241         case RTL_GIGA_MAC_VER_20:
4242         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4243         case RTL_GIGA_MAC_VER_22:
4244         case RTL_GIGA_MAC_VER_23:
4245         case RTL_GIGA_MAC_VER_24:
4246         case RTL_GIGA_MAC_VER_25:
4247         case RTL_GIGA_MAC_VER_26:
4248                 ops->disable    = r8168c_hw_jumbo_disable;
4249                 ops->enable     = r8168c_hw_jumbo_enable;
4250                 break;
4251         case RTL_GIGA_MAC_VER_27:
4252         case RTL_GIGA_MAC_VER_28:
4253                 ops->disable    = r8168dp_hw_jumbo_disable;
4254                 ops->enable     = r8168dp_hw_jumbo_enable;
4255                 break;
4256         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4257         case RTL_GIGA_MAC_VER_32:
4258         case RTL_GIGA_MAC_VER_33:
4259         case RTL_GIGA_MAC_VER_34:
4260                 ops->disable    = r8168e_hw_jumbo_disable;
4261                 ops->enable     = r8168e_hw_jumbo_enable;
4262                 break;
4263
4264         /*
4265          * No action needed for jumbo frames with 8169.
4266          * No jumbo for 810x at all.
4267          */
4268         case RTL_GIGA_MAC_VER_40:
4269         case RTL_GIGA_MAC_VER_41:
4270         default:
4271                 ops->disable    = NULL;
4272                 ops->enable     = NULL;
4273                 break;
4274         }
4275 }
4276
4277 DECLARE_RTL_COND(rtl_chipcmd_cond)
4278 {
4279         void __iomem *ioaddr = tp->mmio_addr;
4280
4281         return RTL_R8(ChipCmd) & CmdReset;
4282 }
4283
4284 static void rtl_hw_reset(struct rtl8169_private *tp)
4285 {
4286         void __iomem *ioaddr = tp->mmio_addr;
4287
4288         RTL_W8(ChipCmd, CmdReset);
4289
4290         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4291 }
4292
4293 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4294 {
4295         struct rtl_fw *rtl_fw;
4296         const char *name;
4297         int rc = -ENOMEM;
4298
4299         name = rtl_lookup_firmware_name(tp);
4300         if (!name)
4301                 goto out_no_firmware;
4302
4303         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4304         if (!rtl_fw)
4305                 goto err_warn;
4306
4307         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4308         if (rc < 0)
4309                 goto err_free;
4310
4311         rc = rtl_check_firmware(tp, rtl_fw);
4312         if (rc < 0)
4313                 goto err_release_firmware;
4314
4315         tp->rtl_fw = rtl_fw;
4316 out:
4317         return;
4318
4319 err_release_firmware:
4320         release_firmware(rtl_fw->fw);
4321 err_free:
4322         kfree(rtl_fw);
4323 err_warn:
4324         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4325                    name, rc);
4326 out_no_firmware:
4327         tp->rtl_fw = NULL;
4328         goto out;
4329 }
4330
4331 static void rtl_request_firmware(struct rtl8169_private *tp)
4332 {
4333         if (IS_ERR(tp->rtl_fw))
4334                 rtl_request_uncached_firmware(tp);
4335 }
4336
4337 static void rtl_rx_close(struct rtl8169_private *tp)
4338 {
4339         void __iomem *ioaddr = tp->mmio_addr;
4340
4341         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4342 }
4343
4344 DECLARE_RTL_COND(rtl_npq_cond)
4345 {
4346         void __iomem *ioaddr = tp->mmio_addr;
4347
4348         return RTL_R8(TxPoll) & NPQ;
4349 }
4350
4351 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4352 {
4353         void __iomem *ioaddr = tp->mmio_addr;
4354
4355         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4356 }
4357
4358 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4359 {
4360         void __iomem *ioaddr = tp->mmio_addr;
4361
4362         /* Disable interrupts */
4363         rtl8169_irq_mask_and_ack(tp);
4364
4365         rtl_rx_close(tp);
4366
4367         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4368             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4369             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4370                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4371         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4372                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4373                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4374                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4375                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4376                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4377                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4378                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4379                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4380         } else {
4381                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4382                 udelay(100);
4383         }
4384
4385         rtl_hw_reset(tp);
4386 }
4387
4388 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4389 {
4390         void __iomem *ioaddr = tp->mmio_addr;
4391
4392         /* Set DMA burst size and Interframe Gap Time */
4393         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4394                 (InterFrameGap << TxInterFrameGapShift));
4395 }
4396
4397 static void rtl_hw_start(struct net_device *dev)
4398 {
4399         struct rtl8169_private *tp = netdev_priv(dev);
4400
4401         tp->hw_start(dev);
4402
4403         rtl_irq_enable_all(tp);
4404 }
4405
4406 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4407                                          void __iomem *ioaddr)
4408 {
4409         /*
4410          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4411          * register to be written before TxDescAddrLow to work.
4412          * Switching from MMIO to I/O access fixes the issue as well.
4413          */
4414         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4415         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4416         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4417         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4418 }
4419
4420 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4421 {
4422         u16 cmd;
4423
4424         cmd = RTL_R16(CPlusCmd);
4425         RTL_W16(CPlusCmd, cmd);
4426         return cmd;
4427 }
4428
4429 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4430 {
4431         /* Low hurts. Let's disable the filtering. */
4432         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4433 }
4434
4435 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4436 {
4437         static const struct rtl_cfg2_info {
4438                 u32 mac_version;
4439                 u32 clk;
4440                 u32 val;
4441         } cfg2_info [] = {
4442                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4443                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4444                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4445                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4446         };
4447         const struct rtl_cfg2_info *p = cfg2_info;
4448         unsigned int i;
4449         u32 clk;
4450
4451         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4452         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4453                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4454                         RTL_W32(0x7c, p->val);
4455                         break;
4456                 }
4457         }
4458 }
4459
4460 static void rtl_set_rx_mode(struct net_device *dev)
4461 {
4462         struct rtl8169_private *tp = netdev_priv(dev);
4463         void __iomem *ioaddr = tp->mmio_addr;
4464         u32 mc_filter[2];       /* Multicast hash filter */
4465         int rx_mode;
4466         u32 tmp = 0;
4467
4468         if (dev->flags & IFF_PROMISC) {
4469                 /* Unconditionally log net taps. */
4470                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4471                 rx_mode =
4472                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4473                     AcceptAllPhys;
4474                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4475         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4476                    (dev->flags & IFF_ALLMULTI)) {
4477                 /* Too many to filter perfectly -- accept all multicasts. */
4478                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4479                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4480         } else {
4481                 struct netdev_hw_addr *ha;
4482
4483                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4484                 mc_filter[1] = mc_filter[0] = 0;
4485                 netdev_for_each_mc_addr(ha, dev) {
4486                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4487                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4488                         rx_mode |= AcceptMulticast;
4489                 }
4490         }
4491
4492         if (dev->features & NETIF_F_RXALL)
4493                 rx_mode |= (AcceptErr | AcceptRunt);
4494
4495         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4496
4497         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4498                 u32 data = mc_filter[0];
4499
4500                 mc_filter[0] = swab32(mc_filter[1]);
4501                 mc_filter[1] = swab32(data);
4502         }
4503
4504         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4505                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4506
4507         RTL_W32(MAR0 + 4, mc_filter[1]);
4508         RTL_W32(MAR0 + 0, mc_filter[0]);
4509
4510         RTL_W32(RxConfig, tmp);
4511 }
4512
4513 static void rtl_hw_start_8169(struct net_device *dev)
4514 {
4515         struct rtl8169_private *tp = netdev_priv(dev);
4516         void __iomem *ioaddr = tp->mmio_addr;
4517         struct pci_dev *pdev = tp->pci_dev;
4518
4519         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4520                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4521                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4522         }
4523
4524         RTL_W8(Cfg9346, Cfg9346_Unlock);
4525         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4526             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4527             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4528             tp->mac_version == RTL_GIGA_MAC_VER_04)
4529                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4530
4531         rtl_init_rxcfg(tp);
4532
4533         RTL_W8(EarlyTxThres, NoEarlyTx);
4534
4535         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4536
4537         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4538             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4539             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4540             tp->mac_version == RTL_GIGA_MAC_VER_04)
4541                 rtl_set_rx_tx_config_registers(tp);
4542
4543         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4544
4545         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4546             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4547                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4548                         "Bit-3 and bit-14 MUST be 1\n");
4549                 tp->cp_cmd |= (1 << 14);
4550         }
4551
4552         RTL_W16(CPlusCmd, tp->cp_cmd);
4553
4554         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4555
4556         /*
4557          * Undocumented corner. Supposedly:
4558          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4559          */
4560         RTL_W16(IntrMitigate, 0x0000);
4561
4562         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4563
4564         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4565             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4566             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4567             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4568                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4569                 rtl_set_rx_tx_config_registers(tp);
4570         }
4571
4572         RTL_W8(Cfg9346, Cfg9346_Lock);
4573
4574         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4575         RTL_R8(IntrMask);
4576
4577         RTL_W32(RxMissed, 0);
4578
4579         rtl_set_rx_mode(dev);
4580
4581         /* no early-rx interrupts */
4582         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4583 }
4584
4585 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4586 {
4587         if (tp->csi_ops.write)
4588                 tp->csi_ops.write(tp, addr, value);
4589 }
4590
4591 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4592 {
4593         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4594 }
4595
4596 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4597 {
4598         u32 csi;
4599
4600         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4601         rtl_csi_write(tp, 0x070c, csi | bits);
4602 }
4603
4604 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4605 {
4606         rtl_csi_access_enable(tp, 0x17000000);
4607 }
4608
4609 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4610 {
4611         rtl_csi_access_enable(tp, 0x27000000);
4612 }
4613
4614 DECLARE_RTL_COND(rtl_csiar_cond)
4615 {
4616         void __iomem *ioaddr = tp->mmio_addr;
4617
4618         return RTL_R32(CSIAR) & CSIAR_FLAG;
4619 }
4620
4621 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4622 {
4623         void __iomem *ioaddr = tp->mmio_addr;
4624
4625         RTL_W32(CSIDR, value);
4626         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4627                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4628
4629         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4630 }
4631
4632 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4633 {
4634         void __iomem *ioaddr = tp->mmio_addr;
4635
4636         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4637                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4638
4639         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4640                 RTL_R32(CSIDR) : ~0;
4641 }
4642
4643 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4644 {
4645         void __iomem *ioaddr = tp->mmio_addr;
4646
4647         RTL_W32(CSIDR, value);
4648         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4649                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4650                 CSIAR_FUNC_NIC);
4651
4652         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4653 }
4654
4655 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4656 {
4657         void __iomem *ioaddr = tp->mmio_addr;
4658
4659         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4660                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4661
4662         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4663                 RTL_R32(CSIDR) : ~0;
4664 }
4665
4666 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4667 {
4668         struct csi_ops *ops = &tp->csi_ops;
4669
4670         switch (tp->mac_version) {
4671         case RTL_GIGA_MAC_VER_01:
4672         case RTL_GIGA_MAC_VER_02:
4673         case RTL_GIGA_MAC_VER_03:
4674         case RTL_GIGA_MAC_VER_04:
4675         case RTL_GIGA_MAC_VER_05:
4676         case RTL_GIGA_MAC_VER_06:
4677         case RTL_GIGA_MAC_VER_10:
4678         case RTL_GIGA_MAC_VER_11:
4679         case RTL_GIGA_MAC_VER_12:
4680         case RTL_GIGA_MAC_VER_13:
4681         case RTL_GIGA_MAC_VER_14:
4682         case RTL_GIGA_MAC_VER_15:
4683         case RTL_GIGA_MAC_VER_16:
4684         case RTL_GIGA_MAC_VER_17:
4685                 ops->write      = NULL;
4686                 ops->read       = NULL;
4687                 break;
4688
4689         case RTL_GIGA_MAC_VER_37:
4690         case RTL_GIGA_MAC_VER_38:
4691                 ops->write      = r8402_csi_write;
4692                 ops->read       = r8402_csi_read;
4693                 break;
4694
4695         default:
4696                 ops->write      = r8169_csi_write;
4697                 ops->read       = r8169_csi_read;
4698                 break;
4699         }
4700 }
4701
4702 struct ephy_info {
4703         unsigned int offset;
4704         u16 mask;
4705         u16 bits;
4706 };
4707
4708 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4709                           int len)
4710 {
4711         u16 w;
4712
4713         while (len-- > 0) {
4714                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4715                 rtl_ephy_write(tp, e->offset, w);
4716                 e++;
4717         }
4718 }
4719
4720 static void rtl_disable_clock_request(struct pci_dev *pdev)
4721 {
4722         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4723                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4724 }
4725
4726 static void rtl_enable_clock_request(struct pci_dev *pdev)
4727 {
4728         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4729                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4730 }
4731
4732 #define R8168_CPCMD_QUIRK_MASK (\
4733         EnableBist | \
4734         Mac_dbgo_oe | \
4735         Force_half_dup | \
4736         Force_rxflow_en | \
4737         Force_txflow_en | \
4738         Cxpl_dbg_sel | \
4739         ASF | \
4740         PktCntrDisable | \
4741         Mac_dbgo_sel)
4742
4743 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4744 {
4745         void __iomem *ioaddr = tp->mmio_addr;
4746         struct pci_dev *pdev = tp->pci_dev;
4747
4748         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4749
4750         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4751
4752         if (tp->dev->mtu <= ETH_DATA_LEN) {
4753                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4754                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4755         }
4756 }
4757
4758 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4759 {
4760         void __iomem *ioaddr = tp->mmio_addr;
4761
4762         rtl_hw_start_8168bb(tp);
4763
4764         RTL_W8(MaxTxPacketSize, TxPacketMax);
4765
4766         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4767 }
4768
4769 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4770 {
4771         void __iomem *ioaddr = tp->mmio_addr;
4772         struct pci_dev *pdev = tp->pci_dev;
4773
4774         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4775
4776         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4777
4778         if (tp->dev->mtu <= ETH_DATA_LEN)
4779                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4780
4781         rtl_disable_clock_request(pdev);
4782
4783         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4784 }
4785
4786 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4787 {
4788         static const struct ephy_info e_info_8168cp[] = {
4789                 { 0x01, 0,      0x0001 },
4790                 { 0x02, 0x0800, 0x1000 },
4791                 { 0x03, 0,      0x0042 },
4792                 { 0x06, 0x0080, 0x0000 },
4793                 { 0x07, 0,      0x2000 }
4794         };
4795
4796         rtl_csi_access_enable_2(tp);
4797
4798         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4799
4800         __rtl_hw_start_8168cp(tp);
4801 }
4802
4803 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4804 {
4805         void __iomem *ioaddr = tp->mmio_addr;
4806         struct pci_dev *pdev = tp->pci_dev;
4807
4808         rtl_csi_access_enable_2(tp);
4809
4810         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4811
4812         if (tp->dev->mtu <= ETH_DATA_LEN)
4813                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4814
4815         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4816 }
4817
4818 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4819 {
4820         void __iomem *ioaddr = tp->mmio_addr;
4821         struct pci_dev *pdev = tp->pci_dev;
4822
4823         rtl_csi_access_enable_2(tp);
4824
4825         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4826
4827         /* Magic. */
4828         RTL_W8(DBG_REG, 0x20);
4829
4830         RTL_W8(MaxTxPacketSize, TxPacketMax);
4831
4832         if (tp->dev->mtu <= ETH_DATA_LEN)
4833                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4834
4835         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4836 }
4837
4838 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4839 {
4840         void __iomem *ioaddr = tp->mmio_addr;
4841         static const struct ephy_info e_info_8168c_1[] = {
4842                 { 0x02, 0x0800, 0x1000 },
4843                 { 0x03, 0,      0x0002 },
4844                 { 0x06, 0x0080, 0x0000 }
4845         };
4846
4847         rtl_csi_access_enable_2(tp);
4848
4849         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4850
4851         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4852
4853         __rtl_hw_start_8168cp(tp);
4854 }
4855
4856 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4857 {
4858         static const struct ephy_info e_info_8168c_2[] = {
4859                 { 0x01, 0,      0x0001 },
4860                 { 0x03, 0x0400, 0x0220 }
4861         };
4862
4863         rtl_csi_access_enable_2(tp);
4864
4865         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4866
4867         __rtl_hw_start_8168cp(tp);
4868 }
4869
4870 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4871 {
4872         rtl_hw_start_8168c_2(tp);
4873 }
4874
4875 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4876 {
4877         rtl_csi_access_enable_2(tp);
4878
4879         __rtl_hw_start_8168cp(tp);
4880 }
4881
4882 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4883 {
4884         void __iomem *ioaddr = tp->mmio_addr;
4885         struct pci_dev *pdev = tp->pci_dev;
4886
4887         rtl_csi_access_enable_2(tp);
4888
4889         rtl_disable_clock_request(pdev);
4890
4891         RTL_W8(MaxTxPacketSize, TxPacketMax);
4892
4893         if (tp->dev->mtu <= ETH_DATA_LEN)
4894                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4895
4896         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4897 }
4898
4899 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4900 {
4901         void __iomem *ioaddr = tp->mmio_addr;
4902         struct pci_dev *pdev = tp->pci_dev;
4903
4904         rtl_csi_access_enable_1(tp);
4905
4906         if (tp->dev->mtu <= ETH_DATA_LEN)
4907                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4908
4909         RTL_W8(MaxTxPacketSize, TxPacketMax);
4910
4911         rtl_disable_clock_request(pdev);
4912 }
4913
4914 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4915 {
4916         void __iomem *ioaddr = tp->mmio_addr;
4917         struct pci_dev *pdev = tp->pci_dev;
4918         static const struct ephy_info e_info_8168d_4[] = {
4919                 { 0x0b, ~0,     0x48 },
4920                 { 0x19, 0x20,   0x50 },
4921                 { 0x0c, ~0,     0x20 }
4922         };
4923         int i;
4924
4925         rtl_csi_access_enable_1(tp);
4926
4927         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4928
4929         RTL_W8(MaxTxPacketSize, TxPacketMax);
4930
4931         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4932                 const struct ephy_info *e = e_info_8168d_4 + i;
4933                 u16 w;
4934
4935                 w = rtl_ephy_read(tp, e->offset);
4936                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
4937         }
4938
4939         rtl_enable_clock_request(pdev);
4940 }
4941
4942 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4943 {
4944         void __iomem *ioaddr = tp->mmio_addr;
4945         struct pci_dev *pdev = tp->pci_dev;
4946         static const struct ephy_info e_info_8168e_1[] = {
4947                 { 0x00, 0x0200, 0x0100 },
4948                 { 0x00, 0x0000, 0x0004 },
4949                 { 0x06, 0x0002, 0x0001 },
4950                 { 0x06, 0x0000, 0x0030 },
4951                 { 0x07, 0x0000, 0x2000 },
4952                 { 0x00, 0x0000, 0x0020 },
4953                 { 0x03, 0x5800, 0x2000 },
4954                 { 0x03, 0x0000, 0x0001 },
4955                 { 0x01, 0x0800, 0x1000 },
4956                 { 0x07, 0x0000, 0x4000 },
4957                 { 0x1e, 0x0000, 0x2000 },
4958                 { 0x19, 0xffff, 0xfe6c },
4959                 { 0x0a, 0x0000, 0x0040 }
4960         };
4961
4962         rtl_csi_access_enable_2(tp);
4963
4964         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4965
4966         if (tp->dev->mtu <= ETH_DATA_LEN)
4967                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4968
4969         RTL_W8(MaxTxPacketSize, TxPacketMax);
4970
4971         rtl_disable_clock_request(pdev);
4972
4973         /* Reset tx FIFO pointer */
4974         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4975         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4976
4977         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4978 }
4979
4980 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4981 {
4982         void __iomem *ioaddr = tp->mmio_addr;
4983         struct pci_dev *pdev = tp->pci_dev;
4984         static const struct ephy_info e_info_8168e_2[] = {
4985                 { 0x09, 0x0000, 0x0080 },
4986                 { 0x19, 0x0000, 0x0224 }
4987         };
4988
4989         rtl_csi_access_enable_1(tp);
4990
4991         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4992
4993         if (tp->dev->mtu <= ETH_DATA_LEN)
4994                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4995
4996         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4997         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4998         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4999         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5000         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5001         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5002         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5003         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5004
5005         RTL_W8(MaxTxPacketSize, EarlySize);
5006
5007         rtl_disable_clock_request(pdev);
5008
5009         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5010         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5011
5012         /* Adjust EEE LED frequency */
5013         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5014
5015         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5016         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5017         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5018 }
5019
5020 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5021 {
5022         void __iomem *ioaddr = tp->mmio_addr;
5023         struct pci_dev *pdev = tp->pci_dev;
5024
5025         rtl_csi_access_enable_2(tp);
5026
5027         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5028
5029         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5030         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5031         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5032         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5033         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5034         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5035         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5036         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5037         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5038         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5039
5040         RTL_W8(MaxTxPacketSize, EarlySize);
5041
5042         rtl_disable_clock_request(pdev);
5043
5044         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5045         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5046         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5047         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5048         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5049 }
5050
5051 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5052 {
5053         void __iomem *ioaddr = tp->mmio_addr;
5054         static const struct ephy_info e_info_8168f_1[] = {
5055                 { 0x06, 0x00c0, 0x0020 },
5056                 { 0x08, 0x0001, 0x0002 },
5057                 { 0x09, 0x0000, 0x0080 },
5058                 { 0x19, 0x0000, 0x0224 }
5059         };
5060
5061         rtl_hw_start_8168f(tp);
5062
5063         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5064
5065         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5066
5067         /* Adjust EEE LED frequency */
5068         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5069 }
5070
5071 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5072 {
5073         static const struct ephy_info e_info_8168f_1[] = {
5074                 { 0x06, 0x00c0, 0x0020 },
5075                 { 0x0f, 0xffff, 0x5200 },
5076                 { 0x1e, 0x0000, 0x4000 },
5077                 { 0x19, 0x0000, 0x0224 }
5078         };
5079
5080         rtl_hw_start_8168f(tp);
5081
5082         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5083
5084         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5085 }
5086
5087 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5088 {
5089         void __iomem *ioaddr = tp->mmio_addr;
5090         struct pci_dev *pdev = tp->pci_dev;
5091
5092         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5093         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5094         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5095         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5096
5097         rtl_csi_access_enable_1(tp);
5098
5099         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5100
5101         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5102         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5103
5104         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5105         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5106         RTL_W8(MaxTxPacketSize, EarlySize);
5107
5108         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5109         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5110
5111         /* Adjust EEE LED frequency */
5112         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5113
5114         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5115 }
5116
5117 static void rtl_hw_start_8168(struct net_device *dev)
5118 {
5119         struct rtl8169_private *tp = netdev_priv(dev);
5120         void __iomem *ioaddr = tp->mmio_addr;
5121
5122         RTL_W8(Cfg9346, Cfg9346_Unlock);
5123
5124         RTL_W8(MaxTxPacketSize, TxPacketMax);
5125
5126         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5127
5128         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5129
5130         RTL_W16(CPlusCmd, tp->cp_cmd);
5131
5132         RTL_W16(IntrMitigate, 0x5151);
5133
5134         /* Work around for RxFIFO overflow. */
5135         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5136                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5137                 tp->event_slow &= ~RxOverflow;
5138         }
5139
5140         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5141
5142         rtl_set_rx_mode(dev);
5143
5144         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5145                 (InterFrameGap << TxInterFrameGapShift));
5146
5147         RTL_R8(IntrMask);
5148
5149         switch (tp->mac_version) {
5150         case RTL_GIGA_MAC_VER_11:
5151                 rtl_hw_start_8168bb(tp);
5152                 break;
5153
5154         case RTL_GIGA_MAC_VER_12:
5155         case RTL_GIGA_MAC_VER_17:
5156                 rtl_hw_start_8168bef(tp);
5157                 break;
5158
5159         case RTL_GIGA_MAC_VER_18:
5160                 rtl_hw_start_8168cp_1(tp);
5161                 break;
5162
5163         case RTL_GIGA_MAC_VER_19:
5164                 rtl_hw_start_8168c_1(tp);
5165                 break;
5166
5167         case RTL_GIGA_MAC_VER_20:
5168                 rtl_hw_start_8168c_2(tp);
5169                 break;
5170
5171         case RTL_GIGA_MAC_VER_21:
5172                 rtl_hw_start_8168c_3(tp);
5173                 break;
5174
5175         case RTL_GIGA_MAC_VER_22:
5176                 rtl_hw_start_8168c_4(tp);
5177                 break;
5178
5179         case RTL_GIGA_MAC_VER_23:
5180                 rtl_hw_start_8168cp_2(tp);
5181                 break;
5182
5183         case RTL_GIGA_MAC_VER_24:
5184                 rtl_hw_start_8168cp_3(tp);
5185                 break;
5186
5187         case RTL_GIGA_MAC_VER_25:
5188         case RTL_GIGA_MAC_VER_26:
5189         case RTL_GIGA_MAC_VER_27:
5190                 rtl_hw_start_8168d(tp);
5191                 break;
5192
5193         case RTL_GIGA_MAC_VER_28:
5194                 rtl_hw_start_8168d_4(tp);
5195                 break;
5196
5197         case RTL_GIGA_MAC_VER_31:
5198                 rtl_hw_start_8168dp(tp);
5199                 break;
5200
5201         case RTL_GIGA_MAC_VER_32:
5202         case RTL_GIGA_MAC_VER_33:
5203                 rtl_hw_start_8168e_1(tp);
5204                 break;
5205         case RTL_GIGA_MAC_VER_34:
5206                 rtl_hw_start_8168e_2(tp);
5207                 break;
5208
5209         case RTL_GIGA_MAC_VER_35:
5210         case RTL_GIGA_MAC_VER_36:
5211                 rtl_hw_start_8168f_1(tp);
5212                 break;
5213
5214         case RTL_GIGA_MAC_VER_38:
5215                 rtl_hw_start_8411(tp);
5216                 break;
5217
5218         case RTL_GIGA_MAC_VER_40:
5219         case RTL_GIGA_MAC_VER_41:
5220                 rtl_hw_start_8168g_1(tp);
5221                 break;
5222
5223         default:
5224                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5225                         dev->name, tp->mac_version);
5226                 break;
5227         }
5228
5229         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5230
5231         RTL_W8(Cfg9346, Cfg9346_Lock);
5232
5233         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5234 }
5235
5236 #define R810X_CPCMD_QUIRK_MASK (\
5237         EnableBist | \
5238         Mac_dbgo_oe | \
5239         Force_half_dup | \
5240         Force_rxflow_en | \
5241         Force_txflow_en | \
5242         Cxpl_dbg_sel | \
5243         ASF | \
5244         PktCntrDisable | \
5245         Mac_dbgo_sel)
5246
5247 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5248 {
5249         void __iomem *ioaddr = tp->mmio_addr;
5250         struct pci_dev *pdev = tp->pci_dev;
5251         static const struct ephy_info e_info_8102e_1[] = {
5252                 { 0x01, 0, 0x6e65 },
5253                 { 0x02, 0, 0x091f },
5254                 { 0x03, 0, 0xc2f9 },
5255                 { 0x06, 0, 0xafb5 },
5256                 { 0x07, 0, 0x0e00 },
5257                 { 0x19, 0, 0xec80 },
5258                 { 0x01, 0, 0x2e65 },
5259                 { 0x01, 0, 0x6e65 }
5260         };
5261         u8 cfg1;
5262
5263         rtl_csi_access_enable_2(tp);
5264
5265         RTL_W8(DBG_REG, FIX_NAK_1);
5266
5267         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5268
5269         RTL_W8(Config1,
5270                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5271         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5272
5273         cfg1 = RTL_R8(Config1);
5274         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5275                 RTL_W8(Config1, cfg1 & ~LEDS0);
5276
5277         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5278 }
5279
5280 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5281 {
5282         void __iomem *ioaddr = tp->mmio_addr;
5283         struct pci_dev *pdev = tp->pci_dev;
5284
5285         rtl_csi_access_enable_2(tp);
5286
5287         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5288
5289         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5290         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5291 }
5292
5293 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5294 {
5295         rtl_hw_start_8102e_2(tp);
5296
5297         rtl_ephy_write(tp, 0x03, 0xc2f9);
5298 }
5299
5300 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5301 {
5302         void __iomem *ioaddr = tp->mmio_addr;
5303         static const struct ephy_info e_info_8105e_1[] = {
5304                 { 0x07, 0, 0x4000 },
5305                 { 0x19, 0, 0x0200 },
5306                 { 0x19, 0, 0x0020 },
5307                 { 0x1e, 0, 0x2000 },
5308                 { 0x03, 0, 0x0001 },
5309                 { 0x19, 0, 0x0100 },
5310                 { 0x19, 0, 0x0004 },
5311                 { 0x0a, 0, 0x0020 }
5312         };
5313
5314         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5315         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5316
5317         /* Disable Early Tally Counter */
5318         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5319
5320         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5321         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5322
5323         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5324 }
5325
5326 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5327 {
5328         rtl_hw_start_8105e_1(tp);
5329         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5330 }
5331
5332 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5333 {
5334         void __iomem *ioaddr = tp->mmio_addr;
5335         static const struct ephy_info e_info_8402[] = {
5336                 { 0x19, 0xffff, 0xff64 },
5337                 { 0x1e, 0, 0x4000 }
5338         };
5339
5340         rtl_csi_access_enable_2(tp);
5341
5342         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5343         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5344
5345         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5346         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5347
5348         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5349
5350         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5351
5352         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5353         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5354         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5355         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5356         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5357         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5358         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5359 }
5360
5361 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5362 {
5363         void __iomem *ioaddr = tp->mmio_addr;
5364
5365         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5366         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5367
5368         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5369         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5370         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5371 }
5372
5373 static void rtl_hw_start_8101(struct net_device *dev)
5374 {
5375         struct rtl8169_private *tp = netdev_priv(dev);
5376         void __iomem *ioaddr = tp->mmio_addr;
5377         struct pci_dev *pdev = tp->pci_dev;
5378
5379         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5380                 tp->event_slow &= ~RxFIFOOver;
5381
5382         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5383             tp->mac_version == RTL_GIGA_MAC_VER_16)
5384                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5385                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5386
5387         RTL_W8(Cfg9346, Cfg9346_Unlock);
5388
5389         switch (tp->mac_version) {
5390         case RTL_GIGA_MAC_VER_07:
5391                 rtl_hw_start_8102e_1(tp);
5392                 break;
5393
5394         case RTL_GIGA_MAC_VER_08:
5395                 rtl_hw_start_8102e_3(tp);
5396                 break;
5397
5398         case RTL_GIGA_MAC_VER_09:
5399                 rtl_hw_start_8102e_2(tp);
5400                 break;
5401
5402         case RTL_GIGA_MAC_VER_29:
5403                 rtl_hw_start_8105e_1(tp);
5404                 break;
5405         case RTL_GIGA_MAC_VER_30:
5406                 rtl_hw_start_8105e_2(tp);
5407                 break;
5408
5409         case RTL_GIGA_MAC_VER_37:
5410                 rtl_hw_start_8402(tp);
5411                 break;
5412
5413         case RTL_GIGA_MAC_VER_39:
5414                 rtl_hw_start_8106(tp);
5415                 break;
5416         }
5417
5418         RTL_W8(Cfg9346, Cfg9346_Lock);
5419
5420         RTL_W8(MaxTxPacketSize, TxPacketMax);
5421
5422         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5423
5424         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5425         RTL_W16(CPlusCmd, tp->cp_cmd);
5426
5427         RTL_W16(IntrMitigate, 0x0000);
5428
5429         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5430
5431         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5432         rtl_set_rx_tx_config_registers(tp);
5433
5434         RTL_R8(IntrMask);
5435
5436         rtl_set_rx_mode(dev);
5437
5438         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5439 }
5440
5441 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5442 {
5443         struct rtl8169_private *tp = netdev_priv(dev);
5444
5445         if (new_mtu < ETH_ZLEN ||
5446             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5447                 return -EINVAL;
5448
5449         if (new_mtu > ETH_DATA_LEN)
5450                 rtl_hw_jumbo_enable(tp);
5451         else
5452                 rtl_hw_jumbo_disable(tp);
5453
5454         dev->mtu = new_mtu;
5455         netdev_update_features(dev);
5456
5457         return 0;
5458 }
5459
5460 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5461 {
5462         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5463         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5464 }
5465
5466 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5467                                      void **data_buff, struct RxDesc *desc)
5468 {
5469         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5470                          DMA_FROM_DEVICE);
5471
5472         kfree(*data_buff);
5473         *data_buff = NULL;
5474         rtl8169_make_unusable_by_asic(desc);
5475 }
5476
5477 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5478 {
5479         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5480
5481         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5482 }
5483
5484 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5485                                        u32 rx_buf_sz)
5486 {
5487         desc->addr = cpu_to_le64(mapping);
5488         wmb();
5489         rtl8169_mark_to_asic(desc, rx_buf_sz);
5490 }
5491
5492 static inline void *rtl8169_align(void *data)
5493 {
5494         return (void *)ALIGN((long)data, 16);
5495 }
5496
5497 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5498                                              struct RxDesc *desc)
5499 {
5500         void *data;
5501         dma_addr_t mapping;
5502         struct device *d = &tp->pci_dev->dev;
5503         struct net_device *dev = tp->dev;
5504         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5505
5506         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5507         if (!data)
5508                 return NULL;
5509
5510         if (rtl8169_align(data) != data) {
5511                 kfree(data);
5512                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5513                 if (!data)
5514                         return NULL;
5515         }
5516
5517         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5518                                  DMA_FROM_DEVICE);
5519         if (unlikely(dma_mapping_error(d, mapping))) {
5520                 if (net_ratelimit())
5521                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5522                 goto err_out;
5523         }
5524
5525         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5526         return data;
5527
5528 err_out:
5529         kfree(data);
5530         return NULL;
5531 }
5532
5533 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5534 {
5535         unsigned int i;
5536
5537         for (i = 0; i < NUM_RX_DESC; i++) {
5538                 if (tp->Rx_databuff[i]) {
5539                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5540                                             tp->RxDescArray + i);
5541                 }
5542         }
5543 }
5544
5545 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5546 {
5547         desc->opts1 |= cpu_to_le32(RingEnd);
5548 }
5549
5550 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5551 {
5552         unsigned int i;
5553
5554         for (i = 0; i < NUM_RX_DESC; i++) {
5555                 void *data;
5556
5557                 if (tp->Rx_databuff[i])
5558                         continue;
5559
5560                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5561                 if (!data) {
5562                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5563                         goto err_out;
5564                 }
5565                 tp->Rx_databuff[i] = data;
5566         }
5567
5568         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5569         return 0;
5570
5571 err_out:
5572         rtl8169_rx_clear(tp);
5573         return -ENOMEM;
5574 }
5575
5576 static int rtl8169_init_ring(struct net_device *dev)
5577 {
5578         struct rtl8169_private *tp = netdev_priv(dev);
5579
5580         rtl8169_init_ring_indexes(tp);
5581
5582         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5583         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5584
5585         return rtl8169_rx_fill(tp);
5586 }
5587
5588 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5589                                  struct TxDesc *desc)
5590 {
5591         unsigned int len = tx_skb->len;
5592
5593         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5594
5595         desc->opts1 = 0x00;
5596         desc->opts2 = 0x00;
5597         desc->addr = 0x00;
5598         tx_skb->len = 0;
5599 }
5600
5601 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5602                                    unsigned int n)
5603 {
5604         unsigned int i;
5605
5606         for (i = 0; i < n; i++) {
5607                 unsigned int entry = (start + i) % NUM_TX_DESC;
5608                 struct ring_info *tx_skb = tp->tx_skb + entry;
5609                 unsigned int len = tx_skb->len;
5610
5611                 if (len) {
5612                         struct sk_buff *skb = tx_skb->skb;
5613
5614                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5615                                              tp->TxDescArray + entry);
5616                         if (skb) {
5617                                 tp->dev->stats.tx_dropped++;
5618                                 dev_kfree_skb(skb);
5619                                 tx_skb->skb = NULL;
5620                         }
5621                 }
5622         }
5623 }
5624
5625 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5626 {
5627         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5628         tp->cur_tx = tp->dirty_tx = 0;
5629 }
5630
5631 static void rtl_reset_work(struct rtl8169_private *tp)
5632 {
5633         struct net_device *dev = tp->dev;
5634         int i;
5635
5636         napi_disable(&tp->napi);
5637         netif_stop_queue(dev);
5638         synchronize_sched();
5639
5640         rtl8169_hw_reset(tp);
5641
5642         for (i = 0; i < NUM_RX_DESC; i++)
5643                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5644
5645         rtl8169_tx_clear(tp);
5646         rtl8169_init_ring_indexes(tp);
5647
5648         napi_enable(&tp->napi);
5649         rtl_hw_start(dev);
5650         netif_wake_queue(dev);
5651         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5652 }
5653
5654 static void rtl8169_tx_timeout(struct net_device *dev)
5655 {
5656         struct rtl8169_private *tp = netdev_priv(dev);
5657
5658         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5659 }
5660
5661 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5662                               u32 *opts)
5663 {
5664         struct skb_shared_info *info = skb_shinfo(skb);
5665         unsigned int cur_frag, entry;
5666         struct TxDesc * uninitialized_var(txd);
5667         struct device *d = &tp->pci_dev->dev;
5668
5669         entry = tp->cur_tx;
5670         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5671                 const skb_frag_t *frag = info->frags + cur_frag;
5672                 dma_addr_t mapping;
5673                 u32 status, len;
5674                 void *addr;
5675
5676                 entry = (entry + 1) % NUM_TX_DESC;
5677
5678                 txd = tp->TxDescArray + entry;
5679                 len = skb_frag_size(frag);
5680                 addr = skb_frag_address(frag);
5681                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5682                 if (unlikely(dma_mapping_error(d, mapping))) {
5683                         if (net_ratelimit())
5684                                 netif_err(tp, drv, tp->dev,
5685                                           "Failed to map TX fragments DMA!\n");
5686                         goto err_out;
5687                 }
5688
5689                 /* Anti gcc 2.95.3 bugware (sic) */
5690                 status = opts[0] | len |
5691                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5692
5693                 txd->opts1 = cpu_to_le32(status);
5694                 txd->opts2 = cpu_to_le32(opts[1]);
5695                 txd->addr = cpu_to_le64(mapping);
5696
5697                 tp->tx_skb[entry].len = len;
5698         }
5699
5700         if (cur_frag) {
5701                 tp->tx_skb[entry].skb = skb;
5702                 txd->opts1 |= cpu_to_le32(LastFrag);
5703         }
5704
5705         return cur_frag;
5706
5707 err_out:
5708         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5709         return -EIO;
5710 }
5711
5712 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5713                                     struct sk_buff *skb, u32 *opts)
5714 {
5715         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5716         u32 mss = skb_shinfo(skb)->gso_size;
5717         int offset = info->opts_offset;
5718
5719         if (mss) {
5720                 opts[0] |= TD_LSO;
5721                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5722         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5723                 const struct iphdr *ip = ip_hdr(skb);
5724
5725                 if (ip->protocol == IPPROTO_TCP)
5726                         opts[offset] |= info->checksum.tcp;
5727                 else if (ip->protocol == IPPROTO_UDP)
5728                         opts[offset] |= info->checksum.udp;
5729                 else
5730                         WARN_ON_ONCE(1);
5731         }
5732 }
5733
5734 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5735                                       struct net_device *dev)
5736 {
5737         struct rtl8169_private *tp = netdev_priv(dev);
5738         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5739         struct TxDesc *txd = tp->TxDescArray + entry;
5740         void __iomem *ioaddr = tp->mmio_addr;
5741         struct device *d = &tp->pci_dev->dev;
5742         dma_addr_t mapping;
5743         u32 status, len;
5744         u32 opts[2];
5745         int frags;
5746
5747         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5748                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5749                 goto err_stop_0;
5750         }
5751
5752         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5753                 goto err_stop_0;
5754
5755         len = skb_headlen(skb);
5756         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5757         if (unlikely(dma_mapping_error(d, mapping))) {
5758                 if (net_ratelimit())
5759                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5760                 goto err_dma_0;
5761         }
5762
5763         tp->tx_skb[entry].len = len;
5764         txd->addr = cpu_to_le64(mapping);
5765
5766         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5767         opts[0] = DescOwn;
5768
5769         rtl8169_tso_csum(tp, skb, opts);
5770
5771         frags = rtl8169_xmit_frags(tp, skb, opts);
5772         if (frags < 0)
5773                 goto err_dma_1;
5774         else if (frags)
5775                 opts[0] |= FirstFrag;
5776         else {
5777                 opts[0] |= FirstFrag | LastFrag;
5778                 tp->tx_skb[entry].skb = skb;
5779         }
5780
5781         txd->opts2 = cpu_to_le32(opts[1]);
5782
5783         skb_tx_timestamp(skb);
5784
5785         wmb();
5786
5787         /* Anti gcc 2.95.3 bugware (sic) */
5788         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5789         txd->opts1 = cpu_to_le32(status);
5790
5791         tp->cur_tx += frags + 1;
5792
5793         wmb();
5794
5795         RTL_W8(TxPoll, NPQ);
5796
5797         mmiowb();
5798
5799         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5800                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5801                  * not miss a ring update when it notices a stopped queue.
5802                  */
5803                 smp_wmb();
5804                 netif_stop_queue(dev);
5805                 /* Sync with rtl_tx:
5806                  * - publish queue status and cur_tx ring index (write barrier)
5807                  * - refresh dirty_tx ring index (read barrier).
5808                  * May the current thread have a pessimistic view of the ring
5809                  * status and forget to wake up queue, a racing rtl_tx thread
5810                  * can't.
5811                  */
5812                 smp_mb();
5813                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5814                         netif_wake_queue(dev);
5815         }
5816
5817         return NETDEV_TX_OK;
5818
5819 err_dma_1:
5820         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5821 err_dma_0:
5822         dev_kfree_skb(skb);
5823         dev->stats.tx_dropped++;
5824         return NETDEV_TX_OK;
5825
5826 err_stop_0:
5827         netif_stop_queue(dev);
5828         dev->stats.tx_dropped++;
5829         return NETDEV_TX_BUSY;
5830 }
5831
5832 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5833 {
5834         struct rtl8169_private *tp = netdev_priv(dev);
5835         struct pci_dev *pdev = tp->pci_dev;
5836         u16 pci_status, pci_cmd;
5837
5838         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5839         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5840
5841         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5842                   pci_cmd, pci_status);
5843
5844         /*
5845          * The recovery sequence below admits a very elaborated explanation:
5846          * - it seems to work;
5847          * - I did not see what else could be done;
5848          * - it makes iop3xx happy.
5849          *
5850          * Feel free to adjust to your needs.
5851          */
5852         if (pdev->broken_parity_status)
5853                 pci_cmd &= ~PCI_COMMAND_PARITY;
5854         else
5855                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5856
5857         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5858
5859         pci_write_config_word(pdev, PCI_STATUS,
5860                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5861                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5862                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5863
5864         /* The infamous DAC f*ckup only happens at boot time */
5865         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
5866                 void __iomem *ioaddr = tp->mmio_addr;
5867
5868                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5869                 tp->cp_cmd &= ~PCIDAC;
5870                 RTL_W16(CPlusCmd, tp->cp_cmd);
5871                 dev->features &= ~NETIF_F_HIGHDMA;
5872         }
5873
5874         rtl8169_hw_reset(tp);
5875
5876         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5877 }
5878
5879 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5880 {
5881         unsigned int dirty_tx, tx_left;
5882
5883         dirty_tx = tp->dirty_tx;
5884         smp_rmb();
5885         tx_left = tp->cur_tx - dirty_tx;
5886
5887         while (tx_left > 0) {
5888                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5889                 struct ring_info *tx_skb = tp->tx_skb + entry;
5890                 u32 status;
5891
5892                 rmb();
5893                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5894                 if (status & DescOwn)
5895                         break;
5896
5897                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5898                                      tp->TxDescArray + entry);
5899                 if (status & LastFrag) {
5900                         u64_stats_update_begin(&tp->tx_stats.syncp);
5901                         tp->tx_stats.packets++;
5902                         tp->tx_stats.bytes += tx_skb->skb->len;
5903                         u64_stats_update_end(&tp->tx_stats.syncp);
5904                         dev_kfree_skb(tx_skb->skb);
5905                         tx_skb->skb = NULL;
5906                 }
5907                 dirty_tx++;
5908                 tx_left--;
5909         }
5910
5911         if (tp->dirty_tx != dirty_tx) {
5912                 tp->dirty_tx = dirty_tx;
5913                 /* Sync with rtl8169_start_xmit:
5914                  * - publish dirty_tx ring index (write barrier)
5915                  * - refresh cur_tx ring index and queue status (read barrier)
5916                  * May the current thread miss the stopped queue condition,
5917                  * a racing xmit thread can only have a right view of the
5918                  * ring status.
5919                  */
5920                 smp_mb();
5921                 if (netif_queue_stopped(dev) &&
5922                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5923                         netif_wake_queue(dev);
5924                 }
5925                 /*
5926                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5927                  * too close. Let's kick an extra TxPoll request when a burst
5928                  * of start_xmit activity is detected (if it is not detected,
5929                  * it is slow enough). -- FR
5930                  */
5931                 if (tp->cur_tx != dirty_tx) {
5932                         void __iomem *ioaddr = tp->mmio_addr;
5933
5934                         RTL_W8(TxPoll, NPQ);
5935                 }
5936         }
5937 }
5938
5939 static inline int rtl8169_fragmented_frame(u32 status)
5940 {
5941         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5942 }
5943
5944 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5945 {
5946         u32 status = opts1 & RxProtoMask;
5947
5948         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5949             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5950                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5951         else
5952                 skb_checksum_none_assert(skb);
5953 }
5954
5955 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5956                                            struct rtl8169_private *tp,
5957                                            int pkt_size,
5958                                            dma_addr_t addr)
5959 {
5960         struct sk_buff *skb;
5961         struct device *d = &tp->pci_dev->dev;
5962
5963         data = rtl8169_align(data);
5964         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5965         prefetch(data);
5966         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5967         if (skb)
5968                 memcpy(skb->data, data, pkt_size);
5969         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5970
5971         return skb;
5972 }
5973
5974 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5975 {
5976         unsigned int cur_rx, rx_left;
5977         unsigned int count;
5978
5979         cur_rx = tp->cur_rx;
5980
5981         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5982                 unsigned int entry = cur_rx % NUM_RX_DESC;
5983                 struct RxDesc *desc = tp->RxDescArray + entry;
5984                 u32 status;
5985
5986                 rmb();
5987                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5988
5989                 if (status & DescOwn)
5990                         break;
5991                 if (unlikely(status & RxRES)) {
5992                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5993                                    status);
5994                         dev->stats.rx_errors++;
5995                         if (status & (RxRWT | RxRUNT))
5996                                 dev->stats.rx_length_errors++;
5997                         if (status & RxCRC)
5998                                 dev->stats.rx_crc_errors++;
5999                         if (status & RxFOVF) {
6000                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6001                                 dev->stats.rx_fifo_errors++;
6002                         }
6003                         if ((status & (RxRUNT | RxCRC)) &&
6004                             !(status & (RxRWT | RxFOVF)) &&
6005                             (dev->features & NETIF_F_RXALL))
6006                                 goto process_pkt;
6007                 } else {
6008                         struct sk_buff *skb;
6009                         dma_addr_t addr;
6010                         int pkt_size;
6011
6012 process_pkt:
6013                         addr = le64_to_cpu(desc->addr);
6014                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6015                                 pkt_size = (status & 0x00003fff) - 4;
6016                         else
6017                                 pkt_size = status & 0x00003fff;
6018
6019                         /*
6020                          * The driver does not support incoming fragmented
6021                          * frames. They are seen as a symptom of over-mtu
6022                          * sized frames.
6023                          */
6024                         if (unlikely(rtl8169_fragmented_frame(status))) {
6025                                 dev->stats.rx_dropped++;
6026                                 dev->stats.rx_length_errors++;
6027                                 goto release_descriptor;
6028                         }
6029
6030                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6031                                                   tp, pkt_size, addr);
6032                         if (!skb) {
6033                                 dev->stats.rx_dropped++;
6034                                 goto release_descriptor;
6035                         }
6036
6037                         rtl8169_rx_csum(skb, status);
6038                         skb_put(skb, pkt_size);
6039                         skb->protocol = eth_type_trans(skb, dev);
6040
6041                         rtl8169_rx_vlan_tag(desc, skb);
6042
6043                         napi_gro_receive(&tp->napi, skb);
6044
6045                         u64_stats_update_begin(&tp->rx_stats.syncp);
6046                         tp->rx_stats.packets++;
6047                         tp->rx_stats.bytes += pkt_size;
6048                         u64_stats_update_end(&tp->rx_stats.syncp);
6049                 }
6050 release_descriptor:
6051                 desc->opts2 = 0;
6052                 wmb();
6053                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6054         }
6055
6056         count = cur_rx - tp->cur_rx;
6057         tp->cur_rx = cur_rx;
6058
6059         return count;
6060 }
6061
6062 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6063 {
6064         struct net_device *dev = dev_instance;
6065         struct rtl8169_private *tp = netdev_priv(dev);
6066         int handled = 0;
6067         u16 status;
6068
6069         status = rtl_get_events(tp);
6070         if (status && status != 0xffff) {
6071                 status &= RTL_EVENT_NAPI | tp->event_slow;
6072                 if (status) {
6073                         handled = 1;
6074
6075                         rtl_irq_disable(tp);
6076                         napi_schedule(&tp->napi);
6077                 }
6078         }
6079         return IRQ_RETVAL(handled);
6080 }
6081
6082 /*
6083  * Workqueue context.
6084  */
6085 static void rtl_slow_event_work(struct rtl8169_private *tp)
6086 {
6087         struct net_device *dev = tp->dev;
6088         u16 status;
6089
6090         status = rtl_get_events(tp) & tp->event_slow;
6091         rtl_ack_events(tp, status);
6092
6093         if (unlikely(status & RxFIFOOver)) {
6094                 switch (tp->mac_version) {
6095                 /* Work around for rx fifo overflow */
6096                 case RTL_GIGA_MAC_VER_11:
6097                         netif_stop_queue(dev);
6098                         /* XXX - Hack alert. See rtl_task(). */
6099                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6100                 default:
6101                         break;
6102                 }
6103         }
6104
6105         if (unlikely(status & SYSErr))
6106                 rtl8169_pcierr_interrupt(dev);
6107
6108         if (status & LinkChg)
6109                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6110
6111         rtl_irq_enable_all(tp);
6112 }
6113
6114 static void rtl_task(struct work_struct *work)
6115 {
6116         static const struct {
6117                 int bitnr;
6118                 void (*action)(struct rtl8169_private *);
6119         } rtl_work[] = {
6120                 /* XXX - keep rtl_slow_event_work() as first element. */
6121                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6122                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6123                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6124         };
6125         struct rtl8169_private *tp =
6126                 container_of(work, struct rtl8169_private, wk.work);
6127         struct net_device *dev = tp->dev;
6128         int i;
6129
6130         rtl_lock_work(tp);
6131
6132         if (!netif_running(dev) ||
6133             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6134                 goto out_unlock;
6135
6136         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6137                 bool pending;
6138
6139                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6140                 if (pending)
6141                         rtl_work[i].action(tp);
6142         }
6143
6144 out_unlock:
6145         rtl_unlock_work(tp);
6146 }
6147
6148 static int rtl8169_poll(struct napi_struct *napi, int budget)
6149 {
6150         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6151         struct net_device *dev = tp->dev;
6152         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6153         int work_done= 0;
6154         u16 status;
6155
6156         status = rtl_get_events(tp);
6157         rtl_ack_events(tp, status & ~tp->event_slow);
6158
6159         if (status & RTL_EVENT_NAPI_RX)
6160                 work_done = rtl_rx(dev, tp, (u32) budget);
6161
6162         if (status & RTL_EVENT_NAPI_TX)
6163                 rtl_tx(dev, tp);
6164
6165         if (status & tp->event_slow) {
6166                 enable_mask &= ~tp->event_slow;
6167
6168                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6169         }
6170
6171         if (work_done < budget) {
6172                 napi_complete(napi);
6173
6174                 rtl_irq_enable(tp, enable_mask);
6175                 mmiowb();
6176         }
6177
6178         return work_done;
6179 }
6180
6181 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6182 {
6183         struct rtl8169_private *tp = netdev_priv(dev);
6184
6185         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6186                 return;
6187
6188         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6189         RTL_W32(RxMissed, 0);
6190 }
6191
6192 static void rtl8169_down(struct net_device *dev)
6193 {
6194         struct rtl8169_private *tp = netdev_priv(dev);
6195         void __iomem *ioaddr = tp->mmio_addr;
6196
6197         del_timer_sync(&tp->timer);
6198
6199         napi_disable(&tp->napi);
6200         netif_stop_queue(dev);
6201
6202         rtl8169_hw_reset(tp);
6203         /*
6204          * At this point device interrupts can not be enabled in any function,
6205          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6206          * and napi is disabled (rtl8169_poll).
6207          */
6208         rtl8169_rx_missed(dev, ioaddr);
6209
6210         /* Give a racing hard_start_xmit a few cycles to complete. */
6211         synchronize_sched();
6212
6213         rtl8169_tx_clear(tp);
6214
6215         rtl8169_rx_clear(tp);
6216
6217         rtl_pll_power_down(tp);
6218 }
6219
6220 static int rtl8169_close(struct net_device *dev)
6221 {
6222         struct rtl8169_private *tp = netdev_priv(dev);
6223         struct pci_dev *pdev = tp->pci_dev;
6224
6225         pm_runtime_get_sync(&pdev->dev);
6226
6227         /* Update counters before going down */
6228         rtl8169_update_counters(dev);
6229
6230         rtl_lock_work(tp);
6231         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6232
6233         rtl8169_down(dev);
6234         rtl_unlock_work(tp);
6235
6236         free_irq(pdev->irq, dev);
6237
6238         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6239                           tp->RxPhyAddr);
6240         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6241                           tp->TxPhyAddr);
6242         tp->TxDescArray = NULL;
6243         tp->RxDescArray = NULL;
6244
6245         pm_runtime_put_sync(&pdev->dev);
6246
6247         return 0;
6248 }
6249
6250 #ifdef CONFIG_NET_POLL_CONTROLLER
6251 static void rtl8169_netpoll(struct net_device *dev)
6252 {
6253         struct rtl8169_private *tp = netdev_priv(dev);
6254
6255         rtl8169_interrupt(tp->pci_dev->irq, dev);
6256 }
6257 #endif
6258
6259 static int rtl_open(struct net_device *dev)
6260 {
6261         struct rtl8169_private *tp = netdev_priv(dev);
6262         void __iomem *ioaddr = tp->mmio_addr;
6263         struct pci_dev *pdev = tp->pci_dev;
6264         int retval = -ENOMEM;
6265
6266         pm_runtime_get_sync(&pdev->dev);
6267
6268         /*
6269          * Rx and Tx descriptors needs 256 bytes alignment.
6270          * dma_alloc_coherent provides more.
6271          */
6272         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6273                                              &tp->TxPhyAddr, GFP_KERNEL);
6274         if (!tp->TxDescArray)
6275                 goto err_pm_runtime_put;
6276
6277         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6278                                              &tp->RxPhyAddr, GFP_KERNEL);
6279         if (!tp->RxDescArray)
6280                 goto err_free_tx_0;
6281
6282         retval = rtl8169_init_ring(dev);
6283         if (retval < 0)
6284                 goto err_free_rx_1;
6285
6286         INIT_WORK(&tp->wk.work, rtl_task);
6287
6288         smp_mb();
6289
6290         rtl_request_firmware(tp);
6291
6292         retval = request_irq(pdev->irq, rtl8169_interrupt,
6293                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6294                              dev->name, dev);
6295         if (retval < 0)
6296                 goto err_release_fw_2;
6297
6298         rtl_lock_work(tp);
6299
6300         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6301
6302         napi_enable(&tp->napi);
6303
6304         rtl8169_init_phy(dev, tp);
6305
6306         __rtl8169_set_features(dev, dev->features);
6307
6308         rtl_pll_power_up(tp);
6309
6310         rtl_hw_start(dev);
6311
6312         netif_start_queue(dev);
6313
6314         rtl_unlock_work(tp);
6315
6316         tp->saved_wolopts = 0;
6317         pm_runtime_put_noidle(&pdev->dev);
6318
6319         rtl8169_check_link_status(dev, tp, ioaddr);
6320 out:
6321         return retval;
6322
6323 err_release_fw_2:
6324         rtl_release_firmware(tp);
6325         rtl8169_rx_clear(tp);
6326 err_free_rx_1:
6327         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6328                           tp->RxPhyAddr);
6329         tp->RxDescArray = NULL;
6330 err_free_tx_0:
6331         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6332                           tp->TxPhyAddr);
6333         tp->TxDescArray = NULL;
6334 err_pm_runtime_put:
6335         pm_runtime_put_noidle(&pdev->dev);
6336         goto out;
6337 }
6338
6339 static struct rtnl_link_stats64 *
6340 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6341 {
6342         struct rtl8169_private *tp = netdev_priv(dev);
6343         void __iomem *ioaddr = tp->mmio_addr;
6344         unsigned int start;
6345
6346         if (netif_running(dev))
6347                 rtl8169_rx_missed(dev, ioaddr);
6348
6349         do {
6350                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6351                 stats->rx_packets = tp->rx_stats.packets;
6352                 stats->rx_bytes = tp->rx_stats.bytes;
6353         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6354
6355
6356         do {
6357                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6358                 stats->tx_packets = tp->tx_stats.packets;
6359                 stats->tx_bytes = tp->tx_stats.bytes;
6360         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6361
6362         stats->rx_dropped       = dev->stats.rx_dropped;
6363         stats->tx_dropped       = dev->stats.tx_dropped;
6364         stats->rx_length_errors = dev->stats.rx_length_errors;
6365         stats->rx_errors        = dev->stats.rx_errors;
6366         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6367         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6368         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6369
6370         return stats;
6371 }
6372
6373 static void rtl8169_net_suspend(struct net_device *dev)
6374 {
6375         struct rtl8169_private *tp = netdev_priv(dev);
6376
6377         if (!netif_running(dev))
6378                 return;
6379
6380         netif_device_detach(dev);
6381         netif_stop_queue(dev);
6382
6383         rtl_lock_work(tp);
6384         napi_disable(&tp->napi);
6385         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6386         rtl_unlock_work(tp);
6387
6388         rtl_pll_power_down(tp);
6389 }
6390
6391 #ifdef CONFIG_PM
6392
6393 static int rtl8169_suspend(struct device *device)
6394 {
6395         struct pci_dev *pdev = to_pci_dev(device);
6396         struct net_device *dev = pci_get_drvdata(pdev);
6397
6398         rtl8169_net_suspend(dev);
6399
6400         return 0;
6401 }
6402
6403 static void __rtl8169_resume(struct net_device *dev)
6404 {
6405         struct rtl8169_private *tp = netdev_priv(dev);
6406
6407         netif_device_attach(dev);
6408
6409         rtl_pll_power_up(tp);
6410
6411         rtl_lock_work(tp);
6412         napi_enable(&tp->napi);
6413         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6414         rtl_unlock_work(tp);
6415
6416         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6417 }
6418
6419 static int rtl8169_resume(struct device *device)
6420 {
6421         struct pci_dev *pdev = to_pci_dev(device);
6422         struct net_device *dev = pci_get_drvdata(pdev);
6423         struct rtl8169_private *tp = netdev_priv(dev);
6424
6425         rtl8169_init_phy(dev, tp);
6426
6427         if (netif_running(dev))
6428                 __rtl8169_resume(dev);
6429
6430         return 0;
6431 }
6432
6433 static int rtl8169_runtime_suspend(struct device *device)
6434 {
6435         struct pci_dev *pdev = to_pci_dev(device);
6436         struct net_device *dev = pci_get_drvdata(pdev);
6437         struct rtl8169_private *tp = netdev_priv(dev);
6438
6439         if (!tp->TxDescArray)
6440                 return 0;
6441
6442         rtl_lock_work(tp);
6443         tp->saved_wolopts = __rtl8169_get_wol(tp);
6444         __rtl8169_set_wol(tp, WAKE_ANY);
6445         rtl_unlock_work(tp);
6446
6447         rtl8169_net_suspend(dev);
6448
6449         return 0;
6450 }
6451
6452 static int rtl8169_runtime_resume(struct device *device)
6453 {
6454         struct pci_dev *pdev = to_pci_dev(device);
6455         struct net_device *dev = pci_get_drvdata(pdev);
6456         struct rtl8169_private *tp = netdev_priv(dev);
6457
6458         if (!tp->TxDescArray)
6459                 return 0;
6460
6461         rtl_lock_work(tp);
6462         __rtl8169_set_wol(tp, tp->saved_wolopts);
6463         tp->saved_wolopts = 0;
6464         rtl_unlock_work(tp);
6465
6466         rtl8169_init_phy(dev, tp);
6467
6468         __rtl8169_resume(dev);
6469
6470         return 0;
6471 }
6472
6473 static int rtl8169_runtime_idle(struct device *device)
6474 {
6475         struct pci_dev *pdev = to_pci_dev(device);
6476         struct net_device *dev = pci_get_drvdata(pdev);
6477         struct rtl8169_private *tp = netdev_priv(dev);
6478
6479         return tp->TxDescArray ? -EBUSY : 0;
6480 }
6481
6482 static const struct dev_pm_ops rtl8169_pm_ops = {
6483         .suspend                = rtl8169_suspend,
6484         .resume                 = rtl8169_resume,
6485         .freeze                 = rtl8169_suspend,
6486         .thaw                   = rtl8169_resume,
6487         .poweroff               = rtl8169_suspend,
6488         .restore                = rtl8169_resume,
6489         .runtime_suspend        = rtl8169_runtime_suspend,
6490         .runtime_resume         = rtl8169_runtime_resume,
6491         .runtime_idle           = rtl8169_runtime_idle,
6492 };
6493
6494 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6495
6496 #else /* !CONFIG_PM */
6497
6498 #define RTL8169_PM_OPS  NULL
6499
6500 #endif /* !CONFIG_PM */
6501
6502 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6503 {
6504         void __iomem *ioaddr = tp->mmio_addr;
6505
6506         /* WoL fails with 8168b when the receiver is disabled. */
6507         switch (tp->mac_version) {
6508         case RTL_GIGA_MAC_VER_11:
6509         case RTL_GIGA_MAC_VER_12:
6510         case RTL_GIGA_MAC_VER_17:
6511                 pci_clear_master(tp->pci_dev);
6512
6513                 RTL_W8(ChipCmd, CmdRxEnb);
6514                 /* PCI commit */
6515                 RTL_R8(ChipCmd);
6516                 break;
6517         default:
6518                 break;
6519         }
6520 }
6521
6522 static void rtl_shutdown(struct pci_dev *pdev)
6523 {
6524         struct net_device *dev = pci_get_drvdata(pdev);
6525         struct rtl8169_private *tp = netdev_priv(dev);
6526         struct device *d = &pdev->dev;
6527
6528         pm_runtime_get_sync(d);
6529
6530         rtl8169_net_suspend(dev);
6531
6532         /* Restore original MAC address */
6533         rtl_rar_set(tp, dev->perm_addr);
6534
6535         rtl8169_hw_reset(tp);
6536
6537         if (system_state == SYSTEM_POWER_OFF) {
6538                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6539                         rtl_wol_suspend_quirk(tp);
6540                         rtl_wol_shutdown_quirk(tp);
6541                 }
6542
6543                 pci_wake_from_d3(pdev, true);
6544                 pci_set_power_state(pdev, PCI_D3hot);
6545         }
6546
6547         pm_runtime_put_noidle(d);
6548 }
6549
6550 static void rtl_remove_one(struct pci_dev *pdev)
6551 {
6552         struct net_device *dev = pci_get_drvdata(pdev);
6553         struct rtl8169_private *tp = netdev_priv(dev);
6554
6555         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6556             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6557             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6558                 rtl8168_driver_stop(tp);
6559         }
6560
6561         cancel_work_sync(&tp->wk.work);
6562
6563         netif_napi_del(&tp->napi);
6564
6565         unregister_netdev(dev);
6566
6567         rtl_release_firmware(tp);
6568
6569         if (pci_dev_run_wake(pdev))
6570                 pm_runtime_get_noresume(&pdev->dev);
6571
6572         /* restore original MAC address */
6573         rtl_rar_set(tp, dev->perm_addr);
6574
6575         rtl_disable_msi(pdev, tp);
6576         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6577         pci_set_drvdata(pdev, NULL);
6578 }
6579
6580 static const struct net_device_ops rtl_netdev_ops = {
6581         .ndo_open               = rtl_open,
6582         .ndo_stop               = rtl8169_close,
6583         .ndo_get_stats64        = rtl8169_get_stats64,
6584         .ndo_start_xmit         = rtl8169_start_xmit,
6585         .ndo_tx_timeout         = rtl8169_tx_timeout,
6586         .ndo_validate_addr      = eth_validate_addr,
6587         .ndo_change_mtu         = rtl8169_change_mtu,
6588         .ndo_fix_features       = rtl8169_fix_features,
6589         .ndo_set_features       = rtl8169_set_features,
6590         .ndo_set_mac_address    = rtl_set_mac_address,
6591         .ndo_do_ioctl           = rtl8169_ioctl,
6592         .ndo_set_rx_mode        = rtl_set_rx_mode,
6593 #ifdef CONFIG_NET_POLL_CONTROLLER
6594         .ndo_poll_controller    = rtl8169_netpoll,
6595 #endif
6596
6597 };
6598
6599 static const struct rtl_cfg_info {
6600         void (*hw_start)(struct net_device *);
6601         unsigned int region;
6602         unsigned int align;
6603         u16 event_slow;
6604         unsigned features;
6605         u8 default_ver;
6606 } rtl_cfg_infos [] = {
6607         [RTL_CFG_0] = {
6608                 .hw_start       = rtl_hw_start_8169,
6609                 .region         = 1,
6610                 .align          = 0,
6611                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6612                 .features       = RTL_FEATURE_GMII,
6613                 .default_ver    = RTL_GIGA_MAC_VER_01,
6614         },
6615         [RTL_CFG_1] = {
6616                 .hw_start       = rtl_hw_start_8168,
6617                 .region         = 2,
6618                 .align          = 8,
6619                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6620                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6621                 .default_ver    = RTL_GIGA_MAC_VER_11,
6622         },
6623         [RTL_CFG_2] = {
6624                 .hw_start       = rtl_hw_start_8101,
6625                 .region         = 2,
6626                 .align          = 8,
6627                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6628                                   PCSTimeout,
6629                 .features       = RTL_FEATURE_MSI,
6630                 .default_ver    = RTL_GIGA_MAC_VER_13,
6631         }
6632 };
6633
6634 /* Cfg9346_Unlock assumed. */
6635 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6636                             const struct rtl_cfg_info *cfg)
6637 {
6638         void __iomem *ioaddr = tp->mmio_addr;
6639         unsigned msi = 0;
6640         u8 cfg2;
6641
6642         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6643         if (cfg->features & RTL_FEATURE_MSI) {
6644                 if (pci_enable_msi(tp->pci_dev)) {
6645                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6646                 } else {
6647                         cfg2 |= MSIEnable;
6648                         msi = RTL_FEATURE_MSI;
6649                 }
6650         }
6651         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6652                 RTL_W8(Config2, cfg2);
6653         return msi;
6654 }
6655
6656 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6657 {
6658         void __iomem *ioaddr = tp->mmio_addr;
6659
6660         return RTL_R8(MCU) & LINK_LIST_RDY;
6661 }
6662
6663 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6664 {
6665         void __iomem *ioaddr = tp->mmio_addr;
6666
6667         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6668 }
6669
6670 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6671 {
6672         void __iomem *ioaddr = tp->mmio_addr;
6673         u32 data;
6674
6675         tp->ocp_base = OCP_STD_PHY_BASE;
6676
6677         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6678
6679         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6680                 return;
6681
6682         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6683                 return;
6684
6685         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6686         msleep(1);
6687         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6688
6689         data = r8168_mac_ocp_read(tp, 0xe8de);
6690         data &= ~(1 << 14);
6691         r8168_mac_ocp_write(tp, 0xe8de, data);
6692
6693         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6694                 return;
6695
6696         data = r8168_mac_ocp_read(tp, 0xe8de);
6697         data |= (1 << 15);
6698         r8168_mac_ocp_write(tp, 0xe8de, data);
6699
6700         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6701                 return;
6702 }
6703
6704 static void rtl_hw_initialize(struct rtl8169_private *tp)
6705 {
6706         switch (tp->mac_version) {
6707         case RTL_GIGA_MAC_VER_40:
6708         case RTL_GIGA_MAC_VER_41:
6709                 rtl_hw_init_8168g(tp);
6710                 break;
6711
6712         default:
6713                 break;
6714         }
6715 }
6716
6717 static int
6718 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6719 {
6720         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6721         const unsigned int region = cfg->region;
6722         struct rtl8169_private *tp;
6723         struct mii_if_info *mii;
6724         struct net_device *dev;
6725         void __iomem *ioaddr;
6726         int chipset, i;
6727         int rc;
6728
6729         if (netif_msg_drv(&debug)) {
6730                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6731                        MODULENAME, RTL8169_VERSION);
6732         }
6733
6734         dev = alloc_etherdev(sizeof (*tp));
6735         if (!dev) {
6736                 rc = -ENOMEM;
6737                 goto out;
6738         }
6739
6740         SET_NETDEV_DEV(dev, &pdev->dev);
6741         dev->netdev_ops = &rtl_netdev_ops;
6742         tp = netdev_priv(dev);
6743         tp->dev = dev;
6744         tp->pci_dev = pdev;
6745         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6746
6747         mii = &tp->mii;
6748         mii->dev = dev;
6749         mii->mdio_read = rtl_mdio_read;
6750         mii->mdio_write = rtl_mdio_write;
6751         mii->phy_id_mask = 0x1f;
6752         mii->reg_num_mask = 0x1f;
6753         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6754
6755         /* disable ASPM completely as that cause random device stop working
6756          * problems as well as full system hangs for some PCIe devices users */
6757         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6758                                      PCIE_LINK_STATE_CLKPM);
6759
6760         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6761         rc = pci_enable_device(pdev);
6762         if (rc < 0) {
6763                 netif_err(tp, probe, dev, "enable failure\n");
6764                 goto err_out_free_dev_1;
6765         }
6766
6767         if (pci_set_mwi(pdev) < 0)
6768                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6769
6770         /* make sure PCI base addr 1 is MMIO */
6771         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6772                 netif_err(tp, probe, dev,
6773                           "region #%d not an MMIO resource, aborting\n",
6774                           region);
6775                 rc = -ENODEV;
6776                 goto err_out_mwi_2;
6777         }
6778
6779         /* check for weird/broken PCI region reporting */
6780         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6781                 netif_err(tp, probe, dev,
6782                           "Invalid PCI region size(s), aborting\n");
6783                 rc = -ENODEV;
6784                 goto err_out_mwi_2;
6785         }
6786
6787         rc = pci_request_regions(pdev, MODULENAME);
6788         if (rc < 0) {
6789                 netif_err(tp, probe, dev, "could not request regions\n");
6790                 goto err_out_mwi_2;
6791         }
6792
6793         tp->cp_cmd = RxChkSum;
6794
6795         if ((sizeof(dma_addr_t) > 4) &&
6796             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6797                 tp->cp_cmd |= PCIDAC;
6798                 dev->features |= NETIF_F_HIGHDMA;
6799         } else {
6800                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6801                 if (rc < 0) {
6802                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6803                         goto err_out_free_res_3;
6804                 }
6805         }
6806
6807         /* ioremap MMIO region */
6808         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6809         if (!ioaddr) {
6810                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6811                 rc = -EIO;
6812                 goto err_out_free_res_3;
6813         }
6814         tp->mmio_addr = ioaddr;
6815
6816         if (!pci_is_pcie(pdev))
6817                 netif_info(tp, probe, dev, "not PCI Express\n");
6818
6819         /* Identify chip attached to board */
6820         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6821
6822         rtl_init_rxcfg(tp);
6823
6824         rtl_irq_disable(tp);
6825
6826         rtl_hw_initialize(tp);
6827
6828         rtl_hw_reset(tp);
6829
6830         rtl_ack_events(tp, 0xffff);
6831
6832         pci_set_master(pdev);
6833
6834         /*
6835          * Pretend we are using VLANs; This bypasses a nasty bug where
6836          * Interrupts stop flowing on high load on 8110SCd controllers.
6837          */
6838         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6839                 tp->cp_cmd |= RxVlan;
6840
6841         rtl_init_mdio_ops(tp);
6842         rtl_init_pll_power_ops(tp);
6843         rtl_init_jumbo_ops(tp);
6844         rtl_init_csi_ops(tp);
6845
6846         rtl8169_print_mac_version(tp);
6847
6848         chipset = tp->mac_version;
6849         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6850
6851         RTL_W8(Cfg9346, Cfg9346_Unlock);
6852         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6853         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6854         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6855                 tp->features |= RTL_FEATURE_WOL;
6856         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6857                 tp->features |= RTL_FEATURE_WOL;
6858         tp->features |= rtl_try_msi(tp, cfg);
6859         RTL_W8(Cfg9346, Cfg9346_Lock);
6860
6861         if (rtl_tbi_enabled(tp)) {
6862                 tp->set_speed = rtl8169_set_speed_tbi;
6863                 tp->get_settings = rtl8169_gset_tbi;
6864                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6865                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6866                 tp->link_ok = rtl8169_tbi_link_ok;
6867                 tp->do_ioctl = rtl_tbi_ioctl;
6868         } else {
6869                 tp->set_speed = rtl8169_set_speed_xmii;
6870                 tp->get_settings = rtl8169_gset_xmii;
6871                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6872                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6873                 tp->link_ok = rtl8169_xmii_link_ok;
6874                 tp->do_ioctl = rtl_xmii_ioctl;
6875         }
6876
6877         mutex_init(&tp->wk.mutex);
6878
6879         /* Get MAC address */
6880         for (i = 0; i < ETH_ALEN; i++)
6881                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6882
6883         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6884         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6885
6886         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6887
6888         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6889          * properly for all devices */
6890         dev->features |= NETIF_F_RXCSUM |
6891                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6892
6893         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6894                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6895         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6896                 NETIF_F_HIGHDMA;
6897
6898         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6899                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6900                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6901
6902         dev->hw_features |= NETIF_F_RXALL;
6903         dev->hw_features |= NETIF_F_RXFCS;
6904
6905         tp->hw_start = cfg->hw_start;
6906         tp->event_slow = cfg->event_slow;
6907
6908         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6909                 ~(RxBOVF | RxFOVF) : ~0;
6910
6911         init_timer(&tp->timer);
6912         tp->timer.data = (unsigned long) dev;
6913         tp->timer.function = rtl8169_phy_timer;
6914
6915         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6916
6917         rc = register_netdev(dev);
6918         if (rc < 0)
6919                 goto err_out_msi_4;
6920
6921         pci_set_drvdata(pdev, dev);
6922
6923         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6924                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6925                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6926         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6927                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6928                            "tx checksumming: %s]\n",
6929                            rtl_chip_infos[chipset].jumbo_max,
6930                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6931         }
6932
6933         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6934             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6935             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6936                 rtl8168_driver_start(tp);
6937         }
6938
6939         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6940
6941         if (pci_dev_run_wake(pdev))
6942                 pm_runtime_put_noidle(&pdev->dev);
6943
6944         netif_carrier_off(dev);
6945
6946 out:
6947         return rc;
6948
6949 err_out_msi_4:
6950         netif_napi_del(&tp->napi);
6951         rtl_disable_msi(pdev, tp);
6952         iounmap(ioaddr);
6953 err_out_free_res_3:
6954         pci_release_regions(pdev);
6955 err_out_mwi_2:
6956         pci_clear_mwi(pdev);
6957         pci_disable_device(pdev);
6958 err_out_free_dev_1:
6959         free_netdev(dev);
6960         goto out;
6961 }
6962
6963 static struct pci_driver rtl8169_pci_driver = {
6964         .name           = MODULENAME,
6965         .id_table       = rtl8169_pci_tbl,
6966         .probe          = rtl_init_one,
6967         .remove         = rtl_remove_one,
6968         .shutdown       = rtl_shutdown,
6969         .driver.pm      = RTL8169_PM_OPS,
6970 };
6971
6972 module_pci_driver(rtl8169_pci_driver);