1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
79 #include <asm/uaccess.h>
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
301 struct cp_dma_stats {
317 struct cp_extra_stats {
318 unsigned long rx_frags;
323 struct net_device *dev;
327 struct napi_struct napi;
329 struct pci_dev *pdev;
333 struct cp_extra_stats cp_stats;
335 unsigned rx_head ____cacheline_aligned;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
340 unsigned tx_head ____cacheline_aligned;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
350 struct mii_if_info mii_if;
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
414 unsigned int mtu = cp->dev->mtu;
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
420 cp->rx_buf_sz = PKT_BUF_SZ;
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
426 u32 opts2 = le32_to_cpu(desc->opts2);
428 skb->protocol = eth_type_trans (skb, cp->dev);
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
436 napi_gro_receive(&cp->napi, skb);
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
457 static inline unsigned int cp_rx_csum_ok (u32 status)
459 unsigned int protocol = (status >> 16) & 0x3;
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
477 cpw16(IntrStatus, cp_rx_intr_mask);
481 dma_addr_t mapping, new_mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
486 skb = cp->rx_skb[rx_tail];
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
519 dev->stats.rx_dropped++;
523 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
525 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
526 dev->stats.rx_dropped++;
531 dma_unmap_single(&cp->pdev->dev, mapping,
532 buflen, PCI_DMA_FROMDEVICE);
534 /* Handle checksum offloading for incoming packets. */
535 if (cp_rx_csum_ok(status))
536 skb->ip_summed = CHECKSUM_UNNECESSARY;
538 skb_checksum_none_assert(skb);
542 cp->rx_skb[rx_tail] = new_skb;
544 cp_rx_skb(cp, skb, desc);
546 mapping = new_mapping;
549 cp->rx_ring[rx_tail].opts2 = 0;
550 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
551 if (rx_tail == (CP_RX_RING_SIZE - 1))
552 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
555 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
556 rx_tail = NEXT_RX(rx_tail);
562 cp->rx_tail = rx_tail;
564 /* if we did not reach work limit, then we're done with
565 * this round of polling
570 if (cpr16(IntrStatus) & cp_rx_intr_mask)
573 napi_gro_flush(napi);
574 spin_lock_irqsave(&cp->lock, flags);
575 __napi_complete(napi);
576 cpw16_f(IntrMask, cp_intr_mask);
577 spin_unlock_irqrestore(&cp->lock, flags);
583 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
585 struct net_device *dev = dev_instance;
586 struct cp_private *cp;
589 if (unlikely(dev == NULL))
591 cp = netdev_priv(dev);
593 status = cpr16(IntrStatus);
594 if (!status || (status == 0xFFFF))
597 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
598 status, cpr8(Cmd), cpr16(CpCmd));
600 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
602 spin_lock(&cp->lock);
604 /* close possible race's with dev_close */
605 if (unlikely(!netif_running(dev))) {
607 spin_unlock(&cp->lock);
611 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
612 if (napi_schedule_prep(&cp->napi)) {
613 cpw16_f(IntrMask, cp_norx_intr_mask);
614 __napi_schedule(&cp->napi);
617 if (status & (TxOK | TxErr | TxEmpty | SWInt))
619 if (status & LinkChg)
620 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
622 spin_unlock(&cp->lock);
624 if (status & PciErr) {
627 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
628 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
629 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
632 /* TODO: reset hardware */
638 #ifdef CONFIG_NET_POLL_CONTROLLER
640 * Polling receive - used by netconsole and other diagnostic tools
641 * to allow network i/o with interrupts disabled.
643 static void cp_poll_controller(struct net_device *dev)
645 disable_irq(dev->irq);
646 cp_interrupt(dev->irq, dev);
647 enable_irq(dev->irq);
651 static void cp_tx (struct cp_private *cp)
653 unsigned tx_head = cp->tx_head;
654 unsigned tx_tail = cp->tx_tail;
656 while (tx_tail != tx_head) {
657 struct cp_desc *txd = cp->tx_ring + tx_tail;
662 status = le32_to_cpu(txd->opts1);
663 if (status & DescOwn)
666 skb = cp->tx_skb[tx_tail];
669 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
670 le32_to_cpu(txd->opts1) & 0xffff,
673 if (status & LastFrag) {
674 if (status & (TxError | TxFIFOUnder)) {
675 netif_dbg(cp, tx_err, cp->dev,
676 "tx err, status 0x%x\n", status);
677 cp->dev->stats.tx_errors++;
679 cp->dev->stats.tx_window_errors++;
680 if (status & TxMaxCol)
681 cp->dev->stats.tx_aborted_errors++;
682 if (status & TxLinkFail)
683 cp->dev->stats.tx_carrier_errors++;
684 if (status & TxFIFOUnder)
685 cp->dev->stats.tx_fifo_errors++;
687 cp->dev->stats.collisions +=
688 ((status >> TxColCntShift) & TxColCntMask);
689 cp->dev->stats.tx_packets++;
690 cp->dev->stats.tx_bytes += skb->len;
691 netif_dbg(cp, tx_done, cp->dev,
692 "tx done, slot %d\n", tx_tail);
694 dev_kfree_skb_irq(skb);
697 cp->tx_skb[tx_tail] = NULL;
699 tx_tail = NEXT_TX(tx_tail);
702 cp->tx_tail = tx_tail;
704 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
705 netif_wake_queue(cp->dev);
708 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
710 return vlan_tx_tag_present(skb) ?
711 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
714 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
715 int first, int entry_last)
719 skb_frag_t *this_frag;
720 for (frag = 0; frag+first < entry_last; frag++) {
722 cp->tx_skb[index] = NULL;
723 txd = &cp->tx_ring[index];
724 this_frag = &skb_shinfo(skb)->frags[frag];
725 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
726 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
730 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
731 struct net_device *dev)
733 struct cp_private *cp = netdev_priv(dev);
736 unsigned long intr_flags;
740 spin_lock_irqsave(&cp->lock, intr_flags);
742 /* This is a hard error, log it. */
743 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
744 netif_stop_queue(dev);
745 spin_unlock_irqrestore(&cp->lock, intr_flags);
746 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
747 return NETDEV_TX_BUSY;
751 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
752 mss = skb_shinfo(skb)->gso_size;
754 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
756 if (skb_shinfo(skb)->nr_frags == 0) {
757 struct cp_desc *txd = &cp->tx_ring[entry];
762 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
763 if (dma_mapping_error(&cp->pdev->dev, mapping))
767 txd->addr = cpu_to_le64(mapping);
770 flags = eor | len | DescOwn | FirstFrag | LastFrag;
773 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
774 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
775 const struct iphdr *ip = ip_hdr(skb);
776 if (ip->protocol == IPPROTO_TCP)
777 flags |= IPCS | TCPCS;
778 else if (ip->protocol == IPPROTO_UDP)
779 flags |= IPCS | UDPCS;
781 WARN_ON(1); /* we need a WARN() */
784 txd->opts1 = cpu_to_le32(flags);
787 cp->tx_skb[entry] = skb;
788 entry = NEXT_TX(entry);
791 u32 first_len, first_eor;
792 dma_addr_t first_mapping;
793 int frag, first_entry = entry;
794 const struct iphdr *ip = ip_hdr(skb);
796 /* We must give this initial chunk to the device last.
797 * Otherwise we could race with the device.
800 first_len = skb_headlen(skb);
801 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
802 first_len, PCI_DMA_TODEVICE);
803 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
806 cp->tx_skb[entry] = skb;
807 entry = NEXT_TX(entry);
809 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
810 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
815 len = skb_frag_size(this_frag);
816 mapping = dma_map_single(&cp->pdev->dev,
817 skb_frag_address(this_frag),
818 len, PCI_DMA_TODEVICE);
819 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
820 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
824 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
826 ctrl = eor | len | DescOwn;
830 ((mss & MSSMask) << MSSShift);
831 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
832 if (ip->protocol == IPPROTO_TCP)
833 ctrl |= IPCS | TCPCS;
834 else if (ip->protocol == IPPROTO_UDP)
835 ctrl |= IPCS | UDPCS;
840 if (frag == skb_shinfo(skb)->nr_frags - 1)
843 txd = &cp->tx_ring[entry];
845 txd->addr = cpu_to_le64(mapping);
848 txd->opts1 = cpu_to_le32(ctrl);
851 cp->tx_skb[entry] = skb;
852 entry = NEXT_TX(entry);
855 txd = &cp->tx_ring[first_entry];
857 txd->addr = cpu_to_le64(first_mapping);
860 if (skb->ip_summed == CHECKSUM_PARTIAL) {
861 if (ip->protocol == IPPROTO_TCP)
862 txd->opts1 = cpu_to_le32(first_eor | first_len |
863 FirstFrag | DescOwn |
865 else if (ip->protocol == IPPROTO_UDP)
866 txd->opts1 = cpu_to_le32(first_eor | first_len |
867 FirstFrag | DescOwn |
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn);
877 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
879 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
880 netif_stop_queue(dev);
883 spin_unlock_irqrestore(&cp->lock, intr_flags);
885 cpw8(TxPoll, NormalTxPoll);
890 cp->dev->stats.tx_dropped++;
894 /* Set or clear the multicast filter for this adaptor.
895 This routine is not state sensitive and need not be SMP locked. */
897 static void __cp_set_rx_mode (struct net_device *dev)
899 struct cp_private *cp = netdev_priv(dev);
900 u32 mc_filter[2]; /* Multicast hash filter */
904 /* Note: do not reorder, GCC is clever about common statements. */
905 if (dev->flags & IFF_PROMISC) {
906 /* Unconditionally log net taps. */
908 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
910 mc_filter[1] = mc_filter[0] = 0xffffffff;
911 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
912 (dev->flags & IFF_ALLMULTI)) {
913 /* Too many to filter perfectly -- accept all multicasts. */
914 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
915 mc_filter[1] = mc_filter[0] = 0xffffffff;
917 struct netdev_hw_addr *ha;
918 rx_mode = AcceptBroadcast | AcceptMyPhys;
919 mc_filter[1] = mc_filter[0] = 0;
920 netdev_for_each_mc_addr(ha, dev) {
921 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
923 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
924 rx_mode |= AcceptMulticast;
928 /* We can safely update without stopping the chip. */
929 tmp = cp_rx_config | rx_mode;
930 if (cp->rx_config != tmp) {
931 cpw32_f (RxConfig, tmp);
934 cpw32_f (MAR0 + 0, mc_filter[0]);
935 cpw32_f (MAR0 + 4, mc_filter[1]);
938 static void cp_set_rx_mode (struct net_device *dev)
941 struct cp_private *cp = netdev_priv(dev);
943 spin_lock_irqsave (&cp->lock, flags);
944 __cp_set_rx_mode(dev);
945 spin_unlock_irqrestore (&cp->lock, flags);
948 static void __cp_get_stats(struct cp_private *cp)
950 /* only lower 24 bits valid; write any value to clear */
951 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
955 static struct net_device_stats *cp_get_stats(struct net_device *dev)
957 struct cp_private *cp = netdev_priv(dev);
960 /* The chip only need report frame silently dropped. */
961 spin_lock_irqsave(&cp->lock, flags);
962 if (netif_running(dev) && netif_device_present(dev))
964 spin_unlock_irqrestore(&cp->lock, flags);
969 static void cp_stop_hw (struct cp_private *cp)
971 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
972 cpw16_f(IntrMask, 0);
975 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
978 cp->tx_head = cp->tx_tail = 0;
981 static void cp_reset_hw (struct cp_private *cp)
983 unsigned work = 1000;
988 if (!(cpr8(Cmd) & CmdReset))
991 schedule_timeout_uninterruptible(10);
994 netdev_err(cp->dev, "hardware reset timeout\n");
997 static inline void cp_start_hw (struct cp_private *cp)
999 cpw16(CpCmd, cp->cpcmd);
1000 cpw8(Cmd, RxOn | TxOn);
1003 static void cp_enable_irq(struct cp_private *cp)
1005 cpw16_f(IntrMask, cp_intr_mask);
1008 static void cp_init_hw (struct cp_private *cp)
1010 struct net_device *dev = cp->dev;
1011 dma_addr_t ring_dma;
1015 cpw8_f (Cfg9346, Cfg9346_Unlock);
1017 /* Restore our idea of the MAC address. */
1018 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1019 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1022 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1024 __cp_set_rx_mode(dev);
1025 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1027 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1028 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1029 cpw8(Config3, PARMEnable);
1030 cp->wol_enabled = 0;
1032 cpw8(Config5, cpr8(Config5) & PMEStatus);
1034 cpw32_f(HiTxRingAddr, 0);
1035 cpw32_f(HiTxRingAddr + 4, 0);
1037 ring_dma = cp->ring_dma;
1038 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1039 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1041 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1042 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1043 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1045 cpw16(MultiIntr, 0);
1047 cpw8_f(Cfg9346, Cfg9346_Lock);
1050 static int cp_refill_rx(struct cp_private *cp)
1052 struct net_device *dev = cp->dev;
1055 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1056 struct sk_buff *skb;
1059 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1063 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1064 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1065 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1069 cp->rx_skb[i] = skb;
1071 cp->rx_ring[i].opts2 = 0;
1072 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1073 if (i == (CP_RX_RING_SIZE - 1))
1074 cp->rx_ring[i].opts1 =
1075 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1077 cp->rx_ring[i].opts1 =
1078 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1088 static void cp_init_rings_index (struct cp_private *cp)
1091 cp->tx_head = cp->tx_tail = 0;
1094 static int cp_init_rings (struct cp_private *cp)
1096 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1097 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1099 cp_init_rings_index(cp);
1101 return cp_refill_rx (cp);
1104 static int cp_alloc_rings (struct cp_private *cp)
1108 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1109 &cp->ring_dma, GFP_KERNEL);
1114 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1116 return cp_init_rings(cp);
1119 static void cp_clean_rings (struct cp_private *cp)
1121 struct cp_desc *desc;
1124 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1125 if (cp->rx_skb[i]) {
1126 desc = cp->rx_ring + i;
1127 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1128 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1129 dev_kfree_skb(cp->rx_skb[i]);
1133 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1134 if (cp->tx_skb[i]) {
1135 struct sk_buff *skb = cp->tx_skb[i];
1137 desc = cp->tx_ring + i;
1138 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1139 le32_to_cpu(desc->opts1) & 0xffff,
1141 if (le32_to_cpu(desc->opts1) & LastFrag)
1143 cp->dev->stats.tx_dropped++;
1147 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1148 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1150 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1151 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1154 static void cp_free_rings (struct cp_private *cp)
1157 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1163 static int cp_open (struct net_device *dev)
1165 struct cp_private *cp = netdev_priv(dev);
1168 netif_dbg(cp, ifup, dev, "enabling interface\n");
1170 rc = cp_alloc_rings(cp);
1174 napi_enable(&cp->napi);
1178 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1184 netif_carrier_off(dev);
1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1186 netif_start_queue(dev);
1191 napi_disable(&cp->napi);
1197 static int cp_close (struct net_device *dev)
1199 struct cp_private *cp = netdev_priv(dev);
1200 unsigned long flags;
1202 napi_disable(&cp->napi);
1204 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1206 spin_lock_irqsave(&cp->lock, flags);
1208 netif_stop_queue(dev);
1209 netif_carrier_off(dev);
1213 spin_unlock_irqrestore(&cp->lock, flags);
1215 free_irq(dev->irq, dev);
1221 static void cp_tx_timeout(struct net_device *dev)
1223 struct cp_private *cp = netdev_priv(dev);
1224 unsigned long flags;
1227 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1228 cpr8(Cmd), cpr16(CpCmd),
1229 cpr16(IntrStatus), cpr16(IntrMask));
1231 spin_lock_irqsave(&cp->lock, flags);
1235 rc = cp_init_rings(cp);
1238 netif_wake_queue(dev);
1240 spin_unlock_irqrestore(&cp->lock, flags);
1244 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1246 struct cp_private *cp = netdev_priv(dev);
1248 unsigned long flags;
1250 /* check for invalid MTU, according to hardware limits */
1251 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1254 /* if network interface not up, no need for complexity */
1255 if (!netif_running(dev)) {
1257 cp_set_rxbufsize(cp); /* set new rx buf size */
1261 spin_lock_irqsave(&cp->lock, flags);
1263 cp_stop_hw(cp); /* stop h/w and free rings */
1267 cp_set_rxbufsize(cp); /* set new rx buf size */
1269 rc = cp_init_rings(cp); /* realloc and restart h/w */
1272 spin_unlock_irqrestore(&cp->lock, flags);
1278 static const char mii_2_8139_map[8] = {
1289 static int mdio_read(struct net_device *dev, int phy_id, int location)
1291 struct cp_private *cp = netdev_priv(dev);
1293 return location < 8 && mii_2_8139_map[location] ?
1294 readw(cp->regs + mii_2_8139_map[location]) : 0;
1298 static void mdio_write(struct net_device *dev, int phy_id, int location,
1301 struct cp_private *cp = netdev_priv(dev);
1303 if (location == 0) {
1304 cpw8(Cfg9346, Cfg9346_Unlock);
1305 cpw16(BasicModeCtrl, value);
1306 cpw8(Cfg9346, Cfg9346_Lock);
1307 } else if (location < 8 && mii_2_8139_map[location])
1308 cpw16(mii_2_8139_map[location], value);
1311 /* Set the ethtool Wake-on-LAN settings */
1312 static int netdev_set_wol (struct cp_private *cp,
1313 const struct ethtool_wolinfo *wol)
1317 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1318 /* If WOL is being disabled, no need for complexity */
1320 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1321 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1324 cpw8 (Cfg9346, Cfg9346_Unlock);
1325 cpw8 (Config3, options);
1326 cpw8 (Cfg9346, Cfg9346_Lock);
1328 options = 0; /* Paranoia setting */
1329 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1330 /* If WOL is being disabled, no need for complexity */
1332 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1333 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1334 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1337 cpw8 (Config5, options);
1339 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1344 /* Get the ethtool Wake-on-LAN settings */
1345 static void netdev_get_wol (struct cp_private *cp,
1346 struct ethtool_wolinfo *wol)
1350 wol->wolopts = 0; /* Start from scratch */
1351 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1352 WAKE_MCAST | WAKE_UCAST;
1353 /* We don't need to go on if WOL is disabled */
1354 if (!cp->wol_enabled) return;
1356 options = cpr8 (Config3);
1357 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1358 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1360 options = 0; /* Paranoia setting */
1361 options = cpr8 (Config5);
1362 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1363 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1364 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1367 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1369 struct cp_private *cp = netdev_priv(dev);
1371 strcpy (info->driver, DRV_NAME);
1372 strcpy (info->version, DRV_VERSION);
1373 strcpy (info->bus_info, pci_name(cp->pdev));
1376 static void cp_get_ringparam(struct net_device *dev,
1377 struct ethtool_ringparam *ring)
1379 ring->rx_max_pending = CP_RX_RING_SIZE;
1380 ring->tx_max_pending = CP_TX_RING_SIZE;
1381 ring->rx_pending = CP_RX_RING_SIZE;
1382 ring->tx_pending = CP_TX_RING_SIZE;
1385 static int cp_get_regs_len(struct net_device *dev)
1387 return CP_REGS_SIZE;
1390 static int cp_get_sset_count (struct net_device *dev, int sset)
1394 return CP_NUM_STATS;
1400 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1402 struct cp_private *cp = netdev_priv(dev);
1404 unsigned long flags;
1406 spin_lock_irqsave(&cp->lock, flags);
1407 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1408 spin_unlock_irqrestore(&cp->lock, flags);
1413 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1415 struct cp_private *cp = netdev_priv(dev);
1417 unsigned long flags;
1419 spin_lock_irqsave(&cp->lock, flags);
1420 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1421 spin_unlock_irqrestore(&cp->lock, flags);
1426 static int cp_nway_reset(struct net_device *dev)
1428 struct cp_private *cp = netdev_priv(dev);
1429 return mii_nway_restart(&cp->mii_if);
1432 static u32 cp_get_msglevel(struct net_device *dev)
1434 struct cp_private *cp = netdev_priv(dev);
1435 return cp->msg_enable;
1438 static void cp_set_msglevel(struct net_device *dev, u32 value)
1440 struct cp_private *cp = netdev_priv(dev);
1441 cp->msg_enable = value;
1444 static int cp_set_features(struct net_device *dev, u32 features)
1446 struct cp_private *cp = netdev_priv(dev);
1447 unsigned long flags;
1449 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1452 spin_lock_irqsave(&cp->lock, flags);
1454 if (features & NETIF_F_RXCSUM)
1455 cp->cpcmd |= RxChkSum;
1457 cp->cpcmd &= ~RxChkSum;
1459 if (features & NETIF_F_HW_VLAN_RX)
1460 cp->cpcmd |= RxVlanOn;
1462 cp->cpcmd &= ~RxVlanOn;
1464 cpw16_f(CpCmd, cp->cpcmd);
1465 spin_unlock_irqrestore(&cp->lock, flags);
1470 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1473 struct cp_private *cp = netdev_priv(dev);
1474 unsigned long flags;
1476 if (regs->len < CP_REGS_SIZE)
1477 return /* -EINVAL */;
1479 regs->version = CP_REGS_VER;
1481 spin_lock_irqsave(&cp->lock, flags);
1482 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1483 spin_unlock_irqrestore(&cp->lock, flags);
1486 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1488 struct cp_private *cp = netdev_priv(dev);
1489 unsigned long flags;
1491 spin_lock_irqsave (&cp->lock, flags);
1492 netdev_get_wol (cp, wol);
1493 spin_unlock_irqrestore (&cp->lock, flags);
1496 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1498 struct cp_private *cp = netdev_priv(dev);
1499 unsigned long flags;
1502 spin_lock_irqsave (&cp->lock, flags);
1503 rc = netdev_set_wol (cp, wol);
1504 spin_unlock_irqrestore (&cp->lock, flags);
1509 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1511 switch (stringset) {
1513 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1521 static void cp_get_ethtool_stats (struct net_device *dev,
1522 struct ethtool_stats *estats, u64 *tmp_stats)
1524 struct cp_private *cp = netdev_priv(dev);
1525 struct cp_dma_stats *nic_stats;
1529 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1534 /* begin NIC statistics dump */
1535 cpw32(StatsAddr + 4, (u64)dma >> 32);
1536 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1539 for (i = 0; i < 1000; i++) {
1540 if ((cpr32(StatsAddr) & DumpStats) == 0)
1544 cpw32(StatsAddr, 0);
1545 cpw32(StatsAddr + 4, 0);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1551 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1552 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1554 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1555 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1556 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1557 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1558 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1559 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1560 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1561 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1562 tmp_stats[i++] = cp->cp_stats.rx_frags;
1563 BUG_ON(i != CP_NUM_STATS);
1565 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1568 static const struct ethtool_ops cp_ethtool_ops = {
1569 .get_drvinfo = cp_get_drvinfo,
1570 .get_regs_len = cp_get_regs_len,
1571 .get_sset_count = cp_get_sset_count,
1572 .get_settings = cp_get_settings,
1573 .set_settings = cp_set_settings,
1574 .nway_reset = cp_nway_reset,
1575 .get_link = ethtool_op_get_link,
1576 .get_msglevel = cp_get_msglevel,
1577 .set_msglevel = cp_set_msglevel,
1578 .get_regs = cp_get_regs,
1579 .get_wol = cp_get_wol,
1580 .set_wol = cp_set_wol,
1581 .get_strings = cp_get_strings,
1582 .get_ethtool_stats = cp_get_ethtool_stats,
1583 .get_eeprom_len = cp_get_eeprom_len,
1584 .get_eeprom = cp_get_eeprom,
1585 .set_eeprom = cp_set_eeprom,
1586 .get_ringparam = cp_get_ringparam,
1589 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1591 struct cp_private *cp = netdev_priv(dev);
1593 unsigned long flags;
1595 if (!netif_running(dev))
1598 spin_lock_irqsave(&cp->lock, flags);
1599 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1600 spin_unlock_irqrestore(&cp->lock, flags);
1604 static int cp_set_mac_address(struct net_device *dev, void *p)
1606 struct cp_private *cp = netdev_priv(dev);
1607 struct sockaddr *addr = p;
1609 if (!is_valid_ether_addr(addr->sa_data))
1610 return -EADDRNOTAVAIL;
1612 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1614 spin_lock_irq(&cp->lock);
1616 cpw8_f(Cfg9346, Cfg9346_Unlock);
1617 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1618 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1619 cpw8_f(Cfg9346, Cfg9346_Lock);
1621 spin_unlock_irq(&cp->lock);
1626 /* Serial EEPROM section. */
1628 /* EEPROM_Ctrl bits. */
1629 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1630 #define EE_CS 0x08 /* EEPROM chip select. */
1631 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1632 #define EE_WRITE_0 0x00
1633 #define EE_WRITE_1 0x02
1634 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1635 #define EE_ENB (0x80 | EE_CS)
1637 /* Delay between EEPROM clock transitions.
1638 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1641 #define eeprom_delay() readl(ee_addr)
1643 /* The EEPROM commands include the alway-set leading bit. */
1644 #define EE_EXTEND_CMD (4)
1645 #define EE_WRITE_CMD (5)
1646 #define EE_READ_CMD (6)
1647 #define EE_ERASE_CMD (7)
1649 #define EE_EWDS_ADDR (0)
1650 #define EE_WRAL_ADDR (1)
1651 #define EE_ERAL_ADDR (2)
1652 #define EE_EWEN_ADDR (3)
1654 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1656 static void eeprom_cmd_start(void __iomem *ee_addr)
1658 writeb (EE_ENB & ~EE_CS, ee_addr);
1659 writeb (EE_ENB, ee_addr);
1663 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1667 /* Shift the command bits out. */
1668 for (i = cmd_len - 1; i >= 0; i--) {
1669 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1670 writeb (EE_ENB | dataval, ee_addr);
1672 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1675 writeb (EE_ENB, ee_addr);
1679 static void eeprom_cmd_end(void __iomem *ee_addr)
1681 writeb (~EE_CS, ee_addr);
1685 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1688 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1690 eeprom_cmd_start(ee_addr);
1691 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1692 eeprom_cmd_end(ee_addr);
1695 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1699 void __iomem *ee_addr = ioaddr + Cfg9346;
1700 int read_cmd = location | (EE_READ_CMD << addr_len);
1702 eeprom_cmd_start(ee_addr);
1703 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1705 for (i = 16; i > 0; i--) {
1706 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1709 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1711 writeb (EE_ENB, ee_addr);
1715 eeprom_cmd_end(ee_addr);
1720 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1724 void __iomem *ee_addr = ioaddr + Cfg9346;
1725 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1727 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1729 eeprom_cmd_start(ee_addr);
1730 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1731 eeprom_cmd(ee_addr, val, 16);
1732 eeprom_cmd_end(ee_addr);
1734 eeprom_cmd_start(ee_addr);
1735 for (i = 0; i < 20000; i++)
1736 if (readb(ee_addr) & EE_DATA_READ)
1738 eeprom_cmd_end(ee_addr);
1740 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1743 static int cp_get_eeprom_len(struct net_device *dev)
1745 struct cp_private *cp = netdev_priv(dev);
1748 spin_lock_irq(&cp->lock);
1749 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1750 spin_unlock_irq(&cp->lock);
1755 static int cp_get_eeprom(struct net_device *dev,
1756 struct ethtool_eeprom *eeprom, u8 *data)
1758 struct cp_private *cp = netdev_priv(dev);
1759 unsigned int addr_len;
1761 u32 offset = eeprom->offset >> 1;
1762 u32 len = eeprom->len;
1765 eeprom->magic = CP_EEPROM_MAGIC;
1767 spin_lock_irq(&cp->lock);
1769 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1771 if (eeprom->offset & 1) {
1772 val = read_eeprom(cp->regs, offset, addr_len);
1773 data[i++] = (u8)(val >> 8);
1777 while (i < len - 1) {
1778 val = read_eeprom(cp->regs, offset, addr_len);
1779 data[i++] = (u8)val;
1780 data[i++] = (u8)(val >> 8);
1785 val = read_eeprom(cp->regs, offset, addr_len);
1789 spin_unlock_irq(&cp->lock);
1793 static int cp_set_eeprom(struct net_device *dev,
1794 struct ethtool_eeprom *eeprom, u8 *data)
1796 struct cp_private *cp = netdev_priv(dev);
1797 unsigned int addr_len;
1799 u32 offset = eeprom->offset >> 1;
1800 u32 len = eeprom->len;
1803 if (eeprom->magic != CP_EEPROM_MAGIC)
1806 spin_lock_irq(&cp->lock);
1808 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1810 if (eeprom->offset & 1) {
1811 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1812 val |= (u16)data[i++] << 8;
1813 write_eeprom(cp->regs, offset, val, addr_len);
1817 while (i < len - 1) {
1818 val = (u16)data[i++];
1819 val |= (u16)data[i++] << 8;
1820 write_eeprom(cp->regs, offset, val, addr_len);
1825 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1826 val |= (u16)data[i];
1827 write_eeprom(cp->regs, offset, val, addr_len);
1830 spin_unlock_irq(&cp->lock);
1834 /* Put the board into D3cold state and wait for WakeUp signal */
1835 static void cp_set_d3_state (struct cp_private *cp)
1837 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1838 pci_set_power_state (cp->pdev, PCI_D3hot);
1841 static const struct net_device_ops cp_netdev_ops = {
1842 .ndo_open = cp_open,
1843 .ndo_stop = cp_close,
1844 .ndo_validate_addr = eth_validate_addr,
1845 .ndo_set_mac_address = cp_set_mac_address,
1846 .ndo_set_rx_mode = cp_set_rx_mode,
1847 .ndo_get_stats = cp_get_stats,
1848 .ndo_do_ioctl = cp_ioctl,
1849 .ndo_start_xmit = cp_start_xmit,
1850 .ndo_tx_timeout = cp_tx_timeout,
1851 .ndo_set_features = cp_set_features,
1853 .ndo_change_mtu = cp_change_mtu,
1856 #ifdef CONFIG_NET_POLL_CONTROLLER
1857 .ndo_poll_controller = cp_poll_controller,
1861 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1863 struct net_device *dev;
1864 struct cp_private *cp;
1867 resource_size_t pciaddr;
1868 unsigned int addr_len, i, pci_using_dac;
1871 static int version_printed;
1872 if (version_printed++ == 0)
1873 pr_info("%s", version);
1876 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1877 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1878 dev_info(&pdev->dev,
1879 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1880 pdev->vendor, pdev->device, pdev->revision);
1884 dev = alloc_etherdev(sizeof(struct cp_private));
1887 SET_NETDEV_DEV(dev, &pdev->dev);
1889 cp = netdev_priv(dev);
1892 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1893 spin_lock_init (&cp->lock);
1894 cp->mii_if.dev = dev;
1895 cp->mii_if.mdio_read = mdio_read;
1896 cp->mii_if.mdio_write = mdio_write;
1897 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1898 cp->mii_if.phy_id_mask = 0x1f;
1899 cp->mii_if.reg_num_mask = 0x1f;
1900 cp_set_rxbufsize(cp);
1902 rc = pci_enable_device(pdev);
1906 rc = pci_set_mwi(pdev);
1908 goto err_out_disable;
1910 rc = pci_request_regions(pdev, DRV_NAME);
1914 pciaddr = pci_resource_start(pdev, 1);
1917 dev_err(&pdev->dev, "no MMIO resource\n");
1920 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1922 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1923 (unsigned long long)pci_resource_len(pdev, 1));
1927 /* Configure DMA attributes. */
1928 if ((sizeof(dma_addr_t) > 4) &&
1929 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1930 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1935 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1938 "No usable DMA configuration, aborting\n");
1941 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1944 "No usable consistent DMA configuration, aborting\n");
1949 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1950 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1952 dev->features |= NETIF_F_RXCSUM;
1953 dev->hw_features |= NETIF_F_RXCSUM;
1955 regs = ioremap(pciaddr, CP_REGS_SIZE);
1958 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1959 (unsigned long long)pci_resource_len(pdev, 1),
1960 (unsigned long long)pciaddr);
1963 dev->base_addr = (unsigned long) regs;
1968 /* read MAC address from EEPROM */
1969 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1970 for (i = 0; i < 3; i++)
1971 ((__le16 *) (dev->dev_addr))[i] =
1972 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1973 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1975 dev->netdev_ops = &cp_netdev_ops;
1976 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1977 dev->ethtool_ops = &cp_ethtool_ops;
1978 dev->watchdog_timeo = TX_TIMEOUT;
1980 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1983 dev->features |= NETIF_F_HIGHDMA;
1985 /* disabled by default until verified */
1986 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1987 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1988 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1991 dev->irq = pdev->irq;
1993 rc = register_netdev(dev);
1997 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1998 dev->base_addr, dev->dev_addr, dev->irq);
2000 pci_set_drvdata(pdev, dev);
2002 /* enable busmastering and memory-write-invalidate */
2003 pci_set_master(pdev);
2005 if (cp->wol_enabled)
2006 cp_set_d3_state (cp);
2013 pci_release_regions(pdev);
2015 pci_clear_mwi(pdev);
2017 pci_disable_device(pdev);
2023 static void cp_remove_one (struct pci_dev *pdev)
2025 struct net_device *dev = pci_get_drvdata(pdev);
2026 struct cp_private *cp = netdev_priv(dev);
2028 unregister_netdev(dev);
2030 if (cp->wol_enabled)
2031 pci_set_power_state (pdev, PCI_D0);
2032 pci_release_regions(pdev);
2033 pci_clear_mwi(pdev);
2034 pci_disable_device(pdev);
2035 pci_set_drvdata(pdev, NULL);
2040 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2042 struct net_device *dev = pci_get_drvdata(pdev);
2043 struct cp_private *cp = netdev_priv(dev);
2044 unsigned long flags;
2046 if (!netif_running(dev))
2049 netif_device_detach (dev);
2050 netif_stop_queue (dev);
2052 spin_lock_irqsave (&cp->lock, flags);
2054 /* Disable Rx and Tx */
2055 cpw16 (IntrMask, 0);
2056 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2058 spin_unlock_irqrestore (&cp->lock, flags);
2060 pci_save_state(pdev);
2061 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2062 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2067 static int cp_resume (struct pci_dev *pdev)
2069 struct net_device *dev = pci_get_drvdata (pdev);
2070 struct cp_private *cp = netdev_priv(dev);
2071 unsigned long flags;
2073 if (!netif_running(dev))
2076 netif_device_attach (dev);
2078 pci_set_power_state(pdev, PCI_D0);
2079 pci_restore_state(pdev);
2080 pci_enable_wake(pdev, PCI_D0, 0);
2082 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2083 cp_init_rings_index (cp);
2086 netif_start_queue (dev);
2088 spin_lock_irqsave (&cp->lock, flags);
2090 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2092 spin_unlock_irqrestore (&cp->lock, flags);
2096 #endif /* CONFIG_PM */
2098 static struct pci_driver cp_driver = {
2100 .id_table = cp_pci_tbl,
2101 .probe = cp_init_one,
2102 .remove = cp_remove_one,
2104 .resume = cp_resume,
2105 .suspend = cp_suspend,
2109 static int __init cp_init (void)
2112 pr_info("%s", version);
2114 return pci_register_driver(&cp_driver);
2117 static void __exit cp_exit (void)
2119 pci_unregister_driver (&cp_driver);
2122 module_init(cp_init);
2123 module_exit(cp_exit);