2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
44 #include <linux/mlx4/device.h>
45 #include <linux/mlx4/qp.h>
46 #include <linux/mlx4/cq.h>
47 #include <linux/mlx4/srq.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
53 #define DRV_NAME "mlx4_en"
54 #define DRV_VERSION "1.5.4.2"
55 #define DRV_RELDATE "October 2011"
57 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64 #define MLX4_EN_PAGE_SHIFT 12
65 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
66 #define MAX_RX_RINGS 16
67 #define MIN_RX_RINGS 4
69 #define HEADROOM (2048 / TXBB_SIZE + 1)
70 #define STAMP_STRIDE 64
71 #define STAMP_DWORDS (STAMP_STRIDE / 4)
72 #define STAMP_SHIFT 31
73 #define STAMP_VAL 0x7fffffff
74 #define STATS_DELAY (HZ / 4)
76 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
77 #define MAX_DESC_SIZE 512
78 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
81 * OS related constants and tunables
84 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
86 #define MLX4_EN_ALLOC_ORDER 2
87 #define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
89 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
91 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
92 * and 4K allocations) */
94 FRAG_SZ0 = 512 - NET_IP_ALIGN,
97 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
99 #define MLX4_EN_MAX_RX_FRAGS 4
101 /* Maximum ring sizes */
102 #define MLX4_EN_MAX_TX_SIZE 8192
103 #define MLX4_EN_MAX_RX_SIZE 8192
105 /* Minimum ring size for our page-allocation sceme to work */
106 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
107 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
109 #define MLX4_EN_SMALL_PKT_SIZE 64
110 #define MLX4_EN_NUM_TX_RINGS 8
111 #define MLX4_EN_NUM_PPP_RINGS 8
112 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
113 #define MLX4_EN_DEF_TX_RING_SIZE 512
114 #define MLX4_EN_DEF_RX_RING_SIZE 1024
116 /* Target number of packets to coalesce with interrupt moderation */
117 #define MLX4_EN_RX_COAL_TARGET 44
118 #define MLX4_EN_RX_COAL_TIME 0x10
120 #define MLX4_EN_TX_COAL_PKTS 5
121 #define MLX4_EN_TX_COAL_TIME 0x80
123 #define MLX4_EN_RX_RATE_LOW 400000
124 #define MLX4_EN_RX_COAL_TIME_LOW 0
125 #define MLX4_EN_RX_RATE_HIGH 450000
126 #define MLX4_EN_RX_COAL_TIME_HIGH 128
127 #define MLX4_EN_RX_SIZE_THRESH 1024
128 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
129 #define MLX4_EN_SAMPLE_INTERVAL 0
130 #define MLX4_EN_AVG_PKT_SMALL 256
132 #define MLX4_EN_AUTO_CONF 0xffff
134 #define MLX4_EN_DEF_RX_PAUSE 1
135 #define MLX4_EN_DEF_TX_PAUSE 1
137 /* Interval between successive polls in the Tx routine when polling is used
138 instead of interrupts (in per-core Tx rings) - should be power of 2 */
139 #define MLX4_EN_TX_POLL_MODER 16
140 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
142 #define ETH_LLC_SNAP_SIZE 8
144 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
145 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
146 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
148 #define MLX4_EN_MIN_MTU 46
149 #define ETH_BCAST 0xffffffffffffULL
151 #define MLX4_EN_LOOPBACK_RETRIES 5
152 #define MLX4_EN_LOOPBACK_TIMEOUT 100
154 #ifdef MLX4_EN_PERF_STAT
155 /* Number of samples to 'average' */
157 #define AVG_FACTOR 1024
158 #define NUM_PERF_STATS NUM_PERF_COUNTERS
160 #define INC_PERF_COUNTER(cnt) (++(cnt))
161 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
162 #define AVG_PERF_COUNTER(cnt, sample) \
163 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
164 #define GET_PERF_COUNTER(cnt) (cnt)
165 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
169 #define NUM_PERF_STATS 0
170 #define INC_PERF_COUNTER(cnt) do {} while (0)
171 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
172 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
173 #define GET_PERF_COUNTER(cnt) (0)
174 #define GET_AVG_PERF_COUNTER(cnt) (0)
175 #endif /* MLX4_EN_PERF_STAT */
190 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
191 #define XNOR(x, y) (!(x) == !(y))
192 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
195 struct mlx4_en_tx_info {
204 #define MLX4_EN_BIT_DESC_OWN 0x80000000
205 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
206 #define MLX4_EN_MEMTYPE_PAD 0x100
207 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
210 struct mlx4_en_tx_desc {
211 struct mlx4_wqe_ctrl_seg ctrl;
213 struct mlx4_wqe_data_seg data; /* at least one data segment */
214 struct mlx4_wqe_lso_seg lso;
215 struct mlx4_wqe_inline_seg inl;
219 #define MLX4_EN_USE_SRQ 0x01000000
221 #define MLX4_EN_CX3_LOW_ID 0x1000
222 #define MLX4_EN_CX3_HIGH_ID 0x1005
224 struct mlx4_en_rx_alloc {
229 struct mlx4_en_tx_ring {
230 struct mlx4_hwq_resources wqres;
231 u32 size ; /* number of TXBBs */
234 u16 cqn; /* index of port CQ associated with this ring */
242 struct mlx4_en_tx_info *tx_info;
246 struct mlx4_qp_context context;
248 enum mlx4_qp_state qp_state;
249 struct mlx4_srq dummy;
251 unsigned long packets;
252 unsigned long tx_csum;
253 spinlock_t comp_lock;
258 struct mlx4_en_rx_desc {
259 /* actual number of entries depends on rx ring stride */
260 struct mlx4_wqe_data_seg data[0];
263 struct mlx4_en_rx_ring {
264 struct mlx4_hwq_resources wqres;
265 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
266 u32 size ; /* number of Rx descs*/
271 u16 cqn; /* index of port CQ associated with this ring */
279 unsigned long packets;
280 unsigned long csum_ok;
281 unsigned long csum_none;
285 static inline int mlx4_en_can_lro(__be16 status)
287 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
288 MLX4_CQE_STATUS_IPV4F |
289 MLX4_CQE_STATUS_IPV6 |
290 MLX4_CQE_STATUS_IPV4OPT |
291 MLX4_CQE_STATUS_TCP |
292 MLX4_CQE_STATUS_UDP |
293 MLX4_CQE_STATUS_IPOK)) ==
294 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
295 MLX4_CQE_STATUS_IPOK |
296 MLX4_CQE_STATUS_TCP);
301 struct mlx4_hwq_resources wqres;
304 struct net_device *dev;
305 struct napi_struct napi;
306 /* Per-core Tx cq processing support */
307 struct timer_list timer;
314 struct mlx4_cqe *buf;
315 #define MLX4_EN_OPCODE_ERROR 0x1e
318 struct mlx4_en_port_profile {
330 struct mlx4_en_profile {
338 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
342 struct mlx4_dev *dev;
343 struct pci_dev *pdev;
344 struct mutex state_lock;
345 struct net_device *pndev[MLX4_MAX_PORTS + 1];
348 struct mlx4_en_profile profile;
350 struct workqueue_struct *workqueue;
351 struct device *dma_device;
352 void __iomem *uar_map;
353 struct mlx4_uar priv_uar;
357 u8 mac_removed[MLX4_MAX_PORTS + 1];
361 struct mlx4_en_rss_map {
363 struct mlx4_qp qps[MAX_RX_RINGS];
364 enum mlx4_qp_state state[MAX_RX_RINGS];
365 struct mlx4_qp indir_qp;
366 enum mlx4_qp_state indir_state;
369 struct mlx4_en_rss_context {
379 struct mlx4_en_port_state {
385 struct mlx4_en_pkt_stats {
386 unsigned long broadcast;
387 unsigned long rx_prio[8];
388 unsigned long tx_prio[8];
389 #define NUM_PKT_STATS 17
392 struct mlx4_en_port_stats {
393 unsigned long tso_packets;
394 unsigned long queue_stopped;
395 unsigned long wake_queue;
396 unsigned long tx_timeout;
397 unsigned long rx_alloc_failed;
398 unsigned long rx_chksum_good;
399 unsigned long rx_chksum_none;
400 unsigned long tx_chksum_offload;
401 #define NUM_PORT_STATS 8
404 struct mlx4_en_perf_stats {
411 #define NUM_PERF_COUNTERS 6
414 struct mlx4_en_frag_info {
416 u16 frag_prefix_size;
423 struct mlx4_en_priv {
424 struct mlx4_en_dev *mdev;
425 struct mlx4_en_port_profile *prof;
426 struct net_device *dev;
427 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
428 struct net_device_stats stats;
429 struct net_device_stats ret_stats;
430 struct mlx4_en_port_state port_state;
431 spinlock_t stats_lock;
433 unsigned long last_moder_packets[MAX_RX_RINGS];
434 unsigned long last_moder_tx_packets;
435 unsigned long last_moder_bytes[MAX_RX_RINGS];
436 unsigned long last_moder_jiffies;
437 int last_moder_time[MAX_RX_RINGS];
447 u16 adaptive_rx_coal;
450 u32 validate_loopback;
452 struct mlx4_hwq_resources res;
465 struct mlx4_en_rss_map rss_map;
467 #define MLX4_EN_FLAG_PROMISC 0x1
468 #define MLX4_EN_FLAG_MC_PROMISC 0x2
472 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
476 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
477 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
478 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
479 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
480 struct work_struct mcast_task;
481 struct work_struct mac_task;
482 struct work_struct watchdog_task;
483 struct work_struct linkstate_task;
484 struct delayed_work stats_task;
485 struct mlx4_en_perf_stats pstats;
486 struct mlx4_en_pkt_stats pkstats;
487 struct mlx4_en_port_stats port_stats;
490 struct mlx4_en_stat_out_mbox hw_stats;
496 MLX4_EN_WOL_MAGIC = (1ULL << 61),
497 MLX4_EN_WOL_ENABLED = (1ULL << 62),
498 MLX4_EN_WOL_DO_MODIFY = (1ULL << 63),
502 void mlx4_en_destroy_netdev(struct net_device *dev);
503 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
504 struct mlx4_en_port_profile *prof);
506 int mlx4_en_start_port(struct net_device *dev);
507 void mlx4_en_stop_port(struct net_device *dev);
509 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
510 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
512 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
513 int entries, int ring, enum cq_type mode);
514 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
515 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
517 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
518 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
519 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
521 void mlx4_en_poll_tx_cq(unsigned long data);
522 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
523 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
524 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
526 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
527 int qpn, u32 size, u16 stride);
528 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
529 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
530 struct mlx4_en_tx_ring *ring,
532 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
533 struct mlx4_en_tx_ring *ring);
535 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
536 struct mlx4_en_rx_ring *ring,
537 u32 size, u16 stride);
538 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
539 struct mlx4_en_rx_ring *ring);
540 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
541 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
542 struct mlx4_en_rx_ring *ring);
543 int mlx4_en_process_rx_cq(struct net_device *dev,
544 struct mlx4_en_cq *cq,
546 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
547 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
548 int is_tx, int rss, int qpn, int cqn,
549 struct mlx4_qp_context *context);
550 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
551 int mlx4_en_map_buffer(struct mlx4_buf *buf);
552 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
554 void mlx4_en_calc_rx_buf(struct net_device *dev);
555 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
556 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
557 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
558 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
560 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
561 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
562 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
563 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
564 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
567 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
568 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
570 #define MLX4_EN_NUM_SELF_TEST 5
571 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
572 u64 mlx4_en_mac_to_u64(u8 *addr);
577 extern const struct ethtool_ops mlx4_en_ethtool_ops;
582 * printk / logging functions
586 int en_print(const char *level, const struct mlx4_en_priv *priv,
587 const char *format, ...);
589 #define en_dbg(mlevel, priv, format, arg...) \
591 if (NETIF_MSG_##mlevel & priv->msg_enable) \
592 en_print(KERN_DEBUG, priv, format, ##arg); \
594 #define en_warn(priv, format, arg...) \
595 en_print(KERN_WARNING, priv, format, ##arg)
596 #define en_err(priv, format, arg...) \
597 en_print(KERN_ERR, priv, format, ##arg)
598 #define en_info(priv, format, arg...) \
599 en_print(KERN_INFO, priv, format, ## arg)
601 #define mlx4_err(mdev, format, arg...) \
602 pr_err("%s %s: " format, DRV_NAME, \
603 dev_name(&mdev->pdev->dev), ##arg)
604 #define mlx4_info(mdev, format, arg...) \
605 pr_info("%s %s: " format, DRV_NAME, \
606 dev_name(&mdev->pdev->dev), ##arg)
607 #define mlx4_warn(mdev, format, arg...) \
608 pr_warning("%s %s: " format, DRV_NAME, \
609 dev_name(&mdev->pdev->dev), ##arg)