drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/tcp.h>
  42 #include <linux/moduleparam.h>
  43
  44 #include "mlx4_en.h"
  45
  46 enum {
  47         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
  48         MAX_BF = 256,
  49 };
  50
  51 static int inline_thold __read_mostly = MAX_INLINE;
  52
  53 module_param_named(inline_thold, inline_thold, int, 0444);
  54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
  55
  56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  57                            struct mlx4_en_tx_ring *ring, int qpn, u32 size,
  58                            u16 stride)
  59 {
  60         struct mlx4_en_dev *mdev = priv->mdev;
  61         int tmp;
  62         int err;
  63
  64         ring->size = size;
  65         ring->size_mask = size - 1;
  66         ring->stride = stride;
  67
  68         inline_thold = min(inline_thold, MAX_INLINE);
  69
  70         tmp = size * sizeof(struct mlx4_en_tx_info);
  71         ring->tx_info = vmalloc(tmp);
  72         if (!ring->tx_info)
  73                 return -ENOMEM;
  74
  75         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  76                  ring->tx_info, tmp);
  77
  78         ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  79         if (!ring->bounce_buf) {
  80                 err = -ENOMEM;
  81                 goto err_tx;
  82         }
  83         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
  84
  85         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
  86                                  2 * PAGE_SIZE);
  87         if (err) {
  88                 en_err(priv, "Failed allocating hwq resources\n");
  89                 goto err_bounce;
  90         }
  91
  92         err = mlx4_en_map_buffer(&ring->wqres.buf);
  93         if (err) {
  94                 en_err(priv, "Failed to map TX buffer\n");
  95                 goto err_hwq_res;
  96         }
  97
  98         ring->buf = ring->wqres.buf.direct.buf;
  99
 100         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
 101                "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
 102                ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
 103
 104         ring->qpn = qpn;
 105         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
 106         if (err) {
 107                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 108                 goto err_map;
 109         }
 110         ring->qp.event = mlx4_en_sqp_event;
 111
 112         err = mlx4_bf_alloc(mdev->dev, &ring->bf);
 113         if (err) {
 114                 en_dbg(DRV, priv, "working without blueflame (%d)", err);
 115                 ring->bf.uar = &mdev->priv_uar;
 116                 ring->bf.uar->map = mdev->uar_map;
 117                 ring->bf_enabled = false;
 118         } else
 119                 ring->bf_enabled = true;
 120
 121         return 0;
 122
 123 err_map:
 124         mlx4_en_unmap_buffer(&ring->wqres.buf);
 125 err_hwq_res:
 126         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 127 err_bounce:
 128         kfree(ring->bounce_buf);
 129         ring->bounce_buf = NULL;
 130 err_tx:
 131         vfree(ring->tx_info);
 132         ring->tx_info = NULL;
 133         return err;
 134 }
 135
 136 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 137                              struct mlx4_en_tx_ring *ring)
 138 {
 139         struct mlx4_en_dev *mdev = priv->mdev;
 140         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 141
 142         if (ring->bf_enabled)
 143                 mlx4_bf_free(mdev->dev, &ring->bf);
 144         mlx4_qp_remove(mdev->dev, &ring->qp);
 145         mlx4_qp_free(mdev->dev, &ring->qp);
 146         mlx4_en_unmap_buffer(&ring->wqres.buf);
 147         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 148         kfree(ring->bounce_buf);
 149         ring->bounce_buf = NULL;
 150         vfree(ring->tx_info);
 151         ring->tx_info = NULL;
 152 }
 153
 154 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 155                              struct mlx4_en_tx_ring *ring,
 156                              int cq, int user_prio)
 157 {
 158         struct mlx4_en_dev *mdev = priv->mdev;
 159         int err;
 160
 161         ring->cqn = cq;
 162         ring->prod = 0;
 163         ring->cons = 0xffffffff;
 164         ring->last_nr_txbb = 1;
 165         ring->poll_cnt = 0;
 166         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 167         memset(ring->buf, 0, ring->buf_size);
 168
 169         ring->qp_state = MLX4_QP_STATE_RST;
 170         ring->doorbell_qpn = ring->qp.qpn << 8;
 171
 172         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
 173                                 ring->cqn, user_prio, &ring->context);
 174         if (ring->bf_enabled)
 175                 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
 176
 177         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
 178                                &ring->qp, &ring->qp_state);
 179
 180         return err;
 181 }
 182
 183 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 184                                 struct mlx4_en_tx_ring *ring)
 185 {
 186         struct mlx4_en_dev *mdev = priv->mdev;
 187
 188         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
 189                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
 190 }
 191
 192
 193 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 194                                 struct mlx4_en_tx_ring *ring,
 195                                 int index, u8 owner)
 196 {
 197         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 198         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 199         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 200         struct sk_buff *skb = tx_info->skb;
 201         struct skb_frag_struct *frag;
 202         void *end = ring->buf + ring->buf_size;
 203         int frags = skb_shinfo(skb)->nr_frags;
 204         int i;
 205         __be32 *ptr = (__be32 *)tx_desc;
 206         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 207
 208         /* Optimize the common case when there are no wraparounds */
 209         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 210                 if (!tx_info->inl) {
 211                         if (tx_info->linear) {
 212                                 dma_unmap_single(priv->ddev,
 213                                         (dma_addr_t) be64_to_cpu(data->addr),
 214                                          be32_to_cpu(data->byte_count),
 215                                          PCI_DMA_TODEVICE);
 216                                 ++data;
 217                         }
 218
 219                         for (i = 0; i < frags; i++) {
 220                                 frag = &skb_shinfo(skb)->frags[i];
 221                                 dma_unmap_page(priv->ddev,
 222                                         (dma_addr_t) be64_to_cpu(data[i].addr),
 223                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
 224                         }
 225                 }
 226                 /* Stamp the freed descriptor */
 227                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
 228                         *ptr = stamp;
 229                         ptr += STAMP_DWORDS;
 230                 }
 231
 232         } else {
 233                 if (!tx_info->inl) {
 234                         if ((void *) data >= end) {
 235                                 data = ring->buf + ((void *)data - end);
 236                         }
 237
 238                         if (tx_info->linear) {
 239                                 dma_unmap_single(priv->ddev,
 240                                         (dma_addr_t) be64_to_cpu(data->addr),
 241                                          be32_to_cpu(data->byte_count),
 242                                          PCI_DMA_TODEVICE);
 243                                 ++data;
 244                         }
 245
 246                         for (i = 0; i < frags; i++) {
 247                                 /* Check for wraparound before unmapping */
 248                                 if ((void *) data >= end)
 249                                         data = ring->buf;
 250                                 frag = &skb_shinfo(skb)->frags[i];
 251                                 dma_unmap_page(priv->ddev,
 252                                         (dma_addr_t) be64_to_cpu(data->addr),
 253                                          skb_frag_size(frag), PCI_DMA_TODEVICE);
 254                                 ++data;
 255                         }
 256                 }
 257                 /* Stamp the freed descriptor */
 258                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
 259                         *ptr = stamp;
 260                         ptr += STAMP_DWORDS;
 261                         if ((void *) ptr >= end) {
 262                                 ptr = ring->buf;
 263                                 stamp ^= cpu_to_be32(0x80000000);
 264                         }
 265                 }
 266
 267         }
 268         dev_kfree_skb_any(skb);
 269         return tx_info->nr_txbb;
 270 }
 271
 272
 273 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 274 {
 275         struct mlx4_en_priv *priv = netdev_priv(dev);
 276         int cnt = 0;
 277
 278         /* Skip last polled descriptor */
 279         ring->cons += ring->last_nr_txbb;
 280         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 281                  ring->cons, ring->prod);
 282
 283         if ((u32) (ring->prod - ring->cons) > ring->size) {
 284                 if (netif_msg_tx_err(priv))
 285                         en_warn(priv, "Tx consumer passed producer!\n");
 286                 return 0;
 287         }
 288
 289         while (ring->cons != ring->prod) {
 290                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
 291                                                 ring->cons & ring->size_mask,
 292                                                 !!(ring->cons & ring->size));
 293                 ring->cons += ring->last_nr_txbb;
 294                 cnt++;
 295         }
 296
 297         if (cnt)
 298                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 299
 300         return cnt;
 301 }
 302
 303 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
 304 {
 305         struct mlx4_en_priv *priv = netdev_priv(dev);
 306         struct mlx4_cq *mcq = &cq->mcq;
 307         struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
 308         struct mlx4_cqe *cqe;
 309         u16 index;
 310         u16 new_index, ring_index;
 311         u32 txbbs_skipped = 0;
 312         u32 cons_index = mcq->cons_index;
 313         int size = cq->size;
 314         u32 size_mask = ring->size_mask;
 315         struct mlx4_cqe *buf = cq->buf;
 316         u32 packets = 0;
 317         u32 bytes = 0;
 318         int factor = priv->cqe_factor;
 319
 320         if (!priv->port_up)
 321                 return;
 322
 323         index = cons_index & size_mask;
 324         cqe = &buf[(index << factor) + factor];
 325         ring_index = ring->cons & size_mask;
 326
 327         /* Process all completed CQEs */
 328         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 329                         cons_index & size)) {
 330                 /*
 331                  * make sure we read the CQE after we read the
 332                  * ownership bit
 333                  */
 334                 rmb();
 335
 336                 /* Skip over last polled CQE */
 337                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 338
 339                 do {
 340                         txbbs_skipped += ring->last_nr_txbb;
 341                         ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
 342                         /* free next descriptor */
 343                         ring->last_nr_txbb = mlx4_en_free_tx_desc(
 344                                         priv, ring, ring_index,
 345                                         !!((ring->cons + txbbs_skipped) &
 346                                                         ring->size));
 347                         packets++;
 348                         bytes += ring->tx_info[ring_index].nr_bytes;
 349                 } while (ring_index != new_index);
 350
 351                 ++cons_index;
 352                 index = cons_index & size_mask;
 353                 cqe = &buf[(index << factor) + factor];
 354         }
 355
 356
 357         /*
 358          * To prevent CQ overflow we first update CQ consumer and only then
 359          * the ring consumer.
 360          */
 361         mcq->cons_index = cons_index;
 362         mlx4_cq_set_ci(mcq);
 363         wmb();
 364         ring->cons += txbbs_skipped;
 365         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 366
 367         /*
 368          * Wakeup Tx queue if this stopped, and at least 1 packet
 369          * was completed
 370          */
 371         if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
 372                 netif_tx_wake_queue(ring->tx_queue);
 373                 priv->port_stats.wake_queue++;
 374         }
 375 }
 376
 377 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 378 {
 379         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 380         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 381
 382         mlx4_en_process_tx_cq(cq->dev, cq);
 383         mlx4_en_arm_cq(priv, cq);
 384 }
 385
 386
 387 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 388                                                       struct mlx4_en_tx_ring *ring,
 389                                                       u32 index,
 390                                                       unsigned int desc_size)
 391 {
 392         u32 copy = (ring->size - index) * TXBB_SIZE;
 393         int i;
 394
 395         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 396                 if ((i & (TXBB_SIZE - 1)) == 0)
 397                         wmb();
 398
 399                 *((u32 *) (ring->buf + i)) =
 400                         *((u32 *) (ring->bounce_buf + copy + i));
 401         }
 402
 403         for (i = copy - 4; i >= 4 ; i -= 4) {
 404                 if ((i & (TXBB_SIZE - 1)) == 0)
 405                         wmb();
 406
 407                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 408                         *((u32 *) (ring->bounce_buf + i));
 409         }
 410
 411         /* Return real descriptor location */
 412         return ring->buf + index * TXBB_SIZE;
 413 }
 414
 415 static int is_inline(struct sk_buff *skb, void **pfrag)
 416 {
 417         void *ptr;
 418
 419         if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
 420                 if (skb_shinfo(skb)->nr_frags == 1) {
 421                         ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]);
 422                         if (unlikely(!ptr))
 423                                 return 0;
 424
 425                         if (pfrag)
 426                                 *pfrag = ptr;
 427
 428                         return 1;
 429                 } else if (unlikely(skb_shinfo(skb)->nr_frags))
 430                         return 0;
 431                 else
 432                         return 1;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int inline_size(struct sk_buff *skb)
 439 {
 440         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 441             <= MLX4_INLINE_ALIGN)
 442                 return ALIGN(skb->len + CTRL_SIZE +
 443                              sizeof(struct mlx4_wqe_inline_seg), 16);
 444         else
 445                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 446                              sizeof(struct mlx4_wqe_inline_seg), 16);
 447 }
 448
 449 static int get_real_size(struct sk_buff *skb, struct net_device *dev,
 450                          int *lso_header_size)
 451 {
 452         struct mlx4_en_priv *priv = netdev_priv(dev);
 453         int real_size;
 454
 455         if (skb_is_gso(skb)) {
 456                 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 457                 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
 458                         ALIGN(*lso_header_size + 4, DS_SIZE);
 459                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 460                         /* We add a segment for the skb linear buffer only if
 461                          * it contains data */
 462                         if (*lso_header_size < skb_headlen(skb))
 463                                 real_size += DS_SIZE;
 464                         else {
 465                                 if (netif_msg_tx_err(priv))
 466                                         en_warn(priv, "Non-linear headers\n");
 467                                 return 0;
 468                         }
 469                 }
 470         } else {
 471                 *lso_header_size = 0;
 472                 if (!is_inline(skb, NULL))
 473                         real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
 474                 else
 475                         real_size = inline_size(skb);
 476         }
 477
 478         return real_size;
 479 }
 480
 481 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
 482                              int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
 483 {
 484         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 485         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 486
 487         if (skb->len <= spc) {
 488                 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 489                 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
 490                 if (skb_shinfo(skb)->nr_frags)
 491                         memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
 492                                skb_frag_size(&skb_shinfo(skb)->frags[0]));
 493
 494         } else {
 495                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 496                 if (skb_headlen(skb) <= spc) {
 497                         skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
 498                         if (skb_headlen(skb) < spc) {
 499                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb),
 500                                         fragptr, spc - skb_headlen(skb));
 501                                 fragptr +=  spc - skb_headlen(skb);
 502                         }
 503                         inl = (void *) (inl + 1) + spc;
 504                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 505                 } else {
 506                         skb_copy_from_linear_data(skb, inl + 1, spc);
 507                         inl = (void *) (inl + 1) + spc;
 508                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 509                                         skb_headlen(skb) - spc);
 510                         if (skb_shinfo(skb)->nr_frags)
 511                                 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
 512                                         fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0]));
 513                 }
 514
 515                 wmb();
 516                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 517         }
 518 }
 519
 520 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
 521 {
 522         struct mlx4_en_priv *priv = netdev_priv(dev);
 523         u16 rings_p_up = priv->num_tx_rings_p_up;
 524         u8 up = 0;
 525
 526         if (dev->num_tc)
 527                 return skb_tx_hash(dev, skb);
 528
 529         if (vlan_tx_tag_present(skb))
 530                 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
 531
 532         return __skb_tx_hash(dev, skb, rings_p_up) + up * rings_p_up;
 533 }
 534
 535 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt)
 536 {
 537         __iowrite64_copy(dst, src, bytecnt / 8);
 538 }
 539
 540 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 541 {
 542         struct mlx4_en_priv *priv = netdev_priv(dev);
 543         struct mlx4_en_dev *mdev = priv->mdev;
 544         struct mlx4_en_tx_ring *ring;
 545         struct mlx4_en_tx_desc *tx_desc;
 546         struct mlx4_wqe_data_seg *data;
 547         struct skb_frag_struct *frag;
 548         struct mlx4_en_tx_info *tx_info;
 549         struct ethhdr *ethh;
 550         int tx_ind = 0;
 551         int nr_txbb;
 552         int desc_size;
 553         int real_size;
 554         dma_addr_t dma;
 555         u32 index, bf_index;
 556         __be32 op_own;
 557         u16 vlan_tag = 0;
 558         int i;
 559         int lso_header_size;
 560         void *fragptr;
 561         bool bounce = false;
 562
 563         if (!priv->port_up)
 564                 goto tx_drop;
 565
 566         real_size = get_real_size(skb, dev, &lso_header_size);
 567         if (unlikely(!real_size))
 568                 goto tx_drop;
 569
 570         /* Align descriptor to TXBB size */
 571         desc_size = ALIGN(real_size, TXBB_SIZE);
 572         nr_txbb = desc_size / TXBB_SIZE;
 573         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 574                 if (netif_msg_tx_err(priv))
 575                         en_warn(priv, "Oversized header or SG list\n");
 576                 goto tx_drop;
 577         }
 578
 579         tx_ind = skb->queue_mapping;
 580         ring = &priv->tx_ring[tx_ind];
 581         if (vlan_tx_tag_present(skb))
 582                 vlan_tag = vlan_tx_tag_get(skb);
 583
 584         /* Check available TXBBs And 2K spare for prefetch */
 585         if (unlikely(((int)(ring->prod - ring->cons)) >
 586                      ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 587                 /* every full Tx ring stops queue */
 588                 netif_tx_stop_queue(ring->tx_queue);
 589                 priv->port_stats.queue_stopped++;
 590
 591                 /* If queue was emptied after the if, and before the
 592                  * stop_queue - need to wake the queue, or else it will remain
 593                  * stopped forever.
 594                  * Need a memory barrier to make sure ring->cons was not
 595                  * updated before queue was stopped.
 596                  */
 597                 wmb();
 598
 599                 if (unlikely(((int)(ring->prod - ring->cons)) <=
 600                              ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 601                         netif_tx_wake_queue(ring->tx_queue);
 602                         priv->port_stats.wake_queue++;
 603                 } else {
 604                         return NETDEV_TX_BUSY;
 605                 }
 606         }
 607
 608         /* Track current inflight packets for performance analysis */
 609         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 610                          (u32) (ring->prod - ring->cons - 1));
 611
 612         /* Packet is good - grab an index and transmit it */
 613         index = ring->prod & ring->size_mask;
 614         bf_index = ring->prod;
 615
 616         /* See if we have enough space for whole descriptor TXBB for setting
 617          * SW ownership on next descriptor; if not, use a bounce buffer. */
 618         if (likely(index + nr_txbb <= ring->size))
 619                 tx_desc = ring->buf + index * TXBB_SIZE;
 620         else {
 621                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 622                 bounce = true;
 623         }
 624
 625         /* Save skb in tx_info ring */
 626         tx_info = &ring->tx_info[index];
 627         tx_info->skb = skb;
 628         tx_info->nr_txbb = nr_txbb;
 629
 630         /* Prepare ctrl segement apart opcode+ownership, which depends on
 631          * whether LSO is used */
 632         tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
 633         tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 634                 !!vlan_tx_tag_present(skb);
 635         tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
 636         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 637         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 638                 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 639                                                          MLX4_WQE_CTRL_TCP_UDP_CSUM);
 640                 ring->tx_csum++;
 641         }
 642
 643         if (mlx4_is_mfunc(mdev->dev) || priv->validate_loopback) {
 644                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 645                  * so that VFs and PF can communicate with each other
 646                  */
 647                 ethh = (struct ethhdr *)skb->data;
 648                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 649                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 650         }
 651
 652         /* Handle LSO (TSO) packets */
 653         if (lso_header_size) {
 654                 /* Mark opcode as LSO */
 655                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 656                         ((ring->prod & ring->size) ?
 657                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 658
 659                 /* Fill in the LSO prefix */
 660                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 661                         skb_shinfo(skb)->gso_size << 16 | lso_header_size);
 662
 663                 /* Copy headers;
 664                  * note that we already verified that it is linear */
 665                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 666                 data = ((void *) &tx_desc->lso +
 667                         ALIGN(lso_header_size + 4, DS_SIZE));
 668
 669                 priv->port_stats.tso_packets++;
 670                 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
 671                         !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
 672                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 673                 ring->packets += i;
 674         } else {
 675                 /* Normal (Non LSO) packet */
 676                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 677                         ((ring->prod & ring->size) ?
 678                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 679                 data = &tx_desc->data;
 680                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 681                 ring->packets++;
 682
 683         }
 684         ring->bytes += tx_info->nr_bytes;
 685         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
 686         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 687
 688
 689         /* valid only for none inline segments */
 690         tx_info->data_offset = (void *) data - (void *) tx_desc;
 691
 692         tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
 693         data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
 694
 695         if (!is_inline(skb, &fragptr)) {
 696                 /* Map fragments */
 697                 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
 698                         frag = &skb_shinfo(skb)->frags[i];
 699                         dma = skb_frag_dma_map(priv->ddev, frag,
 700                                                0, skb_frag_size(frag),
 701                                                DMA_TO_DEVICE);
 702                         data->addr = cpu_to_be64(dma);
 703                         data->lkey = cpu_to_be32(mdev->mr.key);
 704                         wmb();
 705                         data->byte_count = cpu_to_be32(skb_frag_size(frag));
 706                         --data;
 707                 }
 708
 709                 /* Map linear part */
 710                 if (tx_info->linear) {
 711                         dma = dma_map_single(priv->ddev, skb->data + lso_header_size,
 712                                              skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
 713                         data->addr = cpu_to_be64(dma);
 714                         data->lkey = cpu_to_be32(mdev->mr.key);
 715                         wmb();
 716                         data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
 717                 }
 718                 tx_info->inl = 0;
 719         } else {
 720                 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
 721                 tx_info->inl = 1;
 722         }
 723
 724         ring->prod += nr_txbb;
 725
 726         /* If we used a bounce buffer then copy descriptor back into place */
 727         if (bounce)
 728                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
 729
 730         if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) {
 731                 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
 732                 op_own |= htonl((bf_index & 0xffff) << 8);
 733                 /* Ensure new descirptor hits memory
 734                 * before setting ownership of this descriptor to HW */
 735                 wmb();
 736                 tx_desc->ctrl.owner_opcode = op_own;
 737
 738                 wmb();
 739
 740                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl,
 741                      desc_size);
 742
 743                 wmb();
 744
 745                 ring->bf.offset ^= ring->bf.buf_size;
 746         } else {
 747                 /* Ensure new descirptor hits memory
 748                 * before setting ownership of this descriptor to HW */
 749                 wmb();
 750                 tx_desc->ctrl.owner_opcode = op_own;
 751                 wmb();
 752                 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL);
 753         }
 754
 755         return NETDEV_TX_OK;
 756
 757 tx_drop:
 758         dev_kfree_skb_any(skb);
 759         priv->stats.tx_dropped++;
 760         return NETDEV_TX_OK;
 761 }
 762