drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  99          board_82598 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 101          board_82598 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 103          board_82598 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 105          board_82598 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 121          board_82599 },
 122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 123          board_82599 },
 124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 125          board_82599 },
 126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 127          board_82599 },
 128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 129          board_X540 },
 130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 131          board_82599 },
 132         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 133          board_82599 },
 134
 135         /* required last entry */
 136         {0, }
 137 };
 138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 139
 140 #ifdef CONFIG_IXGBE_DCA
 141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 142                             void *p);
 143 static struct notifier_block dca_notifier = {
 144         .notifier_call = ixgbe_notify_dca,
 145         .next          = NULL,
 146         .priority      = 0
 147 };
 148 #endif
 149
 150 #ifdef CONFIG_PCI_IOV
 151 static unsigned int max_vfs;
 152 module_param(max_vfs, uint, 0);
 153 MODULE_PARM_DESC(max_vfs,
 154                  "Maximum number of virtual functions to allocate per physical function");
 155 #endif /* CONFIG_PCI_IOV */
 156
 157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_VERSION);
 161
 162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 163
 164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 165 {
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         u32 gcr;
 168         u32 gpie;
 169         u32 vmdctl;
 170
 171 #ifdef CONFIG_PCI_IOV
 172         /* disable iov and allow time for transactions to clear */
 173         pci_disable_sriov(adapter->pdev);
 174 #endif
 175
 176         /* turn off device IOV mode */
 177         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 178         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 179         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 180         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 181         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 182         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 183
 184         /* set default pool back to 0 */
 185         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 186         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 187         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 188         IXGBE_WRITE_FLUSH(hw);
 189
 190         /* take a breather then clean up driver data */
 191         msleep(100);
 192
 193         kfree(adapter->vfinfo);
 194         adapter->vfinfo = NULL;
 195
 196         adapter->num_vfs = 0;
 197         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 198 }
 199
 200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 201 {
 202         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 203             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 204                 schedule_work(&adapter->service_task);
 205 }
 206
 207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 208 {
 209         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 210
 211         /* flush memory to make sure state is correct before next watchog */
 212         smp_mb__before_clear_bit();
 213         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 214 }
 215
 216 struct ixgbe_reg_info {
 217         u32 ofs;
 218         char *name;
 219 };
 220
 221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 222
 223         /* General Registers */
 224         {IXGBE_CTRL, "CTRL"},
 225         {IXGBE_STATUS, "STATUS"},
 226         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 227
 228         /* Interrupt Registers */
 229         {IXGBE_EICR, "EICR"},
 230
 231         /* RX Registers */
 232         {IXGBE_SRRCTL(0), "SRRCTL"},
 233         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 234         {IXGBE_RDLEN(0), "RDLEN"},
 235         {IXGBE_RDH(0), "RDH"},
 236         {IXGBE_RDT(0), "RDT"},
 237         {IXGBE_RXDCTL(0), "RXDCTL"},
 238         {IXGBE_RDBAL(0), "RDBAL"},
 239         {IXGBE_RDBAH(0), "RDBAH"},
 240
 241         /* TX Registers */
 242         {IXGBE_TDBAL(0), "TDBAL"},
 243         {IXGBE_TDBAH(0), "TDBAH"},
 244         {IXGBE_TDLEN(0), "TDLEN"},
 245         {IXGBE_TDH(0), "TDH"},
 246         {IXGBE_TDT(0), "TDT"},
 247         {IXGBE_TXDCTL(0), "TXDCTL"},
 248
 249         /* List Terminator */
 250         {}
 251 };
 252
 253
 254 /*
 255  * ixgbe_regdump - register printout routine
 256  */
 257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 258 {
 259         int i = 0, j = 0;
 260         char rname[16];
 261         u32 regs[64];
 262
 263         switch (reginfo->ofs) {
 264         case IXGBE_SRRCTL(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 267                 break;
 268         case IXGBE_DCA_RXCTRL(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 271                 break;
 272         case IXGBE_RDLEN(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 275                 break;
 276         case IXGBE_RDH(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 279                 break;
 280         case IXGBE_RDT(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 283                 break;
 284         case IXGBE_RXDCTL(0):
 285                 for (i = 0; i < 64; i++)
 286                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 287                 break;
 288         case IXGBE_RDBAL(0):
 289                 for (i = 0; i < 64; i++)
 290                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 291                 break;
 292         case IXGBE_RDBAH(0):
 293                 for (i = 0; i < 64; i++)
 294                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 295                 break;
 296         case IXGBE_TDBAL(0):
 297                 for (i = 0; i < 64; i++)
 298                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 299                 break;
 300         case IXGBE_TDBAH(0):
 301                 for (i = 0; i < 64; i++)
 302                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 303                 break;
 304         case IXGBE_TDLEN(0):
 305                 for (i = 0; i < 64; i++)
 306                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 307                 break;
 308         case IXGBE_TDH(0):
 309                 for (i = 0; i < 64; i++)
 310                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 311                 break;
 312         case IXGBE_TDT(0):
 313                 for (i = 0; i < 64; i++)
 314                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 315                 break;
 316         case IXGBE_TXDCTL(0):
 317                 for (i = 0; i < 64; i++)
 318                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 319                 break;
 320         default:
 321                 pr_info("%-15s %08x\n", reginfo->name,
 322                         IXGBE_READ_REG(hw, reginfo->ofs));
 323                 return;
 324         }
 325
 326         for (i = 0; i < 8; i++) {
 327                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 328                 pr_err("%-15s", rname);
 329                 for (j = 0; j < 8; j++)
 330                         pr_cont(" %08x", regs[i*8+j]);
 331                 pr_cont("\n");
 332         }
 333
 334 }
 335
 336 /*
 337  * ixgbe_dump - Print registers, tx-rings and rx-rings
 338  */
 339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 340 {
 341         struct net_device *netdev = adapter->netdev;
 342         struct ixgbe_hw *hw = &adapter->hw;
 343         struct ixgbe_reg_info *reginfo;
 344         int n = 0;
 345         struct ixgbe_ring *tx_ring;
 346         struct ixgbe_tx_buffer *tx_buffer_info;
 347         union ixgbe_adv_tx_desc *tx_desc;
 348         struct my_u0 { u64 a; u64 b; } *u0;
 349         struct ixgbe_ring *rx_ring;
 350         union ixgbe_adv_rx_desc *rx_desc;
 351         struct ixgbe_rx_buffer *rx_buffer_info;
 352         u32 staterr;
 353         int i = 0;
 354
 355         if (!netif_msg_hw(adapter))
 356                 return;
 357
 358         /* Print netdevice Info */
 359         if (netdev) {
 360                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 361                 pr_info("Device Name     state            "
 362                         "trans_start      last_rx\n");
 363                 pr_info("%-15s %016lX %016lX %016lX\n",
 364                         netdev->name,
 365                         netdev->state,
 366                         netdev->trans_start,
 367                         netdev->last_rx);
 368         }
 369
 370         /* Print Registers */
 371         dev_info(&adapter->pdev->dev, "Register Dump\n");
 372         pr_info(" Register Name   Value\n");
 373         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 374              reginfo->name; reginfo++) {
 375                 ixgbe_regdump(hw, reginfo);
 376         }
 377
 378         /* Print TX Ring Summary */
 379         if (!netdev || !netif_running(netdev))
 380                 goto exit;
 381
 382         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 383         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 tx_buffer_info =
 387                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 388                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 389                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 390                            (u64)tx_buffer_info->dma,
 391                            tx_buffer_info->length,
 392                            tx_buffer_info->next_to_watch,
 393                            (u64)tx_buffer_info->time_stamp);
 394         }
 395
 396         /* Print TX Rings */
 397         if (!netif_msg_tx_done(adapter))
 398                 goto rx_ring_summary;
 399
 400         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 401
 402         /* Transmit Descriptor Formats
 403          *
 404          * Advanced Transmit Descriptor
 405          *   +--------------------------------------------------------------+
 406          * 0 |         Buffer Address [63:0]                                |
 407          *   +--------------------------------------------------------------+
 408          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 409          *   +--------------------------------------------------------------+
 410          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 411          */
 412
 413         for (n = 0; n < adapter->num_tx_queues; n++) {
 414                 tx_ring = adapter->tx_ring[n];
 415                 pr_info("------------------------------------\n");
 416                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 417                 pr_info("------------------------------------\n");
 418                 pr_info("T [desc]     [address 63:0  ] "
 419                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 420                         "leng  ntw timestamp        bi->skb\n");
 421
 422                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 423                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 424                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 425                         u0 = (struct my_u0 *)tx_desc;
 426                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 427                                 " %04X  %p %016llX %p", i,
 428                                 le64_to_cpu(u0->a),
 429                                 le64_to_cpu(u0->b),
 430                                 (u64)tx_buffer_info->dma,
 431                                 tx_buffer_info->length,
 432                                 tx_buffer_info->next_to_watch,
 433                                 (u64)tx_buffer_info->time_stamp,
 434                                 tx_buffer_info->skb);
 435                         if (i == tx_ring->next_to_use &&
 436                                 i == tx_ring->next_to_clean)
 437                                 pr_cont(" NTC/U\n");
 438                         else if (i == tx_ring->next_to_use)
 439                                 pr_cont(" NTU\n");
 440                         else if (i == tx_ring->next_to_clean)
 441                                 pr_cont(" NTC\n");
 442                         else
 443                                 pr_cont("\n");
 444
 445                         if (netif_msg_pktdata(adapter) &&
 446                                 tx_buffer_info->dma != 0)
 447                                 print_hex_dump(KERN_INFO, "",
 448                                         DUMP_PREFIX_ADDRESS, 16, 1,
 449                                         phys_to_virt(tx_buffer_info->dma),
 450                                         tx_buffer_info->length, true);
 451                 }
 452         }
 453
 454         /* Print RX Rings Summary */
 455 rx_ring_summary:
 456         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 457         pr_info("Queue [NTU] [NTC]\n");
 458         for (n = 0; n < adapter->num_rx_queues; n++) {
 459                 rx_ring = adapter->rx_ring[n];
 460                 pr_info("%5d %5X %5X\n",
 461                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 462         }
 463
 464         /* Print RX Rings */
 465         if (!netif_msg_rx_status(adapter))
 466                 goto exit;
 467
 468         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 469
 470         /* Advanced Receive Descriptor (Read) Format
 471          *    63                                           1        0
 472          *    +-----------------------------------------------------+
 473          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 474          *    +----------------------------------------------+------+
 475          *  8 |       Header Buffer Address [63:1]           |  DD  |
 476          *    +-----------------------------------------------------+
 477          *
 478          *
 479          * Advanced Receive Descriptor (Write-Back) Format
 480          *
 481          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 482          *   +------------------------------------------------------+
 483          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 484          *   | Checksum   Ident  |   |           |    | Type | Type |
 485          *   +------------------------------------------------------+
 486          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 487          *   +------------------------------------------------------+
 488          *   63       48 47    32 31            20 19               0
 489          */
 490         for (n = 0; n < adapter->num_rx_queues; n++) {
 491                 rx_ring = adapter->rx_ring[n];
 492                 pr_info("------------------------------------\n");
 493                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 494                 pr_info("------------------------------------\n");
 495                 pr_info("R  [desc]      [ PktBuf     A0] "
 496                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 497                         "<-- Adv Rx Read format\n");
 498                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 499                         "[vl er S cks ln] ---------------- [bi->skb] "
 500                         "<-- Adv Rx Write-Back format\n");
 501
 502                 for (i = 0; i < rx_ring->count; i++) {
 503                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 504                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 505                         u0 = (struct my_u0 *)rx_desc;
 506                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 507                         if (staterr & IXGBE_RXD_STAT_DD) {
 508                                 /* Descriptor Done */
 509                                 pr_info("RWB[0x%03X]     %016llX "
 510                                         "%016llX ---------------- %p", i,
 511                                         le64_to_cpu(u0->a),
 512                                         le64_to_cpu(u0->b),
 513                                         rx_buffer_info->skb);
 514                         } else {
 515                                 pr_info("R  [0x%03X]     %016llX "
 516                                         "%016llX %016llX %p", i,
 517                                         le64_to_cpu(u0->a),
 518                                         le64_to_cpu(u0->b),
 519                                         (u64)rx_buffer_info->dma,
 520                                         rx_buffer_info->skb);
 521
 522                                 if (netif_msg_pktdata(adapter)) {
 523                                         print_hex_dump(KERN_INFO, "",
 524                                            DUMP_PREFIX_ADDRESS, 16, 1,
 525                                            phys_to_virt(rx_buffer_info->dma),
 526                                            rx_ring->rx_buf_len, true);
 527
 528                                         if (rx_ring->rx_buf_len
 529                                                 < IXGBE_RXBUFFER_2048)
 530                                                 print_hex_dump(KERN_INFO, "",
 531                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 532                                                   phys_to_virt(
 533                                                     rx_buffer_info->page_dma +
 534                                                     rx_buffer_info->page_offset
 535                                                   ),
 536                                                   PAGE_SIZE/2, true);
 537                                 }
 538                         }
 539
 540                         if (i == rx_ring->next_to_use)
 541                                 pr_cont(" NTU\n");
 542                         else if (i == rx_ring->next_to_clean)
 543                                 pr_cont(" NTC\n");
 544                         else
 545                                 pr_cont("\n");
 546
 547                 }
 548         }
 549
 550 exit:
 551         return;
 552 }
 553
 554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 555 {
 556         u32 ctrl_ext;
 557
 558         /* Let firmware take over control of h/w */
 559         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 560         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 561                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 562 }
 563
 564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 565 {
 566         u32 ctrl_ext;
 567
 568         /* Let firmware know the driver has taken over */
 569         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 570         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 571                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 572 }
 573
 574 /*
 575  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 576  * @adapter: pointer to adapter struct
 577  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 578  * @queue: queue to map the corresponding interrupt to
 579  * @msix_vector: the vector to map to the corresponding queue
 580  *
 581  */
 582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 583                            u8 queue, u8 msix_vector)
 584 {
 585         u32 ivar, index;
 586         struct ixgbe_hw *hw = &adapter->hw;
 587         switch (hw->mac.type) {
 588         case ixgbe_mac_82598EB:
 589                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 590                 if (direction == -1)
 591                         direction = 0;
 592                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 593                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 594                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 595                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 596                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 597                 break;
 598         case ixgbe_mac_82599EB:
 599         case ixgbe_mac_X540:
 600                 if (direction == -1) {
 601                         /* other causes */
 602                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 603                         index = ((queue & 1) * 8);
 604                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 605                         ivar &= ~(0xFF << index);
 606                         ivar |= (msix_vector << index);
 607                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 608                         break;
 609                 } else {
 610                         /* tx or rx causes */
 611                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 612                         index = ((16 * (queue & 1)) + (8 * direction));
 613                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 614                         ivar &= ~(0xFF << index);
 615                         ivar |= (msix_vector << index);
 616                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 617                         break;
 618                 }
 619         default:
 620                 break;
 621         }
 622 }
 623
 624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 625                                           u64 qmask)
 626 {
 627         u32 mask;
 628
 629         switch (adapter->hw.mac.type) {
 630         case ixgbe_mac_82598EB:
 631                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 632                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 633                 break;
 634         case ixgbe_mac_82599EB:
 635         case ixgbe_mac_X540:
 636                 mask = (qmask & 0xFFFFFFFF);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 638                 mask = (qmask >> 32);
 639                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 640                 break;
 641         default:
 642                 break;
 643         }
 644 }
 645
 646 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 647                                            struct ixgbe_tx_buffer *tx_buffer)
 648 {
 649         if (tx_buffer->dma) {
 650                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 651                         dma_unmap_page(ring->dev,
 652                                        tx_buffer->dma,
 653                                        tx_buffer->length,
 654                                        DMA_TO_DEVICE);
 655                 else
 656                         dma_unmap_single(ring->dev,
 657                                          tx_buffer->dma,
 658                                          tx_buffer->length,
 659                                          DMA_TO_DEVICE);
 660         }
 661         tx_buffer->dma = 0;
 662 }
 663
 664 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 665                                       struct ixgbe_tx_buffer *tx_buffer_info)
 666 {
 667         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 668         if (tx_buffer_info->skb)
 669                 dev_kfree_skb_any(tx_buffer_info->skb);
 670         tx_buffer_info->skb = NULL;
 671         /* tx_buffer_info must be completely set up in the transmit path */
 672 }
 673
 674 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 675 {
 676         struct ixgbe_hw *hw = &adapter->hw;
 677         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 678         u32 data = 0;
 679         u32 xoff[8] = {0};
 680         int i;
 681
 682         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 683             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 684                 switch (hw->mac.type) {
 685                 case ixgbe_mac_82598EB:
 686                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 687                         break;
 688                 default:
 689                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 690                 }
 691                 hwstats->lxoffrxc += data;
 692
 693                 /* refill credits (no tx hang) if we received xoff */
 694                 if (!data)
 695                         return;
 696
 697                 for (i = 0; i < adapter->num_tx_queues; i++)
 698                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 699                                   &adapter->tx_ring[i]->state);
 700                 return;
 701         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 702                 return;
 703
 704         /* update stats for each tc, only valid with PFC enabled */
 705         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 706                 switch (hw->mac.type) {
 707                 case ixgbe_mac_82598EB:
 708                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 709                         break;
 710                 default:
 711                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 712                 }
 713                 hwstats->pxoffrxc[i] += xoff[i];
 714         }
 715
 716         /* disarm tx queues that have received xoff frames */
 717         for (i = 0; i < adapter->num_tx_queues; i++) {
 718                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 719                 u8 tc = tx_ring->dcb_tc;
 720
 721                 if (xoff[tc])
 722                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 723         }
 724 }
 725
 726 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 727 {
 728         return ring->tx_stats.completed;
 729 }
 730
 731 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 732 {
 733         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 734         struct ixgbe_hw *hw = &adapter->hw;
 735
 736         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 737         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 738
 739         if (head != tail)
 740                 return (head < tail) ?
 741                         tail - head : (tail + ring->count - head);
 742
 743         return 0;
 744 }
 745
 746 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 747 {
 748         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 749         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 750         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 751         bool ret = false;
 752
 753         clear_check_for_tx_hang(tx_ring);
 754
 755         /*
 756          * Check for a hung queue, but be thorough. This verifies
 757          * that a transmit has been completed since the previous
 758          * check AND there is at least one packet pending. The
 759          * ARMED bit is set to indicate a potential hang. The
 760          * bit is cleared if a pause frame is received to remove
 761          * false hang detection due to PFC or 802.3x frames. By
 762          * requiring this to fail twice we avoid races with
 763          * pfc clearing the ARMED bit and conditions where we
 764          * run the check_tx_hang logic with a transmit completion
 765          * pending but without time to complete it yet.
 766          */
 767         if ((tx_done_old == tx_done) && tx_pending) {
 768                 /* make sure it is true for two checks in a row */
 769                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 770                                        &tx_ring->state);
 771         } else {
 772                 /* update completed stats and continue */
 773                 tx_ring->tx_stats.tx_done_old = tx_done;
 774                 /* reset the countdown */
 775                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 776         }
 777
 778         return ret;
 779 }
 780
 781 /**
 782  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 783  * @adapter: driver private struct
 784  **/
 785 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 786 {
 787
 788         /* Do the reset outside of interrupt context */
 789         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 790                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 791                 ixgbe_service_event_schedule(adapter);
 792         }
 793 }
 794
 795 /**
 796  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 797  * @q_vector: structure containing interrupt and ring information
 798  * @tx_ring: tx ring to clean
 799  **/
 800 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 801                                struct ixgbe_ring *tx_ring)
 802 {
 803         struct ixgbe_adapter *adapter = q_vector->adapter;
 804         struct ixgbe_tx_buffer *tx_buffer;
 805         union ixgbe_adv_tx_desc *tx_desc;
 806         unsigned int total_bytes = 0, total_packets = 0;
 807         unsigned int budget = q_vector->tx.work_limit;
 808         u16 i = tx_ring->next_to_clean;
 809
 810         tx_buffer = &tx_ring->tx_buffer_info[i];
 811         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 812
 813         for (; budget; budget--) {
 814                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 815
 816                 /* if next_to_watch is not set then there is no work pending */
 817                 if (!eop_desc)
 818                         break;
 819
 820                 /* if DD is not set pending work has not been completed */
 821                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 822                         break;
 823
 824                 /* count the packet as being completed */
 825                 tx_ring->tx_stats.completed++;
 826
 827                 /* clear next_to_watch to prevent false hangs */
 828                 tx_buffer->next_to_watch = NULL;
 829
 830                 /* prevent any other reads prior to eop_desc being verified */
 831                 rmb();
 832
 833                 do {
 834                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 835                         tx_desc->wb.status = 0;
 836                         if (likely(tx_desc == eop_desc)) {
 837                                 eop_desc = NULL;
 838                                 dev_kfree_skb_any(tx_buffer->skb);
 839                                 tx_buffer->skb = NULL;
 840
 841                                 total_bytes += tx_buffer->bytecount;
 842                                 total_packets += tx_buffer->gso_segs;
 843                         }
 844
 845                         tx_buffer++;
 846                         tx_desc++;
 847                         i++;
 848                         if (unlikely(i == tx_ring->count)) {
 849                                 i = 0;
 850
 851                                 tx_buffer = tx_ring->tx_buffer_info;
 852                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 853                         }
 854
 855                 } while (eop_desc);
 856         }
 857
 858         tx_ring->next_to_clean = i;
 859         u64_stats_update_begin(&tx_ring->syncp);
 860         tx_ring->stats.bytes += total_bytes;
 861         tx_ring->stats.packets += total_packets;
 862         u64_stats_update_end(&tx_ring->syncp);
 863         q_vector->tx.total_bytes += total_bytes;
 864         q_vector->tx.total_packets += total_packets;
 865
 866         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 867                 /* schedule immediate reset if we believe we hung */
 868                 struct ixgbe_hw *hw = &adapter->hw;
 869                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 870                 e_err(drv, "Detected Tx Unit Hang\n"
 871                         "  Tx Queue             <%d>\n"
 872                         "  TDH, TDT             <%x>, <%x>\n"
 873                         "  next_to_use          <%x>\n"
 874                         "  next_to_clean        <%x>\n"
 875                         "tx_buffer_info[next_to_clean]\n"
 876                         "  time_stamp           <%lx>\n"
 877                         "  jiffies              <%lx>\n",
 878                         tx_ring->queue_index,
 879                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 880                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 881                         tx_ring->next_to_use, i,
 882                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 883
 884                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 885
 886                 e_info(probe,
 887                        "tx hang %d detected on queue %d, resetting adapter\n",
 888                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 889
 890                 /* schedule immediate reset if we believe we hung */
 891                 ixgbe_tx_timeout_reset(adapter);
 892
 893                 /* the adapter is about to reset, no point in enabling stuff */
 894                 return true;
 895         }
 896
 897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 898         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 899                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 900                 /* Make sure that anybody stopping the queue after this
 901                  * sees the new next_to_clean.
 902                  */
 903                 smp_mb();
 904                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 905                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 906                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 907                         ++tx_ring->tx_stats.restart_queue;
 908                 }
 909         }
 910
 911         return !!budget;
 912 }
 913
 914 #ifdef CONFIG_IXGBE_DCA
 915 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 916                                 struct ixgbe_ring *rx_ring,
 917                                 int cpu)
 918 {
 919         struct ixgbe_hw *hw = &adapter->hw;
 920         u32 rxctrl;
 921         u8 reg_idx = rx_ring->reg_idx;
 922
 923         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 924         switch (hw->mac.type) {
 925         case ixgbe_mac_82598EB:
 926                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 927                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 928                 break;
 929         case ixgbe_mac_82599EB:
 930         case ixgbe_mac_X540:
 931                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 932                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 933                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 934                 break;
 935         default:
 936                 break;
 937         }
 938         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 939         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 940         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 941         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 942 }
 943
 944 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 945                                 struct ixgbe_ring *tx_ring,
 946                                 int cpu)
 947 {
 948         struct ixgbe_hw *hw = &adapter->hw;
 949         u32 txctrl;
 950         u8 reg_idx = tx_ring->reg_idx;
 951
 952         switch (hw->mac.type) {
 953         case ixgbe_mac_82598EB:
 954                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 955                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 956                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 957                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 958                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 959                 break;
 960         case ixgbe_mac_82599EB:
 961         case ixgbe_mac_X540:
 962                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 963                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 964                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 965                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 966                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 967                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 968                 break;
 969         default:
 970                 break;
 971         }
 972 }
 973
 974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 975 {
 976         struct ixgbe_adapter *adapter = q_vector->adapter;
 977         struct ixgbe_ring *ring;
 978         int cpu = get_cpu();
 979
 980         if (q_vector->cpu == cpu)
 981                 goto out_no_update;
 982
 983         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 984                 ixgbe_update_tx_dca(adapter, ring, cpu);
 985
 986         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 987                 ixgbe_update_rx_dca(adapter, ring, cpu);
 988
 989         q_vector->cpu = cpu;
 990 out_no_update:
 991         put_cpu();
 992 }
 993
 994 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 995 {
 996         int num_q_vectors;
 997         int i;
 998
 999         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000                 return;
1001
1002         /* always use CB2 mode, difference is masked in the CB driver */
1003         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
1005         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007         else
1008                 num_q_vectors = 1;
1009
1010         for (i = 0; i < num_q_vectors; i++) {
1011                 adapter->q_vector[i]->cpu = -1;
1012                 ixgbe_update_dca(adapter->q_vector[i]);
1013         }
1014 }
1015
1016 static int __ixgbe_notify_dca(struct device *dev, void *data)
1017 {
1018         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1019         unsigned long event = *(unsigned long *)data;
1020
1021         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1022                 return 0;
1023
1024         switch (event) {
1025         case DCA_PROVIDER_ADD:
1026                 /* if we're already enabled, don't do it again */
1027                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028                         break;
1029                 if (dca_add_requester(dev) == 0) {
1030                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1031                         ixgbe_setup_dca(adapter);
1032                         break;
1033                 }
1034                 /* Fall Through since DCA is disabled. */
1035         case DCA_PROVIDER_REMOVE:
1036                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037                         dca_remove_requester(dev);
1038                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040                 }
1041                 break;
1042         }
1043
1044         return 0;
1045 }
1046 #endif /* CONFIG_IXGBE_DCA */
1047
1048 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1049                                  struct sk_buff *skb)
1050 {
1051         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1052 }
1053
1054 /**
1055  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1056  * @adapter: address of board private structure
1057  * @rx_desc: advanced rx descriptor
1058  *
1059  * Returns : true if it is FCoE pkt
1060  */
1061 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1062                                     union ixgbe_adv_rx_desc *rx_desc)
1063 {
1064         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1065
1066         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1067                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1068                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1069                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1070 }
1071
1072 /**
1073  * ixgbe_receive_skb - Send a completed packet up the stack
1074  * @adapter: board private structure
1075  * @skb: packet to send up
1076  * @status: hardware indication of status of receive
1077  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1078  * @rx_desc: rx descriptor
1079  **/
1080 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1081                               struct sk_buff *skb, u8 status,
1082                               struct ixgbe_ring *ring,
1083                               union ixgbe_adv_rx_desc *rx_desc)
1084 {
1085         struct ixgbe_adapter *adapter = q_vector->adapter;
1086         struct napi_struct *napi = &q_vector->napi;
1087         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1088         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1089
1090         if (is_vlan && (tag & VLAN_VID_MASK))
1091                 __vlan_hwaccel_put_tag(skb, tag);
1092
1093         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1094                 napi_gro_receive(napi, skb);
1095         else
1096                 netif_rx(skb);
1097 }
1098
1099 /**
1100  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1101  * @adapter: address of board private structure
1102  * @status_err: hardware indication of status of receive
1103  * @skb: skb currently being received and modified
1104  * @status_err: status error value of last descriptor in packet
1105  **/
1106 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1107                                      union ixgbe_adv_rx_desc *rx_desc,
1108                                      struct sk_buff *skb,
1109                                      u32 status_err)
1110 {
1111         skb->ip_summed = CHECKSUM_NONE;
1112
1113         /* Rx csum disabled */
1114         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1115                 return;
1116
1117         /* if IP and error */
1118         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1119             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1120                 adapter->hw_csum_rx_error++;
1121                 return;
1122         }
1123
1124         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1125                 return;
1126
1127         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1128                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1129
1130                 /*
1131                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1132                  * checksum errors.
1133                  */
1134                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1135                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1136                         return;
1137
1138                 adapter->hw_csum_rx_error++;
1139                 return;
1140         }
1141
1142         /* It must be a TCP or UDP packet with a valid checksum */
1143         skb->ip_summed = CHECKSUM_UNNECESSARY;
1144 }
1145
1146 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1147 {
1148         /*
1149          * Force memory writes to complete before letting h/w
1150          * know there are new descriptors to fetch.  (Only
1151          * applicable for weak-ordered memory model archs,
1152          * such as IA-64).
1153          */
1154         wmb();
1155         writel(val, rx_ring->tail);
1156 }
1157
1158 /**
1159  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1160  * @rx_ring: ring to place buffers on
1161  * @cleaned_count: number of buffers to replace
1162  **/
1163 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1164 {
1165         union ixgbe_adv_rx_desc *rx_desc;
1166         struct ixgbe_rx_buffer *bi;
1167         struct sk_buff *skb;
1168         u16 i = rx_ring->next_to_use;
1169
1170         /* do nothing if no valid netdev defined */
1171         if (!rx_ring->netdev)
1172                 return;
1173
1174         while (cleaned_count--) {
1175                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1176                 bi = &rx_ring->rx_buffer_info[i];
1177                 skb = bi->skb;
1178
1179                 if (!skb) {
1180                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1181                                                         rx_ring->rx_buf_len);
1182                         if (!skb) {
1183                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1184                                 goto no_buffers;
1185                         }
1186                         /* initialize queue mapping */
1187                         skb_record_rx_queue(skb, rx_ring->queue_index);
1188                         bi->skb = skb;
1189                 }
1190
1191                 if (!bi->dma) {
1192                         bi->dma = dma_map_single(rx_ring->dev,
1193                                                  skb->data,
1194                                                  rx_ring->rx_buf_len,
1195                                                  DMA_FROM_DEVICE);
1196                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1197                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1198                                 bi->dma = 0;
1199                                 goto no_buffers;
1200                         }
1201                 }
1202
1203                 if (ring_is_ps_enabled(rx_ring)) {
1204                         if (!bi->page) {
1205                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1206                                 if (!bi->page) {
1207                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1208                                         goto no_buffers;
1209                                 }
1210                         }
1211
1212                         if (!bi->page_dma) {
1213                                 /* use a half page if we're re-using */
1214                                 bi->page_offset ^= PAGE_SIZE / 2;
1215                                 bi->page_dma = dma_map_page(rx_ring->dev,
1216                                                             bi->page,
1217                                                             bi->page_offset,
1218                                                             PAGE_SIZE / 2,
1219                                                             DMA_FROM_DEVICE);
1220                                 if (dma_mapping_error(rx_ring->dev,
1221                                                       bi->page_dma)) {
1222                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1223                                         bi->page_dma = 0;
1224                                         goto no_buffers;
1225                                 }
1226                         }
1227
1228                         /* Refresh the desc even if buffer_addrs didn't change
1229                          * because each write-back erases this info. */
1230                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1231                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1232                 } else {
1233                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1234                         rx_desc->read.hdr_addr = 0;
1235                 }
1236
1237                 i++;
1238                 if (i == rx_ring->count)
1239                         i = 0;
1240         }
1241
1242 no_buffers:
1243         if (rx_ring->next_to_use != i) {
1244                 rx_ring->next_to_use = i;
1245                 ixgbe_release_rx_desc(rx_ring, i);
1246         }
1247 }
1248
1249 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1250 {
1251         /* HW will not DMA in data larger than the given buffer, even if it
1252          * parses the (NFS, of course) header to be larger.  In that case, it
1253          * fills the header buffer and spills the rest into the page.
1254          */
1255         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1256         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1257                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1258         if (hlen > IXGBE_RX_HDR_SIZE)
1259                 hlen = IXGBE_RX_HDR_SIZE;
1260         return hlen;
1261 }
1262
1263 /**
1264  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1265  * @skb: pointer to the last skb in the rsc queue
1266  *
1267  * This function changes a queue full of hw rsc buffers into a completed
1268  * packet.  It uses the ->prev pointers to find the first packet and then
1269  * turns it into the frag list owner.
1270  **/
1271 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1272 {
1273         unsigned int frag_list_size = 0;
1274         unsigned int skb_cnt = 1;
1275
1276         while (skb->prev) {
1277                 struct sk_buff *prev = skb->prev;
1278                 frag_list_size += skb->len;
1279                 skb->prev = NULL;
1280                 skb = prev;
1281                 skb_cnt++;
1282         }
1283
1284         skb_shinfo(skb)->frag_list = skb->next;
1285         skb->next = NULL;
1286         skb->len += frag_list_size;
1287         skb->data_len += frag_list_size;
1288         skb->truesize += frag_list_size;
1289         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1290
1291         return skb;
1292 }
1293
1294 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1295 {
1296         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1297                 IXGBE_RXDADV_RSCCNT_MASK);
1298 }
1299
1300 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1301                                struct ixgbe_ring *rx_ring,
1302                                int budget)
1303 {
1304         struct ixgbe_adapter *adapter = q_vector->adapter;
1305         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1306         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1307         struct sk_buff *skb;
1308         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1309         const int current_node = numa_node_id();
1310 #ifdef IXGBE_FCOE
1311         int ddp_bytes = 0;
1312 #endif /* IXGBE_FCOE */
1313         u32 staterr;
1314         u16 i;
1315         u16 cleaned_count = 0;
1316         bool pkt_is_rsc = false;
1317
1318         i = rx_ring->next_to_clean;
1319         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1320         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1321
1322         while (staterr & IXGBE_RXD_STAT_DD) {
1323                 u32 upper_len = 0;
1324
1325                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1326
1327                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1328
1329                 skb = rx_buffer_info->skb;
1330                 rx_buffer_info->skb = NULL;
1331                 prefetch(skb->data);
1332
1333                 if (ring_is_rsc_enabled(rx_ring))
1334                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1335
1336                 /* if this is a skb from previous receive DMA will be 0 */
1337                 if (rx_buffer_info->dma) {
1338                         u16 hlen;
1339                         if (pkt_is_rsc &&
1340                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1341                             !skb->prev) {
1342                                 /*
1343                                  * When HWRSC is enabled, delay unmapping
1344                                  * of the first packet. It carries the
1345                                  * header information, HW may still
1346                                  * access the header after the writeback.
1347                                  * Only unmap it when EOP is reached
1348                                  */
1349                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1350                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1351                         } else {
1352                                 dma_unmap_single(rx_ring->dev,
1353                                                  rx_buffer_info->dma,
1354                                                  rx_ring->rx_buf_len,
1355                                                  DMA_FROM_DEVICE);
1356                         }
1357                         rx_buffer_info->dma = 0;
1358
1359                         if (ring_is_ps_enabled(rx_ring)) {
1360                                 hlen = ixgbe_get_hlen(rx_desc);
1361                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1362                         } else {
1363                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1364                         }
1365
1366                         skb_put(skb, hlen);
1367                 } else {
1368                         /* assume packet split since header is unmapped */
1369                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1370                 }
1371
1372                 if (upper_len) {
1373                         dma_unmap_page(rx_ring->dev,
1374                                        rx_buffer_info->page_dma,
1375                                        PAGE_SIZE / 2,
1376                                        DMA_FROM_DEVICE);
1377                         rx_buffer_info->page_dma = 0;
1378                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1379                                            rx_buffer_info->page,
1380                                            rx_buffer_info->page_offset,
1381                                            upper_len);
1382
1383                         if ((page_count(rx_buffer_info->page) == 1) &&
1384                             (page_to_nid(rx_buffer_info->page) == current_node))
1385                                 get_page(rx_buffer_info->page);
1386                         else
1387                                 rx_buffer_info->page = NULL;
1388
1389                         skb->len += upper_len;
1390                         skb->data_len += upper_len;
1391                         skb->truesize += upper_len;
1392                 }
1393
1394                 i++;
1395                 if (i == rx_ring->count)
1396                         i = 0;
1397
1398                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1399                 prefetch(next_rxd);
1400                 cleaned_count++;
1401
1402                 if (pkt_is_rsc) {
1403                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1404                                      IXGBE_RXDADV_NEXTP_SHIFT;
1405                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1406                 } else {
1407                         next_buffer = &rx_ring->rx_buffer_info[i];
1408                 }
1409
1410                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1411                         if (ring_is_ps_enabled(rx_ring)) {
1412                                 rx_buffer_info->skb = next_buffer->skb;
1413                                 rx_buffer_info->dma = next_buffer->dma;
1414                                 next_buffer->skb = skb;
1415                                 next_buffer->dma = 0;
1416                         } else {
1417                                 skb->next = next_buffer->skb;
1418                                 skb->next->prev = skb;
1419                         }
1420                         rx_ring->rx_stats.non_eop_descs++;
1421                         goto next_desc;
1422                 }
1423
1424                 if (skb->prev) {
1425                         skb = ixgbe_transform_rsc_queue(skb);
1426                         /* if we got here without RSC the packet is invalid */
1427                         if (!pkt_is_rsc) {
1428                                 __pskb_trim(skb, 0);
1429                                 rx_buffer_info->skb = skb;
1430                                 goto next_desc;
1431                         }
1432                 }
1433
1434                 if (ring_is_rsc_enabled(rx_ring)) {
1435                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1436                                 dma_unmap_single(rx_ring->dev,
1437                                                  IXGBE_RSC_CB(skb)->dma,
1438                                                  rx_ring->rx_buf_len,
1439                                                  DMA_FROM_DEVICE);
1440                                 IXGBE_RSC_CB(skb)->dma = 0;
1441                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1442                         }
1443                 }
1444                 if (pkt_is_rsc) {
1445                         if (ring_is_ps_enabled(rx_ring))
1446                                 rx_ring->rx_stats.rsc_count +=
1447                                         skb_shinfo(skb)->nr_frags;
1448                         else
1449                                 rx_ring->rx_stats.rsc_count +=
1450                                         IXGBE_RSC_CB(skb)->skb_cnt;
1451                         rx_ring->rx_stats.rsc_flush++;
1452                 }
1453
1454                 /* ERR_MASK will only have valid bits if EOP set */
1455                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1456                         dev_kfree_skb_any(skb);
1457                         goto next_desc;
1458                 }
1459
1460                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1461                 if (adapter->netdev->features & NETIF_F_RXHASH)
1462                         ixgbe_rx_hash(rx_desc, skb);
1463
1464                 /* probably a little skewed due to removing CRC */
1465                 total_rx_bytes += skb->len;
1466                 total_rx_packets++;
1467
1468                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1469 #ifdef IXGBE_FCOE
1470                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1471                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1472                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1473                                                    staterr);
1474                         if (!ddp_bytes) {
1475                                 dev_kfree_skb_any(skb);
1476                                 goto next_desc;
1477                         }
1478                 }
1479 #endif /* IXGBE_FCOE */
1480                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1481
1482                 budget--;
1483 next_desc:
1484                 rx_desc->wb.upper.status_error = 0;
1485
1486                 if (!budget)
1487                         break;
1488
1489                 /* return some buffers to hardware, one at a time is too slow */
1490                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1491                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1492                         cleaned_count = 0;
1493                 }
1494
1495                 /* use prefetched values */
1496                 rx_desc = next_rxd;
1497                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1498         }
1499
1500         rx_ring->next_to_clean = i;
1501         cleaned_count = ixgbe_desc_unused(rx_ring);
1502
1503         if (cleaned_count)
1504                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1505
1506 #ifdef IXGBE_FCOE
1507         /* include DDPed FCoE data */
1508         if (ddp_bytes > 0) {
1509                 unsigned int mss;
1510
1511                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1512                         sizeof(struct fc_frame_header) -
1513                         sizeof(struct fcoe_crc_eof);
1514                 if (mss > 512)
1515                         mss &= ~511;
1516                 total_rx_bytes += ddp_bytes;
1517                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1518         }
1519 #endif /* IXGBE_FCOE */
1520
1521         u64_stats_update_begin(&rx_ring->syncp);
1522         rx_ring->stats.packets += total_rx_packets;
1523         rx_ring->stats.bytes += total_rx_bytes;
1524         u64_stats_update_end(&rx_ring->syncp);
1525         q_vector->rx.total_packets += total_rx_packets;
1526         q_vector->rx.total_bytes += total_rx_bytes;
1527
1528         return !!budget;
1529 }
1530
1531 /**
1532  * ixgbe_configure_msix - Configure MSI-X hardware
1533  * @adapter: board private structure
1534  *
1535  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1536  * interrupts.
1537  **/
1538 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1539 {
1540         struct ixgbe_q_vector *q_vector;
1541         int q_vectors, v_idx;
1542         u32 mask;
1543
1544         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1545
1546         /*
1547          * Populate the IVAR table and set the ITR values to the
1548          * corresponding register.
1549          */
1550         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1551                 struct ixgbe_ring *ring;
1552                 q_vector = adapter->q_vector[v_idx];
1553
1554                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1555                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1556
1557                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1558                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1559
1560                 if (q_vector->tx.ring && !q_vector->rx.ring)
1561                         /* tx only */
1562                         q_vector->eitr = adapter->tx_eitr_param;
1563                 else if (q_vector->rx.ring)
1564                         /* rx or mixed */
1565                         q_vector->eitr = adapter->rx_eitr_param;
1566
1567                 ixgbe_write_eitr(q_vector);
1568         }
1569
1570         switch (adapter->hw.mac.type) {
1571         case ixgbe_mac_82598EB:
1572                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1573                                v_idx);
1574                 break;
1575         case ixgbe_mac_82599EB:
1576         case ixgbe_mac_X540:
1577                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1578                 break;
1579
1580         default:
1581                 break;
1582         }
1583         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1584
1585         /* set up to autoclear timer, and the vectors */
1586         mask = IXGBE_EIMS_ENABLE_MASK;
1587         if (adapter->num_vfs)
1588                 mask &= ~(IXGBE_EIMS_OTHER |
1589                           IXGBE_EIMS_MAILBOX |
1590                           IXGBE_EIMS_LSC);
1591         else
1592                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1593         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1594 }
1595
1596 enum latency_range {
1597         lowest_latency = 0,
1598         low_latency = 1,
1599         bulk_latency = 2,
1600         latency_invalid = 255
1601 };
1602
1603 /**
1604  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1605  * @q_vector: structure containing interrupt and ring information
1606  * @ring_container: structure containing ring performance data
1607  *
1608  *      Stores a new ITR value based on packets and byte
1609  *      counts during the last interrupt.  The advantage of per interrupt
1610  *      computation is faster updates and more accurate ITR for the current
1611  *      traffic pattern.  Constants in this function were computed
1612  *      based on theoretical maximum wire speed and thresholds were set based
1613  *      on testing data as well as attempting to minimize response time
1614  *      while increasing bulk throughput.
1615  *      this functionality is controlled by the InterruptThrottleRate module
1616  *      parameter (see ixgbe_param.c)
1617  **/
1618 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1619                              struct ixgbe_ring_container *ring_container)
1620 {
1621         u64 bytes_perint;
1622         struct ixgbe_adapter *adapter = q_vector->adapter;
1623         int bytes = ring_container->total_bytes;
1624         int packets = ring_container->total_packets;
1625         u32 timepassed_us;
1626         u8 itr_setting = ring_container->itr;
1627
1628         if (packets == 0)
1629                 return;
1630
1631         /* simple throttlerate management
1632          *    0-20MB/s lowest (100000 ints/s)
1633          *   20-100MB/s low   (20000 ints/s)
1634          *  100-1249MB/s bulk (8000 ints/s)
1635          */
1636         /* what was last interrupt timeslice? */
1637         timepassed_us = 1000000/q_vector->eitr;
1638         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1639
1640         switch (itr_setting) {
1641         case lowest_latency:
1642                 if (bytes_perint > adapter->eitr_low)
1643                         itr_setting = low_latency;
1644                 break;
1645         case low_latency:
1646                 if (bytes_perint > adapter->eitr_high)
1647                         itr_setting = bulk_latency;
1648                 else if (bytes_perint <= adapter->eitr_low)
1649                         itr_setting = lowest_latency;
1650                 break;
1651         case bulk_latency:
1652                 if (bytes_perint <= adapter->eitr_high)
1653                         itr_setting = low_latency;
1654                 break;
1655         }
1656
1657         /* clear work counters since we have the values we need */
1658         ring_container->total_bytes = 0;
1659         ring_container->total_packets = 0;
1660
1661         /* write updated itr to ring container */
1662         ring_container->itr = itr_setting;
1663 }
1664
1665 /**
1666  * ixgbe_write_eitr - write EITR register in hardware specific way
1667  * @q_vector: structure containing interrupt and ring information
1668  *
1669  * This function is made to be called by ethtool and by the driver
1670  * when it needs to update EITR registers at runtime.  Hardware
1671  * specific quirks/differences are taken care of here.
1672  */
1673 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1674 {
1675         struct ixgbe_adapter *adapter = q_vector->adapter;
1676         struct ixgbe_hw *hw = &adapter->hw;
1677         int v_idx = q_vector->v_idx;
1678         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1679
1680         switch (adapter->hw.mac.type) {
1681         case ixgbe_mac_82598EB:
1682                 /* must write high and low 16 bits to reset counter */
1683                 itr_reg |= (itr_reg << 16);
1684                 break;
1685         case ixgbe_mac_82599EB:
1686         case ixgbe_mac_X540:
1687                 /*
1688                  * 82599 and X540 can support a value of zero, so allow it for
1689                  * max interrupt rate, but there is an errata where it can
1690                  * not be zero with RSC
1691                  */
1692                 if (itr_reg == 8 &&
1693                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1694                         itr_reg = 0;
1695
1696                 /*
1697                  * set the WDIS bit to not clear the timer bits and cause an
1698                  * immediate assertion of the interrupt
1699                  */
1700                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1701                 break;
1702         default:
1703                 break;
1704         }
1705         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1706 }
1707
1708 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1709 {
1710         u32 new_itr = q_vector->eitr;
1711         u8 current_itr;
1712
1713         ixgbe_update_itr(q_vector, &q_vector->tx);
1714         ixgbe_update_itr(q_vector, &q_vector->rx);
1715
1716         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1717
1718         switch (current_itr) {
1719         /* counts and packets in update_itr are dependent on these numbers */
1720         case lowest_latency:
1721                 new_itr = 100000;
1722                 break;
1723         case low_latency:
1724                 new_itr = 20000; /* aka hwitr = ~200 */
1725                 break;
1726         case bulk_latency:
1727                 new_itr = 8000;
1728                 break;
1729         default:
1730                 break;
1731         }
1732
1733         if (new_itr != q_vector->eitr) {
1734                 /* do an exponential smoothing */
1735                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1736
1737                 /* save the algorithm value here */
1738                 q_vector->eitr = new_itr;
1739
1740                 ixgbe_write_eitr(q_vector);
1741         }
1742 }
1743
1744 /**
1745  * ixgbe_check_overtemp_subtask - check for over tempurature
1746  * @adapter: pointer to adapter
1747  **/
1748 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1749 {
1750         struct ixgbe_hw *hw = &adapter->hw;
1751         u32 eicr = adapter->interrupt_event;
1752
1753         if (test_bit(__IXGBE_DOWN, &adapter->state))
1754                 return;
1755
1756         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1757             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1758                 return;
1759
1760         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1761
1762         switch (hw->device_id) {
1763         case IXGBE_DEV_ID_82599_T3_LOM:
1764                 /*
1765                  * Since the warning interrupt is for both ports
1766                  * we don't have to check if:
1767                  *  - This interrupt wasn't for our port.
1768                  *  - We may have missed the interrupt so always have to
1769                  *    check if we  got a LSC
1770                  */
1771                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1772                     !(eicr & IXGBE_EICR_LSC))
1773                         return;
1774
1775                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1776                         u32 autoneg;
1777                         bool link_up = false;
1778
1779                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1780
1781                         if (link_up)
1782                                 return;
1783                 }
1784
1785                 /* Check if this is not due to overtemp */
1786                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1787                         return;
1788
1789                 break;
1790         default:
1791                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1792                         return;
1793                 break;
1794         }
1795         e_crit(drv,
1796                "Network adapter has been stopped because it has over heated. "
1797                "Restart the computer. If the problem persists, "
1798                "power off the system and replace the adapter\n");
1799
1800         adapter->interrupt_event = 0;
1801 }
1802
1803 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1804 {
1805         struct ixgbe_hw *hw = &adapter->hw;
1806
1807         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1808             (eicr & IXGBE_EICR_GPI_SDP1)) {
1809                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1810                 /* write to clear the interrupt */
1811                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1812         }
1813 }
1814
1815 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1816 {
1817         struct ixgbe_hw *hw = &adapter->hw;
1818
1819         if (eicr & IXGBE_EICR_GPI_SDP2) {
1820                 /* Clear the interrupt */
1821                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1822                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1823                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1824                         ixgbe_service_event_schedule(adapter);
1825                 }
1826         }
1827
1828         if (eicr & IXGBE_EICR_GPI_SDP1) {
1829                 /* Clear the interrupt */
1830                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1831                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1832                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1833                         ixgbe_service_event_schedule(adapter);
1834                 }
1835         }
1836 }
1837
1838 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1839 {
1840         struct ixgbe_hw *hw = &adapter->hw;
1841
1842         adapter->lsc_int++;
1843         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1844         adapter->link_check_timeout = jiffies;
1845         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1846                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1847                 IXGBE_WRITE_FLUSH(hw);
1848                 ixgbe_service_event_schedule(adapter);
1849         }
1850 }
1851
1852 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1853 {
1854         struct ixgbe_adapter *adapter = data;
1855         struct ixgbe_hw *hw = &adapter->hw;
1856         u32 eicr;
1857
1858         /*
1859          * Workaround for Silicon errata.  Use clear-by-write instead
1860          * of clear-by-read.  Reading with EICS will return the
1861          * interrupt causes without clearing, which later be done
1862          * with the write to EICR.
1863          */
1864         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1865         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1866
1867         if (eicr & IXGBE_EICR_LSC)
1868                 ixgbe_check_lsc(adapter);
1869
1870         if (eicr & IXGBE_EICR_MAILBOX)
1871                 ixgbe_msg_task(adapter);
1872
1873         switch (hw->mac.type) {
1874         case ixgbe_mac_82599EB:
1875         case ixgbe_mac_X540:
1876                 /* Handle Flow Director Full threshold interrupt */
1877                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1878                         int reinit_count = 0;
1879                         int i;
1880                         for (i = 0; i < adapter->num_tx_queues; i++) {
1881                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1882                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1883                                                        &ring->state))
1884                                         reinit_count++;
1885                         }
1886                         if (reinit_count) {
1887                                 /* no more flow director interrupts until after init */
1888                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1889                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1890                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1891                                 ixgbe_service_event_schedule(adapter);
1892                         }
1893                 }
1894                 ixgbe_check_sfp_event(adapter, eicr);
1895                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1896                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1897                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1898                                 adapter->interrupt_event = eicr;
1899                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1900                                 ixgbe_service_event_schedule(adapter);
1901                         }
1902                 }
1903                 break;
1904         default:
1905                 break;
1906         }
1907
1908         ixgbe_check_fan_failure(adapter, eicr);
1909
1910         /* re-enable the original interrupt state, no lsc, no queues */
1911         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1912                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1913                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1914
1915         return IRQ_HANDLED;
1916 }
1917
1918 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1919                                            u64 qmask)
1920 {
1921         u32 mask;
1922         struct ixgbe_hw *hw = &adapter->hw;
1923
1924         switch (hw->mac.type) {
1925         case ixgbe_mac_82598EB:
1926                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1927                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1928                 break;
1929         case ixgbe_mac_82599EB:
1930         case ixgbe_mac_X540:
1931                 mask = (qmask & 0xFFFFFFFF);
1932                 if (mask)
1933                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1934                 mask = (qmask >> 32);
1935                 if (mask)
1936                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1937                 break;
1938         default:
1939                 break;
1940         }
1941         /* skip the flush */
1942 }
1943
1944 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1945                                             u64 qmask)
1946 {
1947         u32 mask;
1948         struct ixgbe_hw *hw = &adapter->hw;
1949
1950         switch (hw->mac.type) {
1951         case ixgbe_mac_82598EB:
1952                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1953                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1954                 break;
1955         case ixgbe_mac_82599EB:
1956         case ixgbe_mac_X540:
1957                 mask = (qmask & 0xFFFFFFFF);
1958                 if (mask)
1959                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1960                 mask = (qmask >> 32);
1961                 if (mask)
1962                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1963                 break;
1964         default:
1965                 break;
1966         }
1967         /* skip the flush */
1968 }
1969
1970 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1971 {
1972         struct ixgbe_q_vector *q_vector = data;
1973
1974         /* EIAM disabled interrupts (on this vector) for us */
1975
1976         if (q_vector->rx.ring || q_vector->tx.ring)
1977                 napi_schedule(&q_vector->napi);
1978
1979         return IRQ_HANDLED;
1980 }
1981
1982 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1983                                      int r_idx)
1984 {
1985         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1986         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
1987
1988         rx_ring->q_vector = q_vector;
1989         rx_ring->next = q_vector->rx.ring;
1990         q_vector->rx.ring = rx_ring;
1991         q_vector->rx.count++;
1992 }
1993
1994 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1995                                      int t_idx)
1996 {
1997         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1998         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
1999
2000         tx_ring->q_vector = q_vector;
2001         tx_ring->next = q_vector->tx.ring;
2002         q_vector->tx.ring = tx_ring;
2003         q_vector->tx.count++;
2004         q_vector->tx.work_limit = a->tx_work_limit;
2005 }
2006
2007 /**
2008  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2009  * @adapter: board private structure to initialize
2010  *
2011  * This function maps descriptor rings to the queue-specific vectors
2012  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2013  * one vector per ring/queue, but on a constrained vector budget, we
2014  * group the rings as "efficiently" as possible.  You would add new
2015  * mapping configurations in here.
2016  **/
2017 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2018 {
2019         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2020         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2021         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2022         int v_start = 0;
2023
2024         /* only one q_vector if MSI-X is disabled. */
2025         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2026                 q_vectors = 1;
2027
2028         /*
2029          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2030          * group them so there are multiple queues per vector.
2031          *
2032          * Re-adjusting *qpv takes care of the remainder.
2033          */
2034         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2035                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2036                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2037                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2038         }
2039
2040         /*
2041          * If there are not enough q_vectors for each ring to have it's own
2042          * vector then we must pair up Rx/Tx on a each vector
2043          */
2044         if ((v_start + txr_remaining) > q_vectors)
2045                 v_start = 0;
2046
2047         for (; v_start < q_vectors && txr_remaining; v_start++) {
2048                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2049                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2050                         map_vector_to_txq(adapter, v_start, txr_idx);
2051         }
2052 }
2053
2054 /**
2055  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2056  * @adapter: board private structure
2057  *
2058  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2059  * interrupts from the kernel.
2060  **/
2061 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2062 {
2063         struct net_device *netdev = adapter->netdev;
2064         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2065         int vector, err;
2066         int ri = 0, ti = 0;
2067
2068         for (vector = 0; vector < q_vectors; vector++) {
2069                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2070                 struct msix_entry *entry = &adapter->msix_entries[vector];
2071
2072                 if (q_vector->tx.ring && q_vector->rx.ring) {
2073                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2074                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2075                         ti++;
2076                 } else if (q_vector->rx.ring) {
2077                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2078                                  "%s-%s-%d", netdev->name, "rx", ri++);
2079                 } else if (q_vector->tx.ring) {
2080                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2081                                  "%s-%s-%d", netdev->name, "tx", ti++);
2082                 } else {
2083                         /* skip this unused q_vector */
2084                         continue;
2085                 }
2086                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2087                                   q_vector->name, q_vector);
2088                 if (err) {
2089                         e_err(probe, "request_irq failed for MSIX interrupt "
2090                               "Error: %d\n", err);
2091                         goto free_queue_irqs;
2092                 }
2093                 /* If Flow Director is enabled, set interrupt affinity */
2094                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2095                         /* assign the mask for this irq */
2096                         irq_set_affinity_hint(entry->vector,
2097                                               q_vector->affinity_mask);
2098                 }
2099         }
2100
2101         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2102         err = request_irq(adapter->msix_entries[vector].vector,
2103                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2104         if (err) {
2105                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2106                 goto free_queue_irqs;
2107         }
2108
2109         return 0;
2110
2111 free_queue_irqs:
2112         while (vector) {
2113                 vector--;
2114                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2115                                       NULL);
2116                 free_irq(adapter->msix_entries[vector].vector,
2117                          adapter->q_vector[vector]);
2118         }
2119         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2120         pci_disable_msix(adapter->pdev);
2121         kfree(adapter->msix_entries);
2122         adapter->msix_entries = NULL;
2123         return err;
2124 }
2125
2126 /**
2127  * ixgbe_irq_enable - Enable default interrupt generation settings
2128  * @adapter: board private structure
2129  **/
2130 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2131                                     bool flush)
2132 {
2133         u32 mask;
2134
2135         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2136         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2137                 mask |= IXGBE_EIMS_GPI_SDP0;
2138         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2139                 mask |= IXGBE_EIMS_GPI_SDP1;
2140         switch (adapter->hw.mac.type) {
2141         case ixgbe_mac_82599EB:
2142         case ixgbe_mac_X540:
2143                 mask |= IXGBE_EIMS_ECC;
2144                 mask |= IXGBE_EIMS_GPI_SDP1;
2145                 mask |= IXGBE_EIMS_GPI_SDP2;
2146                 if (adapter->num_vfs)
2147                         mask |= IXGBE_EIMS_MAILBOX;
2148                 break;
2149         default:
2150                 break;
2151         }
2152         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2153                 mask |= IXGBE_EIMS_FLOW_DIR;
2154
2155         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2156         if (queues)
2157                 ixgbe_irq_enable_queues(adapter, ~0);
2158         if (flush)
2159                 IXGBE_WRITE_FLUSH(&adapter->hw);
2160
2161         if (adapter->num_vfs > 32) {
2162                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2163                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2164         }
2165 }
2166
2167 /**
2168  * ixgbe_intr - legacy mode Interrupt Handler
2169  * @irq: interrupt number
2170  * @data: pointer to a network interface device structure
2171  **/
2172 static irqreturn_t ixgbe_intr(int irq, void *data)
2173 {
2174         struct ixgbe_adapter *adapter = data;
2175         struct ixgbe_hw *hw = &adapter->hw;
2176         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2177         u32 eicr;
2178
2179         /*
2180          * Workaround for silicon errata on 82598.  Mask the interrupts
2181          * before the read of EICR.
2182          */
2183         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2184
2185         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2186          * therefore no explict interrupt disable is necessary */
2187         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2188         if (!eicr) {
2189                 /*
2190                  * shared interrupt alert!
2191                  * make sure interrupts are enabled because the read will
2192                  * have disabled interrupts due to EIAM
2193                  * finish the workaround of silicon errata on 82598.  Unmask
2194                  * the interrupt that we masked before the EICR read.
2195                  */
2196                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2197                         ixgbe_irq_enable(adapter, true, true);
2198                 return IRQ_NONE;        /* Not our interrupt */
2199         }
2200
2201         if (eicr & IXGBE_EICR_LSC)
2202                 ixgbe_check_lsc(adapter);
2203
2204         switch (hw->mac.type) {
2205         case ixgbe_mac_82599EB:
2206                 ixgbe_check_sfp_event(adapter, eicr);
2207                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2208                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2209                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2210                                 adapter->interrupt_event = eicr;
2211                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2212                                 ixgbe_service_event_schedule(adapter);
2213                         }
2214                 }
2215                 break;
2216         default:
2217                 break;
2218         }
2219
2220         ixgbe_check_fan_failure(adapter, eicr);
2221
2222         if (napi_schedule_prep(&(q_vector->napi))) {
2223                 /* would disable interrupts here but EIAM disabled it */
2224                 __napi_schedule(&(q_vector->napi));
2225         }
2226
2227         /*
2228          * re-enable link(maybe) and non-queue interrupts, no flush.
2229          * ixgbe_poll will re-enable the queue interrupts
2230          */
2231
2232         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2233                 ixgbe_irq_enable(adapter, false, false);
2234
2235         return IRQ_HANDLED;
2236 }
2237
2238 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2239 {
2240         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2241         int i;
2242
2243         /* legacy and MSI only use one vector */
2244         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2245                 q_vectors = 1;
2246
2247         for (i = 0; i < adapter->num_rx_queues; i++) {
2248                 adapter->rx_ring[i]->q_vector = NULL;
2249                 adapter->rx_ring[i]->next = NULL;
2250         }
2251         for (i = 0; i < adapter->num_tx_queues; i++) {
2252                 adapter->tx_ring[i]->q_vector = NULL;
2253                 adapter->tx_ring[i]->next = NULL;
2254         }
2255
2256         for (i = 0; i < q_vectors; i++) {
2257                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2258                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2259                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2260         }
2261 }
2262
2263 /**
2264  * ixgbe_request_irq - initialize interrupts
2265  * @adapter: board private structure
2266  *
2267  * Attempts to configure interrupts using the best available
2268  * capabilities of the hardware and kernel.
2269  **/
2270 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2271 {
2272         struct net_device *netdev = adapter->netdev;
2273         int err;
2274
2275         /* map all of the rings to the q_vectors */
2276         ixgbe_map_rings_to_vectors(adapter);
2277
2278         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2279                 err = ixgbe_request_msix_irqs(adapter);
2280         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2281                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2282                                   netdev->name, adapter);
2283         else
2284                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2285                                   netdev->name, adapter);
2286
2287         if (err) {
2288                 e_err(probe, "request_irq failed, Error %d\n", err);
2289
2290                 /* place q_vectors and rings back into a known good state */
2291                 ixgbe_reset_q_vectors(adapter);
2292         }
2293
2294         return err;
2295 }
2296
2297 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2298 {
2299         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2300                 int i, q_vectors;
2301
2302                 q_vectors = adapter->num_msix_vectors;
2303                 i = q_vectors - 1;
2304                 free_irq(adapter->msix_entries[i].vector, adapter);
2305                 i--;
2306
2307                 for (; i >= 0; i--) {
2308                         /* free only the irqs that were actually requested */
2309                         if (!adapter->q_vector[i]->rx.ring &&
2310                             !adapter->q_vector[i]->tx.ring)
2311                                 continue;
2312
2313                         /* clear the affinity_mask in the IRQ descriptor */
2314                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2315                                               NULL);
2316
2317                         free_irq(adapter->msix_entries[i].vector,
2318                                  adapter->q_vector[i]);
2319                 }
2320         } else {
2321                 free_irq(adapter->pdev->irq, adapter);
2322         }
2323
2324         /* clear q_vector state information */
2325         ixgbe_reset_q_vectors(adapter);
2326 }
2327
2328 /**
2329  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2330  * @adapter: board private structure
2331  **/
2332 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2333 {
2334         switch (adapter->hw.mac.type) {
2335         case ixgbe_mac_82598EB:
2336                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2337                 break;
2338         case ixgbe_mac_82599EB:
2339         case ixgbe_mac_X540:
2340                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2341                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2342                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2343                 if (adapter->num_vfs > 32)
2344                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2345                 break;
2346         default:
2347                 break;
2348         }
2349         IXGBE_WRITE_FLUSH(&adapter->hw);
2350         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2351                 int i;
2352                 for (i = 0; i < adapter->num_msix_vectors; i++)
2353                         synchronize_irq(adapter->msix_entries[i].vector);
2354         } else {
2355                 synchronize_irq(adapter->pdev->irq);
2356         }
2357 }
2358
2359 /**
2360  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2361  *
2362  **/
2363 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2364 {
2365         struct ixgbe_hw *hw = &adapter->hw;
2366
2367         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2368                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2369
2370         ixgbe_set_ivar(adapter, 0, 0, 0);
2371         ixgbe_set_ivar(adapter, 1, 0, 0);
2372
2373         e_info(hw, "Legacy interrupt IVAR setup done\n");
2374 }
2375
2376 /**
2377  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2378  * @adapter: board private structure
2379  * @ring: structure containing ring specific data
2380  *
2381  * Configure the Tx descriptor ring after a reset.
2382  **/
2383 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2384                              struct ixgbe_ring *ring)
2385 {
2386         struct ixgbe_hw *hw = &adapter->hw;
2387         u64 tdba = ring->dma;
2388         int wait_loop = 10;
2389         u32 txdctl;
2390         u8 reg_idx = ring->reg_idx;
2391
2392         /* disable queue to avoid issues while updating state */
2393         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2394         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2395                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2396         IXGBE_WRITE_FLUSH(hw);
2397
2398         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2399                         (tdba & DMA_BIT_MASK(32)));
2400         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2401         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2402                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2403         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2404         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2405         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2406
2407         /* configure fetching thresholds */
2408         if (adapter->rx_itr_setting == 0) {
2409                 /* cannot set wthresh when itr==0 */
2410                 txdctl &= ~0x007F0000;
2411         } else {
2412                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2413                 txdctl |= (8 << 16);
2414         }
2415         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2416                 /* PThresh workaround for Tx hang with DFP enabled. */
2417                 txdctl |= 32;
2418         }
2419
2420         /* reinitialize flowdirector state */
2421         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2422             adapter->atr_sample_rate) {
2423                 ring->atr_sample_rate = adapter->atr_sample_rate;
2424                 ring->atr_count = 0;
2425                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2426         } else {
2427                 ring->atr_sample_rate = 0;
2428         }
2429
2430         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2431
2432         /* enable queue */
2433         txdctl |= IXGBE_TXDCTL_ENABLE;
2434         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2435
2436         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2437         if (hw->mac.type == ixgbe_mac_82598EB &&
2438             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2439                 return;
2440
2441         /* poll to verify queue is enabled */
2442         do {
2443                 usleep_range(1000, 2000);
2444                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2445         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2446         if (!wait_loop)
2447                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2448 }
2449
2450 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2451 {
2452         struct ixgbe_hw *hw = &adapter->hw;
2453         u32 rttdcs;
2454         u32 reg;
2455         u8 tcs = netdev_get_num_tc(adapter->netdev);
2456
2457         if (hw->mac.type == ixgbe_mac_82598EB)
2458                 return;
2459
2460         /* disable the arbiter while setting MTQC */
2461         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2462         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2463         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2464
2465         /* set transmit pool layout */
2466         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2467         case (IXGBE_FLAG_SRIOV_ENABLED):
2468                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2469                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2470                 break;
2471         default:
2472                 if (!tcs)
2473                         reg = IXGBE_MTQC_64Q_1PB;
2474                 else if (tcs <= 4)
2475                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2476                 else
2477                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2478
2479                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2480
2481                 /* Enable Security TX Buffer IFG for multiple pb */
2482                 if (tcs) {
2483                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2484                         reg |= IXGBE_SECTX_DCB;
2485                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2486                 }
2487                 break;
2488         }
2489
2490         /* re-enable the arbiter */
2491         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2492         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2493 }
2494
2495 /**
2496  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2497  * @adapter: board private structure
2498  *
2499  * Configure the Tx unit of the MAC after a reset.
2500  **/
2501 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2502 {
2503         struct ixgbe_hw *hw = &adapter->hw;
2504         u32 dmatxctl;
2505         u32 i;
2506
2507         ixgbe_setup_mtqc(adapter);
2508
2509         if (hw->mac.type != ixgbe_mac_82598EB) {
2510                 /* DMATXCTL.EN must be before Tx queues are enabled */
2511                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2512                 dmatxctl |= IXGBE_DMATXCTL_TE;
2513                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2514         }
2515
2516         /* Setup the HW Tx Head and Tail descriptor pointers */
2517         for (i = 0; i < adapter->num_tx_queues; i++)
2518                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2519 }
2520
2521 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2522
2523 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2524                                    struct ixgbe_ring *rx_ring)
2525 {
2526         u32 srrctl;
2527         u8 reg_idx = rx_ring->reg_idx;
2528
2529         switch (adapter->hw.mac.type) {
2530         case ixgbe_mac_82598EB: {
2531                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2532                 const int mask = feature[RING_F_RSS].mask;
2533                 reg_idx = reg_idx & mask;
2534         }
2535                 break;
2536         case ixgbe_mac_82599EB:
2537         case ixgbe_mac_X540:
2538         default:
2539                 break;
2540         }
2541
2542         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2543
2544         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2545         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2546         if (adapter->num_vfs)
2547                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2548
2549         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2550                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2551
2552         if (ring_is_ps_enabled(rx_ring)) {
2553 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2554                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2555 #else
2556                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2557 #endif
2558                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2559         } else {
2560                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2561                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2562                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2563         }
2564
2565         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2566 }
2567
2568 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2569 {
2570         struct ixgbe_hw *hw = &adapter->hw;
2571         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2572                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2573                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2574         u32 mrqc = 0, reta = 0;
2575         u32 rxcsum;
2576         int i, j;
2577         u8 tcs = netdev_get_num_tc(adapter->netdev);
2578         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2579
2580         if (tcs)
2581                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2582
2583         /* Fill out hash function seeds */
2584         for (i = 0; i < 10; i++)
2585                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2586
2587         /* Fill out redirection table */
2588         for (i = 0, j = 0; i < 128; i++, j++) {
2589                 if (j == maxq)
2590                         j = 0;
2591                 /* reta = 4-byte sliding window of
2592                  * 0x00..(indices-1)(indices-1)00..etc. */
2593                 reta = (reta << 8) | (j * 0x11);
2594                 if ((i & 3) == 3)
2595                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2596         }
2597
2598         /* Disable indicating checksum in descriptor, enables RSS hash */
2599         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2600         rxcsum |= IXGBE_RXCSUM_PCSD;
2601         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2602
2603         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2604             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2605                 mrqc = IXGBE_MRQC_RSSEN;
2606         } else {
2607                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2608                                              | IXGBE_FLAG_SRIOV_ENABLED);
2609
2610                 switch (mask) {
2611                 case (IXGBE_FLAG_RSS_ENABLED):
2612                         if (!tcs)
2613                                 mrqc = IXGBE_MRQC_RSSEN;
2614                         else if (tcs <= 4)
2615                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2616                         else
2617                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2618                         break;
2619                 case (IXGBE_FLAG_SRIOV_ENABLED):
2620                         mrqc = IXGBE_MRQC_VMDQEN;
2621                         break;
2622                 default:
2623                         break;
2624                 }
2625         }
2626
2627         /* Perform hash on these packet types */
2628         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2629               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2630               | IXGBE_MRQC_RSS_FIELD_IPV6
2631               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2632
2633         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2634 }
2635
2636 /**
2637  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2638  * @adapter:    address of board private structure
2639  * @index:      index of ring to set
2640  **/
2641 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2642                                    struct ixgbe_ring *ring)
2643 {
2644         struct ixgbe_hw *hw = &adapter->hw;
2645         u32 rscctrl;
2646         int rx_buf_len;
2647         u8 reg_idx = ring->reg_idx;
2648
2649         if (!ring_is_rsc_enabled(ring))
2650                 return;
2651
2652         rx_buf_len = ring->rx_buf_len;
2653         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2654         rscctrl |= IXGBE_RSCCTL_RSCEN;
2655         /*
2656          * we must limit the number of descriptors so that the
2657          * total size of max desc * buf_len is not greater
2658          * than 65535
2659          */
2660         if (ring_is_ps_enabled(ring)) {
2661 #if (MAX_SKB_FRAGS > 16)
2662                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2663 #elif (MAX_SKB_FRAGS > 8)
2664                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2665 #elif (MAX_SKB_FRAGS > 4)
2666                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2667 #else
2668                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2669 #endif
2670         } else {
2671                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2672                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2673                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2674                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2675                 else
2676                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2677         }
2678         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2679 }
2680
2681 /**
2682  *  ixgbe_set_uta - Set unicast filter table address
2683  *  @adapter: board private structure
2684  *
2685  *  The unicast table address is a register array of 32-bit registers.
2686  *  The table is meant to be used in a way similar to how the MTA is used
2687  *  however due to certain limitations in the hardware it is necessary to
2688  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2689  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2690  **/
2691 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2692 {
2693         struct ixgbe_hw *hw = &adapter->hw;
2694         int i;
2695
2696         /* The UTA table only exists on 82599 hardware and newer */
2697         if (hw->mac.type < ixgbe_mac_82599EB)
2698                 return;
2699
2700         /* we only need to do this if VMDq is enabled */
2701         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2702                 return;
2703
2704         for (i = 0; i < 128; i++)
2705                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2706 }
2707
2708 #define IXGBE_MAX_RX_DESC_POLL 10
2709 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2710                                        struct ixgbe_ring *ring)
2711 {
2712         struct ixgbe_hw *hw = &adapter->hw;
2713         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714         u32 rxdctl;
2715         u8 reg_idx = ring->reg_idx;
2716
2717         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2718         if (hw->mac.type == ixgbe_mac_82598EB &&
2719             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2720                 return;
2721
2722         do {
2723                 usleep_range(1000, 2000);
2724                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2725         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2726
2727         if (!wait_loop) {
2728                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2729                       "the polling period\n", reg_idx);
2730         }
2731 }
2732
2733 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2734                             struct ixgbe_ring *ring)
2735 {
2736         struct ixgbe_hw *hw = &adapter->hw;
2737         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2738         u32 rxdctl;
2739         u8 reg_idx = ring->reg_idx;
2740
2741         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2742         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2743
2744         /* write value back with RXDCTL.ENABLE bit cleared */
2745         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2746
2747         if (hw->mac.type == ixgbe_mac_82598EB &&
2748             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2749                 return;
2750
2751         /* the hardware may take up to 100us to really disable the rx queue */
2752         do {
2753                 udelay(10);
2754                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2755         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2756
2757         if (!wait_loop) {
2758                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2759                       "the polling period\n", reg_idx);
2760         }
2761 }
2762
2763 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2764                              struct ixgbe_ring *ring)
2765 {
2766         struct ixgbe_hw *hw = &adapter->hw;
2767         u64 rdba = ring->dma;
2768         u32 rxdctl;
2769         u8 reg_idx = ring->reg_idx;
2770
2771         /* disable queue to avoid issues while updating state */
2772         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2773         ixgbe_disable_rx_queue(adapter, ring);
2774
2775         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2776         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2777         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2778                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2779         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2780         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2781         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2782
2783         ixgbe_configure_srrctl(adapter, ring);
2784         ixgbe_configure_rscctl(adapter, ring);
2785
2786         /* If operating in IOV mode set RLPML for X540 */
2787         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2788             hw->mac.type == ixgbe_mac_X540) {
2789                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2790                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2791                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2792         }
2793
2794         if (hw->mac.type == ixgbe_mac_82598EB) {
2795                 /*
2796                  * enable cache line friendly hardware writes:
2797                  * PTHRESH=32 descriptors (half the internal cache),
2798                  * this also removes ugly rx_no_buffer_count increment
2799                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2800                  * WTHRESH=8 burst writeback up to two cache lines
2801                  */
2802                 rxdctl &= ~0x3FFFFF;
2803                 rxdctl |=  0x080420;
2804         }
2805
2806         /* enable receive descriptor ring */
2807         rxdctl |= IXGBE_RXDCTL_ENABLE;
2808         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2809
2810         ixgbe_rx_desc_queue_enable(adapter, ring);
2811         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2812 }
2813
2814 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2815 {
2816         struct ixgbe_hw *hw = &adapter->hw;
2817         int p;
2818
2819         /* PSRTYPE must be initialized in non 82598 adapters */
2820         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2821                       IXGBE_PSRTYPE_UDPHDR |
2822                       IXGBE_PSRTYPE_IPV4HDR |
2823                       IXGBE_PSRTYPE_L2HDR |
2824                       IXGBE_PSRTYPE_IPV6HDR;
2825
2826         if (hw->mac.type == ixgbe_mac_82598EB)
2827                 return;
2828
2829         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2830                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2831
2832         for (p = 0; p < adapter->num_rx_pools; p++)
2833                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2834                                 psrtype);
2835 }
2836
2837 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2838 {
2839         struct ixgbe_hw *hw = &adapter->hw;
2840         u32 gcr_ext;
2841         u32 vt_reg_bits;
2842         u32 reg_offset, vf_shift;
2843         u32 vmdctl;
2844
2845         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2846                 return;
2847
2848         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2849         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2850         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2851         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2852
2853         vf_shift = adapter->num_vfs % 32;
2854         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2855
2856         /* Enable only the PF's pool for Tx/Rx */
2857         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2858         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2859         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2860         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2861         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2862
2863         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2864         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2865
2866         /*
2867          * Set up VF register offsets for selected VT Mode,
2868          * i.e. 32 or 64 VFs for SR-IOV
2869          */
2870         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2871         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2872         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2873         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2874
2875         /* enable Tx loopback for VF/PF communication */
2876         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2877         /* Enable MAC Anti-Spoofing */
2878         hw->mac.ops.set_mac_anti_spoofing(hw,
2879                                           (adapter->antispoofing_enabled =
2880                                            (adapter->num_vfs != 0)),
2881                                           adapter->num_vfs);
2882 }
2883
2884 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2885 {
2886         struct ixgbe_hw *hw = &adapter->hw;
2887         struct net_device *netdev = adapter->netdev;
2888         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2889         int rx_buf_len;
2890         struct ixgbe_ring *rx_ring;
2891         int i;
2892         u32 mhadd, hlreg0;
2893
2894         /* Decide whether to use packet split mode or not */
2895         /* On by default */
2896         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2897
2898         /* Do not use packet split if we're in SR-IOV Mode */
2899         if (adapter->num_vfs)
2900                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2901
2902         /* Disable packet split due to 82599 erratum #45 */
2903         if (hw->mac.type == ixgbe_mac_82599EB)
2904                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2905
2906         /* Set the RX buffer length according to the mode */
2907         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2908                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2909         } else {
2910                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2911                     (netdev->mtu <= ETH_DATA_LEN))
2912                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2913                 else
2914                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2915         }
2916
2917 #ifdef IXGBE_FCOE
2918         /* adjust max frame to be able to do baby jumbo for FCoE */
2919         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2920             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2921                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2922
2923 #endif /* IXGBE_FCOE */
2924         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2925         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2926                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2927                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2928
2929                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2930         }
2931
2932         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2933         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2934         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2935         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2936
2937         /*
2938          * Setup the HW Rx Head and Tail Descriptor Pointers and
2939          * the Base and Length of the Rx Descriptor Ring
2940          */
2941         for (i = 0; i < adapter->num_rx_queues; i++) {
2942                 rx_ring = adapter->rx_ring[i];
2943                 rx_ring->rx_buf_len = rx_buf_len;
2944
2945                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2946                         set_ring_ps_enabled(rx_ring);
2947                 else
2948                         clear_ring_ps_enabled(rx_ring);
2949
2950                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2951                         set_ring_rsc_enabled(rx_ring);
2952                 else
2953                         clear_ring_rsc_enabled(rx_ring);
2954
2955 #ifdef IXGBE_FCOE
2956                 if (netdev->features & NETIF_F_FCOE_MTU) {
2957                         struct ixgbe_ring_feature *f;
2958                         f = &adapter->ring_feature[RING_F_FCOE];
2959                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2960                                 clear_ring_ps_enabled(rx_ring);
2961                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2962                                         rx_ring->rx_buf_len =
2963                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2964                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2965                                    !ring_is_ps_enabled(rx_ring)) {
2966                                 rx_ring->rx_buf_len =
2967                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2968                         }
2969                 }
2970 #endif /* IXGBE_FCOE */
2971         }
2972 }
2973
2974 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2975 {
2976         struct ixgbe_hw *hw = &adapter->hw;
2977         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2978
2979         switch (hw->mac.type) {
2980         case ixgbe_mac_82598EB:
2981                 /*
2982                  * For VMDq support of different descriptor types or
2983                  * buffer sizes through the use of multiple SRRCTL
2984                  * registers, RDRXCTL.MVMEN must be set to 1
2985                  *
2986                  * also, the manual doesn't mention it clearly but DCA hints
2987                  * will only use queue 0's tags unless this bit is set.  Side
2988                  * effects of setting this bit are only that SRRCTL must be
2989                  * fully programmed [0..15]
2990                  */
2991                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2992                 break;
2993         case ixgbe_mac_82599EB:
2994         case ixgbe_mac_X540:
2995                 /* Disable RSC for ACK packets */
2996                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2997                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2998                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2999                 /* hardware requires some bits to be set by default */
3000                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3001                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3002                 break;
3003         default:
3004                 /* We should do nothing since we don't know this hardware */
3005                 return;
3006         }
3007
3008         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3009 }
3010
3011 /**
3012  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3013  * @adapter: board private structure
3014  *
3015  * Configure the Rx unit of the MAC after a reset.
3016  **/
3017 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3018 {
3019         struct ixgbe_hw *hw = &adapter->hw;
3020         int i;
3021         u32 rxctrl;
3022
3023         /* disable receives while setting up the descriptors */
3024         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3025         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3026
3027         ixgbe_setup_psrtype(adapter);
3028         ixgbe_setup_rdrxctl(adapter);
3029
3030         /* Program registers for the distribution of queues */
3031         ixgbe_setup_mrqc(adapter);
3032
3033         ixgbe_set_uta(adapter);
3034
3035         /* set_rx_buffer_len must be called before ring initialization */
3036         ixgbe_set_rx_buffer_len(adapter);
3037
3038         /*
3039          * Setup the HW Rx Head and Tail Descriptor Pointers and
3040          * the Base and Length of the Rx Descriptor Ring
3041          */
3042         for (i = 0; i < adapter->num_rx_queues; i++)
3043                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3044
3045         /* disable drop enable for 82598 parts */
3046         if (hw->mac.type == ixgbe_mac_82598EB)
3047                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3048
3049         /* enable all receives */
3050         rxctrl |= IXGBE_RXCTRL_RXEN;
3051         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3052 }
3053
3054 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3055 {
3056         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3057         struct ixgbe_hw *hw = &adapter->hw;
3058         int pool_ndx = adapter->num_vfs;
3059
3060         /* add VID to filter table */
3061         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3062         set_bit(vid, adapter->active_vlans);
3063 }
3064
3065 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3066 {
3067         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3068         struct ixgbe_hw *hw = &adapter->hw;
3069         int pool_ndx = adapter->num_vfs;
3070
3071         /* remove VID from filter table */
3072         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3073         clear_bit(vid, adapter->active_vlans);
3074 }
3075
3076 /**
3077  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3078  * @adapter: driver data
3079  */
3080 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3081 {
3082         struct ixgbe_hw *hw = &adapter->hw;
3083         u32 vlnctrl;
3084
3085         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3086         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3087         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3088 }
3089
3090 /**
3091  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3092  * @adapter: driver data
3093  */
3094 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3095 {
3096         struct ixgbe_hw *hw = &adapter->hw;
3097         u32 vlnctrl;
3098
3099         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3100         vlnctrl |= IXGBE_VLNCTRL_VFE;
3101         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3102         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3103 }
3104
3105 /**
3106  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3107  * @adapter: driver data
3108  */
3109 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3110 {
3111         struct ixgbe_hw *hw = &adapter->hw;
3112         u32 vlnctrl;
3113         int i, j;
3114
3115         switch (hw->mac.type) {
3116         case ixgbe_mac_82598EB:
3117                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3118                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3119                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3120                 break;
3121         case ixgbe_mac_82599EB:
3122         case ixgbe_mac_X540:
3123                 for (i = 0; i < adapter->num_rx_queues; i++) {
3124                         j = adapter->rx_ring[i]->reg_idx;
3125                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3126                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3127                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3128                 }
3129                 break;
3130         default:
3131                 break;
3132         }
3133 }
3134
3135 /**
3136  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3137  * @adapter: driver data
3138  */
3139 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3140 {
3141         struct ixgbe_hw *hw = &adapter->hw;
3142         u32 vlnctrl;
3143         int i, j;
3144
3145         switch (hw->mac.type) {
3146         case ixgbe_mac_82598EB:
3147                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3148                 vlnctrl |= IXGBE_VLNCTRL_VME;
3149                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3150                 break;
3151         case ixgbe_mac_82599EB:
3152         case ixgbe_mac_X540:
3153                 for (i = 0; i < adapter->num_rx_queues; i++) {
3154                         j = adapter->rx_ring[i]->reg_idx;
3155                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3156                         vlnctrl |= IXGBE_RXDCTL_VME;
3157                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3158                 }
3159                 break;
3160         default:
3161                 break;
3162         }
3163 }
3164
3165 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3166 {
3167         u16 vid;
3168
3169         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3170
3171         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3172                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3173 }
3174
3175 /**
3176  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3177  * @netdev: network interface device structure
3178  *
3179  * Writes unicast address list to the RAR table.
3180  * Returns: -ENOMEM on failure/insufficient address space
3181  *                0 on no addresses written
3182  *                X on writing X addresses to the RAR table
3183  **/
3184 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3185 {
3186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3187         struct ixgbe_hw *hw = &adapter->hw;
3188         unsigned int vfn = adapter->num_vfs;
3189         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3190         int count = 0;
3191
3192         /* return ENOMEM indicating insufficient memory for addresses */
3193         if (netdev_uc_count(netdev) > rar_entries)
3194                 return -ENOMEM;
3195
3196         if (!netdev_uc_empty(netdev) && rar_entries) {
3197                 struct netdev_hw_addr *ha;
3198                 /* return error if we do not support writing to RAR table */
3199                 if (!hw->mac.ops.set_rar)
3200                         return -ENOMEM;
3201
3202                 netdev_for_each_uc_addr(ha, netdev) {
3203                         if (!rar_entries)
3204                                 break;
3205                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3206                                             vfn, IXGBE_RAH_AV);
3207                         count++;
3208                 }
3209         }
3210         /* write the addresses in reverse order to avoid write combining */
3211         for (; rar_entries > 0 ; rar_entries--)
3212                 hw->mac.ops.clear_rar(hw, rar_entries);
3213
3214         return count;
3215 }
3216
3217 /**
3218  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3219  * @netdev: network interface device structure
3220  *
3221  * The set_rx_method entry point is called whenever the unicast/multicast
3222  * address list or the network interface flags are updated.  This routine is
3223  * responsible for configuring the hardware for proper unicast, multicast and
3224  * promiscuous mode.
3225  **/
3226 void ixgbe_set_rx_mode(struct net_device *netdev)
3227 {
3228         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3229         struct ixgbe_hw *hw = &adapter->hw;
3230         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3231         int count;
3232
3233         /* Check for Promiscuous and All Multicast modes */
3234
3235         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3236
3237         /* set all bits that we expect to always be set */
3238         fctrl |= IXGBE_FCTRL_BAM;
3239         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3240         fctrl |= IXGBE_FCTRL_PMCF;
3241
3242         /* clear the bits we are changing the status of */
3243         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3244
3245         if (netdev->flags & IFF_PROMISC) {
3246                 hw->addr_ctrl.user_set_promisc = true;
3247                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3248                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3249                 /* don't hardware filter vlans in promisc mode */
3250                 ixgbe_vlan_filter_disable(adapter);
3251         } else {
3252                 if (netdev->flags & IFF_ALLMULTI) {
3253                         fctrl |= IXGBE_FCTRL_MPE;
3254                         vmolr |= IXGBE_VMOLR_MPE;
3255                 } else {
3256                         /*
3257                          * Write addresses to the MTA, if the attempt fails
3258                          * then we should just turn on promiscuous mode so
3259                          * that we can at least receive multicast traffic
3260                          */
3261                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3262                         vmolr |= IXGBE_VMOLR_ROMPE;
3263                 }
3264                 ixgbe_vlan_filter_enable(adapter);
3265                 hw->addr_ctrl.user_set_promisc = false;
3266                 /*
3267                  * Write addresses to available RAR registers, if there is not
3268                  * sufficient space to store all the addresses then enable
3269                  * unicast promiscuous mode
3270                  */
3271                 count = ixgbe_write_uc_addr_list(netdev);
3272                 if (count < 0) {
3273                         fctrl |= IXGBE_FCTRL_UPE;
3274                         vmolr |= IXGBE_VMOLR_ROPE;
3275                 }
3276         }
3277
3278         if (adapter->num_vfs) {
3279                 ixgbe_restore_vf_multicasts(adapter);
3280                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3281                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3282                            IXGBE_VMOLR_ROPE);
3283                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3284         }
3285
3286         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3287
3288         if (netdev->features & NETIF_F_HW_VLAN_RX)
3289                 ixgbe_vlan_strip_enable(adapter);
3290         else
3291                 ixgbe_vlan_strip_disable(adapter);
3292 }
3293
3294 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3295 {
3296         int q_idx;
3297         struct ixgbe_q_vector *q_vector;
3298         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3299
3300         /* legacy and MSI only use one vector */
3301         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3302                 q_vectors = 1;
3303
3304         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3305                 q_vector = adapter->q_vector[q_idx];
3306                 napi_enable(&q_vector->napi);
3307         }
3308 }
3309
3310 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3311 {
3312         int q_idx;
3313         struct ixgbe_q_vector *q_vector;
3314         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3315
3316         /* legacy and MSI only use one vector */
3317         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3318                 q_vectors = 1;
3319
3320         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3321                 q_vector = adapter->q_vector[q_idx];
3322                 napi_disable(&q_vector->napi);
3323         }
3324 }
3325
3326 #ifdef CONFIG_IXGBE_DCB
3327 /*
3328  * ixgbe_configure_dcb - Configure DCB hardware
3329  * @adapter: ixgbe adapter struct
3330  *
3331  * This is called by the driver on open to configure the DCB hardware.
3332  * This is also called by the gennetlink interface when reconfiguring
3333  * the DCB state.
3334  */
3335 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3336 {
3337         struct ixgbe_hw *hw = &adapter->hw;
3338         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3339
3340         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3341                 if (hw->mac.type == ixgbe_mac_82598EB)
3342                         netif_set_gso_max_size(adapter->netdev, 65536);
3343                 return;
3344         }
3345
3346         if (hw->mac.type == ixgbe_mac_82598EB)
3347                 netif_set_gso_max_size(adapter->netdev, 32768);
3348
3349
3350         /* Enable VLAN tag insert/strip */
3351         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3352
3353         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3354
3355         /* reconfigure the hardware */
3356         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3357 #ifdef IXGBE_FCOE
3358                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3359                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3360 #endif
3361                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3362                                                 DCB_TX_CONFIG);
3363                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3364                                                 DCB_RX_CONFIG);
3365                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3366         } else {
3367                 struct net_device *dev = adapter->netdev;
3368
3369                 if (adapter->ixgbe_ieee_ets)
3370                         dev->dcbnl_ops->ieee_setets(dev,
3371                                                     adapter->ixgbe_ieee_ets);
3372                 if (adapter->ixgbe_ieee_pfc)
3373                         dev->dcbnl_ops->ieee_setpfc(dev,
3374                                                     adapter->ixgbe_ieee_pfc);
3375         }
3376
3377         /* Enable RSS Hash per TC */
3378         if (hw->mac.type != ixgbe_mac_82598EB) {
3379                 int i;
3380                 u32 reg = 0;
3381
3382                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3383                         u8 msb = 0;
3384                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3385
3386                         while (cnt >>= 1)
3387                                 msb++;
3388
3389                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3390                 }
3391                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3392         }
3393 }
3394
3395 #endif
3396
3397 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3398 {
3399         int hdrm = 0;
3400         int num_tc = netdev_get_num_tc(adapter->netdev);
3401         struct ixgbe_hw *hw = &adapter->hw;
3402
3403         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3404             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3405                 hdrm = 64 << adapter->fdir_pballoc;
3406
3407         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3408 }
3409
3410 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3411 {
3412         struct ixgbe_hw *hw = &adapter->hw;
3413         struct hlist_node *node, *node2;
3414         struct ixgbe_fdir_filter *filter;
3415
3416         spin_lock(&adapter->fdir_perfect_lock);
3417
3418         if (!hlist_empty(&adapter->fdir_filter_list))
3419                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3420
3421         hlist_for_each_entry_safe(filter, node, node2,
3422                                   &adapter->fdir_filter_list, fdir_node) {
3423                 ixgbe_fdir_write_perfect_filter_82599(hw,
3424                                 &filter->filter,
3425                                 filter->sw_idx,
3426                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3427                                 IXGBE_FDIR_DROP_QUEUE :
3428                                 adapter->rx_ring[filter->action]->reg_idx);
3429         }
3430
3431         spin_unlock(&adapter->fdir_perfect_lock);
3432 }
3433
3434 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3435 {
3436         struct net_device *netdev = adapter->netdev;
3437         struct ixgbe_hw *hw = &adapter->hw;
3438         int i;
3439
3440         ixgbe_configure_pb(adapter);
3441 #ifdef CONFIG_IXGBE_DCB
3442         ixgbe_configure_dcb(adapter);
3443 #endif
3444
3445         ixgbe_set_rx_mode(netdev);
3446         ixgbe_restore_vlan(adapter);
3447
3448 #ifdef IXGBE_FCOE
3449         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3450                 ixgbe_configure_fcoe(adapter);
3451
3452 #endif /* IXGBE_FCOE */
3453         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3454                 for (i = 0; i < adapter->num_tx_queues; i++)
3455                         adapter->tx_ring[i]->atr_sample_rate =
3456                                                        adapter->atr_sample_rate;
3457                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3458         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3459                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3460                                               adapter->fdir_pballoc);
3461                 ixgbe_fdir_filter_restore(adapter);
3462         }
3463         ixgbe_configure_virtualization(adapter);
3464
3465         ixgbe_configure_tx(adapter);
3466         ixgbe_configure_rx(adapter);
3467 }
3468
3469 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3470 {
3471         switch (hw->phy.type) {
3472         case ixgbe_phy_sfp_avago:
3473         case ixgbe_phy_sfp_ftl:
3474         case ixgbe_phy_sfp_intel:
3475         case ixgbe_phy_sfp_unknown:
3476         case ixgbe_phy_sfp_passive_tyco:
3477         case ixgbe_phy_sfp_passive_unknown:
3478         case ixgbe_phy_sfp_active_unknown:
3479         case ixgbe_phy_sfp_ftl_active:
3480                 return true;
3481         default:
3482                 return false;
3483         }
3484 }
3485
3486 /**
3487  * ixgbe_sfp_link_config - set up SFP+ link
3488  * @adapter: pointer to private adapter struct
3489  **/
3490 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3491 {
3492         /*
3493          * We are assuming the worst case scenerio here, and that
3494          * is that an SFP was inserted/removed after the reset
3495          * but before SFP detection was enabled.  As such the best
3496          * solution is to just start searching as soon as we start
3497          */
3498         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3499                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3500
3501         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3502 }
3503
3504 /**
3505  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3506  * @hw: pointer to private hardware struct
3507  *
3508  * Returns 0 on success, negative on failure
3509  **/
3510 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3511 {
3512         u32 autoneg;
3513         bool negotiation, link_up = false;
3514         u32 ret = IXGBE_ERR_LINK_SETUP;
3515
3516         if (hw->mac.ops.check_link)
3517                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3518
3519         if (ret)
3520                 goto link_cfg_out;
3521
3522         autoneg = hw->phy.autoneg_advertised;
3523         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3524                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3525                                                         &negotiation);
3526         if (ret)
3527                 goto link_cfg_out;
3528
3529         if (hw->mac.ops.setup_link)
3530                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3531 link_cfg_out:
3532         return ret;
3533 }
3534
3535 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3536 {
3537         struct ixgbe_hw *hw = &adapter->hw;
3538         u32 gpie = 0;
3539
3540         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3541                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3542                        IXGBE_GPIE_OCD;
3543                 gpie |= IXGBE_GPIE_EIAME;
3544                 /*
3545                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3546                  * this saves a register write for every interrupt
3547                  */
3548                 switch (hw->mac.type) {
3549                 case ixgbe_mac_82598EB:
3550                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3551                         break;
3552                 case ixgbe_mac_82599EB:
3553                 case ixgbe_mac_X540:
3554                 default:
3555                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3556                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3557                         break;
3558                 }
3559         } else {
3560                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3561                  * specifically only auto mask tx and rx interrupts */
3562                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3563         }
3564
3565         /* XXX: to interrupt immediately for EICS writes, enable this */
3566         /* gpie |= IXGBE_GPIE_EIMEN; */
3567
3568         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3569                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3570                 gpie |= IXGBE_GPIE_VTMODE_64;
3571         }
3572
3573         /* Enable fan failure interrupt */
3574         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3575                 gpie |= IXGBE_SDP1_GPIEN;
3576
3577         if (hw->mac.type == ixgbe_mac_82599EB) {
3578                 gpie |= IXGBE_SDP1_GPIEN;
3579                 gpie |= IXGBE_SDP2_GPIEN;
3580         }
3581
3582         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3583 }
3584
3585 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3586 {
3587         struct ixgbe_hw *hw = &adapter->hw;
3588         int err;
3589         u32 ctrl_ext;
3590
3591         ixgbe_get_hw_control(adapter);
3592         ixgbe_setup_gpie(adapter);
3593
3594         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3595                 ixgbe_configure_msix(adapter);
3596         else
3597                 ixgbe_configure_msi_and_legacy(adapter);
3598
3599         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3600         if (hw->mac.ops.enable_tx_laser &&
3601             ((hw->phy.multispeed_fiber) ||
3602              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3603               (hw->mac.type == ixgbe_mac_82599EB))))
3604                 hw->mac.ops.enable_tx_laser(hw);
3605
3606         clear_bit(__IXGBE_DOWN, &adapter->state);
3607         ixgbe_napi_enable_all(adapter);
3608
3609         if (ixgbe_is_sfp(hw)) {
3610                 ixgbe_sfp_link_config(adapter);
3611         } else {
3612                 err = ixgbe_non_sfp_link_config(hw);
3613                 if (err)
3614                         e_err(probe, "link_config FAILED %d\n", err);
3615         }
3616
3617         /* clear any pending interrupts, may auto mask */
3618         IXGBE_READ_REG(hw, IXGBE_EICR);
3619         ixgbe_irq_enable(adapter, true, true);
3620
3621         /*
3622          * If this adapter has a fan, check to see if we had a failure
3623          * before we enabled the interrupt.
3624          */
3625         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3626                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3627                 if (esdp & IXGBE_ESDP_SDP1)
3628                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3629         }
3630
3631         /* enable transmits */
3632         netif_tx_start_all_queues(adapter->netdev);
3633
3634         /* bring the link up in the watchdog, this could race with our first
3635          * link up interrupt but shouldn't be a problem */
3636         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3637         adapter->link_check_timeout = jiffies;
3638         mod_timer(&adapter->service_timer, jiffies);
3639
3640         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3641         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3642         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3643         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3644
3645         return 0;
3646 }
3647
3648 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3649 {
3650         WARN_ON(in_interrupt());
3651         /* put off any impending NetWatchDogTimeout */
3652         adapter->netdev->trans_start = jiffies;
3653
3654         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3655                 usleep_range(1000, 2000);
3656         ixgbe_down(adapter);
3657         /*
3658          * If SR-IOV enabled then wait a bit before bringing the adapter
3659          * back up to give the VFs time to respond to the reset.  The
3660          * two second wait is based upon the watchdog timer cycle in
3661          * the VF driver.
3662          */
3663         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3664                 msleep(2000);
3665         ixgbe_up(adapter);
3666         clear_bit(__IXGBE_RESETTING, &adapter->state);
3667 }
3668
3669 int ixgbe_up(struct ixgbe_adapter *adapter)
3670 {
3671         /* hardware has been reset, we need to reload some things */
3672         ixgbe_configure(adapter);
3673
3674         return ixgbe_up_complete(adapter);
3675 }
3676
3677 void ixgbe_reset(struct ixgbe_adapter *adapter)
3678 {
3679         struct ixgbe_hw *hw = &adapter->hw;
3680         int err;
3681
3682         /* lock SFP init bit to prevent race conditions with the watchdog */
3683         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3684                 usleep_range(1000, 2000);
3685
3686         /* clear all SFP and link config related flags while holding SFP_INIT */
3687         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3688                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3689         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3690
3691         err = hw->mac.ops.init_hw(hw);
3692         switch (err) {
3693         case 0:
3694         case IXGBE_ERR_SFP_NOT_PRESENT:
3695         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3696                 break;
3697         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3698                 e_dev_err("master disable timed out\n");
3699                 break;
3700         case IXGBE_ERR_EEPROM_VERSION:
3701                 /* We are running on a pre-production device, log a warning */
3702                 e_dev_warn("This device is a pre-production adapter/LOM. "
3703                            "Please be aware there may be issuesassociated with "
3704                            "your hardware.  If you are experiencing problems "
3705                            "please contact your Intel or hardware "
3706                            "representative who provided you with this "
3707                            "hardware.\n");
3708                 break;
3709         default:
3710                 e_dev_err("Hardware Error: %d\n", err);
3711         }
3712
3713         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3714
3715         /* reprogram the RAR[0] in case user changed it. */
3716         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3717                             IXGBE_RAH_AV);
3718 }
3719
3720 /**
3721  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3722  * @rx_ring: ring to free buffers from
3723  **/
3724 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3725 {
3726         struct device *dev = rx_ring->dev;
3727         unsigned long size;
3728         u16 i;
3729
3730         /* ring already cleared, nothing to do */
3731         if (!rx_ring->rx_buffer_info)
3732                 return;
3733
3734         /* Free all the Rx ring sk_buffs */
3735         for (i = 0; i < rx_ring->count; i++) {
3736                 struct ixgbe_rx_buffer *rx_buffer_info;
3737
3738                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3739                 if (rx_buffer_info->dma) {
3740                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3741                                          rx_ring->rx_buf_len,
3742                                          DMA_FROM_DEVICE);
3743                         rx_buffer_info->dma = 0;
3744                 }
3745                 if (rx_buffer_info->skb) {
3746                         struct sk_buff *skb = rx_buffer_info->skb;
3747                         rx_buffer_info->skb = NULL;
3748                         do {
3749                                 struct sk_buff *this = skb;
3750                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3751                                         dma_unmap_single(dev,
3752                                                          IXGBE_RSC_CB(this)->dma,
3753                                                          rx_ring->rx_buf_len,
3754                                                          DMA_FROM_DEVICE);
3755                                         IXGBE_RSC_CB(this)->dma = 0;
3756                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3757                                 }
3758                                 skb = skb->prev;
3759                                 dev_kfree_skb(this);
3760                         } while (skb);
3761                 }
3762                 if (!rx_buffer_info->page)
3763                         continue;
3764                 if (rx_buffer_info->page_dma) {
3765                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3766                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3767                         rx_buffer_info->page_dma = 0;
3768                 }
3769                 put_page(rx_buffer_info->page);
3770                 rx_buffer_info->page = NULL;
3771                 rx_buffer_info->page_offset = 0;
3772         }
3773
3774         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3775         memset(rx_ring->rx_buffer_info, 0, size);
3776
3777         /* Zero out the descriptor ring */
3778         memset(rx_ring->desc, 0, rx_ring->size);
3779
3780         rx_ring->next_to_clean = 0;
3781         rx_ring->next_to_use = 0;
3782 }
3783
3784 /**
3785  * ixgbe_clean_tx_ring - Free Tx Buffers
3786  * @tx_ring: ring to be cleaned
3787  **/
3788 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3789 {
3790         struct ixgbe_tx_buffer *tx_buffer_info;
3791         unsigned long size;
3792         u16 i;
3793
3794         /* ring already cleared, nothing to do */
3795         if (!tx_ring->tx_buffer_info)
3796                 return;
3797
3798         /* Free all the Tx ring sk_buffs */
3799         for (i = 0; i < tx_ring->count; i++) {
3800                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3801                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3802         }
3803
3804         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3805         memset(tx_ring->tx_buffer_info, 0, size);
3806
3807         /* Zero out the descriptor ring */
3808         memset(tx_ring->desc, 0, tx_ring->size);
3809
3810         tx_ring->next_to_use = 0;
3811         tx_ring->next_to_clean = 0;
3812 }
3813
3814 /**
3815  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3816  * @adapter: board private structure
3817  **/
3818 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3819 {
3820         int i;
3821
3822         for (i = 0; i < adapter->num_rx_queues; i++)
3823                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3824 }
3825
3826 /**
3827  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3828  * @adapter: board private structure
3829  **/
3830 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3831 {
3832         int i;
3833
3834         for (i = 0; i < adapter->num_tx_queues; i++)
3835                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3836 }
3837
3838 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3839 {
3840         struct hlist_node *node, *node2;
3841         struct ixgbe_fdir_filter *filter;
3842
3843         spin_lock(&adapter->fdir_perfect_lock);
3844
3845         hlist_for_each_entry_safe(filter, node, node2,
3846                                   &adapter->fdir_filter_list, fdir_node) {
3847                 hlist_del(&filter->fdir_node);
3848                 kfree(filter);
3849         }
3850         adapter->fdir_filter_count = 0;
3851
3852         spin_unlock(&adapter->fdir_perfect_lock);
3853 }
3854
3855 void ixgbe_down(struct ixgbe_adapter *adapter)
3856 {
3857         struct net_device *netdev = adapter->netdev;
3858         struct ixgbe_hw *hw = &adapter->hw;
3859         u32 rxctrl;
3860         int i;
3861
3862         /* signal that we are down to the interrupt handler */
3863         set_bit(__IXGBE_DOWN, &adapter->state);
3864
3865         /* disable receives */
3866         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3867         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3868
3869         /* disable all enabled rx queues */
3870         for (i = 0; i < adapter->num_rx_queues; i++)
3871                 /* this call also flushes the previous write */
3872                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3873
3874         usleep_range(10000, 20000);
3875
3876         netif_tx_stop_all_queues(netdev);
3877
3878         /* call carrier off first to avoid false dev_watchdog timeouts */
3879         netif_carrier_off(netdev);
3880         netif_tx_disable(netdev);
3881
3882         ixgbe_irq_disable(adapter);
3883
3884         ixgbe_napi_disable_all(adapter);
3885
3886         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3887                              IXGBE_FLAG2_RESET_REQUESTED);
3888         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3889
3890         del_timer_sync(&adapter->service_timer);
3891
3892         /* disable receive for all VFs and wait one second */
3893         if (adapter->num_vfs) {
3894                 /* ping all the active vfs to let them know we are going down */
3895                 ixgbe_ping_all_vfs(adapter);
3896
3897                 /* Disable all VFTE/VFRE TX/RX */
3898                 ixgbe_disable_tx_rx(adapter);
3899
3900                 /* Mark all the VFs as inactive */
3901                 for (i = 0 ; i < adapter->num_vfs; i++)
3902                         adapter->vfinfo[i].clear_to_send = 0;
3903         }
3904
3905         /* disable transmits in the hardware now that interrupts are off */
3906         for (i = 0; i < adapter->num_tx_queues; i++) {
3907                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3908                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3909         }
3910
3911         /* Disable the Tx DMA engine on 82599 and X540 */
3912         switch (hw->mac.type) {
3913         case ixgbe_mac_82599EB:
3914         case ixgbe_mac_X540:
3915                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3916                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3917                                  ~IXGBE_DMATXCTL_TE));
3918                 break;
3919         default:
3920                 break;
3921         }
3922
3923         if (!pci_channel_offline(adapter->pdev))
3924                 ixgbe_reset(adapter);
3925
3926         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3927         if (hw->mac.ops.disable_tx_laser &&
3928             ((hw->phy.multispeed_fiber) ||
3929              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3930               (hw->mac.type == ixgbe_mac_82599EB))))
3931                 hw->mac.ops.disable_tx_laser(hw);
3932
3933         ixgbe_clean_all_tx_rings(adapter);
3934         ixgbe_clean_all_rx_rings(adapter);
3935
3936 #ifdef CONFIG_IXGBE_DCA
3937         /* since we reset the hardware DCA settings were cleared */
3938         ixgbe_setup_dca(adapter);
3939 #endif
3940 }
3941
3942 /**
3943  * ixgbe_poll - NAPI Rx polling callback
3944  * @napi: structure for representing this polling device
3945  * @budget: how many packets driver is allowed to clean
3946  *
3947  * This function is used for legacy and MSI, NAPI mode
3948  **/
3949 static int ixgbe_poll(struct napi_struct *napi, int budget)
3950 {
3951         struct ixgbe_q_vector *q_vector =
3952                                 container_of(napi, struct ixgbe_q_vector, napi);
3953         struct ixgbe_adapter *adapter = q_vector->adapter;
3954         struct ixgbe_ring *ring;
3955         int per_ring_budget;
3956         bool clean_complete = true;
3957
3958 #ifdef CONFIG_IXGBE_DCA
3959         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3960                 ixgbe_update_dca(q_vector);
3961 #endif
3962
3963         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3964                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3965
3966         /* attempt to distribute budget to each queue fairly, but don't allow
3967          * the budget to go below 1 because we'll exit polling */
3968         if (q_vector->rx.count > 1)
3969                 per_ring_budget = max(budget/q_vector->rx.count, 1);
3970         else
3971                 per_ring_budget = budget;
3972
3973         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3974                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3975                                                      per_ring_budget);
3976
3977         /* If all work not completed, return budget and keep polling */
3978         if (!clean_complete)
3979                 return budget;
3980
3981         /* all work done, exit the polling mode */
3982         napi_complete(napi);
3983         if (adapter->rx_itr_setting & 1)
3984                 ixgbe_set_itr(q_vector);
3985         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3986                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3987
3988         return 0;
3989 }
3990
3991 /**
3992  * ixgbe_tx_timeout - Respond to a Tx Hang
3993  * @netdev: network interface device structure
3994  **/
3995 static void ixgbe_tx_timeout(struct net_device *netdev)
3996 {
3997         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3998
3999         /* Do the reset outside of interrupt context */
4000         ixgbe_tx_timeout_reset(adapter);
4001 }
4002
4003 /**
4004  * ixgbe_set_rss_queues: Allocate queues for RSS
4005  * @adapter: board private structure to initialize
4006  *
4007  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4008  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4009  *
4010  **/
4011 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4012 {
4013         bool ret = false;
4014         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4015
4016         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4017                 f->mask = 0xF;
4018                 adapter->num_rx_queues = f->indices;
4019                 adapter->num_tx_queues = f->indices;
4020                 ret = true;
4021         } else {
4022                 ret = false;
4023         }
4024
4025         return ret;
4026 }
4027
4028 /**
4029  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4030  * @adapter: board private structure to initialize
4031  *
4032  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4033  * to the original CPU that initiated the Tx session.  This runs in addition
4034  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4035  * Rx load across CPUs using RSS.
4036  *
4037  **/
4038 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4039 {
4040         bool ret = false;
4041         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4042
4043         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4044         f_fdir->mask = 0;
4045
4046         /* Flow Director must have RSS enabled */
4047         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4048             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4049                 adapter->num_tx_queues = f_fdir->indices;
4050                 adapter->num_rx_queues = f_fdir->indices;
4051                 ret = true;
4052         } else {
4053                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4054         }
4055         return ret;
4056 }
4057
4058 #ifdef IXGBE_FCOE
4059 /**
4060  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4061  * @adapter: board private structure to initialize
4062  *
4063  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4064  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4065  * rx queues out of the max number of rx queues, instead, it is used as the
4066  * index of the first rx queue used by FCoE.
4067  *
4068  **/
4069 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4070 {
4071         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4072
4073         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4074                 return false;
4075
4076         f->indices = min((int)num_online_cpus(), f->indices);
4077
4078         adapter->num_rx_queues = 1;
4079         adapter->num_tx_queues = 1;
4080
4081         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4082                 e_info(probe, "FCoE enabled with RSS\n");
4083                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4084                         ixgbe_set_fdir_queues(adapter);
4085                 else
4086                         ixgbe_set_rss_queues(adapter);
4087         }
4088
4089         /* adding FCoE rx rings to the end */
4090         f->mask = adapter->num_rx_queues;
4091         adapter->num_rx_queues += f->indices;
4092         adapter->num_tx_queues += f->indices;
4093
4094         return true;
4095 }
4096 #endif /* IXGBE_FCOE */
4097
4098 /* Artificial max queue cap per traffic class in DCB mode */
4099 #define DCB_QUEUE_CAP 8
4100
4101 #ifdef CONFIG_IXGBE_DCB
4102 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4103 {
4104         int per_tc_q, q, i, offset = 0;
4105         struct net_device *dev = adapter->netdev;
4106         int tcs = netdev_get_num_tc(dev);
4107
4108         if (!tcs)
4109                 return false;
4110
4111         /* Map queue offset and counts onto allocated tx queues */
4112         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4113         q = min((int)num_online_cpus(), per_tc_q);
4114
4115         for (i = 0; i < tcs; i++) {
4116                 netdev_set_prio_tc_map(dev, i, i);
4117                 netdev_set_tc_queue(dev, i, q, offset);
4118                 offset += q;
4119         }
4120
4121         adapter->num_tx_queues = q * tcs;
4122         adapter->num_rx_queues = q * tcs;
4123
4124 #ifdef IXGBE_FCOE
4125         /* FCoE enabled queues require special configuration indexed
4126          * by feature specific indices and mask. Here we map FCoE
4127          * indices onto the DCB queue pairs allowing FCoE to own
4128          * configuration later.
4129          */
4130         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4131                 int tc;
4132                 struct ixgbe_ring_feature *f =
4133                                         &adapter->ring_feature[RING_F_FCOE];
4134
4135                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4136                 f->indices = dev->tc_to_txq[tc].count;
4137                 f->mask = dev->tc_to_txq[tc].offset;
4138         }
4139 #endif
4140
4141         return true;
4142 }
4143 #endif
4144
4145 /**
4146  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4147  * @adapter: board private structure to initialize
4148  *
4149  * IOV doesn't actually use anything, so just NAK the
4150  * request for now and let the other queue routines
4151  * figure out what to do.
4152  */
4153 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4154 {
4155         return false;
4156 }
4157
4158 /*
4159  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4160  * @adapter: board private structure to initialize
4161  *
4162  * This is the top level queue allocation routine.  The order here is very
4163  * important, starting with the "most" number of features turned on at once,
4164  * and ending with the smallest set of features.  This way large combinations
4165  * can be allocated if they're turned on, and smaller combinations are the
4166  * fallthrough conditions.
4167  *
4168  **/
4169 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4170 {
4171         /* Start with base case */
4172         adapter->num_rx_queues = 1;
4173         adapter->num_tx_queues = 1;
4174         adapter->num_rx_pools = adapter->num_rx_queues;
4175         adapter->num_rx_queues_per_pool = 1;
4176
4177         if (ixgbe_set_sriov_queues(adapter))
4178                 goto done;
4179
4180 #ifdef CONFIG_IXGBE_DCB
4181         if (ixgbe_set_dcb_queues(adapter))
4182                 goto done;
4183
4184 #endif
4185 #ifdef IXGBE_FCOE
4186         if (ixgbe_set_fcoe_queues(adapter))
4187                 goto done;
4188
4189 #endif /* IXGBE_FCOE */
4190         if (ixgbe_set_fdir_queues(adapter))
4191                 goto done;
4192
4193         if (ixgbe_set_rss_queues(adapter))
4194                 goto done;
4195
4196         /* fallback to base case */
4197         adapter->num_rx_queues = 1;
4198         adapter->num_tx_queues = 1;
4199
4200 done:
4201         /* Notify the stack of the (possibly) reduced queue counts. */
4202         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4203         return netif_set_real_num_rx_queues(adapter->netdev,
4204                                             adapter->num_rx_queues);
4205 }
4206
4207 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4208                                        int vectors)
4209 {
4210         int err, vector_threshold;
4211
4212         /* We'll want at least 3 (vector_threshold):
4213          * 1) TxQ[0] Cleanup
4214          * 2) RxQ[0] Cleanup
4215          * 3) Other (Link Status Change, etc.)
4216          * 4) TCP Timer (optional)
4217          */
4218         vector_threshold = MIN_MSIX_COUNT;
4219
4220         /* The more we get, the more we will assign to Tx/Rx Cleanup
4221          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4222          * Right now, we simply care about how many we'll get; we'll
4223          * set them up later while requesting irq's.
4224          */
4225         while (vectors >= vector_threshold) {
4226                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4227                                       vectors);
4228                 if (!err) /* Success in acquiring all requested vectors. */
4229                         break;
4230                 else if (err < 0)
4231                         vectors = 0; /* Nasty failure, quit now */
4232                 else /* err == number of vectors we should try again with */
4233                         vectors = err;
4234         }
4235
4236         if (vectors < vector_threshold) {
4237                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4238                  * This just means we'll go with either a single MSI
4239                  * vector or fall back to legacy interrupts.
4240                  */
4241                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4242                              "Unable to allocate MSI-X interrupts\n");
4243                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4244                 kfree(adapter->msix_entries);
4245                 adapter->msix_entries = NULL;
4246         } else {
4247                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4248                 /*
4249                  * Adjust for only the vectors we'll use, which is minimum
4250                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4251                  * vectors we were allocated.
4252                  */
4253                 adapter->num_msix_vectors = min(vectors,
4254                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4255         }
4256 }
4257
4258 /**
4259  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4260  * @adapter: board private structure to initialize
4261  *
4262  * Cache the descriptor ring offsets for RSS to the assigned rings.
4263  *
4264  **/
4265 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4266 {
4267         int i;
4268
4269         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4270                 return false;
4271
4272         for (i = 0; i < adapter->num_rx_queues; i++)
4273                 adapter->rx_ring[i]->reg_idx = i;
4274         for (i = 0; i < adapter->num_tx_queues; i++)
4275                 adapter->tx_ring[i]->reg_idx = i;
4276
4277         return true;
4278 }
4279
4280 #ifdef CONFIG_IXGBE_DCB
4281
4282 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4283 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4284                                     unsigned int *tx, unsigned int *rx)
4285 {
4286         struct net_device *dev = adapter->netdev;
4287         struct ixgbe_hw *hw = &adapter->hw;
4288         u8 num_tcs = netdev_get_num_tc(dev);
4289
4290         *tx = 0;
4291         *rx = 0;
4292
4293         switch (hw->mac.type) {
4294         case ixgbe_mac_82598EB:
4295                 *tx = tc << 2;
4296                 *rx = tc << 3;
4297                 break;
4298         case ixgbe_mac_82599EB:
4299         case ixgbe_mac_X540:
4300                 if (num_tcs > 4) {
4301                         if (tc < 3) {
4302                                 *tx = tc << 5;
4303                                 *rx = tc << 4;
4304                         } else if (tc <  5) {
4305                                 *tx = ((tc + 2) << 4);
4306                                 *rx = tc << 4;
4307                         } else if (tc < num_tcs) {
4308                                 *tx = ((tc + 8) << 3);
4309                                 *rx = tc << 4;
4310                         }
4311                 } else {
4312                         *rx =  tc << 5;
4313                         switch (tc) {
4314                         case 0:
4315                                 *tx =  0;
4316                                 break;
4317                         case 1:
4318                                 *tx = 64;
4319                                 break;
4320                         case 2:
4321                                 *tx = 96;
4322                                 break;
4323                         case 3:
4324                                 *tx = 112;
4325                                 break;
4326                         default:
4327                                 break;
4328                         }
4329                 }
4330                 break;
4331         default:
4332                 break;
4333         }
4334 }
4335
4336 /**
4337  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4338  * @adapter: board private structure to initialize
4339  *
4340  * Cache the descriptor ring offsets for DCB to the assigned rings.
4341  *
4342  **/
4343 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4344 {
4345         struct net_device *dev = adapter->netdev;
4346         int i, j, k;
4347         u8 num_tcs = netdev_get_num_tc(dev);
4348
4349         if (!num_tcs)
4350                 return false;
4351
4352         for (i = 0, k = 0; i < num_tcs; i++) {
4353                 unsigned int tx_s, rx_s;
4354                 u16 count = dev->tc_to_txq[i].count;
4355
4356                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4357                 for (j = 0; j < count; j++, k++) {
4358                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4359                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4360                         adapter->tx_ring[k]->dcb_tc = i;
4361                         adapter->rx_ring[k]->dcb_tc = i;
4362                 }
4363         }
4364
4365         return true;
4366 }
4367 #endif
4368
4369 /**
4370  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4371  * @adapter: board private structure to initialize
4372  *
4373  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4374  *
4375  **/
4376 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4377 {
4378         int i;
4379         bool ret = false;
4380
4381         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4382             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4383                 for (i = 0; i < adapter->num_rx_queues; i++)
4384                         adapter->rx_ring[i]->reg_idx = i;
4385                 for (i = 0; i < adapter->num_tx_queues; i++)
4386                         adapter->tx_ring[i]->reg_idx = i;
4387                 ret = true;
4388         }
4389
4390         return ret;
4391 }
4392
4393 #ifdef IXGBE_FCOE
4394 /**
4395  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4396  * @adapter: board private structure to initialize
4397  *
4398  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4399  *
4400  */
4401 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4402 {
4403         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4404         int i;
4405         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4406
4407         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4408                 return false;
4409
4410         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4411                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4412                         ixgbe_cache_ring_fdir(adapter);
4413                 else
4414                         ixgbe_cache_ring_rss(adapter);
4415
4416                 fcoe_rx_i = f->mask;
4417                 fcoe_tx_i = f->mask;
4418         }
4419         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4420                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4421                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4422         }
4423         return true;
4424 }
4425
4426 #endif /* IXGBE_FCOE */
4427 /**
4428  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4429  * @adapter: board private structure to initialize
4430  *
4431  * SR-IOV doesn't use any descriptor rings but changes the default if
4432  * no other mapping is used.
4433  *
4434  */
4435 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4436 {
4437         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4438         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4439         if (adapter->num_vfs)
4440                 return true;
4441         else
4442                 return false;
4443 }
4444
4445 /**
4446  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4447  * @adapter: board private structure to initialize
4448  *
4449  * Once we know the feature-set enabled for the device, we'll cache
4450  * the register offset the descriptor ring is assigned to.
4451  *
4452  * Note, the order the various feature calls is important.  It must start with
4453  * the "most" features enabled at the same time, then trickle down to the
4454  * least amount of features turned on at once.
4455  **/
4456 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4457 {
4458         /* start with default case */
4459         adapter->rx_ring[0]->reg_idx = 0;
4460         adapter->tx_ring[0]->reg_idx = 0;
4461
4462         if (ixgbe_cache_ring_sriov(adapter))
4463                 return;
4464
4465 #ifdef CONFIG_IXGBE_DCB
4466         if (ixgbe_cache_ring_dcb(adapter))
4467                 return;
4468 #endif
4469
4470 #ifdef IXGBE_FCOE
4471         if (ixgbe_cache_ring_fcoe(adapter))
4472                 return;
4473 #endif /* IXGBE_FCOE */
4474
4475         if (ixgbe_cache_ring_fdir(adapter))
4476                 return;
4477
4478         if (ixgbe_cache_ring_rss(adapter))
4479                 return;
4480 }
4481
4482 /**
4483  * ixgbe_alloc_queues - Allocate memory for all rings
4484  * @adapter: board private structure to initialize
4485  *
4486  * We allocate one ring per queue at run-time since we don't know the
4487  * number of queues at compile-time.  The polling_netdev array is
4488  * intended for Multiqueue, but should work fine with a single queue.
4489  **/
4490 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4491 {
4492         int rx = 0, tx = 0, nid = adapter->node;
4493
4494         if (nid < 0 || !node_online(nid))
4495                 nid = first_online_node;
4496
4497         for (; tx < adapter->num_tx_queues; tx++) {
4498                 struct ixgbe_ring *ring;
4499
4500                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4501                 if (!ring)
4502                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4503                 if (!ring)
4504                         goto err_allocation;
4505                 ring->count = adapter->tx_ring_count;
4506                 ring->queue_index = tx;
4507                 ring->numa_node = nid;
4508                 ring->dev = &adapter->pdev->dev;
4509                 ring->netdev = adapter->netdev;
4510
4511                 adapter->tx_ring[tx] = ring;
4512         }
4513
4514         for (; rx < adapter->num_rx_queues; rx++) {
4515                 struct ixgbe_ring *ring;
4516
4517                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4518                 if (!ring)
4519                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4520                 if (!ring)
4521                         goto err_allocation;
4522                 ring->count = adapter->rx_ring_count;
4523                 ring->queue_index = rx;
4524                 ring->numa_node = nid;
4525                 ring->dev = &adapter->pdev->dev;
4526                 ring->netdev = adapter->netdev;
4527
4528                 adapter->rx_ring[rx] = ring;
4529         }
4530
4531         ixgbe_cache_ring_register(adapter);
4532
4533         return 0;
4534
4535 err_allocation:
4536         while (tx)
4537                 kfree(adapter->tx_ring[--tx]);
4538
4539         while (rx)
4540                 kfree(adapter->rx_ring[--rx]);
4541         return -ENOMEM;
4542 }
4543
4544 /**
4545  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4546  * @adapter: board private structure to initialize
4547  *
4548  * Attempt to configure the interrupts using the best available
4549  * capabilities of the hardware and the kernel.
4550  **/
4551 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4552 {
4553         struct ixgbe_hw *hw = &adapter->hw;
4554         int err = 0;
4555         int vector, v_budget;
4556
4557         /*
4558          * It's easy to be greedy for MSI-X vectors, but it really
4559          * doesn't do us much good if we have a lot more vectors
4560          * than CPU's.  So let's be conservative and only ask for
4561          * (roughly) the same number of vectors as there are CPU's.
4562          */
4563         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4564                        (int)num_online_cpus()) + NON_Q_VECTORS;
4565
4566         /*
4567          * At the same time, hardware can only support a maximum of
4568          * hw.mac->max_msix_vectors vectors.  With features
4569          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4570          * descriptor queues supported by our device.  Thus, we cap it off in
4571          * those rare cases where the cpu count also exceeds our vector limit.
4572          */
4573         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4574
4575         /* A failure in MSI-X entry allocation isn't fatal, but it does
4576          * mean we disable MSI-X capabilities of the adapter. */
4577         adapter->msix_entries = kcalloc(v_budget,
4578                                         sizeof(struct msix_entry), GFP_KERNEL);
4579         if (adapter->msix_entries) {
4580                 for (vector = 0; vector < v_budget; vector++)
4581                         adapter->msix_entries[vector].entry = vector;
4582
4583                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4584
4585                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4586                         goto out;
4587         }
4588
4589         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4590         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4591         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4592                 e_err(probe,
4593                       "ATR is not supported while multiple "
4594                       "queues are disabled.  Disabling Flow Director\n");
4595         }
4596         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4597         adapter->atr_sample_rate = 0;
4598         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4599                 ixgbe_disable_sriov(adapter);
4600
4601         err = ixgbe_set_num_queues(adapter);
4602         if (err)
4603                 return err;
4604
4605         err = pci_enable_msi(adapter->pdev);
4606         if (!err) {
4607                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4608         } else {
4609                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4610                              "Unable to allocate MSI interrupt, "
4611                              "falling back to legacy.  Error: %d\n", err);
4612                 /* reset err */
4613                 err = 0;
4614         }
4615
4616 out:
4617         return err;
4618 }
4619
4620 /**
4621  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4622  * @adapter: board private structure to initialize
4623  *
4624  * We allocate one q_vector per queue interrupt.  If allocation fails we
4625  * return -ENOMEM.
4626  **/
4627 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4628 {
4629         int v_idx, num_q_vectors;
4630         struct ixgbe_q_vector *q_vector;
4631
4632         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4633                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4634         else
4635                 num_q_vectors = 1;
4636
4637         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4638                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4639                                         GFP_KERNEL, adapter->node);
4640                 if (!q_vector)
4641                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4642                                            GFP_KERNEL);
4643                 if (!q_vector)
4644                         goto err_out;
4645
4646                 q_vector->adapter = adapter;
4647                 q_vector->v_idx = v_idx;
4648
4649                 /* Allocate the affinity_hint cpumask, configure the mask */
4650                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4651                         goto err_out;
4652                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4653
4654                 if (q_vector->tx.count && !q_vector->rx.count)
4655                         q_vector->eitr = adapter->tx_eitr_param;
4656                 else
4657                         q_vector->eitr = adapter->rx_eitr_param;
4658
4659                 netif_napi_add(adapter->netdev, &q_vector->napi,
4660                                ixgbe_poll, 64);
4661                 adapter->q_vector[v_idx] = q_vector;
4662         }
4663
4664         return 0;
4665
4666 err_out:
4667         while (v_idx) {
4668                 v_idx--;
4669                 q_vector = adapter->q_vector[v_idx];
4670                 netif_napi_del(&q_vector->napi);
4671                 free_cpumask_var(q_vector->affinity_mask);
4672                 kfree(q_vector);
4673                 adapter->q_vector[v_idx] = NULL;
4674         }
4675         return -ENOMEM;
4676 }
4677
4678 /**
4679  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4680  * @adapter: board private structure to initialize
4681  *
4682  * This function frees the memory allocated to the q_vectors.  In addition if
4683  * NAPI is enabled it will delete any references to the NAPI struct prior
4684  * to freeing the q_vector.
4685  **/
4686 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4687 {
4688         int v_idx, num_q_vectors;
4689
4690         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4691                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4692         else
4693                 num_q_vectors = 1;
4694
4695         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4696                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4697                 adapter->q_vector[v_idx] = NULL;
4698                 netif_napi_del(&q_vector->napi);
4699                 free_cpumask_var(q_vector->affinity_mask);
4700                 kfree(q_vector);
4701         }
4702 }
4703
4704 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4705 {
4706         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4707                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4708                 pci_disable_msix(adapter->pdev);
4709                 kfree(adapter->msix_entries);
4710                 adapter->msix_entries = NULL;
4711         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4712                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4713                 pci_disable_msi(adapter->pdev);
4714         }
4715 }
4716
4717 /**
4718  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4719  * @adapter: board private structure to initialize
4720  *
4721  * We determine which interrupt scheme to use based on...
4722  * - Kernel support (MSI, MSI-X)
4723  *   - which can be user-defined (via MODULE_PARAM)
4724  * - Hardware queue count (num_*_queues)
4725  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4726  **/
4727 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4728 {
4729         int err;
4730
4731         /* Number of supported queues */
4732         err = ixgbe_set_num_queues(adapter);
4733         if (err)
4734                 return err;
4735
4736         err = ixgbe_set_interrupt_capability(adapter);
4737         if (err) {
4738                 e_dev_err("Unable to setup interrupt capabilities\n");
4739                 goto err_set_interrupt;
4740         }
4741
4742         err = ixgbe_alloc_q_vectors(adapter);
4743         if (err) {
4744                 e_dev_err("Unable to allocate memory for queue vectors\n");
4745                 goto err_alloc_q_vectors;
4746         }
4747
4748         err = ixgbe_alloc_queues(adapter);
4749         if (err) {
4750                 e_dev_err("Unable to allocate memory for queues\n");
4751                 goto err_alloc_queues;
4752         }
4753
4754         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4755                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4756                    adapter->num_rx_queues, adapter->num_tx_queues);
4757
4758         set_bit(__IXGBE_DOWN, &adapter->state);
4759
4760         return 0;
4761
4762 err_alloc_queues:
4763         ixgbe_free_q_vectors(adapter);
4764 err_alloc_q_vectors:
4765         ixgbe_reset_interrupt_capability(adapter);
4766 err_set_interrupt:
4767         return err;
4768 }
4769
4770 /**
4771  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4772  * @adapter: board private structure to clear interrupt scheme on
4773  *
4774  * We go through and clear interrupt specific resources and reset the structure
4775  * to pre-load conditions
4776  **/
4777 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4778 {
4779         int i;
4780
4781         for (i = 0; i < adapter->num_tx_queues; i++) {
4782                 kfree(adapter->tx_ring[i]);
4783                 adapter->tx_ring[i] = NULL;
4784         }
4785         for (i = 0; i < adapter->num_rx_queues; i++) {
4786                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4787
4788                 /* ixgbe_get_stats64() might access this ring, we must wait
4789                  * a grace period before freeing it.
4790                  */
4791                 kfree_rcu(ring, rcu);
4792                 adapter->rx_ring[i] = NULL;
4793         }
4794
4795         adapter->num_tx_queues = 0;
4796         adapter->num_rx_queues = 0;
4797
4798         ixgbe_free_q_vectors(adapter);
4799         ixgbe_reset_interrupt_capability(adapter);
4800 }
4801
4802 /**
4803  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4804  * @adapter: board private structure to initialize
4805  *
4806  * ixgbe_sw_init initializes the Adapter private data structure.
4807  * Fields are initialized based on PCI device information and
4808  * OS network device settings (MTU size).
4809  **/
4810 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4811 {
4812         struct ixgbe_hw *hw = &adapter->hw;
4813         struct pci_dev *pdev = adapter->pdev;
4814         struct net_device *dev = adapter->netdev;
4815         unsigned int rss;
4816 #ifdef CONFIG_IXGBE_DCB
4817         int j;
4818         struct tc_configuration *tc;
4819 #endif
4820         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4821
4822         /* PCI config space info */
4823
4824         hw->vendor_id = pdev->vendor;
4825         hw->device_id = pdev->device;
4826         hw->revision_id = pdev->revision;
4827         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4828         hw->subsystem_device_id = pdev->subsystem_device;
4829
4830         /* Set capability flags */
4831         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4832         adapter->ring_feature[RING_F_RSS].indices = rss;
4833         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4834         switch (hw->mac.type) {
4835         case ixgbe_mac_82598EB:
4836                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4837                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4838                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4839                 break;
4840         case ixgbe_mac_82599EB:
4841         case ixgbe_mac_X540:
4842                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4843                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4844                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4845                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4846                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4847                 /* Flow Director hash filters enabled */
4848                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4849                 adapter->atr_sample_rate = 20;
4850                 adapter->ring_feature[RING_F_FDIR].indices =
4851                                                          IXGBE_MAX_FDIR_INDICES;
4852                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4853 #ifdef IXGBE_FCOE
4854                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4855                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4856                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4857 #ifdef CONFIG_IXGBE_DCB
4858                 /* Default traffic class to use for FCoE */
4859                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4860 #endif
4861 #endif /* IXGBE_FCOE */
4862                 break;
4863         default:
4864                 break;
4865         }
4866
4867         /* n-tuple support exists, always init our spinlock */
4868         spin_lock_init(&adapter->fdir_perfect_lock);
4869
4870 #ifdef CONFIG_IXGBE_DCB
4871         /* Configure DCB traffic classes */
4872         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4873                 tc = &adapter->dcb_cfg.tc_config[j];
4874                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4875                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4876                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4877                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4878                 tc->dcb_pfc = pfc_disabled;
4879         }
4880         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4881         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4882         adapter->dcb_cfg.pfc_mode_enable = false;
4883         adapter->dcb_set_bitmap = 0x00;
4884         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4885         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4886                            MAX_TRAFFIC_CLASS);
4887
4888 #endif
4889
4890         /* default flow control settings */
4891         hw->fc.requested_mode = ixgbe_fc_full;
4892         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4893 #ifdef CONFIG_DCB
4894         adapter->last_lfc_mode = hw->fc.current_mode;
4895 #endif
4896         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4897         hw->fc.low_water = FC_LOW_WATER(max_frame);
4898         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4899         hw->fc.send_xon = true;
4900         hw->fc.disable_fc_autoneg = false;
4901
4902         /* enable itr by default in dynamic mode */
4903         adapter->rx_itr_setting = 1;
4904         adapter->rx_eitr_param = 20000;
4905         adapter->tx_itr_setting = 1;
4906         adapter->tx_eitr_param = 10000;
4907
4908         /* set defaults for eitr in MegaBytes */
4909         adapter->eitr_low = 10;
4910         adapter->eitr_high = 20;
4911
4912         /* set default ring sizes */
4913         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4914         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4915
4916         /* set default work limits */
4917         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4918
4919         /* initialize eeprom parameters */
4920         if (ixgbe_init_eeprom_params_generic(hw)) {
4921                 e_dev_err("EEPROM initialization failed\n");
4922                 return -EIO;
4923         }
4924
4925         /* enable rx csum by default */
4926         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4927
4928         /* get assigned NUMA node */
4929         adapter->node = dev_to_node(&pdev->dev);
4930
4931         set_bit(__IXGBE_DOWN, &adapter->state);
4932
4933         return 0;
4934 }
4935
4936 /**
4937  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4938  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4939  *
4940  * Return 0 on success, negative on failure
4941  **/
4942 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4943 {
4944         struct device *dev = tx_ring->dev;
4945         int size;
4946
4947         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4948         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4949         if (!tx_ring->tx_buffer_info)
4950                 tx_ring->tx_buffer_info = vzalloc(size);
4951         if (!tx_ring->tx_buffer_info)
4952                 goto err;
4953
4954         /* round up to nearest 4K */
4955         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4956         tx_ring->size = ALIGN(tx_ring->size, 4096);
4957
4958         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4959                                            &tx_ring->dma, GFP_KERNEL);
4960         if (!tx_ring->desc)
4961                 goto err;
4962
4963         tx_ring->next_to_use = 0;
4964         tx_ring->next_to_clean = 0;
4965         return 0;
4966
4967 err:
4968         vfree(tx_ring->tx_buffer_info);
4969         tx_ring->tx_buffer_info = NULL;
4970         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4971         return -ENOMEM;
4972 }
4973
4974 /**
4975  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4976  * @adapter: board private structure
4977  *
4978  * If this function returns with an error, then it's possible one or
4979  * more of the rings is populated (while the rest are not).  It is the
4980  * callers duty to clean those orphaned rings.
4981  *
4982  * Return 0 on success, negative on failure
4983  **/
4984 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4985 {
4986         int i, err = 0;
4987
4988         for (i = 0; i < adapter->num_tx_queues; i++) {
4989                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4990                 if (!err)
4991                         continue;
4992                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4993                 break;
4994         }
4995
4996         return err;
4997 }
4998
4999 /**
5000  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5001  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5002  *
5003  * Returns 0 on success, negative on failure
5004  **/
5005 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5006 {
5007         struct device *dev = rx_ring->dev;
5008         int size;
5009
5010         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5011         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5012         if (!rx_ring->rx_buffer_info)
5013                 rx_ring->rx_buffer_info = vzalloc(size);
5014         if (!rx_ring->rx_buffer_info)
5015                 goto err;
5016
5017         /* Round up to nearest 4K */
5018         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5019         rx_ring->size = ALIGN(rx_ring->size, 4096);
5020
5021         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5022                                            &rx_ring->dma, GFP_KERNEL);
5023
5024         if (!rx_ring->desc)
5025                 goto err;
5026
5027         rx_ring->next_to_clean = 0;
5028         rx_ring->next_to_use = 0;
5029
5030         return 0;
5031 err:
5032         vfree(rx_ring->rx_buffer_info);
5033         rx_ring->rx_buffer_info = NULL;
5034         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5035         return -ENOMEM;
5036 }
5037
5038 /**
5039  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5040  * @adapter: board private structure
5041  *
5042  * If this function returns with an error, then it's possible one or
5043  * more of the rings is populated (while the rest are not).  It is the
5044  * callers duty to clean those orphaned rings.
5045  *
5046  * Return 0 on success, negative on failure
5047  **/
5048 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5049 {
5050         int i, err = 0;
5051
5052         for (i = 0; i < adapter->num_rx_queues; i++) {
5053                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5054                 if (!err)
5055                         continue;
5056                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5057                 break;
5058         }
5059
5060         return err;
5061 }
5062
5063 /**
5064  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5065  * @tx_ring: Tx descriptor ring for a specific queue
5066  *
5067  * Free all transmit software resources
5068  **/
5069 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5070 {
5071         ixgbe_clean_tx_ring(tx_ring);
5072
5073         vfree(tx_ring->tx_buffer_info);
5074         tx_ring->tx_buffer_info = NULL;
5075
5076         /* if not set, then don't free */
5077         if (!tx_ring->desc)
5078                 return;
5079
5080         dma_free_coherent(tx_ring->dev, tx_ring->size,
5081                           tx_ring->desc, tx_ring->dma);
5082
5083         tx_ring->desc = NULL;
5084 }
5085
5086 /**
5087  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5088  * @adapter: board private structure
5089  *
5090  * Free all transmit software resources
5091  **/
5092 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5093 {
5094         int i;
5095
5096         for (i = 0; i < adapter->num_tx_queues; i++)
5097                 if (adapter->tx_ring[i]->desc)
5098                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5099 }
5100
5101 /**
5102  * ixgbe_free_rx_resources - Free Rx Resources
5103  * @rx_ring: ring to clean the resources from
5104  *
5105  * Free all receive software resources
5106  **/
5107 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5108 {
5109         ixgbe_clean_rx_ring(rx_ring);
5110
5111         vfree(rx_ring->rx_buffer_info);
5112         rx_ring->rx_buffer_info = NULL;
5113
5114         /* if not set, then don't free */
5115         if (!rx_ring->desc)
5116                 return;
5117
5118         dma_free_coherent(rx_ring->dev, rx_ring->size,
5119                           rx_ring->desc, rx_ring->dma);
5120
5121         rx_ring->desc = NULL;
5122 }
5123
5124 /**
5125  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5126  * @adapter: board private structure
5127  *
5128  * Free all receive software resources
5129  **/
5130 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5131 {
5132         int i;
5133
5134         for (i = 0; i < adapter->num_rx_queues; i++)
5135                 if (adapter->rx_ring[i]->desc)
5136                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5137 }
5138
5139 /**
5140  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5141  * @netdev: network interface device structure
5142  * @new_mtu: new value for maximum frame size
5143  *
5144  * Returns 0 on success, negative on failure
5145  **/
5146 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5147 {
5148         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5149         struct ixgbe_hw *hw = &adapter->hw;
5150         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5151
5152         /* MTU < 68 is an error and causes problems on some kernels */
5153         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5154             hw->mac.type != ixgbe_mac_X540) {
5155                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5156                         return -EINVAL;
5157         } else {
5158                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5159                         return -EINVAL;
5160         }
5161
5162         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5163         /* must set new MTU before calling down or up */
5164         netdev->mtu = new_mtu;
5165
5166         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5167         hw->fc.low_water = FC_LOW_WATER(max_frame);
5168
5169         if (netif_running(netdev))
5170                 ixgbe_reinit_locked(adapter);
5171
5172         return 0;
5173 }
5174
5175 /**
5176  * ixgbe_open - Called when a network interface is made active
5177  * @netdev: network interface device structure
5178  *
5179  * Returns 0 on success, negative value on failure
5180  *
5181  * The open entry point is called when a network interface is made
5182  * active by the system (IFF_UP).  At this point all resources needed
5183  * for transmit and receive operations are allocated, the interrupt
5184  * handler is registered with the OS, the watchdog timer is started,
5185  * and the stack is notified that the interface is ready.
5186  **/
5187 static int ixgbe_open(struct net_device *netdev)
5188 {
5189         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5190         int err;
5191
5192         /* disallow open during test */
5193         if (test_bit(__IXGBE_TESTING, &adapter->state))
5194                 return -EBUSY;
5195
5196         netif_carrier_off(netdev);
5197
5198         /* allocate transmit descriptors */
5199         err = ixgbe_setup_all_tx_resources(adapter);
5200         if (err)
5201                 goto err_setup_tx;
5202
5203         /* allocate receive descriptors */
5204         err = ixgbe_setup_all_rx_resources(adapter);
5205         if (err)
5206                 goto err_setup_rx;
5207
5208         ixgbe_configure(adapter);
5209
5210         err = ixgbe_request_irq(adapter);
5211         if (err)
5212                 goto err_req_irq;
5213
5214         err = ixgbe_up_complete(adapter);
5215         if (err)
5216                 goto err_up;
5217
5218         netif_tx_start_all_queues(netdev);
5219
5220         return 0;
5221
5222 err_up:
5223         ixgbe_release_hw_control(adapter);
5224         ixgbe_free_irq(adapter);
5225 err_req_irq:
5226 err_setup_rx:
5227         ixgbe_free_all_rx_resources(adapter);
5228 err_setup_tx:
5229         ixgbe_free_all_tx_resources(adapter);
5230         ixgbe_reset(adapter);
5231
5232         return err;
5233 }
5234
5235 /**
5236  * ixgbe_close - Disables a network interface
5237  * @netdev: network interface device structure
5238  *
5239  * Returns 0, this is not allowed to fail
5240  *
5241  * The close entry point is called when an interface is de-activated
5242  * by the OS.  The hardware is still under the drivers control, but
5243  * needs to be disabled.  A global MAC reset is issued to stop the
5244  * hardware, and all transmit and receive resources are freed.
5245  **/
5246 static int ixgbe_close(struct net_device *netdev)
5247 {
5248         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5249
5250         ixgbe_down(adapter);
5251         ixgbe_free_irq(adapter);
5252
5253         ixgbe_fdir_filter_exit(adapter);
5254
5255         ixgbe_free_all_tx_resources(adapter);
5256         ixgbe_free_all_rx_resources(adapter);
5257
5258         ixgbe_release_hw_control(adapter);
5259
5260         return 0;
5261 }
5262
5263 #ifdef CONFIG_PM
5264 static int ixgbe_resume(struct pci_dev *pdev)
5265 {
5266         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5267         struct net_device *netdev = adapter->netdev;
5268         u32 err;
5269
5270         pci_set_power_state(pdev, PCI_D0);
5271         pci_restore_state(pdev);
5272         /*
5273          * pci_restore_state clears dev->state_saved so call
5274          * pci_save_state to restore it.
5275          */
5276         pci_save_state(pdev);
5277
5278         err = pci_enable_device_mem(pdev);
5279         if (err) {
5280                 e_dev_err("Cannot enable PCI device from suspend\n");
5281                 return err;
5282         }
5283         pci_set_master(pdev);
5284
5285         pci_wake_from_d3(pdev, false);
5286
5287         err = ixgbe_init_interrupt_scheme(adapter);
5288         if (err) {
5289                 e_dev_err("Cannot initialize interrupts for device\n");
5290                 return err;
5291         }
5292
5293         ixgbe_reset(adapter);
5294
5295         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5296
5297         if (netif_running(netdev)) {
5298                 err = ixgbe_open(netdev);
5299                 if (err)
5300                         return err;
5301         }
5302
5303         netif_device_attach(netdev);
5304
5305         return 0;
5306 }
5307 #endif /* CONFIG_PM */
5308
5309 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5310 {
5311         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5312         struct net_device *netdev = adapter->netdev;
5313         struct ixgbe_hw *hw = &adapter->hw;
5314         u32 ctrl, fctrl;
5315         u32 wufc = adapter->wol;
5316 #ifdef CONFIG_PM
5317         int retval = 0;
5318 #endif
5319
5320         netif_device_detach(netdev);
5321
5322         if (netif_running(netdev)) {
5323                 ixgbe_down(adapter);
5324                 ixgbe_free_irq(adapter);
5325                 ixgbe_free_all_tx_resources(adapter);
5326                 ixgbe_free_all_rx_resources(adapter);
5327         }
5328
5329         ixgbe_clear_interrupt_scheme(adapter);
5330 #ifdef CONFIG_DCB
5331         kfree(adapter->ixgbe_ieee_pfc);
5332         kfree(adapter->ixgbe_ieee_ets);
5333 #endif
5334
5335 #ifdef CONFIG_PM
5336         retval = pci_save_state(pdev);
5337         if (retval)
5338                 return retval;
5339
5340 #endif
5341         if (wufc) {
5342                 ixgbe_set_rx_mode(netdev);
5343
5344                 /* turn on all-multi mode if wake on multicast is enabled */
5345                 if (wufc & IXGBE_WUFC_MC) {
5346                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5347                         fctrl |= IXGBE_FCTRL_MPE;
5348                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5349                 }
5350
5351                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5352                 ctrl |= IXGBE_CTRL_GIO_DIS;
5353                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5354
5355                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5356         } else {
5357                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5358                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5359         }
5360
5361         switch (hw->mac.type) {
5362         case ixgbe_mac_82598EB:
5363                 pci_wake_from_d3(pdev, false);
5364                 break;
5365         case ixgbe_mac_82599EB:
5366         case ixgbe_mac_X540:
5367                 pci_wake_from_d3(pdev, !!wufc);
5368                 break;
5369         default:
5370                 break;
5371         }
5372
5373         *enable_wake = !!wufc;
5374
5375         ixgbe_release_hw_control(adapter);
5376
5377         pci_disable_device(pdev);
5378
5379         return 0;
5380 }
5381
5382 #ifdef CONFIG_PM
5383 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5384 {
5385         int retval;
5386         bool wake;
5387
5388         retval = __ixgbe_shutdown(pdev, &wake);
5389         if (retval)
5390                 return retval;
5391
5392         if (wake) {
5393                 pci_prepare_to_sleep(pdev);
5394         } else {
5395                 pci_wake_from_d3(pdev, false);
5396                 pci_set_power_state(pdev, PCI_D3hot);
5397         }
5398
5399         return 0;
5400 }
5401 #endif /* CONFIG_PM */
5402
5403 static void ixgbe_shutdown(struct pci_dev *pdev)
5404 {
5405         bool wake;
5406
5407         __ixgbe_shutdown(pdev, &wake);
5408
5409         if (system_state == SYSTEM_POWER_OFF) {
5410                 pci_wake_from_d3(pdev, wake);
5411                 pci_set_power_state(pdev, PCI_D3hot);
5412         }
5413 }
5414
5415 /**
5416  * ixgbe_update_stats - Update the board statistics counters.
5417  * @adapter: board private structure
5418  **/
5419 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5420 {
5421         struct net_device *netdev = adapter->netdev;
5422         struct ixgbe_hw *hw = &adapter->hw;
5423         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5424         u64 total_mpc = 0;
5425         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5426         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5427         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5428         u64 bytes = 0, packets = 0;
5429
5430         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5431             test_bit(__IXGBE_RESETTING, &adapter->state))
5432                 return;
5433
5434         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5435                 u64 rsc_count = 0;
5436                 u64 rsc_flush = 0;
5437                 for (i = 0; i < 16; i++)
5438                         adapter->hw_rx_no_dma_resources +=
5439                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5440                 for (i = 0; i < adapter->num_rx_queues; i++) {
5441                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5442                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5443                 }
5444                 adapter->rsc_total_count = rsc_count;
5445                 adapter->rsc_total_flush = rsc_flush;
5446         }
5447
5448         for (i = 0; i < adapter->num_rx_queues; i++) {
5449                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5450                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5451                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5452                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5453                 bytes += rx_ring->stats.bytes;
5454                 packets += rx_ring->stats.packets;
5455         }
5456         adapter->non_eop_descs = non_eop_descs;
5457         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5458         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5459         netdev->stats.rx_bytes = bytes;
5460         netdev->stats.rx_packets = packets;
5461
5462         bytes = 0;
5463         packets = 0;
5464         /* gather some stats to the adapter struct that are per queue */
5465         for (i = 0; i < adapter->num_tx_queues; i++) {
5466                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5467                 restart_queue += tx_ring->tx_stats.restart_queue;
5468                 tx_busy += tx_ring->tx_stats.tx_busy;
5469                 bytes += tx_ring->stats.bytes;
5470                 packets += tx_ring->stats.packets;
5471         }
5472         adapter->restart_queue = restart_queue;
5473         adapter->tx_busy = tx_busy;
5474         netdev->stats.tx_bytes = bytes;
5475         netdev->stats.tx_packets = packets;
5476
5477         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5478         for (i = 0; i < 8; i++) {
5479                 /* for packet buffers not used, the register should read 0 */
5480                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5481                 missed_rx += mpc;
5482                 hwstats->mpc[i] += mpc;
5483                 total_mpc += hwstats->mpc[i];
5484                 if (hw->mac.type == ixgbe_mac_82598EB)
5485                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5486                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5487                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5488                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5489                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5490                 switch (hw->mac.type) {
5491                 case ixgbe_mac_82598EB:
5492                         hwstats->pxonrxc[i] +=
5493                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5494                         break;
5495                 case ixgbe_mac_82599EB:
5496                 case ixgbe_mac_X540:
5497                         hwstats->pxonrxc[i] +=
5498                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5499                         break;
5500                 default:
5501                         break;
5502                 }
5503                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5504                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5505         }
5506         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5507         /* work around hardware counting issue */
5508         hwstats->gprc -= missed_rx;
5509
5510         ixgbe_update_xoff_received(adapter);
5511
5512         /* 82598 hardware only has a 32 bit counter in the high register */
5513         switch (hw->mac.type) {
5514         case ixgbe_mac_82598EB:
5515                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5516                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5517                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5518                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5519                 break;
5520         case ixgbe_mac_X540:
5521                 /* OS2BMC stats are X540 only*/
5522                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5523                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5524                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5525                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5526         case ixgbe_mac_82599EB:
5527                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5528                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5529                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5530                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5531                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5532                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5533                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5534                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5535                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5536 #ifdef IXGBE_FCOE
5537                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5538                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5539                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5540                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5541                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5542                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5543 #endif /* IXGBE_FCOE */
5544                 break;
5545         default:
5546                 break;
5547         }
5548         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5549         hwstats->bprc += bprc;
5550         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5551         if (hw->mac.type == ixgbe_mac_82598EB)
5552                 hwstats->mprc -= bprc;
5553         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5554         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5555         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5556         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5557         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5558         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5559         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5560         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5561         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5562         hwstats->lxontxc += lxon;
5563         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5564         hwstats->lxofftxc += lxoff;
5565         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5566         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5567         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5568         /*
5569          * 82598 errata - tx of flow control packets is included in tx counters
5570          */
5571         xon_off_tot = lxon + lxoff;
5572         hwstats->gptc -= xon_off_tot;
5573         hwstats->mptc -= xon_off_tot;
5574         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5575         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5576         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5577         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5578         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5579         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5580         hwstats->ptc64 -= xon_off_tot;
5581         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5582         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5583         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5584         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5585         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5586         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5587
5588         /* Fill out the OS statistics structure */
5589         netdev->stats.multicast = hwstats->mprc;
5590
5591         /* Rx Errors */
5592         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5593         netdev->stats.rx_dropped = 0;
5594         netdev->stats.rx_length_errors = hwstats->rlec;
5595         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5596         netdev->stats.rx_missed_errors = total_mpc;
5597 }
5598
5599 /**
5600  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5601  * @adapter - pointer to the device adapter structure
5602  **/
5603 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5604 {
5605         struct ixgbe_hw *hw = &adapter->hw;
5606         int i;
5607
5608         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5609                 return;
5610
5611         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5612
5613         /* if interface is down do nothing */
5614         if (test_bit(__IXGBE_DOWN, &adapter->state))
5615                 return;
5616
5617         /* do nothing if we are not using signature filters */
5618         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5619                 return;
5620
5621         adapter->fdir_overflow++;
5622
5623         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5624                 for (i = 0; i < adapter->num_tx_queues; i++)
5625                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5626                                 &(adapter->tx_ring[i]->state));
5627                 /* re-enable flow director interrupts */
5628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5629         } else {
5630                 e_err(probe, "failed to finish FDIR re-initialization, "
5631                       "ignored adding FDIR ATR filters\n");
5632         }
5633 }
5634
5635 /**
5636  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5637  * @adapter - pointer to the device adapter structure
5638  *
5639  * This function serves two purposes.  First it strobes the interrupt lines
5640  * in order to make certain interrupts are occuring.  Secondly it sets the
5641  * bits needed to check for TX hangs.  As a result we should immediately
5642  * determine if a hang has occured.
5643  */
5644 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5645 {
5646         struct ixgbe_hw *hw = &adapter->hw;
5647         u64 eics = 0;
5648         int i;
5649
5650         /* If we're down or resetting, just bail */
5651         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5652             test_bit(__IXGBE_RESETTING, &adapter->state))
5653                 return;
5654
5655         /* Force detection of hung controller */
5656         if (netif_carrier_ok(adapter->netdev)) {
5657                 for (i = 0; i < adapter->num_tx_queues; i++)
5658                         set_check_for_tx_hang(adapter->tx_ring[i]);
5659         }
5660
5661         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5662                 /*
5663                  * for legacy and MSI interrupts don't set any bits
5664                  * that are enabled for EIAM, because this operation
5665                  * would set *both* EIMS and EICS for any bit in EIAM
5666                  */
5667                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5668                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5669         } else {
5670                 /* get one bit for every active tx/rx interrupt vector */
5671                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5672                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5673                         if (qv->rx.ring || qv->tx.ring)
5674                                 eics |= ((u64)1 << i);
5675                 }
5676         }
5677
5678         /* Cause software interrupt to ensure rings are cleaned */
5679         ixgbe_irq_rearm_queues(adapter, eics);
5680
5681 }
5682
5683 /**
5684  * ixgbe_watchdog_update_link - update the link status
5685  * @adapter - pointer to the device adapter structure
5686  * @link_speed - pointer to a u32 to store the link_speed
5687  **/
5688 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5689 {
5690         struct ixgbe_hw *hw = &adapter->hw;
5691         u32 link_speed = adapter->link_speed;
5692         bool link_up = adapter->link_up;
5693         int i;
5694
5695         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5696                 return;
5697
5698         if (hw->mac.ops.check_link) {
5699                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5700         } else {
5701                 /* always assume link is up, if no check link function */
5702                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5703                 link_up = true;
5704         }
5705         if (link_up) {
5706                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5707                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5708                                 hw->mac.ops.fc_enable(hw, i);
5709                 } else {
5710                         hw->mac.ops.fc_enable(hw, 0);
5711                 }
5712         }
5713
5714         if (link_up ||
5715             time_after(jiffies, (adapter->link_check_timeout +
5716                                  IXGBE_TRY_LINK_TIMEOUT))) {
5717                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5718                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5719                 IXGBE_WRITE_FLUSH(hw);
5720         }
5721
5722         adapter->link_up = link_up;
5723         adapter->link_speed = link_speed;
5724 }
5725
5726 /**
5727  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5728  *                             print link up message
5729  * @adapter - pointer to the device adapter structure
5730  **/
5731 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5732 {
5733         struct net_device *netdev = adapter->netdev;
5734         struct ixgbe_hw *hw = &adapter->hw;
5735         u32 link_speed = adapter->link_speed;
5736         bool flow_rx, flow_tx;
5737
5738         /* only continue if link was previously down */
5739         if (netif_carrier_ok(netdev))
5740                 return;
5741
5742         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5743
5744         switch (hw->mac.type) {
5745         case ixgbe_mac_82598EB: {
5746                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5747                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5748                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5749                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5750         }
5751                 break;
5752         case ixgbe_mac_X540:
5753         case ixgbe_mac_82599EB: {
5754                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5755                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5756                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5757                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5758         }
5759                 break;
5760         default:
5761                 flow_tx = false;
5762                 flow_rx = false;
5763                 break;
5764         }
5765         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5766                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5767                "10 Gbps" :
5768                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5769                "1 Gbps" :
5770                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5771                "100 Mbps" :
5772                "unknown speed"))),
5773                ((flow_rx && flow_tx) ? "RX/TX" :
5774                (flow_rx ? "RX" :
5775                (flow_tx ? "TX" : "None"))));
5776
5777         netif_carrier_on(netdev);
5778         ixgbe_check_vf_rate_limit(adapter);
5779 }
5780
5781 /**
5782  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5783  *                               print link down message
5784  * @adapter - pointer to the adapter structure
5785  **/
5786 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5787 {
5788         struct net_device *netdev = adapter->netdev;
5789         struct ixgbe_hw *hw = &adapter->hw;
5790
5791         adapter->link_up = false;
5792         adapter->link_speed = 0;
5793
5794         /* only continue if link was up previously */
5795         if (!netif_carrier_ok(netdev))
5796                 return;
5797
5798         /* poll for SFP+ cable when link is down */
5799         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5800                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5801
5802         e_info(drv, "NIC Link is Down\n");
5803         netif_carrier_off(netdev);
5804 }
5805
5806 /**
5807  * ixgbe_watchdog_flush_tx - flush queues on link down
5808  * @adapter - pointer to the device adapter structure
5809  **/
5810 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5811 {
5812         int i;
5813         int some_tx_pending = 0;
5814
5815         if (!netif_carrier_ok(adapter->netdev)) {
5816                 for (i = 0; i < adapter->num_tx_queues; i++) {
5817                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5818                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5819                                 some_tx_pending = 1;
5820                                 break;
5821                         }
5822                 }
5823
5824                 if (some_tx_pending) {
5825                         /* We've lost link, so the controller stops DMA,
5826                          * but we've got queued Tx work that's never going
5827                          * to get done, so reset controller to flush Tx.
5828                          * (Do the reset outside of interrupt context).
5829                          */
5830                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5831                 }
5832         }
5833 }
5834
5835 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5836 {
5837         u32 ssvpc;
5838
5839         /* Do not perform spoof check for 82598 */
5840         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5841                 return;
5842
5843         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5844
5845         /*
5846          * ssvpc register is cleared on read, if zero then no
5847          * spoofed packets in the last interval.
5848          */
5849         if (!ssvpc)
5850                 return;
5851
5852         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5853 }
5854
5855 /**
5856  * ixgbe_watchdog_subtask - check and bring link up
5857  * @adapter - pointer to the device adapter structure
5858  **/
5859 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5860 {
5861         /* if interface is down do nothing */
5862         if (test_bit(__IXGBE_DOWN, &adapter->state))
5863                 return;
5864
5865         ixgbe_watchdog_update_link(adapter);
5866
5867         if (adapter->link_up)
5868                 ixgbe_watchdog_link_is_up(adapter);
5869         else
5870                 ixgbe_watchdog_link_is_down(adapter);
5871
5872         ixgbe_spoof_check(adapter);
5873         ixgbe_update_stats(adapter);
5874
5875         ixgbe_watchdog_flush_tx(adapter);
5876 }
5877
5878 /**
5879  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5880  * @adapter - the ixgbe adapter structure
5881  **/
5882 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5883 {
5884         struct ixgbe_hw *hw = &adapter->hw;
5885         s32 err;
5886
5887         /* not searching for SFP so there is nothing to do here */
5888         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5889             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5890                 return;
5891
5892         /* someone else is in init, wait until next service event */
5893         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5894                 return;
5895
5896         err = hw->phy.ops.identify_sfp(hw);
5897         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5898                 goto sfp_out;
5899
5900         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5901                 /* If no cable is present, then we need to reset
5902                  * the next time we find a good cable. */
5903                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5904         }
5905
5906         /* exit on error */
5907         if (err)
5908                 goto sfp_out;
5909
5910         /* exit if reset not needed */
5911         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5912                 goto sfp_out;
5913
5914         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5915
5916         /*
5917          * A module may be identified correctly, but the EEPROM may not have
5918          * support for that module.  setup_sfp() will fail in that case, so
5919          * we should not allow that module to load.
5920          */
5921         if (hw->mac.type == ixgbe_mac_82598EB)
5922                 err = hw->phy.ops.reset(hw);
5923         else
5924                 err = hw->mac.ops.setup_sfp(hw);
5925
5926         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5927                 goto sfp_out;
5928
5929         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5930         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5931
5932 sfp_out:
5933         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5934
5935         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5936             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5937                 e_dev_err("failed to initialize because an unsupported "
5938                           "SFP+ module type was detected.\n");
5939                 e_dev_err("Reload the driver after installing a "
5940                           "supported module.\n");
5941                 unregister_netdev(adapter->netdev);
5942         }
5943 }
5944
5945 /**
5946  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5947  * @adapter - the ixgbe adapter structure
5948  **/
5949 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5950 {
5951         struct ixgbe_hw *hw = &adapter->hw;
5952         u32 autoneg;
5953         bool negotiation;
5954
5955         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5956                 return;
5957
5958         /* someone else is in init, wait until next service event */
5959         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5960                 return;
5961
5962         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5963
5964         autoneg = hw->phy.autoneg_advertised;
5965         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5966                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5967         hw->mac.autotry_restart = false;
5968         if (hw->mac.ops.setup_link)
5969                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5970
5971         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5972         adapter->link_check_timeout = jiffies;
5973         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5974 }
5975
5976 /**
5977  * ixgbe_service_timer - Timer Call-back
5978  * @data: pointer to adapter cast into an unsigned long
5979  **/
5980 static void ixgbe_service_timer(unsigned long data)
5981 {
5982         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5983         unsigned long next_event_offset;
5984
5985         /* poll faster when waiting for link */
5986         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5987                 next_event_offset = HZ / 10;
5988         else
5989                 next_event_offset = HZ * 2;
5990
5991         /* Reset the timer */
5992         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5993
5994         ixgbe_service_event_schedule(adapter);
5995 }
5996
5997 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5998 {
5999         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6000                 return;
6001
6002         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6003
6004         /* If we're already down or resetting, just bail */
6005         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6006             test_bit(__IXGBE_RESETTING, &adapter->state))
6007                 return;
6008
6009         ixgbe_dump(adapter);
6010         netdev_err(adapter->netdev, "Reset adapter\n");
6011         adapter->tx_timeout_count++;
6012
6013         ixgbe_reinit_locked(adapter);
6014 }
6015
6016 /**
6017  * ixgbe_service_task - manages and runs subtasks
6018  * @work: pointer to work_struct containing our data
6019  **/
6020 static void ixgbe_service_task(struct work_struct *work)
6021 {
6022         struct ixgbe_adapter *adapter = container_of(work,
6023                                                      struct ixgbe_adapter,
6024                                                      service_task);
6025
6026         ixgbe_reset_subtask(adapter);
6027         ixgbe_sfp_detection_subtask(adapter);
6028         ixgbe_sfp_link_config_subtask(adapter);
6029         ixgbe_check_overtemp_subtask(adapter);
6030         ixgbe_watchdog_subtask(adapter);
6031         ixgbe_fdir_reinit_subtask(adapter);
6032         ixgbe_check_hang_subtask(adapter);
6033
6034         ixgbe_service_event_complete(adapter);
6035 }
6036
6037 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6038                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6039 {
6040         struct ixgbe_adv_tx_context_desc *context_desc;
6041         u16 i = tx_ring->next_to_use;
6042
6043         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6044
6045         i++;
6046         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6047
6048         /* set bits to identify this as an advanced context descriptor */
6049         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6050
6051         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6052         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6053         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6054         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6055 }
6056
6057 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6058                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6059 {
6060         int err;
6061         u32 vlan_macip_lens, type_tucmd;
6062         u32 mss_l4len_idx, l4len;
6063
6064         if (!skb_is_gso(skb))
6065                 return 0;
6066
6067         if (skb_header_cloned(skb)) {
6068                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6069                 if (err)
6070                         return err;
6071         }
6072
6073         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6074         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6075
6076         if (protocol == __constant_htons(ETH_P_IP)) {
6077                 struct iphdr *iph = ip_hdr(skb);
6078                 iph->tot_len = 0;
6079                 iph->check = 0;
6080                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6081                                                          iph->daddr, 0,
6082                                                          IPPROTO_TCP,
6083                                                          0);
6084                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6085         } else if (skb_is_gso_v6(skb)) {
6086                 ipv6_hdr(skb)->payload_len = 0;
6087                 tcp_hdr(skb)->check =
6088                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6089                                      &ipv6_hdr(skb)->daddr,
6090                                      0, IPPROTO_TCP, 0);
6091         }
6092
6093         l4len = tcp_hdrlen(skb);
6094         *hdr_len = skb_transport_offset(skb) + l4len;
6095
6096         /* mss_l4len_id: use 1 as index for TSO */
6097         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6098         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6099         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6100
6101         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6102         vlan_macip_lens = skb_network_header_len(skb);
6103         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6104         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6105
6106         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6107                           mss_l4len_idx);
6108
6109         return 1;
6110 }
6111
6112 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6113                           struct sk_buff *skb, u32 tx_flags,
6114                           __be16 protocol)
6115 {
6116         u32 vlan_macip_lens = 0;
6117         u32 mss_l4len_idx = 0;
6118         u32 type_tucmd = 0;
6119
6120         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6121             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6122                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6123                         return false;
6124         } else {
6125                 u8 l4_hdr = 0;
6126                 switch (protocol) {
6127                 case __constant_htons(ETH_P_IP):
6128                         vlan_macip_lens |= skb_network_header_len(skb);
6129                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6130                         l4_hdr = ip_hdr(skb)->protocol;
6131                         break;
6132                 case __constant_htons(ETH_P_IPV6):
6133                         vlan_macip_lens |= skb_network_header_len(skb);
6134                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6135                         break;
6136                 default:
6137                         if (unlikely(net_ratelimit())) {
6138                                 dev_warn(tx_ring->dev,
6139                                  "partial checksum but proto=%x!\n",
6140                                  skb->protocol);
6141                         }
6142                         break;
6143                 }
6144
6145                 switch (l4_hdr) {
6146                 case IPPROTO_TCP:
6147                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6148                         mss_l4len_idx = tcp_hdrlen(skb) <<
6149                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6150                         break;
6151                 case IPPROTO_SCTP:
6152                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6153                         mss_l4len_idx = sizeof(struct sctphdr) <<
6154                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6155                         break;
6156                 case IPPROTO_UDP:
6157                         mss_l4len_idx = sizeof(struct udphdr) <<
6158                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6159                         break;
6160                 default:
6161                         if (unlikely(net_ratelimit())) {
6162                                 dev_warn(tx_ring->dev,
6163                                  "partial checksum but l4 proto=%x!\n",
6164                                  skb->protocol);
6165                         }
6166                         break;
6167                 }
6168         }
6169
6170         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6171         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6172
6173         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6174                           type_tucmd, mss_l4len_idx);
6175
6176         return (skb->ip_summed == CHECKSUM_PARTIAL);
6177 }
6178
6179 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6180 {
6181         /* set type for advanced descriptor with frame checksum insertion */
6182         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6183                                       IXGBE_ADVTXD_DCMD_IFCS |
6184                                       IXGBE_ADVTXD_DCMD_DEXT);
6185
6186         /* set HW vlan bit if vlan is present */
6187         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6188                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6189
6190         /* set segmentation enable bits for TSO/FSO */
6191 #ifdef IXGBE_FCOE
6192         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6193 #else
6194         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6195 #endif
6196                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6197
6198         return cmd_type;
6199 }
6200
6201 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6202 {
6203         __le32 olinfo_status =
6204                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6205
6206         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6207                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6208                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6209                 /* enble IPv4 checksum for TSO */
6210                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6211                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6212         }
6213
6214         /* enable L4 checksum for TSO and TX checksum offload */
6215         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6216                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6217
6218 #ifdef IXGBE_FCOE
6219         /* use index 1 context for FCOE/FSO */
6220         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6221                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6222                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6223
6224 #endif
6225         /*
6226          * Check Context must be set if Tx switch is enabled, which it
6227          * always is for case where virtual functions are running
6228          */
6229         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6230                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6231
6232         return olinfo_status;
6233 }
6234
6235 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6236                        IXGBE_TXD_CMD_RS)
6237
6238 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6239                          struct sk_buff *skb,
6240                          struct ixgbe_tx_buffer *first,
6241                          u32 tx_flags,
6242                          const u8 hdr_len)
6243 {
6244         struct device *dev = tx_ring->dev;
6245         struct ixgbe_tx_buffer *tx_buffer_info;
6246         union ixgbe_adv_tx_desc *tx_desc;
6247         dma_addr_t dma;
6248         __le32 cmd_type, olinfo_status;
6249         struct skb_frag_struct *frag;
6250         unsigned int f = 0;
6251         unsigned int data_len = skb->data_len;
6252         unsigned int size = skb_headlen(skb);
6253         u32 offset = 0;
6254         u32 paylen = skb->len - hdr_len;
6255         u16 i = tx_ring->next_to_use;
6256         u16 gso_segs;
6257
6258 #ifdef IXGBE_FCOE
6259         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6260                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6261                         data_len -= sizeof(struct fcoe_crc_eof);
6262                 } else {
6263                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6264                         data_len = 0;
6265                 }
6266         }
6267
6268 #endif
6269         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6270         if (dma_mapping_error(dev, dma))
6271                 goto dma_error;
6272
6273         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6274         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6275
6276         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6277
6278         for (;;) {
6279                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6280                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6281                         tx_desc->read.cmd_type_len =
6282                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6283                         tx_desc->read.olinfo_status = olinfo_status;
6284
6285                         offset += IXGBE_MAX_DATA_PER_TXD;
6286                         size -= IXGBE_MAX_DATA_PER_TXD;
6287
6288                         tx_desc++;
6289                         i++;
6290                         if (i == tx_ring->count) {
6291                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6292                                 i = 0;
6293                         }
6294                 }
6295
6296                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6297                 tx_buffer_info->length = offset + size;
6298                 tx_buffer_info->tx_flags = tx_flags;
6299                 tx_buffer_info->dma = dma;
6300
6301                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6302                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6303                 tx_desc->read.olinfo_status = olinfo_status;
6304
6305                 if (!data_len)
6306                         break;
6307
6308                 frag = &skb_shinfo(skb)->frags[f];
6309 #ifdef IXGBE_FCOE
6310                 size = min_t(unsigned int, data_len, frag->size);
6311 #else
6312                 size = frag->size;
6313 #endif
6314                 data_len -= size;
6315                 f++;
6316
6317                 offset = 0;
6318                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6319
6320                 dma = dma_map_page(dev, frag->page, frag->page_offset,
6321                                    size, DMA_TO_DEVICE);
6322                 if (dma_mapping_error(dev, dma))
6323                         goto dma_error;
6324
6325                 tx_desc++;
6326                 i++;
6327                 if (i == tx_ring->count) {
6328                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6329                         i = 0;
6330                 }
6331         }
6332
6333         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6334
6335         i++;
6336         if (i == tx_ring->count)
6337                 i = 0;
6338
6339         tx_ring->next_to_use = i;
6340
6341         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6342                 gso_segs = skb_shinfo(skb)->gso_segs;
6343 #ifdef IXGBE_FCOE
6344         /* adjust for FCoE Sequence Offload */
6345         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6346                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6347                                         skb_shinfo(skb)->gso_size);
6348 #endif /* IXGBE_FCOE */
6349         else
6350                 gso_segs = 1;
6351
6352         /* multiply data chunks by size of headers */
6353         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6354         tx_buffer_info->gso_segs = gso_segs;
6355         tx_buffer_info->skb = skb;
6356
6357         /* set the timestamp */
6358         first->time_stamp = jiffies;
6359
6360         /*
6361          * Force memory writes to complete before letting h/w
6362          * know there are new descriptors to fetch.  (Only
6363          * applicable for weak-ordered memory model archs,
6364          * such as IA-64).
6365          */
6366         wmb();
6367
6368         /* set next_to_watch value indicating a packet is present */
6369         first->next_to_watch = tx_desc;
6370
6371         /* notify HW of packet */
6372         writel(i, tx_ring->tail);
6373
6374         return;
6375 dma_error:
6376         dev_err(dev, "TX DMA map failed\n");
6377
6378         /* clear dma mappings for failed tx_buffer_info map */
6379         for (;;) {
6380                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6381                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6382                 if (tx_buffer_info == first)
6383                         break;
6384                 if (i == 0)
6385                         i = tx_ring->count;
6386                 i--;
6387         }
6388
6389         dev_kfree_skb_any(skb);
6390
6391         tx_ring->next_to_use = i;
6392 }
6393
6394 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6395                       u32 tx_flags, __be16 protocol)
6396 {
6397         struct ixgbe_q_vector *q_vector = ring->q_vector;
6398         union ixgbe_atr_hash_dword input = { .dword = 0 };
6399         union ixgbe_atr_hash_dword common = { .dword = 0 };
6400         union {
6401                 unsigned char *network;
6402                 struct iphdr *ipv4;
6403                 struct ipv6hdr *ipv6;
6404         } hdr;
6405         struct tcphdr *th;
6406         __be16 vlan_id;
6407
6408         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6409         if (!q_vector)
6410                 return;
6411
6412         /* do nothing if sampling is disabled */
6413         if (!ring->atr_sample_rate)
6414                 return;
6415
6416         ring->atr_count++;
6417
6418         /* snag network header to get L4 type and address */
6419         hdr.network = skb_network_header(skb);
6420
6421         /* Currently only IPv4/IPv6 with TCP is supported */
6422         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6423              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6424             (protocol != __constant_htons(ETH_P_IP) ||
6425              hdr.ipv4->protocol != IPPROTO_TCP))
6426                 return;
6427
6428         th = tcp_hdr(skb);
6429
6430         /* skip this packet since it is invalid or the socket is closing */
6431         if (!th || th->fin)
6432                 return;
6433
6434         /* sample on all syn packets or once every atr sample count */
6435         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6436                 return;
6437
6438         /* reset sample count */
6439         ring->atr_count = 0;
6440
6441         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6442
6443         /*
6444          * src and dst are inverted, think how the receiver sees them
6445          *
6446          * The input is broken into two sections, a non-compressed section
6447          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6448          * is XORed together and stored in the compressed dword.
6449          */
6450         input.formatted.vlan_id = vlan_id;
6451
6452         /*
6453          * since src port and flex bytes occupy the same word XOR them together
6454          * and write the value to source port portion of compressed dword
6455          */
6456         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6457                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6458         else
6459                 common.port.src ^= th->dest ^ protocol;
6460         common.port.dst ^= th->source;
6461
6462         if (protocol == __constant_htons(ETH_P_IP)) {
6463                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6464                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6465         } else {
6466                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6467                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6468                              hdr.ipv6->saddr.s6_addr32[1] ^
6469                              hdr.ipv6->saddr.s6_addr32[2] ^
6470                              hdr.ipv6->saddr.s6_addr32[3] ^
6471                              hdr.ipv6->daddr.s6_addr32[0] ^
6472                              hdr.ipv6->daddr.s6_addr32[1] ^
6473                              hdr.ipv6->daddr.s6_addr32[2] ^
6474                              hdr.ipv6->daddr.s6_addr32[3];
6475         }
6476
6477         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6478         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6479                                               input, common, ring->queue_index);
6480 }
6481
6482 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6483 {
6484         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6485         /* Herbert's original patch had:
6486          *  smp_mb__after_netif_stop_queue();
6487          * but since that doesn't exist yet, just open code it. */
6488         smp_mb();
6489
6490         /* We need to check again in a case another CPU has just
6491          * made room available. */
6492         if (likely(ixgbe_desc_unused(tx_ring) < size))
6493                 return -EBUSY;
6494
6495         /* A reprieve! - use start_queue because it doesn't call schedule */
6496         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6497         ++tx_ring->tx_stats.restart_queue;
6498         return 0;
6499 }
6500
6501 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6502 {
6503         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6504                 return 0;
6505         return __ixgbe_maybe_stop_tx(tx_ring, size);
6506 }
6507
6508 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6509 {
6510         struct ixgbe_adapter *adapter = netdev_priv(dev);
6511         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6512                                                smp_processor_id();
6513 #ifdef IXGBE_FCOE
6514         __be16 protocol = vlan_get_protocol(skb);
6515
6516         if (((protocol == htons(ETH_P_FCOE)) ||
6517             (protocol == htons(ETH_P_FIP))) &&
6518             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6519                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6520                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6521                 return txq;
6522         }
6523 #endif
6524
6525         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6526                 while (unlikely(txq >= dev->real_num_tx_queues))
6527                         txq -= dev->real_num_tx_queues;
6528                 return txq;
6529         }
6530
6531         return skb_tx_hash(dev, skb);
6532 }
6533
6534 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6535                           struct ixgbe_adapter *adapter,
6536                           struct ixgbe_ring *tx_ring)
6537 {
6538         struct ixgbe_tx_buffer *first;
6539         int tso;
6540         u32 tx_flags = 0;
6541 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6542         unsigned short f;
6543 #endif
6544         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6545         __be16 protocol = skb->protocol;
6546         u8 hdr_len = 0;
6547
6548         /*
6549          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6550          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6551          *       + 2 desc gap to keep tail from touching head,
6552          *       + 1 desc for context descriptor,
6553          * otherwise try next time
6554          */
6555 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6556         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6557                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6558 #else
6559         count += skb_shinfo(skb)->nr_frags;
6560 #endif
6561         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6562                 tx_ring->tx_stats.tx_busy++;
6563                 return NETDEV_TX_BUSY;
6564         }
6565
6566 #ifdef CONFIG_PCI_IOV
6567         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6568                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6569
6570 #endif
6571         /* if we have a HW VLAN tag being added default to the HW one */
6572         if (vlan_tx_tag_present(skb)) {
6573                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6574                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6575         /* else if it is a SW VLAN check the next protocol and store the tag */
6576         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6577                 struct vlan_hdr *vhdr, _vhdr;
6578                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6579                 if (!vhdr)
6580                         goto out_drop;
6581
6582                 protocol = vhdr->h_vlan_encapsulated_proto;
6583                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6584                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6585         }
6586
6587         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6588             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6589              (skb->priority != TC_PRIO_CONTROL))) {
6590                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6591                 tx_flags |= tx_ring->dcb_tc <<
6592                             IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6593                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6594                         struct vlan_ethhdr *vhdr;
6595                         if (skb_header_cloned(skb) &&
6596                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6597                                 goto out_drop;
6598                         vhdr = (struct vlan_ethhdr *)skb->data;
6599                         vhdr->h_vlan_TCI = htons(tx_flags >>
6600                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6601                 } else {
6602                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6603                 }
6604         }
6605
6606         /* record the location of the first descriptor for this packet */
6607         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6608
6609 #ifdef IXGBE_FCOE
6610         /* setup tx offload for FCoE */
6611         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6612             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6613                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6614                 if (tso < 0)
6615                         goto out_drop;
6616                 else if (tso)
6617                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6618                                     IXGBE_TX_FLAGS_FCOE;
6619                 else
6620                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6621
6622                 goto xmit_fcoe;
6623         }
6624
6625 #endif /* IXGBE_FCOE */
6626         /* setup IPv4/IPv6 offloads */
6627         if (protocol == __constant_htons(ETH_P_IP))
6628                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6629
6630         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6631         if (tso < 0)
6632                 goto out_drop;
6633         else if (tso)
6634                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6635         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6636                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6637
6638         /* add the ATR filter if ATR is on */
6639         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6640                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6641
6642 #ifdef IXGBE_FCOE
6643 xmit_fcoe:
6644 #endif /* IXGBE_FCOE */
6645         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6646
6647         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6648
6649         return NETDEV_TX_OK;
6650
6651 out_drop:
6652         dev_kfree_skb_any(skb);
6653         return NETDEV_TX_OK;
6654 }
6655
6656 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6657 {
6658         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6659         struct ixgbe_ring *tx_ring;
6660
6661         tx_ring = adapter->tx_ring[skb->queue_mapping];
6662         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6663 }
6664
6665 /**
6666  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6667  * @netdev: network interface device structure
6668  * @p: pointer to an address structure
6669  *
6670  * Returns 0 on success, negative on failure
6671  **/
6672 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6673 {
6674         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6675         struct ixgbe_hw *hw = &adapter->hw;
6676         struct sockaddr *addr = p;
6677
6678         if (!is_valid_ether_addr(addr->sa_data))
6679                 return -EADDRNOTAVAIL;
6680
6681         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6682         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6683
6684         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6685                             IXGBE_RAH_AV);
6686
6687         return 0;
6688 }
6689
6690 static int
6691 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6692 {
6693         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6694         struct ixgbe_hw *hw = &adapter->hw;
6695         u16 value;
6696         int rc;
6697
6698         if (prtad != hw->phy.mdio.prtad)
6699                 return -EINVAL;
6700         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6701         if (!rc)
6702                 rc = value;
6703         return rc;
6704 }
6705
6706 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6707                             u16 addr, u16 value)
6708 {
6709         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6710         struct ixgbe_hw *hw = &adapter->hw;
6711
6712         if (prtad != hw->phy.mdio.prtad)
6713                 return -EINVAL;
6714         return hw->phy.ops.write_reg(hw, addr, devad, value);
6715 }
6716
6717 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6718 {
6719         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6720
6721         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6722 }
6723
6724 /**
6725  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6726  * netdev->dev_addrs
6727  * @netdev: network interface device structure
6728  *
6729  * Returns non-zero on failure
6730  **/
6731 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6732 {
6733         int err = 0;
6734         struct ixgbe_adapter *adapter = netdev_priv(dev);
6735         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6736
6737         if (is_valid_ether_addr(mac->san_addr)) {
6738                 rtnl_lock();
6739                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6740                 rtnl_unlock();
6741         }
6742         return err;
6743 }
6744
6745 /**
6746  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6747  * netdev->dev_addrs
6748  * @netdev: network interface device structure
6749  *
6750  * Returns non-zero on failure
6751  **/
6752 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6753 {
6754         int err = 0;
6755         struct ixgbe_adapter *adapter = netdev_priv(dev);
6756         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6757
6758         if (is_valid_ether_addr(mac->san_addr)) {
6759                 rtnl_lock();
6760                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6761                 rtnl_unlock();
6762         }
6763         return err;
6764 }
6765
6766 #ifdef CONFIG_NET_POLL_CONTROLLER
6767 /*
6768  * Polling 'interrupt' - used by things like netconsole to send skbs
6769  * without having to re-enable interrupts. It's not called while
6770  * the interrupt routine is executing.
6771  */
6772 static void ixgbe_netpoll(struct net_device *netdev)
6773 {
6774         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6775         int i;
6776
6777         /* if interface is down do nothing */
6778         if (test_bit(__IXGBE_DOWN, &adapter->state))
6779                 return;
6780
6781         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6782         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6783                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6784                 for (i = 0; i < num_q_vectors; i++) {
6785                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6786                         ixgbe_msix_clean_rings(0, q_vector);
6787                 }
6788         } else {
6789                 ixgbe_intr(adapter->pdev->irq, netdev);
6790         }
6791         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6792 }
6793 #endif
6794
6795 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6796                                                    struct rtnl_link_stats64 *stats)
6797 {
6798         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6799         int i;
6800
6801         rcu_read_lock();
6802         for (i = 0; i < adapter->num_rx_queues; i++) {
6803                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6804                 u64 bytes, packets;
6805                 unsigned int start;
6806
6807                 if (ring) {
6808                         do {
6809                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6810                                 packets = ring->stats.packets;
6811                                 bytes   = ring->stats.bytes;
6812                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6813                         stats->rx_packets += packets;
6814                         stats->rx_bytes   += bytes;
6815                 }
6816         }
6817
6818         for (i = 0; i < adapter->num_tx_queues; i++) {
6819                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6820                 u64 bytes, packets;
6821                 unsigned int start;
6822
6823                 if (ring) {
6824                         do {
6825                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6826                                 packets = ring->stats.packets;
6827                                 bytes   = ring->stats.bytes;
6828                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6829                         stats->tx_packets += packets;
6830                         stats->tx_bytes   += bytes;
6831                 }
6832         }
6833         rcu_read_unlock();
6834         /* following stats updated by ixgbe_watchdog_task() */
6835         stats->multicast        = netdev->stats.multicast;
6836         stats->rx_errors        = netdev->stats.rx_errors;
6837         stats->rx_length_errors = netdev->stats.rx_length_errors;
6838         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6839         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6840         return stats;
6841 }
6842
6843 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6844  * #adapter: pointer to ixgbe_adapter
6845  * @tc: number of traffic classes currently enabled
6846  *
6847  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6848  * 802.1Q priority maps to a packet buffer that exists.
6849  */
6850 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6851 {
6852         struct ixgbe_hw *hw = &adapter->hw;
6853         u32 reg, rsave;
6854         int i;
6855
6856         /* 82598 have a static priority to TC mapping that can not
6857          * be changed so no validation is needed.
6858          */
6859         if (hw->mac.type == ixgbe_mac_82598EB)
6860                 return;
6861
6862         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6863         rsave = reg;
6864
6865         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6866                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6867
6868                 /* If up2tc is out of bounds default to zero */
6869                 if (up2tc > tc)
6870                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6871         }
6872
6873         if (reg != rsave)
6874                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6875
6876         return;
6877 }
6878
6879
6880 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6881  * classes.
6882  *
6883  * @netdev: net device to configure
6884  * @tc: number of traffic classes to enable
6885  */
6886 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6887 {
6888         struct ixgbe_adapter *adapter = netdev_priv(dev);
6889         struct ixgbe_hw *hw = &adapter->hw;
6890
6891         /* Multiple traffic classes requires multiple queues */
6892         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6893                 e_err(drv, "Enable failed, needs MSI-X\n");
6894                 return -EINVAL;
6895         }
6896
6897         /* Hardware supports up to 8 traffic classes */
6898         if (tc > MAX_TRAFFIC_CLASS ||
6899             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6900                 return -EINVAL;
6901
6902         /* Hardware has to reinitialize queues and interrupts to
6903          * match packet buffer alignment. Unfortunantly, the
6904          * hardware is not flexible enough to do this dynamically.
6905          */
6906         if (netif_running(dev))
6907                 ixgbe_close(dev);
6908         ixgbe_clear_interrupt_scheme(adapter);
6909
6910         if (tc) {
6911                 netdev_set_num_tc(dev, tc);
6912                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6913
6914                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6915                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6916
6917                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6918                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
6919         } else {
6920                 netdev_reset_tc(dev);
6921
6922                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6923
6924                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6925                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6926
6927                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6928                 adapter->dcb_cfg.pfc_mode_enable = false;
6929         }
6930
6931         ixgbe_init_interrupt_scheme(adapter);
6932         ixgbe_validate_rtr(adapter, tc);
6933         if (netif_running(dev))
6934                 ixgbe_open(dev);
6935
6936         return 0;
6937 }
6938
6939 void ixgbe_do_reset(struct net_device *netdev)
6940 {
6941         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6942
6943         if (netif_running(netdev))
6944                 ixgbe_reinit_locked(adapter);
6945         else
6946                 ixgbe_reset(adapter);
6947 }
6948
6949 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6950 {
6951         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6952
6953 #ifdef CONFIG_DCB
6954         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6955                 data &= ~NETIF_F_HW_VLAN_RX;
6956 #endif
6957
6958         /* return error if RXHASH is being enabled when RSS is not supported */
6959         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6960                 data &= ~NETIF_F_RXHASH;
6961
6962         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6963         if (!(data & NETIF_F_RXCSUM))
6964                 data &= ~NETIF_F_LRO;
6965
6966         /* Turn off LRO if not RSC capable or invalid ITR settings */
6967         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6968                 data &= ~NETIF_F_LRO;
6969         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6970                    (adapter->rx_itr_setting != 1 &&
6971                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6972                 data &= ~NETIF_F_LRO;
6973                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6974         }
6975
6976         return data;
6977 }
6978
6979 static int ixgbe_set_features(struct net_device *netdev, u32 data)
6980 {
6981         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6982         bool need_reset = false;
6983
6984         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6985         if (!(data & NETIF_F_RXCSUM))
6986                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6987         else
6988                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6989
6990         /* Make sure RSC matches LRO, reset if change */
6991         if (!!(data & NETIF_F_LRO) !=
6992              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6993                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6994                 switch (adapter->hw.mac.type) {
6995                 case ixgbe_mac_X540:
6996                 case ixgbe_mac_82599EB:
6997                         need_reset = true;
6998                         break;
6999                 default:
7000                         break;
7001                 }
7002         }
7003
7004         /*
7005          * Check if Flow Director n-tuple support was enabled or disabled.  If
7006          * the state changed, we need to reset.
7007          */
7008         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7009                 /* turn off ATR, enable perfect filters and reset */
7010                 if (data & NETIF_F_NTUPLE) {
7011                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7012                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7013                         need_reset = true;
7014                 }
7015         } else if (!(data & NETIF_F_NTUPLE)) {
7016                 /* turn off Flow Director, set ATR and reset */
7017                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7018                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7019                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7020                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7021                 need_reset = true;
7022         }
7023
7024         if (need_reset)
7025                 ixgbe_do_reset(netdev);
7026
7027         return 0;
7028
7029 }
7030
7031 static const struct net_device_ops ixgbe_netdev_ops = {
7032         .ndo_open               = ixgbe_open,
7033         .ndo_stop               = ixgbe_close,
7034         .ndo_start_xmit         = ixgbe_xmit_frame,
7035         .ndo_select_queue       = ixgbe_select_queue,
7036         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7037         .ndo_validate_addr      = eth_validate_addr,
7038         .ndo_set_mac_address    = ixgbe_set_mac,
7039         .ndo_change_mtu         = ixgbe_change_mtu,
7040         .ndo_tx_timeout         = ixgbe_tx_timeout,
7041         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7042         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7043         .ndo_do_ioctl           = ixgbe_ioctl,
7044         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7045         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7046         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7047         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7048         .ndo_get_stats64        = ixgbe_get_stats64,
7049         .ndo_setup_tc           = ixgbe_setup_tc,
7050 #ifdef CONFIG_NET_POLL_CONTROLLER
7051         .ndo_poll_controller    = ixgbe_netpoll,
7052 #endif
7053 #ifdef IXGBE_FCOE
7054         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7055         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7056         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7057         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7058         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7059         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7060 #endif /* IXGBE_FCOE */
7061         .ndo_set_features = ixgbe_set_features,
7062         .ndo_fix_features = ixgbe_fix_features,
7063 };
7064
7065 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7066                            const struct ixgbe_info *ii)
7067 {
7068 #ifdef CONFIG_PCI_IOV
7069         struct ixgbe_hw *hw = &adapter->hw;
7070         int err;
7071         int num_vf_macvlans, i;
7072         struct vf_macvlans *mv_list;
7073
7074         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7075                 return;
7076
7077         /* The 82599 supports up to 64 VFs per physical function
7078          * but this implementation limits allocation to 63 so that
7079          * basic networking resources are still available to the
7080          * physical function
7081          */
7082         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7083         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7084         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7085         if (err) {
7086                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7087                 goto err_novfs;
7088         }
7089
7090         num_vf_macvlans = hw->mac.num_rar_entries -
7091                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7092
7093         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7094                                              sizeof(struct vf_macvlans),
7095                                              GFP_KERNEL);
7096         if (mv_list) {
7097                 /* Initialize list of VF macvlans */
7098                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7099                 for (i = 0; i < num_vf_macvlans; i++) {
7100                         mv_list->vf = -1;
7101                         mv_list->free = true;
7102                         mv_list->rar_entry = hw->mac.num_rar_entries -
7103                                 (i + adapter->num_vfs + 1);
7104                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7105                         mv_list++;
7106                 }
7107         }
7108
7109         /* If call to enable VFs succeeded then allocate memory
7110          * for per VF control structures.
7111          */
7112         adapter->vfinfo =
7113                 kcalloc(adapter->num_vfs,
7114                         sizeof(struct vf_data_storage), GFP_KERNEL);
7115         if (adapter->vfinfo) {
7116                 /* Now that we're sure SR-IOV is enabled
7117                  * and memory allocated set up the mailbox parameters
7118                  */
7119                 ixgbe_init_mbx_params_pf(hw);
7120                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7121                        sizeof(hw->mbx.ops));
7122
7123                 /* Disable RSC when in SR-IOV mode */
7124                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7125                                      IXGBE_FLAG2_RSC_ENABLED);
7126                 return;
7127         }
7128
7129         /* Oh oh */
7130         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7131               "SRIOV disabled\n");
7132         pci_disable_sriov(adapter->pdev);
7133
7134 err_novfs:
7135         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7136         adapter->num_vfs = 0;
7137 #endif /* CONFIG_PCI_IOV */
7138 }
7139
7140 /**
7141  * ixgbe_probe - Device Initialization Routine
7142  * @pdev: PCI device information struct
7143  * @ent: entry in ixgbe_pci_tbl
7144  *
7145  * Returns 0 on success, negative on failure
7146  *
7147  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7148  * The OS initialization, configuring of the adapter private structure,
7149  * and a hardware reset occur.
7150  **/
7151 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7152                                  const struct pci_device_id *ent)
7153 {
7154         struct net_device *netdev;
7155         struct ixgbe_adapter *adapter = NULL;
7156         struct ixgbe_hw *hw;
7157         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7158         static int cards_found;
7159         int i, err, pci_using_dac;
7160         u8 part_str[IXGBE_PBANUM_LENGTH];
7161         unsigned int indices = num_possible_cpus();
7162 #ifdef IXGBE_FCOE
7163         u16 device_caps;
7164 #endif
7165         u32 eec;
7166
7167         /* Catch broken hardware that put the wrong VF device ID in
7168          * the PCIe SR-IOV capability.
7169          */
7170         if (pdev->is_virtfn) {
7171                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7172                      pci_name(pdev), pdev->vendor, pdev->device);
7173                 return -EINVAL;
7174         }
7175
7176         err = pci_enable_device_mem(pdev);
7177         if (err)
7178                 return err;
7179
7180         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7181             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7182                 pci_using_dac = 1;
7183         } else {
7184                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7185                 if (err) {
7186                         err = dma_set_coherent_mask(&pdev->dev,
7187                                                     DMA_BIT_MASK(32));
7188                         if (err) {
7189                                 dev_err(&pdev->dev,
7190                                         "No usable DMA configuration, aborting\n");
7191                                 goto err_dma;
7192                         }
7193                 }
7194                 pci_using_dac = 0;
7195         }
7196
7197         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7198                                            IORESOURCE_MEM), ixgbe_driver_name);
7199         if (err) {
7200                 dev_err(&pdev->dev,
7201                         "pci_request_selected_regions failed 0x%x\n", err);
7202                 goto err_pci_reg;
7203         }
7204
7205         pci_enable_pcie_error_reporting(pdev);
7206
7207         pci_set_master(pdev);
7208         pci_save_state(pdev);
7209
7210 #ifdef CONFIG_IXGBE_DCB
7211         indices *= MAX_TRAFFIC_CLASS;
7212 #endif
7213
7214         if (ii->mac == ixgbe_mac_82598EB)
7215                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7216         else
7217                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7218
7219 #ifdef IXGBE_FCOE
7220         indices += min_t(unsigned int, num_possible_cpus(),
7221                          IXGBE_MAX_FCOE_INDICES);
7222 #endif
7223         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7224         if (!netdev) {
7225                 err = -ENOMEM;
7226                 goto err_alloc_etherdev;
7227         }
7228
7229         SET_NETDEV_DEV(netdev, &pdev->dev);
7230
7231         adapter = netdev_priv(netdev);
7232         pci_set_drvdata(pdev, adapter);
7233
7234         adapter->netdev = netdev;
7235         adapter->pdev = pdev;
7236         hw = &adapter->hw;
7237         hw->back = adapter;
7238         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7239
7240         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7241                               pci_resource_len(pdev, 0));
7242         if (!hw->hw_addr) {
7243                 err = -EIO;
7244                 goto err_ioremap;
7245         }
7246
7247         for (i = 1; i <= 5; i++) {
7248                 if (pci_resource_len(pdev, i) == 0)
7249                         continue;
7250         }
7251
7252         netdev->netdev_ops = &ixgbe_netdev_ops;
7253         ixgbe_set_ethtool_ops(netdev);
7254         netdev->watchdog_timeo = 5 * HZ;
7255         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7256
7257         adapter->bd_number = cards_found;
7258
7259         /* Setup hw api */
7260         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7261         hw->mac.type  = ii->mac;
7262
7263         /* EEPROM */
7264         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7265         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7266         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7267         if (!(eec & (1 << 8)))
7268                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7269
7270         /* PHY */
7271         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7272         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7273         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7274         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7275         hw->phy.mdio.mmds = 0;
7276         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7277         hw->phy.mdio.dev = netdev;
7278         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7279         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7280
7281         ii->get_invariants(hw);
7282
7283         /* setup the private structure */
7284         err = ixgbe_sw_init(adapter);
7285         if (err)
7286                 goto err_sw_init;
7287
7288         /* Make it possible the adapter to be woken up via WOL */
7289         switch (adapter->hw.mac.type) {
7290         case ixgbe_mac_82599EB:
7291         case ixgbe_mac_X540:
7292                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7293                 break;
7294         default:
7295                 break;
7296         }
7297
7298         /*
7299          * If there is a fan on this device and it has failed log the
7300          * failure.
7301          */
7302         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7303                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7304                 if (esdp & IXGBE_ESDP_SDP1)
7305                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7306         }
7307
7308         /* reset_hw fills in the perm_addr as well */
7309         hw->phy.reset_if_overtemp = true;
7310         err = hw->mac.ops.reset_hw(hw);
7311         hw->phy.reset_if_overtemp = false;
7312         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7313             hw->mac.type == ixgbe_mac_82598EB) {
7314                 err = 0;
7315         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7316                 e_dev_err("failed to load because an unsupported SFP+ "
7317                           "module type was detected.\n");
7318                 e_dev_err("Reload the driver after installing a supported "
7319                           "module.\n");
7320                 goto err_sw_init;
7321         } else if (err) {
7322                 e_dev_err("HW Init failed: %d\n", err);
7323                 goto err_sw_init;
7324         }
7325
7326         ixgbe_probe_vf(adapter, ii);
7327
7328         netdev->features = NETIF_F_SG |
7329                            NETIF_F_IP_CSUM |
7330                            NETIF_F_IPV6_CSUM |
7331                            NETIF_F_HW_VLAN_TX |
7332                            NETIF_F_HW_VLAN_RX |
7333                            NETIF_F_HW_VLAN_FILTER |
7334                            NETIF_F_TSO |
7335                            NETIF_F_TSO6 |
7336                            NETIF_F_RXHASH |
7337                            NETIF_F_RXCSUM;
7338
7339         netdev->hw_features = netdev->features;
7340
7341         switch (adapter->hw.mac.type) {
7342         case ixgbe_mac_82599EB:
7343         case ixgbe_mac_X540:
7344                 netdev->features |= NETIF_F_SCTP_CSUM;
7345                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7346                                        NETIF_F_NTUPLE;
7347                 break;
7348         default:
7349                 break;
7350         }
7351
7352         netdev->vlan_features |= NETIF_F_TSO;
7353         netdev->vlan_features |= NETIF_F_TSO6;
7354         netdev->vlan_features |= NETIF_F_IP_CSUM;
7355         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7356         netdev->vlan_features |= NETIF_F_SG;
7357
7358         netdev->priv_flags |= IFF_UNICAST_FLT;
7359
7360         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7361                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7362                                     IXGBE_FLAG_DCB_ENABLED);
7363
7364 #ifdef CONFIG_IXGBE_DCB
7365         netdev->dcbnl_ops = &dcbnl_ops;
7366 #endif
7367
7368 #ifdef IXGBE_FCOE
7369         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7370                 if (hw->mac.ops.get_device_caps) {
7371                         hw->mac.ops.get_device_caps(hw, &device_caps);
7372                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7373                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7374                 }
7375         }
7376         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7377                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7378                 netdev->vlan_features |= NETIF_F_FSO;
7379                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7380         }
7381 #endif /* IXGBE_FCOE */
7382         if (pci_using_dac) {
7383                 netdev->features |= NETIF_F_HIGHDMA;
7384                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7385         }
7386
7387         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7388                 netdev->hw_features |= NETIF_F_LRO;
7389         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7390                 netdev->features |= NETIF_F_LRO;
7391
7392         /* make sure the EEPROM is good */
7393         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7394                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7395                 err = -EIO;
7396                 goto err_eeprom;
7397         }
7398
7399         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7400         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7401
7402         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7403                 e_dev_err("invalid MAC address\n");
7404                 err = -EIO;
7405                 goto err_eeprom;
7406         }
7407
7408         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7409         if (hw->mac.ops.disable_tx_laser &&
7410             ((hw->phy.multispeed_fiber) ||
7411              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7412               (hw->mac.type == ixgbe_mac_82599EB))))
7413                 hw->mac.ops.disable_tx_laser(hw);
7414
7415         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7416                     (unsigned long) adapter);
7417
7418         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7419         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7420
7421         err = ixgbe_init_interrupt_scheme(adapter);
7422         if (err)
7423                 goto err_sw_init;
7424
7425         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7426                 netdev->hw_features &= ~NETIF_F_RXHASH;
7427                 netdev->features &= ~NETIF_F_RXHASH;
7428         }
7429
7430         switch (pdev->device) {
7431         case IXGBE_DEV_ID_82599_SFP:
7432                 /* Only this subdevice supports WOL */
7433                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7434                         adapter->wol = IXGBE_WUFC_MAG;
7435                 break;
7436         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7437                 /* All except this subdevice support WOL */
7438                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7439                         adapter->wol = IXGBE_WUFC_MAG;
7440                 break;
7441         case IXGBE_DEV_ID_82599_KX4:
7442                 adapter->wol = IXGBE_WUFC_MAG;
7443                 break;
7444         default:
7445                 adapter->wol = 0;
7446                 break;
7447         }
7448         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7449
7450         /* pick up the PCI bus settings for reporting later */
7451         hw->mac.ops.get_bus_info(hw);
7452
7453         /* print bus type/speed/width info */
7454         e_dev_info("(PCI Express:%s:%s) %pM\n",
7455                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7456                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7457                     "Unknown"),
7458                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7459                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7460                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7461                     "Unknown"),
7462                    netdev->dev_addr);
7463
7464         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7465         if (err)
7466                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7467         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7468                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7469                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7470                            part_str);
7471         else
7472                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7473                            hw->mac.type, hw->phy.type, part_str);
7474
7475         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7476                 e_dev_warn("PCI-Express bandwidth available for this card is "
7477                            "not sufficient for optimal performance.\n");
7478                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7479                            "is required.\n");
7480         }
7481
7482         /* save off EEPROM version number */
7483         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7484
7485         /* reset the hardware with the new settings */
7486         err = hw->mac.ops.start_hw(hw);
7487
7488         if (err == IXGBE_ERR_EEPROM_VERSION) {
7489                 /* We are running on a pre-production device, log a warning */
7490                 e_dev_warn("This device is a pre-production adapter/LOM. "
7491                            "Please be aware there may be issues associated "
7492                            "with your hardware.  If you are experiencing "
7493                            "problems please contact your Intel or hardware "
7494                            "representative who provided you with this "
7495                            "hardware.\n");
7496         }
7497         strcpy(netdev->name, "eth%d");
7498         err = register_netdev(netdev);
7499         if (err)
7500                 goto err_register;
7501
7502         /* carrier off reporting is important to ethtool even BEFORE open */
7503         netif_carrier_off(netdev);
7504
7505 #ifdef CONFIG_IXGBE_DCA
7506         if (dca_add_requester(&pdev->dev) == 0) {
7507                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7508                 ixgbe_setup_dca(adapter);
7509         }
7510 #endif
7511         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7512                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7513                 for (i = 0; i < adapter->num_vfs; i++)
7514                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7515         }
7516
7517         /* Inform firmware of driver version */
7518         if (hw->mac.ops.set_fw_drv_ver)
7519                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7520                                            FW_CEM_UNUSED_VER);
7521
7522         /* add san mac addr to netdev */
7523         ixgbe_add_sanmac_netdev(netdev);
7524
7525         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7526         cards_found++;
7527         return 0;
7528
7529 err_register:
7530         ixgbe_release_hw_control(adapter);
7531         ixgbe_clear_interrupt_scheme(adapter);
7532 err_sw_init:
7533 err_eeprom:
7534         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7535                 ixgbe_disable_sriov(adapter);
7536         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7537         iounmap(hw->hw_addr);
7538 err_ioremap:
7539         free_netdev(netdev);
7540 err_alloc_etherdev:
7541         pci_release_selected_regions(pdev,
7542                                      pci_select_bars(pdev, IORESOURCE_MEM));
7543 err_pci_reg:
7544 err_dma:
7545         pci_disable_device(pdev);
7546         return err;
7547 }
7548
7549 /**
7550  * ixgbe_remove - Device Removal Routine
7551  * @pdev: PCI device information struct
7552  *
7553  * ixgbe_remove is called by the PCI subsystem to alert the driver
7554  * that it should release a PCI device.  The could be caused by a
7555  * Hot-Plug event, or because the driver is going to be removed from
7556  * memory.
7557  **/
7558 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7559 {
7560         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7561         struct net_device *netdev = adapter->netdev;
7562
7563         set_bit(__IXGBE_DOWN, &adapter->state);
7564         cancel_work_sync(&adapter->service_task);
7565
7566 #ifdef CONFIG_IXGBE_DCA
7567         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7568                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7569                 dca_remove_requester(&pdev->dev);
7570                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7571         }
7572
7573 #endif
7574 #ifdef IXGBE_FCOE
7575         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7576                 ixgbe_cleanup_fcoe(adapter);
7577
7578 #endif /* IXGBE_FCOE */
7579
7580         /* remove the added san mac */
7581         ixgbe_del_sanmac_netdev(netdev);
7582
7583         if (netdev->reg_state == NETREG_REGISTERED)
7584                 unregister_netdev(netdev);
7585
7586         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7587                 ixgbe_disable_sriov(adapter);
7588
7589         ixgbe_clear_interrupt_scheme(adapter);
7590
7591         ixgbe_release_hw_control(adapter);
7592
7593         iounmap(adapter->hw.hw_addr);
7594         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7595                                      IORESOURCE_MEM));
7596
7597         e_dev_info("complete\n");
7598
7599         free_netdev(netdev);
7600
7601         pci_disable_pcie_error_reporting(pdev);
7602
7603         pci_disable_device(pdev);
7604 }
7605
7606 /**
7607  * ixgbe_io_error_detected - called when PCI error is detected
7608  * @pdev: Pointer to PCI device
7609  * @state: The current pci connection state
7610  *
7611  * This function is called after a PCI bus error affecting
7612  * this device has been detected.
7613  */
7614 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7615                                                 pci_channel_state_t state)
7616 {
7617         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7618         struct net_device *netdev = adapter->netdev;
7619
7620         netif_device_detach(netdev);
7621
7622         if (state == pci_channel_io_perm_failure)
7623                 return PCI_ERS_RESULT_DISCONNECT;
7624
7625         if (netif_running(netdev))
7626                 ixgbe_down(adapter);
7627         pci_disable_device(pdev);
7628
7629         /* Request a slot reset. */
7630         return PCI_ERS_RESULT_NEED_RESET;
7631 }
7632
7633 /**
7634  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7635  * @pdev: Pointer to PCI device
7636  *
7637  * Restart the card from scratch, as if from a cold-boot.
7638  */
7639 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7640 {
7641         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7642         pci_ers_result_t result;
7643         int err;
7644
7645         if (pci_enable_device_mem(pdev)) {
7646                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7647                 result = PCI_ERS_RESULT_DISCONNECT;
7648         } else {
7649                 pci_set_master(pdev);
7650                 pci_restore_state(pdev);
7651                 pci_save_state(pdev);
7652
7653                 pci_wake_from_d3(pdev, false);
7654
7655                 ixgbe_reset(adapter);
7656                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7657                 result = PCI_ERS_RESULT_RECOVERED;
7658         }
7659
7660         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7661         if (err) {
7662                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7663                           "failed 0x%0x\n", err);
7664                 /* non-fatal, continue */
7665         }
7666
7667         return result;
7668 }
7669
7670 /**
7671  * ixgbe_io_resume - called when traffic can start flowing again.
7672  * @pdev: Pointer to PCI device
7673  *
7674  * This callback is called when the error recovery driver tells us that
7675  * its OK to resume normal operation.
7676  */
7677 static void ixgbe_io_resume(struct pci_dev *pdev)
7678 {
7679         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7680         struct net_device *netdev = adapter->netdev;
7681
7682         if (netif_running(netdev)) {
7683                 if (ixgbe_up(adapter)) {
7684                         e_info(probe, "ixgbe_up failed after reset\n");
7685                         return;
7686                 }
7687         }
7688
7689         netif_device_attach(netdev);
7690 }
7691
7692 static struct pci_error_handlers ixgbe_err_handler = {
7693         .error_detected = ixgbe_io_error_detected,
7694         .slot_reset = ixgbe_io_slot_reset,
7695         .resume = ixgbe_io_resume,
7696 };
7697
7698 static struct pci_driver ixgbe_driver = {
7699         .name     = ixgbe_driver_name,
7700         .id_table = ixgbe_pci_tbl,
7701         .probe    = ixgbe_probe,
7702         .remove   = __devexit_p(ixgbe_remove),
7703 #ifdef CONFIG_PM
7704         .suspend  = ixgbe_suspend,
7705         .resume   = ixgbe_resume,
7706 #endif
7707         .shutdown = ixgbe_shutdown,
7708         .err_handler = &ixgbe_err_handler
7709 };
7710
7711 /**
7712  * ixgbe_init_module - Driver Registration Routine
7713  *
7714  * ixgbe_init_module is the first routine called when the driver is
7715  * loaded. All it does is register with the PCI subsystem.
7716  **/
7717 static int __init ixgbe_init_module(void)
7718 {
7719         int ret;
7720         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7721         pr_info("%s\n", ixgbe_copyright);
7722
7723 #ifdef CONFIG_IXGBE_DCA
7724         dca_register_notify(&dca_notifier);
7725 #endif
7726
7727         ret = pci_register_driver(&ixgbe_driver);
7728         return ret;
7729 }
7730
7731 module_init(ixgbe_init_module);
7732
7733 /**
7734  * ixgbe_exit_module - Driver Exit Cleanup Routine
7735  *
7736  * ixgbe_exit_module is called just before the driver is removed
7737  * from memory.
7738  **/
7739 static void __exit ixgbe_exit_module(void)
7740 {
7741 #ifdef CONFIG_IXGBE_DCA
7742         dca_unregister_notify(&dca_notifier);
7743 #endif
7744         pci_unregister_driver(&ixgbe_driver);
7745         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7746 }
7747
7748 #ifdef CONFIG_IXGBE_DCA
7749 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7750                             void *p)
7751 {
7752         int ret_val;
7753
7754         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7755                                          __ixgbe_notify_dca);
7756
7757         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7758 }
7759
7760 #endif /* CONFIG_IXGBE_DCA */
7761
7762 module_exit(ixgbe_exit_module);
7763
7764 /* ixgbe_main.c */