drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  99          board_82598 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 101          board_82598 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 103          board_82598 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 105          board_82598 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 121          board_82599 },
 122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 123          board_82599 },
 124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 125          board_82599 },
 126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 127          board_82599 },
 128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 129          board_X540 },
 130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 131          board_82599 },
 132         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 133          board_82599 },
 134
 135         /* required last entry */
 136         {0, }
 137 };
 138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 139
 140 #ifdef CONFIG_IXGBE_DCA
 141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 142                             void *p);
 143 static struct notifier_block dca_notifier = {
 144         .notifier_call = ixgbe_notify_dca,
 145         .next          = NULL,
 146         .priority      = 0
 147 };
 148 #endif
 149
 150 #ifdef CONFIG_PCI_IOV
 151 static unsigned int max_vfs;
 152 module_param(max_vfs, uint, 0);
 153 MODULE_PARM_DESC(max_vfs,
 154                  "Maximum number of virtual functions to allocate per physical function");
 155 #endif /* CONFIG_PCI_IOV */
 156
 157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_VERSION);
 161
 162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 163
 164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 165 {
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         u32 gcr;
 168         u32 gpie;
 169         u32 vmdctl;
 170
 171 #ifdef CONFIG_PCI_IOV
 172         /* disable iov and allow time for transactions to clear */
 173         pci_disable_sriov(adapter->pdev);
 174 #endif
 175
 176         /* turn off device IOV mode */
 177         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 178         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 179         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 180         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 181         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 182         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 183
 184         /* set default pool back to 0 */
 185         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 186         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 187         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 188         IXGBE_WRITE_FLUSH(hw);
 189
 190         /* take a breather then clean up driver data */
 191         msleep(100);
 192
 193         kfree(adapter->vfinfo);
 194         adapter->vfinfo = NULL;
 195
 196         adapter->num_vfs = 0;
 197         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 198 }
 199
 200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 201 {
 202         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 203             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 204                 schedule_work(&adapter->service_task);
 205 }
 206
 207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 208 {
 209         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 210
 211         /* flush memory to make sure state is correct before next watchog */
 212         smp_mb__before_clear_bit();
 213         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 214 }
 215
 216 struct ixgbe_reg_info {
 217         u32 ofs;
 218         char *name;
 219 };
 220
 221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 222
 223         /* General Registers */
 224         {IXGBE_CTRL, "CTRL"},
 225         {IXGBE_STATUS, "STATUS"},
 226         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 227
 228         /* Interrupt Registers */
 229         {IXGBE_EICR, "EICR"},
 230
 231         /* RX Registers */
 232         {IXGBE_SRRCTL(0), "SRRCTL"},
 233         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 234         {IXGBE_RDLEN(0), "RDLEN"},
 235         {IXGBE_RDH(0), "RDH"},
 236         {IXGBE_RDT(0), "RDT"},
 237         {IXGBE_RXDCTL(0), "RXDCTL"},
 238         {IXGBE_RDBAL(0), "RDBAL"},
 239         {IXGBE_RDBAH(0), "RDBAH"},
 240
 241         /* TX Registers */
 242         {IXGBE_TDBAL(0), "TDBAL"},
 243         {IXGBE_TDBAH(0), "TDBAH"},
 244         {IXGBE_TDLEN(0), "TDLEN"},
 245         {IXGBE_TDH(0), "TDH"},
 246         {IXGBE_TDT(0), "TDT"},
 247         {IXGBE_TXDCTL(0), "TXDCTL"},
 248
 249         /* List Terminator */
 250         {}
 251 };
 252
 253
 254 /*
 255  * ixgbe_regdump - register printout routine
 256  */
 257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 258 {
 259         int i = 0, j = 0;
 260         char rname[16];
 261         u32 regs[64];
 262
 263         switch (reginfo->ofs) {
 264         case IXGBE_SRRCTL(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 267                 break;
 268         case IXGBE_DCA_RXCTRL(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 271                 break;
 272         case IXGBE_RDLEN(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 275                 break;
 276         case IXGBE_RDH(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 279                 break;
 280         case IXGBE_RDT(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 283                 break;
 284         case IXGBE_RXDCTL(0):
 285                 for (i = 0; i < 64; i++)
 286                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 287                 break;
 288         case IXGBE_RDBAL(0):
 289                 for (i = 0; i < 64; i++)
 290                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 291                 break;
 292         case IXGBE_RDBAH(0):
 293                 for (i = 0; i < 64; i++)
 294                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 295                 break;
 296         case IXGBE_TDBAL(0):
 297                 for (i = 0; i < 64; i++)
 298                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 299                 break;
 300         case IXGBE_TDBAH(0):
 301                 for (i = 0; i < 64; i++)
 302                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 303                 break;
 304         case IXGBE_TDLEN(0):
 305                 for (i = 0; i < 64; i++)
 306                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 307                 break;
 308         case IXGBE_TDH(0):
 309                 for (i = 0; i < 64; i++)
 310                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 311                 break;
 312         case IXGBE_TDT(0):
 313                 for (i = 0; i < 64; i++)
 314                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 315                 break;
 316         case IXGBE_TXDCTL(0):
 317                 for (i = 0; i < 64; i++)
 318                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 319                 break;
 320         default:
 321                 pr_info("%-15s %08x\n", reginfo->name,
 322                         IXGBE_READ_REG(hw, reginfo->ofs));
 323                 return;
 324         }
 325
 326         for (i = 0; i < 8; i++) {
 327                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 328                 pr_err("%-15s", rname);
 329                 for (j = 0; j < 8; j++)
 330                         pr_cont(" %08x", regs[i*8+j]);
 331                 pr_cont("\n");
 332         }
 333
 334 }
 335
 336 /*
 337  * ixgbe_dump - Print registers, tx-rings and rx-rings
 338  */
 339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 340 {
 341         struct net_device *netdev = adapter->netdev;
 342         struct ixgbe_hw *hw = &adapter->hw;
 343         struct ixgbe_reg_info *reginfo;
 344         int n = 0;
 345         struct ixgbe_ring *tx_ring;
 346         struct ixgbe_tx_buffer *tx_buffer_info;
 347         union ixgbe_adv_tx_desc *tx_desc;
 348         struct my_u0 { u64 a; u64 b; } *u0;
 349         struct ixgbe_ring *rx_ring;
 350         union ixgbe_adv_rx_desc *rx_desc;
 351         struct ixgbe_rx_buffer *rx_buffer_info;
 352         u32 staterr;
 353         int i = 0;
 354
 355         if (!netif_msg_hw(adapter))
 356                 return;
 357
 358         /* Print netdevice Info */
 359         if (netdev) {
 360                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 361                 pr_info("Device Name     state            "
 362                         "trans_start      last_rx\n");
 363                 pr_info("%-15s %016lX %016lX %016lX\n",
 364                         netdev->name,
 365                         netdev->state,
 366                         netdev->trans_start,
 367                         netdev->last_rx);
 368         }
 369
 370         /* Print Registers */
 371         dev_info(&adapter->pdev->dev, "Register Dump\n");
 372         pr_info(" Register Name   Value\n");
 373         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 374              reginfo->name; reginfo++) {
 375                 ixgbe_regdump(hw, reginfo);
 376         }
 377
 378         /* Print TX Ring Summary */
 379         if (!netdev || !netif_running(netdev))
 380                 goto exit;
 381
 382         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 383         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 tx_buffer_info =
 387                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 388                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 389                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 390                            (u64)tx_buffer_info->dma,
 391                            tx_buffer_info->length,
 392                            tx_buffer_info->next_to_watch,
 393                            (u64)tx_buffer_info->time_stamp);
 394         }
 395
 396         /* Print TX Rings */
 397         if (!netif_msg_tx_done(adapter))
 398                 goto rx_ring_summary;
 399
 400         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 401
 402         /* Transmit Descriptor Formats
 403          *
 404          * Advanced Transmit Descriptor
 405          *   +--------------------------------------------------------------+
 406          * 0 |         Buffer Address [63:0]                                |
 407          *   +--------------------------------------------------------------+
 408          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 409          *   +--------------------------------------------------------------+
 410          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 411          */
 412
 413         for (n = 0; n < adapter->num_tx_queues; n++) {
 414                 tx_ring = adapter->tx_ring[n];
 415                 pr_info("------------------------------------\n");
 416                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 417                 pr_info("------------------------------------\n");
 418                 pr_info("T [desc]     [address 63:0  ] "
 419                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 420                         "leng  ntw timestamp        bi->skb\n");
 421
 422                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 423                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 424                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 425                         u0 = (struct my_u0 *)tx_desc;
 426                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 427                                 " %04X  %p %016llX %p", i,
 428                                 le64_to_cpu(u0->a),
 429                                 le64_to_cpu(u0->b),
 430                                 (u64)tx_buffer_info->dma,
 431                                 tx_buffer_info->length,
 432                                 tx_buffer_info->next_to_watch,
 433                                 (u64)tx_buffer_info->time_stamp,
 434                                 tx_buffer_info->skb);
 435                         if (i == tx_ring->next_to_use &&
 436                                 i == tx_ring->next_to_clean)
 437                                 pr_cont(" NTC/U\n");
 438                         else if (i == tx_ring->next_to_use)
 439                                 pr_cont(" NTU\n");
 440                         else if (i == tx_ring->next_to_clean)
 441                                 pr_cont(" NTC\n");
 442                         else
 443                                 pr_cont("\n");
 444
 445                         if (netif_msg_pktdata(adapter) &&
 446                                 tx_buffer_info->dma != 0)
 447                                 print_hex_dump(KERN_INFO, "",
 448                                         DUMP_PREFIX_ADDRESS, 16, 1,
 449                                         phys_to_virt(tx_buffer_info->dma),
 450                                         tx_buffer_info->length, true);
 451                 }
 452         }
 453
 454         /* Print RX Rings Summary */
 455 rx_ring_summary:
 456         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 457         pr_info("Queue [NTU] [NTC]\n");
 458         for (n = 0; n < adapter->num_rx_queues; n++) {
 459                 rx_ring = adapter->rx_ring[n];
 460                 pr_info("%5d %5X %5X\n",
 461                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 462         }
 463
 464         /* Print RX Rings */
 465         if (!netif_msg_rx_status(adapter))
 466                 goto exit;
 467
 468         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 469
 470         /* Advanced Receive Descriptor (Read) Format
 471          *    63                                           1        0
 472          *    +-----------------------------------------------------+
 473          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 474          *    +----------------------------------------------+------+
 475          *  8 |       Header Buffer Address [63:1]           |  DD  |
 476          *    +-----------------------------------------------------+
 477          *
 478          *
 479          * Advanced Receive Descriptor (Write-Back) Format
 480          *
 481          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 482          *   +------------------------------------------------------+
 483          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 484          *   | Checksum   Ident  |   |           |    | Type | Type |
 485          *   +------------------------------------------------------+
 486          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 487          *   +------------------------------------------------------+
 488          *   63       48 47    32 31            20 19               0
 489          */
 490         for (n = 0; n < adapter->num_rx_queues; n++) {
 491                 rx_ring = adapter->rx_ring[n];
 492                 pr_info("------------------------------------\n");
 493                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 494                 pr_info("------------------------------------\n");
 495                 pr_info("R  [desc]      [ PktBuf     A0] "
 496                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 497                         "<-- Adv Rx Read format\n");
 498                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 499                         "[vl er S cks ln] ---------------- [bi->skb] "
 500                         "<-- Adv Rx Write-Back format\n");
 501
 502                 for (i = 0; i < rx_ring->count; i++) {
 503                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 504                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 505                         u0 = (struct my_u0 *)rx_desc;
 506                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 507                         if (staterr & IXGBE_RXD_STAT_DD) {
 508                                 /* Descriptor Done */
 509                                 pr_info("RWB[0x%03X]     %016llX "
 510                                         "%016llX ---------------- %p", i,
 511                                         le64_to_cpu(u0->a),
 512                                         le64_to_cpu(u0->b),
 513                                         rx_buffer_info->skb);
 514                         } else {
 515                                 pr_info("R  [0x%03X]     %016llX "
 516                                         "%016llX %016llX %p", i,
 517                                         le64_to_cpu(u0->a),
 518                                         le64_to_cpu(u0->b),
 519                                         (u64)rx_buffer_info->dma,
 520                                         rx_buffer_info->skb);
 521
 522                                 if (netif_msg_pktdata(adapter)) {
 523                                         print_hex_dump(KERN_INFO, "",
 524                                            DUMP_PREFIX_ADDRESS, 16, 1,
 525                                            phys_to_virt(rx_buffer_info->dma),
 526                                            rx_ring->rx_buf_len, true);
 527
 528                                         if (rx_ring->rx_buf_len
 529                                                 < IXGBE_RXBUFFER_2048)
 530                                                 print_hex_dump(KERN_INFO, "",
 531                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 532                                                   phys_to_virt(
 533                                                     rx_buffer_info->page_dma +
 534                                                     rx_buffer_info->page_offset
 535                                                   ),
 536                                                   PAGE_SIZE/2, true);
 537                                 }
 538                         }
 539
 540                         if (i == rx_ring->next_to_use)
 541                                 pr_cont(" NTU\n");
 542                         else if (i == rx_ring->next_to_clean)
 543                                 pr_cont(" NTC\n");
 544                         else
 545                                 pr_cont("\n");
 546
 547                 }
 548         }
 549
 550 exit:
 551         return;
 552 }
 553
 554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 555 {
 556         u32 ctrl_ext;
 557
 558         /* Let firmware take over control of h/w */
 559         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 560         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 561                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 562 }
 563
 564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 565 {
 566         u32 ctrl_ext;
 567
 568         /* Let firmware know the driver has taken over */
 569         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 570         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 571                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 572 }
 573
 574 /*
 575  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 576  * @adapter: pointer to adapter struct
 577  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 578  * @queue: queue to map the corresponding interrupt to
 579  * @msix_vector: the vector to map to the corresponding queue
 580  *
 581  */
 582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 583                            u8 queue, u8 msix_vector)
 584 {
 585         u32 ivar, index;
 586         struct ixgbe_hw *hw = &adapter->hw;
 587         switch (hw->mac.type) {
 588         case ixgbe_mac_82598EB:
 589                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 590                 if (direction == -1)
 591                         direction = 0;
 592                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 593                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 594                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 595                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 596                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 597                 break;
 598         case ixgbe_mac_82599EB:
 599         case ixgbe_mac_X540:
 600                 if (direction == -1) {
 601                         /* other causes */
 602                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 603                         index = ((queue & 1) * 8);
 604                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 605                         ivar &= ~(0xFF << index);
 606                         ivar |= (msix_vector << index);
 607                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 608                         break;
 609                 } else {
 610                         /* tx or rx causes */
 611                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 612                         index = ((16 * (queue & 1)) + (8 * direction));
 613                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 614                         ivar &= ~(0xFF << index);
 615                         ivar |= (msix_vector << index);
 616                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 617                         break;
 618                 }
 619         default:
 620                 break;
 621         }
 622 }
 623
 624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 625                                           u64 qmask)
 626 {
 627         u32 mask;
 628
 629         switch (adapter->hw.mac.type) {
 630         case ixgbe_mac_82598EB:
 631                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 632                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 633                 break;
 634         case ixgbe_mac_82599EB:
 635         case ixgbe_mac_X540:
 636                 mask = (qmask & 0xFFFFFFFF);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 638                 mask = (qmask >> 32);
 639                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 640                 break;
 641         default:
 642                 break;
 643         }
 644 }
 645
 646 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 647                                            struct ixgbe_tx_buffer *tx_buffer)
 648 {
 649         if (tx_buffer->dma) {
 650                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 651                         dma_unmap_page(ring->dev,
 652                                        tx_buffer->dma,
 653                                        tx_buffer->length,
 654                                        DMA_TO_DEVICE);
 655                 else
 656                         dma_unmap_single(ring->dev,
 657                                          tx_buffer->dma,
 658                                          tx_buffer->length,
 659                                          DMA_TO_DEVICE);
 660         }
 661         tx_buffer->dma = 0;
 662 }
 663
 664 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 665                                       struct ixgbe_tx_buffer *tx_buffer_info)
 666 {
 667         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 668         if (tx_buffer_info->skb)
 669                 dev_kfree_skb_any(tx_buffer_info->skb);
 670         tx_buffer_info->skb = NULL;
 671         /* tx_buffer_info must be completely set up in the transmit path */
 672 }
 673
 674 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 675 {
 676         struct ixgbe_hw *hw = &adapter->hw;
 677         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 678         u32 data = 0;
 679         u32 xoff[8] = {0};
 680         int i;
 681
 682         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 683             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 684                 switch (hw->mac.type) {
 685                 case ixgbe_mac_82598EB:
 686                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 687                         break;
 688                 default:
 689                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 690                 }
 691                 hwstats->lxoffrxc += data;
 692
 693                 /* refill credits (no tx hang) if we received xoff */
 694                 if (!data)
 695                         return;
 696
 697                 for (i = 0; i < adapter->num_tx_queues; i++)
 698                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 699                                   &adapter->tx_ring[i]->state);
 700                 return;
 701         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 702                 return;
 703
 704         /* update stats for each tc, only valid with PFC enabled */
 705         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 706                 switch (hw->mac.type) {
 707                 case ixgbe_mac_82598EB:
 708                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 709                         break;
 710                 default:
 711                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 712                 }
 713                 hwstats->pxoffrxc[i] += xoff[i];
 714         }
 715
 716         /* disarm tx queues that have received xoff frames */
 717         for (i = 0; i < adapter->num_tx_queues; i++) {
 718                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 719                 u8 tc = tx_ring->dcb_tc;
 720
 721                 if (xoff[tc])
 722                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 723         }
 724 }
 725
 726 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 727 {
 728         return ring->tx_stats.completed;
 729 }
 730
 731 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 732 {
 733         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 734         struct ixgbe_hw *hw = &adapter->hw;
 735
 736         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 737         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 738
 739         if (head != tail)
 740                 return (head < tail) ?
 741                         tail - head : (tail + ring->count - head);
 742
 743         return 0;
 744 }
 745
 746 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 747 {
 748         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 749         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 750         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 751         bool ret = false;
 752
 753         clear_check_for_tx_hang(tx_ring);
 754
 755         /*
 756          * Check for a hung queue, but be thorough. This verifies
 757          * that a transmit has been completed since the previous
 758          * check AND there is at least one packet pending. The
 759          * ARMED bit is set to indicate a potential hang. The
 760          * bit is cleared if a pause frame is received to remove
 761          * false hang detection due to PFC or 802.3x frames. By
 762          * requiring this to fail twice we avoid races with
 763          * pfc clearing the ARMED bit and conditions where we
 764          * run the check_tx_hang logic with a transmit completion
 765          * pending but without time to complete it yet.
 766          */
 767         if ((tx_done_old == tx_done) && tx_pending) {
 768                 /* make sure it is true for two checks in a row */
 769                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 770                                        &tx_ring->state);
 771         } else {
 772                 /* update completed stats and continue */
 773                 tx_ring->tx_stats.tx_done_old = tx_done;
 774                 /* reset the countdown */
 775                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 776         }
 777
 778         return ret;
 779 }
 780
 781 /**
 782  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 783  * @adapter: driver private struct
 784  **/
 785 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 786 {
 787
 788         /* Do the reset outside of interrupt context */
 789         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 790                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 791                 ixgbe_service_event_schedule(adapter);
 792         }
 793 }
 794
 795 /**
 796  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 797  * @q_vector: structure containing interrupt and ring information
 798  * @tx_ring: tx ring to clean
 799  **/
 800 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 801                                struct ixgbe_ring *tx_ring)
 802 {
 803         struct ixgbe_adapter *adapter = q_vector->adapter;
 804         struct ixgbe_tx_buffer *tx_buffer;
 805         union ixgbe_adv_tx_desc *tx_desc;
 806         unsigned int total_bytes = 0, total_packets = 0;
 807         unsigned int budget = q_vector->tx.work_limit;
 808         u16 i = tx_ring->next_to_clean;
 809
 810         tx_buffer = &tx_ring->tx_buffer_info[i];
 811         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 812
 813         for (; budget; budget--) {
 814                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 815
 816                 /* if next_to_watch is not set then there is no work pending */
 817                 if (!eop_desc)
 818                         break;
 819
 820                 /* if DD is not set pending work has not been completed */
 821                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 822                         break;
 823
 824                 /* count the packet as being completed */
 825                 tx_ring->tx_stats.completed++;
 826
 827                 /* clear next_to_watch to prevent false hangs */
 828                 tx_buffer->next_to_watch = NULL;
 829
 830                 /* prevent any other reads prior to eop_desc being verified */
 831                 rmb();
 832
 833                 do {
 834                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 835                         tx_desc->wb.status = 0;
 836                         if (likely(tx_desc == eop_desc)) {
 837                                 eop_desc = NULL;
 838                                 dev_kfree_skb_any(tx_buffer->skb);
 839                                 tx_buffer->skb = NULL;
 840
 841                                 total_bytes += tx_buffer->bytecount;
 842                                 total_packets += tx_buffer->gso_segs;
 843                         }
 844
 845                         tx_buffer++;
 846                         tx_desc++;
 847                         i++;
 848                         if (unlikely(i == tx_ring->count)) {
 849                                 i = 0;
 850
 851                                 tx_buffer = tx_ring->tx_buffer_info;
 852                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 853                         }
 854
 855                 } while (eop_desc);
 856         }
 857
 858         tx_ring->next_to_clean = i;
 859         u64_stats_update_begin(&tx_ring->syncp);
 860         tx_ring->stats.bytes += total_bytes;
 861         tx_ring->stats.packets += total_packets;
 862         u64_stats_update_end(&tx_ring->syncp);
 863         q_vector->tx.total_bytes += total_bytes;
 864         q_vector->tx.total_packets += total_packets;
 865
 866         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 867                 /* schedule immediate reset if we believe we hung */
 868                 struct ixgbe_hw *hw = &adapter->hw;
 869                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 870                 e_err(drv, "Detected Tx Unit Hang\n"
 871                         "  Tx Queue             <%d>\n"
 872                         "  TDH, TDT             <%x>, <%x>\n"
 873                         "  next_to_use          <%x>\n"
 874                         "  next_to_clean        <%x>\n"
 875                         "tx_buffer_info[next_to_clean]\n"
 876                         "  time_stamp           <%lx>\n"
 877                         "  jiffies              <%lx>\n",
 878                         tx_ring->queue_index,
 879                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 880                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 881                         tx_ring->next_to_use, i,
 882                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 883
 884                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 885
 886                 e_info(probe,
 887                        "tx hang %d detected on queue %d, resetting adapter\n",
 888                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 889
 890                 /* schedule immediate reset if we believe we hung */
 891                 ixgbe_tx_timeout_reset(adapter);
 892
 893                 /* the adapter is about to reset, no point in enabling stuff */
 894                 return true;
 895         }
 896
 897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 898         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 899                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 900                 /* Make sure that anybody stopping the queue after this
 901                  * sees the new next_to_clean.
 902                  */
 903                 smp_mb();
 904                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 905                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 906                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 907                         ++tx_ring->tx_stats.restart_queue;
 908                 }
 909         }
 910
 911         return !!budget;
 912 }
 913
 914 #ifdef CONFIG_IXGBE_DCA
 915 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 916                                 struct ixgbe_ring *rx_ring,
 917                                 int cpu)
 918 {
 919         struct ixgbe_hw *hw = &adapter->hw;
 920         u32 rxctrl;
 921         u8 reg_idx = rx_ring->reg_idx;
 922
 923         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 924         switch (hw->mac.type) {
 925         case ixgbe_mac_82598EB:
 926                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 927                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 928                 break;
 929         case ixgbe_mac_82599EB:
 930         case ixgbe_mac_X540:
 931                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 932                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 933                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 934                 break;
 935         default:
 936                 break;
 937         }
 938         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 939         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 940         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 941         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 942 }
 943
 944 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 945                                 struct ixgbe_ring *tx_ring,
 946                                 int cpu)
 947 {
 948         struct ixgbe_hw *hw = &adapter->hw;
 949         u32 txctrl;
 950         u8 reg_idx = tx_ring->reg_idx;
 951
 952         switch (hw->mac.type) {
 953         case ixgbe_mac_82598EB:
 954                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 955                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 956                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 957                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 958                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 959                 break;
 960         case ixgbe_mac_82599EB:
 961         case ixgbe_mac_X540:
 962                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 963                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 964                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 965                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 966                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 967                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 968                 break;
 969         default:
 970                 break;
 971         }
 972 }
 973
 974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 975 {
 976         struct ixgbe_adapter *adapter = q_vector->adapter;
 977         struct ixgbe_ring *ring;
 978         int cpu = get_cpu();
 979
 980         if (q_vector->cpu == cpu)
 981                 goto out_no_update;
 982
 983         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 984                 ixgbe_update_tx_dca(adapter, ring, cpu);
 985
 986         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 987                 ixgbe_update_rx_dca(adapter, ring, cpu);
 988
 989         q_vector->cpu = cpu;
 990 out_no_update:
 991         put_cpu();
 992 }
 993
 994 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 995 {
 996         int num_q_vectors;
 997         int i;
 998
 999         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000                 return;
1001
1002         /* always use CB2 mode, difference is masked in the CB driver */
1003         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
1005         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007         else
1008                 num_q_vectors = 1;
1009
1010         for (i = 0; i < num_q_vectors; i++) {
1011                 adapter->q_vector[i]->cpu = -1;
1012                 ixgbe_update_dca(adapter->q_vector[i]);
1013         }
1014 }
1015
1016 static int __ixgbe_notify_dca(struct device *dev, void *data)
1017 {
1018         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1019         unsigned long event = *(unsigned long *)data;
1020
1021         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1022                 return 0;
1023
1024         switch (event) {
1025         case DCA_PROVIDER_ADD:
1026                 /* if we're already enabled, don't do it again */
1027                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028                         break;
1029                 if (dca_add_requester(dev) == 0) {
1030                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1031                         ixgbe_setup_dca(adapter);
1032                         break;
1033                 }
1034                 /* Fall Through since DCA is disabled. */
1035         case DCA_PROVIDER_REMOVE:
1036                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037                         dca_remove_requester(dev);
1038                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040                 }
1041                 break;
1042         }
1043
1044         return 0;
1045 }
1046 #endif /* CONFIG_IXGBE_DCA */
1047
1048 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1049                                  struct sk_buff *skb)
1050 {
1051         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1052 }
1053
1054 /**
1055  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1056  * @adapter: address of board private structure
1057  * @rx_desc: advanced rx descriptor
1058  *
1059  * Returns : true if it is FCoE pkt
1060  */
1061 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1062                                     union ixgbe_adv_rx_desc *rx_desc)
1063 {
1064         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1065
1066         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1067                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1068                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1069                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1070 }
1071
1072 /**
1073  * ixgbe_receive_skb - Send a completed packet up the stack
1074  * @adapter: board private structure
1075  * @skb: packet to send up
1076  * @status: hardware indication of status of receive
1077  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1078  * @rx_desc: rx descriptor
1079  **/
1080 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1081                               struct sk_buff *skb, u8 status,
1082                               struct ixgbe_ring *ring,
1083                               union ixgbe_adv_rx_desc *rx_desc)
1084 {
1085         struct ixgbe_adapter *adapter = q_vector->adapter;
1086         struct napi_struct *napi = &q_vector->napi;
1087         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1088         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1089
1090         if (is_vlan && (tag & VLAN_VID_MASK))
1091                 __vlan_hwaccel_put_tag(skb, tag);
1092
1093         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1094                 napi_gro_receive(napi, skb);
1095         else
1096                 netif_rx(skb);
1097 }
1098
1099 /**
1100  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1101  * @adapter: address of board private structure
1102  * @status_err: hardware indication of status of receive
1103  * @skb: skb currently being received and modified
1104  * @status_err: status error value of last descriptor in packet
1105  **/
1106 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1107                                      union ixgbe_adv_rx_desc *rx_desc,
1108                                      struct sk_buff *skb,
1109                                      u32 status_err)
1110 {
1111         skb->ip_summed = CHECKSUM_NONE;
1112
1113         /* Rx csum disabled */
1114         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1115                 return;
1116
1117         /* if IP and error */
1118         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1119             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1120                 adapter->hw_csum_rx_error++;
1121                 return;
1122         }
1123
1124         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1125                 return;
1126
1127         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1128                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1129
1130                 /*
1131                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1132                  * checksum errors.
1133                  */
1134                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1135                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1136                         return;
1137
1138                 adapter->hw_csum_rx_error++;
1139                 return;
1140         }
1141
1142         /* It must be a TCP or UDP packet with a valid checksum */
1143         skb->ip_summed = CHECKSUM_UNNECESSARY;
1144 }
1145
1146 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1147 {
1148         /*
1149          * Force memory writes to complete before letting h/w
1150          * know there are new descriptors to fetch.  (Only
1151          * applicable for weak-ordered memory model archs,
1152          * such as IA-64).
1153          */
1154         wmb();
1155         writel(val, rx_ring->tail);
1156 }
1157
1158 /**
1159  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1160  * @rx_ring: ring to place buffers on
1161  * @cleaned_count: number of buffers to replace
1162  **/
1163 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1164 {
1165         union ixgbe_adv_rx_desc *rx_desc;
1166         struct ixgbe_rx_buffer *bi;
1167         struct sk_buff *skb;
1168         u16 i = rx_ring->next_to_use;
1169
1170         /* do nothing if no valid netdev defined */
1171         if (!rx_ring->netdev)
1172                 return;
1173
1174         while (cleaned_count--) {
1175                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1176                 bi = &rx_ring->rx_buffer_info[i];
1177                 skb = bi->skb;
1178
1179                 if (!skb) {
1180                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1181                                                         rx_ring->rx_buf_len);
1182                         if (!skb) {
1183                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1184                                 goto no_buffers;
1185                         }
1186                         /* initialize queue mapping */
1187                         skb_record_rx_queue(skb, rx_ring->queue_index);
1188                         bi->skb = skb;
1189                 }
1190
1191                 if (!bi->dma) {
1192                         bi->dma = dma_map_single(rx_ring->dev,
1193                                                  skb->data,
1194                                                  rx_ring->rx_buf_len,
1195                                                  DMA_FROM_DEVICE);
1196                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1197                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1198                                 bi->dma = 0;
1199                                 goto no_buffers;
1200                         }
1201                 }
1202
1203                 if (ring_is_ps_enabled(rx_ring)) {
1204                         if (!bi->page) {
1205                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1206                                 if (!bi->page) {
1207                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1208                                         goto no_buffers;
1209                                 }
1210                         }
1211
1212                         if (!bi->page_dma) {
1213                                 /* use a half page if we're re-using */
1214                                 bi->page_offset ^= PAGE_SIZE / 2;
1215                                 bi->page_dma = dma_map_page(rx_ring->dev,
1216                                                             bi->page,
1217                                                             bi->page_offset,
1218                                                             PAGE_SIZE / 2,
1219                                                             DMA_FROM_DEVICE);
1220                                 if (dma_mapping_error(rx_ring->dev,
1221                                                       bi->page_dma)) {
1222                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1223                                         bi->page_dma = 0;
1224                                         goto no_buffers;
1225                                 }
1226                         }
1227
1228                         /* Refresh the desc even if buffer_addrs didn't change
1229                          * because each write-back erases this info. */
1230                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1231                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1232                 } else {
1233                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1234                         rx_desc->read.hdr_addr = 0;
1235                 }
1236
1237                 i++;
1238                 if (i == rx_ring->count)
1239                         i = 0;
1240         }
1241
1242 no_buffers:
1243         if (rx_ring->next_to_use != i) {
1244                 rx_ring->next_to_use = i;
1245                 ixgbe_release_rx_desc(rx_ring, i);
1246         }
1247 }
1248
1249 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1250 {
1251         /* HW will not DMA in data larger than the given buffer, even if it
1252          * parses the (NFS, of course) header to be larger.  In that case, it
1253          * fills the header buffer and spills the rest into the page.
1254          */
1255         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1256         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1257                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1258         if (hlen > IXGBE_RX_HDR_SIZE)
1259                 hlen = IXGBE_RX_HDR_SIZE;
1260         return hlen;
1261 }
1262
1263 /**
1264  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1265  * @skb: pointer to the last skb in the rsc queue
1266  *
1267  * This function changes a queue full of hw rsc buffers into a completed
1268  * packet.  It uses the ->prev pointers to find the first packet and then
1269  * turns it into the frag list owner.
1270  **/
1271 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1272 {
1273         unsigned int frag_list_size = 0;
1274         unsigned int skb_cnt = 1;
1275
1276         while (skb->prev) {
1277                 struct sk_buff *prev = skb->prev;
1278                 frag_list_size += skb->len;
1279                 skb->prev = NULL;
1280                 skb = prev;
1281                 skb_cnt++;
1282         }
1283
1284         skb_shinfo(skb)->frag_list = skb->next;
1285         skb->next = NULL;
1286         skb->len += frag_list_size;
1287         skb->data_len += frag_list_size;
1288         skb->truesize += frag_list_size;
1289         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1290
1291         return skb;
1292 }
1293
1294 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1295 {
1296         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1297                 IXGBE_RXDADV_RSCCNT_MASK);
1298 }
1299
1300 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1301                                struct ixgbe_ring *rx_ring,
1302                                int budget)
1303 {
1304         struct ixgbe_adapter *adapter = q_vector->adapter;
1305         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1306         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1307         struct sk_buff *skb;
1308         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1309         const int current_node = numa_node_id();
1310 #ifdef IXGBE_FCOE
1311         int ddp_bytes = 0;
1312 #endif /* IXGBE_FCOE */
1313         u32 staterr;
1314         u16 i;
1315         u16 cleaned_count = 0;
1316         bool pkt_is_rsc = false;
1317
1318         i = rx_ring->next_to_clean;
1319         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1320         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1321
1322         while (staterr & IXGBE_RXD_STAT_DD) {
1323                 u32 upper_len = 0;
1324
1325                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1326
1327                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1328
1329                 skb = rx_buffer_info->skb;
1330                 rx_buffer_info->skb = NULL;
1331                 prefetch(skb->data);
1332
1333                 if (ring_is_rsc_enabled(rx_ring))
1334                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1335
1336                 /* if this is a skb from previous receive DMA will be 0 */
1337                 if (rx_buffer_info->dma) {
1338                         u16 hlen;
1339                         if (pkt_is_rsc &&
1340                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1341                             !skb->prev) {
1342                                 /*
1343                                  * When HWRSC is enabled, delay unmapping
1344                                  * of the first packet. It carries the
1345                                  * header information, HW may still
1346                                  * access the header after the writeback.
1347                                  * Only unmap it when EOP is reached
1348                                  */
1349                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1350                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1351                         } else {
1352                                 dma_unmap_single(rx_ring->dev,
1353                                                  rx_buffer_info->dma,
1354                                                  rx_ring->rx_buf_len,
1355                                                  DMA_FROM_DEVICE);
1356                         }
1357                         rx_buffer_info->dma = 0;
1358
1359                         if (ring_is_ps_enabled(rx_ring)) {
1360                                 hlen = ixgbe_get_hlen(rx_desc);
1361                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1362                         } else {
1363                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1364                         }
1365
1366                         skb_put(skb, hlen);
1367                 } else {
1368                         /* assume packet split since header is unmapped */
1369                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1370                 }
1371
1372                 if (upper_len) {
1373                         dma_unmap_page(rx_ring->dev,
1374                                        rx_buffer_info->page_dma,
1375                                        PAGE_SIZE / 2,
1376                                        DMA_FROM_DEVICE);
1377                         rx_buffer_info->page_dma = 0;
1378                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1379                                            rx_buffer_info->page,
1380                                            rx_buffer_info->page_offset,
1381                                            upper_len);
1382
1383                         if ((page_count(rx_buffer_info->page) == 1) &&
1384                             (page_to_nid(rx_buffer_info->page) == current_node))
1385                                 get_page(rx_buffer_info->page);
1386                         else
1387                                 rx_buffer_info->page = NULL;
1388
1389                         skb->len += upper_len;
1390                         skb->data_len += upper_len;
1391                         skb->truesize += upper_len;
1392                 }
1393
1394                 i++;
1395                 if (i == rx_ring->count)
1396                         i = 0;
1397
1398                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1399                 prefetch(next_rxd);
1400                 cleaned_count++;
1401
1402                 if (pkt_is_rsc) {
1403                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1404                                      IXGBE_RXDADV_NEXTP_SHIFT;
1405                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1406                 } else {
1407                         next_buffer = &rx_ring->rx_buffer_info[i];
1408                 }
1409
1410                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1411                         if (ring_is_ps_enabled(rx_ring)) {
1412                                 rx_buffer_info->skb = next_buffer->skb;
1413                                 rx_buffer_info->dma = next_buffer->dma;
1414                                 next_buffer->skb = skb;
1415                                 next_buffer->dma = 0;
1416                         } else {
1417                                 skb->next = next_buffer->skb;
1418                                 skb->next->prev = skb;
1419                         }
1420                         rx_ring->rx_stats.non_eop_descs++;
1421                         goto next_desc;
1422                 }
1423
1424                 if (skb->prev) {
1425                         skb = ixgbe_transform_rsc_queue(skb);
1426                         /* if we got here without RSC the packet is invalid */
1427                         if (!pkt_is_rsc) {
1428                                 __pskb_trim(skb, 0);
1429                                 rx_buffer_info->skb = skb;
1430                                 goto next_desc;
1431                         }
1432                 }
1433
1434                 if (ring_is_rsc_enabled(rx_ring)) {
1435                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1436                                 dma_unmap_single(rx_ring->dev,
1437                                                  IXGBE_RSC_CB(skb)->dma,
1438                                                  rx_ring->rx_buf_len,
1439                                                  DMA_FROM_DEVICE);
1440                                 IXGBE_RSC_CB(skb)->dma = 0;
1441                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1442                         }
1443                 }
1444                 if (pkt_is_rsc) {
1445                         if (ring_is_ps_enabled(rx_ring))
1446                                 rx_ring->rx_stats.rsc_count +=
1447                                         skb_shinfo(skb)->nr_frags;
1448                         else
1449                                 rx_ring->rx_stats.rsc_count +=
1450                                         IXGBE_RSC_CB(skb)->skb_cnt;
1451                         rx_ring->rx_stats.rsc_flush++;
1452                 }
1453
1454                 /* ERR_MASK will only have valid bits if EOP set */
1455                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1456                         dev_kfree_skb_any(skb);
1457                         goto next_desc;
1458                 }
1459
1460                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1461                 if (adapter->netdev->features & NETIF_F_RXHASH)
1462                         ixgbe_rx_hash(rx_desc, skb);
1463
1464                 /* probably a little skewed due to removing CRC */
1465                 total_rx_bytes += skb->len;
1466                 total_rx_packets++;
1467
1468                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1469 #ifdef IXGBE_FCOE
1470                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1471                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1472                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1473                                                    staterr);
1474                         if (!ddp_bytes) {
1475                                 dev_kfree_skb_any(skb);
1476                                 goto next_desc;
1477                         }
1478                 }
1479 #endif /* IXGBE_FCOE */
1480                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1481
1482                 budget--;
1483 next_desc:
1484                 rx_desc->wb.upper.status_error = 0;
1485
1486                 if (!budget)
1487                         break;
1488
1489                 /* return some buffers to hardware, one at a time is too slow */
1490                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1491                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1492                         cleaned_count = 0;
1493                 }
1494
1495                 /* use prefetched values */
1496                 rx_desc = next_rxd;
1497                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1498         }
1499
1500         rx_ring->next_to_clean = i;
1501         cleaned_count = ixgbe_desc_unused(rx_ring);
1502
1503         if (cleaned_count)
1504                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1505
1506 #ifdef IXGBE_FCOE
1507         /* include DDPed FCoE data */
1508         if (ddp_bytes > 0) {
1509                 unsigned int mss;
1510
1511                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1512                         sizeof(struct fc_frame_header) -
1513                         sizeof(struct fcoe_crc_eof);
1514                 if (mss > 512)
1515                         mss &= ~511;
1516                 total_rx_bytes += ddp_bytes;
1517                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1518         }
1519 #endif /* IXGBE_FCOE */
1520
1521         u64_stats_update_begin(&rx_ring->syncp);
1522         rx_ring->stats.packets += total_rx_packets;
1523         rx_ring->stats.bytes += total_rx_bytes;
1524         u64_stats_update_end(&rx_ring->syncp);
1525         q_vector->rx.total_packets += total_rx_packets;
1526         q_vector->rx.total_bytes += total_rx_bytes;
1527
1528         return !!budget;
1529 }
1530
1531 /**
1532  * ixgbe_configure_msix - Configure MSI-X hardware
1533  * @adapter: board private structure
1534  *
1535  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1536  * interrupts.
1537  **/
1538 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1539 {
1540         struct ixgbe_q_vector *q_vector;
1541         int q_vectors, v_idx;
1542         u32 mask;
1543
1544         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1545
1546         /*
1547          * Populate the IVAR table and set the ITR values to the
1548          * corresponding register.
1549          */
1550         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1551                 struct ixgbe_ring *ring;
1552                 q_vector = adapter->q_vector[v_idx];
1553
1554                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1555                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1556
1557                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1558                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1559
1560                 if (q_vector->tx.ring && !q_vector->rx.ring)
1561                         /* tx only */
1562                         q_vector->eitr = adapter->tx_eitr_param;
1563                 else if (q_vector->rx.ring)
1564                         /* rx or mixed */
1565                         q_vector->eitr = adapter->rx_eitr_param;
1566
1567                 ixgbe_write_eitr(q_vector);
1568         }
1569
1570         switch (adapter->hw.mac.type) {
1571         case ixgbe_mac_82598EB:
1572                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1573                                v_idx);
1574                 break;
1575         case ixgbe_mac_82599EB:
1576         case ixgbe_mac_X540:
1577                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1578                 break;
1579
1580         default:
1581                 break;
1582         }
1583         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1584
1585         /* set up to autoclear timer, and the vectors */
1586         mask = IXGBE_EIMS_ENABLE_MASK;
1587         if (adapter->num_vfs)
1588                 mask &= ~(IXGBE_EIMS_OTHER |
1589                           IXGBE_EIMS_MAILBOX |
1590                           IXGBE_EIMS_LSC);
1591         else
1592                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1593         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1594 }
1595
1596 enum latency_range {
1597         lowest_latency = 0,
1598         low_latency = 1,
1599         bulk_latency = 2,
1600         latency_invalid = 255
1601 };
1602
1603 /**
1604  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1605  * @q_vector: structure containing interrupt and ring information
1606  * @ring_container: structure containing ring performance data
1607  *
1608  *      Stores a new ITR value based on packets and byte
1609  *      counts during the last interrupt.  The advantage of per interrupt
1610  *      computation is faster updates and more accurate ITR for the current
1611  *      traffic pattern.  Constants in this function were computed
1612  *      based on theoretical maximum wire speed and thresholds were set based
1613  *      on testing data as well as attempting to minimize response time
1614  *      while increasing bulk throughput.
1615  *      this functionality is controlled by the InterruptThrottleRate module
1616  *      parameter (see ixgbe_param.c)
1617  **/
1618 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1619                              struct ixgbe_ring_container *ring_container)
1620 {
1621         u64 bytes_perint;
1622         struct ixgbe_adapter *adapter = q_vector->adapter;
1623         int bytes = ring_container->total_bytes;
1624         int packets = ring_container->total_packets;
1625         u32 timepassed_us;
1626         u8 itr_setting = ring_container->itr;
1627
1628         if (packets == 0)
1629                 return;
1630
1631         /* simple throttlerate management
1632          *    0-20MB/s lowest (100000 ints/s)
1633          *   20-100MB/s low   (20000 ints/s)
1634          *  100-1249MB/s bulk (8000 ints/s)
1635          */
1636         /* what was last interrupt timeslice? */
1637         timepassed_us = 1000000/q_vector->eitr;
1638         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1639
1640         switch (itr_setting) {
1641         case lowest_latency:
1642                 if (bytes_perint > adapter->eitr_low)
1643                         itr_setting = low_latency;
1644                 break;
1645         case low_latency:
1646                 if (bytes_perint > adapter->eitr_high)
1647                         itr_setting = bulk_latency;
1648                 else if (bytes_perint <= adapter->eitr_low)
1649                         itr_setting = lowest_latency;
1650                 break;
1651         case bulk_latency:
1652                 if (bytes_perint <= adapter->eitr_high)
1653                         itr_setting = low_latency;
1654                 break;
1655         }
1656
1657         /* clear work counters since we have the values we need */
1658         ring_container->total_bytes = 0;
1659         ring_container->total_packets = 0;
1660
1661         /* write updated itr to ring container */
1662         ring_container->itr = itr_setting;
1663 }
1664
1665 /**
1666  * ixgbe_write_eitr - write EITR register in hardware specific way
1667  * @q_vector: structure containing interrupt and ring information
1668  *
1669  * This function is made to be called by ethtool and by the driver
1670  * when it needs to update EITR registers at runtime.  Hardware
1671  * specific quirks/differences are taken care of here.
1672  */
1673 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1674 {
1675         struct ixgbe_adapter *adapter = q_vector->adapter;
1676         struct ixgbe_hw *hw = &adapter->hw;
1677         int v_idx = q_vector->v_idx;
1678         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1679
1680         switch (adapter->hw.mac.type) {
1681         case ixgbe_mac_82598EB:
1682                 /* must write high and low 16 bits to reset counter */
1683                 itr_reg |= (itr_reg << 16);
1684                 break;
1685         case ixgbe_mac_82599EB:
1686         case ixgbe_mac_X540:
1687                 /*
1688                  * 82599 and X540 can support a value of zero, so allow it for
1689                  * max interrupt rate, but there is an errata where it can
1690                  * not be zero with RSC
1691                  */
1692                 if (itr_reg == 8 &&
1693                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1694                         itr_reg = 0;
1695
1696                 /*
1697                  * set the WDIS bit to not clear the timer bits and cause an
1698                  * immediate assertion of the interrupt
1699                  */
1700                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1701                 break;
1702         default:
1703                 break;
1704         }
1705         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1706 }
1707
1708 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1709 {
1710         u32 new_itr = q_vector->eitr;
1711         u8 current_itr;
1712
1713         ixgbe_update_itr(q_vector, &q_vector->tx);
1714         ixgbe_update_itr(q_vector, &q_vector->rx);
1715
1716         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1717
1718         switch (current_itr) {
1719         /* counts and packets in update_itr are dependent on these numbers */
1720         case lowest_latency:
1721                 new_itr = 100000;
1722                 break;
1723         case low_latency:
1724                 new_itr = 20000; /* aka hwitr = ~200 */
1725                 break;
1726         case bulk_latency:
1727                 new_itr = 8000;
1728                 break;
1729         default:
1730                 break;
1731         }
1732
1733         if (new_itr != q_vector->eitr) {
1734                 /* do an exponential smoothing */
1735                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1736
1737                 /* save the algorithm value here */
1738                 q_vector->eitr = new_itr;
1739
1740                 ixgbe_write_eitr(q_vector);
1741         }
1742 }
1743
1744 /**
1745  * ixgbe_check_overtemp_subtask - check for over tempurature
1746  * @adapter: pointer to adapter
1747  **/
1748 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1749 {
1750         struct ixgbe_hw *hw = &adapter->hw;
1751         u32 eicr = adapter->interrupt_event;
1752
1753         if (test_bit(__IXGBE_DOWN, &adapter->state))
1754                 return;
1755
1756         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1757             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1758                 return;
1759
1760         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1761
1762         switch (hw->device_id) {
1763         case IXGBE_DEV_ID_82599_T3_LOM:
1764                 /*
1765                  * Since the warning interrupt is for both ports
1766                  * we don't have to check if:
1767                  *  - This interrupt wasn't for our port.
1768                  *  - We may have missed the interrupt so always have to
1769                  *    check if we  got a LSC
1770                  */
1771                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1772                     !(eicr & IXGBE_EICR_LSC))
1773                         return;
1774
1775                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1776                         u32 autoneg;
1777                         bool link_up = false;
1778
1779                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1780
1781                         if (link_up)
1782                                 return;
1783                 }
1784
1785                 /* Check if this is not due to overtemp */
1786                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1787                         return;
1788
1789                 break;
1790         default:
1791                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1792                         return;
1793                 break;
1794         }
1795         e_crit(drv,
1796                "Network adapter has been stopped because it has over heated. "
1797                "Restart the computer. If the problem persists, "
1798                "power off the system and replace the adapter\n");
1799
1800         adapter->interrupt_event = 0;
1801 }
1802
1803 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1804 {
1805         struct ixgbe_hw *hw = &adapter->hw;
1806
1807         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1808             (eicr & IXGBE_EICR_GPI_SDP1)) {
1809                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1810                 /* write to clear the interrupt */
1811                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1812         }
1813 }
1814
1815 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1816 {
1817         struct ixgbe_hw *hw = &adapter->hw;
1818
1819         if (eicr & IXGBE_EICR_GPI_SDP2) {
1820                 /* Clear the interrupt */
1821                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1822                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1823                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1824                         ixgbe_service_event_schedule(adapter);
1825                 }
1826         }
1827
1828         if (eicr & IXGBE_EICR_GPI_SDP1) {
1829                 /* Clear the interrupt */
1830                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1831                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1832                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1833                         ixgbe_service_event_schedule(adapter);
1834                 }
1835         }
1836 }
1837
1838 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1839 {
1840         struct ixgbe_hw *hw = &adapter->hw;
1841
1842         adapter->lsc_int++;
1843         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1844         adapter->link_check_timeout = jiffies;
1845         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1846                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1847                 IXGBE_WRITE_FLUSH(hw);
1848                 ixgbe_service_event_schedule(adapter);
1849         }
1850 }
1851
1852 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1853 {
1854         struct ixgbe_adapter *adapter = data;
1855         struct ixgbe_hw *hw = &adapter->hw;
1856         u32 eicr;
1857
1858         /*
1859          * Workaround for Silicon errata.  Use clear-by-write instead
1860          * of clear-by-read.  Reading with EICS will return the
1861          * interrupt causes without clearing, which later be done
1862          * with the write to EICR.
1863          */
1864         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1865         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1866
1867         if (eicr & IXGBE_EICR_LSC)
1868                 ixgbe_check_lsc(adapter);
1869
1870         if (eicr & IXGBE_EICR_MAILBOX)
1871                 ixgbe_msg_task(adapter);
1872
1873         switch (hw->mac.type) {
1874         case ixgbe_mac_82599EB:
1875         case ixgbe_mac_X540:
1876                 /* Handle Flow Director Full threshold interrupt */
1877                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1878                         int reinit_count = 0;
1879                         int i;
1880                         for (i = 0; i < adapter->num_tx_queues; i++) {
1881                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1882                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1883                                                        &ring->state))
1884                                         reinit_count++;
1885                         }
1886                         if (reinit_count) {
1887                                 /* no more flow director interrupts until after init */
1888                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1889                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1890                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1891                                 ixgbe_service_event_schedule(adapter);
1892                         }
1893                 }
1894                 ixgbe_check_sfp_event(adapter, eicr);
1895                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1896                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1897                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1898                                 adapter->interrupt_event = eicr;
1899                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1900                                 ixgbe_service_event_schedule(adapter);
1901                         }
1902                 }
1903                 break;
1904         default:
1905                 break;
1906         }
1907
1908         ixgbe_check_fan_failure(adapter, eicr);
1909
1910         /* re-enable the original interrupt state, no lsc, no queues */
1911         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1912                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1913                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1914
1915         return IRQ_HANDLED;
1916 }
1917
1918 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1919                                            u64 qmask)
1920 {
1921         u32 mask;
1922         struct ixgbe_hw *hw = &adapter->hw;
1923
1924         switch (hw->mac.type) {
1925         case ixgbe_mac_82598EB:
1926                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1927                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1928                 break;
1929         case ixgbe_mac_82599EB:
1930         case ixgbe_mac_X540:
1931                 mask = (qmask & 0xFFFFFFFF);
1932                 if (mask)
1933                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1934                 mask = (qmask >> 32);
1935                 if (mask)
1936                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1937                 break;
1938         default:
1939                 break;
1940         }
1941         /* skip the flush */
1942 }
1943
1944 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1945                                             u64 qmask)
1946 {
1947         u32 mask;
1948         struct ixgbe_hw *hw = &adapter->hw;
1949
1950         switch (hw->mac.type) {
1951         case ixgbe_mac_82598EB:
1952                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1953                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1954                 break;
1955         case ixgbe_mac_82599EB:
1956         case ixgbe_mac_X540:
1957                 mask = (qmask & 0xFFFFFFFF);
1958                 if (mask)
1959                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1960                 mask = (qmask >> 32);
1961                 if (mask)
1962                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1963                 break;
1964         default:
1965                 break;
1966         }
1967         /* skip the flush */
1968 }
1969
1970 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1971 {
1972         struct ixgbe_q_vector *q_vector = data;
1973
1974         /* EIAM disabled interrupts (on this vector) for us */
1975
1976         if (q_vector->rx.ring || q_vector->tx.ring)
1977                 napi_schedule(&q_vector->napi);
1978
1979         return IRQ_HANDLED;
1980 }
1981
1982 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1983                                      int r_idx)
1984 {
1985         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1986         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
1987
1988         rx_ring->q_vector = q_vector;
1989         rx_ring->next = q_vector->rx.ring;
1990         q_vector->rx.ring = rx_ring;
1991         q_vector->rx.count++;
1992 }
1993
1994 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1995                                      int t_idx)
1996 {
1997         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1998         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
1999
2000         tx_ring->q_vector = q_vector;
2001         tx_ring->next = q_vector->tx.ring;
2002         q_vector->tx.ring = tx_ring;
2003         q_vector->tx.count++;
2004         q_vector->tx.work_limit = a->tx_work_limit;
2005 }
2006
2007 /**
2008  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2009  * @adapter: board private structure to initialize
2010  *
2011  * This function maps descriptor rings to the queue-specific vectors
2012  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2013  * one vector per ring/queue, but on a constrained vector budget, we
2014  * group the rings as "efficiently" as possible.  You would add new
2015  * mapping configurations in here.
2016  **/
2017 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2018 {
2019         int q_vectors;
2020         int v_start = 0;
2021         int rxr_idx = 0, txr_idx = 0;
2022         int rxr_remaining = adapter->num_rx_queues;
2023         int txr_remaining = adapter->num_tx_queues;
2024         int i, j;
2025         int rqpv, tqpv;
2026         int err = 0;
2027
2028         /* No mapping required if MSI-X is disabled. */
2029         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2030                 goto out;
2031
2032         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2033
2034         /*
2035          * The ideal configuration...
2036          * We have enough vectors to map one per queue.
2037          */
2038         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2039                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2040                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2041
2042                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2043                         map_vector_to_txq(adapter, v_start, txr_idx);
2044
2045                 goto out;
2046         }
2047
2048         /*
2049          * If we don't have enough vectors for a 1-to-1
2050          * mapping, we'll have to group them so there are
2051          * multiple queues per vector.
2052          */
2053         /* Re-adjusting *qpv takes care of the remainder. */
2054         for (i = v_start; i < q_vectors; i++) {
2055                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2056                 for (j = 0; j < rqpv; j++) {
2057                         map_vector_to_rxq(adapter, i, rxr_idx);
2058                         rxr_idx++;
2059                         rxr_remaining--;
2060                 }
2061                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2062                 for (j = 0; j < tqpv; j++) {
2063                         map_vector_to_txq(adapter, i, txr_idx);
2064                         txr_idx++;
2065                         txr_remaining--;
2066                 }
2067         }
2068 out:
2069         return err;
2070 }
2071
2072 /**
2073  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2074  * @adapter: board private structure
2075  *
2076  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2077  * interrupts from the kernel.
2078  **/
2079 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2080 {
2081         struct net_device *netdev = adapter->netdev;
2082         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2083         int vector, err;
2084         int ri = 0, ti = 0;
2085
2086         err = ixgbe_map_rings_to_vectors(adapter);
2087         if (err)
2088                 return err;
2089
2090         for (vector = 0; vector < q_vectors; vector++) {
2091                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2092                 struct msix_entry *entry = &adapter->msix_entries[vector];
2093
2094                 if (q_vector->tx.ring && q_vector->rx.ring) {
2095                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2096                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2097                         ti++;
2098                 } else if (q_vector->rx.ring) {
2099                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2100                                  "%s-%s-%d", netdev->name, "rx", ri++);
2101                 } else if (q_vector->tx.ring) {
2102                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2103                                  "%s-%s-%d", netdev->name, "tx", ti++);
2104                 } else {
2105                         /* skip this unused q_vector */
2106                         continue;
2107                 }
2108                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2109                                   q_vector->name, q_vector);
2110                 if (err) {
2111                         e_err(probe, "request_irq failed for MSIX interrupt "
2112                               "Error: %d\n", err);
2113                         goto free_queue_irqs;
2114                 }
2115                 /* If Flow Director is enabled, set interrupt affinity */
2116                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2117                         /* assign the mask for this irq */
2118                         irq_set_affinity_hint(entry->vector,
2119                                               q_vector->affinity_mask);
2120                 }
2121         }
2122
2123         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2124         err = request_irq(adapter->msix_entries[vector].vector,
2125                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2126         if (err) {
2127                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2128                 goto free_queue_irqs;
2129         }
2130
2131         return 0;
2132
2133 free_queue_irqs:
2134         while (vector) {
2135                 vector--;
2136                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2137                                       NULL);
2138                 free_irq(adapter->msix_entries[vector].vector,
2139                          adapter->q_vector[vector]);
2140         }
2141         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2142         pci_disable_msix(adapter->pdev);
2143         kfree(adapter->msix_entries);
2144         adapter->msix_entries = NULL;
2145         return err;
2146 }
2147
2148 /**
2149  * ixgbe_irq_enable - Enable default interrupt generation settings
2150  * @adapter: board private structure
2151  **/
2152 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2153                                     bool flush)
2154 {
2155         u32 mask;
2156
2157         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2158         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2159                 mask |= IXGBE_EIMS_GPI_SDP0;
2160         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2161                 mask |= IXGBE_EIMS_GPI_SDP1;
2162         switch (adapter->hw.mac.type) {
2163         case ixgbe_mac_82599EB:
2164         case ixgbe_mac_X540:
2165                 mask |= IXGBE_EIMS_ECC;
2166                 mask |= IXGBE_EIMS_GPI_SDP1;
2167                 mask |= IXGBE_EIMS_GPI_SDP2;
2168                 if (adapter->num_vfs)
2169                         mask |= IXGBE_EIMS_MAILBOX;
2170                 break;
2171         default:
2172                 break;
2173         }
2174         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2175                 mask |= IXGBE_EIMS_FLOW_DIR;
2176
2177         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2178         if (queues)
2179                 ixgbe_irq_enable_queues(adapter, ~0);
2180         if (flush)
2181                 IXGBE_WRITE_FLUSH(&adapter->hw);
2182
2183         if (adapter->num_vfs > 32) {
2184                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2185                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2186         }
2187 }
2188
2189 /**
2190  * ixgbe_intr - legacy mode Interrupt Handler
2191  * @irq: interrupt number
2192  * @data: pointer to a network interface device structure
2193  **/
2194 static irqreturn_t ixgbe_intr(int irq, void *data)
2195 {
2196         struct ixgbe_adapter *adapter = data;
2197         struct ixgbe_hw *hw = &adapter->hw;
2198         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2199         u32 eicr;
2200
2201         /*
2202          * Workaround for silicon errata on 82598.  Mask the interrupts
2203          * before the read of EICR.
2204          */
2205         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2206
2207         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2208          * therefore no explict interrupt disable is necessary */
2209         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2210         if (!eicr) {
2211                 /*
2212                  * shared interrupt alert!
2213                  * make sure interrupts are enabled because the read will
2214                  * have disabled interrupts due to EIAM
2215                  * finish the workaround of silicon errata on 82598.  Unmask
2216                  * the interrupt that we masked before the EICR read.
2217                  */
2218                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2219                         ixgbe_irq_enable(adapter, true, true);
2220                 return IRQ_NONE;        /* Not our interrupt */
2221         }
2222
2223         if (eicr & IXGBE_EICR_LSC)
2224                 ixgbe_check_lsc(adapter);
2225
2226         switch (hw->mac.type) {
2227         case ixgbe_mac_82599EB:
2228                 ixgbe_check_sfp_event(adapter, eicr);
2229                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2230                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2231                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2232                                 adapter->interrupt_event = eicr;
2233                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2234                                 ixgbe_service_event_schedule(adapter);
2235                         }
2236                 }
2237                 break;
2238         default:
2239                 break;
2240         }
2241
2242         ixgbe_check_fan_failure(adapter, eicr);
2243
2244         if (napi_schedule_prep(&(q_vector->napi))) {
2245                 /* would disable interrupts here but EIAM disabled it */
2246                 __napi_schedule(&(q_vector->napi));
2247         }
2248
2249         /*
2250          * re-enable link(maybe) and non-queue interrupts, no flush.
2251          * ixgbe_poll will re-enable the queue interrupts
2252          */
2253
2254         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2255                 ixgbe_irq_enable(adapter, false, false);
2256
2257         return IRQ_HANDLED;
2258 }
2259
2260 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2261 {
2262         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2263         int i;
2264
2265         /* legacy and MSI only use one vector */
2266         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2267                 q_vectors = 1;
2268
2269         for (i = 0; i < adapter->num_rx_queues; i++) {
2270                 adapter->rx_ring[i]->q_vector = NULL;
2271                 adapter->rx_ring[i]->next = NULL;
2272         }
2273         for (i = 0; i < adapter->num_tx_queues; i++) {
2274                 adapter->tx_ring[i]->q_vector = NULL;
2275                 adapter->tx_ring[i]->next = NULL;
2276         }
2277
2278         for (i = 0; i < q_vectors; i++) {
2279                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2280                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2281                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2282         }
2283 }
2284
2285 /**
2286  * ixgbe_request_irq - initialize interrupts
2287  * @adapter: board private structure
2288  *
2289  * Attempts to configure interrupts using the best available
2290  * capabilities of the hardware and kernel.
2291  **/
2292 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2293 {
2294         struct net_device *netdev = adapter->netdev;
2295         int err;
2296
2297         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2298                 err = ixgbe_request_msix_irqs(adapter);
2299         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2300                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2301                                   netdev->name, adapter);
2302         } else {
2303                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2304                                   netdev->name, adapter);
2305         }
2306
2307         if (err)
2308                 e_err(probe, "request_irq failed, Error %d\n", err);
2309
2310         return err;
2311 }
2312
2313 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2314 {
2315         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2316                 int i, q_vectors;
2317
2318                 q_vectors = adapter->num_msix_vectors;
2319
2320                 i = q_vectors - 1;
2321                 free_irq(adapter->msix_entries[i].vector, adapter);
2322
2323                 i--;
2324                 for (; i >= 0; i--) {
2325                         /* free only the irqs that were actually requested */
2326                         if (!adapter->q_vector[i]->rx.ring &&
2327                             !adapter->q_vector[i]->tx.ring)
2328                                 continue;
2329
2330                         /* clear the affinity_mask in the IRQ descriptor */
2331                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2332                                               NULL);
2333
2334                         free_irq(adapter->msix_entries[i].vector,
2335                                  adapter->q_vector[i]);
2336                 }
2337         } else {
2338                 free_irq(adapter->pdev->irq, adapter);
2339         }
2340
2341         /* clear q_vector state information */
2342         ixgbe_reset_q_vectors(adapter);
2343 }
2344
2345 /**
2346  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2347  * @adapter: board private structure
2348  **/
2349 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2350 {
2351         switch (adapter->hw.mac.type) {
2352         case ixgbe_mac_82598EB:
2353                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2354                 break;
2355         case ixgbe_mac_82599EB:
2356         case ixgbe_mac_X540:
2357                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2358                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2359                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2360                 if (adapter->num_vfs > 32)
2361                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2362                 break;
2363         default:
2364                 break;
2365         }
2366         IXGBE_WRITE_FLUSH(&adapter->hw);
2367         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2368                 int i;
2369                 for (i = 0; i < adapter->num_msix_vectors; i++)
2370                         synchronize_irq(adapter->msix_entries[i].vector);
2371         } else {
2372                 synchronize_irq(adapter->pdev->irq);
2373         }
2374 }
2375
2376 /**
2377  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2378  *
2379  **/
2380 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2381 {
2382         struct ixgbe_hw *hw = &adapter->hw;
2383
2384         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2385                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2386
2387         ixgbe_set_ivar(adapter, 0, 0, 0);
2388         ixgbe_set_ivar(adapter, 1, 0, 0);
2389
2390         map_vector_to_rxq(adapter, 0, 0);
2391         map_vector_to_txq(adapter, 0, 0);
2392
2393         e_info(hw, "Legacy interrupt IVAR setup done\n");
2394 }
2395
2396 /**
2397  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2398  * @adapter: board private structure
2399  * @ring: structure containing ring specific data
2400  *
2401  * Configure the Tx descriptor ring after a reset.
2402  **/
2403 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2404                              struct ixgbe_ring *ring)
2405 {
2406         struct ixgbe_hw *hw = &adapter->hw;
2407         u64 tdba = ring->dma;
2408         int wait_loop = 10;
2409         u32 txdctl;
2410         u8 reg_idx = ring->reg_idx;
2411
2412         /* disable queue to avoid issues while updating state */
2413         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2414         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2415                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2416         IXGBE_WRITE_FLUSH(hw);
2417
2418         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2419                         (tdba & DMA_BIT_MASK(32)));
2420         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2421         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2422                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2423         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2424         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2425         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2426
2427         /* configure fetching thresholds */
2428         if (adapter->rx_itr_setting == 0) {
2429                 /* cannot set wthresh when itr==0 */
2430                 txdctl &= ~0x007F0000;
2431         } else {
2432                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2433                 txdctl |= (8 << 16);
2434         }
2435         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2436                 /* PThresh workaround for Tx hang with DFP enabled. */
2437                 txdctl |= 32;
2438         }
2439
2440         /* reinitialize flowdirector state */
2441         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2442             adapter->atr_sample_rate) {
2443                 ring->atr_sample_rate = adapter->atr_sample_rate;
2444                 ring->atr_count = 0;
2445                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2446         } else {
2447                 ring->atr_sample_rate = 0;
2448         }
2449
2450         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2451
2452         /* enable queue */
2453         txdctl |= IXGBE_TXDCTL_ENABLE;
2454         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2455
2456         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2457         if (hw->mac.type == ixgbe_mac_82598EB &&
2458             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2459                 return;
2460
2461         /* poll to verify queue is enabled */
2462         do {
2463                 usleep_range(1000, 2000);
2464                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2465         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2466         if (!wait_loop)
2467                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2468 }
2469
2470 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2471 {
2472         struct ixgbe_hw *hw = &adapter->hw;
2473         u32 rttdcs;
2474         u32 reg;
2475         u8 tcs = netdev_get_num_tc(adapter->netdev);
2476
2477         if (hw->mac.type == ixgbe_mac_82598EB)
2478                 return;
2479
2480         /* disable the arbiter while setting MTQC */
2481         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2482         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2483         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2484
2485         /* set transmit pool layout */
2486         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2487         case (IXGBE_FLAG_SRIOV_ENABLED):
2488                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2489                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2490                 break;
2491         default:
2492                 if (!tcs)
2493                         reg = IXGBE_MTQC_64Q_1PB;
2494                 else if (tcs <= 4)
2495                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2496                 else
2497                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2498
2499                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2500
2501                 /* Enable Security TX Buffer IFG for multiple pb */
2502                 if (tcs) {
2503                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2504                         reg |= IXGBE_SECTX_DCB;
2505                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2506                 }
2507                 break;
2508         }
2509
2510         /* re-enable the arbiter */
2511         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2512         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2513 }
2514
2515 /**
2516  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2517  * @adapter: board private structure
2518  *
2519  * Configure the Tx unit of the MAC after a reset.
2520  **/
2521 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2522 {
2523         struct ixgbe_hw *hw = &adapter->hw;
2524         u32 dmatxctl;
2525         u32 i;
2526
2527         ixgbe_setup_mtqc(adapter);
2528
2529         if (hw->mac.type != ixgbe_mac_82598EB) {
2530                 /* DMATXCTL.EN must be before Tx queues are enabled */
2531                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2532                 dmatxctl |= IXGBE_DMATXCTL_TE;
2533                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2534         }
2535
2536         /* Setup the HW Tx Head and Tail descriptor pointers */
2537         for (i = 0; i < adapter->num_tx_queues; i++)
2538                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2539 }
2540
2541 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2542
2543 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2544                                    struct ixgbe_ring *rx_ring)
2545 {
2546         u32 srrctl;
2547         u8 reg_idx = rx_ring->reg_idx;
2548
2549         switch (adapter->hw.mac.type) {
2550         case ixgbe_mac_82598EB: {
2551                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2552                 const int mask = feature[RING_F_RSS].mask;
2553                 reg_idx = reg_idx & mask;
2554         }
2555                 break;
2556         case ixgbe_mac_82599EB:
2557         case ixgbe_mac_X540:
2558         default:
2559                 break;
2560         }
2561
2562         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2563
2564         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2565         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2566         if (adapter->num_vfs)
2567                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2568
2569         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2570                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2571
2572         if (ring_is_ps_enabled(rx_ring)) {
2573 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2574                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2575 #else
2576                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2577 #endif
2578                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2579         } else {
2580                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2581                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2582                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2583         }
2584
2585         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2586 }
2587
2588 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2589 {
2590         struct ixgbe_hw *hw = &adapter->hw;
2591         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2592                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2593                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2594         u32 mrqc = 0, reta = 0;
2595         u32 rxcsum;
2596         int i, j;
2597         u8 tcs = netdev_get_num_tc(adapter->netdev);
2598         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2599
2600         if (tcs)
2601                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2602
2603         /* Fill out hash function seeds */
2604         for (i = 0; i < 10; i++)
2605                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2606
2607         /* Fill out redirection table */
2608         for (i = 0, j = 0; i < 128; i++, j++) {
2609                 if (j == maxq)
2610                         j = 0;
2611                 /* reta = 4-byte sliding window of
2612                  * 0x00..(indices-1)(indices-1)00..etc. */
2613                 reta = (reta << 8) | (j * 0x11);
2614                 if ((i & 3) == 3)
2615                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2616         }
2617
2618         /* Disable indicating checksum in descriptor, enables RSS hash */
2619         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2620         rxcsum |= IXGBE_RXCSUM_PCSD;
2621         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2622
2623         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2624             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2625                 mrqc = IXGBE_MRQC_RSSEN;
2626         } else {
2627                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2628                                              | IXGBE_FLAG_SRIOV_ENABLED);
2629
2630                 switch (mask) {
2631                 case (IXGBE_FLAG_RSS_ENABLED):
2632                         if (!tcs)
2633                                 mrqc = IXGBE_MRQC_RSSEN;
2634                         else if (tcs <= 4)
2635                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2636                         else
2637                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2638                         break;
2639                 case (IXGBE_FLAG_SRIOV_ENABLED):
2640                         mrqc = IXGBE_MRQC_VMDQEN;
2641                         break;
2642                 default:
2643                         break;
2644                 }
2645         }
2646
2647         /* Perform hash on these packet types */
2648         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2649               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2650               | IXGBE_MRQC_RSS_FIELD_IPV6
2651               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2652
2653         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2654 }
2655
2656 /**
2657  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2658  * @adapter:    address of board private structure
2659  * @index:      index of ring to set
2660  **/
2661 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2662                                    struct ixgbe_ring *ring)
2663 {
2664         struct ixgbe_hw *hw = &adapter->hw;
2665         u32 rscctrl;
2666         int rx_buf_len;
2667         u8 reg_idx = ring->reg_idx;
2668
2669         if (!ring_is_rsc_enabled(ring))
2670                 return;
2671
2672         rx_buf_len = ring->rx_buf_len;
2673         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2674         rscctrl |= IXGBE_RSCCTL_RSCEN;
2675         /*
2676          * we must limit the number of descriptors so that the
2677          * total size of max desc * buf_len is not greater
2678          * than 65535
2679          */
2680         if (ring_is_ps_enabled(ring)) {
2681 #if (MAX_SKB_FRAGS > 16)
2682                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2683 #elif (MAX_SKB_FRAGS > 8)
2684                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2685 #elif (MAX_SKB_FRAGS > 4)
2686                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2687 #else
2688                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2689 #endif
2690         } else {
2691                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2692                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2693                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2694                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2695                 else
2696                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2697         }
2698         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2699 }
2700
2701 /**
2702  *  ixgbe_set_uta - Set unicast filter table address
2703  *  @adapter: board private structure
2704  *
2705  *  The unicast table address is a register array of 32-bit registers.
2706  *  The table is meant to be used in a way similar to how the MTA is used
2707  *  however due to certain limitations in the hardware it is necessary to
2708  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2709  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2710  **/
2711 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2712 {
2713         struct ixgbe_hw *hw = &adapter->hw;
2714         int i;
2715
2716         /* The UTA table only exists on 82599 hardware and newer */
2717         if (hw->mac.type < ixgbe_mac_82599EB)
2718                 return;
2719
2720         /* we only need to do this if VMDq is enabled */
2721         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2722                 return;
2723
2724         for (i = 0; i < 128; i++)
2725                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2726 }
2727
2728 #define IXGBE_MAX_RX_DESC_POLL 10
2729 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2730                                        struct ixgbe_ring *ring)
2731 {
2732         struct ixgbe_hw *hw = &adapter->hw;
2733         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2734         u32 rxdctl;
2735         u8 reg_idx = ring->reg_idx;
2736
2737         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2738         if (hw->mac.type == ixgbe_mac_82598EB &&
2739             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2740                 return;
2741
2742         do {
2743                 usleep_range(1000, 2000);
2744                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2745         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2746
2747         if (!wait_loop) {
2748                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2749                       "the polling period\n", reg_idx);
2750         }
2751 }
2752
2753 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2754                             struct ixgbe_ring *ring)
2755 {
2756         struct ixgbe_hw *hw = &adapter->hw;
2757         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2758         u32 rxdctl;
2759         u8 reg_idx = ring->reg_idx;
2760
2761         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2762         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2763
2764         /* write value back with RXDCTL.ENABLE bit cleared */
2765         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2766
2767         if (hw->mac.type == ixgbe_mac_82598EB &&
2768             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2769                 return;
2770
2771         /* the hardware may take up to 100us to really disable the rx queue */
2772         do {
2773                 udelay(10);
2774                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2775         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2776
2777         if (!wait_loop) {
2778                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2779                       "the polling period\n", reg_idx);
2780         }
2781 }
2782
2783 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2784                              struct ixgbe_ring *ring)
2785 {
2786         struct ixgbe_hw *hw = &adapter->hw;
2787         u64 rdba = ring->dma;
2788         u32 rxdctl;
2789         u8 reg_idx = ring->reg_idx;
2790
2791         /* disable queue to avoid issues while updating state */
2792         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2793         ixgbe_disable_rx_queue(adapter, ring);
2794
2795         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2796         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2797         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2798                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2799         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2800         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2801         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2802
2803         ixgbe_configure_srrctl(adapter, ring);
2804         ixgbe_configure_rscctl(adapter, ring);
2805
2806         /* If operating in IOV mode set RLPML for X540 */
2807         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2808             hw->mac.type == ixgbe_mac_X540) {
2809                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2810                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2811                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2812         }
2813
2814         if (hw->mac.type == ixgbe_mac_82598EB) {
2815                 /*
2816                  * enable cache line friendly hardware writes:
2817                  * PTHRESH=32 descriptors (half the internal cache),
2818                  * this also removes ugly rx_no_buffer_count increment
2819                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2820                  * WTHRESH=8 burst writeback up to two cache lines
2821                  */
2822                 rxdctl &= ~0x3FFFFF;
2823                 rxdctl |=  0x080420;
2824         }
2825
2826         /* enable receive descriptor ring */
2827         rxdctl |= IXGBE_RXDCTL_ENABLE;
2828         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2829
2830         ixgbe_rx_desc_queue_enable(adapter, ring);
2831         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2832 }
2833
2834 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2835 {
2836         struct ixgbe_hw *hw = &adapter->hw;
2837         int p;
2838
2839         /* PSRTYPE must be initialized in non 82598 adapters */
2840         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2841                       IXGBE_PSRTYPE_UDPHDR |
2842                       IXGBE_PSRTYPE_IPV4HDR |
2843                       IXGBE_PSRTYPE_L2HDR |
2844                       IXGBE_PSRTYPE_IPV6HDR;
2845
2846         if (hw->mac.type == ixgbe_mac_82598EB)
2847                 return;
2848
2849         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2850                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2851
2852         for (p = 0; p < adapter->num_rx_pools; p++)
2853                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2854                                 psrtype);
2855 }
2856
2857 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2858 {
2859         struct ixgbe_hw *hw = &adapter->hw;
2860         u32 gcr_ext;
2861         u32 vt_reg_bits;
2862         u32 reg_offset, vf_shift;
2863         u32 vmdctl;
2864
2865         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2866                 return;
2867
2868         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2869         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2870         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2871         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2872
2873         vf_shift = adapter->num_vfs % 32;
2874         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2875
2876         /* Enable only the PF's pool for Tx/Rx */
2877         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2878         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2879         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2880         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2881         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2882
2883         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2884         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2885
2886         /*
2887          * Set up VF register offsets for selected VT Mode,
2888          * i.e. 32 or 64 VFs for SR-IOV
2889          */
2890         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2891         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2892         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2893         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2894
2895         /* enable Tx loopback for VF/PF communication */
2896         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2897         /* Enable MAC Anti-Spoofing */
2898         hw->mac.ops.set_mac_anti_spoofing(hw,
2899                                           (adapter->antispoofing_enabled =
2900                                            (adapter->num_vfs != 0)),
2901                                           adapter->num_vfs);
2902 }
2903
2904 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2905 {
2906         struct ixgbe_hw *hw = &adapter->hw;
2907         struct net_device *netdev = adapter->netdev;
2908         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2909         int rx_buf_len;
2910         struct ixgbe_ring *rx_ring;
2911         int i;
2912         u32 mhadd, hlreg0;
2913
2914         /* Decide whether to use packet split mode or not */
2915         /* On by default */
2916         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2917
2918         /* Do not use packet split if we're in SR-IOV Mode */
2919         if (adapter->num_vfs)
2920                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2921
2922         /* Disable packet split due to 82599 erratum #45 */
2923         if (hw->mac.type == ixgbe_mac_82599EB)
2924                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2925
2926         /* Set the RX buffer length according to the mode */
2927         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2928                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2929         } else {
2930                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2931                     (netdev->mtu <= ETH_DATA_LEN))
2932                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2933                 else
2934                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2935         }
2936
2937 #ifdef IXGBE_FCOE
2938         /* adjust max frame to be able to do baby jumbo for FCoE */
2939         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2940             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2941                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2942
2943 #endif /* IXGBE_FCOE */
2944         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2945         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2946                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2947                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2948
2949                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2950         }
2951
2952         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2953         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2954         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2955         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2956
2957         /*
2958          * Setup the HW Rx Head and Tail Descriptor Pointers and
2959          * the Base and Length of the Rx Descriptor Ring
2960          */
2961         for (i = 0; i < adapter->num_rx_queues; i++) {
2962                 rx_ring = adapter->rx_ring[i];
2963                 rx_ring->rx_buf_len = rx_buf_len;
2964
2965                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2966                         set_ring_ps_enabled(rx_ring);
2967                 else
2968                         clear_ring_ps_enabled(rx_ring);
2969
2970                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2971                         set_ring_rsc_enabled(rx_ring);
2972                 else
2973                         clear_ring_rsc_enabled(rx_ring);
2974
2975 #ifdef IXGBE_FCOE
2976                 if (netdev->features & NETIF_F_FCOE_MTU) {
2977                         struct ixgbe_ring_feature *f;
2978                         f = &adapter->ring_feature[RING_F_FCOE];
2979                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2980                                 clear_ring_ps_enabled(rx_ring);
2981                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2982                                         rx_ring->rx_buf_len =
2983                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2984                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2985                                    !ring_is_ps_enabled(rx_ring)) {
2986                                 rx_ring->rx_buf_len =
2987                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2988                         }
2989                 }
2990 #endif /* IXGBE_FCOE */
2991         }
2992 }
2993
2994 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2995 {
2996         struct ixgbe_hw *hw = &adapter->hw;
2997         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2998
2999         switch (hw->mac.type) {
3000         case ixgbe_mac_82598EB:
3001                 /*
3002                  * For VMDq support of different descriptor types or
3003                  * buffer sizes through the use of multiple SRRCTL
3004                  * registers, RDRXCTL.MVMEN must be set to 1
3005                  *
3006                  * also, the manual doesn't mention it clearly but DCA hints
3007                  * will only use queue 0's tags unless this bit is set.  Side
3008                  * effects of setting this bit are only that SRRCTL must be
3009                  * fully programmed [0..15]
3010                  */
3011                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3012                 break;
3013         case ixgbe_mac_82599EB:
3014         case ixgbe_mac_X540:
3015                 /* Disable RSC for ACK packets */
3016                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3017                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3018                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3019                 /* hardware requires some bits to be set by default */
3020                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3021                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3022                 break;
3023         default:
3024                 /* We should do nothing since we don't know this hardware */
3025                 return;
3026         }
3027
3028         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3029 }
3030
3031 /**
3032  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3033  * @adapter: board private structure
3034  *
3035  * Configure the Rx unit of the MAC after a reset.
3036  **/
3037 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3038 {
3039         struct ixgbe_hw *hw = &adapter->hw;
3040         int i;
3041         u32 rxctrl;
3042
3043         /* disable receives while setting up the descriptors */
3044         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3045         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3046
3047         ixgbe_setup_psrtype(adapter);
3048         ixgbe_setup_rdrxctl(adapter);
3049
3050         /* Program registers for the distribution of queues */
3051         ixgbe_setup_mrqc(adapter);
3052
3053         ixgbe_set_uta(adapter);
3054
3055         /* set_rx_buffer_len must be called before ring initialization */
3056         ixgbe_set_rx_buffer_len(adapter);
3057
3058         /*
3059          * Setup the HW Rx Head and Tail Descriptor Pointers and
3060          * the Base and Length of the Rx Descriptor Ring
3061          */
3062         for (i = 0; i < adapter->num_rx_queues; i++)
3063                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3064
3065         /* disable drop enable for 82598 parts */
3066         if (hw->mac.type == ixgbe_mac_82598EB)
3067                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3068
3069         /* enable all receives */
3070         rxctrl |= IXGBE_RXCTRL_RXEN;
3071         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3072 }
3073
3074 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3075 {
3076         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3077         struct ixgbe_hw *hw = &adapter->hw;
3078         int pool_ndx = adapter->num_vfs;
3079
3080         /* add VID to filter table */
3081         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3082         set_bit(vid, adapter->active_vlans);
3083 }
3084
3085 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3086 {
3087         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3088         struct ixgbe_hw *hw = &adapter->hw;
3089         int pool_ndx = adapter->num_vfs;
3090
3091         /* remove VID from filter table */
3092         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3093         clear_bit(vid, adapter->active_vlans);
3094 }
3095
3096 /**
3097  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3098  * @adapter: driver data
3099  */
3100 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3101 {
3102         struct ixgbe_hw *hw = &adapter->hw;
3103         u32 vlnctrl;
3104
3105         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3106         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3107         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3108 }
3109
3110 /**
3111  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3112  * @adapter: driver data
3113  */
3114 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3115 {
3116         struct ixgbe_hw *hw = &adapter->hw;
3117         u32 vlnctrl;
3118
3119         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3120         vlnctrl |= IXGBE_VLNCTRL_VFE;
3121         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3122         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3123 }
3124
3125 /**
3126  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3127  * @adapter: driver data
3128  */
3129 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3130 {
3131         struct ixgbe_hw *hw = &adapter->hw;
3132         u32 vlnctrl;
3133         int i, j;
3134
3135         switch (hw->mac.type) {
3136         case ixgbe_mac_82598EB:
3137                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3138                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3139                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3140                 break;
3141         case ixgbe_mac_82599EB:
3142         case ixgbe_mac_X540:
3143                 for (i = 0; i < adapter->num_rx_queues; i++) {
3144                         j = adapter->rx_ring[i]->reg_idx;
3145                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3146                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3147                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3148                 }
3149                 break;
3150         default:
3151                 break;
3152         }
3153 }
3154
3155 /**
3156  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3157  * @adapter: driver data
3158  */
3159 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3160 {
3161         struct ixgbe_hw *hw = &adapter->hw;
3162         u32 vlnctrl;
3163         int i, j;
3164
3165         switch (hw->mac.type) {
3166         case ixgbe_mac_82598EB:
3167                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3168                 vlnctrl |= IXGBE_VLNCTRL_VME;
3169                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3170                 break;
3171         case ixgbe_mac_82599EB:
3172         case ixgbe_mac_X540:
3173                 for (i = 0; i < adapter->num_rx_queues; i++) {
3174                         j = adapter->rx_ring[i]->reg_idx;
3175                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3176                         vlnctrl |= IXGBE_RXDCTL_VME;
3177                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3178                 }
3179                 break;
3180         default:
3181                 break;
3182         }
3183 }
3184
3185 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3186 {
3187         u16 vid;
3188
3189         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3190
3191         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3192                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3193 }
3194
3195 /**
3196  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3197  * @netdev: network interface device structure
3198  *
3199  * Writes unicast address list to the RAR table.
3200  * Returns: -ENOMEM on failure/insufficient address space
3201  *                0 on no addresses written
3202  *                X on writing X addresses to the RAR table
3203  **/
3204 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3205 {
3206         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3207         struct ixgbe_hw *hw = &adapter->hw;
3208         unsigned int vfn = adapter->num_vfs;
3209         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3210         int count = 0;
3211
3212         /* return ENOMEM indicating insufficient memory for addresses */
3213         if (netdev_uc_count(netdev) > rar_entries)
3214                 return -ENOMEM;
3215
3216         if (!netdev_uc_empty(netdev) && rar_entries) {
3217                 struct netdev_hw_addr *ha;
3218                 /* return error if we do not support writing to RAR table */
3219                 if (!hw->mac.ops.set_rar)
3220                         return -ENOMEM;
3221
3222                 netdev_for_each_uc_addr(ha, netdev) {
3223                         if (!rar_entries)
3224                                 break;
3225                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3226                                             vfn, IXGBE_RAH_AV);
3227                         count++;
3228                 }
3229         }
3230         /* write the addresses in reverse order to avoid write combining */
3231         for (; rar_entries > 0 ; rar_entries--)
3232                 hw->mac.ops.clear_rar(hw, rar_entries);
3233
3234         return count;
3235 }
3236
3237 /**
3238  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3239  * @netdev: network interface device structure
3240  *
3241  * The set_rx_method entry point is called whenever the unicast/multicast
3242  * address list or the network interface flags are updated.  This routine is
3243  * responsible for configuring the hardware for proper unicast, multicast and
3244  * promiscuous mode.
3245  **/
3246 void ixgbe_set_rx_mode(struct net_device *netdev)
3247 {
3248         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3249         struct ixgbe_hw *hw = &adapter->hw;
3250         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3251         int count;
3252
3253         /* Check for Promiscuous and All Multicast modes */
3254
3255         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3256
3257         /* set all bits that we expect to always be set */
3258         fctrl |= IXGBE_FCTRL_BAM;
3259         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3260         fctrl |= IXGBE_FCTRL_PMCF;
3261
3262         /* clear the bits we are changing the status of */
3263         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3264
3265         if (netdev->flags & IFF_PROMISC) {
3266                 hw->addr_ctrl.user_set_promisc = true;
3267                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3268                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3269                 /* don't hardware filter vlans in promisc mode */
3270                 ixgbe_vlan_filter_disable(adapter);
3271         } else {
3272                 if (netdev->flags & IFF_ALLMULTI) {
3273                         fctrl |= IXGBE_FCTRL_MPE;
3274                         vmolr |= IXGBE_VMOLR_MPE;
3275                 } else {
3276                         /*
3277                          * Write addresses to the MTA, if the attempt fails
3278                          * then we should just turn on promiscuous mode so
3279                          * that we can at least receive multicast traffic
3280                          */
3281                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3282                         vmolr |= IXGBE_VMOLR_ROMPE;
3283                 }
3284                 ixgbe_vlan_filter_enable(adapter);
3285                 hw->addr_ctrl.user_set_promisc = false;
3286                 /*
3287                  * Write addresses to available RAR registers, if there is not
3288                  * sufficient space to store all the addresses then enable
3289                  * unicast promiscuous mode
3290                  */
3291                 count = ixgbe_write_uc_addr_list(netdev);
3292                 if (count < 0) {
3293                         fctrl |= IXGBE_FCTRL_UPE;
3294                         vmolr |= IXGBE_VMOLR_ROPE;
3295                 }
3296         }
3297
3298         if (adapter->num_vfs) {
3299                 ixgbe_restore_vf_multicasts(adapter);
3300                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3301                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3302                            IXGBE_VMOLR_ROPE);
3303                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3304         }
3305
3306         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3307
3308         if (netdev->features & NETIF_F_HW_VLAN_RX)
3309                 ixgbe_vlan_strip_enable(adapter);
3310         else
3311                 ixgbe_vlan_strip_disable(adapter);
3312 }
3313
3314 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3315 {
3316         int q_idx;
3317         struct ixgbe_q_vector *q_vector;
3318         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3319
3320         /* legacy and MSI only use one vector */
3321         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3322                 q_vectors = 1;
3323
3324         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3325                 q_vector = adapter->q_vector[q_idx];
3326                 napi_enable(&q_vector->napi);
3327         }
3328 }
3329
3330 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3331 {
3332         int q_idx;
3333         struct ixgbe_q_vector *q_vector;
3334         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3335
3336         /* legacy and MSI only use one vector */
3337         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3338                 q_vectors = 1;
3339
3340         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3341                 q_vector = adapter->q_vector[q_idx];
3342                 napi_disable(&q_vector->napi);
3343         }
3344 }
3345
3346 #ifdef CONFIG_IXGBE_DCB
3347 /*
3348  * ixgbe_configure_dcb - Configure DCB hardware
3349  * @adapter: ixgbe adapter struct
3350  *
3351  * This is called by the driver on open to configure the DCB hardware.
3352  * This is also called by the gennetlink interface when reconfiguring
3353  * the DCB state.
3354  */
3355 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3356 {
3357         struct ixgbe_hw *hw = &adapter->hw;
3358         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3359
3360         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3361                 if (hw->mac.type == ixgbe_mac_82598EB)
3362                         netif_set_gso_max_size(adapter->netdev, 65536);
3363                 return;
3364         }
3365
3366         if (hw->mac.type == ixgbe_mac_82598EB)
3367                 netif_set_gso_max_size(adapter->netdev, 32768);
3368
3369
3370         /* Enable VLAN tag insert/strip */
3371         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3372
3373         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3374
3375         /* reconfigure the hardware */
3376         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3377 #ifdef IXGBE_FCOE
3378                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3379                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3380 #endif
3381                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3382                                                 DCB_TX_CONFIG);
3383                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3384                                                 DCB_RX_CONFIG);
3385                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3386         } else {
3387                 struct net_device *dev = adapter->netdev;
3388
3389                 if (adapter->ixgbe_ieee_ets)
3390                         dev->dcbnl_ops->ieee_setets(dev,
3391                                                     adapter->ixgbe_ieee_ets);
3392                 if (adapter->ixgbe_ieee_pfc)
3393                         dev->dcbnl_ops->ieee_setpfc(dev,
3394                                                     adapter->ixgbe_ieee_pfc);
3395         }
3396
3397         /* Enable RSS Hash per TC */
3398         if (hw->mac.type != ixgbe_mac_82598EB) {
3399                 int i;
3400                 u32 reg = 0;
3401
3402                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3403                         u8 msb = 0;
3404                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3405
3406                         while (cnt >>= 1)
3407                                 msb++;
3408
3409                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3410                 }
3411                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3412         }
3413 }
3414
3415 #endif
3416
3417 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3418 {
3419         int hdrm = 0;
3420         int num_tc = netdev_get_num_tc(adapter->netdev);
3421         struct ixgbe_hw *hw = &adapter->hw;
3422
3423         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3424             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3425                 hdrm = 64 << adapter->fdir_pballoc;
3426
3427         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3428 }
3429
3430 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3431 {
3432         struct ixgbe_hw *hw = &adapter->hw;
3433         struct hlist_node *node, *node2;
3434         struct ixgbe_fdir_filter *filter;
3435
3436         spin_lock(&adapter->fdir_perfect_lock);
3437
3438         if (!hlist_empty(&adapter->fdir_filter_list))
3439                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3440
3441         hlist_for_each_entry_safe(filter, node, node2,
3442                                   &adapter->fdir_filter_list, fdir_node) {
3443                 ixgbe_fdir_write_perfect_filter_82599(hw,
3444                                 &filter->filter,
3445                                 filter->sw_idx,
3446                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3447                                 IXGBE_FDIR_DROP_QUEUE :
3448                                 adapter->rx_ring[filter->action]->reg_idx);
3449         }
3450
3451         spin_unlock(&adapter->fdir_perfect_lock);
3452 }
3453
3454 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3455 {
3456         struct net_device *netdev = adapter->netdev;
3457         struct ixgbe_hw *hw = &adapter->hw;
3458         int i;
3459
3460         ixgbe_configure_pb(adapter);
3461 #ifdef CONFIG_IXGBE_DCB
3462         ixgbe_configure_dcb(adapter);
3463 #endif
3464
3465         ixgbe_set_rx_mode(netdev);
3466         ixgbe_restore_vlan(adapter);
3467
3468 #ifdef IXGBE_FCOE
3469         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3470                 ixgbe_configure_fcoe(adapter);
3471
3472 #endif /* IXGBE_FCOE */
3473         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3474                 for (i = 0; i < adapter->num_tx_queues; i++)
3475                         adapter->tx_ring[i]->atr_sample_rate =
3476                                                        adapter->atr_sample_rate;
3477                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3478         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3479                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3480                                               adapter->fdir_pballoc);
3481                 ixgbe_fdir_filter_restore(adapter);
3482         }
3483         ixgbe_configure_virtualization(adapter);
3484
3485         ixgbe_configure_tx(adapter);
3486         ixgbe_configure_rx(adapter);
3487 }
3488
3489 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3490 {
3491         switch (hw->phy.type) {
3492         case ixgbe_phy_sfp_avago:
3493         case ixgbe_phy_sfp_ftl:
3494         case ixgbe_phy_sfp_intel:
3495         case ixgbe_phy_sfp_unknown:
3496         case ixgbe_phy_sfp_passive_tyco:
3497         case ixgbe_phy_sfp_passive_unknown:
3498         case ixgbe_phy_sfp_active_unknown:
3499         case ixgbe_phy_sfp_ftl_active:
3500                 return true;
3501         default:
3502                 return false;
3503         }
3504 }
3505
3506 /**
3507  * ixgbe_sfp_link_config - set up SFP+ link
3508  * @adapter: pointer to private adapter struct
3509  **/
3510 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3511 {
3512         /*
3513          * We are assuming the worst case scenerio here, and that
3514          * is that an SFP was inserted/removed after the reset
3515          * but before SFP detection was enabled.  As such the best
3516          * solution is to just start searching as soon as we start
3517          */
3518         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3519                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3520
3521         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3522 }
3523
3524 /**
3525  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3526  * @hw: pointer to private hardware struct
3527  *
3528  * Returns 0 on success, negative on failure
3529  **/
3530 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3531 {
3532         u32 autoneg;
3533         bool negotiation, link_up = false;
3534         u32 ret = IXGBE_ERR_LINK_SETUP;
3535
3536         if (hw->mac.ops.check_link)
3537                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3538
3539         if (ret)
3540                 goto link_cfg_out;
3541
3542         autoneg = hw->phy.autoneg_advertised;
3543         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3544                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3545                                                         &negotiation);
3546         if (ret)
3547                 goto link_cfg_out;
3548
3549         if (hw->mac.ops.setup_link)
3550                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3551 link_cfg_out:
3552         return ret;
3553 }
3554
3555 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3556 {
3557         struct ixgbe_hw *hw = &adapter->hw;
3558         u32 gpie = 0;
3559
3560         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3561                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3562                        IXGBE_GPIE_OCD;
3563                 gpie |= IXGBE_GPIE_EIAME;
3564                 /*
3565                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3566                  * this saves a register write for every interrupt
3567                  */
3568                 switch (hw->mac.type) {
3569                 case ixgbe_mac_82598EB:
3570                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3571                         break;
3572                 case ixgbe_mac_82599EB:
3573                 case ixgbe_mac_X540:
3574                 default:
3575                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3576                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3577                         break;
3578                 }
3579         } else {
3580                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3581                  * specifically only auto mask tx and rx interrupts */
3582                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3583         }
3584
3585         /* XXX: to interrupt immediately for EICS writes, enable this */
3586         /* gpie |= IXGBE_GPIE_EIMEN; */
3587
3588         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3589                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3590                 gpie |= IXGBE_GPIE_VTMODE_64;
3591         }
3592
3593         /* Enable fan failure interrupt */
3594         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3595                 gpie |= IXGBE_SDP1_GPIEN;
3596
3597         if (hw->mac.type == ixgbe_mac_82599EB) {
3598                 gpie |= IXGBE_SDP1_GPIEN;
3599                 gpie |= IXGBE_SDP2_GPIEN;
3600         }
3601
3602         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3603 }
3604
3605 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3606 {
3607         struct ixgbe_hw *hw = &adapter->hw;
3608         int err;
3609         u32 ctrl_ext;
3610
3611         ixgbe_get_hw_control(adapter);
3612         ixgbe_setup_gpie(adapter);
3613
3614         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3615                 ixgbe_configure_msix(adapter);
3616         else
3617                 ixgbe_configure_msi_and_legacy(adapter);
3618
3619         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3620         if (hw->mac.ops.enable_tx_laser &&
3621             ((hw->phy.multispeed_fiber) ||
3622              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3623               (hw->mac.type == ixgbe_mac_82599EB))))
3624                 hw->mac.ops.enable_tx_laser(hw);
3625
3626         clear_bit(__IXGBE_DOWN, &adapter->state);
3627         ixgbe_napi_enable_all(adapter);
3628
3629         if (ixgbe_is_sfp(hw)) {
3630                 ixgbe_sfp_link_config(adapter);
3631         } else {
3632                 err = ixgbe_non_sfp_link_config(hw);
3633                 if (err)
3634                         e_err(probe, "link_config FAILED %d\n", err);
3635         }
3636
3637         /* clear any pending interrupts, may auto mask */
3638         IXGBE_READ_REG(hw, IXGBE_EICR);
3639         ixgbe_irq_enable(adapter, true, true);
3640
3641         /*
3642          * If this adapter has a fan, check to see if we had a failure
3643          * before we enabled the interrupt.
3644          */
3645         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3646                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3647                 if (esdp & IXGBE_ESDP_SDP1)
3648                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3649         }
3650
3651         /* enable transmits */
3652         netif_tx_start_all_queues(adapter->netdev);
3653
3654         /* bring the link up in the watchdog, this could race with our first
3655          * link up interrupt but shouldn't be a problem */
3656         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3657         adapter->link_check_timeout = jiffies;
3658         mod_timer(&adapter->service_timer, jiffies);
3659
3660         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3661         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3662         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3663         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3664
3665         return 0;
3666 }
3667
3668 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3669 {
3670         WARN_ON(in_interrupt());
3671         /* put off any impending NetWatchDogTimeout */
3672         adapter->netdev->trans_start = jiffies;
3673
3674         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3675                 usleep_range(1000, 2000);
3676         ixgbe_down(adapter);
3677         /*
3678          * If SR-IOV enabled then wait a bit before bringing the adapter
3679          * back up to give the VFs time to respond to the reset.  The
3680          * two second wait is based upon the watchdog timer cycle in
3681          * the VF driver.
3682          */
3683         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3684                 msleep(2000);
3685         ixgbe_up(adapter);
3686         clear_bit(__IXGBE_RESETTING, &adapter->state);
3687 }
3688
3689 int ixgbe_up(struct ixgbe_adapter *adapter)
3690 {
3691         /* hardware has been reset, we need to reload some things */
3692         ixgbe_configure(adapter);
3693
3694         return ixgbe_up_complete(adapter);
3695 }
3696
3697 void ixgbe_reset(struct ixgbe_adapter *adapter)
3698 {
3699         struct ixgbe_hw *hw = &adapter->hw;
3700         int err;
3701
3702         /* lock SFP init bit to prevent race conditions with the watchdog */
3703         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3704                 usleep_range(1000, 2000);
3705
3706         /* clear all SFP and link config related flags while holding SFP_INIT */
3707         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3708                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3709         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3710
3711         err = hw->mac.ops.init_hw(hw);
3712         switch (err) {
3713         case 0:
3714         case IXGBE_ERR_SFP_NOT_PRESENT:
3715         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3716                 break;
3717         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3718                 e_dev_err("master disable timed out\n");
3719                 break;
3720         case IXGBE_ERR_EEPROM_VERSION:
3721                 /* We are running on a pre-production device, log a warning */
3722                 e_dev_warn("This device is a pre-production adapter/LOM. "
3723                            "Please be aware there may be issuesassociated with "
3724                            "your hardware.  If you are experiencing problems "
3725                            "please contact your Intel or hardware "
3726                            "representative who provided you with this "
3727                            "hardware.\n");
3728                 break;
3729         default:
3730                 e_dev_err("Hardware Error: %d\n", err);
3731         }
3732
3733         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3734
3735         /* reprogram the RAR[0] in case user changed it. */
3736         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3737                             IXGBE_RAH_AV);
3738 }
3739
3740 /**
3741  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3742  * @rx_ring: ring to free buffers from
3743  **/
3744 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3745 {
3746         struct device *dev = rx_ring->dev;
3747         unsigned long size;
3748         u16 i;
3749
3750         /* ring already cleared, nothing to do */
3751         if (!rx_ring->rx_buffer_info)
3752                 return;
3753
3754         /* Free all the Rx ring sk_buffs */
3755         for (i = 0; i < rx_ring->count; i++) {
3756                 struct ixgbe_rx_buffer *rx_buffer_info;
3757
3758                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3759                 if (rx_buffer_info->dma) {
3760                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3761                                          rx_ring->rx_buf_len,
3762                                          DMA_FROM_DEVICE);
3763                         rx_buffer_info->dma = 0;
3764                 }
3765                 if (rx_buffer_info->skb) {
3766                         struct sk_buff *skb = rx_buffer_info->skb;
3767                         rx_buffer_info->skb = NULL;
3768                         do {
3769                                 struct sk_buff *this = skb;
3770                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3771                                         dma_unmap_single(dev,
3772                                                          IXGBE_RSC_CB(this)->dma,
3773                                                          rx_ring->rx_buf_len,
3774                                                          DMA_FROM_DEVICE);
3775                                         IXGBE_RSC_CB(this)->dma = 0;
3776                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3777                                 }
3778                                 skb = skb->prev;
3779                                 dev_kfree_skb(this);
3780                         } while (skb);
3781                 }
3782                 if (!rx_buffer_info->page)
3783                         continue;
3784                 if (rx_buffer_info->page_dma) {
3785                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3786                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3787                         rx_buffer_info->page_dma = 0;
3788                 }
3789                 put_page(rx_buffer_info->page);
3790                 rx_buffer_info->page = NULL;
3791                 rx_buffer_info->page_offset = 0;
3792         }
3793
3794         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3795         memset(rx_ring->rx_buffer_info, 0, size);
3796
3797         /* Zero out the descriptor ring */
3798         memset(rx_ring->desc, 0, rx_ring->size);
3799
3800         rx_ring->next_to_clean = 0;
3801         rx_ring->next_to_use = 0;
3802 }
3803
3804 /**
3805  * ixgbe_clean_tx_ring - Free Tx Buffers
3806  * @tx_ring: ring to be cleaned
3807  **/
3808 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3809 {
3810         struct ixgbe_tx_buffer *tx_buffer_info;
3811         unsigned long size;
3812         u16 i;
3813
3814         /* ring already cleared, nothing to do */
3815         if (!tx_ring->tx_buffer_info)
3816                 return;
3817
3818         /* Free all the Tx ring sk_buffs */
3819         for (i = 0; i < tx_ring->count; i++) {
3820                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3821                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3822         }
3823
3824         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3825         memset(tx_ring->tx_buffer_info, 0, size);
3826
3827         /* Zero out the descriptor ring */
3828         memset(tx_ring->desc, 0, tx_ring->size);
3829
3830         tx_ring->next_to_use = 0;
3831         tx_ring->next_to_clean = 0;
3832 }
3833
3834 /**
3835  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3836  * @adapter: board private structure
3837  **/
3838 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3839 {
3840         int i;
3841
3842         for (i = 0; i < adapter->num_rx_queues; i++)
3843                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3844 }
3845
3846 /**
3847  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3848  * @adapter: board private structure
3849  **/
3850 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3851 {
3852         int i;
3853
3854         for (i = 0; i < adapter->num_tx_queues; i++)
3855                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3856 }
3857
3858 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3859 {
3860         struct hlist_node *node, *node2;
3861         struct ixgbe_fdir_filter *filter;
3862
3863         spin_lock(&adapter->fdir_perfect_lock);
3864
3865         hlist_for_each_entry_safe(filter, node, node2,
3866                                   &adapter->fdir_filter_list, fdir_node) {
3867                 hlist_del(&filter->fdir_node);
3868                 kfree(filter);
3869         }
3870         adapter->fdir_filter_count = 0;
3871
3872         spin_unlock(&adapter->fdir_perfect_lock);
3873 }
3874
3875 void ixgbe_down(struct ixgbe_adapter *adapter)
3876 {
3877         struct net_device *netdev = adapter->netdev;
3878         struct ixgbe_hw *hw = &adapter->hw;
3879         u32 rxctrl;
3880         int i;
3881
3882         /* signal that we are down to the interrupt handler */
3883         set_bit(__IXGBE_DOWN, &adapter->state);
3884
3885         /* disable receives */
3886         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3887         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3888
3889         /* disable all enabled rx queues */
3890         for (i = 0; i < adapter->num_rx_queues; i++)
3891                 /* this call also flushes the previous write */
3892                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3893
3894         usleep_range(10000, 20000);
3895
3896         netif_tx_stop_all_queues(netdev);
3897
3898         /* call carrier off first to avoid false dev_watchdog timeouts */
3899         netif_carrier_off(netdev);
3900         netif_tx_disable(netdev);
3901
3902         ixgbe_irq_disable(adapter);
3903
3904         ixgbe_napi_disable_all(adapter);
3905
3906         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3907                              IXGBE_FLAG2_RESET_REQUESTED);
3908         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3909
3910         del_timer_sync(&adapter->service_timer);
3911
3912         /* disable receive for all VFs and wait one second */
3913         if (adapter->num_vfs) {
3914                 /* ping all the active vfs to let them know we are going down */
3915                 ixgbe_ping_all_vfs(adapter);
3916
3917                 /* Disable all VFTE/VFRE TX/RX */
3918                 ixgbe_disable_tx_rx(adapter);
3919
3920                 /* Mark all the VFs as inactive */
3921                 for (i = 0 ; i < adapter->num_vfs; i++)
3922                         adapter->vfinfo[i].clear_to_send = 0;
3923         }
3924
3925         /* disable transmits in the hardware now that interrupts are off */
3926         for (i = 0; i < adapter->num_tx_queues; i++) {
3927                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3928                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3929         }
3930
3931         /* Disable the Tx DMA engine on 82599 and X540 */
3932         switch (hw->mac.type) {
3933         case ixgbe_mac_82599EB:
3934         case ixgbe_mac_X540:
3935                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3936                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3937                                  ~IXGBE_DMATXCTL_TE));
3938                 break;
3939         default:
3940                 break;
3941         }
3942
3943         if (!pci_channel_offline(adapter->pdev))
3944                 ixgbe_reset(adapter);
3945
3946         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3947         if (hw->mac.ops.disable_tx_laser &&
3948             ((hw->phy.multispeed_fiber) ||
3949              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3950               (hw->mac.type == ixgbe_mac_82599EB))))
3951                 hw->mac.ops.disable_tx_laser(hw);
3952
3953         ixgbe_clean_all_tx_rings(adapter);
3954         ixgbe_clean_all_rx_rings(adapter);
3955
3956 #ifdef CONFIG_IXGBE_DCA
3957         /* since we reset the hardware DCA settings were cleared */
3958         ixgbe_setup_dca(adapter);
3959 #endif
3960 }
3961
3962 /**
3963  * ixgbe_poll - NAPI Rx polling callback
3964  * @napi: structure for representing this polling device
3965  * @budget: how many packets driver is allowed to clean
3966  *
3967  * This function is used for legacy and MSI, NAPI mode
3968  **/
3969 static int ixgbe_poll(struct napi_struct *napi, int budget)
3970 {
3971         struct ixgbe_q_vector *q_vector =
3972                                 container_of(napi, struct ixgbe_q_vector, napi);
3973         struct ixgbe_adapter *adapter = q_vector->adapter;
3974         struct ixgbe_ring *ring;
3975         int per_ring_budget;
3976         bool clean_complete = true;
3977
3978 #ifdef CONFIG_IXGBE_DCA
3979         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3980                 ixgbe_update_dca(q_vector);
3981 #endif
3982
3983         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3984                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3985
3986         /* attempt to distribute budget to each queue fairly, but don't allow
3987          * the budget to go below 1 because we'll exit polling */
3988         if (q_vector->rx.count > 1)
3989                 per_ring_budget = max(budget/q_vector->rx.count, 1);
3990         else
3991                 per_ring_budget = budget;
3992
3993         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3994                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3995                                                      per_ring_budget);
3996
3997         /* If all work not completed, return budget and keep polling */
3998         if (!clean_complete)
3999                 return budget;
4000
4001         /* all work done, exit the polling mode */
4002         napi_complete(napi);
4003         if (adapter->rx_itr_setting & 1)
4004                 ixgbe_set_itr(q_vector);
4005         if (!test_bit(__IXGBE_DOWN, &adapter->state))
4006                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4007
4008         return 0;
4009 }
4010
4011 /**
4012  * ixgbe_tx_timeout - Respond to a Tx Hang
4013  * @netdev: network interface device structure
4014  **/
4015 static void ixgbe_tx_timeout(struct net_device *netdev)
4016 {
4017         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4018
4019         /* Do the reset outside of interrupt context */
4020         ixgbe_tx_timeout_reset(adapter);
4021 }
4022
4023 /**
4024  * ixgbe_set_rss_queues: Allocate queues for RSS
4025  * @adapter: board private structure to initialize
4026  *
4027  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4028  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4029  *
4030  **/
4031 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4032 {
4033         bool ret = false;
4034         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4035
4036         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4037                 f->mask = 0xF;
4038                 adapter->num_rx_queues = f->indices;
4039                 adapter->num_tx_queues = f->indices;
4040                 ret = true;
4041         } else {
4042                 ret = false;
4043         }
4044
4045         return ret;
4046 }
4047
4048 /**
4049  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4050  * @adapter: board private structure to initialize
4051  *
4052  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4053  * to the original CPU that initiated the Tx session.  This runs in addition
4054  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4055  * Rx load across CPUs using RSS.
4056  *
4057  **/
4058 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4059 {
4060         bool ret = false;
4061         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4062
4063         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4064         f_fdir->mask = 0;
4065
4066         /* Flow Director must have RSS enabled */
4067         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4068             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4069                 adapter->num_tx_queues = f_fdir->indices;
4070                 adapter->num_rx_queues = f_fdir->indices;
4071                 ret = true;
4072         } else {
4073                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4074         }
4075         return ret;
4076 }
4077
4078 #ifdef IXGBE_FCOE
4079 /**
4080  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4081  * @adapter: board private structure to initialize
4082  *
4083  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4084  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4085  * rx queues out of the max number of rx queues, instead, it is used as the
4086  * index of the first rx queue used by FCoE.
4087  *
4088  **/
4089 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4090 {
4091         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4092
4093         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4094                 return false;
4095
4096         f->indices = min((int)num_online_cpus(), f->indices);
4097
4098         adapter->num_rx_queues = 1;
4099         adapter->num_tx_queues = 1;
4100
4101         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4102                 e_info(probe, "FCoE enabled with RSS\n");
4103                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4104                         ixgbe_set_fdir_queues(adapter);
4105                 else
4106                         ixgbe_set_rss_queues(adapter);
4107         }
4108
4109         /* adding FCoE rx rings to the end */
4110         f->mask = adapter->num_rx_queues;
4111         adapter->num_rx_queues += f->indices;
4112         adapter->num_tx_queues += f->indices;
4113
4114         return true;
4115 }
4116 #endif /* IXGBE_FCOE */
4117
4118 /* Artificial max queue cap per traffic class in DCB mode */
4119 #define DCB_QUEUE_CAP 8
4120
4121 #ifdef CONFIG_IXGBE_DCB
4122 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4123 {
4124         int per_tc_q, q, i, offset = 0;
4125         struct net_device *dev = adapter->netdev;
4126         int tcs = netdev_get_num_tc(dev);
4127
4128         if (!tcs)
4129                 return false;
4130
4131         /* Map queue offset and counts onto allocated tx queues */
4132         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4133         q = min((int)num_online_cpus(), per_tc_q);
4134
4135         for (i = 0; i < tcs; i++) {
4136                 netdev_set_prio_tc_map(dev, i, i);
4137                 netdev_set_tc_queue(dev, i, q, offset);
4138                 offset += q;
4139         }
4140
4141         adapter->num_tx_queues = q * tcs;
4142         adapter->num_rx_queues = q * tcs;
4143
4144 #ifdef IXGBE_FCOE
4145         /* FCoE enabled queues require special configuration indexed
4146          * by feature specific indices and mask. Here we map FCoE
4147          * indices onto the DCB queue pairs allowing FCoE to own
4148          * configuration later.
4149          */
4150         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4151                 int tc;
4152                 struct ixgbe_ring_feature *f =
4153                                         &adapter->ring_feature[RING_F_FCOE];
4154
4155                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4156                 f->indices = dev->tc_to_txq[tc].count;
4157                 f->mask = dev->tc_to_txq[tc].offset;
4158         }
4159 #endif
4160
4161         return true;
4162 }
4163 #endif
4164
4165 /**
4166  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4167  * @adapter: board private structure to initialize
4168  *
4169  * IOV doesn't actually use anything, so just NAK the
4170  * request for now and let the other queue routines
4171  * figure out what to do.
4172  */
4173 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4174 {
4175         return false;
4176 }
4177
4178 /*
4179  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4180  * @adapter: board private structure to initialize
4181  *
4182  * This is the top level queue allocation routine.  The order here is very
4183  * important, starting with the "most" number of features turned on at once,
4184  * and ending with the smallest set of features.  This way large combinations
4185  * can be allocated if they're turned on, and smaller combinations are the
4186  * fallthrough conditions.
4187  *
4188  **/
4189 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4190 {
4191         /* Start with base case */
4192         adapter->num_rx_queues = 1;
4193         adapter->num_tx_queues = 1;
4194         adapter->num_rx_pools = adapter->num_rx_queues;
4195         adapter->num_rx_queues_per_pool = 1;
4196
4197         if (ixgbe_set_sriov_queues(adapter))
4198                 goto done;
4199
4200 #ifdef CONFIG_IXGBE_DCB
4201         if (ixgbe_set_dcb_queues(adapter))
4202                 goto done;
4203
4204 #endif
4205 #ifdef IXGBE_FCOE
4206         if (ixgbe_set_fcoe_queues(adapter))
4207                 goto done;
4208
4209 #endif /* IXGBE_FCOE */
4210         if (ixgbe_set_fdir_queues(adapter))
4211                 goto done;
4212
4213         if (ixgbe_set_rss_queues(adapter))
4214                 goto done;
4215
4216         /* fallback to base case */
4217         adapter->num_rx_queues = 1;
4218         adapter->num_tx_queues = 1;
4219
4220 done:
4221         /* Notify the stack of the (possibly) reduced queue counts. */
4222         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4223         return netif_set_real_num_rx_queues(adapter->netdev,
4224                                             adapter->num_rx_queues);
4225 }
4226
4227 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4228                                        int vectors)
4229 {
4230         int err, vector_threshold;
4231
4232         /* We'll want at least 3 (vector_threshold):
4233          * 1) TxQ[0] Cleanup
4234          * 2) RxQ[0] Cleanup
4235          * 3) Other (Link Status Change, etc.)
4236          * 4) TCP Timer (optional)
4237          */
4238         vector_threshold = MIN_MSIX_COUNT;
4239
4240         /* The more we get, the more we will assign to Tx/Rx Cleanup
4241          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4242          * Right now, we simply care about how many we'll get; we'll
4243          * set them up later while requesting irq's.
4244          */
4245         while (vectors >= vector_threshold) {
4246                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4247                                       vectors);
4248                 if (!err) /* Success in acquiring all requested vectors. */
4249                         break;
4250                 else if (err < 0)
4251                         vectors = 0; /* Nasty failure, quit now */
4252                 else /* err == number of vectors we should try again with */
4253                         vectors = err;
4254         }
4255
4256         if (vectors < vector_threshold) {
4257                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4258                  * This just means we'll go with either a single MSI
4259                  * vector or fall back to legacy interrupts.
4260                  */
4261                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4262                              "Unable to allocate MSI-X interrupts\n");
4263                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4264                 kfree(adapter->msix_entries);
4265                 adapter->msix_entries = NULL;
4266         } else {
4267                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4268                 /*
4269                  * Adjust for only the vectors we'll use, which is minimum
4270                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4271                  * vectors we were allocated.
4272                  */
4273                 adapter->num_msix_vectors = min(vectors,
4274                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4275         }
4276 }
4277
4278 /**
4279  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4280  * @adapter: board private structure to initialize
4281  *
4282  * Cache the descriptor ring offsets for RSS to the assigned rings.
4283  *
4284  **/
4285 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4286 {
4287         int i;
4288
4289         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4290                 return false;
4291
4292         for (i = 0; i < adapter->num_rx_queues; i++)
4293                 adapter->rx_ring[i]->reg_idx = i;
4294         for (i = 0; i < adapter->num_tx_queues; i++)
4295                 adapter->tx_ring[i]->reg_idx = i;
4296
4297         return true;
4298 }
4299
4300 #ifdef CONFIG_IXGBE_DCB
4301
4302 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4303 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4304                                     unsigned int *tx, unsigned int *rx)
4305 {
4306         struct net_device *dev = adapter->netdev;
4307         struct ixgbe_hw *hw = &adapter->hw;
4308         u8 num_tcs = netdev_get_num_tc(dev);
4309
4310         *tx = 0;
4311         *rx = 0;
4312
4313         switch (hw->mac.type) {
4314         case ixgbe_mac_82598EB:
4315                 *tx = tc << 2;
4316                 *rx = tc << 3;
4317                 break;
4318         case ixgbe_mac_82599EB:
4319         case ixgbe_mac_X540:
4320                 if (num_tcs > 4) {
4321                         if (tc < 3) {
4322                                 *tx = tc << 5;
4323                                 *rx = tc << 4;
4324                         } else if (tc <  5) {
4325                                 *tx = ((tc + 2) << 4);
4326                                 *rx = tc << 4;
4327                         } else if (tc < num_tcs) {
4328                                 *tx = ((tc + 8) << 3);
4329                                 *rx = tc << 4;
4330                         }
4331                 } else {
4332                         *rx =  tc << 5;
4333                         switch (tc) {
4334                         case 0:
4335                                 *tx =  0;
4336                                 break;
4337                         case 1:
4338                                 *tx = 64;
4339                                 break;
4340                         case 2:
4341                                 *tx = 96;
4342                                 break;
4343                         case 3:
4344                                 *tx = 112;
4345                                 break;
4346                         default:
4347                                 break;
4348                         }
4349                 }
4350                 break;
4351         default:
4352                 break;
4353         }
4354 }
4355
4356 /**
4357  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4358  * @adapter: board private structure to initialize
4359  *
4360  * Cache the descriptor ring offsets for DCB to the assigned rings.
4361  *
4362  **/
4363 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4364 {
4365         struct net_device *dev = adapter->netdev;
4366         int i, j, k;
4367         u8 num_tcs = netdev_get_num_tc(dev);
4368
4369         if (!num_tcs)
4370                 return false;
4371
4372         for (i = 0, k = 0; i < num_tcs; i++) {
4373                 unsigned int tx_s, rx_s;
4374                 u16 count = dev->tc_to_txq[i].count;
4375
4376                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4377                 for (j = 0; j < count; j++, k++) {
4378                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4379                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4380                         adapter->tx_ring[k]->dcb_tc = i;
4381                         adapter->rx_ring[k]->dcb_tc = i;
4382                 }
4383         }
4384
4385         return true;
4386 }
4387 #endif
4388
4389 /**
4390  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4391  * @adapter: board private structure to initialize
4392  *
4393  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4394  *
4395  **/
4396 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4397 {
4398         int i;
4399         bool ret = false;
4400
4401         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4402             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4403                 for (i = 0; i < adapter->num_rx_queues; i++)
4404                         adapter->rx_ring[i]->reg_idx = i;
4405                 for (i = 0; i < adapter->num_tx_queues; i++)
4406                         adapter->tx_ring[i]->reg_idx = i;
4407                 ret = true;
4408         }
4409
4410         return ret;
4411 }
4412
4413 #ifdef IXGBE_FCOE
4414 /**
4415  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4416  * @adapter: board private structure to initialize
4417  *
4418  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4419  *
4420  */
4421 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4422 {
4423         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4424         int i;
4425         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4426
4427         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4428                 return false;
4429
4430         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4431                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4432                         ixgbe_cache_ring_fdir(adapter);
4433                 else
4434                         ixgbe_cache_ring_rss(adapter);
4435
4436                 fcoe_rx_i = f->mask;
4437                 fcoe_tx_i = f->mask;
4438         }
4439         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4440                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4441                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4442         }
4443         return true;
4444 }
4445
4446 #endif /* IXGBE_FCOE */
4447 /**
4448  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4449  * @adapter: board private structure to initialize
4450  *
4451  * SR-IOV doesn't use any descriptor rings but changes the default if
4452  * no other mapping is used.
4453  *
4454  */
4455 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4456 {
4457         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4458         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4459         if (adapter->num_vfs)
4460                 return true;
4461         else
4462                 return false;
4463 }
4464
4465 /**
4466  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4467  * @adapter: board private structure to initialize
4468  *
4469  * Once we know the feature-set enabled for the device, we'll cache
4470  * the register offset the descriptor ring is assigned to.
4471  *
4472  * Note, the order the various feature calls is important.  It must start with
4473  * the "most" features enabled at the same time, then trickle down to the
4474  * least amount of features turned on at once.
4475  **/
4476 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4477 {
4478         /* start with default case */
4479         adapter->rx_ring[0]->reg_idx = 0;
4480         adapter->tx_ring[0]->reg_idx = 0;
4481
4482         if (ixgbe_cache_ring_sriov(adapter))
4483                 return;
4484
4485 #ifdef CONFIG_IXGBE_DCB
4486         if (ixgbe_cache_ring_dcb(adapter))
4487                 return;
4488 #endif
4489
4490 #ifdef IXGBE_FCOE
4491         if (ixgbe_cache_ring_fcoe(adapter))
4492                 return;
4493 #endif /* IXGBE_FCOE */
4494
4495         if (ixgbe_cache_ring_fdir(adapter))
4496                 return;
4497
4498         if (ixgbe_cache_ring_rss(adapter))
4499                 return;
4500 }
4501
4502 /**
4503  * ixgbe_alloc_queues - Allocate memory for all rings
4504  * @adapter: board private structure to initialize
4505  *
4506  * We allocate one ring per queue at run-time since we don't know the
4507  * number of queues at compile-time.  The polling_netdev array is
4508  * intended for Multiqueue, but should work fine with a single queue.
4509  **/
4510 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4511 {
4512         int rx = 0, tx = 0, nid = adapter->node;
4513
4514         if (nid < 0 || !node_online(nid))
4515                 nid = first_online_node;
4516
4517         for (; tx < adapter->num_tx_queues; tx++) {
4518                 struct ixgbe_ring *ring;
4519
4520                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4521                 if (!ring)
4522                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4523                 if (!ring)
4524                         goto err_allocation;
4525                 ring->count = adapter->tx_ring_count;
4526                 ring->queue_index = tx;
4527                 ring->numa_node = nid;
4528                 ring->dev = &adapter->pdev->dev;
4529                 ring->netdev = adapter->netdev;
4530
4531                 adapter->tx_ring[tx] = ring;
4532         }
4533
4534         for (; rx < adapter->num_rx_queues; rx++) {
4535                 struct ixgbe_ring *ring;
4536
4537                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4538                 if (!ring)
4539                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4540                 if (!ring)
4541                         goto err_allocation;
4542                 ring->count = adapter->rx_ring_count;
4543                 ring->queue_index = rx;
4544                 ring->numa_node = nid;
4545                 ring->dev = &adapter->pdev->dev;
4546                 ring->netdev = adapter->netdev;
4547
4548                 adapter->rx_ring[rx] = ring;
4549         }
4550
4551         ixgbe_cache_ring_register(adapter);
4552
4553         return 0;
4554
4555 err_allocation:
4556         while (tx)
4557                 kfree(adapter->tx_ring[--tx]);
4558
4559         while (rx)
4560                 kfree(adapter->rx_ring[--rx]);
4561         return -ENOMEM;
4562 }
4563
4564 /**
4565  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4566  * @adapter: board private structure to initialize
4567  *
4568  * Attempt to configure the interrupts using the best available
4569  * capabilities of the hardware and the kernel.
4570  **/
4571 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4572 {
4573         struct ixgbe_hw *hw = &adapter->hw;
4574         int err = 0;
4575         int vector, v_budget;
4576
4577         /*
4578          * It's easy to be greedy for MSI-X vectors, but it really
4579          * doesn't do us much good if we have a lot more vectors
4580          * than CPU's.  So let's be conservative and only ask for
4581          * (roughly) the same number of vectors as there are CPU's.
4582          */
4583         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4584                        (int)num_online_cpus()) + NON_Q_VECTORS;
4585
4586         /*
4587          * At the same time, hardware can only support a maximum of
4588          * hw.mac->max_msix_vectors vectors.  With features
4589          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4590          * descriptor queues supported by our device.  Thus, we cap it off in
4591          * those rare cases where the cpu count also exceeds our vector limit.
4592          */
4593         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4594
4595         /* A failure in MSI-X entry allocation isn't fatal, but it does
4596          * mean we disable MSI-X capabilities of the adapter. */
4597         adapter->msix_entries = kcalloc(v_budget,
4598                                         sizeof(struct msix_entry), GFP_KERNEL);
4599         if (adapter->msix_entries) {
4600                 for (vector = 0; vector < v_budget; vector++)
4601                         adapter->msix_entries[vector].entry = vector;
4602
4603                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4604
4605                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4606                         goto out;
4607         }
4608
4609         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4610         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4611         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4612                 e_err(probe,
4613                       "ATR is not supported while multiple "
4614                       "queues are disabled.  Disabling Flow Director\n");
4615         }
4616         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4617         adapter->atr_sample_rate = 0;
4618         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4619                 ixgbe_disable_sriov(adapter);
4620
4621         err = ixgbe_set_num_queues(adapter);
4622         if (err)
4623                 return err;
4624
4625         err = pci_enable_msi(adapter->pdev);
4626         if (!err) {
4627                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4628         } else {
4629                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4630                              "Unable to allocate MSI interrupt, "
4631                              "falling back to legacy.  Error: %d\n", err);
4632                 /* reset err */
4633                 err = 0;
4634         }
4635
4636 out:
4637         return err;
4638 }
4639
4640 /**
4641  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4642  * @adapter: board private structure to initialize
4643  *
4644  * We allocate one q_vector per queue interrupt.  If allocation fails we
4645  * return -ENOMEM.
4646  **/
4647 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4648 {
4649         int v_idx, num_q_vectors;
4650         struct ixgbe_q_vector *q_vector;
4651
4652         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4653                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4654         else
4655                 num_q_vectors = 1;
4656
4657         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4658                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4659                                         GFP_KERNEL, adapter->node);
4660                 if (!q_vector)
4661                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4662                                            GFP_KERNEL);
4663                 if (!q_vector)
4664                         goto err_out;
4665
4666                 q_vector->adapter = adapter;
4667                 q_vector->v_idx = v_idx;
4668
4669                 /* Allocate the affinity_hint cpumask, configure the mask */
4670                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4671                         goto err_out;
4672                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4673
4674                 if (q_vector->tx.count && !q_vector->rx.count)
4675                         q_vector->eitr = adapter->tx_eitr_param;
4676                 else
4677                         q_vector->eitr = adapter->rx_eitr_param;
4678
4679                 netif_napi_add(adapter->netdev, &q_vector->napi,
4680                                ixgbe_poll, 64);
4681                 adapter->q_vector[v_idx] = q_vector;
4682         }
4683
4684         return 0;
4685
4686 err_out:
4687         while (v_idx) {
4688                 v_idx--;
4689                 q_vector = adapter->q_vector[v_idx];
4690                 netif_napi_del(&q_vector->napi);
4691                 free_cpumask_var(q_vector->affinity_mask);
4692                 kfree(q_vector);
4693                 adapter->q_vector[v_idx] = NULL;
4694         }
4695         return -ENOMEM;
4696 }
4697
4698 /**
4699  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4700  * @adapter: board private structure to initialize
4701  *
4702  * This function frees the memory allocated to the q_vectors.  In addition if
4703  * NAPI is enabled it will delete any references to the NAPI struct prior
4704  * to freeing the q_vector.
4705  **/
4706 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4707 {
4708         int v_idx, num_q_vectors;
4709
4710         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4711                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4712         else
4713                 num_q_vectors = 1;
4714
4715         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4716                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4717                 adapter->q_vector[v_idx] = NULL;
4718                 netif_napi_del(&q_vector->napi);
4719                 free_cpumask_var(q_vector->affinity_mask);
4720                 kfree(q_vector);
4721         }
4722 }
4723
4724 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4725 {
4726         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4727                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4728                 pci_disable_msix(adapter->pdev);
4729                 kfree(adapter->msix_entries);
4730                 adapter->msix_entries = NULL;
4731         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4732                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4733                 pci_disable_msi(adapter->pdev);
4734         }
4735 }
4736
4737 /**
4738  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4739  * @adapter: board private structure to initialize
4740  *
4741  * We determine which interrupt scheme to use based on...
4742  * - Kernel support (MSI, MSI-X)
4743  *   - which can be user-defined (via MODULE_PARAM)
4744  * - Hardware queue count (num_*_queues)
4745  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4746  **/
4747 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4748 {
4749         int err;
4750
4751         /* Number of supported queues */
4752         err = ixgbe_set_num_queues(adapter);
4753         if (err)
4754                 return err;
4755
4756         err = ixgbe_set_interrupt_capability(adapter);
4757         if (err) {
4758                 e_dev_err("Unable to setup interrupt capabilities\n");
4759                 goto err_set_interrupt;
4760         }
4761
4762         err = ixgbe_alloc_q_vectors(adapter);
4763         if (err) {
4764                 e_dev_err("Unable to allocate memory for queue vectors\n");
4765                 goto err_alloc_q_vectors;
4766         }
4767
4768         err = ixgbe_alloc_queues(adapter);
4769         if (err) {
4770                 e_dev_err("Unable to allocate memory for queues\n");
4771                 goto err_alloc_queues;
4772         }
4773
4774         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4775                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4776                    adapter->num_rx_queues, adapter->num_tx_queues);
4777
4778         set_bit(__IXGBE_DOWN, &adapter->state);
4779
4780         return 0;
4781
4782 err_alloc_queues:
4783         ixgbe_free_q_vectors(adapter);
4784 err_alloc_q_vectors:
4785         ixgbe_reset_interrupt_capability(adapter);
4786 err_set_interrupt:
4787         return err;
4788 }
4789
4790 /**
4791  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4792  * @adapter: board private structure to clear interrupt scheme on
4793  *
4794  * We go through and clear interrupt specific resources and reset the structure
4795  * to pre-load conditions
4796  **/
4797 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4798 {
4799         int i;
4800
4801         for (i = 0; i < adapter->num_tx_queues; i++) {
4802                 kfree(adapter->tx_ring[i]);
4803                 adapter->tx_ring[i] = NULL;
4804         }
4805         for (i = 0; i < adapter->num_rx_queues; i++) {
4806                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4807
4808                 /* ixgbe_get_stats64() might access this ring, we must wait
4809                  * a grace period before freeing it.
4810                  */
4811                 kfree_rcu(ring, rcu);
4812                 adapter->rx_ring[i] = NULL;
4813         }
4814
4815         adapter->num_tx_queues = 0;
4816         adapter->num_rx_queues = 0;
4817
4818         ixgbe_free_q_vectors(adapter);
4819         ixgbe_reset_interrupt_capability(adapter);
4820 }
4821
4822 /**
4823  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4824  * @adapter: board private structure to initialize
4825  *
4826  * ixgbe_sw_init initializes the Adapter private data structure.
4827  * Fields are initialized based on PCI device information and
4828  * OS network device settings (MTU size).
4829  **/
4830 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4831 {
4832         struct ixgbe_hw *hw = &adapter->hw;
4833         struct pci_dev *pdev = adapter->pdev;
4834         struct net_device *dev = adapter->netdev;
4835         unsigned int rss;
4836 #ifdef CONFIG_IXGBE_DCB
4837         int j;
4838         struct tc_configuration *tc;
4839 #endif
4840         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4841
4842         /* PCI config space info */
4843
4844         hw->vendor_id = pdev->vendor;
4845         hw->device_id = pdev->device;
4846         hw->revision_id = pdev->revision;
4847         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4848         hw->subsystem_device_id = pdev->subsystem_device;
4849
4850         /* Set capability flags */
4851         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4852         adapter->ring_feature[RING_F_RSS].indices = rss;
4853         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4854         switch (hw->mac.type) {
4855         case ixgbe_mac_82598EB:
4856                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4857                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4858                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4859                 break;
4860         case ixgbe_mac_82599EB:
4861         case ixgbe_mac_X540:
4862                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4863                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4864                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4865                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4866                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4867                 /* Flow Director hash filters enabled */
4868                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4869                 adapter->atr_sample_rate = 20;
4870                 adapter->ring_feature[RING_F_FDIR].indices =
4871                                                          IXGBE_MAX_FDIR_INDICES;
4872                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4873 #ifdef IXGBE_FCOE
4874                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4875                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4876                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4877 #ifdef CONFIG_IXGBE_DCB
4878                 /* Default traffic class to use for FCoE */
4879                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4880 #endif
4881 #endif /* IXGBE_FCOE */
4882                 break;
4883         default:
4884                 break;
4885         }
4886
4887         /* n-tuple support exists, always init our spinlock */
4888         spin_lock_init(&adapter->fdir_perfect_lock);
4889
4890 #ifdef CONFIG_IXGBE_DCB
4891         /* Configure DCB traffic classes */
4892         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4893                 tc = &adapter->dcb_cfg.tc_config[j];
4894                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4895                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4896                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4897                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4898                 tc->dcb_pfc = pfc_disabled;
4899         }
4900         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4901         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4902         adapter->dcb_cfg.pfc_mode_enable = false;
4903         adapter->dcb_set_bitmap = 0x00;
4904         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4905         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4906                            MAX_TRAFFIC_CLASS);
4907
4908 #endif
4909
4910         /* default flow control settings */
4911         hw->fc.requested_mode = ixgbe_fc_full;
4912         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4913 #ifdef CONFIG_DCB
4914         adapter->last_lfc_mode = hw->fc.current_mode;
4915 #endif
4916         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4917         hw->fc.low_water = FC_LOW_WATER(max_frame);
4918         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4919         hw->fc.send_xon = true;
4920         hw->fc.disable_fc_autoneg = false;
4921
4922         /* enable itr by default in dynamic mode */
4923         adapter->rx_itr_setting = 1;
4924         adapter->rx_eitr_param = 20000;
4925         adapter->tx_itr_setting = 1;
4926         adapter->tx_eitr_param = 10000;
4927
4928         /* set defaults for eitr in MegaBytes */
4929         adapter->eitr_low = 10;
4930         adapter->eitr_high = 20;
4931
4932         /* set default ring sizes */
4933         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4934         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4935
4936         /* set default work limits */
4937         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4938
4939         /* initialize eeprom parameters */
4940         if (ixgbe_init_eeprom_params_generic(hw)) {
4941                 e_dev_err("EEPROM initialization failed\n");
4942                 return -EIO;
4943         }
4944
4945         /* enable rx csum by default */
4946         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4947
4948         /* get assigned NUMA node */
4949         adapter->node = dev_to_node(&pdev->dev);
4950
4951         set_bit(__IXGBE_DOWN, &adapter->state);
4952
4953         return 0;
4954 }
4955
4956 /**
4957  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4958  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4959  *
4960  * Return 0 on success, negative on failure
4961  **/
4962 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4963 {
4964         struct device *dev = tx_ring->dev;
4965         int size;
4966
4967         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4968         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4969         if (!tx_ring->tx_buffer_info)
4970                 tx_ring->tx_buffer_info = vzalloc(size);
4971         if (!tx_ring->tx_buffer_info)
4972                 goto err;
4973
4974         /* round up to nearest 4K */
4975         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4976         tx_ring->size = ALIGN(tx_ring->size, 4096);
4977
4978         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4979                                            &tx_ring->dma, GFP_KERNEL);
4980         if (!tx_ring->desc)
4981                 goto err;
4982
4983         tx_ring->next_to_use = 0;
4984         tx_ring->next_to_clean = 0;
4985         return 0;
4986
4987 err:
4988         vfree(tx_ring->tx_buffer_info);
4989         tx_ring->tx_buffer_info = NULL;
4990         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4991         return -ENOMEM;
4992 }
4993
4994 /**
4995  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4996  * @adapter: board private structure
4997  *
4998  * If this function returns with an error, then it's possible one or
4999  * more of the rings is populated (while the rest are not).  It is the
5000  * callers duty to clean those orphaned rings.
5001  *
5002  * Return 0 on success, negative on failure
5003  **/
5004 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5005 {
5006         int i, err = 0;
5007
5008         for (i = 0; i < adapter->num_tx_queues; i++) {
5009                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5010                 if (!err)
5011                         continue;
5012                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5013                 break;
5014         }
5015
5016         return err;
5017 }
5018
5019 /**
5020  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5021  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5022  *
5023  * Returns 0 on success, negative on failure
5024  **/
5025 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5026 {
5027         struct device *dev = rx_ring->dev;
5028         int size;
5029
5030         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5031         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5032         if (!rx_ring->rx_buffer_info)
5033                 rx_ring->rx_buffer_info = vzalloc(size);
5034         if (!rx_ring->rx_buffer_info)
5035                 goto err;
5036
5037         /* Round up to nearest 4K */
5038         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5039         rx_ring->size = ALIGN(rx_ring->size, 4096);
5040
5041         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5042                                            &rx_ring->dma, GFP_KERNEL);
5043
5044         if (!rx_ring->desc)
5045                 goto err;
5046
5047         rx_ring->next_to_clean = 0;
5048         rx_ring->next_to_use = 0;
5049
5050         return 0;
5051 err:
5052         vfree(rx_ring->rx_buffer_info);
5053         rx_ring->rx_buffer_info = NULL;
5054         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5055         return -ENOMEM;
5056 }
5057
5058 /**
5059  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5060  * @adapter: board private structure
5061  *
5062  * If this function returns with an error, then it's possible one or
5063  * more of the rings is populated (while the rest are not).  It is the
5064  * callers duty to clean those orphaned rings.
5065  *
5066  * Return 0 on success, negative on failure
5067  **/
5068 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5069 {
5070         int i, err = 0;
5071
5072         for (i = 0; i < adapter->num_rx_queues; i++) {
5073                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5074                 if (!err)
5075                         continue;
5076                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5077                 break;
5078         }
5079
5080         return err;
5081 }
5082
5083 /**
5084  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5085  * @tx_ring: Tx descriptor ring for a specific queue
5086  *
5087  * Free all transmit software resources
5088  **/
5089 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5090 {
5091         ixgbe_clean_tx_ring(tx_ring);
5092
5093         vfree(tx_ring->tx_buffer_info);
5094         tx_ring->tx_buffer_info = NULL;
5095
5096         /* if not set, then don't free */
5097         if (!tx_ring->desc)
5098                 return;
5099
5100         dma_free_coherent(tx_ring->dev, tx_ring->size,
5101                           tx_ring->desc, tx_ring->dma);
5102
5103         tx_ring->desc = NULL;
5104 }
5105
5106 /**
5107  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5108  * @adapter: board private structure
5109  *
5110  * Free all transmit software resources
5111  **/
5112 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5113 {
5114         int i;
5115
5116         for (i = 0; i < adapter->num_tx_queues; i++)
5117                 if (adapter->tx_ring[i]->desc)
5118                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5119 }
5120
5121 /**
5122  * ixgbe_free_rx_resources - Free Rx Resources
5123  * @rx_ring: ring to clean the resources from
5124  *
5125  * Free all receive software resources
5126  **/
5127 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5128 {
5129         ixgbe_clean_rx_ring(rx_ring);
5130
5131         vfree(rx_ring->rx_buffer_info);
5132         rx_ring->rx_buffer_info = NULL;
5133
5134         /* if not set, then don't free */
5135         if (!rx_ring->desc)
5136                 return;
5137
5138         dma_free_coherent(rx_ring->dev, rx_ring->size,
5139                           rx_ring->desc, rx_ring->dma);
5140
5141         rx_ring->desc = NULL;
5142 }
5143
5144 /**
5145  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5146  * @adapter: board private structure
5147  *
5148  * Free all receive software resources
5149  **/
5150 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5151 {
5152         int i;
5153
5154         for (i = 0; i < adapter->num_rx_queues; i++)
5155                 if (adapter->rx_ring[i]->desc)
5156                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5157 }
5158
5159 /**
5160  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5161  * @netdev: network interface device structure
5162  * @new_mtu: new value for maximum frame size
5163  *
5164  * Returns 0 on success, negative on failure
5165  **/
5166 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5167 {
5168         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5169         struct ixgbe_hw *hw = &adapter->hw;
5170         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5171
5172         /* MTU < 68 is an error and causes problems on some kernels */
5173         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5174             hw->mac.type != ixgbe_mac_X540) {
5175                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5176                         return -EINVAL;
5177         } else {
5178                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5179                         return -EINVAL;
5180         }
5181
5182         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5183         /* must set new MTU before calling down or up */
5184         netdev->mtu = new_mtu;
5185
5186         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5187         hw->fc.low_water = FC_LOW_WATER(max_frame);
5188
5189         if (netif_running(netdev))
5190                 ixgbe_reinit_locked(adapter);
5191
5192         return 0;
5193 }
5194
5195 /**
5196  * ixgbe_open - Called when a network interface is made active
5197  * @netdev: network interface device structure
5198  *
5199  * Returns 0 on success, negative value on failure
5200  *
5201  * The open entry point is called when a network interface is made
5202  * active by the system (IFF_UP).  At this point all resources needed
5203  * for transmit and receive operations are allocated, the interrupt
5204  * handler is registered with the OS, the watchdog timer is started,
5205  * and the stack is notified that the interface is ready.
5206  **/
5207 static int ixgbe_open(struct net_device *netdev)
5208 {
5209         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5210         int err;
5211
5212         /* disallow open during test */
5213         if (test_bit(__IXGBE_TESTING, &adapter->state))
5214                 return -EBUSY;
5215
5216         netif_carrier_off(netdev);
5217
5218         /* allocate transmit descriptors */
5219         err = ixgbe_setup_all_tx_resources(adapter);
5220         if (err)
5221                 goto err_setup_tx;
5222
5223         /* allocate receive descriptors */
5224         err = ixgbe_setup_all_rx_resources(adapter);
5225         if (err)
5226                 goto err_setup_rx;
5227
5228         ixgbe_configure(adapter);
5229
5230         err = ixgbe_request_irq(adapter);
5231         if (err)
5232                 goto err_req_irq;
5233
5234         err = ixgbe_up_complete(adapter);
5235         if (err)
5236                 goto err_up;
5237
5238         netif_tx_start_all_queues(netdev);
5239
5240         return 0;
5241
5242 err_up:
5243         ixgbe_release_hw_control(adapter);
5244         ixgbe_free_irq(adapter);
5245 err_req_irq:
5246 err_setup_rx:
5247         ixgbe_free_all_rx_resources(adapter);
5248 err_setup_tx:
5249         ixgbe_free_all_tx_resources(adapter);
5250         ixgbe_reset(adapter);
5251
5252         return err;
5253 }
5254
5255 /**
5256  * ixgbe_close - Disables a network interface
5257  * @netdev: network interface device structure
5258  *
5259  * Returns 0, this is not allowed to fail
5260  *
5261  * The close entry point is called when an interface is de-activated
5262  * by the OS.  The hardware is still under the drivers control, but
5263  * needs to be disabled.  A global MAC reset is issued to stop the
5264  * hardware, and all transmit and receive resources are freed.
5265  **/
5266 static int ixgbe_close(struct net_device *netdev)
5267 {
5268         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5269
5270         ixgbe_down(adapter);
5271         ixgbe_free_irq(adapter);
5272
5273         ixgbe_fdir_filter_exit(adapter);
5274
5275         ixgbe_free_all_tx_resources(adapter);
5276         ixgbe_free_all_rx_resources(adapter);
5277
5278         ixgbe_release_hw_control(adapter);
5279
5280         return 0;
5281 }
5282
5283 #ifdef CONFIG_PM
5284 static int ixgbe_resume(struct pci_dev *pdev)
5285 {
5286         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5287         struct net_device *netdev = adapter->netdev;
5288         u32 err;
5289
5290         pci_set_power_state(pdev, PCI_D0);
5291         pci_restore_state(pdev);
5292         /*
5293          * pci_restore_state clears dev->state_saved so call
5294          * pci_save_state to restore it.
5295          */
5296         pci_save_state(pdev);
5297
5298         err = pci_enable_device_mem(pdev);
5299         if (err) {
5300                 e_dev_err("Cannot enable PCI device from suspend\n");
5301                 return err;
5302         }
5303         pci_set_master(pdev);
5304
5305         pci_wake_from_d3(pdev, false);
5306
5307         err = ixgbe_init_interrupt_scheme(adapter);
5308         if (err) {
5309                 e_dev_err("Cannot initialize interrupts for device\n");
5310                 return err;
5311         }
5312
5313         ixgbe_reset(adapter);
5314
5315         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5316
5317         if (netif_running(netdev)) {
5318                 err = ixgbe_open(netdev);
5319                 if (err)
5320                         return err;
5321         }
5322
5323         netif_device_attach(netdev);
5324
5325         return 0;
5326 }
5327 #endif /* CONFIG_PM */
5328
5329 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5330 {
5331         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5332         struct net_device *netdev = adapter->netdev;
5333         struct ixgbe_hw *hw = &adapter->hw;
5334         u32 ctrl, fctrl;
5335         u32 wufc = adapter->wol;
5336 #ifdef CONFIG_PM
5337         int retval = 0;
5338 #endif
5339
5340         netif_device_detach(netdev);
5341
5342         if (netif_running(netdev)) {
5343                 ixgbe_down(adapter);
5344                 ixgbe_free_irq(adapter);
5345                 ixgbe_free_all_tx_resources(adapter);
5346                 ixgbe_free_all_rx_resources(adapter);
5347         }
5348
5349         ixgbe_clear_interrupt_scheme(adapter);
5350 #ifdef CONFIG_DCB
5351         kfree(adapter->ixgbe_ieee_pfc);
5352         kfree(adapter->ixgbe_ieee_ets);
5353 #endif
5354
5355 #ifdef CONFIG_PM
5356         retval = pci_save_state(pdev);
5357         if (retval)
5358                 return retval;
5359
5360 #endif
5361         if (wufc) {
5362                 ixgbe_set_rx_mode(netdev);
5363
5364                 /* turn on all-multi mode if wake on multicast is enabled */
5365                 if (wufc & IXGBE_WUFC_MC) {
5366                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5367                         fctrl |= IXGBE_FCTRL_MPE;
5368                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5369                 }
5370
5371                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5372                 ctrl |= IXGBE_CTRL_GIO_DIS;
5373                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5374
5375                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5376         } else {
5377                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5378                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5379         }
5380
5381         switch (hw->mac.type) {
5382         case ixgbe_mac_82598EB:
5383                 pci_wake_from_d3(pdev, false);
5384                 break;
5385         case ixgbe_mac_82599EB:
5386         case ixgbe_mac_X540:
5387                 pci_wake_from_d3(pdev, !!wufc);
5388                 break;
5389         default:
5390                 break;
5391         }
5392
5393         *enable_wake = !!wufc;
5394
5395         ixgbe_release_hw_control(adapter);
5396
5397         pci_disable_device(pdev);
5398
5399         return 0;
5400 }
5401
5402 #ifdef CONFIG_PM
5403 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5404 {
5405         int retval;
5406         bool wake;
5407
5408         retval = __ixgbe_shutdown(pdev, &wake);
5409         if (retval)
5410                 return retval;
5411
5412         if (wake) {
5413                 pci_prepare_to_sleep(pdev);
5414         } else {
5415                 pci_wake_from_d3(pdev, false);
5416                 pci_set_power_state(pdev, PCI_D3hot);
5417         }
5418
5419         return 0;
5420 }
5421 #endif /* CONFIG_PM */
5422
5423 static void ixgbe_shutdown(struct pci_dev *pdev)
5424 {
5425         bool wake;
5426
5427         __ixgbe_shutdown(pdev, &wake);
5428
5429         if (system_state == SYSTEM_POWER_OFF) {
5430                 pci_wake_from_d3(pdev, wake);
5431                 pci_set_power_state(pdev, PCI_D3hot);
5432         }
5433 }
5434
5435 /**
5436  * ixgbe_update_stats - Update the board statistics counters.
5437  * @adapter: board private structure
5438  **/
5439 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5440 {
5441         struct net_device *netdev = adapter->netdev;
5442         struct ixgbe_hw *hw = &adapter->hw;
5443         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5444         u64 total_mpc = 0;
5445         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5446         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5447         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5448         u64 bytes = 0, packets = 0;
5449
5450         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5451             test_bit(__IXGBE_RESETTING, &adapter->state))
5452                 return;
5453
5454         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5455                 u64 rsc_count = 0;
5456                 u64 rsc_flush = 0;
5457                 for (i = 0; i < 16; i++)
5458                         adapter->hw_rx_no_dma_resources +=
5459                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5460                 for (i = 0; i < adapter->num_rx_queues; i++) {
5461                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5462                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5463                 }
5464                 adapter->rsc_total_count = rsc_count;
5465                 adapter->rsc_total_flush = rsc_flush;
5466         }
5467
5468         for (i = 0; i < adapter->num_rx_queues; i++) {
5469                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5470                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5471                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5472                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5473                 bytes += rx_ring->stats.bytes;
5474                 packets += rx_ring->stats.packets;
5475         }
5476         adapter->non_eop_descs = non_eop_descs;
5477         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5478         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5479         netdev->stats.rx_bytes = bytes;
5480         netdev->stats.rx_packets = packets;
5481
5482         bytes = 0;
5483         packets = 0;
5484         /* gather some stats to the adapter struct that are per queue */
5485         for (i = 0; i < adapter->num_tx_queues; i++) {
5486                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5487                 restart_queue += tx_ring->tx_stats.restart_queue;
5488                 tx_busy += tx_ring->tx_stats.tx_busy;
5489                 bytes += tx_ring->stats.bytes;
5490                 packets += tx_ring->stats.packets;
5491         }
5492         adapter->restart_queue = restart_queue;
5493         adapter->tx_busy = tx_busy;
5494         netdev->stats.tx_bytes = bytes;
5495         netdev->stats.tx_packets = packets;
5496
5497         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5498         for (i = 0; i < 8; i++) {
5499                 /* for packet buffers not used, the register should read 0 */
5500                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5501                 missed_rx += mpc;
5502                 hwstats->mpc[i] += mpc;
5503                 total_mpc += hwstats->mpc[i];
5504                 if (hw->mac.type == ixgbe_mac_82598EB)
5505                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5506                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5507                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5508                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5509                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5510                 switch (hw->mac.type) {
5511                 case ixgbe_mac_82598EB:
5512                         hwstats->pxonrxc[i] +=
5513                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5514                         break;
5515                 case ixgbe_mac_82599EB:
5516                 case ixgbe_mac_X540:
5517                         hwstats->pxonrxc[i] +=
5518                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5519                         break;
5520                 default:
5521                         break;
5522                 }
5523                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5524                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5525         }
5526         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5527         /* work around hardware counting issue */
5528         hwstats->gprc -= missed_rx;
5529
5530         ixgbe_update_xoff_received(adapter);
5531
5532         /* 82598 hardware only has a 32 bit counter in the high register */
5533         switch (hw->mac.type) {
5534         case ixgbe_mac_82598EB:
5535                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5536                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5537                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5538                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5539                 break;
5540         case ixgbe_mac_X540:
5541                 /* OS2BMC stats are X540 only*/
5542                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5543                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5544                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5545                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5546         case ixgbe_mac_82599EB:
5547                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5548                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5549                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5550                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5551                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5552                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5553                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5554                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5555                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5556 #ifdef IXGBE_FCOE
5557                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5558                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5559                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5560                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5561                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5562                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5563 #endif /* IXGBE_FCOE */
5564                 break;
5565         default:
5566                 break;
5567         }
5568         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5569         hwstats->bprc += bprc;
5570         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5571         if (hw->mac.type == ixgbe_mac_82598EB)
5572                 hwstats->mprc -= bprc;
5573         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5574         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5575         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5576         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5577         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5578         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5579         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5580         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5581         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5582         hwstats->lxontxc += lxon;
5583         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5584         hwstats->lxofftxc += lxoff;
5585         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5586         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5587         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5588         /*
5589          * 82598 errata - tx of flow control packets is included in tx counters
5590          */
5591         xon_off_tot = lxon + lxoff;
5592         hwstats->gptc -= xon_off_tot;
5593         hwstats->mptc -= xon_off_tot;
5594         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5595         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5596         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5597         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5598         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5599         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5600         hwstats->ptc64 -= xon_off_tot;
5601         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5602         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5603         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5604         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5605         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5606         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5607
5608         /* Fill out the OS statistics structure */
5609         netdev->stats.multicast = hwstats->mprc;
5610
5611         /* Rx Errors */
5612         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5613         netdev->stats.rx_dropped = 0;
5614         netdev->stats.rx_length_errors = hwstats->rlec;
5615         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5616         netdev->stats.rx_missed_errors = total_mpc;
5617 }
5618
5619 /**
5620  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5621  * @adapter - pointer to the device adapter structure
5622  **/
5623 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5624 {
5625         struct ixgbe_hw *hw = &adapter->hw;
5626         int i;
5627
5628         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5629                 return;
5630
5631         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5632
5633         /* if interface is down do nothing */
5634         if (test_bit(__IXGBE_DOWN, &adapter->state))
5635                 return;
5636
5637         /* do nothing if we are not using signature filters */
5638         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5639                 return;
5640
5641         adapter->fdir_overflow++;
5642
5643         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5644                 for (i = 0; i < adapter->num_tx_queues; i++)
5645                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5646                                 &(adapter->tx_ring[i]->state));
5647                 /* re-enable flow director interrupts */
5648                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5649         } else {
5650                 e_err(probe, "failed to finish FDIR re-initialization, "
5651                       "ignored adding FDIR ATR filters\n");
5652         }
5653 }
5654
5655 /**
5656  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5657  * @adapter - pointer to the device adapter structure
5658  *
5659  * This function serves two purposes.  First it strobes the interrupt lines
5660  * in order to make certain interrupts are occuring.  Secondly it sets the
5661  * bits needed to check for TX hangs.  As a result we should immediately
5662  * determine if a hang has occured.
5663  */
5664 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5665 {
5666         struct ixgbe_hw *hw = &adapter->hw;
5667         u64 eics = 0;
5668         int i;
5669
5670         /* If we're down or resetting, just bail */
5671         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5672             test_bit(__IXGBE_RESETTING, &adapter->state))
5673                 return;
5674
5675         /* Force detection of hung controller */
5676         if (netif_carrier_ok(adapter->netdev)) {
5677                 for (i = 0; i < adapter->num_tx_queues; i++)
5678                         set_check_for_tx_hang(adapter->tx_ring[i]);
5679         }
5680
5681         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5682                 /*
5683                  * for legacy and MSI interrupts don't set any bits
5684                  * that are enabled for EIAM, because this operation
5685                  * would set *both* EIMS and EICS for any bit in EIAM
5686                  */
5687                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5688                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5689         } else {
5690                 /* get one bit for every active tx/rx interrupt vector */
5691                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5692                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5693                         if (qv->rx.ring || qv->tx.ring)
5694                                 eics |= ((u64)1 << i);
5695                 }
5696         }
5697
5698         /* Cause software interrupt to ensure rings are cleaned */
5699         ixgbe_irq_rearm_queues(adapter, eics);
5700
5701 }
5702
5703 /**
5704  * ixgbe_watchdog_update_link - update the link status
5705  * @adapter - pointer to the device adapter structure
5706  * @link_speed - pointer to a u32 to store the link_speed
5707  **/
5708 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5709 {
5710         struct ixgbe_hw *hw = &adapter->hw;
5711         u32 link_speed = adapter->link_speed;
5712         bool link_up = adapter->link_up;
5713         int i;
5714
5715         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5716                 return;
5717
5718         if (hw->mac.ops.check_link) {
5719                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5720         } else {
5721                 /* always assume link is up, if no check link function */
5722                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5723                 link_up = true;
5724         }
5725         if (link_up) {
5726                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5727                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5728                                 hw->mac.ops.fc_enable(hw, i);
5729                 } else {
5730                         hw->mac.ops.fc_enable(hw, 0);
5731                 }
5732         }
5733
5734         if (link_up ||
5735             time_after(jiffies, (adapter->link_check_timeout +
5736                                  IXGBE_TRY_LINK_TIMEOUT))) {
5737                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5738                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5739                 IXGBE_WRITE_FLUSH(hw);
5740         }
5741
5742         adapter->link_up = link_up;
5743         adapter->link_speed = link_speed;
5744 }
5745
5746 /**
5747  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5748  *                             print link up message
5749  * @adapter - pointer to the device adapter structure
5750  **/
5751 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5752 {
5753         struct net_device *netdev = adapter->netdev;
5754         struct ixgbe_hw *hw = &adapter->hw;
5755         u32 link_speed = adapter->link_speed;
5756         bool flow_rx, flow_tx;
5757
5758         /* only continue if link was previously down */
5759         if (netif_carrier_ok(netdev))
5760                 return;
5761
5762         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5763
5764         switch (hw->mac.type) {
5765         case ixgbe_mac_82598EB: {
5766                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5767                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5768                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5769                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5770         }
5771                 break;
5772         case ixgbe_mac_X540:
5773         case ixgbe_mac_82599EB: {
5774                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5775                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5776                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5777                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5778         }
5779                 break;
5780         default:
5781                 flow_tx = false;
5782                 flow_rx = false;
5783                 break;
5784         }
5785         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5786                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5787                "10 Gbps" :
5788                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5789                "1 Gbps" :
5790                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5791                "100 Mbps" :
5792                "unknown speed"))),
5793                ((flow_rx && flow_tx) ? "RX/TX" :
5794                (flow_rx ? "RX" :
5795                (flow_tx ? "TX" : "None"))));
5796
5797         netif_carrier_on(netdev);
5798         ixgbe_check_vf_rate_limit(adapter);
5799 }
5800
5801 /**
5802  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5803  *                               print link down message
5804  * @adapter - pointer to the adapter structure
5805  **/
5806 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5807 {
5808         struct net_device *netdev = adapter->netdev;
5809         struct ixgbe_hw *hw = &adapter->hw;
5810
5811         adapter->link_up = false;
5812         adapter->link_speed = 0;
5813
5814         /* only continue if link was up previously */
5815         if (!netif_carrier_ok(netdev))
5816                 return;
5817
5818         /* poll for SFP+ cable when link is down */
5819         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5820                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5821
5822         e_info(drv, "NIC Link is Down\n");
5823         netif_carrier_off(netdev);
5824 }
5825
5826 /**
5827  * ixgbe_watchdog_flush_tx - flush queues on link down
5828  * @adapter - pointer to the device adapter structure
5829  **/
5830 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5831 {
5832         int i;
5833         int some_tx_pending = 0;
5834
5835         if (!netif_carrier_ok(adapter->netdev)) {
5836                 for (i = 0; i < adapter->num_tx_queues; i++) {
5837                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5838                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5839                                 some_tx_pending = 1;
5840                                 break;
5841                         }
5842                 }
5843
5844                 if (some_tx_pending) {
5845                         /* We've lost link, so the controller stops DMA,
5846                          * but we've got queued Tx work that's never going
5847                          * to get done, so reset controller to flush Tx.
5848                          * (Do the reset outside of interrupt context).
5849                          */
5850                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5851                 }
5852         }
5853 }
5854
5855 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5856 {
5857         u32 ssvpc;
5858
5859         /* Do not perform spoof check for 82598 */
5860         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5861                 return;
5862
5863         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5864
5865         /*
5866          * ssvpc register is cleared on read, if zero then no
5867          * spoofed packets in the last interval.
5868          */
5869         if (!ssvpc)
5870                 return;
5871
5872         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5873 }
5874
5875 /**
5876  * ixgbe_watchdog_subtask - check and bring link up
5877  * @adapter - pointer to the device adapter structure
5878  **/
5879 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5880 {
5881         /* if interface is down do nothing */
5882         if (test_bit(__IXGBE_DOWN, &adapter->state))
5883                 return;
5884
5885         ixgbe_watchdog_update_link(adapter);
5886
5887         if (adapter->link_up)
5888                 ixgbe_watchdog_link_is_up(adapter);
5889         else
5890                 ixgbe_watchdog_link_is_down(adapter);
5891
5892         ixgbe_spoof_check(adapter);
5893         ixgbe_update_stats(adapter);
5894
5895         ixgbe_watchdog_flush_tx(adapter);
5896 }
5897
5898 /**
5899  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5900  * @adapter - the ixgbe adapter structure
5901  **/
5902 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5903 {
5904         struct ixgbe_hw *hw = &adapter->hw;
5905         s32 err;
5906
5907         /* not searching for SFP so there is nothing to do here */
5908         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5909             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5910                 return;
5911
5912         /* someone else is in init, wait until next service event */
5913         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5914                 return;
5915
5916         err = hw->phy.ops.identify_sfp(hw);
5917         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5918                 goto sfp_out;
5919
5920         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5921                 /* If no cable is present, then we need to reset
5922                  * the next time we find a good cable. */
5923                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5924         }
5925
5926         /* exit on error */
5927         if (err)
5928                 goto sfp_out;
5929
5930         /* exit if reset not needed */
5931         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5932                 goto sfp_out;
5933
5934         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5935
5936         /*
5937          * A module may be identified correctly, but the EEPROM may not have
5938          * support for that module.  setup_sfp() will fail in that case, so
5939          * we should not allow that module to load.
5940          */
5941         if (hw->mac.type == ixgbe_mac_82598EB)
5942                 err = hw->phy.ops.reset(hw);
5943         else
5944                 err = hw->mac.ops.setup_sfp(hw);
5945
5946         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5947                 goto sfp_out;
5948
5949         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5950         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5951
5952 sfp_out:
5953         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5954
5955         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5956             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5957                 e_dev_err("failed to initialize because an unsupported "
5958                           "SFP+ module type was detected.\n");
5959                 e_dev_err("Reload the driver after installing a "
5960                           "supported module.\n");
5961                 unregister_netdev(adapter->netdev);
5962         }
5963 }
5964
5965 /**
5966  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5967  * @adapter - the ixgbe adapter structure
5968  **/
5969 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5970 {
5971         struct ixgbe_hw *hw = &adapter->hw;
5972         u32 autoneg;
5973         bool negotiation;
5974
5975         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5976                 return;
5977
5978         /* someone else is in init, wait until next service event */
5979         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5980                 return;
5981
5982         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5983
5984         autoneg = hw->phy.autoneg_advertised;
5985         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5986                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5987         hw->mac.autotry_restart = false;
5988         if (hw->mac.ops.setup_link)
5989                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5990
5991         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5992         adapter->link_check_timeout = jiffies;
5993         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5994 }
5995
5996 /**
5997  * ixgbe_service_timer - Timer Call-back
5998  * @data: pointer to adapter cast into an unsigned long
5999  **/
6000 static void ixgbe_service_timer(unsigned long data)
6001 {
6002         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6003         unsigned long next_event_offset;
6004
6005         /* poll faster when waiting for link */
6006         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6007                 next_event_offset = HZ / 10;
6008         else
6009                 next_event_offset = HZ * 2;
6010
6011         /* Reset the timer */
6012         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6013
6014         ixgbe_service_event_schedule(adapter);
6015 }
6016
6017 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6018 {
6019         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6020                 return;
6021
6022         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6023
6024         /* If we're already down or resetting, just bail */
6025         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6026             test_bit(__IXGBE_RESETTING, &adapter->state))
6027                 return;
6028
6029         ixgbe_dump(adapter);
6030         netdev_err(adapter->netdev, "Reset adapter\n");
6031         adapter->tx_timeout_count++;
6032
6033         ixgbe_reinit_locked(adapter);
6034 }
6035
6036 /**
6037  * ixgbe_service_task - manages and runs subtasks
6038  * @work: pointer to work_struct containing our data
6039  **/
6040 static void ixgbe_service_task(struct work_struct *work)
6041 {
6042         struct ixgbe_adapter *adapter = container_of(work,
6043                                                      struct ixgbe_adapter,
6044                                                      service_task);
6045
6046         ixgbe_reset_subtask(adapter);
6047         ixgbe_sfp_detection_subtask(adapter);
6048         ixgbe_sfp_link_config_subtask(adapter);
6049         ixgbe_check_overtemp_subtask(adapter);
6050         ixgbe_watchdog_subtask(adapter);
6051         ixgbe_fdir_reinit_subtask(adapter);
6052         ixgbe_check_hang_subtask(adapter);
6053
6054         ixgbe_service_event_complete(adapter);
6055 }
6056
6057 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6058                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6059 {
6060         struct ixgbe_adv_tx_context_desc *context_desc;
6061         u16 i = tx_ring->next_to_use;
6062
6063         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6064
6065         i++;
6066         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6067
6068         /* set bits to identify this as an advanced context descriptor */
6069         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6070
6071         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6072         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6073         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6074         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6075 }
6076
6077 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6078                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6079 {
6080         int err;
6081         u32 vlan_macip_lens, type_tucmd;
6082         u32 mss_l4len_idx, l4len;
6083
6084         if (!skb_is_gso(skb))
6085                 return 0;
6086
6087         if (skb_header_cloned(skb)) {
6088                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6089                 if (err)
6090                         return err;
6091         }
6092
6093         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6094         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6095
6096         if (protocol == __constant_htons(ETH_P_IP)) {
6097                 struct iphdr *iph = ip_hdr(skb);
6098                 iph->tot_len = 0;
6099                 iph->check = 0;
6100                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6101                                                          iph->daddr, 0,
6102                                                          IPPROTO_TCP,
6103                                                          0);
6104                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6105         } else if (skb_is_gso_v6(skb)) {
6106                 ipv6_hdr(skb)->payload_len = 0;
6107                 tcp_hdr(skb)->check =
6108                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6109                                      &ipv6_hdr(skb)->daddr,
6110                                      0, IPPROTO_TCP, 0);
6111         }
6112
6113         l4len = tcp_hdrlen(skb);
6114         *hdr_len = skb_transport_offset(skb) + l4len;
6115
6116         /* mss_l4len_id: use 1 as index for TSO */
6117         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6118         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6119         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6120
6121         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6122         vlan_macip_lens = skb_network_header_len(skb);
6123         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6124         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6125
6126         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6127                           mss_l4len_idx);
6128
6129         return 1;
6130 }
6131
6132 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6133                           struct sk_buff *skb, u32 tx_flags,
6134                           __be16 protocol)
6135 {
6136         u32 vlan_macip_lens = 0;
6137         u32 mss_l4len_idx = 0;
6138         u32 type_tucmd = 0;
6139
6140         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6141             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6142                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6143                         return false;
6144         } else {
6145                 u8 l4_hdr = 0;
6146                 switch (protocol) {
6147                 case __constant_htons(ETH_P_IP):
6148                         vlan_macip_lens |= skb_network_header_len(skb);
6149                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6150                         l4_hdr = ip_hdr(skb)->protocol;
6151                         break;
6152                 case __constant_htons(ETH_P_IPV6):
6153                         vlan_macip_lens |= skb_network_header_len(skb);
6154                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6155                         break;
6156                 default:
6157                         if (unlikely(net_ratelimit())) {
6158                                 dev_warn(tx_ring->dev,
6159                                  "partial checksum but proto=%x!\n",
6160                                  skb->protocol);
6161                         }
6162                         break;
6163                 }
6164
6165                 switch (l4_hdr) {
6166                 case IPPROTO_TCP:
6167                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6168                         mss_l4len_idx = tcp_hdrlen(skb) <<
6169                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6170                         break;
6171                 case IPPROTO_SCTP:
6172                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6173                         mss_l4len_idx = sizeof(struct sctphdr) <<
6174                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6175                         break;
6176                 case IPPROTO_UDP:
6177                         mss_l4len_idx = sizeof(struct udphdr) <<
6178                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6179                         break;
6180                 default:
6181                         if (unlikely(net_ratelimit())) {
6182                                 dev_warn(tx_ring->dev,
6183                                  "partial checksum but l4 proto=%x!\n",
6184                                  skb->protocol);
6185                         }
6186                         break;
6187                 }
6188         }
6189
6190         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6191         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6192
6193         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6194                           type_tucmd, mss_l4len_idx);
6195
6196         return (skb->ip_summed == CHECKSUM_PARTIAL);
6197 }
6198
6199 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6200 {
6201         /* set type for advanced descriptor with frame checksum insertion */
6202         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6203                                       IXGBE_ADVTXD_DCMD_IFCS |
6204                                       IXGBE_ADVTXD_DCMD_DEXT);
6205
6206         /* set HW vlan bit if vlan is present */
6207         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6208                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6209
6210         /* set segmentation enable bits for TSO/FSO */
6211 #ifdef IXGBE_FCOE
6212         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6213 #else
6214         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6215 #endif
6216                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6217
6218         return cmd_type;
6219 }
6220
6221 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6222 {
6223         __le32 olinfo_status =
6224                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6225
6226         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6227                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6228                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6229                 /* enble IPv4 checksum for TSO */
6230                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6231                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6232         }
6233
6234         /* enable L4 checksum for TSO and TX checksum offload */
6235         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6236                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6237
6238 #ifdef IXGBE_FCOE
6239         /* use index 1 context for FCOE/FSO */
6240         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6241                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6242                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6243
6244 #endif
6245         /*
6246          * Check Context must be set if Tx switch is enabled, which it
6247          * always is for case where virtual functions are running
6248          */
6249         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6250                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6251
6252         return olinfo_status;
6253 }
6254
6255 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6256                        IXGBE_TXD_CMD_RS)
6257
6258 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6259                          struct sk_buff *skb,
6260                          struct ixgbe_tx_buffer *first,
6261                          u32 tx_flags,
6262                          const u8 hdr_len)
6263 {
6264         struct device *dev = tx_ring->dev;
6265         struct ixgbe_tx_buffer *tx_buffer_info;
6266         union ixgbe_adv_tx_desc *tx_desc;
6267         dma_addr_t dma;
6268         __le32 cmd_type, olinfo_status;
6269         struct skb_frag_struct *frag;
6270         unsigned int f = 0;
6271         unsigned int data_len = skb->data_len;
6272         unsigned int size = skb_headlen(skb);
6273         u32 offset = 0;
6274         u32 paylen = skb->len - hdr_len;
6275         u16 i = tx_ring->next_to_use;
6276         u16 gso_segs;
6277
6278 #ifdef IXGBE_FCOE
6279         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6280                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6281                         data_len -= sizeof(struct fcoe_crc_eof);
6282                 } else {
6283                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6284                         data_len = 0;
6285                 }
6286         }
6287
6288 #endif
6289         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6290         if (dma_mapping_error(dev, dma))
6291                 goto dma_error;
6292
6293         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6294         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6295
6296         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6297
6298         for (;;) {
6299                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6300                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6301                         tx_desc->read.cmd_type_len =
6302                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6303                         tx_desc->read.olinfo_status = olinfo_status;
6304
6305                         offset += IXGBE_MAX_DATA_PER_TXD;
6306                         size -= IXGBE_MAX_DATA_PER_TXD;
6307
6308                         tx_desc++;
6309                         i++;
6310                         if (i == tx_ring->count) {
6311                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6312                                 i = 0;
6313                         }
6314                 }
6315
6316                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6317                 tx_buffer_info->length = offset + size;
6318                 tx_buffer_info->tx_flags = tx_flags;
6319                 tx_buffer_info->dma = dma;
6320
6321                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6322                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6323                 tx_desc->read.olinfo_status = olinfo_status;
6324
6325                 if (!data_len)
6326                         break;
6327
6328                 frag = &skb_shinfo(skb)->frags[f];
6329 #ifdef IXGBE_FCOE
6330                 size = min_t(unsigned int, data_len, frag->size);
6331 #else
6332                 size = frag->size;
6333 #endif
6334                 data_len -= size;
6335                 f++;
6336
6337                 offset = 0;
6338                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6339
6340                 dma = dma_map_page(dev, frag->page, frag->page_offset,
6341                                    size, DMA_TO_DEVICE);
6342                 if (dma_mapping_error(dev, dma))
6343                         goto dma_error;
6344
6345                 tx_desc++;
6346                 i++;
6347                 if (i == tx_ring->count) {
6348                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6349                         i = 0;
6350                 }
6351         }
6352
6353         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6354
6355         i++;
6356         if (i == tx_ring->count)
6357                 i = 0;
6358
6359         tx_ring->next_to_use = i;
6360
6361         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6362                 gso_segs = skb_shinfo(skb)->gso_segs;
6363 #ifdef IXGBE_FCOE
6364         /* adjust for FCoE Sequence Offload */
6365         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6366                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6367                                         skb_shinfo(skb)->gso_size);
6368 #endif /* IXGBE_FCOE */
6369         else
6370                 gso_segs = 1;
6371
6372         /* multiply data chunks by size of headers */
6373         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6374         tx_buffer_info->gso_segs = gso_segs;
6375         tx_buffer_info->skb = skb;
6376
6377         /* set the timestamp */
6378         first->time_stamp = jiffies;
6379
6380         /*
6381          * Force memory writes to complete before letting h/w
6382          * know there are new descriptors to fetch.  (Only
6383          * applicable for weak-ordered memory model archs,
6384          * such as IA-64).
6385          */
6386         wmb();
6387
6388         /* set next_to_watch value indicating a packet is present */
6389         first->next_to_watch = tx_desc;
6390
6391         /* notify HW of packet */
6392         writel(i, tx_ring->tail);
6393
6394         return;
6395 dma_error:
6396         dev_err(dev, "TX DMA map failed\n");
6397
6398         /* clear dma mappings for failed tx_buffer_info map */
6399         for (;;) {
6400                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6401                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6402                 if (tx_buffer_info == first)
6403                         break;
6404                 if (i == 0)
6405                         i = tx_ring->count;
6406                 i--;
6407         }
6408
6409         dev_kfree_skb_any(skb);
6410
6411         tx_ring->next_to_use = i;
6412 }
6413
6414 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6415                       u32 tx_flags, __be16 protocol)
6416 {
6417         struct ixgbe_q_vector *q_vector = ring->q_vector;
6418         union ixgbe_atr_hash_dword input = { .dword = 0 };
6419         union ixgbe_atr_hash_dword common = { .dword = 0 };
6420         union {
6421                 unsigned char *network;
6422                 struct iphdr *ipv4;
6423                 struct ipv6hdr *ipv6;
6424         } hdr;
6425         struct tcphdr *th;
6426         __be16 vlan_id;
6427
6428         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6429         if (!q_vector)
6430                 return;
6431
6432         /* do nothing if sampling is disabled */
6433         if (!ring->atr_sample_rate)
6434                 return;
6435
6436         ring->atr_count++;
6437
6438         /* snag network header to get L4 type and address */
6439         hdr.network = skb_network_header(skb);
6440
6441         /* Currently only IPv4/IPv6 with TCP is supported */
6442         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6443              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6444             (protocol != __constant_htons(ETH_P_IP) ||
6445              hdr.ipv4->protocol != IPPROTO_TCP))
6446                 return;
6447
6448         th = tcp_hdr(skb);
6449
6450         /* skip this packet since it is invalid or the socket is closing */
6451         if (!th || th->fin)
6452                 return;
6453
6454         /* sample on all syn packets or once every atr sample count */
6455         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6456                 return;
6457
6458         /* reset sample count */
6459         ring->atr_count = 0;
6460
6461         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6462
6463         /*
6464          * src and dst are inverted, think how the receiver sees them
6465          *
6466          * The input is broken into two sections, a non-compressed section
6467          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6468          * is XORed together and stored in the compressed dword.
6469          */
6470         input.formatted.vlan_id = vlan_id;
6471
6472         /*
6473          * since src port and flex bytes occupy the same word XOR them together
6474          * and write the value to source port portion of compressed dword
6475          */
6476         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6477                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6478         else
6479                 common.port.src ^= th->dest ^ protocol;
6480         common.port.dst ^= th->source;
6481
6482         if (protocol == __constant_htons(ETH_P_IP)) {
6483                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6484                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6485         } else {
6486                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6487                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6488                              hdr.ipv6->saddr.s6_addr32[1] ^
6489                              hdr.ipv6->saddr.s6_addr32[2] ^
6490                              hdr.ipv6->saddr.s6_addr32[3] ^
6491                              hdr.ipv6->daddr.s6_addr32[0] ^
6492                              hdr.ipv6->daddr.s6_addr32[1] ^
6493                              hdr.ipv6->daddr.s6_addr32[2] ^
6494                              hdr.ipv6->daddr.s6_addr32[3];
6495         }
6496
6497         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6498         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6499                                               input, common, ring->queue_index);
6500 }
6501
6502 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6503 {
6504         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6505         /* Herbert's original patch had:
6506          *  smp_mb__after_netif_stop_queue();
6507          * but since that doesn't exist yet, just open code it. */
6508         smp_mb();
6509
6510         /* We need to check again in a case another CPU has just
6511          * made room available. */
6512         if (likely(ixgbe_desc_unused(tx_ring) < size))
6513                 return -EBUSY;
6514
6515         /* A reprieve! - use start_queue because it doesn't call schedule */
6516         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6517         ++tx_ring->tx_stats.restart_queue;
6518         return 0;
6519 }
6520
6521 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6522 {
6523         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6524                 return 0;
6525         return __ixgbe_maybe_stop_tx(tx_ring, size);
6526 }
6527
6528 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6529 {
6530         struct ixgbe_adapter *adapter = netdev_priv(dev);
6531         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6532                                                smp_processor_id();
6533 #ifdef IXGBE_FCOE
6534         __be16 protocol = vlan_get_protocol(skb);
6535
6536         if (((protocol == htons(ETH_P_FCOE)) ||
6537             (protocol == htons(ETH_P_FIP))) &&
6538             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6539                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6540                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6541                 return txq;
6542         }
6543 #endif
6544
6545         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6546                 while (unlikely(txq >= dev->real_num_tx_queues))
6547                         txq -= dev->real_num_tx_queues;
6548                 return txq;
6549         }
6550
6551         return skb_tx_hash(dev, skb);
6552 }
6553
6554 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6555                           struct ixgbe_adapter *adapter,
6556                           struct ixgbe_ring *tx_ring)
6557 {
6558         struct ixgbe_tx_buffer *first;
6559         int tso;
6560         u32 tx_flags = 0;
6561 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6562         unsigned short f;
6563 #endif
6564         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6565         __be16 protocol = skb->protocol;
6566         u8 hdr_len = 0;
6567
6568         /*
6569          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6570          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6571          *       + 2 desc gap to keep tail from touching head,
6572          *       + 1 desc for context descriptor,
6573          * otherwise try next time
6574          */
6575 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6576         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6577                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6578 #else
6579         count += skb_shinfo(skb)->nr_frags;
6580 #endif
6581         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6582                 tx_ring->tx_stats.tx_busy++;
6583                 return NETDEV_TX_BUSY;
6584         }
6585
6586 #ifdef CONFIG_PCI_IOV
6587         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6588                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6589
6590 #endif
6591         /* if we have a HW VLAN tag being added default to the HW one */
6592         if (vlan_tx_tag_present(skb)) {
6593                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6594                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6595         /* else if it is a SW VLAN check the next protocol and store the tag */
6596         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6597                 struct vlan_hdr *vhdr, _vhdr;
6598                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6599                 if (!vhdr)
6600                         goto out_drop;
6601
6602                 protocol = vhdr->h_vlan_encapsulated_proto;
6603                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6604                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6605         }
6606
6607         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6608             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6609              (skb->priority != TC_PRIO_CONTROL))) {
6610                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6611                 tx_flags |= tx_ring->dcb_tc <<
6612                             IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6613                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6614                         struct vlan_ethhdr *vhdr;
6615                         if (skb_header_cloned(skb) &&
6616                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6617                                 goto out_drop;
6618                         vhdr = (struct vlan_ethhdr *)skb->data;
6619                         vhdr->h_vlan_TCI = htons(tx_flags >>
6620                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6621                 } else {
6622                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6623                 }
6624         }
6625
6626         /* record the location of the first descriptor for this packet */
6627         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6628
6629 #ifdef IXGBE_FCOE
6630         /* setup tx offload for FCoE */
6631         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6632             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6633                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6634                 if (tso < 0)
6635                         goto out_drop;
6636                 else if (tso)
6637                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6638                                     IXGBE_TX_FLAGS_FCOE;
6639                 else
6640                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6641
6642                 goto xmit_fcoe;
6643         }
6644
6645 #endif /* IXGBE_FCOE */
6646         /* setup IPv4/IPv6 offloads */
6647         if (protocol == __constant_htons(ETH_P_IP))
6648                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6649
6650         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6651         if (tso < 0)
6652                 goto out_drop;
6653         else if (tso)
6654                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6655         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6656                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6657
6658         /* add the ATR filter if ATR is on */
6659         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6660                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6661
6662 #ifdef IXGBE_FCOE
6663 xmit_fcoe:
6664 #endif /* IXGBE_FCOE */
6665         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6666
6667         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6668
6669         return NETDEV_TX_OK;
6670
6671 out_drop:
6672         dev_kfree_skb_any(skb);
6673         return NETDEV_TX_OK;
6674 }
6675
6676 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6677 {
6678         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6679         struct ixgbe_ring *tx_ring;
6680
6681         tx_ring = adapter->tx_ring[skb->queue_mapping];
6682         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6683 }
6684
6685 /**
6686  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6687  * @netdev: network interface device structure
6688  * @p: pointer to an address structure
6689  *
6690  * Returns 0 on success, negative on failure
6691  **/
6692 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6693 {
6694         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6695         struct ixgbe_hw *hw = &adapter->hw;
6696         struct sockaddr *addr = p;
6697
6698         if (!is_valid_ether_addr(addr->sa_data))
6699                 return -EADDRNOTAVAIL;
6700
6701         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6702         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6703
6704         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6705                             IXGBE_RAH_AV);
6706
6707         return 0;
6708 }
6709
6710 static int
6711 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6712 {
6713         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6714         struct ixgbe_hw *hw = &adapter->hw;
6715         u16 value;
6716         int rc;
6717
6718         if (prtad != hw->phy.mdio.prtad)
6719                 return -EINVAL;
6720         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6721         if (!rc)
6722                 rc = value;
6723         return rc;
6724 }
6725
6726 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6727                             u16 addr, u16 value)
6728 {
6729         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6730         struct ixgbe_hw *hw = &adapter->hw;
6731
6732         if (prtad != hw->phy.mdio.prtad)
6733                 return -EINVAL;
6734         return hw->phy.ops.write_reg(hw, addr, devad, value);
6735 }
6736
6737 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6738 {
6739         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6740
6741         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6742 }
6743
6744 /**
6745  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6746  * netdev->dev_addrs
6747  * @netdev: network interface device structure
6748  *
6749  * Returns non-zero on failure
6750  **/
6751 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6752 {
6753         int err = 0;
6754         struct ixgbe_adapter *adapter = netdev_priv(dev);
6755         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6756
6757         if (is_valid_ether_addr(mac->san_addr)) {
6758                 rtnl_lock();
6759                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6760                 rtnl_unlock();
6761         }
6762         return err;
6763 }
6764
6765 /**
6766  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6767  * netdev->dev_addrs
6768  * @netdev: network interface device structure
6769  *
6770  * Returns non-zero on failure
6771  **/
6772 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6773 {
6774         int err = 0;
6775         struct ixgbe_adapter *adapter = netdev_priv(dev);
6776         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6777
6778         if (is_valid_ether_addr(mac->san_addr)) {
6779                 rtnl_lock();
6780                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6781                 rtnl_unlock();
6782         }
6783         return err;
6784 }
6785
6786 #ifdef CONFIG_NET_POLL_CONTROLLER
6787 /*
6788  * Polling 'interrupt' - used by things like netconsole to send skbs
6789  * without having to re-enable interrupts. It's not called while
6790  * the interrupt routine is executing.
6791  */
6792 static void ixgbe_netpoll(struct net_device *netdev)
6793 {
6794         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6795         int i;
6796
6797         /* if interface is down do nothing */
6798         if (test_bit(__IXGBE_DOWN, &adapter->state))
6799                 return;
6800
6801         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6802         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6803                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6804                 for (i = 0; i < num_q_vectors; i++) {
6805                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6806                         ixgbe_msix_clean_rings(0, q_vector);
6807                 }
6808         } else {
6809                 ixgbe_intr(adapter->pdev->irq, netdev);
6810         }
6811         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6812 }
6813 #endif
6814
6815 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6816                                                    struct rtnl_link_stats64 *stats)
6817 {
6818         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6819         int i;
6820
6821         rcu_read_lock();
6822         for (i = 0; i < adapter->num_rx_queues; i++) {
6823                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6824                 u64 bytes, packets;
6825                 unsigned int start;
6826
6827                 if (ring) {
6828                         do {
6829                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6830                                 packets = ring->stats.packets;
6831                                 bytes   = ring->stats.bytes;
6832                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6833                         stats->rx_packets += packets;
6834                         stats->rx_bytes   += bytes;
6835                 }
6836         }
6837
6838         for (i = 0; i < adapter->num_tx_queues; i++) {
6839                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6840                 u64 bytes, packets;
6841                 unsigned int start;
6842
6843                 if (ring) {
6844                         do {
6845                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6846                                 packets = ring->stats.packets;
6847                                 bytes   = ring->stats.bytes;
6848                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6849                         stats->tx_packets += packets;
6850                         stats->tx_bytes   += bytes;
6851                 }
6852         }
6853         rcu_read_unlock();
6854         /* following stats updated by ixgbe_watchdog_task() */
6855         stats->multicast        = netdev->stats.multicast;
6856         stats->rx_errors        = netdev->stats.rx_errors;
6857         stats->rx_length_errors = netdev->stats.rx_length_errors;
6858         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6859         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6860         return stats;
6861 }
6862
6863 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6864  * #adapter: pointer to ixgbe_adapter
6865  * @tc: number of traffic classes currently enabled
6866  *
6867  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6868  * 802.1Q priority maps to a packet buffer that exists.
6869  */
6870 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6871 {
6872         struct ixgbe_hw *hw = &adapter->hw;
6873         u32 reg, rsave;
6874         int i;
6875
6876         /* 82598 have a static priority to TC mapping that can not
6877          * be changed so no validation is needed.
6878          */
6879         if (hw->mac.type == ixgbe_mac_82598EB)
6880                 return;
6881
6882         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6883         rsave = reg;
6884
6885         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6886                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6887
6888                 /* If up2tc is out of bounds default to zero */
6889                 if (up2tc > tc)
6890                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6891         }
6892
6893         if (reg != rsave)
6894                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6895
6896         return;
6897 }
6898
6899
6900 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6901  * classes.
6902  *
6903  * @netdev: net device to configure
6904  * @tc: number of traffic classes to enable
6905  */
6906 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6907 {
6908         struct ixgbe_adapter *adapter = netdev_priv(dev);
6909         struct ixgbe_hw *hw = &adapter->hw;
6910
6911         /* Multiple traffic classes requires multiple queues */
6912         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6913                 e_err(drv, "Enable failed, needs MSI-X\n");
6914                 return -EINVAL;
6915         }
6916
6917         /* Hardware supports up to 8 traffic classes */
6918         if (tc > MAX_TRAFFIC_CLASS ||
6919             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6920                 return -EINVAL;
6921
6922         /* Hardware has to reinitialize queues and interrupts to
6923          * match packet buffer alignment. Unfortunantly, the
6924          * hardware is not flexible enough to do this dynamically.
6925          */
6926         if (netif_running(dev))
6927                 ixgbe_close(dev);
6928         ixgbe_clear_interrupt_scheme(adapter);
6929
6930         if (tc) {
6931                 netdev_set_num_tc(dev, tc);
6932                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6933
6934                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6935                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6936
6937                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6938                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
6939         } else {
6940                 netdev_reset_tc(dev);
6941
6942                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6943
6944                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6945                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6946
6947                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6948                 adapter->dcb_cfg.pfc_mode_enable = false;
6949         }
6950
6951         ixgbe_init_interrupt_scheme(adapter);
6952         ixgbe_validate_rtr(adapter, tc);
6953         if (netif_running(dev))
6954                 ixgbe_open(dev);
6955
6956         return 0;
6957 }
6958
6959 void ixgbe_do_reset(struct net_device *netdev)
6960 {
6961         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6962
6963         if (netif_running(netdev))
6964                 ixgbe_reinit_locked(adapter);
6965         else
6966                 ixgbe_reset(adapter);
6967 }
6968
6969 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6970 {
6971         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6972
6973 #ifdef CONFIG_DCB
6974         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6975                 data &= ~NETIF_F_HW_VLAN_RX;
6976 #endif
6977
6978         /* return error if RXHASH is being enabled when RSS is not supported */
6979         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6980                 data &= ~NETIF_F_RXHASH;
6981
6982         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6983         if (!(data & NETIF_F_RXCSUM))
6984                 data &= ~NETIF_F_LRO;
6985
6986         /* Turn off LRO if not RSC capable or invalid ITR settings */
6987         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6988                 data &= ~NETIF_F_LRO;
6989         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6990                    (adapter->rx_itr_setting != 1 &&
6991                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6992                 data &= ~NETIF_F_LRO;
6993                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6994         }
6995
6996         return data;
6997 }
6998
6999 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7000 {
7001         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7002         bool need_reset = false;
7003
7004         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7005         if (!(data & NETIF_F_RXCSUM))
7006                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7007         else
7008                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7009
7010         /* Make sure RSC matches LRO, reset if change */
7011         if (!!(data & NETIF_F_LRO) !=
7012              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7013                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7014                 switch (adapter->hw.mac.type) {
7015                 case ixgbe_mac_X540:
7016                 case ixgbe_mac_82599EB:
7017                         need_reset = true;
7018                         break;
7019                 default:
7020                         break;
7021                 }
7022         }
7023
7024         /*
7025          * Check if Flow Director n-tuple support was enabled or disabled.  If
7026          * the state changed, we need to reset.
7027          */
7028         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7029                 /* turn off ATR, enable perfect filters and reset */
7030                 if (data & NETIF_F_NTUPLE) {
7031                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7032                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7033                         need_reset = true;
7034                 }
7035         } else if (!(data & NETIF_F_NTUPLE)) {
7036                 /* turn off Flow Director, set ATR and reset */
7037                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7038                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7039                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7040                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7041                 need_reset = true;
7042         }
7043
7044         if (need_reset)
7045                 ixgbe_do_reset(netdev);
7046
7047         return 0;
7048
7049 }
7050
7051 static const struct net_device_ops ixgbe_netdev_ops = {
7052         .ndo_open               = ixgbe_open,
7053         .ndo_stop               = ixgbe_close,
7054         .ndo_start_xmit         = ixgbe_xmit_frame,
7055         .ndo_select_queue       = ixgbe_select_queue,
7056         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7057         .ndo_validate_addr      = eth_validate_addr,
7058         .ndo_set_mac_address    = ixgbe_set_mac,
7059         .ndo_change_mtu         = ixgbe_change_mtu,
7060         .ndo_tx_timeout         = ixgbe_tx_timeout,
7061         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7062         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7063         .ndo_do_ioctl           = ixgbe_ioctl,
7064         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7065         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7066         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7067         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7068         .ndo_get_stats64        = ixgbe_get_stats64,
7069         .ndo_setup_tc           = ixgbe_setup_tc,
7070 #ifdef CONFIG_NET_POLL_CONTROLLER
7071         .ndo_poll_controller    = ixgbe_netpoll,
7072 #endif
7073 #ifdef IXGBE_FCOE
7074         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7075         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7076         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7077         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7078         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7079         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7080 #endif /* IXGBE_FCOE */
7081         .ndo_set_features = ixgbe_set_features,
7082         .ndo_fix_features = ixgbe_fix_features,
7083 };
7084
7085 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7086                            const struct ixgbe_info *ii)
7087 {
7088 #ifdef CONFIG_PCI_IOV
7089         struct ixgbe_hw *hw = &adapter->hw;
7090         int err;
7091         int num_vf_macvlans, i;
7092         struct vf_macvlans *mv_list;
7093
7094         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7095                 return;
7096
7097         /* The 82599 supports up to 64 VFs per physical function
7098          * but this implementation limits allocation to 63 so that
7099          * basic networking resources are still available to the
7100          * physical function
7101          */
7102         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7103         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7104         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7105         if (err) {
7106                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7107                 goto err_novfs;
7108         }
7109
7110         num_vf_macvlans = hw->mac.num_rar_entries -
7111                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7112
7113         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7114                                              sizeof(struct vf_macvlans),
7115                                              GFP_KERNEL);
7116         if (mv_list) {
7117                 /* Initialize list of VF macvlans */
7118                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7119                 for (i = 0; i < num_vf_macvlans; i++) {
7120                         mv_list->vf = -1;
7121                         mv_list->free = true;
7122                         mv_list->rar_entry = hw->mac.num_rar_entries -
7123                                 (i + adapter->num_vfs + 1);
7124                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7125                         mv_list++;
7126                 }
7127         }
7128
7129         /* If call to enable VFs succeeded then allocate memory
7130          * for per VF control structures.
7131          */
7132         adapter->vfinfo =
7133                 kcalloc(adapter->num_vfs,
7134                         sizeof(struct vf_data_storage), GFP_KERNEL);
7135         if (adapter->vfinfo) {
7136                 /* Now that we're sure SR-IOV is enabled
7137                  * and memory allocated set up the mailbox parameters
7138                  */
7139                 ixgbe_init_mbx_params_pf(hw);
7140                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7141                        sizeof(hw->mbx.ops));
7142
7143                 /* Disable RSC when in SR-IOV mode */
7144                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7145                                      IXGBE_FLAG2_RSC_ENABLED);
7146                 return;
7147         }
7148
7149         /* Oh oh */
7150         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7151               "SRIOV disabled\n");
7152         pci_disable_sriov(adapter->pdev);
7153
7154 err_novfs:
7155         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7156         adapter->num_vfs = 0;
7157 #endif /* CONFIG_PCI_IOV */
7158 }
7159
7160 /**
7161  * ixgbe_probe - Device Initialization Routine
7162  * @pdev: PCI device information struct
7163  * @ent: entry in ixgbe_pci_tbl
7164  *
7165  * Returns 0 on success, negative on failure
7166  *
7167  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7168  * The OS initialization, configuring of the adapter private structure,
7169  * and a hardware reset occur.
7170  **/
7171 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7172                                  const struct pci_device_id *ent)
7173 {
7174         struct net_device *netdev;
7175         struct ixgbe_adapter *adapter = NULL;
7176         struct ixgbe_hw *hw;
7177         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7178         static int cards_found;
7179         int i, err, pci_using_dac;
7180         u8 part_str[IXGBE_PBANUM_LENGTH];
7181         unsigned int indices = num_possible_cpus();
7182 #ifdef IXGBE_FCOE
7183         u16 device_caps;
7184 #endif
7185         u32 eec;
7186
7187         /* Catch broken hardware that put the wrong VF device ID in
7188          * the PCIe SR-IOV capability.
7189          */
7190         if (pdev->is_virtfn) {
7191                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7192                      pci_name(pdev), pdev->vendor, pdev->device);
7193                 return -EINVAL;
7194         }
7195
7196         err = pci_enable_device_mem(pdev);
7197         if (err)
7198                 return err;
7199
7200         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7201             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7202                 pci_using_dac = 1;
7203         } else {
7204                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7205                 if (err) {
7206                         err = dma_set_coherent_mask(&pdev->dev,
7207                                                     DMA_BIT_MASK(32));
7208                         if (err) {
7209                                 dev_err(&pdev->dev,
7210                                         "No usable DMA configuration, aborting\n");
7211                                 goto err_dma;
7212                         }
7213                 }
7214                 pci_using_dac = 0;
7215         }
7216
7217         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7218                                            IORESOURCE_MEM), ixgbe_driver_name);
7219         if (err) {
7220                 dev_err(&pdev->dev,
7221                         "pci_request_selected_regions failed 0x%x\n", err);
7222                 goto err_pci_reg;
7223         }
7224
7225         pci_enable_pcie_error_reporting(pdev);
7226
7227         pci_set_master(pdev);
7228         pci_save_state(pdev);
7229
7230 #ifdef CONFIG_IXGBE_DCB
7231         indices *= MAX_TRAFFIC_CLASS;
7232 #endif
7233
7234         if (ii->mac == ixgbe_mac_82598EB)
7235                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7236         else
7237                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7238
7239 #ifdef IXGBE_FCOE
7240         indices += min_t(unsigned int, num_possible_cpus(),
7241                          IXGBE_MAX_FCOE_INDICES);
7242 #endif
7243         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7244         if (!netdev) {
7245                 err = -ENOMEM;
7246                 goto err_alloc_etherdev;
7247         }
7248
7249         SET_NETDEV_DEV(netdev, &pdev->dev);
7250
7251         adapter = netdev_priv(netdev);
7252         pci_set_drvdata(pdev, adapter);
7253
7254         adapter->netdev = netdev;
7255         adapter->pdev = pdev;
7256         hw = &adapter->hw;
7257         hw->back = adapter;
7258         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7259
7260         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7261                               pci_resource_len(pdev, 0));
7262         if (!hw->hw_addr) {
7263                 err = -EIO;
7264                 goto err_ioremap;
7265         }
7266
7267         for (i = 1; i <= 5; i++) {
7268                 if (pci_resource_len(pdev, i) == 0)
7269                         continue;
7270         }
7271
7272         netdev->netdev_ops = &ixgbe_netdev_ops;
7273         ixgbe_set_ethtool_ops(netdev);
7274         netdev->watchdog_timeo = 5 * HZ;
7275         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7276
7277         adapter->bd_number = cards_found;
7278
7279         /* Setup hw api */
7280         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7281         hw->mac.type  = ii->mac;
7282
7283         /* EEPROM */
7284         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7285         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7286         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7287         if (!(eec & (1 << 8)))
7288                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7289
7290         /* PHY */
7291         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7292         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7293         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7294         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7295         hw->phy.mdio.mmds = 0;
7296         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7297         hw->phy.mdio.dev = netdev;
7298         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7299         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7300
7301         ii->get_invariants(hw);
7302
7303         /* setup the private structure */
7304         err = ixgbe_sw_init(adapter);
7305         if (err)
7306                 goto err_sw_init;
7307
7308         /* Make it possible the adapter to be woken up via WOL */
7309         switch (adapter->hw.mac.type) {
7310         case ixgbe_mac_82599EB:
7311         case ixgbe_mac_X540:
7312                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7313                 break;
7314         default:
7315                 break;
7316         }
7317
7318         /*
7319          * If there is a fan on this device and it has failed log the
7320          * failure.
7321          */
7322         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7323                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7324                 if (esdp & IXGBE_ESDP_SDP1)
7325                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7326         }
7327
7328         /* reset_hw fills in the perm_addr as well */
7329         hw->phy.reset_if_overtemp = true;
7330         err = hw->mac.ops.reset_hw(hw);
7331         hw->phy.reset_if_overtemp = false;
7332         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7333             hw->mac.type == ixgbe_mac_82598EB) {
7334                 err = 0;
7335         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7336                 e_dev_err("failed to load because an unsupported SFP+ "
7337                           "module type was detected.\n");
7338                 e_dev_err("Reload the driver after installing a supported "
7339                           "module.\n");
7340                 goto err_sw_init;
7341         } else if (err) {
7342                 e_dev_err("HW Init failed: %d\n", err);
7343                 goto err_sw_init;
7344         }
7345
7346         ixgbe_probe_vf(adapter, ii);
7347
7348         netdev->features = NETIF_F_SG |
7349                            NETIF_F_IP_CSUM |
7350                            NETIF_F_IPV6_CSUM |
7351                            NETIF_F_HW_VLAN_TX |
7352                            NETIF_F_HW_VLAN_RX |
7353                            NETIF_F_HW_VLAN_FILTER |
7354                            NETIF_F_TSO |
7355                            NETIF_F_TSO6 |
7356                            NETIF_F_RXHASH |
7357                            NETIF_F_RXCSUM;
7358
7359         netdev->hw_features = netdev->features;
7360
7361         switch (adapter->hw.mac.type) {
7362         case ixgbe_mac_82599EB:
7363         case ixgbe_mac_X540:
7364                 netdev->features |= NETIF_F_SCTP_CSUM;
7365                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7366                                        NETIF_F_NTUPLE;
7367                 break;
7368         default:
7369                 break;
7370         }
7371
7372         netdev->vlan_features |= NETIF_F_TSO;
7373         netdev->vlan_features |= NETIF_F_TSO6;
7374         netdev->vlan_features |= NETIF_F_IP_CSUM;
7375         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7376         netdev->vlan_features |= NETIF_F_SG;
7377
7378         netdev->priv_flags |= IFF_UNICAST_FLT;
7379
7380         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7381                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7382                                     IXGBE_FLAG_DCB_ENABLED);
7383
7384 #ifdef CONFIG_IXGBE_DCB
7385         netdev->dcbnl_ops = &dcbnl_ops;
7386 #endif
7387
7388 #ifdef IXGBE_FCOE
7389         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7390                 if (hw->mac.ops.get_device_caps) {
7391                         hw->mac.ops.get_device_caps(hw, &device_caps);
7392                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7393                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7394                 }
7395         }
7396         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7397                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7398                 netdev->vlan_features |= NETIF_F_FSO;
7399                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7400         }
7401 #endif /* IXGBE_FCOE */
7402         if (pci_using_dac) {
7403                 netdev->features |= NETIF_F_HIGHDMA;
7404                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7405         }
7406
7407         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7408                 netdev->hw_features |= NETIF_F_LRO;
7409         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7410                 netdev->features |= NETIF_F_LRO;
7411
7412         /* make sure the EEPROM is good */
7413         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7414                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7415                 err = -EIO;
7416                 goto err_eeprom;
7417         }
7418
7419         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7420         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7421
7422         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7423                 e_dev_err("invalid MAC address\n");
7424                 err = -EIO;
7425                 goto err_eeprom;
7426         }
7427
7428         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7429         if (hw->mac.ops.disable_tx_laser &&
7430             ((hw->phy.multispeed_fiber) ||
7431              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7432               (hw->mac.type == ixgbe_mac_82599EB))))
7433                 hw->mac.ops.disable_tx_laser(hw);
7434
7435         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7436                     (unsigned long) adapter);
7437
7438         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7439         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7440
7441         err = ixgbe_init_interrupt_scheme(adapter);
7442         if (err)
7443                 goto err_sw_init;
7444
7445         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7446                 netdev->hw_features &= ~NETIF_F_RXHASH;
7447                 netdev->features &= ~NETIF_F_RXHASH;
7448         }
7449
7450         switch (pdev->device) {
7451         case IXGBE_DEV_ID_82599_SFP:
7452                 /* Only this subdevice supports WOL */
7453                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7454                         adapter->wol = IXGBE_WUFC_MAG;
7455                 break;
7456         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7457                 /* All except this subdevice support WOL */
7458                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7459                         adapter->wol = IXGBE_WUFC_MAG;
7460                 break;
7461         case IXGBE_DEV_ID_82599_KX4:
7462                 adapter->wol = IXGBE_WUFC_MAG;
7463                 break;
7464         default:
7465                 adapter->wol = 0;
7466                 break;
7467         }
7468         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7469
7470         /* pick up the PCI bus settings for reporting later */
7471         hw->mac.ops.get_bus_info(hw);
7472
7473         /* print bus type/speed/width info */
7474         e_dev_info("(PCI Express:%s:%s) %pM\n",
7475                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7476                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7477                     "Unknown"),
7478                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7479                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7480                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7481                     "Unknown"),
7482                    netdev->dev_addr);
7483
7484         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7485         if (err)
7486                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7487         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7488                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7489                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7490                            part_str);
7491         else
7492                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7493                            hw->mac.type, hw->phy.type, part_str);
7494
7495         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7496                 e_dev_warn("PCI-Express bandwidth available for this card is "
7497                            "not sufficient for optimal performance.\n");
7498                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7499                            "is required.\n");
7500         }
7501
7502         /* save off EEPROM version number */
7503         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7504
7505         /* reset the hardware with the new settings */
7506         err = hw->mac.ops.start_hw(hw);
7507
7508         if (err == IXGBE_ERR_EEPROM_VERSION) {
7509                 /* We are running on a pre-production device, log a warning */
7510                 e_dev_warn("This device is a pre-production adapter/LOM. "
7511                            "Please be aware there may be issues associated "
7512                            "with your hardware.  If you are experiencing "
7513                            "problems please contact your Intel or hardware "
7514                            "representative who provided you with this "
7515                            "hardware.\n");
7516         }
7517         strcpy(netdev->name, "eth%d");
7518         err = register_netdev(netdev);
7519         if (err)
7520                 goto err_register;
7521
7522         /* carrier off reporting is important to ethtool even BEFORE open */
7523         netif_carrier_off(netdev);
7524
7525 #ifdef CONFIG_IXGBE_DCA
7526         if (dca_add_requester(&pdev->dev) == 0) {
7527                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7528                 ixgbe_setup_dca(adapter);
7529         }
7530 #endif
7531         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7532                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7533                 for (i = 0; i < adapter->num_vfs; i++)
7534                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7535         }
7536
7537         /* Inform firmware of driver version */
7538         if (hw->mac.ops.set_fw_drv_ver)
7539                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7540                                            FW_CEM_UNUSED_VER);
7541
7542         /* add san mac addr to netdev */
7543         ixgbe_add_sanmac_netdev(netdev);
7544
7545         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7546         cards_found++;
7547         return 0;
7548
7549 err_register:
7550         ixgbe_release_hw_control(adapter);
7551         ixgbe_clear_interrupt_scheme(adapter);
7552 err_sw_init:
7553 err_eeprom:
7554         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7555                 ixgbe_disable_sriov(adapter);
7556         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7557         iounmap(hw->hw_addr);
7558 err_ioremap:
7559         free_netdev(netdev);
7560 err_alloc_etherdev:
7561         pci_release_selected_regions(pdev,
7562                                      pci_select_bars(pdev, IORESOURCE_MEM));
7563 err_pci_reg:
7564 err_dma:
7565         pci_disable_device(pdev);
7566         return err;
7567 }
7568
7569 /**
7570  * ixgbe_remove - Device Removal Routine
7571  * @pdev: PCI device information struct
7572  *
7573  * ixgbe_remove is called by the PCI subsystem to alert the driver
7574  * that it should release a PCI device.  The could be caused by a
7575  * Hot-Plug event, or because the driver is going to be removed from
7576  * memory.
7577  **/
7578 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7579 {
7580         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7581         struct net_device *netdev = adapter->netdev;
7582
7583         set_bit(__IXGBE_DOWN, &adapter->state);
7584         cancel_work_sync(&adapter->service_task);
7585
7586 #ifdef CONFIG_IXGBE_DCA
7587         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7588                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7589                 dca_remove_requester(&pdev->dev);
7590                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7591         }
7592
7593 #endif
7594 #ifdef IXGBE_FCOE
7595         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7596                 ixgbe_cleanup_fcoe(adapter);
7597
7598 #endif /* IXGBE_FCOE */
7599
7600         /* remove the added san mac */
7601         ixgbe_del_sanmac_netdev(netdev);
7602
7603         if (netdev->reg_state == NETREG_REGISTERED)
7604                 unregister_netdev(netdev);
7605
7606         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7607                 ixgbe_disable_sriov(adapter);
7608
7609         ixgbe_clear_interrupt_scheme(adapter);
7610
7611         ixgbe_release_hw_control(adapter);
7612
7613         iounmap(adapter->hw.hw_addr);
7614         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7615                                      IORESOURCE_MEM));
7616
7617         e_dev_info("complete\n");
7618
7619         free_netdev(netdev);
7620
7621         pci_disable_pcie_error_reporting(pdev);
7622
7623         pci_disable_device(pdev);
7624 }
7625
7626 /**
7627  * ixgbe_io_error_detected - called when PCI error is detected
7628  * @pdev: Pointer to PCI device
7629  * @state: The current pci connection state
7630  *
7631  * This function is called after a PCI bus error affecting
7632  * this device has been detected.
7633  */
7634 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7635                                                 pci_channel_state_t state)
7636 {
7637         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7638         struct net_device *netdev = adapter->netdev;
7639
7640         netif_device_detach(netdev);
7641
7642         if (state == pci_channel_io_perm_failure)
7643                 return PCI_ERS_RESULT_DISCONNECT;
7644
7645         if (netif_running(netdev))
7646                 ixgbe_down(adapter);
7647         pci_disable_device(pdev);
7648
7649         /* Request a slot reset. */
7650         return PCI_ERS_RESULT_NEED_RESET;
7651 }
7652
7653 /**
7654  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7655  * @pdev: Pointer to PCI device
7656  *
7657  * Restart the card from scratch, as if from a cold-boot.
7658  */
7659 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7660 {
7661         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7662         pci_ers_result_t result;
7663         int err;
7664
7665         if (pci_enable_device_mem(pdev)) {
7666                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7667                 result = PCI_ERS_RESULT_DISCONNECT;
7668         } else {
7669                 pci_set_master(pdev);
7670                 pci_restore_state(pdev);
7671                 pci_save_state(pdev);
7672
7673                 pci_wake_from_d3(pdev, false);
7674
7675                 ixgbe_reset(adapter);
7676                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7677                 result = PCI_ERS_RESULT_RECOVERED;
7678         }
7679
7680         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7681         if (err) {
7682                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7683                           "failed 0x%0x\n", err);
7684                 /* non-fatal, continue */
7685         }
7686
7687         return result;
7688 }
7689
7690 /**
7691  * ixgbe_io_resume - called when traffic can start flowing again.
7692  * @pdev: Pointer to PCI device
7693  *
7694  * This callback is called when the error recovery driver tells us that
7695  * its OK to resume normal operation.
7696  */
7697 static void ixgbe_io_resume(struct pci_dev *pdev)
7698 {
7699         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7700         struct net_device *netdev = adapter->netdev;
7701
7702         if (netif_running(netdev)) {
7703                 if (ixgbe_up(adapter)) {
7704                         e_info(probe, "ixgbe_up failed after reset\n");
7705                         return;
7706                 }
7707         }
7708
7709         netif_device_attach(netdev);
7710 }
7711
7712 static struct pci_error_handlers ixgbe_err_handler = {
7713         .error_detected = ixgbe_io_error_detected,
7714         .slot_reset = ixgbe_io_slot_reset,
7715         .resume = ixgbe_io_resume,
7716 };
7717
7718 static struct pci_driver ixgbe_driver = {
7719         .name     = ixgbe_driver_name,
7720         .id_table = ixgbe_pci_tbl,
7721         .probe    = ixgbe_probe,
7722         .remove   = __devexit_p(ixgbe_remove),
7723 #ifdef CONFIG_PM
7724         .suspend  = ixgbe_suspend,
7725         .resume   = ixgbe_resume,
7726 #endif
7727         .shutdown = ixgbe_shutdown,
7728         .err_handler = &ixgbe_err_handler
7729 };
7730
7731 /**
7732  * ixgbe_init_module - Driver Registration Routine
7733  *
7734  * ixgbe_init_module is the first routine called when the driver is
7735  * loaded. All it does is register with the PCI subsystem.
7736  **/
7737 static int __init ixgbe_init_module(void)
7738 {
7739         int ret;
7740         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7741         pr_info("%s\n", ixgbe_copyright);
7742
7743 #ifdef CONFIG_IXGBE_DCA
7744         dca_register_notify(&dca_notifier);
7745 #endif
7746
7747         ret = pci_register_driver(&ixgbe_driver);
7748         return ret;
7749 }
7750
7751 module_init(ixgbe_init_module);
7752
7753 /**
7754  * ixgbe_exit_module - Driver Exit Cleanup Routine
7755  *
7756  * ixgbe_exit_module is called just before the driver is removed
7757  * from memory.
7758  **/
7759 static void __exit ixgbe_exit_module(void)
7760 {
7761 #ifdef CONFIG_IXGBE_DCA
7762         dca_unregister_notify(&dca_notifier);
7763 #endif
7764         pci_unregister_driver(&ixgbe_driver);
7765         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7766 }
7767
7768 #ifdef CONFIG_IXGBE_DCA
7769 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7770                             void *p)
7771 {
7772         int ret_val;
7773
7774         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7775                                          __ixgbe_notify_dca);
7776
7777         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7778 }
7779
7780 #endif /* CONFIG_IXGBE_DCA */
7781
7782 module_exit(ixgbe_exit_module);
7783
7784 /* ixgbe_main.c */