drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 6
  60 #define BUILD 7
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
 111         /* required last entry */
 112         {0, }
 113 };
 114 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 115
 116 #ifdef CONFIG_IXGBE_DCA
 117 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 118                             void *p);
 119 static struct notifier_block dca_notifier = {
 120         .notifier_call = ixgbe_notify_dca,
 121         .next          = NULL,
 122         .priority      = 0
 123 };
 124 #endif
 125
 126 #ifdef CONFIG_PCI_IOV
 127 static unsigned int max_vfs;
 128 module_param(max_vfs, uint, 0);
 129 MODULE_PARM_DESC(max_vfs,
 130                  "Maximum number of virtual functions to allocate per physical function");
 131 #endif /* CONFIG_PCI_IOV */
 132
 133 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 134 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 135 MODULE_LICENSE("GPL");
 136 MODULE_VERSION(DRV_VERSION);
 137
 138 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 139
 140 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 141 {
 142         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 143             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 144                 schedule_work(&adapter->service_task);
 145 }
 146
 147 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 148 {
 149         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 150
 151         /* flush memory to make sure state is correct before next watchog */
 152         smp_mb__before_clear_bit();
 153         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 154 }
 155
 156 struct ixgbe_reg_info {
 157         u32 ofs;
 158         char *name;
 159 };
 160
 161 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 162
 163         /* General Registers */
 164         {IXGBE_CTRL, "CTRL"},
 165         {IXGBE_STATUS, "STATUS"},
 166         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 167
 168         /* Interrupt Registers */
 169         {IXGBE_EICR, "EICR"},
 170
 171         /* RX Registers */
 172         {IXGBE_SRRCTL(0), "SRRCTL"},
 173         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 174         {IXGBE_RDLEN(0), "RDLEN"},
 175         {IXGBE_RDH(0), "RDH"},
 176         {IXGBE_RDT(0), "RDT"},
 177         {IXGBE_RXDCTL(0), "RXDCTL"},
 178         {IXGBE_RDBAL(0), "RDBAL"},
 179         {IXGBE_RDBAH(0), "RDBAH"},
 180
 181         /* TX Registers */
 182         {IXGBE_TDBAL(0), "TDBAL"},
 183         {IXGBE_TDBAH(0), "TDBAH"},
 184         {IXGBE_TDLEN(0), "TDLEN"},
 185         {IXGBE_TDH(0), "TDH"},
 186         {IXGBE_TDT(0), "TDT"},
 187         {IXGBE_TXDCTL(0), "TXDCTL"},
 188
 189         /* List Terminator */
 190         {}
 191 };
 192
 193
 194 /*
 195  * ixgbe_regdump - register printout routine
 196  */
 197 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 198 {
 199         int i = 0, j = 0;
 200         char rname[16];
 201         u32 regs[64];
 202
 203         switch (reginfo->ofs) {
 204         case IXGBE_SRRCTL(0):
 205                 for (i = 0; i < 64; i++)
 206                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 207                 break;
 208         case IXGBE_DCA_RXCTRL(0):
 209                 for (i = 0; i < 64; i++)
 210                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 211                 break;
 212         case IXGBE_RDLEN(0):
 213                 for (i = 0; i < 64; i++)
 214                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 215                 break;
 216         case IXGBE_RDH(0):
 217                 for (i = 0; i < 64; i++)
 218                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 219                 break;
 220         case IXGBE_RDT(0):
 221                 for (i = 0; i < 64; i++)
 222                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 223                 break;
 224         case IXGBE_RXDCTL(0):
 225                 for (i = 0; i < 64; i++)
 226                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 227                 break;
 228         case IXGBE_RDBAL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 231                 break;
 232         case IXGBE_RDBAH(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 235                 break;
 236         case IXGBE_TDBAL(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 239                 break;
 240         case IXGBE_TDBAH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 243                 break;
 244         case IXGBE_TDLEN(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 247                 break;
 248         case IXGBE_TDH(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 251                 break;
 252         case IXGBE_TDT(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 255                 break;
 256         case IXGBE_TXDCTL(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 259                 break;
 260         default:
 261                 pr_info("%-15s %08x\n", reginfo->name,
 262                         IXGBE_READ_REG(hw, reginfo->ofs));
 263                 return;
 264         }
 265
 266         for (i = 0; i < 8; i++) {
 267                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 268                 pr_err("%-15s", rname);
 269                 for (j = 0; j < 8; j++)
 270                         pr_cont(" %08x", regs[i*8+j]);
 271                 pr_cont("\n");
 272         }
 273
 274 }
 275
 276 /*
 277  * ixgbe_dump - Print registers, tx-rings and rx-rings
 278  */
 279 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 280 {
 281         struct net_device *netdev = adapter->netdev;
 282         struct ixgbe_hw *hw = &adapter->hw;
 283         struct ixgbe_reg_info *reginfo;
 284         int n = 0;
 285         struct ixgbe_ring *tx_ring;
 286         struct ixgbe_tx_buffer *tx_buffer_info;
 287         union ixgbe_adv_tx_desc *tx_desc;
 288         struct my_u0 { u64 a; u64 b; } *u0;
 289         struct ixgbe_ring *rx_ring;
 290         union ixgbe_adv_rx_desc *rx_desc;
 291         struct ixgbe_rx_buffer *rx_buffer_info;
 292         u32 staterr;
 293         int i = 0;
 294
 295         if (!netif_msg_hw(adapter))
 296                 return;
 297
 298         /* Print netdevice Info */
 299         if (netdev) {
 300                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 301                 pr_info("Device Name     state            "
 302                         "trans_start      last_rx\n");
 303                 pr_info("%-15s %016lX %016lX %016lX\n",
 304                         netdev->name,
 305                         netdev->state,
 306                         netdev->trans_start,
 307                         netdev->last_rx);
 308         }
 309
 310         /* Print Registers */
 311         dev_info(&adapter->pdev->dev, "Register Dump\n");
 312         pr_info(" Register Name   Value\n");
 313         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 314              reginfo->name; reginfo++) {
 315                 ixgbe_regdump(hw, reginfo);
 316         }
 317
 318         /* Print TX Ring Summary */
 319         if (!netdev || !netif_running(netdev))
 320                 goto exit;
 321
 322         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 323         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 324         for (n = 0; n < adapter->num_tx_queues; n++) {
 325                 tx_ring = adapter->tx_ring[n];
 326                 tx_buffer_info =
 327                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 328                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 329                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 330                            (u64)tx_buffer_info->dma,
 331                            tx_buffer_info->length,
 332                            tx_buffer_info->next_to_watch,
 333                            (u64)tx_buffer_info->time_stamp);
 334         }
 335
 336         /* Print TX Rings */
 337         if (!netif_msg_tx_done(adapter))
 338                 goto rx_ring_summary;
 339
 340         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 341
 342         /* Transmit Descriptor Formats
 343          *
 344          * Advanced Transmit Descriptor
 345          *   +--------------------------------------------------------------+
 346          * 0 |         Buffer Address [63:0]                                |
 347          *   +--------------------------------------------------------------+
 348          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 349          *   +--------------------------------------------------------------+
 350          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 351          */
 352
 353         for (n = 0; n < adapter->num_tx_queues; n++) {
 354                 tx_ring = adapter->tx_ring[n];
 355                 pr_info("------------------------------------\n");
 356                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 357                 pr_info("------------------------------------\n");
 358                 pr_info("T [desc]     [address 63:0  ] "
 359                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 360                         "leng  ntw timestamp        bi->skb\n");
 361
 362                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 363                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 364                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 365                         u0 = (struct my_u0 *)tx_desc;
 366                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 367                                 " %04X  %p %016llX %p", i,
 368                                 le64_to_cpu(u0->a),
 369                                 le64_to_cpu(u0->b),
 370                                 (u64)tx_buffer_info->dma,
 371                                 tx_buffer_info->length,
 372                                 tx_buffer_info->next_to_watch,
 373                                 (u64)tx_buffer_info->time_stamp,
 374                                 tx_buffer_info->skb);
 375                         if (i == tx_ring->next_to_use &&
 376                                 i == tx_ring->next_to_clean)
 377                                 pr_cont(" NTC/U\n");
 378                         else if (i == tx_ring->next_to_use)
 379                                 pr_cont(" NTU\n");
 380                         else if (i == tx_ring->next_to_clean)
 381                                 pr_cont(" NTC\n");
 382                         else
 383                                 pr_cont("\n");
 384
 385                         if (netif_msg_pktdata(adapter) &&
 386                                 tx_buffer_info->dma != 0)
 387                                 print_hex_dump(KERN_INFO, "",
 388                                         DUMP_PREFIX_ADDRESS, 16, 1,
 389                                         phys_to_virt(tx_buffer_info->dma),
 390                                         tx_buffer_info->length, true);
 391                 }
 392         }
 393
 394         /* Print RX Rings Summary */
 395 rx_ring_summary:
 396         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 397         pr_info("Queue [NTU] [NTC]\n");
 398         for (n = 0; n < adapter->num_rx_queues; n++) {
 399                 rx_ring = adapter->rx_ring[n];
 400                 pr_info("%5d %5X %5X\n",
 401                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 402         }
 403
 404         /* Print RX Rings */
 405         if (!netif_msg_rx_status(adapter))
 406                 goto exit;
 407
 408         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 409
 410         /* Advanced Receive Descriptor (Read) Format
 411          *    63                                           1        0
 412          *    +-----------------------------------------------------+
 413          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 414          *    +----------------------------------------------+------+
 415          *  8 |       Header Buffer Address [63:1]           |  DD  |
 416          *    +-----------------------------------------------------+
 417          *
 418          *
 419          * Advanced Receive Descriptor (Write-Back) Format
 420          *
 421          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 422          *   +------------------------------------------------------+
 423          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 424          *   | Checksum   Ident  |   |           |    | Type | Type |
 425          *   +------------------------------------------------------+
 426          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 427          *   +------------------------------------------------------+
 428          *   63       48 47    32 31            20 19               0
 429          */
 430         for (n = 0; n < adapter->num_rx_queues; n++) {
 431                 rx_ring = adapter->rx_ring[n];
 432                 pr_info("------------------------------------\n");
 433                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 434                 pr_info("------------------------------------\n");
 435                 pr_info("R  [desc]      [ PktBuf     A0] "
 436                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 437                         "<-- Adv Rx Read format\n");
 438                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 439                         "[vl er S cks ln] ---------------- [bi->skb] "
 440                         "<-- Adv Rx Write-Back format\n");
 441
 442                 for (i = 0; i < rx_ring->count; i++) {
 443                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 444                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 445                         u0 = (struct my_u0 *)rx_desc;
 446                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 447                         if (staterr & IXGBE_RXD_STAT_DD) {
 448                                 /* Descriptor Done */
 449                                 pr_info("RWB[0x%03X]     %016llX "
 450                                         "%016llX ---------------- %p", i,
 451                                         le64_to_cpu(u0->a),
 452                                         le64_to_cpu(u0->b),
 453                                         rx_buffer_info->skb);
 454                         } else {
 455                                 pr_info("R  [0x%03X]     %016llX "
 456                                         "%016llX %016llX %p", i,
 457                                         le64_to_cpu(u0->a),
 458                                         le64_to_cpu(u0->b),
 459                                         (u64)rx_buffer_info->dma,
 460                                         rx_buffer_info->skb);
 461
 462                                 if (netif_msg_pktdata(adapter)) {
 463                                         print_hex_dump(KERN_INFO, "",
 464                                            DUMP_PREFIX_ADDRESS, 16, 1,
 465                                            phys_to_virt(rx_buffer_info->dma),
 466                                            rx_ring->rx_buf_len, true);
 467
 468                                         if (rx_ring->rx_buf_len
 469                                                 < IXGBE_RXBUFFER_2K)
 470                                                 print_hex_dump(KERN_INFO, "",
 471                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 472                                                   phys_to_virt(
 473                                                     rx_buffer_info->page_dma +
 474                                                     rx_buffer_info->page_offset
 475                                                   ),
 476                                                   PAGE_SIZE/2, true);
 477                                 }
 478                         }
 479
 480                         if (i == rx_ring->next_to_use)
 481                                 pr_cont(" NTU\n");
 482                         else if (i == rx_ring->next_to_clean)
 483                                 pr_cont(" NTC\n");
 484                         else
 485                                 pr_cont("\n");
 486
 487                 }
 488         }
 489
 490 exit:
 491         return;
 492 }
 493
 494 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 495 {
 496         u32 ctrl_ext;
 497
 498         /* Let firmware take over control of h/w */
 499         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 500         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 501                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 502 }
 503
 504 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 505 {
 506         u32 ctrl_ext;
 507
 508         /* Let firmware know the driver has taken over */
 509         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 510         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 511                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 512 }
 513
 514 /*
 515  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 516  * @adapter: pointer to adapter struct
 517  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 518  * @queue: queue to map the corresponding interrupt to
 519  * @msix_vector: the vector to map to the corresponding queue
 520  *
 521  */
 522 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 523                            u8 queue, u8 msix_vector)
 524 {
 525         u32 ivar, index;
 526         struct ixgbe_hw *hw = &adapter->hw;
 527         switch (hw->mac.type) {
 528         case ixgbe_mac_82598EB:
 529                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 530                 if (direction == -1)
 531                         direction = 0;
 532                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 533                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 534                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 535                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 536                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 537                 break;
 538         case ixgbe_mac_82599EB:
 539         case ixgbe_mac_X540:
 540                 if (direction == -1) {
 541                         /* other causes */
 542                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 543                         index = ((queue & 1) * 8);
 544                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 545                         ivar &= ~(0xFF << index);
 546                         ivar |= (msix_vector << index);
 547                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 548                         break;
 549                 } else {
 550                         /* tx or rx causes */
 551                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 552                         index = ((16 * (queue & 1)) + (8 * direction));
 553                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 554                         ivar &= ~(0xFF << index);
 555                         ivar |= (msix_vector << index);
 556                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 557                         break;
 558                 }
 559         default:
 560                 break;
 561         }
 562 }
 563
 564 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 565                                           u64 qmask)
 566 {
 567         u32 mask;
 568
 569         switch (adapter->hw.mac.type) {
 570         case ixgbe_mac_82598EB:
 571                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 572                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 573                 break;
 574         case ixgbe_mac_82599EB:
 575         case ixgbe_mac_X540:
 576                 mask = (qmask & 0xFFFFFFFF);
 577                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 578                 mask = (qmask >> 32);
 579                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 580                 break;
 581         default:
 582                 break;
 583         }
 584 }
 585
 586 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 587                                            struct ixgbe_tx_buffer *tx_buffer)
 588 {
 589         if (tx_buffer->dma) {
 590                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 591                         dma_unmap_page(ring->dev,
 592                                        tx_buffer->dma,
 593                                        tx_buffer->length,
 594                                        DMA_TO_DEVICE);
 595                 else
 596                         dma_unmap_single(ring->dev,
 597                                          tx_buffer->dma,
 598                                          tx_buffer->length,
 599                                          DMA_TO_DEVICE);
 600         }
 601         tx_buffer->dma = 0;
 602 }
 603
 604 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 605                                       struct ixgbe_tx_buffer *tx_buffer_info)
 606 {
 607         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 608         if (tx_buffer_info->skb)
 609                 dev_kfree_skb_any(tx_buffer_info->skb);
 610         tx_buffer_info->skb = NULL;
 611         /* tx_buffer_info must be completely set up in the transmit path */
 612 }
 613
 614 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 615 {
 616         struct ixgbe_hw *hw = &adapter->hw;
 617         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 618         u32 data = 0;
 619         u32 xoff[8] = {0};
 620         int i;
 621
 622         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 623             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 624                 switch (hw->mac.type) {
 625                 case ixgbe_mac_82598EB:
 626                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 627                         break;
 628                 default:
 629                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 630                 }
 631                 hwstats->lxoffrxc += data;
 632
 633                 /* refill credits (no tx hang) if we received xoff */
 634                 if (!data)
 635                         return;
 636
 637                 for (i = 0; i < adapter->num_tx_queues; i++)
 638                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 639                                   &adapter->tx_ring[i]->state);
 640                 return;
 641         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 642                 return;
 643
 644         /* update stats for each tc, only valid with PFC enabled */
 645         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 646                 switch (hw->mac.type) {
 647                 case ixgbe_mac_82598EB:
 648                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 649                         break;
 650                 default:
 651                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 652                 }
 653                 hwstats->pxoffrxc[i] += xoff[i];
 654         }
 655
 656         /* disarm tx queues that have received xoff frames */
 657         for (i = 0; i < adapter->num_tx_queues; i++) {
 658                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 659                 u8 tc = tx_ring->dcb_tc;
 660
 661                 if (xoff[tc])
 662                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 663         }
 664 }
 665
 666 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 667 {
 668         return ring->tx_stats.completed;
 669 }
 670
 671 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 672 {
 673         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 674         struct ixgbe_hw *hw = &adapter->hw;
 675
 676         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 677         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 678
 679         if (head != tail)
 680                 return (head < tail) ?
 681                         tail - head : (tail + ring->count - head);
 682
 683         return 0;
 684 }
 685
 686 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 687 {
 688         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 689         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 690         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 691         bool ret = false;
 692
 693         clear_check_for_tx_hang(tx_ring);
 694
 695         /*
 696          * Check for a hung queue, but be thorough. This verifies
 697          * that a transmit has been completed since the previous
 698          * check AND there is at least one packet pending. The
 699          * ARMED bit is set to indicate a potential hang. The
 700          * bit is cleared if a pause frame is received to remove
 701          * false hang detection due to PFC or 802.3x frames. By
 702          * requiring this to fail twice we avoid races with
 703          * pfc clearing the ARMED bit and conditions where we
 704          * run the check_tx_hang logic with a transmit completion
 705          * pending but without time to complete it yet.
 706          */
 707         if ((tx_done_old == tx_done) && tx_pending) {
 708                 /* make sure it is true for two checks in a row */
 709                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 710                                        &tx_ring->state);
 711         } else {
 712                 /* update completed stats and continue */
 713                 tx_ring->tx_stats.tx_done_old = tx_done;
 714                 /* reset the countdown */
 715                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 716         }
 717
 718         return ret;
 719 }
 720
 721 /**
 722  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 723  * @adapter: driver private struct
 724  **/
 725 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 726 {
 727
 728         /* Do the reset outside of interrupt context */
 729         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 730                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 731                 ixgbe_service_event_schedule(adapter);
 732         }
 733 }
 734
 735 /**
 736  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 737  * @q_vector: structure containing interrupt and ring information
 738  * @tx_ring: tx ring to clean
 739  **/
 740 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 741                                struct ixgbe_ring *tx_ring)
 742 {
 743         struct ixgbe_adapter *adapter = q_vector->adapter;
 744         struct ixgbe_tx_buffer *tx_buffer;
 745         union ixgbe_adv_tx_desc *tx_desc;
 746         unsigned int total_bytes = 0, total_packets = 0;
 747         unsigned int budget = q_vector->tx.work_limit;
 748         u16 i = tx_ring->next_to_clean;
 749
 750         tx_buffer = &tx_ring->tx_buffer_info[i];
 751         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 752
 753         for (; budget; budget--) {
 754                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 755
 756                 /* if next_to_watch is not set then there is no work pending */
 757                 if (!eop_desc)
 758                         break;
 759
 760                 /* if DD is not set pending work has not been completed */
 761                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 762                         break;
 763
 764                 /* count the packet as being completed */
 765                 tx_ring->tx_stats.completed++;
 766
 767                 /* clear next_to_watch to prevent false hangs */
 768                 tx_buffer->next_to_watch = NULL;
 769
 770                 /* prevent any other reads prior to eop_desc being verified */
 771                 rmb();
 772
 773                 do {
 774                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 775                         tx_desc->wb.status = 0;
 776                         if (likely(tx_desc == eop_desc)) {
 777                                 eop_desc = NULL;
 778                                 dev_kfree_skb_any(tx_buffer->skb);
 779                                 tx_buffer->skb = NULL;
 780
 781                                 total_bytes += tx_buffer->bytecount;
 782                                 total_packets += tx_buffer->gso_segs;
 783                         }
 784
 785                         tx_buffer++;
 786                         tx_desc++;
 787                         i++;
 788                         if (unlikely(i == tx_ring->count)) {
 789                                 i = 0;
 790
 791                                 tx_buffer = tx_ring->tx_buffer_info;
 792                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 793                         }
 794
 795                 } while (eop_desc);
 796         }
 797
 798         tx_ring->next_to_clean = i;
 799         u64_stats_update_begin(&tx_ring->syncp);
 800         tx_ring->stats.bytes += total_bytes;
 801         tx_ring->stats.packets += total_packets;
 802         u64_stats_update_end(&tx_ring->syncp);
 803         q_vector->tx.total_bytes += total_bytes;
 804         q_vector->tx.total_packets += total_packets;
 805
 806         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 807                 /* schedule immediate reset if we believe we hung */
 808                 struct ixgbe_hw *hw = &adapter->hw;
 809                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 810                 e_err(drv, "Detected Tx Unit Hang\n"
 811                         "  Tx Queue             <%d>\n"
 812                         "  TDH, TDT             <%x>, <%x>\n"
 813                         "  next_to_use          <%x>\n"
 814                         "  next_to_clean        <%x>\n"
 815                         "tx_buffer_info[next_to_clean]\n"
 816                         "  time_stamp           <%lx>\n"
 817                         "  jiffies              <%lx>\n",
 818                         tx_ring->queue_index,
 819                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 820                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 821                         tx_ring->next_to_use, i,
 822                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 823
 824                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 825
 826                 e_info(probe,
 827                        "tx hang %d detected on queue %d, resetting adapter\n",
 828                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 829
 830                 /* schedule immediate reset if we believe we hung */
 831                 ixgbe_tx_timeout_reset(adapter);
 832
 833                 /* the adapter is about to reset, no point in enabling stuff */
 834                 return true;
 835         }
 836
 837 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 838         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 839                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 840                 /* Make sure that anybody stopping the queue after this
 841                  * sees the new next_to_clean.
 842                  */
 843                 smp_mb();
 844                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 845                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 846                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 847                         ++tx_ring->tx_stats.restart_queue;
 848                 }
 849         }
 850
 851         return !!budget;
 852 }
 853
 854 #ifdef CONFIG_IXGBE_DCA
 855 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 856                                 struct ixgbe_ring *rx_ring,
 857                                 int cpu)
 858 {
 859         struct ixgbe_hw *hw = &adapter->hw;
 860         u32 rxctrl;
 861         u8 reg_idx = rx_ring->reg_idx;
 862
 863         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 864         switch (hw->mac.type) {
 865         case ixgbe_mac_82598EB:
 866                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 867                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 868                 break;
 869         case ixgbe_mac_82599EB:
 870         case ixgbe_mac_X540:
 871                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 872                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 873                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 874                 break;
 875         default:
 876                 break;
 877         }
 878         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 879         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 880         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 881         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 882 }
 883
 884 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 885                                 struct ixgbe_ring *tx_ring,
 886                                 int cpu)
 887 {
 888         struct ixgbe_hw *hw = &adapter->hw;
 889         u32 txctrl;
 890         u8 reg_idx = tx_ring->reg_idx;
 891
 892         switch (hw->mac.type) {
 893         case ixgbe_mac_82598EB:
 894                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 895                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 896                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 897                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 898                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 899                 break;
 900         case ixgbe_mac_82599EB:
 901         case ixgbe_mac_X540:
 902                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 903                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 904                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 905                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 906                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 907                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 908                 break;
 909         default:
 910                 break;
 911         }
 912 }
 913
 914 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 915 {
 916         struct ixgbe_adapter *adapter = q_vector->adapter;
 917         struct ixgbe_ring *ring;
 918         int cpu = get_cpu();
 919
 920         if (q_vector->cpu == cpu)
 921                 goto out_no_update;
 922
 923         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 924                 ixgbe_update_tx_dca(adapter, ring, cpu);
 925
 926         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 927                 ixgbe_update_rx_dca(adapter, ring, cpu);
 928
 929         q_vector->cpu = cpu;
 930 out_no_update:
 931         put_cpu();
 932 }
 933
 934 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 935 {
 936         int num_q_vectors;
 937         int i;
 938
 939         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 940                 return;
 941
 942         /* always use CB2 mode, difference is masked in the CB driver */
 943         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 944
 945         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 946                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 947         else
 948                 num_q_vectors = 1;
 949
 950         for (i = 0; i < num_q_vectors; i++) {
 951                 adapter->q_vector[i]->cpu = -1;
 952                 ixgbe_update_dca(adapter->q_vector[i]);
 953         }
 954 }
 955
 956 static int __ixgbe_notify_dca(struct device *dev, void *data)
 957 {
 958         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 959         unsigned long event = *(unsigned long *)data;
 960
 961         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
 962                 return 0;
 963
 964         switch (event) {
 965         case DCA_PROVIDER_ADD:
 966                 /* if we're already enabled, don't do it again */
 967                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 968                         break;
 969                 if (dca_add_requester(dev) == 0) {
 970                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 971                         ixgbe_setup_dca(adapter);
 972                         break;
 973                 }
 974                 /* Fall Through since DCA is disabled. */
 975         case DCA_PROVIDER_REMOVE:
 976                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 977                         dca_remove_requester(dev);
 978                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 979                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 980                 }
 981                 break;
 982         }
 983
 984         return 0;
 985 }
 986 #endif /* CONFIG_IXGBE_DCA */
 987
 988 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
 989                                  struct sk_buff *skb)
 990 {
 991         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
 992 }
 993
 994 /**
 995  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
 996  * @adapter: address of board private structure
 997  * @rx_desc: advanced rx descriptor
 998  *
 999  * Returns : true if it is FCoE pkt
1000  */
1001 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1002                                     union ixgbe_adv_rx_desc *rx_desc)
1003 {
1004         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1005
1006         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1007                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1008                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1009                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1010 }
1011
1012 /**
1013  * ixgbe_receive_skb - Send a completed packet up the stack
1014  * @adapter: board private structure
1015  * @skb: packet to send up
1016  * @status: hardware indication of status of receive
1017  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1018  * @rx_desc: rx descriptor
1019  **/
1020 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1021                               struct sk_buff *skb, u8 status,
1022                               struct ixgbe_ring *ring,
1023                               union ixgbe_adv_rx_desc *rx_desc)
1024 {
1025         struct ixgbe_adapter *adapter = q_vector->adapter;
1026         struct napi_struct *napi = &q_vector->napi;
1027         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1028         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1029
1030         if (is_vlan && (tag & VLAN_VID_MASK))
1031                 __vlan_hwaccel_put_tag(skb, tag);
1032
1033         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1034                 napi_gro_receive(napi, skb);
1035         else
1036                 netif_rx(skb);
1037 }
1038
1039 /**
1040  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1041  * @adapter: address of board private structure
1042  * @status_err: hardware indication of status of receive
1043  * @skb: skb currently being received and modified
1044  * @status_err: status error value of last descriptor in packet
1045  **/
1046 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1047                                      union ixgbe_adv_rx_desc *rx_desc,
1048                                      struct sk_buff *skb,
1049                                      u32 status_err)
1050 {
1051         skb->ip_summed = CHECKSUM_NONE;
1052
1053         /* Rx csum disabled */
1054         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1055                 return;
1056
1057         /* if IP and error */
1058         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1059             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1060                 adapter->hw_csum_rx_error++;
1061                 return;
1062         }
1063
1064         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1065                 return;
1066
1067         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1068                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1069
1070                 /*
1071                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1072                  * checksum errors.
1073                  */
1074                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1075                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1076                         return;
1077
1078                 adapter->hw_csum_rx_error++;
1079                 return;
1080         }
1081
1082         /* It must be a TCP or UDP packet with a valid checksum */
1083         skb->ip_summed = CHECKSUM_UNNECESSARY;
1084 }
1085
1086 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1087 {
1088         /*
1089          * Force memory writes to complete before letting h/w
1090          * know there are new descriptors to fetch.  (Only
1091          * applicable for weak-ordered memory model archs,
1092          * such as IA-64).
1093          */
1094         wmb();
1095         writel(val, rx_ring->tail);
1096 }
1097
1098 /**
1099  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1100  * @rx_ring: ring to place buffers on
1101  * @cleaned_count: number of buffers to replace
1102  **/
1103 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1104 {
1105         union ixgbe_adv_rx_desc *rx_desc;
1106         struct ixgbe_rx_buffer *bi;
1107         struct sk_buff *skb;
1108         u16 i = rx_ring->next_to_use;
1109
1110         /* do nothing if no valid netdev defined */
1111         if (!rx_ring->netdev)
1112                 return;
1113
1114         while (cleaned_count--) {
1115                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1116                 bi = &rx_ring->rx_buffer_info[i];
1117                 skb = bi->skb;
1118
1119                 if (!skb) {
1120                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1121                                                         rx_ring->rx_buf_len);
1122                         if (!skb) {
1123                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1124                                 goto no_buffers;
1125                         }
1126                         /* initialize queue mapping */
1127                         skb_record_rx_queue(skb, rx_ring->queue_index);
1128                         bi->skb = skb;
1129                 }
1130
1131                 if (!bi->dma) {
1132                         bi->dma = dma_map_single(rx_ring->dev,
1133                                                  skb->data,
1134                                                  rx_ring->rx_buf_len,
1135                                                  DMA_FROM_DEVICE);
1136                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1137                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1138                                 bi->dma = 0;
1139                                 goto no_buffers;
1140                         }
1141                 }
1142
1143                 if (ring_is_ps_enabled(rx_ring)) {
1144                         if (!bi->page) {
1145                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1146                                 if (!bi->page) {
1147                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1148                                         goto no_buffers;
1149                                 }
1150                         }
1151
1152                         if (!bi->page_dma) {
1153                                 /* use a half page if we're re-using */
1154                                 bi->page_offset ^= PAGE_SIZE / 2;
1155                                 bi->page_dma = dma_map_page(rx_ring->dev,
1156                                                             bi->page,
1157                                                             bi->page_offset,
1158                                                             PAGE_SIZE / 2,
1159                                                             DMA_FROM_DEVICE);
1160                                 if (dma_mapping_error(rx_ring->dev,
1161                                                       bi->page_dma)) {
1162                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1163                                         bi->page_dma = 0;
1164                                         goto no_buffers;
1165                                 }
1166                         }
1167
1168                         /* Refresh the desc even if buffer_addrs didn't change
1169                          * because each write-back erases this info. */
1170                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1171                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1172                 } else {
1173                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1174                         rx_desc->read.hdr_addr = 0;
1175                 }
1176
1177                 i++;
1178                 if (i == rx_ring->count)
1179                         i = 0;
1180         }
1181
1182 no_buffers:
1183         if (rx_ring->next_to_use != i) {
1184                 rx_ring->next_to_use = i;
1185                 ixgbe_release_rx_desc(rx_ring, i);
1186         }
1187 }
1188
1189 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1190 {
1191         /* HW will not DMA in data larger than the given buffer, even if it
1192          * parses the (NFS, of course) header to be larger.  In that case, it
1193          * fills the header buffer and spills the rest into the page.
1194          */
1195         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1196         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1197                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1198         if (hlen > IXGBE_RX_HDR_SIZE)
1199                 hlen = IXGBE_RX_HDR_SIZE;
1200         return hlen;
1201 }
1202
1203 /**
1204  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1205  * @skb: pointer to the last skb in the rsc queue
1206  *
1207  * This function changes a queue full of hw rsc buffers into a completed
1208  * packet.  It uses the ->prev pointers to find the first packet and then
1209  * turns it into the frag list owner.
1210  **/
1211 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1212 {
1213         unsigned int frag_list_size = 0;
1214         unsigned int skb_cnt = 1;
1215
1216         while (skb->prev) {
1217                 struct sk_buff *prev = skb->prev;
1218                 frag_list_size += skb->len;
1219                 skb->prev = NULL;
1220                 skb = prev;
1221                 skb_cnt++;
1222         }
1223
1224         skb_shinfo(skb)->frag_list = skb->next;
1225         skb->next = NULL;
1226         skb->len += frag_list_size;
1227         skb->data_len += frag_list_size;
1228         skb->truesize += frag_list_size;
1229         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1230
1231         return skb;
1232 }
1233
1234 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1235 {
1236         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1237                 IXGBE_RXDADV_RSCCNT_MASK);
1238 }
1239
1240 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1241                                struct ixgbe_ring *rx_ring,
1242                                int budget)
1243 {
1244         struct ixgbe_adapter *adapter = q_vector->adapter;
1245         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1246         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1247         struct sk_buff *skb;
1248         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1249         const int current_node = numa_node_id();
1250 #ifdef IXGBE_FCOE
1251         int ddp_bytes = 0;
1252 #endif /* IXGBE_FCOE */
1253         u32 staterr;
1254         u16 i;
1255         u16 cleaned_count = 0;
1256         bool pkt_is_rsc = false;
1257
1258         i = rx_ring->next_to_clean;
1259         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1260         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1261
1262         while (staterr & IXGBE_RXD_STAT_DD) {
1263                 u32 upper_len = 0;
1264
1265                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1266
1267                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1268
1269                 skb = rx_buffer_info->skb;
1270                 rx_buffer_info->skb = NULL;
1271                 prefetch(skb->data);
1272
1273                 if (ring_is_rsc_enabled(rx_ring))
1274                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1275
1276                 /* linear means we are building an skb from multiple pages */
1277                 if (!skb_is_nonlinear(skb)) {
1278                         u16 hlen;
1279                         if (pkt_is_rsc &&
1280                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1281                             !skb->prev) {
1282                                 /*
1283                                  * When HWRSC is enabled, delay unmapping
1284                                  * of the first packet. It carries the
1285                                  * header information, HW may still
1286                                  * access the header after the writeback.
1287                                  * Only unmap it when EOP is reached
1288                                  */
1289                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1290                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1291                         } else {
1292                                 dma_unmap_single(rx_ring->dev,
1293                                                  rx_buffer_info->dma,
1294                                                  rx_ring->rx_buf_len,
1295                                                  DMA_FROM_DEVICE);
1296                         }
1297                         rx_buffer_info->dma = 0;
1298
1299                         if (ring_is_ps_enabled(rx_ring)) {
1300                                 hlen = ixgbe_get_hlen(rx_desc);
1301                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1302                         } else {
1303                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1304                         }
1305
1306                         skb_put(skb, hlen);
1307                 } else {
1308                         /* assume packet split since header is unmapped */
1309                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1310                 }
1311
1312                 if (upper_len) {
1313                         dma_unmap_page(rx_ring->dev,
1314                                        rx_buffer_info->page_dma,
1315                                        PAGE_SIZE / 2,
1316                                        DMA_FROM_DEVICE);
1317                         rx_buffer_info->page_dma = 0;
1318                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1319                                            rx_buffer_info->page,
1320                                            rx_buffer_info->page_offset,
1321                                            upper_len);
1322
1323                         if ((page_count(rx_buffer_info->page) == 1) &&
1324                             (page_to_nid(rx_buffer_info->page) == current_node))
1325                                 get_page(rx_buffer_info->page);
1326                         else
1327                                 rx_buffer_info->page = NULL;
1328
1329                         skb->len += upper_len;
1330                         skb->data_len += upper_len;
1331                         skb->truesize += PAGE_SIZE / 2;
1332                 }
1333
1334                 i++;
1335                 if (i == rx_ring->count)
1336                         i = 0;
1337
1338                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1339                 prefetch(next_rxd);
1340                 cleaned_count++;
1341
1342                 if (pkt_is_rsc) {
1343                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1344                                      IXGBE_RXDADV_NEXTP_SHIFT;
1345                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1346                 } else {
1347                         next_buffer = &rx_ring->rx_buffer_info[i];
1348                 }
1349
1350                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1351                         if (ring_is_ps_enabled(rx_ring)) {
1352                                 rx_buffer_info->skb = next_buffer->skb;
1353                                 rx_buffer_info->dma = next_buffer->dma;
1354                                 next_buffer->skb = skb;
1355                                 next_buffer->dma = 0;
1356                         } else {
1357                                 skb->next = next_buffer->skb;
1358                                 skb->next->prev = skb;
1359                         }
1360                         rx_ring->rx_stats.non_eop_descs++;
1361                         goto next_desc;
1362                 }
1363
1364                 if (skb->prev) {
1365                         skb = ixgbe_transform_rsc_queue(skb);
1366                         /* if we got here without RSC the packet is invalid */
1367                         if (!pkt_is_rsc) {
1368                                 __pskb_trim(skb, 0);
1369                                 rx_buffer_info->skb = skb;
1370                                 goto next_desc;
1371                         }
1372                 }
1373
1374                 if (ring_is_rsc_enabled(rx_ring)) {
1375                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1376                                 dma_unmap_single(rx_ring->dev,
1377                                                  IXGBE_RSC_CB(skb)->dma,
1378                                                  rx_ring->rx_buf_len,
1379                                                  DMA_FROM_DEVICE);
1380                                 IXGBE_RSC_CB(skb)->dma = 0;
1381                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1382                         }
1383                 }
1384                 if (pkt_is_rsc) {
1385                         if (ring_is_ps_enabled(rx_ring))
1386                                 rx_ring->rx_stats.rsc_count +=
1387                                         skb_shinfo(skb)->nr_frags;
1388                         else
1389                                 rx_ring->rx_stats.rsc_count +=
1390                                         IXGBE_RSC_CB(skb)->skb_cnt;
1391                         rx_ring->rx_stats.rsc_flush++;
1392                 }
1393
1394                 /* ERR_MASK will only have valid bits if EOP set */
1395                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1396                         dev_kfree_skb_any(skb);
1397                         goto next_desc;
1398                 }
1399
1400                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1401                 if (adapter->netdev->features & NETIF_F_RXHASH)
1402                         ixgbe_rx_hash(rx_desc, skb);
1403
1404                 /* probably a little skewed due to removing CRC */
1405                 total_rx_bytes += skb->len;
1406                 total_rx_packets++;
1407
1408                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1409 #ifdef IXGBE_FCOE
1410                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1411                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1412                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1413                                                    staterr);
1414                         if (!ddp_bytes) {
1415                                 dev_kfree_skb_any(skb);
1416                                 goto next_desc;
1417                         }
1418                 }
1419 #endif /* IXGBE_FCOE */
1420                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1421
1422                 budget--;
1423 next_desc:
1424                 rx_desc->wb.upper.status_error = 0;
1425
1426                 if (!budget)
1427                         break;
1428
1429                 /* return some buffers to hardware, one at a time is too slow */
1430                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1431                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1432                         cleaned_count = 0;
1433                 }
1434
1435                 /* use prefetched values */
1436                 rx_desc = next_rxd;
1437                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1438         }
1439
1440         rx_ring->next_to_clean = i;
1441         cleaned_count = ixgbe_desc_unused(rx_ring);
1442
1443         if (cleaned_count)
1444                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1445
1446 #ifdef IXGBE_FCOE
1447         /* include DDPed FCoE data */
1448         if (ddp_bytes > 0) {
1449                 unsigned int mss;
1450
1451                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1452                         sizeof(struct fc_frame_header) -
1453                         sizeof(struct fcoe_crc_eof);
1454                 if (mss > 512)
1455                         mss &= ~511;
1456                 total_rx_bytes += ddp_bytes;
1457                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1458         }
1459 #endif /* IXGBE_FCOE */
1460
1461         u64_stats_update_begin(&rx_ring->syncp);
1462         rx_ring->stats.packets += total_rx_packets;
1463         rx_ring->stats.bytes += total_rx_bytes;
1464         u64_stats_update_end(&rx_ring->syncp);
1465         q_vector->rx.total_packets += total_rx_packets;
1466         q_vector->rx.total_bytes += total_rx_bytes;
1467
1468         return !!budget;
1469 }
1470
1471 /**
1472  * ixgbe_configure_msix - Configure MSI-X hardware
1473  * @adapter: board private structure
1474  *
1475  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1476  * interrupts.
1477  **/
1478 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1479 {
1480         struct ixgbe_q_vector *q_vector;
1481         int q_vectors, v_idx;
1482         u32 mask;
1483
1484         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1485
1486         /* Populate MSIX to EITR Select */
1487         if (adapter->num_vfs > 32) {
1488                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1489                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1490         }
1491
1492         /*
1493          * Populate the IVAR table and set the ITR values to the
1494          * corresponding register.
1495          */
1496         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1497                 struct ixgbe_ring *ring;
1498                 q_vector = adapter->q_vector[v_idx];
1499
1500                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1501                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1502
1503                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1504                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1505
1506                 if (q_vector->tx.ring && !q_vector->rx.ring) {
1507                         /* tx only vector */
1508                         if (adapter->tx_itr_setting == 1)
1509                                 q_vector->itr = IXGBE_10K_ITR;
1510                         else
1511                                 q_vector->itr = adapter->tx_itr_setting;
1512                 } else {
1513                         /* rx or rx/tx vector */
1514                         if (adapter->rx_itr_setting == 1)
1515                                 q_vector->itr = IXGBE_20K_ITR;
1516                         else
1517                                 q_vector->itr = adapter->rx_itr_setting;
1518                 }
1519
1520                 ixgbe_write_eitr(q_vector);
1521         }
1522
1523         switch (adapter->hw.mac.type) {
1524         case ixgbe_mac_82598EB:
1525                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1526                                v_idx);
1527                 break;
1528         case ixgbe_mac_82599EB:
1529         case ixgbe_mac_X540:
1530                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1531                 break;
1532         default:
1533                 break;
1534         }
1535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1536
1537         /* set up to autoclear timer, and the vectors */
1538         mask = IXGBE_EIMS_ENABLE_MASK;
1539         mask &= ~(IXGBE_EIMS_OTHER |
1540                   IXGBE_EIMS_MAILBOX |
1541                   IXGBE_EIMS_LSC);
1542
1543         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1544 }
1545
1546 enum latency_range {
1547         lowest_latency = 0,
1548         low_latency = 1,
1549         bulk_latency = 2,
1550         latency_invalid = 255
1551 };
1552
1553 /**
1554  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1555  * @q_vector: structure containing interrupt and ring information
1556  * @ring_container: structure containing ring performance data
1557  *
1558  *      Stores a new ITR value based on packets and byte
1559  *      counts during the last interrupt.  The advantage of per interrupt
1560  *      computation is faster updates and more accurate ITR for the current
1561  *      traffic pattern.  Constants in this function were computed
1562  *      based on theoretical maximum wire speed and thresholds were set based
1563  *      on testing data as well as attempting to minimize response time
1564  *      while increasing bulk throughput.
1565  *      this functionality is controlled by the InterruptThrottleRate module
1566  *      parameter (see ixgbe_param.c)
1567  **/
1568 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1569                              struct ixgbe_ring_container *ring_container)
1570 {
1571         u64 bytes_perint;
1572         struct ixgbe_adapter *adapter = q_vector->adapter;
1573         int bytes = ring_container->total_bytes;
1574         int packets = ring_container->total_packets;
1575         u32 timepassed_us;
1576         u8 itr_setting = ring_container->itr;
1577
1578         if (packets == 0)
1579                 return;
1580
1581         /* simple throttlerate management
1582          *    0-20MB/s lowest (100000 ints/s)
1583          *   20-100MB/s low   (20000 ints/s)
1584          *  100-1249MB/s bulk (8000 ints/s)
1585          */
1586         /* what was last interrupt timeslice? */
1587         timepassed_us = q_vector->itr >> 2;
1588         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1589
1590         switch (itr_setting) {
1591         case lowest_latency:
1592                 if (bytes_perint > adapter->eitr_low)
1593                         itr_setting = low_latency;
1594                 break;
1595         case low_latency:
1596                 if (bytes_perint > adapter->eitr_high)
1597                         itr_setting = bulk_latency;
1598                 else if (bytes_perint <= adapter->eitr_low)
1599                         itr_setting = lowest_latency;
1600                 break;
1601         case bulk_latency:
1602                 if (bytes_perint <= adapter->eitr_high)
1603                         itr_setting = low_latency;
1604                 break;
1605         }
1606
1607         /* clear work counters since we have the values we need */
1608         ring_container->total_bytes = 0;
1609         ring_container->total_packets = 0;
1610
1611         /* write updated itr to ring container */
1612         ring_container->itr = itr_setting;
1613 }
1614
1615 /**
1616  * ixgbe_write_eitr - write EITR register in hardware specific way
1617  * @q_vector: structure containing interrupt and ring information
1618  *
1619  * This function is made to be called by ethtool and by the driver
1620  * when it needs to update EITR registers at runtime.  Hardware
1621  * specific quirks/differences are taken care of here.
1622  */
1623 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1624 {
1625         struct ixgbe_adapter *adapter = q_vector->adapter;
1626         struct ixgbe_hw *hw = &adapter->hw;
1627         int v_idx = q_vector->v_idx;
1628         u32 itr_reg = q_vector->itr;
1629
1630         switch (adapter->hw.mac.type) {
1631         case ixgbe_mac_82598EB:
1632                 /* must write high and low 16 bits to reset counter */
1633                 itr_reg |= (itr_reg << 16);
1634                 break;
1635         case ixgbe_mac_82599EB:
1636         case ixgbe_mac_X540:
1637                 /*
1638                  * set the WDIS bit to not clear the timer bits and cause an
1639                  * immediate assertion of the interrupt
1640                  */
1641                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1642                 break;
1643         default:
1644                 break;
1645         }
1646         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1647 }
1648
1649 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1650 {
1651         u32 new_itr = q_vector->itr;
1652         u8 current_itr;
1653
1654         ixgbe_update_itr(q_vector, &q_vector->tx);
1655         ixgbe_update_itr(q_vector, &q_vector->rx);
1656
1657         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1658
1659         switch (current_itr) {
1660         /* counts and packets in update_itr are dependent on these numbers */
1661         case lowest_latency:
1662                 new_itr = IXGBE_100K_ITR;
1663                 break;
1664         case low_latency:
1665                 new_itr = IXGBE_20K_ITR;
1666                 break;
1667         case bulk_latency:
1668                 new_itr = IXGBE_8K_ITR;
1669                 break;
1670         default:
1671                 break;
1672         }
1673
1674         if (new_itr != q_vector->itr) {
1675                 /* do an exponential smoothing */
1676                 new_itr = (10 * new_itr * q_vector->itr) /
1677                           ((9 * new_itr) + q_vector->itr);
1678
1679                 /* save the algorithm value here */
1680                 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1681
1682                 ixgbe_write_eitr(q_vector);
1683         }
1684 }
1685
1686 /**
1687  * ixgbe_check_overtemp_subtask - check for over tempurature
1688  * @adapter: pointer to adapter
1689  **/
1690 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1691 {
1692         struct ixgbe_hw *hw = &adapter->hw;
1693         u32 eicr = adapter->interrupt_event;
1694
1695         if (test_bit(__IXGBE_DOWN, &adapter->state))
1696                 return;
1697
1698         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1699             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1700                 return;
1701
1702         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1703
1704         switch (hw->device_id) {
1705         case IXGBE_DEV_ID_82599_T3_LOM:
1706                 /*
1707                  * Since the warning interrupt is for both ports
1708                  * we don't have to check if:
1709                  *  - This interrupt wasn't for our port.
1710                  *  - We may have missed the interrupt so always have to
1711                  *    check if we  got a LSC
1712                  */
1713                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1714                     !(eicr & IXGBE_EICR_LSC))
1715                         return;
1716
1717                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1718                         u32 autoneg;
1719                         bool link_up = false;
1720
1721                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1722
1723                         if (link_up)
1724                                 return;
1725                 }
1726
1727                 /* Check if this is not due to overtemp */
1728                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1729                         return;
1730
1731                 break;
1732         default:
1733                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1734                         return;
1735                 break;
1736         }
1737         e_crit(drv,
1738                "Network adapter has been stopped because it has over heated. "
1739                "Restart the computer. If the problem persists, "
1740                "power off the system and replace the adapter\n");
1741
1742         adapter->interrupt_event = 0;
1743 }
1744
1745 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1746 {
1747         struct ixgbe_hw *hw = &adapter->hw;
1748
1749         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1750             (eicr & IXGBE_EICR_GPI_SDP1)) {
1751                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1752                 /* write to clear the interrupt */
1753                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1754         }
1755 }
1756
1757 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1758 {
1759         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1760                 return;
1761
1762         switch (adapter->hw.mac.type) {
1763         case ixgbe_mac_82599EB:
1764                 /*
1765                  * Need to check link state so complete overtemp check
1766                  * on service task
1767                  */
1768                 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1769                     (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1770                         adapter->interrupt_event = eicr;
1771                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1772                         ixgbe_service_event_schedule(adapter);
1773                         return;
1774                 }
1775                 return;
1776         case ixgbe_mac_X540:
1777                 if (!(eicr & IXGBE_EICR_TS))
1778                         return;
1779                 break;
1780         default:
1781                 return;
1782         }
1783
1784         e_crit(drv,
1785                "Network adapter has been stopped because it has over heated. "
1786                "Restart the computer. If the problem persists, "
1787                "power off the system and replace the adapter\n");
1788 }
1789
1790 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1791 {
1792         struct ixgbe_hw *hw = &adapter->hw;
1793
1794         if (eicr & IXGBE_EICR_GPI_SDP2) {
1795                 /* Clear the interrupt */
1796                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1797                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1798                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1799                         ixgbe_service_event_schedule(adapter);
1800                 }
1801         }
1802
1803         if (eicr & IXGBE_EICR_GPI_SDP1) {
1804                 /* Clear the interrupt */
1805                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1806                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1807                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1808                         ixgbe_service_event_schedule(adapter);
1809                 }
1810         }
1811 }
1812
1813 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1814 {
1815         struct ixgbe_hw *hw = &adapter->hw;
1816
1817         adapter->lsc_int++;
1818         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1819         adapter->link_check_timeout = jiffies;
1820         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1821                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1822                 IXGBE_WRITE_FLUSH(hw);
1823                 ixgbe_service_event_schedule(adapter);
1824         }
1825 }
1826
1827 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1828                                            u64 qmask)
1829 {
1830         u32 mask;
1831         struct ixgbe_hw *hw = &adapter->hw;
1832
1833         switch (hw->mac.type) {
1834         case ixgbe_mac_82598EB:
1835                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1837                 break;
1838         case ixgbe_mac_82599EB:
1839         case ixgbe_mac_X540:
1840                 mask = (qmask & 0xFFFFFFFF);
1841                 if (mask)
1842                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1843                 mask = (qmask >> 32);
1844                 if (mask)
1845                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1846                 break;
1847         default:
1848                 break;
1849         }
1850         /* skip the flush */
1851 }
1852
1853 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1854                                             u64 qmask)
1855 {
1856         u32 mask;
1857         struct ixgbe_hw *hw = &adapter->hw;
1858
1859         switch (hw->mac.type) {
1860         case ixgbe_mac_82598EB:
1861                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1863                 break;
1864         case ixgbe_mac_82599EB:
1865         case ixgbe_mac_X540:
1866                 mask = (qmask & 0xFFFFFFFF);
1867                 if (mask)
1868                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1869                 mask = (qmask >> 32);
1870                 if (mask)
1871                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1872                 break;
1873         default:
1874                 break;
1875         }
1876         /* skip the flush */
1877 }
1878
1879 /**
1880  * ixgbe_irq_enable - Enable default interrupt generation settings
1881  * @adapter: board private structure
1882  **/
1883 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1884                                     bool flush)
1885 {
1886         u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1887
1888         /* don't reenable LSC while waiting for link */
1889         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1890                 mask &= ~IXGBE_EIMS_LSC;
1891
1892         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1893                 switch (adapter->hw.mac.type) {
1894                 case ixgbe_mac_82599EB:
1895                         mask |= IXGBE_EIMS_GPI_SDP0;
1896                         break;
1897                 case ixgbe_mac_X540:
1898                         mask |= IXGBE_EIMS_TS;
1899                         break;
1900                 default:
1901                         break;
1902                 }
1903         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1904                 mask |= IXGBE_EIMS_GPI_SDP1;
1905         switch (adapter->hw.mac.type) {
1906         case ixgbe_mac_82599EB:
1907                 mask |= IXGBE_EIMS_GPI_SDP1;
1908                 mask |= IXGBE_EIMS_GPI_SDP2;
1909         case ixgbe_mac_X540:
1910                 mask |= IXGBE_EIMS_ECC;
1911                 mask |= IXGBE_EIMS_MAILBOX;
1912                 break;
1913         default:
1914                 break;
1915         }
1916         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1917             !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1918                 mask |= IXGBE_EIMS_FLOW_DIR;
1919
1920         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1921         if (queues)
1922                 ixgbe_irq_enable_queues(adapter, ~0);
1923         if (flush)
1924                 IXGBE_WRITE_FLUSH(&adapter->hw);
1925 }
1926
1927 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1928 {
1929         struct ixgbe_adapter *adapter = data;
1930         struct ixgbe_hw *hw = &adapter->hw;
1931         u32 eicr;
1932
1933         /*
1934          * Workaround for Silicon errata.  Use clear-by-write instead
1935          * of clear-by-read.  Reading with EICS will return the
1936          * interrupt causes without clearing, which later be done
1937          * with the write to EICR.
1938          */
1939         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1940         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1941
1942         if (eicr & IXGBE_EICR_LSC)
1943                 ixgbe_check_lsc(adapter);
1944
1945         if (eicr & IXGBE_EICR_MAILBOX)
1946                 ixgbe_msg_task(adapter);
1947
1948         switch (hw->mac.type) {
1949         case ixgbe_mac_82599EB:
1950         case ixgbe_mac_X540:
1951                 if (eicr & IXGBE_EICR_ECC)
1952                         e_info(link, "Received unrecoverable ECC Err, please "
1953                                "reboot\n");
1954                 /* Handle Flow Director Full threshold interrupt */
1955                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1956                         int reinit_count = 0;
1957                         int i;
1958                         for (i = 0; i < adapter->num_tx_queues; i++) {
1959                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1960                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1961                                                        &ring->state))
1962                                         reinit_count++;
1963                         }
1964                         if (reinit_count) {
1965                                 /* no more flow director interrupts until after init */
1966                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1967                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1968                                 ixgbe_service_event_schedule(adapter);
1969                         }
1970                 }
1971                 ixgbe_check_sfp_event(adapter, eicr);
1972                 ixgbe_check_overtemp_event(adapter, eicr);
1973                 break;
1974         default:
1975                 break;
1976         }
1977
1978         ixgbe_check_fan_failure(adapter, eicr);
1979
1980         /* re-enable the original interrupt state, no lsc, no queues */
1981         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1982                 ixgbe_irq_enable(adapter, false, false);
1983
1984         return IRQ_HANDLED;
1985 }
1986
1987 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1988 {
1989         struct ixgbe_q_vector *q_vector = data;
1990
1991         /* EIAM disabled interrupts (on this vector) for us */
1992
1993         if (q_vector->rx.ring || q_vector->tx.ring)
1994                 napi_schedule(&q_vector->napi);
1995
1996         return IRQ_HANDLED;
1997 }
1998
1999 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2000                                      int r_idx)
2001 {
2002         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2003         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2004
2005         rx_ring->q_vector = q_vector;
2006         rx_ring->next = q_vector->rx.ring;
2007         q_vector->rx.ring = rx_ring;
2008         q_vector->rx.count++;
2009 }
2010
2011 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2012                                      int t_idx)
2013 {
2014         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2015         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2016
2017         tx_ring->q_vector = q_vector;
2018         tx_ring->next = q_vector->tx.ring;
2019         q_vector->tx.ring = tx_ring;
2020         q_vector->tx.count++;
2021         q_vector->tx.work_limit = a->tx_work_limit;
2022 }
2023
2024 /**
2025  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2026  * @adapter: board private structure to initialize
2027  *
2028  * This function maps descriptor rings to the queue-specific vectors
2029  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2030  * one vector per ring/queue, but on a constrained vector budget, we
2031  * group the rings as "efficiently" as possible.  You would add new
2032  * mapping configurations in here.
2033  **/
2034 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2035 {
2036         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2037         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2038         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2039         int v_start = 0;
2040
2041         /* only one q_vector if MSI-X is disabled. */
2042         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2043                 q_vectors = 1;
2044
2045         /*
2046          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2047          * group them so there are multiple queues per vector.
2048          *
2049          * Re-adjusting *qpv takes care of the remainder.
2050          */
2051         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2052                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2053                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2054                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2055         }
2056
2057         /*
2058          * If there are not enough q_vectors for each ring to have it's own
2059          * vector then we must pair up Rx/Tx on a each vector
2060          */
2061         if ((v_start + txr_remaining) > q_vectors)
2062                 v_start = 0;
2063
2064         for (; v_start < q_vectors && txr_remaining; v_start++) {
2065                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2066                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2067                         map_vector_to_txq(adapter, v_start, txr_idx);
2068         }
2069 }
2070
2071 /**
2072  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2073  * @adapter: board private structure
2074  *
2075  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2076  * interrupts from the kernel.
2077  **/
2078 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2079 {
2080         struct net_device *netdev = adapter->netdev;
2081         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2082         int vector, err;
2083         int ri = 0, ti = 0;
2084
2085         for (vector = 0; vector < q_vectors; vector++) {
2086                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2087                 struct msix_entry *entry = &adapter->msix_entries[vector];
2088
2089                 if (q_vector->tx.ring && q_vector->rx.ring) {
2090                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2091                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2092                         ti++;
2093                 } else if (q_vector->rx.ring) {
2094                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2095                                  "%s-%s-%d", netdev->name, "rx", ri++);
2096                 } else if (q_vector->tx.ring) {
2097                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2098                                  "%s-%s-%d", netdev->name, "tx", ti++);
2099                 } else {
2100                         /* skip this unused q_vector */
2101                         continue;
2102                 }
2103                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2104                                   q_vector->name, q_vector);
2105                 if (err) {
2106                         e_err(probe, "request_irq failed for MSIX interrupt "
2107                               "Error: %d\n", err);
2108                         goto free_queue_irqs;
2109                 }
2110                 /* If Flow Director is enabled, set interrupt affinity */
2111                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2112                         /* assign the mask for this irq */
2113                         irq_set_affinity_hint(entry->vector,
2114                                               q_vector->affinity_mask);
2115                 }
2116         }
2117
2118         err = request_irq(adapter->msix_entries[vector].vector,
2119                           ixgbe_msix_other, 0, netdev->name, adapter);
2120         if (err) {
2121                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2122                 goto free_queue_irqs;
2123         }
2124
2125         return 0;
2126
2127 free_queue_irqs:
2128         while (vector) {
2129                 vector--;
2130                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2131                                       NULL);
2132                 free_irq(adapter->msix_entries[vector].vector,
2133                          adapter->q_vector[vector]);
2134         }
2135         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2136         pci_disable_msix(adapter->pdev);
2137         kfree(adapter->msix_entries);
2138         adapter->msix_entries = NULL;
2139         return err;
2140 }
2141
2142 /**
2143  * ixgbe_intr - legacy mode Interrupt Handler
2144  * @irq: interrupt number
2145  * @data: pointer to a network interface device structure
2146  **/
2147 static irqreturn_t ixgbe_intr(int irq, void *data)
2148 {
2149         struct ixgbe_adapter *adapter = data;
2150         struct ixgbe_hw *hw = &adapter->hw;
2151         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2152         u32 eicr;
2153
2154         /*
2155          * Workaround for silicon errata on 82598.  Mask the interrupts
2156          * before the read of EICR.
2157          */
2158         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2159
2160         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2161          * therefore no explict interrupt disable is necessary */
2162         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2163         if (!eicr) {
2164                 /*
2165                  * shared interrupt alert!
2166                  * make sure interrupts are enabled because the read will
2167                  * have disabled interrupts due to EIAM
2168                  * finish the workaround of silicon errata on 82598.  Unmask
2169                  * the interrupt that we masked before the EICR read.
2170                  */
2171                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2172                         ixgbe_irq_enable(adapter, true, true);
2173                 return IRQ_NONE;        /* Not our interrupt */
2174         }
2175
2176         if (eicr & IXGBE_EICR_LSC)
2177                 ixgbe_check_lsc(adapter);
2178
2179         switch (hw->mac.type) {
2180         case ixgbe_mac_82599EB:
2181                 ixgbe_check_sfp_event(adapter, eicr);
2182                 /* Fall through */
2183         case ixgbe_mac_X540:
2184                 if (eicr & IXGBE_EICR_ECC)
2185                         e_info(link, "Received unrecoverable ECC err, please "
2186                                      "reboot\n");
2187                 ixgbe_check_overtemp_event(adapter, eicr);
2188                 break;
2189         default:
2190                 break;
2191         }
2192
2193         ixgbe_check_fan_failure(adapter, eicr);
2194
2195         if (napi_schedule_prep(&(q_vector->napi))) {
2196                 /* would disable interrupts here but EIAM disabled it */
2197                 __napi_schedule(&(q_vector->napi));
2198         }
2199
2200         /*
2201          * re-enable link(maybe) and non-queue interrupts, no flush.
2202          * ixgbe_poll will re-enable the queue interrupts
2203          */
2204
2205         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2206                 ixgbe_irq_enable(adapter, false, false);
2207
2208         return IRQ_HANDLED;
2209 }
2210
2211 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2212 {
2213         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2214         int i;
2215
2216         /* legacy and MSI only use one vector */
2217         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2218                 q_vectors = 1;
2219
2220         for (i = 0; i < adapter->num_rx_queues; i++) {
2221                 adapter->rx_ring[i]->q_vector = NULL;
2222                 adapter->rx_ring[i]->next = NULL;
2223         }
2224         for (i = 0; i < adapter->num_tx_queues; i++) {
2225                 adapter->tx_ring[i]->q_vector = NULL;
2226                 adapter->tx_ring[i]->next = NULL;
2227         }
2228
2229         for (i = 0; i < q_vectors; i++) {
2230                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2231                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2232                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2233         }
2234 }
2235
2236 /**
2237  * ixgbe_request_irq - initialize interrupts
2238  * @adapter: board private structure
2239  *
2240  * Attempts to configure interrupts using the best available
2241  * capabilities of the hardware and kernel.
2242  **/
2243 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2244 {
2245         struct net_device *netdev = adapter->netdev;
2246         int err;
2247
2248         /* map all of the rings to the q_vectors */
2249         ixgbe_map_rings_to_vectors(adapter);
2250
2251         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2252                 err = ixgbe_request_msix_irqs(adapter);
2253         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2254                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2255                                   netdev->name, adapter);
2256         else
2257                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2258                                   netdev->name, adapter);
2259
2260         if (err) {
2261                 e_err(probe, "request_irq failed, Error %d\n", err);
2262
2263                 /* place q_vectors and rings back into a known good state */
2264                 ixgbe_reset_q_vectors(adapter);
2265         }
2266
2267         return err;
2268 }
2269
2270 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2271 {
2272         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2273                 int i, q_vectors;
2274
2275                 q_vectors = adapter->num_msix_vectors;
2276                 i = q_vectors - 1;
2277                 free_irq(adapter->msix_entries[i].vector, adapter);
2278                 i--;
2279
2280                 for (; i >= 0; i--) {
2281                         /* free only the irqs that were actually requested */
2282                         if (!adapter->q_vector[i]->rx.ring &&
2283                             !adapter->q_vector[i]->tx.ring)
2284                                 continue;
2285
2286                         /* clear the affinity_mask in the IRQ descriptor */
2287                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2288                                               NULL);
2289
2290                         free_irq(adapter->msix_entries[i].vector,
2291                                  adapter->q_vector[i]);
2292                 }
2293         } else {
2294                 free_irq(adapter->pdev->irq, adapter);
2295         }
2296
2297         /* clear q_vector state information */
2298         ixgbe_reset_q_vectors(adapter);
2299 }
2300
2301 /**
2302  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2303  * @adapter: board private structure
2304  **/
2305 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2306 {
2307         switch (adapter->hw.mac.type) {
2308         case ixgbe_mac_82598EB:
2309                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2310                 break;
2311         case ixgbe_mac_82599EB:
2312         case ixgbe_mac_X540:
2313                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2314                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2315                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2316                 break;
2317         default:
2318                 break;
2319         }
2320         IXGBE_WRITE_FLUSH(&adapter->hw);
2321         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2322                 int i;
2323                 for (i = 0; i < adapter->num_msix_vectors; i++)
2324                         synchronize_irq(adapter->msix_entries[i].vector);
2325         } else {
2326                 synchronize_irq(adapter->pdev->irq);
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2332  *
2333  **/
2334 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2335 {
2336         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2337
2338         /* rx/tx vector */
2339         if (adapter->rx_itr_setting == 1)
2340                 q_vector->itr = IXGBE_20K_ITR;
2341         else
2342                 q_vector->itr = adapter->rx_itr_setting;
2343
2344         ixgbe_write_eitr(q_vector);
2345
2346         ixgbe_set_ivar(adapter, 0, 0, 0);
2347         ixgbe_set_ivar(adapter, 1, 0, 0);
2348
2349         e_info(hw, "Legacy interrupt IVAR setup done\n");
2350 }
2351
2352 /**
2353  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2354  * @adapter: board private structure
2355  * @ring: structure containing ring specific data
2356  *
2357  * Configure the Tx descriptor ring after a reset.
2358  **/
2359 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2360                              struct ixgbe_ring *ring)
2361 {
2362         struct ixgbe_hw *hw = &adapter->hw;
2363         u64 tdba = ring->dma;
2364         int wait_loop = 10;
2365         u32 txdctl = IXGBE_TXDCTL_ENABLE;
2366         u8 reg_idx = ring->reg_idx;
2367
2368         /* disable queue to avoid issues while updating state */
2369         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2370         IXGBE_WRITE_FLUSH(hw);
2371
2372         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2373                         (tdba & DMA_BIT_MASK(32)));
2374         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2375         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2376                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2377         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2378         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2379         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2380
2381         /*
2382          * set WTHRESH to encourage burst writeback, it should not be set
2383          * higher than 1 when ITR is 0 as it could cause false TX hangs
2384          *
2385          * In order to avoid issues WTHRESH + PTHRESH should always be equal
2386          * to or less than the number of on chip descriptors, which is
2387          * currently 40.
2388          */
2389         if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2390                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
2391         else
2392                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
2393
2394         /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2395         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
2396                    32;          /* PTHRESH = 32 */
2397
2398         /* reinitialize flowdirector state */
2399         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2400             adapter->atr_sample_rate) {
2401                 ring->atr_sample_rate = adapter->atr_sample_rate;
2402                 ring->atr_count = 0;
2403                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2404         } else {
2405                 ring->atr_sample_rate = 0;
2406         }
2407
2408         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2409
2410         /* enable queue */
2411         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2412
2413         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2414         if (hw->mac.type == ixgbe_mac_82598EB &&
2415             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2416                 return;
2417
2418         /* poll to verify queue is enabled */
2419         do {
2420                 usleep_range(1000, 2000);
2421                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2422         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2423         if (!wait_loop)
2424                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2425 }
2426
2427 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2428 {
2429         struct ixgbe_hw *hw = &adapter->hw;
2430         u32 rttdcs;
2431         u32 reg;
2432         u8 tcs = netdev_get_num_tc(adapter->netdev);
2433
2434         if (hw->mac.type == ixgbe_mac_82598EB)
2435                 return;
2436
2437         /* disable the arbiter while setting MTQC */
2438         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2439         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2440         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2441
2442         /* set transmit pool layout */
2443         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2444         case (IXGBE_FLAG_SRIOV_ENABLED):
2445                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2446                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2447                 break;
2448         default:
2449                 if (!tcs)
2450                         reg = IXGBE_MTQC_64Q_1PB;
2451                 else if (tcs <= 4)
2452                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2453                 else
2454                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2455
2456                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2457
2458                 /* Enable Security TX Buffer IFG for multiple pb */
2459                 if (tcs) {
2460                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2461                         reg |= IXGBE_SECTX_DCB;
2462                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2463                 }
2464                 break;
2465         }
2466
2467         /* re-enable the arbiter */
2468         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2469         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2470 }
2471
2472 /**
2473  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2474  * @adapter: board private structure
2475  *
2476  * Configure the Tx unit of the MAC after a reset.
2477  **/
2478 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2479 {
2480         struct ixgbe_hw *hw = &adapter->hw;
2481         u32 dmatxctl;
2482         u32 i;
2483
2484         ixgbe_setup_mtqc(adapter);
2485
2486         if (hw->mac.type != ixgbe_mac_82598EB) {
2487                 /* DMATXCTL.EN must be before Tx queues are enabled */
2488                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2489                 dmatxctl |= IXGBE_DMATXCTL_TE;
2490                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2491         }
2492
2493         /* Setup the HW Tx Head and Tail descriptor pointers */
2494         for (i = 0; i < adapter->num_tx_queues; i++)
2495                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2496 }
2497
2498 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2499
2500 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2501                                    struct ixgbe_ring *rx_ring)
2502 {
2503         u32 srrctl;
2504         u8 reg_idx = rx_ring->reg_idx;
2505
2506         switch (adapter->hw.mac.type) {
2507         case ixgbe_mac_82598EB: {
2508                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2509                 const int mask = feature[RING_F_RSS].mask;
2510                 reg_idx = reg_idx & mask;
2511         }
2512                 break;
2513         case ixgbe_mac_82599EB:
2514         case ixgbe_mac_X540:
2515         default:
2516                 break;
2517         }
2518
2519         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2520
2521         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2522         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2523         if (adapter->num_vfs)
2524                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2525
2526         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2527                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2528
2529         if (ring_is_ps_enabled(rx_ring)) {
2530 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2531                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2532 #else
2533                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2534 #endif
2535                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2536         } else {
2537                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2538                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2539                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2540         }
2541
2542         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2543 }
2544
2545 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2546 {
2547         struct ixgbe_hw *hw = &adapter->hw;
2548         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2549                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2550                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2551         u32 mrqc = 0, reta = 0;
2552         u32 rxcsum;
2553         int i, j;
2554         u8 tcs = netdev_get_num_tc(adapter->netdev);
2555         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2556
2557         if (tcs)
2558                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2559
2560         /* Fill out hash function seeds */
2561         for (i = 0; i < 10; i++)
2562                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2563
2564         /* Fill out redirection table */
2565         for (i = 0, j = 0; i < 128; i++, j++) {
2566                 if (j == maxq)
2567                         j = 0;
2568                 /* reta = 4-byte sliding window of
2569                  * 0x00..(indices-1)(indices-1)00..etc. */
2570                 reta = (reta << 8) | (j * 0x11);
2571                 if ((i & 3) == 3)
2572                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2573         }
2574
2575         /* Disable indicating checksum in descriptor, enables RSS hash */
2576         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2577         rxcsum |= IXGBE_RXCSUM_PCSD;
2578         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2579
2580         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2581             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2582                 mrqc = IXGBE_MRQC_RSSEN;
2583         } else {
2584                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2585                                              | IXGBE_FLAG_SRIOV_ENABLED);
2586
2587                 switch (mask) {
2588                 case (IXGBE_FLAG_RSS_ENABLED):
2589                         if (!tcs)
2590                                 mrqc = IXGBE_MRQC_RSSEN;
2591                         else if (tcs <= 4)
2592                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2593                         else
2594                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2595                         break;
2596                 case (IXGBE_FLAG_SRIOV_ENABLED):
2597                         mrqc = IXGBE_MRQC_VMDQEN;
2598                         break;
2599                 default:
2600                         break;
2601                 }
2602         }
2603
2604         /* Perform hash on these packet types */
2605         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2606               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2607               | IXGBE_MRQC_RSS_FIELD_IPV6
2608               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2609
2610         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2611 }
2612
2613 /**
2614  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2615  * @adapter:    address of board private structure
2616  * @index:      index of ring to set
2617  **/
2618 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2619                                    struct ixgbe_ring *ring)
2620 {
2621         struct ixgbe_hw *hw = &adapter->hw;
2622         u32 rscctrl;
2623         int rx_buf_len;
2624         u8 reg_idx = ring->reg_idx;
2625
2626         if (!ring_is_rsc_enabled(ring))
2627                 return;
2628
2629         rx_buf_len = ring->rx_buf_len;
2630         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2631         rscctrl |= IXGBE_RSCCTL_RSCEN;
2632         /*
2633          * we must limit the number of descriptors so that the
2634          * total size of max desc * buf_len is not greater
2635          * than 65535
2636          */
2637         if (ring_is_ps_enabled(ring)) {
2638 #if (MAX_SKB_FRAGS > 16)
2639                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2640 #elif (MAX_SKB_FRAGS > 8)
2641                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2642 #elif (MAX_SKB_FRAGS > 4)
2643                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2644 #else
2645                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2646 #endif
2647         } else {
2648                 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2649                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650                 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2651                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652                 else
2653                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654         }
2655         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2656 }
2657
2658 /**
2659  *  ixgbe_set_uta - Set unicast filter table address
2660  *  @adapter: board private structure
2661  *
2662  *  The unicast table address is a register array of 32-bit registers.
2663  *  The table is meant to be used in a way similar to how the MTA is used
2664  *  however due to certain limitations in the hardware it is necessary to
2665  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2666  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2667  **/
2668 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2669 {
2670         struct ixgbe_hw *hw = &adapter->hw;
2671         int i;
2672
2673         /* The UTA table only exists on 82599 hardware and newer */
2674         if (hw->mac.type < ixgbe_mac_82599EB)
2675                 return;
2676
2677         /* we only need to do this if VMDq is enabled */
2678         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2679                 return;
2680
2681         for (i = 0; i < 128; i++)
2682                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2683 }
2684
2685 #define IXGBE_MAX_RX_DESC_POLL 10
2686 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2687                                        struct ixgbe_ring *ring)
2688 {
2689         struct ixgbe_hw *hw = &adapter->hw;
2690         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2691         u32 rxdctl;
2692         u8 reg_idx = ring->reg_idx;
2693
2694         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2695         if (hw->mac.type == ixgbe_mac_82598EB &&
2696             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2697                 return;
2698
2699         do {
2700                 usleep_range(1000, 2000);
2701                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2702         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2703
2704         if (!wait_loop) {
2705                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2706                       "the polling period\n", reg_idx);
2707         }
2708 }
2709
2710 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2711                             struct ixgbe_ring *ring)
2712 {
2713         struct ixgbe_hw *hw = &adapter->hw;
2714         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2715         u32 rxdctl;
2716         u8 reg_idx = ring->reg_idx;
2717
2718         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2719         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2720
2721         /* write value back with RXDCTL.ENABLE bit cleared */
2722         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2723
2724         if (hw->mac.type == ixgbe_mac_82598EB &&
2725             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2726                 return;
2727
2728         /* the hardware may take up to 100us to really disable the rx queue */
2729         do {
2730                 udelay(10);
2731                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2732         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2733
2734         if (!wait_loop) {
2735                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2736                       "the polling period\n", reg_idx);
2737         }
2738 }
2739
2740 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2741                              struct ixgbe_ring *ring)
2742 {
2743         struct ixgbe_hw *hw = &adapter->hw;
2744         u64 rdba = ring->dma;
2745         u32 rxdctl;
2746         u8 reg_idx = ring->reg_idx;
2747
2748         /* disable queue to avoid issues while updating state */
2749         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2750         ixgbe_disable_rx_queue(adapter, ring);
2751
2752         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2753         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2754         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2755                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2756         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2757         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2758         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2759
2760         ixgbe_configure_srrctl(adapter, ring);
2761         ixgbe_configure_rscctl(adapter, ring);
2762
2763         /* If operating in IOV mode set RLPML for X540 */
2764         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2765             hw->mac.type == ixgbe_mac_X540) {
2766                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2767                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2768                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2769         }
2770
2771         if (hw->mac.type == ixgbe_mac_82598EB) {
2772                 /*
2773                  * enable cache line friendly hardware writes:
2774                  * PTHRESH=32 descriptors (half the internal cache),
2775                  * this also removes ugly rx_no_buffer_count increment
2776                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2777                  * WTHRESH=8 burst writeback up to two cache lines
2778                  */
2779                 rxdctl &= ~0x3FFFFF;
2780                 rxdctl |=  0x080420;
2781         }
2782
2783         /* enable receive descriptor ring */
2784         rxdctl |= IXGBE_RXDCTL_ENABLE;
2785         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2786
2787         ixgbe_rx_desc_queue_enable(adapter, ring);
2788         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2789 }
2790
2791 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2792 {
2793         struct ixgbe_hw *hw = &adapter->hw;
2794         int p;
2795
2796         /* PSRTYPE must be initialized in non 82598 adapters */
2797         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2798                       IXGBE_PSRTYPE_UDPHDR |
2799                       IXGBE_PSRTYPE_IPV4HDR |
2800                       IXGBE_PSRTYPE_L2HDR |
2801                       IXGBE_PSRTYPE_IPV6HDR;
2802
2803         if (hw->mac.type == ixgbe_mac_82598EB)
2804                 return;
2805
2806         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2807                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2808
2809         for (p = 0; p < adapter->num_rx_pools; p++)
2810                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2811                                 psrtype);
2812 }
2813
2814 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2815 {
2816         struct ixgbe_hw *hw = &adapter->hw;
2817         u32 gcr_ext;
2818         u32 vt_reg_bits;
2819         u32 reg_offset, vf_shift;
2820         u32 vmdctl;
2821         int i;
2822
2823         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2824                 return;
2825
2826         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2827         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2828         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2829         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2830
2831         vf_shift = adapter->num_vfs % 32;
2832         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2833
2834         /* Enable only the PF's pool for Tx/Rx */
2835         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2836         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2837         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2838         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2839         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2840
2841         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2842         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2843
2844         /*
2845          * Set up VF register offsets for selected VT Mode,
2846          * i.e. 32 or 64 VFs for SR-IOV
2847          */
2848         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2849         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2850         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2851         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2852
2853         /* enable Tx loopback for VF/PF communication */
2854         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2855         /* Enable MAC Anti-Spoofing */
2856         hw->mac.ops.set_mac_anti_spoofing(hw,
2857                                            (adapter->num_vfs != 0),
2858                                           adapter->num_vfs);
2859         /* For VFs that have spoof checking turned off */
2860         for (i = 0; i < adapter->num_vfs; i++) {
2861                 if (!adapter->vfinfo[i].spoofchk_enabled)
2862                         ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2863         }
2864 }
2865
2866 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2867 {
2868         struct ixgbe_hw *hw = &adapter->hw;
2869         struct net_device *netdev = adapter->netdev;
2870         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2871         int rx_buf_len;
2872         struct ixgbe_ring *rx_ring;
2873         int i;
2874         u32 mhadd, hlreg0;
2875
2876         /* Decide whether to use packet split mode or not */
2877         /* On by default */
2878         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2879
2880         /* Do not use packet split if we're in SR-IOV Mode */
2881         if (adapter->num_vfs)
2882                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2883
2884         /* Disable packet split due to 82599 erratum #45 */
2885         if (hw->mac.type == ixgbe_mac_82599EB)
2886                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2887
2888 #ifdef IXGBE_FCOE
2889         /* adjust max frame to be able to do baby jumbo for FCoE */
2890         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2891             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2892                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2893
2894 #endif /* IXGBE_FCOE */
2895         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2896         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2897                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2898                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2899
2900                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2901         }
2902
2903         /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2904         max_frame += VLAN_HLEN;
2905
2906         /* Set the RX buffer length according to the mode */
2907         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2908                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2909         } else {
2910                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2911                     (netdev->mtu <= ETH_DATA_LEN))
2912                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2913                 /*
2914                  * Make best use of allocation by using all but 1K of a
2915                  * power of 2 allocation that will be used for skb->head.
2916                  */
2917                 else if (max_frame <= IXGBE_RXBUFFER_3K)
2918                         rx_buf_len = IXGBE_RXBUFFER_3K;
2919                 else if (max_frame <= IXGBE_RXBUFFER_7K)
2920                         rx_buf_len = IXGBE_RXBUFFER_7K;
2921                 else if (max_frame <= IXGBE_RXBUFFER_15K)
2922                         rx_buf_len = IXGBE_RXBUFFER_15K;
2923                 else
2924                         rx_buf_len = IXGBE_MAX_RXBUFFER;
2925         }
2926
2927         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2928         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2929         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2930         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2931
2932         /*
2933          * Setup the HW Rx Head and Tail Descriptor Pointers and
2934          * the Base and Length of the Rx Descriptor Ring
2935          */
2936         for (i = 0; i < adapter->num_rx_queues; i++) {
2937                 rx_ring = adapter->rx_ring[i];
2938                 rx_ring->rx_buf_len = rx_buf_len;
2939
2940                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2941                         set_ring_ps_enabled(rx_ring);
2942                 else
2943                         clear_ring_ps_enabled(rx_ring);
2944
2945                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2946                         set_ring_rsc_enabled(rx_ring);
2947                 else
2948                         clear_ring_rsc_enabled(rx_ring);
2949
2950 #ifdef IXGBE_FCOE
2951                 if (netdev->features & NETIF_F_FCOE_MTU) {
2952                         struct ixgbe_ring_feature *f;
2953                         f = &adapter->ring_feature[RING_F_FCOE];
2954                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2955                                 clear_ring_ps_enabled(rx_ring);
2956                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2957                                         rx_ring->rx_buf_len =
2958                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2959                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2960                                    !ring_is_ps_enabled(rx_ring)) {
2961                                 rx_ring->rx_buf_len =
2962                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2963                         }
2964                 }
2965 #endif /* IXGBE_FCOE */
2966         }
2967 }
2968
2969 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2970 {
2971         struct ixgbe_hw *hw = &adapter->hw;
2972         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2973
2974         switch (hw->mac.type) {
2975         case ixgbe_mac_82598EB:
2976                 /*
2977                  * For VMDq support of different descriptor types or
2978                  * buffer sizes through the use of multiple SRRCTL
2979                  * registers, RDRXCTL.MVMEN must be set to 1
2980                  *
2981                  * also, the manual doesn't mention it clearly but DCA hints
2982                  * will only use queue 0's tags unless this bit is set.  Side
2983                  * effects of setting this bit are only that SRRCTL must be
2984                  * fully programmed [0..15]
2985                  */
2986                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2987                 break;
2988         case ixgbe_mac_82599EB:
2989         case ixgbe_mac_X540:
2990                 /* Disable RSC for ACK packets */
2991                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2992                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2993                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2994                 /* hardware requires some bits to be set by default */
2995                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2996                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2997                 break;
2998         default:
2999                 /* We should do nothing since we don't know this hardware */
3000                 return;
3001         }
3002
3003         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3004 }
3005
3006 /**
3007  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3008  * @adapter: board private structure
3009  *
3010  * Configure the Rx unit of the MAC after a reset.
3011  **/
3012 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3013 {
3014         struct ixgbe_hw *hw = &adapter->hw;
3015         int i;
3016         u32 rxctrl;
3017
3018         /* disable receives while setting up the descriptors */
3019         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3020         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3021
3022         ixgbe_setup_psrtype(adapter);
3023         ixgbe_setup_rdrxctl(adapter);
3024
3025         /* Program registers for the distribution of queues */
3026         ixgbe_setup_mrqc(adapter);
3027
3028         ixgbe_set_uta(adapter);
3029
3030         /* set_rx_buffer_len must be called before ring initialization */
3031         ixgbe_set_rx_buffer_len(adapter);
3032
3033         /*
3034          * Setup the HW Rx Head and Tail Descriptor Pointers and
3035          * the Base and Length of the Rx Descriptor Ring
3036          */
3037         for (i = 0; i < adapter->num_rx_queues; i++)
3038                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3039
3040         /* disable drop enable for 82598 parts */
3041         if (hw->mac.type == ixgbe_mac_82598EB)
3042                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3043
3044         /* enable all receives */
3045         rxctrl |= IXGBE_RXCTRL_RXEN;
3046         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3047 }
3048
3049 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3050 {
3051         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3052         struct ixgbe_hw *hw = &adapter->hw;
3053         int pool_ndx = adapter->num_vfs;
3054
3055         /* add VID to filter table */
3056         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3057         set_bit(vid, adapter->active_vlans);
3058 }
3059
3060 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3061 {
3062         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3063         struct ixgbe_hw *hw = &adapter->hw;
3064         int pool_ndx = adapter->num_vfs;
3065
3066         /* remove VID from filter table */
3067         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3068         clear_bit(vid, adapter->active_vlans);
3069 }
3070
3071 /**
3072  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3073  * @adapter: driver data
3074  */
3075 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3076 {
3077         struct ixgbe_hw *hw = &adapter->hw;
3078         u32 vlnctrl;
3079
3080         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3081         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3082         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3083 }
3084
3085 /**
3086  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3087  * @adapter: driver data
3088  */
3089 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3090 {
3091         struct ixgbe_hw *hw = &adapter->hw;
3092         u32 vlnctrl;
3093
3094         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3095         vlnctrl |= IXGBE_VLNCTRL_VFE;
3096         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3097         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3098 }
3099
3100 /**
3101  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3102  * @adapter: driver data
3103  */
3104 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3105 {
3106         struct ixgbe_hw *hw = &adapter->hw;
3107         u32 vlnctrl;
3108         int i, j;
3109
3110         switch (hw->mac.type) {
3111         case ixgbe_mac_82598EB:
3112                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3113                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3114                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3115                 break;
3116         case ixgbe_mac_82599EB:
3117         case ixgbe_mac_X540:
3118                 for (i = 0; i < adapter->num_rx_queues; i++) {
3119                         j = adapter->rx_ring[i]->reg_idx;
3120                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3121                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3122                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3123                 }
3124                 break;
3125         default:
3126                 break;
3127         }
3128 }
3129
3130 /**
3131  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3132  * @adapter: driver data
3133  */
3134 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3135 {
3136         struct ixgbe_hw *hw = &adapter->hw;
3137         u32 vlnctrl;
3138         int i, j;
3139
3140         switch (hw->mac.type) {
3141         case ixgbe_mac_82598EB:
3142                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3143                 vlnctrl |= IXGBE_VLNCTRL_VME;
3144                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3145                 break;
3146         case ixgbe_mac_82599EB:
3147         case ixgbe_mac_X540:
3148                 for (i = 0; i < adapter->num_rx_queues; i++) {
3149                         j = adapter->rx_ring[i]->reg_idx;
3150                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3151                         vlnctrl |= IXGBE_RXDCTL_VME;
3152                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3153                 }
3154                 break;
3155         default:
3156                 break;
3157         }
3158 }
3159
3160 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3161 {
3162         u16 vid;
3163
3164         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3165
3166         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3167                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3168 }
3169
3170 /**
3171  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3172  * @netdev: network interface device structure
3173  *
3174  * Writes unicast address list to the RAR table.
3175  * Returns: -ENOMEM on failure/insufficient address space
3176  *                0 on no addresses written
3177  *                X on writing X addresses to the RAR table
3178  **/
3179 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3180 {
3181         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3182         struct ixgbe_hw *hw = &adapter->hw;
3183         unsigned int vfn = adapter->num_vfs;
3184         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3185         int count = 0;
3186
3187         /* return ENOMEM indicating insufficient memory for addresses */
3188         if (netdev_uc_count(netdev) > rar_entries)
3189                 return -ENOMEM;
3190
3191         if (!netdev_uc_empty(netdev) && rar_entries) {
3192                 struct netdev_hw_addr *ha;
3193                 /* return error if we do not support writing to RAR table */
3194                 if (!hw->mac.ops.set_rar)
3195                         return -ENOMEM;
3196
3197                 netdev_for_each_uc_addr(ha, netdev) {
3198                         if (!rar_entries)
3199                                 break;
3200                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3201                                             vfn, IXGBE_RAH_AV);
3202                         count++;
3203                 }
3204         }
3205         /* write the addresses in reverse order to avoid write combining */
3206         for (; rar_entries > 0 ; rar_entries--)
3207                 hw->mac.ops.clear_rar(hw, rar_entries);
3208
3209         return count;
3210 }
3211
3212 /**
3213  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3214  * @netdev: network interface device structure
3215  *
3216  * The set_rx_method entry point is called whenever the unicast/multicast
3217  * address list or the network interface flags are updated.  This routine is
3218  * responsible for configuring the hardware for proper unicast, multicast and
3219  * promiscuous mode.
3220  **/
3221 void ixgbe_set_rx_mode(struct net_device *netdev)
3222 {
3223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3224         struct ixgbe_hw *hw = &adapter->hw;
3225         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3226         int count;
3227
3228         /* Check for Promiscuous and All Multicast modes */
3229
3230         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3231
3232         /* set all bits that we expect to always be set */
3233         fctrl |= IXGBE_FCTRL_BAM;
3234         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3235         fctrl |= IXGBE_FCTRL_PMCF;
3236
3237         /* clear the bits we are changing the status of */
3238         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3239
3240         if (netdev->flags & IFF_PROMISC) {
3241                 hw->addr_ctrl.user_set_promisc = true;
3242                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3243                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3244                 /* don't hardware filter vlans in promisc mode */
3245                 ixgbe_vlan_filter_disable(adapter);
3246         } else {
3247                 if (netdev->flags & IFF_ALLMULTI) {
3248                         fctrl |= IXGBE_FCTRL_MPE;
3249                         vmolr |= IXGBE_VMOLR_MPE;
3250                 } else {
3251                         /*
3252                          * Write addresses to the MTA, if the attempt fails
3253                          * then we should just turn on promiscuous mode so
3254                          * that we can at least receive multicast traffic
3255                          */
3256                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3257                         vmolr |= IXGBE_VMOLR_ROMPE;
3258                 }
3259                 ixgbe_vlan_filter_enable(adapter);
3260                 hw->addr_ctrl.user_set_promisc = false;
3261                 /*
3262                  * Write addresses to available RAR registers, if there is not
3263                  * sufficient space to store all the addresses then enable
3264                  * unicast promiscuous mode
3265                  */
3266                 count = ixgbe_write_uc_addr_list(netdev);
3267                 if (count < 0) {
3268                         fctrl |= IXGBE_FCTRL_UPE;
3269                         vmolr |= IXGBE_VMOLR_ROPE;
3270                 }
3271         }
3272
3273         if (adapter->num_vfs) {
3274                 ixgbe_restore_vf_multicasts(adapter);
3275                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3276                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3277                            IXGBE_VMOLR_ROPE);
3278                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3279         }
3280
3281         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3282
3283         if (netdev->features & NETIF_F_HW_VLAN_RX)
3284                 ixgbe_vlan_strip_enable(adapter);
3285         else
3286                 ixgbe_vlan_strip_disable(adapter);
3287 }
3288
3289 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3290 {
3291         int q_idx;
3292         struct ixgbe_q_vector *q_vector;
3293         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3294
3295         /* legacy and MSI only use one vector */
3296         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3297                 q_vectors = 1;
3298
3299         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3300                 q_vector = adapter->q_vector[q_idx];
3301                 napi_enable(&q_vector->napi);
3302         }
3303 }
3304
3305 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3306 {
3307         int q_idx;
3308         struct ixgbe_q_vector *q_vector;
3309         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3310
3311         /* legacy and MSI only use one vector */
3312         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3313                 q_vectors = 1;
3314
3315         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3316                 q_vector = adapter->q_vector[q_idx];
3317                 napi_disable(&q_vector->napi);
3318         }
3319 }
3320
3321 #ifdef CONFIG_IXGBE_DCB
3322 /*
3323  * ixgbe_configure_dcb - Configure DCB hardware
3324  * @adapter: ixgbe adapter struct
3325  *
3326  * This is called by the driver on open to configure the DCB hardware.
3327  * This is also called by the gennetlink interface when reconfiguring
3328  * the DCB state.
3329  */
3330 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3331 {
3332         struct ixgbe_hw *hw = &adapter->hw;
3333         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3334
3335         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3336                 if (hw->mac.type == ixgbe_mac_82598EB)
3337                         netif_set_gso_max_size(adapter->netdev, 65536);
3338                 return;
3339         }
3340
3341         if (hw->mac.type == ixgbe_mac_82598EB)
3342                 netif_set_gso_max_size(adapter->netdev, 32768);
3343
3344
3345         /* Enable VLAN tag insert/strip */
3346         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3347
3348         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3349
3350 #ifdef IXGBE_FCOE
3351         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3352                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3353 #endif
3354
3355         /* reconfigure the hardware */
3356         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3357                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3358                                                 DCB_TX_CONFIG);
3359                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3360                                                 DCB_RX_CONFIG);
3361                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3362         } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3363                 ixgbe_dcb_hw_ets(&adapter->hw,
3364                                  adapter->ixgbe_ieee_ets,
3365                                  max_frame);
3366                 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3367                                         adapter->ixgbe_ieee_pfc->pfc_en,
3368                                         adapter->ixgbe_ieee_ets->prio_tc);
3369         }
3370
3371         /* Enable RSS Hash per TC */
3372         if (hw->mac.type != ixgbe_mac_82598EB) {
3373                 int i;
3374                 u32 reg = 0;
3375
3376                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3377                         u8 msb = 0;
3378                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3379
3380                         while (cnt >>= 1)
3381                                 msb++;
3382
3383                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3384                 }
3385                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3386         }
3387 }
3388 #endif
3389
3390 /* Additional bittime to account for IXGBE framing */
3391 #define IXGBE_ETH_FRAMING 20
3392
3393 /*
3394  * ixgbe_hpbthresh - calculate high water mark for flow control
3395  *
3396  * @adapter: board private structure to calculate for
3397  * @pb - packet buffer to calculate
3398  */
3399 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3400 {
3401         struct ixgbe_hw *hw = &adapter->hw;
3402         struct net_device *dev = adapter->netdev;
3403         int link, tc, kb, marker;
3404         u32 dv_id, rx_pba;
3405
3406         /* Calculate max LAN frame size */
3407         tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3408
3409 #ifdef IXGBE_FCOE
3410         /* FCoE traffic class uses FCOE jumbo frames */
3411         if (dev->features & NETIF_F_FCOE_MTU) {
3412                 int fcoe_pb = 0;
3413
3414 #ifdef CONFIG_IXGBE_DCB
3415                 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3416
3417 #endif
3418                 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3419                         tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3420         }
3421 #endif
3422
3423         /* Calculate delay value for device */
3424         switch (hw->mac.type) {
3425         case ixgbe_mac_X540:
3426                 dv_id = IXGBE_DV_X540(link, tc);
3427                 break;
3428         default:
3429                 dv_id = IXGBE_DV(link, tc);
3430                 break;
3431         }
3432
3433         /* Loopback switch introduces additional latency */
3434         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3435                 dv_id += IXGBE_B2BT(tc);
3436
3437         /* Delay value is calculated in bit times convert to KB */
3438         kb = IXGBE_BT2KB(dv_id);
3439         rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3440
3441         marker = rx_pba - kb;
3442
3443         /* It is possible that the packet buffer is not large enough
3444          * to provide required headroom. In this case throw an error
3445          * to user and a do the best we can.
3446          */
3447         if (marker < 0) {
3448                 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3449                             "headroom to support flow control."
3450                             "Decrease MTU or number of traffic classes\n", pb);
3451                 marker = tc + 1;
3452         }
3453
3454         return marker;
3455 }
3456
3457 /*
3458  * ixgbe_lpbthresh - calculate low water mark for for flow control
3459  *
3460  * @adapter: board private structure to calculate for
3461  * @pb - packet buffer to calculate
3462  */
3463 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3464 {
3465         struct ixgbe_hw *hw = &adapter->hw;
3466         struct net_device *dev = adapter->netdev;
3467         int tc;
3468         u32 dv_id;
3469
3470         /* Calculate max LAN frame size */
3471         tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3472
3473         /* Calculate delay value for device */
3474         switch (hw->mac.type) {
3475         case ixgbe_mac_X540:
3476                 dv_id = IXGBE_LOW_DV_X540(tc);
3477                 break;
3478         default:
3479                 dv_id = IXGBE_LOW_DV(tc);
3480                 break;
3481         }
3482
3483         /* Delay value is calculated in bit times convert to KB */
3484         return IXGBE_BT2KB(dv_id);
3485 }
3486
3487 /*
3488  * ixgbe_pbthresh_setup - calculate and setup high low water marks
3489  */
3490 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3491 {
3492         struct ixgbe_hw *hw = &adapter->hw;
3493         int num_tc = netdev_get_num_tc(adapter->netdev);
3494         int i;
3495
3496         if (!num_tc)
3497                 num_tc = 1;
3498
3499         hw->fc.low_water = ixgbe_lpbthresh(adapter);
3500
3501         for (i = 0; i < num_tc; i++) {
3502                 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3503
3504                 /* Low water marks must not be larger than high water marks */
3505                 if (hw->fc.low_water > hw->fc.high_water[i])
3506                         hw->fc.low_water = 0;
3507         }
3508 }
3509
3510 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3511 {
3512         struct ixgbe_hw *hw = &adapter->hw;
3513         int hdrm;
3514         u8 tc = netdev_get_num_tc(adapter->netdev);
3515
3516         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3517             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3518                 hdrm = 32 << adapter->fdir_pballoc;
3519         else
3520                 hdrm = 0;
3521
3522         hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3523         ixgbe_pbthresh_setup(adapter);
3524 }
3525
3526 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3527 {
3528         struct ixgbe_hw *hw = &adapter->hw;
3529         struct hlist_node *node, *node2;
3530         struct ixgbe_fdir_filter *filter;
3531
3532         spin_lock(&adapter->fdir_perfect_lock);
3533
3534         if (!hlist_empty(&adapter->fdir_filter_list))
3535                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3536
3537         hlist_for_each_entry_safe(filter, node, node2,
3538                                   &adapter->fdir_filter_list, fdir_node) {
3539                 ixgbe_fdir_write_perfect_filter_82599(hw,
3540                                 &filter->filter,
3541                                 filter->sw_idx,
3542                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3543                                 IXGBE_FDIR_DROP_QUEUE :
3544                                 adapter->rx_ring[filter->action]->reg_idx);
3545         }
3546
3547         spin_unlock(&adapter->fdir_perfect_lock);
3548 }
3549
3550 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3551 {
3552         ixgbe_configure_pb(adapter);
3553 #ifdef CONFIG_IXGBE_DCB
3554         ixgbe_configure_dcb(adapter);
3555 #endif
3556
3557         ixgbe_set_rx_mode(adapter->netdev);
3558         ixgbe_restore_vlan(adapter);
3559
3560 #ifdef IXGBE_FCOE
3561         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3562                 ixgbe_configure_fcoe(adapter);
3563
3564 #endif /* IXGBE_FCOE */
3565         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3566                 ixgbe_init_fdir_signature_82599(&adapter->hw,
3567                                                 adapter->fdir_pballoc);
3568         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3569                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3570                                               adapter->fdir_pballoc);
3571                 ixgbe_fdir_filter_restore(adapter);
3572         }
3573
3574         ixgbe_configure_virtualization(adapter);
3575
3576         ixgbe_configure_tx(adapter);
3577         ixgbe_configure_rx(adapter);
3578 }
3579
3580 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3581 {
3582         switch (hw->phy.type) {
3583         case ixgbe_phy_sfp_avago:
3584         case ixgbe_phy_sfp_ftl:
3585         case ixgbe_phy_sfp_intel:
3586         case ixgbe_phy_sfp_unknown:
3587         case ixgbe_phy_sfp_passive_tyco:
3588         case ixgbe_phy_sfp_passive_unknown:
3589         case ixgbe_phy_sfp_active_unknown:
3590         case ixgbe_phy_sfp_ftl_active:
3591                 return true;
3592         case ixgbe_phy_nl:
3593                 if (hw->mac.type == ixgbe_mac_82598EB)
3594                         return true;
3595         default:
3596                 return false;
3597         }
3598 }
3599
3600 /**
3601  * ixgbe_sfp_link_config - set up SFP+ link
3602  * @adapter: pointer to private adapter struct
3603  **/
3604 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3605 {
3606         /*
3607          * We are assuming the worst case scenerio here, and that
3608          * is that an SFP was inserted/removed after the reset
3609          * but before SFP detection was enabled.  As such the best
3610          * solution is to just start searching as soon as we start
3611          */
3612         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3613                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3614
3615         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3616 }
3617
3618 /**
3619  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3620  * @hw: pointer to private hardware struct
3621  *
3622  * Returns 0 on success, negative on failure
3623  **/
3624 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3625 {
3626         u32 autoneg;
3627         bool negotiation, link_up = false;
3628         u32 ret = IXGBE_ERR_LINK_SETUP;
3629
3630         if (hw->mac.ops.check_link)
3631                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3632
3633         if (ret)
3634                 goto link_cfg_out;
3635
3636         autoneg = hw->phy.autoneg_advertised;
3637         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3638                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3639                                                         &negotiation);
3640         if (ret)
3641                 goto link_cfg_out;
3642
3643         if (hw->mac.ops.setup_link)
3644                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3645 link_cfg_out:
3646         return ret;
3647 }
3648
3649 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3650 {
3651         struct ixgbe_hw *hw = &adapter->hw;
3652         u32 gpie = 0;
3653
3654         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3655                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3656                        IXGBE_GPIE_OCD;
3657                 gpie |= IXGBE_GPIE_EIAME;
3658                 /*
3659                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3660                  * this saves a register write for every interrupt
3661                  */
3662                 switch (hw->mac.type) {
3663                 case ixgbe_mac_82598EB:
3664                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3665                         break;
3666                 case ixgbe_mac_82599EB:
3667                 case ixgbe_mac_X540:
3668                 default:
3669                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3670                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3671                         break;
3672                 }
3673         } else {
3674                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3675                  * specifically only auto mask tx and rx interrupts */
3676                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3677         }
3678
3679         /* XXX: to interrupt immediately for EICS writes, enable this */
3680         /* gpie |= IXGBE_GPIE_EIMEN; */
3681
3682         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3683                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3684                 gpie |= IXGBE_GPIE_VTMODE_64;
3685         }
3686
3687         /* Enable Thermal over heat sensor interrupt */
3688         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3689                 switch (adapter->hw.mac.type) {
3690                 case ixgbe_mac_82599EB:
3691                         gpie |= IXGBE_SDP0_GPIEN;
3692                         break;
3693                 case ixgbe_mac_X540:
3694                         gpie |= IXGBE_EIMS_TS;
3695                         break;
3696                 default:
3697                         break;
3698                 }
3699         }
3700
3701         /* Enable fan failure interrupt */
3702         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3703                 gpie |= IXGBE_SDP1_GPIEN;
3704
3705         if (hw->mac.type == ixgbe_mac_82599EB) {
3706                 gpie |= IXGBE_SDP1_GPIEN;
3707                 gpie |= IXGBE_SDP2_GPIEN;
3708         }
3709
3710         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3711 }
3712
3713 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3714 {
3715         struct ixgbe_hw *hw = &adapter->hw;
3716         int err;
3717         u32 ctrl_ext;
3718
3719         ixgbe_get_hw_control(adapter);
3720         ixgbe_setup_gpie(adapter);
3721
3722         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3723                 ixgbe_configure_msix(adapter);
3724         else
3725                 ixgbe_configure_msi_and_legacy(adapter);
3726
3727         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3728         if (hw->mac.ops.enable_tx_laser &&
3729             ((hw->phy.multispeed_fiber) ||
3730              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3731               (hw->mac.type == ixgbe_mac_82599EB))))
3732                 hw->mac.ops.enable_tx_laser(hw);
3733
3734         clear_bit(__IXGBE_DOWN, &adapter->state);
3735         ixgbe_napi_enable_all(adapter);
3736
3737         if (ixgbe_is_sfp(hw)) {
3738                 ixgbe_sfp_link_config(adapter);
3739         } else {
3740                 err = ixgbe_non_sfp_link_config(hw);
3741                 if (err)
3742                         e_err(probe, "link_config FAILED %d\n", err);
3743         }
3744
3745         /* clear any pending interrupts, may auto mask */
3746         IXGBE_READ_REG(hw, IXGBE_EICR);
3747         ixgbe_irq_enable(adapter, true, true);
3748
3749         /*
3750          * If this adapter has a fan, check to see if we had a failure
3751          * before we enabled the interrupt.
3752          */
3753         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3754                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3755                 if (esdp & IXGBE_ESDP_SDP1)
3756                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3757         }
3758
3759         /* enable transmits */
3760         netif_tx_start_all_queues(adapter->netdev);
3761
3762         /* bring the link up in the watchdog, this could race with our first
3763          * link up interrupt but shouldn't be a problem */
3764         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3765         adapter->link_check_timeout = jiffies;
3766         mod_timer(&adapter->service_timer, jiffies);
3767
3768         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3769         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3770         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3771         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3772 }
3773
3774 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3775 {
3776         WARN_ON(in_interrupt());
3777         /* put off any impending NetWatchDogTimeout */
3778         adapter->netdev->trans_start = jiffies;
3779
3780         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3781                 usleep_range(1000, 2000);
3782         ixgbe_down(adapter);
3783         /*
3784          * If SR-IOV enabled then wait a bit before bringing the adapter
3785          * back up to give the VFs time to respond to the reset.  The
3786          * two second wait is based upon the watchdog timer cycle in
3787          * the VF driver.
3788          */
3789         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3790                 msleep(2000);
3791         ixgbe_up(adapter);
3792         clear_bit(__IXGBE_RESETTING, &adapter->state);
3793 }
3794
3795 void ixgbe_up(struct ixgbe_adapter *adapter)
3796 {
3797         /* hardware has been reset, we need to reload some things */
3798         ixgbe_configure(adapter);
3799
3800         ixgbe_up_complete(adapter);
3801 }
3802
3803 void ixgbe_reset(struct ixgbe_adapter *adapter)
3804 {
3805         struct ixgbe_hw *hw = &adapter->hw;
3806         int err;
3807
3808         /* lock SFP init bit to prevent race conditions with the watchdog */
3809         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3810                 usleep_range(1000, 2000);
3811
3812         /* clear all SFP and link config related flags while holding SFP_INIT */
3813         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3814                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3815         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3816
3817         err = hw->mac.ops.init_hw(hw);
3818         switch (err) {
3819         case 0:
3820         case IXGBE_ERR_SFP_NOT_PRESENT:
3821         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3822                 break;
3823         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3824                 e_dev_err("master disable timed out\n");
3825                 break;
3826         case IXGBE_ERR_EEPROM_VERSION:
3827                 /* We are running on a pre-production device, log a warning */
3828                 e_dev_warn("This device is a pre-production adapter/LOM. "
3829                            "Please be aware there may be issuesassociated with "
3830                            "your hardware.  If you are experiencing problems "
3831                            "please contact your Intel or hardware "
3832                            "representative who provided you with this "
3833                            "hardware.\n");
3834                 break;
3835         default:
3836                 e_dev_err("Hardware Error: %d\n", err);
3837         }
3838
3839         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3840
3841         /* reprogram the RAR[0] in case user changed it. */
3842         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3843                             IXGBE_RAH_AV);
3844 }
3845
3846 /**
3847  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3848  * @rx_ring: ring to free buffers from
3849  **/
3850 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3851 {
3852         struct device *dev = rx_ring->dev;
3853         unsigned long size;
3854         u16 i;
3855
3856         /* ring already cleared, nothing to do */
3857         if (!rx_ring->rx_buffer_info)
3858                 return;
3859
3860         /* Free all the Rx ring sk_buffs */
3861         for (i = 0; i < rx_ring->count; i++) {
3862                 struct ixgbe_rx_buffer *rx_buffer_info;
3863
3864                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3865                 if (rx_buffer_info->dma) {
3866                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3867                                          rx_ring->rx_buf_len,
3868                                          DMA_FROM_DEVICE);
3869                         rx_buffer_info->dma = 0;
3870                 }
3871                 if (rx_buffer_info->skb) {
3872                         struct sk_buff *skb = rx_buffer_info->skb;
3873                         rx_buffer_info->skb = NULL;
3874                         do {
3875                                 struct sk_buff *this = skb;
3876                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3877                                         dma_unmap_single(dev,
3878                                                          IXGBE_RSC_CB(this)->dma,
3879                                                          rx_ring->rx_buf_len,
3880                                                          DMA_FROM_DEVICE);
3881                                         IXGBE_RSC_CB(this)->dma = 0;
3882                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3883                                 }
3884                                 skb = skb->prev;
3885                                 dev_kfree_skb(this);
3886                         } while (skb);
3887                 }
3888                 if (!rx_buffer_info->page)
3889                         continue;
3890                 if (rx_buffer_info->page_dma) {
3891                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3892                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3893                         rx_buffer_info->page_dma = 0;
3894                 }
3895                 put_page(rx_buffer_info->page);
3896                 rx_buffer_info->page = NULL;
3897                 rx_buffer_info->page_offset = 0;
3898         }
3899
3900         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3901         memset(rx_ring->rx_buffer_info, 0, size);
3902
3903         /* Zero out the descriptor ring */
3904         memset(rx_ring->desc, 0, rx_ring->size);
3905
3906         rx_ring->next_to_clean = 0;
3907         rx_ring->next_to_use = 0;
3908 }
3909
3910 /**
3911  * ixgbe_clean_tx_ring - Free Tx Buffers
3912  * @tx_ring: ring to be cleaned
3913  **/
3914 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3915 {
3916         struct ixgbe_tx_buffer *tx_buffer_info;
3917         unsigned long size;
3918         u16 i;
3919
3920         /* ring already cleared, nothing to do */
3921         if (!tx_ring->tx_buffer_info)
3922                 return;
3923
3924         /* Free all the Tx ring sk_buffs */
3925         for (i = 0; i < tx_ring->count; i++) {
3926                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3927                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3928         }
3929
3930         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3931         memset(tx_ring->tx_buffer_info, 0, size);
3932
3933         /* Zero out the descriptor ring */
3934         memset(tx_ring->desc, 0, tx_ring->size);
3935
3936         tx_ring->next_to_use = 0;
3937         tx_ring->next_to_clean = 0;
3938 }
3939
3940 /**
3941  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3942  * @adapter: board private structure
3943  **/
3944 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3945 {
3946         int i;
3947
3948         for (i = 0; i < adapter->num_rx_queues; i++)
3949                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3950 }
3951
3952 /**
3953  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3954  * @adapter: board private structure
3955  **/
3956 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3957 {
3958         int i;
3959
3960         for (i = 0; i < adapter->num_tx_queues; i++)
3961                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3962 }
3963
3964 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3965 {
3966         struct hlist_node *node, *node2;
3967         struct ixgbe_fdir_filter *filter;
3968
3969         spin_lock(&adapter->fdir_perfect_lock);
3970
3971         hlist_for_each_entry_safe(filter, node, node2,
3972                                   &adapter->fdir_filter_list, fdir_node) {
3973                 hlist_del(&filter->fdir_node);
3974                 kfree(filter);
3975         }
3976         adapter->fdir_filter_count = 0;
3977
3978         spin_unlock(&adapter->fdir_perfect_lock);
3979 }
3980
3981 void ixgbe_down(struct ixgbe_adapter *adapter)
3982 {
3983         struct net_device *netdev = adapter->netdev;
3984         struct ixgbe_hw *hw = &adapter->hw;
3985         u32 rxctrl;
3986         int i;
3987
3988         /* signal that we are down to the interrupt handler */
3989         set_bit(__IXGBE_DOWN, &adapter->state);
3990
3991         /* disable receives */
3992         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3993         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3994
3995         /* disable all enabled rx queues */
3996         for (i = 0; i < adapter->num_rx_queues; i++)
3997                 /* this call also flushes the previous write */
3998                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3999
4000         usleep_range(10000, 20000);
4001
4002         netif_tx_stop_all_queues(netdev);
4003
4004         /* call carrier off first to avoid false dev_watchdog timeouts */
4005         netif_carrier_off(netdev);
4006         netif_tx_disable(netdev);
4007
4008         ixgbe_irq_disable(adapter);
4009
4010         ixgbe_napi_disable_all(adapter);
4011
4012         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4013                              IXGBE_FLAG2_RESET_REQUESTED);
4014         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4015
4016         del_timer_sync(&adapter->service_timer);
4017
4018         if (adapter->num_vfs) {
4019                 /* Clear EITR Select mapping */
4020                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4021
4022                 /* Mark all the VFs as inactive */
4023                 for (i = 0 ; i < adapter->num_vfs; i++)
4024                         adapter->vfinfo[i].clear_to_send = 0;
4025
4026                 /* ping all the active vfs to let them know we are going down */
4027                 ixgbe_ping_all_vfs(adapter);
4028
4029                 /* Disable all VFTE/VFRE TX/RX */
4030                 ixgbe_disable_tx_rx(adapter);
4031         }
4032
4033         /* disable transmits in the hardware now that interrupts are off */
4034         for (i = 0; i < adapter->num_tx_queues; i++) {
4035                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4036                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4037         }
4038
4039         /* Disable the Tx DMA engine on 82599 and X540 */
4040         switch (hw->mac.type) {
4041         case ixgbe_mac_82599EB:
4042         case ixgbe_mac_X540:
4043                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4044                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4045                                  ~IXGBE_DMATXCTL_TE));
4046                 break;
4047         default:
4048                 break;
4049         }
4050
4051         if (!pci_channel_offline(adapter->pdev))
4052                 ixgbe_reset(adapter);
4053
4054         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4055         if (hw->mac.ops.disable_tx_laser &&
4056             ((hw->phy.multispeed_fiber) ||
4057              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4058               (hw->mac.type == ixgbe_mac_82599EB))))
4059                 hw->mac.ops.disable_tx_laser(hw);
4060
4061         ixgbe_clean_all_tx_rings(adapter);
4062         ixgbe_clean_all_rx_rings(adapter);
4063
4064 #ifdef CONFIG_IXGBE_DCA
4065         /* since we reset the hardware DCA settings were cleared */
4066         ixgbe_setup_dca(adapter);
4067 #endif
4068 }
4069
4070 /**
4071  * ixgbe_poll - NAPI Rx polling callback
4072  * @napi: structure for representing this polling device
4073  * @budget: how many packets driver is allowed to clean
4074  *
4075  * This function is used for legacy and MSI, NAPI mode
4076  **/
4077 static int ixgbe_poll(struct napi_struct *napi, int budget)
4078 {
4079         struct ixgbe_q_vector *q_vector =
4080                                 container_of(napi, struct ixgbe_q_vector, napi);
4081         struct ixgbe_adapter *adapter = q_vector->adapter;
4082         struct ixgbe_ring *ring;
4083         int per_ring_budget;
4084         bool clean_complete = true;
4085
4086 #ifdef CONFIG_IXGBE_DCA
4087         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4088                 ixgbe_update_dca(q_vector);
4089 #endif
4090
4091         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4092                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4093
4094         /* attempt to distribute budget to each queue fairly, but don't allow
4095          * the budget to go below 1 because we'll exit polling */
4096         if (q_vector->rx.count > 1)
4097                 per_ring_budget = max(budget/q_vector->rx.count, 1);
4098         else
4099                 per_ring_budget = budget;
4100
4101         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4102                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4103                                                      per_ring_budget);
4104
4105         /* If all work not completed, return budget and keep polling */
4106         if (!clean_complete)
4107                 return budget;
4108
4109         /* all work done, exit the polling mode */
4110         napi_complete(napi);
4111         if (adapter->rx_itr_setting & 1)
4112                 ixgbe_set_itr(q_vector);
4113         if (!test_bit(__IXGBE_DOWN, &adapter->state))
4114                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4115
4116         return 0;
4117 }
4118
4119 /**
4120  * ixgbe_tx_timeout - Respond to a Tx Hang
4121  * @netdev: network interface device structure
4122  **/
4123 static void ixgbe_tx_timeout(struct net_device *netdev)
4124 {
4125         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4126
4127         /* Do the reset outside of interrupt context */
4128         ixgbe_tx_timeout_reset(adapter);
4129 }
4130
4131 /**
4132  * ixgbe_set_rss_queues: Allocate queues for RSS
4133  * @adapter: board private structure to initialize
4134  *
4135  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4136  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4137  *
4138  **/
4139 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4140 {
4141         bool ret = false;
4142         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4143
4144         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4145                 f->mask = 0xF;
4146                 adapter->num_rx_queues = f->indices;
4147                 adapter->num_tx_queues = f->indices;
4148                 ret = true;
4149         } else {
4150                 ret = false;
4151         }
4152
4153         return ret;
4154 }
4155
4156 /**
4157  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4158  * @adapter: board private structure to initialize
4159  *
4160  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4161  * to the original CPU that initiated the Tx session.  This runs in addition
4162  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4163  * Rx load across CPUs using RSS.
4164  *
4165  **/
4166 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4167 {
4168         bool ret = false;
4169         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4170
4171         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4172         f_fdir->mask = 0;
4173
4174         /* Flow Director must have RSS enabled */
4175         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4176             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4177                 adapter->num_tx_queues = f_fdir->indices;
4178                 adapter->num_rx_queues = f_fdir->indices;
4179                 ret = true;
4180         } else {
4181                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4182         }
4183         return ret;
4184 }
4185
4186 #ifdef IXGBE_FCOE
4187 /**
4188  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4189  * @adapter: board private structure to initialize
4190  *
4191  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4192  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4193  * rx queues out of the max number of rx queues, instead, it is used as the
4194  * index of the first rx queue used by FCoE.
4195  *
4196  **/
4197 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4198 {
4199         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4200
4201         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4202                 return false;
4203
4204         f->indices = min((int)num_online_cpus(), f->indices);
4205
4206         adapter->num_rx_queues = 1;
4207         adapter->num_tx_queues = 1;
4208
4209         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4210                 e_info(probe, "FCoE enabled with RSS\n");
4211                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4212                         ixgbe_set_fdir_queues(adapter);
4213                 else
4214                         ixgbe_set_rss_queues(adapter);
4215         }
4216
4217         /* adding FCoE rx rings to the end */
4218         f->mask = adapter->num_rx_queues;
4219         adapter->num_rx_queues += f->indices;
4220         adapter->num_tx_queues += f->indices;
4221
4222         return true;
4223 }
4224 #endif /* IXGBE_FCOE */
4225
4226 /* Artificial max queue cap per traffic class in DCB mode */
4227 #define DCB_QUEUE_CAP 8
4228
4229 #ifdef CONFIG_IXGBE_DCB
4230 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4231 {
4232         int per_tc_q, q, i, offset = 0;
4233         struct net_device *dev = adapter->netdev;
4234         int tcs = netdev_get_num_tc(dev);
4235
4236         if (!tcs)
4237                 return false;
4238
4239         /* Map queue offset and counts onto allocated tx queues */
4240         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4241         q = min((int)num_online_cpus(), per_tc_q);
4242
4243         for (i = 0; i < tcs; i++) {
4244                 netdev_set_tc_queue(dev, i, q, offset);
4245                 offset += q;
4246         }
4247
4248         adapter->num_tx_queues = q * tcs;
4249         adapter->num_rx_queues = q * tcs;
4250
4251 #ifdef IXGBE_FCOE
4252         /* FCoE enabled queues require special configuration indexed
4253          * by feature specific indices and mask. Here we map FCoE
4254          * indices onto the DCB queue pairs allowing FCoE to own
4255          * configuration later.
4256          */
4257         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4258                 int tc;
4259                 struct ixgbe_ring_feature *f =
4260                                         &adapter->ring_feature[RING_F_FCOE];
4261
4262                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4263                 f->indices = dev->tc_to_txq[tc].count;
4264                 f->mask = dev->tc_to_txq[tc].offset;
4265         }
4266 #endif
4267
4268         return true;
4269 }
4270 #endif
4271
4272 /**
4273  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4274  * @adapter: board private structure to initialize
4275  *
4276  * IOV doesn't actually use anything, so just NAK the
4277  * request for now and let the other queue routines
4278  * figure out what to do.
4279  */
4280 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4281 {
4282         return false;
4283 }
4284
4285 /*
4286  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4287  * @adapter: board private structure to initialize
4288  *
4289  * This is the top level queue allocation routine.  The order here is very
4290  * important, starting with the "most" number of features turned on at once,
4291  * and ending with the smallest set of features.  This way large combinations
4292  * can be allocated if they're turned on, and smaller combinations are the
4293  * fallthrough conditions.
4294  *
4295  **/
4296 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4297 {
4298         /* Start with base case */
4299         adapter->num_rx_queues = 1;
4300         adapter->num_tx_queues = 1;
4301         adapter->num_rx_pools = adapter->num_rx_queues;
4302         adapter->num_rx_queues_per_pool = 1;
4303
4304         if (ixgbe_set_sriov_queues(adapter))
4305                 goto done;
4306
4307 #ifdef CONFIG_IXGBE_DCB
4308         if (ixgbe_set_dcb_queues(adapter))
4309                 goto done;
4310
4311 #endif
4312 #ifdef IXGBE_FCOE
4313         if (ixgbe_set_fcoe_queues(adapter))
4314                 goto done;
4315
4316 #endif /* IXGBE_FCOE */
4317         if (ixgbe_set_fdir_queues(adapter))
4318                 goto done;
4319
4320         if (ixgbe_set_rss_queues(adapter))
4321                 goto done;
4322
4323         /* fallback to base case */
4324         adapter->num_rx_queues = 1;
4325         adapter->num_tx_queues = 1;
4326
4327 done:
4328         /* Notify the stack of the (possibly) reduced queue counts. */
4329         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4330         return netif_set_real_num_rx_queues(adapter->netdev,
4331                                             adapter->num_rx_queues);
4332 }
4333
4334 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4335                                        int vectors)
4336 {
4337         int err, vector_threshold;
4338
4339         /* We'll want at least 3 (vector_threshold):
4340          * 1) TxQ[0] Cleanup
4341          * 2) RxQ[0] Cleanup
4342          * 3) Other (Link Status Change, etc.)
4343          * 4) TCP Timer (optional)
4344          */
4345         vector_threshold = MIN_MSIX_COUNT;
4346
4347         /* The more we get, the more we will assign to Tx/Rx Cleanup
4348          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4349          * Right now, we simply care about how many we'll get; we'll
4350          * set them up later while requesting irq's.
4351          */
4352         while (vectors >= vector_threshold) {
4353                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4354                                       vectors);
4355                 if (!err) /* Success in acquiring all requested vectors. */
4356                         break;
4357                 else if (err < 0)
4358                         vectors = 0; /* Nasty failure, quit now */
4359                 else /* err == number of vectors we should try again with */
4360                         vectors = err;
4361         }
4362
4363         if (vectors < vector_threshold) {
4364                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4365                  * This just means we'll go with either a single MSI
4366                  * vector or fall back to legacy interrupts.
4367                  */
4368                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4369                              "Unable to allocate MSI-X interrupts\n");
4370                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4371                 kfree(adapter->msix_entries);
4372                 adapter->msix_entries = NULL;
4373         } else {
4374                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4375                 /*
4376                  * Adjust for only the vectors we'll use, which is minimum
4377                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4378                  * vectors we were allocated.
4379                  */
4380                 adapter->num_msix_vectors = min(vectors,
4381                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4382         }
4383 }
4384
4385 /**
4386  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4387  * @adapter: board private structure to initialize
4388  *
4389  * Cache the descriptor ring offsets for RSS to the assigned rings.
4390  *
4391  **/
4392 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4393 {
4394         int i;
4395
4396         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4397                 return false;
4398
4399         for (i = 0; i < adapter->num_rx_queues; i++)
4400                 adapter->rx_ring[i]->reg_idx = i;
4401         for (i = 0; i < adapter->num_tx_queues; i++)
4402                 adapter->tx_ring[i]->reg_idx = i;
4403
4404         return true;
4405 }
4406
4407 #ifdef CONFIG_IXGBE_DCB
4408
4409 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4410 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4411                                     unsigned int *tx, unsigned int *rx)
4412 {
4413         struct net_device *dev = adapter->netdev;
4414         struct ixgbe_hw *hw = &adapter->hw;
4415         u8 num_tcs = netdev_get_num_tc(dev);
4416
4417         *tx = 0;
4418         *rx = 0;
4419
4420         switch (hw->mac.type) {
4421         case ixgbe_mac_82598EB:
4422                 *tx = tc << 2;
4423                 *rx = tc << 3;
4424                 break;
4425         case ixgbe_mac_82599EB:
4426         case ixgbe_mac_X540:
4427                 if (num_tcs > 4) {
4428                         if (tc < 3) {
4429                                 *tx = tc << 5;
4430                                 *rx = tc << 4;
4431                         } else if (tc <  5) {
4432                                 *tx = ((tc + 2) << 4);
4433                                 *rx = tc << 4;
4434                         } else if (tc < num_tcs) {
4435                                 *tx = ((tc + 8) << 3);
4436                                 *rx = tc << 4;
4437                         }
4438                 } else {
4439                         *rx =  tc << 5;
4440                         switch (tc) {
4441                         case 0:
4442                                 *tx =  0;
4443                                 break;
4444                         case 1:
4445                                 *tx = 64;
4446                                 break;
4447                         case 2:
4448                                 *tx = 96;
4449                                 break;
4450                         case 3:
4451                                 *tx = 112;
4452                                 break;
4453                         default:
4454                                 break;
4455                         }
4456                 }
4457                 break;
4458         default:
4459                 break;
4460         }
4461 }
4462
4463 /**
4464  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4465  * @adapter: board private structure to initialize
4466  *
4467  * Cache the descriptor ring offsets for DCB to the assigned rings.
4468  *
4469  **/
4470 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4471 {
4472         struct net_device *dev = adapter->netdev;
4473         int i, j, k;
4474         u8 num_tcs = netdev_get_num_tc(dev);
4475
4476         if (!num_tcs)
4477                 return false;
4478
4479         for (i = 0, k = 0; i < num_tcs; i++) {
4480                 unsigned int tx_s, rx_s;
4481                 u16 count = dev->tc_to_txq[i].count;
4482
4483                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4484                 for (j = 0; j < count; j++, k++) {
4485                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4486                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4487                         adapter->tx_ring[k]->dcb_tc = i;
4488                         adapter->rx_ring[k]->dcb_tc = i;
4489                 }
4490         }
4491
4492         return true;
4493 }
4494 #endif
4495
4496 /**
4497  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4498  * @adapter: board private structure to initialize
4499  *
4500  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4501  *
4502  **/
4503 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4504 {
4505         int i;
4506         bool ret = false;
4507
4508         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4509             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4510                 for (i = 0; i < adapter->num_rx_queues; i++)
4511                         adapter->rx_ring[i]->reg_idx = i;
4512                 for (i = 0; i < adapter->num_tx_queues; i++)
4513                         adapter->tx_ring[i]->reg_idx = i;
4514                 ret = true;
4515         }
4516
4517         return ret;
4518 }
4519
4520 #ifdef IXGBE_FCOE
4521 /**
4522  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4523  * @adapter: board private structure to initialize
4524  *
4525  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4526  *
4527  */
4528 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4529 {
4530         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4531         int i;
4532         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4533
4534         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4535                 return false;
4536
4537         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4538                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4539                         ixgbe_cache_ring_fdir(adapter);
4540                 else
4541                         ixgbe_cache_ring_rss(adapter);
4542
4543                 fcoe_rx_i = f->mask;
4544                 fcoe_tx_i = f->mask;
4545         }
4546         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4547                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4548                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4549         }
4550         return true;
4551 }
4552
4553 #endif /* IXGBE_FCOE */
4554 /**
4555  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4556  * @adapter: board private structure to initialize
4557  *
4558  * SR-IOV doesn't use any descriptor rings but changes the default if
4559  * no other mapping is used.
4560  *
4561  */
4562 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4563 {
4564         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4565         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4566         if (adapter->num_vfs)
4567                 return true;
4568         else
4569                 return false;
4570 }
4571
4572 /**
4573  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4574  * @adapter: board private structure to initialize
4575  *
4576  * Once we know the feature-set enabled for the device, we'll cache
4577  * the register offset the descriptor ring is assigned to.
4578  *
4579  * Note, the order the various feature calls is important.  It must start with
4580  * the "most" features enabled at the same time, then trickle down to the
4581  * least amount of features turned on at once.
4582  **/
4583 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4584 {
4585         /* start with default case */
4586         adapter->rx_ring[0]->reg_idx = 0;
4587         adapter->tx_ring[0]->reg_idx = 0;
4588
4589         if (ixgbe_cache_ring_sriov(adapter))
4590                 return;
4591
4592 #ifdef CONFIG_IXGBE_DCB
4593         if (ixgbe_cache_ring_dcb(adapter))
4594                 return;
4595 #endif
4596
4597 #ifdef IXGBE_FCOE
4598         if (ixgbe_cache_ring_fcoe(adapter))
4599                 return;
4600 #endif /* IXGBE_FCOE */
4601
4602         if (ixgbe_cache_ring_fdir(adapter))
4603                 return;
4604
4605         if (ixgbe_cache_ring_rss(adapter))
4606                 return;
4607 }
4608
4609 /**
4610  * ixgbe_alloc_queues - Allocate memory for all rings
4611  * @adapter: board private structure to initialize
4612  *
4613  * We allocate one ring per queue at run-time since we don't know the
4614  * number of queues at compile-time.  The polling_netdev array is
4615  * intended for Multiqueue, but should work fine with a single queue.
4616  **/
4617 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4618 {
4619         int rx = 0, tx = 0, nid = adapter->node;
4620
4621         if (nid < 0 || !node_online(nid))
4622                 nid = first_online_node;
4623
4624         for (; tx < adapter->num_tx_queues; tx++) {
4625                 struct ixgbe_ring *ring;
4626
4627                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4628                 if (!ring)
4629                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4630                 if (!ring)
4631                         goto err_allocation;
4632                 ring->count = adapter->tx_ring_count;
4633                 ring->queue_index = tx;
4634                 ring->numa_node = nid;
4635                 ring->dev = &adapter->pdev->dev;
4636                 ring->netdev = adapter->netdev;
4637
4638                 adapter->tx_ring[tx] = ring;
4639         }
4640
4641         for (; rx < adapter->num_rx_queues; rx++) {
4642                 struct ixgbe_ring *ring;
4643
4644                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4645                 if (!ring)
4646                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4647                 if (!ring)
4648                         goto err_allocation;
4649                 ring->count = adapter->rx_ring_count;
4650                 ring->queue_index = rx;
4651                 ring->numa_node = nid;
4652                 ring->dev = &adapter->pdev->dev;
4653                 ring->netdev = adapter->netdev;
4654
4655                 adapter->rx_ring[rx] = ring;
4656         }
4657
4658         ixgbe_cache_ring_register(adapter);
4659
4660         return 0;
4661
4662 err_allocation:
4663         while (tx)
4664                 kfree(adapter->tx_ring[--tx]);
4665
4666         while (rx)
4667                 kfree(adapter->rx_ring[--rx]);
4668         return -ENOMEM;
4669 }
4670
4671 /**
4672  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4673  * @adapter: board private structure to initialize
4674  *
4675  * Attempt to configure the interrupts using the best available
4676  * capabilities of the hardware and the kernel.
4677  **/
4678 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4679 {
4680         struct ixgbe_hw *hw = &adapter->hw;
4681         int err = 0;
4682         int vector, v_budget;
4683
4684         /*
4685          * It's easy to be greedy for MSI-X vectors, but it really
4686          * doesn't do us much good if we have a lot more vectors
4687          * than CPU's.  So let's be conservative and only ask for
4688          * (roughly) the same number of vectors as there are CPU's.
4689          */
4690         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4691                        (int)num_online_cpus()) + NON_Q_VECTORS;
4692
4693         /*
4694          * At the same time, hardware can only support a maximum of
4695          * hw.mac->max_msix_vectors vectors.  With features
4696          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4697          * descriptor queues supported by our device.  Thus, we cap it off in
4698          * those rare cases where the cpu count also exceeds our vector limit.
4699          */
4700         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4701
4702         /* A failure in MSI-X entry allocation isn't fatal, but it does
4703          * mean we disable MSI-X capabilities of the adapter. */
4704         adapter->msix_entries = kcalloc(v_budget,
4705                                         sizeof(struct msix_entry), GFP_KERNEL);
4706         if (adapter->msix_entries) {
4707                 for (vector = 0; vector < v_budget; vector++)
4708                         adapter->msix_entries[vector].entry = vector;
4709
4710                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4711
4712                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4713                         goto out;
4714         }
4715
4716         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4717         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4718         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4719                 e_err(probe,
4720                       "ATR is not supported while multiple "
4721                       "queues are disabled.  Disabling Flow Director\n");
4722         }
4723         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4724         adapter->atr_sample_rate = 0;
4725         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4726                 ixgbe_disable_sriov(adapter);
4727
4728         err = ixgbe_set_num_queues(adapter);
4729         if (err)
4730                 return err;
4731
4732         err = pci_enable_msi(adapter->pdev);
4733         if (!err) {
4734                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4735         } else {
4736                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4737                              "Unable to allocate MSI interrupt, "
4738                              "falling back to legacy.  Error: %d\n", err);
4739                 /* reset err */
4740                 err = 0;
4741         }
4742
4743 out:
4744         return err;
4745 }
4746
4747 /**
4748  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4749  * @adapter: board private structure to initialize
4750  *
4751  * We allocate one q_vector per queue interrupt.  If allocation fails we
4752  * return -ENOMEM.
4753  **/
4754 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4755 {
4756         int v_idx, num_q_vectors;
4757         struct ixgbe_q_vector *q_vector;
4758
4759         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4760                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4761         else
4762                 num_q_vectors = 1;
4763
4764         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4765                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4766                                         GFP_KERNEL, adapter->node);
4767                 if (!q_vector)
4768                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4769                                            GFP_KERNEL);
4770                 if (!q_vector)
4771                         goto err_out;
4772
4773                 q_vector->adapter = adapter;
4774                 q_vector->v_idx = v_idx;
4775
4776                 /* Allocate the affinity_hint cpumask, configure the mask */
4777                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4778                         goto err_out;
4779                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4780                 netif_napi_add(adapter->netdev, &q_vector->napi,
4781                                ixgbe_poll, 64);
4782                 adapter->q_vector[v_idx] = q_vector;
4783         }
4784
4785         return 0;
4786
4787 err_out:
4788         while (v_idx) {
4789                 v_idx--;
4790                 q_vector = adapter->q_vector[v_idx];
4791                 netif_napi_del(&q_vector->napi);
4792                 free_cpumask_var(q_vector->affinity_mask);
4793                 kfree(q_vector);
4794                 adapter->q_vector[v_idx] = NULL;
4795         }
4796         return -ENOMEM;
4797 }
4798
4799 /**
4800  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4801  * @adapter: board private structure to initialize
4802  *
4803  * This function frees the memory allocated to the q_vectors.  In addition if
4804  * NAPI is enabled it will delete any references to the NAPI struct prior
4805  * to freeing the q_vector.
4806  **/
4807 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4808 {
4809         int v_idx, num_q_vectors;
4810
4811         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4812                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4813         else
4814                 num_q_vectors = 1;
4815
4816         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4817                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4818                 adapter->q_vector[v_idx] = NULL;
4819                 netif_napi_del(&q_vector->napi);
4820                 free_cpumask_var(q_vector->affinity_mask);
4821                 kfree(q_vector);
4822         }
4823 }
4824
4825 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4826 {
4827         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4828                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4829                 pci_disable_msix(adapter->pdev);
4830                 kfree(adapter->msix_entries);
4831                 adapter->msix_entries = NULL;
4832         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4833                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4834                 pci_disable_msi(adapter->pdev);
4835         }
4836 }
4837
4838 /**
4839  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4840  * @adapter: board private structure to initialize
4841  *
4842  * We determine which interrupt scheme to use based on...
4843  * - Kernel support (MSI, MSI-X)
4844  *   - which can be user-defined (via MODULE_PARAM)
4845  * - Hardware queue count (num_*_queues)
4846  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4847  **/
4848 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4849 {
4850         int err;
4851
4852         /* Number of supported queues */
4853         err = ixgbe_set_num_queues(adapter);
4854         if (err)
4855                 return err;
4856
4857         err = ixgbe_set_interrupt_capability(adapter);
4858         if (err) {
4859                 e_dev_err("Unable to setup interrupt capabilities\n");
4860                 goto err_set_interrupt;
4861         }
4862
4863         err = ixgbe_alloc_q_vectors(adapter);
4864         if (err) {
4865                 e_dev_err("Unable to allocate memory for queue vectors\n");
4866                 goto err_alloc_q_vectors;
4867         }
4868
4869         err = ixgbe_alloc_queues(adapter);
4870         if (err) {
4871                 e_dev_err("Unable to allocate memory for queues\n");
4872                 goto err_alloc_queues;
4873         }
4874
4875         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4876                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4877                    adapter->num_rx_queues, adapter->num_tx_queues);
4878
4879         set_bit(__IXGBE_DOWN, &adapter->state);
4880
4881         return 0;
4882
4883 err_alloc_queues:
4884         ixgbe_free_q_vectors(adapter);
4885 err_alloc_q_vectors:
4886         ixgbe_reset_interrupt_capability(adapter);
4887 err_set_interrupt:
4888         return err;
4889 }
4890
4891 /**
4892  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4893  * @adapter: board private structure to clear interrupt scheme on
4894  *
4895  * We go through and clear interrupt specific resources and reset the structure
4896  * to pre-load conditions
4897  **/
4898 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4899 {
4900         int i;
4901
4902         for (i = 0; i < adapter->num_tx_queues; i++) {
4903                 kfree(adapter->tx_ring[i]);
4904                 adapter->tx_ring[i] = NULL;
4905         }
4906         for (i = 0; i < adapter->num_rx_queues; i++) {
4907                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4908
4909                 /* ixgbe_get_stats64() might access this ring, we must wait
4910                  * a grace period before freeing it.
4911                  */
4912                 kfree_rcu(ring, rcu);
4913                 adapter->rx_ring[i] = NULL;
4914         }
4915
4916         adapter->num_tx_queues = 0;
4917         adapter->num_rx_queues = 0;
4918
4919         ixgbe_free_q_vectors(adapter);
4920         ixgbe_reset_interrupt_capability(adapter);
4921 }
4922
4923 /**
4924  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4925  * @adapter: board private structure to initialize
4926  *
4927  * ixgbe_sw_init initializes the Adapter private data structure.
4928  * Fields are initialized based on PCI device information and
4929  * OS network device settings (MTU size).
4930  **/
4931 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4932 {
4933         struct ixgbe_hw *hw = &adapter->hw;
4934         struct pci_dev *pdev = adapter->pdev;
4935         unsigned int rss;
4936 #ifdef CONFIG_IXGBE_DCB
4937         int j;
4938         struct tc_configuration *tc;
4939 #endif
4940
4941         /* PCI config space info */
4942
4943         hw->vendor_id = pdev->vendor;
4944         hw->device_id = pdev->device;
4945         hw->revision_id = pdev->revision;
4946         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4947         hw->subsystem_device_id = pdev->subsystem_device;
4948
4949         /* Set capability flags */
4950         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4951         adapter->ring_feature[RING_F_RSS].indices = rss;
4952         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4953         switch (hw->mac.type) {
4954         case ixgbe_mac_82598EB:
4955                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4956                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4957                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4958                 break;
4959         case ixgbe_mac_X540:
4960                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4961         case ixgbe_mac_82599EB:
4962                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4963                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4964                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4965                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4966                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4967                 /* Flow Director hash filters enabled */
4968                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4969                 adapter->atr_sample_rate = 20;
4970                 adapter->ring_feature[RING_F_FDIR].indices =
4971                                                          IXGBE_MAX_FDIR_INDICES;
4972                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4973 #ifdef IXGBE_FCOE
4974                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4975                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4976                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4977 #ifdef CONFIG_IXGBE_DCB
4978                 /* Default traffic class to use for FCoE */
4979                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4980 #endif
4981 #endif /* IXGBE_FCOE */
4982                 break;
4983         default:
4984                 break;
4985         }
4986
4987         /* n-tuple support exists, always init our spinlock */
4988         spin_lock_init(&adapter->fdir_perfect_lock);
4989
4990 #ifdef CONFIG_IXGBE_DCB
4991         switch (hw->mac.type) {
4992         case ixgbe_mac_X540:
4993                 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4994                 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4995                 break;
4996         default:
4997                 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4998                 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4999                 break;
5000         }
5001
5002         /* Configure DCB traffic classes */
5003         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5004                 tc = &adapter->dcb_cfg.tc_config[j];
5005                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5006                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5007                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5008                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5009                 tc->dcb_pfc = pfc_disabled;
5010         }
5011
5012         /* Initialize default user to priority mapping, UPx->TC0 */
5013         tc = &adapter->dcb_cfg.tc_config[0];
5014         tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5015         tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5016
5017         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5018         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5019         adapter->dcb_cfg.pfc_mode_enable = false;
5020         adapter->dcb_set_bitmap = 0x00;
5021         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5022         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5023                            MAX_TRAFFIC_CLASS);
5024
5025 #endif
5026
5027         /* default flow control settings */
5028         hw->fc.requested_mode = ixgbe_fc_full;
5029         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5030 #ifdef CONFIG_DCB
5031         adapter->last_lfc_mode = hw->fc.current_mode;
5032 #endif
5033         ixgbe_pbthresh_setup(adapter);
5034         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5035         hw->fc.send_xon = true;
5036         hw->fc.disable_fc_autoneg = false;
5037
5038         /* enable itr by default in dynamic mode */
5039         adapter->rx_itr_setting = 1;
5040         adapter->tx_itr_setting = 1;
5041
5042         /* set defaults for eitr in MegaBytes */
5043         adapter->eitr_low = 10;
5044         adapter->eitr_high = 20;
5045
5046         /* set default ring sizes */
5047         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5048         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5049
5050         /* set default work limits */
5051         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5052
5053         /* initialize eeprom parameters */
5054         if (ixgbe_init_eeprom_params_generic(hw)) {
5055                 e_dev_err("EEPROM initialization failed\n");
5056                 return -EIO;
5057         }
5058
5059         /* enable rx csum by default */
5060         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5061
5062         /* get assigned NUMA node */
5063         adapter->node = dev_to_node(&pdev->dev);
5064
5065         set_bit(__IXGBE_DOWN, &adapter->state);
5066
5067         return 0;
5068 }
5069
5070 /**
5071  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5072  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5073  *
5074  * Return 0 on success, negative on failure
5075  **/
5076 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5077 {
5078         struct device *dev = tx_ring->dev;
5079         int size;
5080
5081         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5082         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5083         if (!tx_ring->tx_buffer_info)
5084                 tx_ring->tx_buffer_info = vzalloc(size);
5085         if (!tx_ring->tx_buffer_info)
5086                 goto err;
5087
5088         /* round up to nearest 4K */
5089         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5090         tx_ring->size = ALIGN(tx_ring->size, 4096);
5091
5092         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5093                                            &tx_ring->dma, GFP_KERNEL);
5094         if (!tx_ring->desc)
5095                 goto err;
5096
5097         tx_ring->next_to_use = 0;
5098         tx_ring->next_to_clean = 0;
5099         return 0;
5100
5101 err:
5102         vfree(tx_ring->tx_buffer_info);
5103         tx_ring->tx_buffer_info = NULL;
5104         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5105         return -ENOMEM;
5106 }
5107
5108 /**
5109  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5110  * @adapter: board private structure
5111  *
5112  * If this function returns with an error, then it's possible one or
5113  * more of the rings is populated (while the rest are not).  It is the
5114  * callers duty to clean those orphaned rings.
5115  *
5116  * Return 0 on success, negative on failure
5117  **/
5118 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5119 {
5120         int i, err = 0;
5121
5122         for (i = 0; i < adapter->num_tx_queues; i++) {
5123                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5124                 if (!err)
5125                         continue;
5126                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5127                 break;
5128         }
5129
5130         return err;
5131 }
5132
5133 /**
5134  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5135  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5136  *
5137  * Returns 0 on success, negative on failure
5138  **/
5139 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5140 {
5141         struct device *dev = rx_ring->dev;
5142         int size;
5143
5144         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5145         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5146         if (!rx_ring->rx_buffer_info)
5147                 rx_ring->rx_buffer_info = vzalloc(size);
5148         if (!rx_ring->rx_buffer_info)
5149                 goto err;
5150
5151         /* Round up to nearest 4K */
5152         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5153         rx_ring->size = ALIGN(rx_ring->size, 4096);
5154
5155         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5156                                            &rx_ring->dma, GFP_KERNEL);
5157
5158         if (!rx_ring->desc)
5159                 goto err;
5160
5161         rx_ring->next_to_clean = 0;
5162         rx_ring->next_to_use = 0;
5163
5164         return 0;
5165 err:
5166         vfree(rx_ring->rx_buffer_info);
5167         rx_ring->rx_buffer_info = NULL;
5168         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5169         return -ENOMEM;
5170 }
5171
5172 /**
5173  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5174  * @adapter: board private structure
5175  *
5176  * If this function returns with an error, then it's possible one or
5177  * more of the rings is populated (while the rest are not).  It is the
5178  * callers duty to clean those orphaned rings.
5179  *
5180  * Return 0 on success, negative on failure
5181  **/
5182 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5183 {
5184         int i, err = 0;
5185
5186         for (i = 0; i < adapter->num_rx_queues; i++) {
5187                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5188                 if (!err)
5189                         continue;
5190                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5191                 break;
5192         }
5193
5194         return err;
5195 }
5196
5197 /**
5198  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5199  * @tx_ring: Tx descriptor ring for a specific queue
5200  *
5201  * Free all transmit software resources
5202  **/
5203 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5204 {
5205         ixgbe_clean_tx_ring(tx_ring);
5206
5207         vfree(tx_ring->tx_buffer_info);
5208         tx_ring->tx_buffer_info = NULL;
5209
5210         /* if not set, then don't free */
5211         if (!tx_ring->desc)
5212                 return;
5213
5214         dma_free_coherent(tx_ring->dev, tx_ring->size,
5215                           tx_ring->desc, tx_ring->dma);
5216
5217         tx_ring->desc = NULL;
5218 }
5219
5220 /**
5221  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5222  * @adapter: board private structure
5223  *
5224  * Free all transmit software resources
5225  **/
5226 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5227 {
5228         int i;
5229
5230         for (i = 0; i < adapter->num_tx_queues; i++)
5231                 if (adapter->tx_ring[i]->desc)
5232                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5233 }
5234
5235 /**
5236  * ixgbe_free_rx_resources - Free Rx Resources
5237  * @rx_ring: ring to clean the resources from
5238  *
5239  * Free all receive software resources
5240  **/
5241 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5242 {
5243         ixgbe_clean_rx_ring(rx_ring);
5244
5245         vfree(rx_ring->rx_buffer_info);
5246         rx_ring->rx_buffer_info = NULL;
5247
5248         /* if not set, then don't free */
5249         if (!rx_ring->desc)
5250                 return;
5251
5252         dma_free_coherent(rx_ring->dev, rx_ring->size,
5253                           rx_ring->desc, rx_ring->dma);
5254
5255         rx_ring->desc = NULL;
5256 }
5257
5258 /**
5259  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5260  * @adapter: board private structure
5261  *
5262  * Free all receive software resources
5263  **/
5264 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5265 {
5266         int i;
5267
5268         for (i = 0; i < adapter->num_rx_queues; i++)
5269                 if (adapter->rx_ring[i]->desc)
5270                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5271 }
5272
5273 /**
5274  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5275  * @netdev: network interface device structure
5276  * @new_mtu: new value for maximum frame size
5277  *
5278  * Returns 0 on success, negative on failure
5279  **/
5280 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5281 {
5282         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5283         struct ixgbe_hw *hw = &adapter->hw;
5284         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5285
5286         /* MTU < 68 is an error and causes problems on some kernels */
5287         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5288             hw->mac.type != ixgbe_mac_X540) {
5289                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5290                         return -EINVAL;
5291         } else {
5292                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5293                         return -EINVAL;
5294         }
5295
5296         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5297         /* must set new MTU before calling down or up */
5298         netdev->mtu = new_mtu;
5299
5300         if (netif_running(netdev))
5301                 ixgbe_reinit_locked(adapter);
5302
5303         return 0;
5304 }
5305
5306 /**
5307  * ixgbe_open - Called when a network interface is made active
5308  * @netdev: network interface device structure
5309  *
5310  * Returns 0 on success, negative value on failure
5311  *
5312  * The open entry point is called when a network interface is made
5313  * active by the system (IFF_UP).  At this point all resources needed
5314  * for transmit and receive operations are allocated, the interrupt
5315  * handler is registered with the OS, the watchdog timer is started,
5316  * and the stack is notified that the interface is ready.
5317  **/
5318 static int ixgbe_open(struct net_device *netdev)
5319 {
5320         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5321         int err;
5322
5323         /* disallow open during test */
5324         if (test_bit(__IXGBE_TESTING, &adapter->state))
5325                 return -EBUSY;
5326
5327         netif_carrier_off(netdev);
5328
5329         /* allocate transmit descriptors */
5330         err = ixgbe_setup_all_tx_resources(adapter);
5331         if (err)
5332                 goto err_setup_tx;
5333
5334         /* allocate receive descriptors */
5335         err = ixgbe_setup_all_rx_resources(adapter);
5336         if (err)
5337                 goto err_setup_rx;
5338
5339         ixgbe_configure(adapter);
5340
5341         err = ixgbe_request_irq(adapter);
5342         if (err)
5343                 goto err_req_irq;
5344
5345         ixgbe_up_complete(adapter);
5346
5347         return 0;
5348
5349 err_req_irq:
5350 err_setup_rx:
5351         ixgbe_free_all_rx_resources(adapter);
5352 err_setup_tx:
5353         ixgbe_free_all_tx_resources(adapter);
5354         ixgbe_reset(adapter);
5355
5356         return err;
5357 }
5358
5359 /**
5360  * ixgbe_close - Disables a network interface
5361  * @netdev: network interface device structure
5362  *
5363  * Returns 0, this is not allowed to fail
5364  *
5365  * The close entry point is called when an interface is de-activated
5366  * by the OS.  The hardware is still under the drivers control, but
5367  * needs to be disabled.  A global MAC reset is issued to stop the
5368  * hardware, and all transmit and receive resources are freed.
5369  **/
5370 static int ixgbe_close(struct net_device *netdev)
5371 {
5372         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5373
5374         ixgbe_down(adapter);
5375         ixgbe_free_irq(adapter);
5376
5377         ixgbe_fdir_filter_exit(adapter);
5378
5379         ixgbe_free_all_tx_resources(adapter);
5380         ixgbe_free_all_rx_resources(adapter);
5381
5382         ixgbe_release_hw_control(adapter);
5383
5384         return 0;
5385 }
5386
5387 #ifdef CONFIG_PM
5388 static int ixgbe_resume(struct pci_dev *pdev)
5389 {
5390         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5391         struct net_device *netdev = adapter->netdev;
5392         u32 err;
5393
5394         pci_set_power_state(pdev, PCI_D0);
5395         pci_restore_state(pdev);
5396         /*
5397          * pci_restore_state clears dev->state_saved so call
5398          * pci_save_state to restore it.
5399          */
5400         pci_save_state(pdev);
5401
5402         err = pci_enable_device_mem(pdev);
5403         if (err) {
5404                 e_dev_err("Cannot enable PCI device from suspend\n");
5405                 return err;
5406         }
5407         pci_set_master(pdev);
5408
5409         pci_wake_from_d3(pdev, false);
5410
5411         err = ixgbe_init_interrupt_scheme(adapter);
5412         if (err) {
5413                 e_dev_err("Cannot initialize interrupts for device\n");
5414                 return err;
5415         }
5416
5417         ixgbe_reset(adapter);
5418
5419         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5420
5421         if (netif_running(netdev)) {
5422                 err = ixgbe_open(netdev);
5423                 if (err)
5424                         return err;
5425         }
5426
5427         netif_device_attach(netdev);
5428
5429         return 0;
5430 }
5431 #endif /* CONFIG_PM */
5432
5433 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5434 {
5435         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5436         struct net_device *netdev = adapter->netdev;
5437         struct ixgbe_hw *hw = &adapter->hw;
5438         u32 ctrl, fctrl;
5439         u32 wufc = adapter->wol;
5440 #ifdef CONFIG_PM
5441         int retval = 0;
5442 #endif
5443
5444         netif_device_detach(netdev);
5445
5446         if (netif_running(netdev)) {
5447                 ixgbe_down(adapter);
5448                 ixgbe_free_irq(adapter);
5449                 ixgbe_free_all_tx_resources(adapter);
5450                 ixgbe_free_all_rx_resources(adapter);
5451         }
5452
5453         ixgbe_clear_interrupt_scheme(adapter);
5454 #ifdef CONFIG_DCB
5455         kfree(adapter->ixgbe_ieee_pfc);
5456         kfree(adapter->ixgbe_ieee_ets);
5457 #endif
5458
5459 #ifdef CONFIG_PM
5460         retval = pci_save_state(pdev);
5461         if (retval)
5462                 return retval;
5463
5464 #endif
5465         if (wufc) {
5466                 ixgbe_set_rx_mode(netdev);
5467
5468                 /* turn on all-multi mode if wake on multicast is enabled */
5469                 if (wufc & IXGBE_WUFC_MC) {
5470                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5471                         fctrl |= IXGBE_FCTRL_MPE;
5472                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5473                 }
5474
5475                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5476                 ctrl |= IXGBE_CTRL_GIO_DIS;
5477                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5478
5479                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5480         } else {
5481                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5482                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5483         }
5484
5485         switch (hw->mac.type) {
5486         case ixgbe_mac_82598EB:
5487                 pci_wake_from_d3(pdev, false);
5488                 break;
5489         case ixgbe_mac_82599EB:
5490         case ixgbe_mac_X540:
5491                 pci_wake_from_d3(pdev, !!wufc);
5492                 break;
5493         default:
5494                 break;
5495         }
5496
5497         *enable_wake = !!wufc;
5498
5499         ixgbe_release_hw_control(adapter);
5500
5501         pci_disable_device(pdev);
5502
5503         return 0;
5504 }
5505
5506 #ifdef CONFIG_PM
5507 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5508 {
5509         int retval;
5510         bool wake;
5511
5512         retval = __ixgbe_shutdown(pdev, &wake);
5513         if (retval)
5514                 return retval;
5515
5516         if (wake) {
5517                 pci_prepare_to_sleep(pdev);
5518         } else {
5519                 pci_wake_from_d3(pdev, false);
5520                 pci_set_power_state(pdev, PCI_D3hot);
5521         }
5522
5523         return 0;
5524 }
5525 #endif /* CONFIG_PM */
5526
5527 static void ixgbe_shutdown(struct pci_dev *pdev)
5528 {
5529         bool wake;
5530
5531         __ixgbe_shutdown(pdev, &wake);
5532
5533         if (system_state == SYSTEM_POWER_OFF) {
5534                 pci_wake_from_d3(pdev, wake);
5535                 pci_set_power_state(pdev, PCI_D3hot);
5536         }
5537 }
5538
5539 /**
5540  * ixgbe_update_stats - Update the board statistics counters.
5541  * @adapter: board private structure
5542  **/
5543 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5544 {
5545         struct net_device *netdev = adapter->netdev;
5546         struct ixgbe_hw *hw = &adapter->hw;
5547         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5548         u64 total_mpc = 0;
5549         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5550         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5551         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5552         u64 bytes = 0, packets = 0;
5553 #ifdef IXGBE_FCOE
5554         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5555         unsigned int cpu;
5556         u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5557 #endif /* IXGBE_FCOE */
5558
5559         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5560             test_bit(__IXGBE_RESETTING, &adapter->state))
5561                 return;
5562
5563         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5564                 u64 rsc_count = 0;
5565                 u64 rsc_flush = 0;
5566                 for (i = 0; i < 16; i++)
5567                         adapter->hw_rx_no_dma_resources +=
5568                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5569                 for (i = 0; i < adapter->num_rx_queues; i++) {
5570                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5571                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5572                 }
5573                 adapter->rsc_total_count = rsc_count;
5574                 adapter->rsc_total_flush = rsc_flush;
5575         }
5576
5577         for (i = 0; i < adapter->num_rx_queues; i++) {
5578                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5579                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5580                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5581                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5582                 bytes += rx_ring->stats.bytes;
5583                 packets += rx_ring->stats.packets;
5584         }
5585         adapter->non_eop_descs = non_eop_descs;
5586         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5587         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5588         netdev->stats.rx_bytes = bytes;
5589         netdev->stats.rx_packets = packets;
5590
5591         bytes = 0;
5592         packets = 0;
5593         /* gather some stats to the adapter struct that are per queue */
5594         for (i = 0; i < adapter->num_tx_queues; i++) {
5595                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5596                 restart_queue += tx_ring->tx_stats.restart_queue;
5597                 tx_busy += tx_ring->tx_stats.tx_busy;
5598                 bytes += tx_ring->stats.bytes;
5599                 packets += tx_ring->stats.packets;
5600         }
5601         adapter->restart_queue = restart_queue;
5602         adapter->tx_busy = tx_busy;
5603         netdev->stats.tx_bytes = bytes;
5604         netdev->stats.tx_packets = packets;
5605
5606         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5607
5608         /* 8 register reads */
5609         for (i = 0; i < 8; i++) {
5610                 /* for packet buffers not used, the register should read 0 */
5611                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5612                 missed_rx += mpc;
5613                 hwstats->mpc[i] += mpc;
5614                 total_mpc += hwstats->mpc[i];
5615                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5616                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5617                 switch (hw->mac.type) {
5618                 case ixgbe_mac_82598EB:
5619                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5620                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5621                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5622                         hwstats->pxonrxc[i] +=
5623                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5624                         break;
5625                 case ixgbe_mac_82599EB:
5626                 case ixgbe_mac_X540:
5627                         hwstats->pxonrxc[i] +=
5628                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5629                         break;
5630                 default:
5631                         break;
5632                 }
5633         }
5634
5635         /*16 register reads */
5636         for (i = 0; i < 16; i++) {
5637                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5638                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5639                 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5640                     (hw->mac.type == ixgbe_mac_X540)) {
5641                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5642                         IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5643                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5644                         IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5645                 }
5646         }
5647
5648         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5649         /* work around hardware counting issue */
5650         hwstats->gprc -= missed_rx;
5651
5652         ixgbe_update_xoff_received(adapter);
5653
5654         /* 82598 hardware only has a 32 bit counter in the high register */
5655         switch (hw->mac.type) {
5656         case ixgbe_mac_82598EB:
5657                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5658                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5659                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5660                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5661                 break;
5662         case ixgbe_mac_X540:
5663                 /* OS2BMC stats are X540 only*/
5664                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5665                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5666                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5667                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5668         case ixgbe_mac_82599EB:
5669                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5670                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5671                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5672                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5673                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5674                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5675                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5676                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5677                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5678 #ifdef IXGBE_FCOE
5679                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5680                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5681                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5682                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5683                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5684                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5685                 /* Add up per cpu counters for total ddp aloc fail */
5686                 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5687                         for_each_possible_cpu(cpu) {
5688                                 fcoe_noddp_counts_sum +=
5689                                         *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5690                                 fcoe_noddp_ext_buff_counts_sum +=
5691                                         *per_cpu_ptr(fcoe->
5692                                                 pcpu_noddp_ext_buff, cpu);
5693                         }
5694                 }
5695                 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5696                 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5697 #endif /* IXGBE_FCOE */
5698                 break;
5699         default:
5700                 break;
5701         }
5702         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5703         hwstats->bprc += bprc;
5704         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5705         if (hw->mac.type == ixgbe_mac_82598EB)
5706                 hwstats->mprc -= bprc;
5707         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5708         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5709         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5710         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5711         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5712         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5713         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5714         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5715         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5716         hwstats->lxontxc += lxon;
5717         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5718         hwstats->lxofftxc += lxoff;
5719         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5720         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5721         /*
5722          * 82598 errata - tx of flow control packets is included in tx counters
5723          */
5724         xon_off_tot = lxon + lxoff;
5725         hwstats->gptc -= xon_off_tot;
5726         hwstats->mptc -= xon_off_tot;
5727         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5728         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5729         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5730         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5731         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5732         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5733         hwstats->ptc64 -= xon_off_tot;
5734         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5735         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5736         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5737         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5738         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5739         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5740
5741         /* Fill out the OS statistics structure */
5742         netdev->stats.multicast = hwstats->mprc;
5743
5744         /* Rx Errors */
5745         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5746         netdev->stats.rx_dropped = 0;
5747         netdev->stats.rx_length_errors = hwstats->rlec;
5748         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5749         netdev->stats.rx_missed_errors = total_mpc;
5750 }
5751
5752 /**
5753  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5754  * @adapter - pointer to the device adapter structure
5755  **/
5756 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5757 {
5758         struct ixgbe_hw *hw = &adapter->hw;
5759         int i;
5760
5761         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5762                 return;
5763
5764         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5765
5766         /* if interface is down do nothing */
5767         if (test_bit(__IXGBE_DOWN, &adapter->state))
5768                 return;
5769
5770         /* do nothing if we are not using signature filters */
5771         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5772                 return;
5773
5774         adapter->fdir_overflow++;
5775
5776         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5777                 for (i = 0; i < adapter->num_tx_queues; i++)
5778                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5779                                 &(adapter->tx_ring[i]->state));
5780                 /* re-enable flow director interrupts */
5781                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5782         } else {
5783                 e_err(probe, "failed to finish FDIR re-initialization, "
5784                       "ignored adding FDIR ATR filters\n");
5785         }
5786 }
5787
5788 /**
5789  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5790  * @adapter - pointer to the device adapter structure
5791  *
5792  * This function serves two purposes.  First it strobes the interrupt lines
5793  * in order to make certain interrupts are occuring.  Secondly it sets the
5794  * bits needed to check for TX hangs.  As a result we should immediately
5795  * determine if a hang has occured.
5796  */
5797 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5798 {
5799         struct ixgbe_hw *hw = &adapter->hw;
5800         u64 eics = 0;
5801         int i;
5802
5803         /* If we're down or resetting, just bail */
5804         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5805             test_bit(__IXGBE_RESETTING, &adapter->state))
5806                 return;
5807
5808         /* Force detection of hung controller */
5809         if (netif_carrier_ok(adapter->netdev)) {
5810                 for (i = 0; i < adapter->num_tx_queues; i++)
5811                         set_check_for_tx_hang(adapter->tx_ring[i]);
5812         }
5813
5814         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5815                 /*
5816                  * for legacy and MSI interrupts don't set any bits
5817                  * that are enabled for EIAM, because this operation
5818                  * would set *both* EIMS and EICS for any bit in EIAM
5819                  */
5820                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5821                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5822         } else {
5823                 /* get one bit for every active tx/rx interrupt vector */
5824                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5825                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5826                         if (qv->rx.ring || qv->tx.ring)
5827                                 eics |= ((u64)1 << i);
5828                 }
5829         }
5830
5831         /* Cause software interrupt to ensure rings are cleaned */
5832         ixgbe_irq_rearm_queues(adapter, eics);
5833
5834 }
5835
5836 /**
5837  * ixgbe_watchdog_update_link - update the link status
5838  * @adapter - pointer to the device adapter structure
5839  * @link_speed - pointer to a u32 to store the link_speed
5840  **/
5841 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5842 {
5843         struct ixgbe_hw *hw = &adapter->hw;
5844         u32 link_speed = adapter->link_speed;
5845         bool link_up = adapter->link_up;
5846         int i;
5847
5848         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5849                 return;
5850
5851         if (hw->mac.ops.check_link) {
5852                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5853         } else {
5854                 /* always assume link is up, if no check link function */
5855                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5856                 link_up = true;
5857         }
5858         if (link_up) {
5859                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5860                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5861                                 hw->mac.ops.fc_enable(hw, i);
5862                 } else {
5863                         hw->mac.ops.fc_enable(hw, 0);
5864                 }
5865         }
5866
5867         if (link_up ||
5868             time_after(jiffies, (adapter->link_check_timeout +
5869                                  IXGBE_TRY_LINK_TIMEOUT))) {
5870                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5871                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5872                 IXGBE_WRITE_FLUSH(hw);
5873         }
5874
5875         adapter->link_up = link_up;
5876         adapter->link_speed = link_speed;
5877 }
5878
5879 /**
5880  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5881  *                             print link up message
5882  * @adapter - pointer to the device adapter structure
5883  **/
5884 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5885 {
5886         struct net_device *netdev = adapter->netdev;
5887         struct ixgbe_hw *hw = &adapter->hw;
5888         u32 link_speed = adapter->link_speed;
5889         bool flow_rx, flow_tx;
5890
5891         /* only continue if link was previously down */
5892         if (netif_carrier_ok(netdev))
5893                 return;
5894
5895         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5896
5897         switch (hw->mac.type) {
5898         case ixgbe_mac_82598EB: {
5899                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5900                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5901                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5902                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5903         }
5904                 break;
5905         case ixgbe_mac_X540:
5906         case ixgbe_mac_82599EB: {
5907                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5908                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5909                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5910                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5911         }
5912                 break;
5913         default:
5914                 flow_tx = false;
5915                 flow_rx = false;
5916                 break;
5917         }
5918         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5919                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5920                "10 Gbps" :
5921                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5922                "1 Gbps" :
5923                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5924                "100 Mbps" :
5925                "unknown speed"))),
5926                ((flow_rx && flow_tx) ? "RX/TX" :
5927                (flow_rx ? "RX" :
5928                (flow_tx ? "TX" : "None"))));
5929
5930         netif_carrier_on(netdev);
5931         ixgbe_check_vf_rate_limit(adapter);
5932 }
5933
5934 /**
5935  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5936  *                               print link down message
5937  * @adapter - pointer to the adapter structure
5938  **/
5939 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5940 {
5941         struct net_device *netdev = adapter->netdev;
5942         struct ixgbe_hw *hw = &adapter->hw;
5943
5944         adapter->link_up = false;
5945         adapter->link_speed = 0;
5946
5947         /* only continue if link was up previously */
5948         if (!netif_carrier_ok(netdev))
5949                 return;
5950
5951         /* poll for SFP+ cable when link is down */
5952         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5953                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5954
5955         e_info(drv, "NIC Link is Down\n");
5956         netif_carrier_off(netdev);
5957 }
5958
5959 /**
5960  * ixgbe_watchdog_flush_tx - flush queues on link down
5961  * @adapter - pointer to the device adapter structure
5962  **/
5963 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5964 {
5965         int i;
5966         int some_tx_pending = 0;
5967
5968         if (!netif_carrier_ok(adapter->netdev)) {
5969                 for (i = 0; i < adapter->num_tx_queues; i++) {
5970                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5971                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5972                                 some_tx_pending = 1;
5973                                 break;
5974                         }
5975                 }
5976
5977                 if (some_tx_pending) {
5978                         /* We've lost link, so the controller stops DMA,
5979                          * but we've got queued Tx work that's never going
5980                          * to get done, so reset controller to flush Tx.
5981                          * (Do the reset outside of interrupt context).
5982                          */
5983                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5984                 }
5985         }
5986 }
5987
5988 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5989 {
5990         u32 ssvpc;
5991
5992         /* Do not perform spoof check for 82598 */
5993         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5994                 return;
5995
5996         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5997
5998         /*
5999          * ssvpc register is cleared on read, if zero then no
6000          * spoofed packets in the last interval.
6001          */
6002         if (!ssvpc)
6003                 return;
6004
6005         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6006 }
6007
6008 /**
6009  * ixgbe_watchdog_subtask - check and bring link up
6010  * @adapter - pointer to the device adapter structure
6011  **/
6012 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6013 {
6014         /* if interface is down do nothing */
6015         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6016             test_bit(__IXGBE_RESETTING, &adapter->state))
6017                 return;
6018
6019         ixgbe_watchdog_update_link(adapter);
6020
6021         if (adapter->link_up)
6022                 ixgbe_watchdog_link_is_up(adapter);
6023         else
6024                 ixgbe_watchdog_link_is_down(adapter);
6025
6026         ixgbe_spoof_check(adapter);
6027         ixgbe_update_stats(adapter);
6028
6029         ixgbe_watchdog_flush_tx(adapter);
6030 }
6031
6032 /**
6033  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6034  * @adapter - the ixgbe adapter structure
6035  **/
6036 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6037 {
6038         struct ixgbe_hw *hw = &adapter->hw;
6039         s32 err;
6040
6041         /* not searching for SFP so there is nothing to do here */
6042         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6043             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6044                 return;
6045
6046         /* someone else is in init, wait until next service event */
6047         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6048                 return;
6049
6050         err = hw->phy.ops.identify_sfp(hw);
6051         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6052                 goto sfp_out;
6053
6054         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6055                 /* If no cable is present, then we need to reset
6056                  * the next time we find a good cable. */
6057                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6058         }
6059
6060         /* exit on error */
6061         if (err)
6062                 goto sfp_out;
6063
6064         /* exit if reset not needed */
6065         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6066                 goto sfp_out;
6067
6068         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6069
6070         /*
6071          * A module may be identified correctly, but the EEPROM may not have
6072          * support for that module.  setup_sfp() will fail in that case, so
6073          * we should not allow that module to load.
6074          */
6075         if (hw->mac.type == ixgbe_mac_82598EB)
6076                 err = hw->phy.ops.reset(hw);
6077         else
6078                 err = hw->mac.ops.setup_sfp(hw);
6079
6080         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6081                 goto sfp_out;
6082
6083         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6084         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6085
6086 sfp_out:
6087         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6088
6089         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6090             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6091                 e_dev_err("failed to initialize because an unsupported "
6092                           "SFP+ module type was detected.\n");
6093                 e_dev_err("Reload the driver after installing a "
6094                           "supported module.\n");
6095                 unregister_netdev(adapter->netdev);
6096         }
6097 }
6098
6099 /**
6100  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6101  * @adapter - the ixgbe adapter structure
6102  **/
6103 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6104 {
6105         struct ixgbe_hw *hw = &adapter->hw;
6106         u32 autoneg;
6107         bool negotiation;
6108
6109         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6110                 return;
6111
6112         /* someone else is in init, wait until next service event */
6113         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6114                 return;
6115
6116         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6117
6118         autoneg = hw->phy.autoneg_advertised;
6119         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6120                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6121         if (hw->mac.ops.setup_link)
6122                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6123
6124         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6125         adapter->link_check_timeout = jiffies;
6126         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6127 }
6128
6129 #ifdef CONFIG_PCI_IOV
6130 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6131 {
6132         int vf;
6133         struct ixgbe_hw *hw = &adapter->hw;
6134         struct net_device *netdev = adapter->netdev;
6135         u32 gpc;
6136         u32 ciaa, ciad;
6137
6138         gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6139         if (gpc) /* If incrementing then no need for the check below */
6140                 return;
6141         /*
6142          * Check to see if a bad DMA write target from an errant or
6143          * malicious VF has caused a PCIe error.  If so then we can
6144          * issue a VFLR to the offending VF(s) and then resume without
6145          * requesting a full slot reset.
6146          */
6147
6148         for (vf = 0; vf < adapter->num_vfs; vf++) {
6149                 ciaa = (vf << 16) | 0x80000000;
6150                 /* 32 bit read so align, we really want status at offset 6 */
6151                 ciaa |= PCI_COMMAND;
6152                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6153                 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6154                 ciaa &= 0x7FFFFFFF;
6155                 /* disable debug mode asap after reading data */
6156                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6157                 /* Get the upper 16 bits which will be the PCI status reg */
6158                 ciad >>= 16;
6159                 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6160                         netdev_err(netdev, "VF %d Hung DMA\n", vf);
6161                         /* Issue VFLR */
6162                         ciaa = (vf << 16) | 0x80000000;
6163                         ciaa |= 0xA8;
6164                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6165                         ciad = 0x00008000;  /* VFLR */
6166                         IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6167                         ciaa &= 0x7FFFFFFF;
6168                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6169                 }
6170         }
6171 }
6172
6173 #endif
6174 /**
6175  * ixgbe_service_timer - Timer Call-back
6176  * @data: pointer to adapter cast into an unsigned long
6177  **/
6178 static void ixgbe_service_timer(unsigned long data)
6179 {
6180         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6181         unsigned long next_event_offset;
6182         bool ready = true;
6183
6184 #ifdef CONFIG_PCI_IOV
6185         ready = false;
6186
6187         /*
6188          * don't bother with SR-IOV VF DMA hang check if there are
6189          * no VFs or the link is down
6190          */
6191         if (!adapter->num_vfs ||
6192             (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6193                 ready = true;
6194                 goto normal_timer_service;
6195         }
6196
6197         /* If we have VFs allocated then we must check for DMA hangs */
6198         ixgbe_check_for_bad_vf(adapter);
6199         next_event_offset = HZ / 50;
6200         adapter->timer_event_accumulator++;
6201
6202         if (adapter->timer_event_accumulator >= 100) {
6203                 ready = true;
6204                 adapter->timer_event_accumulator = 0;
6205         }
6206
6207         goto schedule_event;
6208
6209 normal_timer_service:
6210 #endif
6211         /* poll faster when waiting for link */
6212         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6213                 next_event_offset = HZ / 10;
6214         else
6215                 next_event_offset = HZ * 2;
6216
6217 #ifdef CONFIG_PCI_IOV
6218 schedule_event:
6219 #endif
6220         /* Reset the timer */
6221         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6222
6223         if (ready)
6224                 ixgbe_service_event_schedule(adapter);
6225 }
6226
6227 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6228 {
6229         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6230                 return;
6231
6232         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6233
6234         /* If we're already down or resetting, just bail */
6235         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6236             test_bit(__IXGBE_RESETTING, &adapter->state))
6237                 return;
6238
6239         ixgbe_dump(adapter);
6240         netdev_err(adapter->netdev, "Reset adapter\n");
6241         adapter->tx_timeout_count++;
6242
6243         ixgbe_reinit_locked(adapter);
6244 }
6245
6246 /**
6247  * ixgbe_service_task - manages and runs subtasks
6248  * @work: pointer to work_struct containing our data
6249  **/
6250 static void ixgbe_service_task(struct work_struct *work)
6251 {
6252         struct ixgbe_adapter *adapter = container_of(work,
6253                                                      struct ixgbe_adapter,
6254                                                      service_task);
6255
6256         ixgbe_reset_subtask(adapter);
6257         ixgbe_sfp_detection_subtask(adapter);
6258         ixgbe_sfp_link_config_subtask(adapter);
6259         ixgbe_check_overtemp_subtask(adapter);
6260         ixgbe_watchdog_subtask(adapter);
6261         ixgbe_fdir_reinit_subtask(adapter);
6262         ixgbe_check_hang_subtask(adapter);
6263
6264         ixgbe_service_event_complete(adapter);
6265 }
6266
6267 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6268                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6269 {
6270         struct ixgbe_adv_tx_context_desc *context_desc;
6271         u16 i = tx_ring->next_to_use;
6272
6273         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6274
6275         i++;
6276         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6277
6278         /* set bits to identify this as an advanced context descriptor */
6279         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6280
6281         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6282         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6283         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6284         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6285 }
6286
6287 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6288                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6289 {
6290         int err;
6291         u32 vlan_macip_lens, type_tucmd;
6292         u32 mss_l4len_idx, l4len;
6293
6294         if (!skb_is_gso(skb))
6295                 return 0;
6296
6297         if (skb_header_cloned(skb)) {
6298                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6299                 if (err)
6300                         return err;
6301         }
6302
6303         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6304         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6305
6306         if (protocol == __constant_htons(ETH_P_IP)) {
6307                 struct iphdr *iph = ip_hdr(skb);
6308                 iph->tot_len = 0;
6309                 iph->check = 0;
6310                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6311                                                          iph->daddr, 0,
6312                                                          IPPROTO_TCP,
6313                                                          0);
6314                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6315         } else if (skb_is_gso_v6(skb)) {
6316                 ipv6_hdr(skb)->payload_len = 0;
6317                 tcp_hdr(skb)->check =
6318                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6319                                      &ipv6_hdr(skb)->daddr,
6320                                      0, IPPROTO_TCP, 0);
6321         }
6322
6323         l4len = tcp_hdrlen(skb);
6324         *hdr_len = skb_transport_offset(skb) + l4len;
6325
6326         /* mss_l4len_id: use 1 as index for TSO */
6327         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6328         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6329         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6330
6331         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6332         vlan_macip_lens = skb_network_header_len(skb);
6333         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6334         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6335
6336         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6337                           mss_l4len_idx);
6338
6339         return 1;
6340 }
6341
6342 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6343                           struct sk_buff *skb, u32 tx_flags,
6344                           __be16 protocol)
6345 {
6346         u32 vlan_macip_lens = 0;
6347         u32 mss_l4len_idx = 0;
6348         u32 type_tucmd = 0;
6349
6350         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6351             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6352                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6353                         return false;
6354         } else {
6355                 u8 l4_hdr = 0;
6356                 switch (protocol) {
6357                 case __constant_htons(ETH_P_IP):
6358                         vlan_macip_lens |= skb_network_header_len(skb);
6359                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6360                         l4_hdr = ip_hdr(skb)->protocol;
6361                         break;
6362                 case __constant_htons(ETH_P_IPV6):
6363                         vlan_macip_lens |= skb_network_header_len(skb);
6364                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6365                         break;
6366                 default:
6367                         if (unlikely(net_ratelimit())) {
6368                                 dev_warn(tx_ring->dev,
6369                                  "partial checksum but proto=%x!\n",
6370                                  skb->protocol);
6371                         }
6372                         break;
6373                 }
6374
6375                 switch (l4_hdr) {
6376                 case IPPROTO_TCP:
6377                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6378                         mss_l4len_idx = tcp_hdrlen(skb) <<
6379                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6380                         break;
6381                 case IPPROTO_SCTP:
6382                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6383                         mss_l4len_idx = sizeof(struct sctphdr) <<
6384                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6385                         break;
6386                 case IPPROTO_UDP:
6387                         mss_l4len_idx = sizeof(struct udphdr) <<
6388                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6389                         break;
6390                 default:
6391                         if (unlikely(net_ratelimit())) {
6392                                 dev_warn(tx_ring->dev,
6393                                  "partial checksum but l4 proto=%x!\n",
6394                                  skb->protocol);
6395                         }
6396                         break;
6397                 }
6398         }
6399
6400         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6401         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6402
6403         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6404                           type_tucmd, mss_l4len_idx);
6405
6406         return (skb->ip_summed == CHECKSUM_PARTIAL);
6407 }
6408
6409 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6410 {
6411         /* set type for advanced descriptor with frame checksum insertion */
6412         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6413                                       IXGBE_ADVTXD_DCMD_IFCS |
6414                                       IXGBE_ADVTXD_DCMD_DEXT);
6415
6416         /* set HW vlan bit if vlan is present */
6417         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6418                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6419
6420         /* set segmentation enable bits for TSO/FSO */
6421 #ifdef IXGBE_FCOE
6422         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6423 #else
6424         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6425 #endif
6426                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6427
6428         return cmd_type;
6429 }
6430
6431 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6432 {
6433         __le32 olinfo_status =
6434                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6435
6436         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6437                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6438                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6439                 /* enble IPv4 checksum for TSO */
6440                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6441                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6442         }
6443
6444         /* enable L4 checksum for TSO and TX checksum offload */
6445         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6446                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6447
6448 #ifdef IXGBE_FCOE
6449         /* use index 1 context for FCOE/FSO */
6450         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6451                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6452                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6453
6454 #endif
6455         /*
6456          * Check Context must be set if Tx switch is enabled, which it
6457          * always is for case where virtual functions are running
6458          */
6459         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6460                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6461
6462         return olinfo_status;
6463 }
6464
6465 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6466                        IXGBE_TXD_CMD_RS)
6467
6468 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6469                          struct sk_buff *skb,
6470                          struct ixgbe_tx_buffer *first,
6471                          u32 tx_flags,
6472                          const u8 hdr_len)
6473 {
6474         struct device *dev = tx_ring->dev;
6475         struct ixgbe_tx_buffer *tx_buffer_info;
6476         union ixgbe_adv_tx_desc *tx_desc;
6477         dma_addr_t dma;
6478         __le32 cmd_type, olinfo_status;
6479         struct skb_frag_struct *frag;
6480         unsigned int f = 0;
6481         unsigned int data_len = skb->data_len;
6482         unsigned int size = skb_headlen(skb);
6483         u32 offset = 0;
6484         u32 paylen = skb->len - hdr_len;
6485         u16 i = tx_ring->next_to_use;
6486         u16 gso_segs;
6487
6488 #ifdef IXGBE_FCOE
6489         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6490                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6491                         data_len -= sizeof(struct fcoe_crc_eof);
6492                 } else {
6493                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6494                         data_len = 0;
6495                 }
6496         }
6497
6498 #endif
6499         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6500         if (dma_mapping_error(dev, dma))
6501                 goto dma_error;
6502
6503         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6504         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6505
6506         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6507
6508         for (;;) {
6509                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6510                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6511                         tx_desc->read.cmd_type_len =
6512                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6513                         tx_desc->read.olinfo_status = olinfo_status;
6514
6515                         offset += IXGBE_MAX_DATA_PER_TXD;
6516                         size -= IXGBE_MAX_DATA_PER_TXD;
6517
6518                         tx_desc++;
6519                         i++;
6520                         if (i == tx_ring->count) {
6521                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6522                                 i = 0;
6523                         }
6524                 }
6525
6526                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6527                 tx_buffer_info->length = offset + size;
6528                 tx_buffer_info->tx_flags = tx_flags;
6529                 tx_buffer_info->dma = dma;
6530
6531                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6532                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6533                 tx_desc->read.olinfo_status = olinfo_status;
6534
6535                 if (!data_len)
6536                         break;
6537
6538                 frag = &skb_shinfo(skb)->frags[f];
6539 #ifdef IXGBE_FCOE
6540                 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6541 #else
6542                 size = skb_frag_size(frag);
6543 #endif
6544                 data_len -= size;
6545                 f++;
6546
6547                 offset = 0;
6548                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6549
6550                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6551                 if (dma_mapping_error(dev, dma))
6552                         goto dma_error;
6553
6554                 tx_desc++;
6555                 i++;
6556                 if (i == tx_ring->count) {
6557                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6558                         i = 0;
6559                 }
6560         }
6561
6562         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6563
6564         i++;
6565         if (i == tx_ring->count)
6566                 i = 0;
6567
6568         tx_ring->next_to_use = i;
6569
6570         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6571                 gso_segs = skb_shinfo(skb)->gso_segs;
6572 #ifdef IXGBE_FCOE
6573         /* adjust for FCoE Sequence Offload */
6574         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6575                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6576                                         skb_shinfo(skb)->gso_size);
6577 #endif /* IXGBE_FCOE */
6578         else
6579                 gso_segs = 1;
6580
6581         /* multiply data chunks by size of headers */
6582         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6583         tx_buffer_info->gso_segs = gso_segs;
6584         tx_buffer_info->skb = skb;
6585
6586         /* set the timestamp */
6587         first->time_stamp = jiffies;
6588
6589         /*
6590          * Force memory writes to complete before letting h/w
6591          * know there are new descriptors to fetch.  (Only
6592          * applicable for weak-ordered memory model archs,
6593          * such as IA-64).
6594          */
6595         wmb();
6596
6597         /* set next_to_watch value indicating a packet is present */
6598         first->next_to_watch = tx_desc;
6599
6600         /* notify HW of packet */
6601         writel(i, tx_ring->tail);
6602
6603         return;
6604 dma_error:
6605         dev_err(dev, "TX DMA map failed\n");
6606
6607         /* clear dma mappings for failed tx_buffer_info map */
6608         for (;;) {
6609                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6610                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6611                 if (tx_buffer_info == first)
6612                         break;
6613                 if (i == 0)
6614                         i = tx_ring->count;
6615                 i--;
6616         }
6617
6618         dev_kfree_skb_any(skb);
6619
6620         tx_ring->next_to_use = i;
6621 }
6622
6623 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6624                       u32 tx_flags, __be16 protocol)
6625 {
6626         struct ixgbe_q_vector *q_vector = ring->q_vector;
6627         union ixgbe_atr_hash_dword input = { .dword = 0 };
6628         union ixgbe_atr_hash_dword common = { .dword = 0 };
6629         union {
6630                 unsigned char *network;
6631                 struct iphdr *ipv4;
6632                 struct ipv6hdr *ipv6;
6633         } hdr;
6634         struct tcphdr *th;
6635         __be16 vlan_id;
6636
6637         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6638         if (!q_vector)
6639                 return;
6640
6641         /* do nothing if sampling is disabled */
6642         if (!ring->atr_sample_rate)
6643                 return;
6644
6645         ring->atr_count++;
6646
6647         /* snag network header to get L4 type and address */
6648         hdr.network = skb_network_header(skb);
6649
6650         /* Currently only IPv4/IPv6 with TCP is supported */
6651         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6652              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6653             (protocol != __constant_htons(ETH_P_IP) ||
6654              hdr.ipv4->protocol != IPPROTO_TCP))
6655                 return;
6656
6657         th = tcp_hdr(skb);
6658
6659         /* skip this packet since it is invalid or the socket is closing */
6660         if (!th || th->fin)
6661                 return;
6662
6663         /* sample on all syn packets or once every atr sample count */
6664         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6665                 return;
6666
6667         /* reset sample count */
6668         ring->atr_count = 0;
6669
6670         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6671
6672         /*
6673          * src and dst are inverted, think how the receiver sees them
6674          *
6675          * The input is broken into two sections, a non-compressed section
6676          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6677          * is XORed together and stored in the compressed dword.
6678          */
6679         input.formatted.vlan_id = vlan_id;
6680
6681         /*
6682          * since src port and flex bytes occupy the same word XOR them together
6683          * and write the value to source port portion of compressed dword
6684          */
6685         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6686                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6687         else
6688                 common.port.src ^= th->dest ^ protocol;
6689         common.port.dst ^= th->source;
6690
6691         if (protocol == __constant_htons(ETH_P_IP)) {
6692                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6693                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6694         } else {
6695                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6696                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6697                              hdr.ipv6->saddr.s6_addr32[1] ^
6698                              hdr.ipv6->saddr.s6_addr32[2] ^
6699                              hdr.ipv6->saddr.s6_addr32[3] ^
6700                              hdr.ipv6->daddr.s6_addr32[0] ^
6701                              hdr.ipv6->daddr.s6_addr32[1] ^
6702                              hdr.ipv6->daddr.s6_addr32[2] ^
6703                              hdr.ipv6->daddr.s6_addr32[3];
6704         }
6705
6706         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6707         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6708                                               input, common, ring->queue_index);
6709 }
6710
6711 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6712 {
6713         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6714         /* Herbert's original patch had:
6715          *  smp_mb__after_netif_stop_queue();
6716          * but since that doesn't exist yet, just open code it. */
6717         smp_mb();
6718
6719         /* We need to check again in a case another CPU has just
6720          * made room available. */
6721         if (likely(ixgbe_desc_unused(tx_ring) < size))
6722                 return -EBUSY;
6723
6724         /* A reprieve! - use start_queue because it doesn't call schedule */
6725         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6726         ++tx_ring->tx_stats.restart_queue;
6727         return 0;
6728 }
6729
6730 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6731 {
6732         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6733                 return 0;
6734         return __ixgbe_maybe_stop_tx(tx_ring, size);
6735 }
6736
6737 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6738 {
6739         struct ixgbe_adapter *adapter = netdev_priv(dev);
6740         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6741                                                smp_processor_id();
6742 #ifdef IXGBE_FCOE
6743         __be16 protocol = vlan_get_protocol(skb);
6744
6745         if (((protocol == htons(ETH_P_FCOE)) ||
6746             (protocol == htons(ETH_P_FIP))) &&
6747             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6748                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6749                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6750                 return txq;
6751         }
6752 #endif
6753
6754         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6755                 while (unlikely(txq >= dev->real_num_tx_queues))
6756                         txq -= dev->real_num_tx_queues;
6757                 return txq;
6758         }
6759
6760         return skb_tx_hash(dev, skb);
6761 }
6762
6763 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6764                           struct ixgbe_adapter *adapter,
6765                           struct ixgbe_ring *tx_ring)
6766 {
6767         struct ixgbe_tx_buffer *first;
6768         int tso;
6769         u32 tx_flags = 0;
6770 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6771         unsigned short f;
6772 #endif
6773         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6774         __be16 protocol = skb->protocol;
6775         u8 hdr_len = 0;
6776
6777         /*
6778          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6779          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6780          *       + 2 desc gap to keep tail from touching head,
6781          *       + 1 desc for context descriptor,
6782          * otherwise try next time
6783          */
6784 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6785         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6786                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6787 #else
6788         count += skb_shinfo(skb)->nr_frags;
6789 #endif
6790         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6791                 tx_ring->tx_stats.tx_busy++;
6792                 return NETDEV_TX_BUSY;
6793         }
6794
6795 #ifdef CONFIG_PCI_IOV
6796         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6797                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6798
6799 #endif
6800         /* if we have a HW VLAN tag being added default to the HW one */
6801         if (vlan_tx_tag_present(skb)) {
6802                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6803                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6804         /* else if it is a SW VLAN check the next protocol and store the tag */
6805         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6806                 struct vlan_hdr *vhdr, _vhdr;
6807                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6808                 if (!vhdr)
6809                         goto out_drop;
6810
6811                 protocol = vhdr->h_vlan_encapsulated_proto;
6812                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6813                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6814         }
6815
6816         /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6817         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6818             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6819              (skb->priority != TC_PRIO_CONTROL))) {
6820                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6821                 tx_flags |= (skb->priority & 0x7) <<
6822                                         IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6823                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6824                         struct vlan_ethhdr *vhdr;
6825                         if (skb_header_cloned(skb) &&
6826                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6827                                 goto out_drop;
6828                         vhdr = (struct vlan_ethhdr *)skb->data;
6829                         vhdr->h_vlan_TCI = htons(tx_flags >>
6830                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6831                 } else {
6832                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6833                 }
6834         }
6835
6836         /* record the location of the first descriptor for this packet */
6837         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6838
6839 #ifdef IXGBE_FCOE
6840         /* setup tx offload for FCoE */
6841         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6842             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6843                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6844                 if (tso < 0)
6845                         goto out_drop;
6846                 else if (tso)
6847                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6848                                     IXGBE_TX_FLAGS_FCOE;
6849                 else
6850                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6851
6852                 goto xmit_fcoe;
6853         }
6854
6855 #endif /* IXGBE_FCOE */
6856         /* setup IPv4/IPv6 offloads */
6857         if (protocol == __constant_htons(ETH_P_IP))
6858                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6859
6860         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6861         if (tso < 0)
6862                 goto out_drop;
6863         else if (tso)
6864                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6865         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6866                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6867
6868         /* add the ATR filter if ATR is on */
6869         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6870                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6871
6872 #ifdef IXGBE_FCOE
6873 xmit_fcoe:
6874 #endif /* IXGBE_FCOE */
6875         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6876
6877         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6878
6879         return NETDEV_TX_OK;
6880
6881 out_drop:
6882         dev_kfree_skb_any(skb);
6883         return NETDEV_TX_OK;
6884 }
6885
6886 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6887 {
6888         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6889         struct ixgbe_ring *tx_ring;
6890
6891         tx_ring = adapter->tx_ring[skb->queue_mapping];
6892         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6893 }
6894
6895 /**
6896  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6897  * @netdev: network interface device structure
6898  * @p: pointer to an address structure
6899  *
6900  * Returns 0 on success, negative on failure
6901  **/
6902 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6903 {
6904         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6905         struct ixgbe_hw *hw = &adapter->hw;
6906         struct sockaddr *addr = p;
6907
6908         if (!is_valid_ether_addr(addr->sa_data))
6909                 return -EADDRNOTAVAIL;
6910
6911         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6912         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6913
6914         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6915                             IXGBE_RAH_AV);
6916
6917         return 0;
6918 }
6919
6920 static int
6921 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6922 {
6923         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6924         struct ixgbe_hw *hw = &adapter->hw;
6925         u16 value;
6926         int rc;
6927
6928         if (prtad != hw->phy.mdio.prtad)
6929                 return -EINVAL;
6930         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6931         if (!rc)
6932                 rc = value;
6933         return rc;
6934 }
6935
6936 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6937                             u16 addr, u16 value)
6938 {
6939         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6940         struct ixgbe_hw *hw = &adapter->hw;
6941
6942         if (prtad != hw->phy.mdio.prtad)
6943                 return -EINVAL;
6944         return hw->phy.ops.write_reg(hw, addr, devad, value);
6945 }
6946
6947 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6948 {
6949         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6950
6951         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6952 }
6953
6954 /**
6955  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6956  * netdev->dev_addrs
6957  * @netdev: network interface device structure
6958  *
6959  * Returns non-zero on failure
6960  **/
6961 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6962 {
6963         int err = 0;
6964         struct ixgbe_adapter *adapter = netdev_priv(dev);
6965         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6966
6967         if (is_valid_ether_addr(mac->san_addr)) {
6968                 rtnl_lock();
6969                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6970                 rtnl_unlock();
6971         }
6972         return err;
6973 }
6974
6975 /**
6976  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6977  * netdev->dev_addrs
6978  * @netdev: network interface device structure
6979  *
6980  * Returns non-zero on failure
6981  **/
6982 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6983 {
6984         int err = 0;
6985         struct ixgbe_adapter *adapter = netdev_priv(dev);
6986         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6987
6988         if (is_valid_ether_addr(mac->san_addr)) {
6989                 rtnl_lock();
6990                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6991                 rtnl_unlock();
6992         }
6993         return err;
6994 }
6995
6996 #ifdef CONFIG_NET_POLL_CONTROLLER
6997 /*
6998  * Polling 'interrupt' - used by things like netconsole to send skbs
6999  * without having to re-enable interrupts. It's not called while
7000  * the interrupt routine is executing.
7001  */
7002 static void ixgbe_netpoll(struct net_device *netdev)
7003 {
7004         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7005         int i;
7006
7007         /* if interface is down do nothing */
7008         if (test_bit(__IXGBE_DOWN, &adapter->state))
7009                 return;
7010
7011         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7012         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7013                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7014                 for (i = 0; i < num_q_vectors; i++) {
7015                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7016                         ixgbe_msix_clean_rings(0, q_vector);
7017                 }
7018         } else {
7019                 ixgbe_intr(adapter->pdev->irq, netdev);
7020         }
7021         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7022 }
7023 #endif
7024
7025 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7026                                                    struct rtnl_link_stats64 *stats)
7027 {
7028         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7029         int i;
7030
7031         rcu_read_lock();
7032         for (i = 0; i < adapter->num_rx_queues; i++) {
7033                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7034                 u64 bytes, packets;
7035                 unsigned int start;
7036
7037                 if (ring) {
7038                         do {
7039                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7040                                 packets = ring->stats.packets;
7041                                 bytes   = ring->stats.bytes;
7042                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7043                         stats->rx_packets += packets;
7044                         stats->rx_bytes   += bytes;
7045                 }
7046         }
7047
7048         for (i = 0; i < adapter->num_tx_queues; i++) {
7049                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7050                 u64 bytes, packets;
7051                 unsigned int start;
7052
7053                 if (ring) {
7054                         do {
7055                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7056                                 packets = ring->stats.packets;
7057                                 bytes   = ring->stats.bytes;
7058                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7059                         stats->tx_packets += packets;
7060                         stats->tx_bytes   += bytes;
7061                 }
7062         }
7063         rcu_read_unlock();
7064         /* following stats updated by ixgbe_watchdog_task() */
7065         stats->multicast        = netdev->stats.multicast;
7066         stats->rx_errors        = netdev->stats.rx_errors;
7067         stats->rx_length_errors = netdev->stats.rx_length_errors;
7068         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7069         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7070         return stats;
7071 }
7072
7073 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7074  * #adapter: pointer to ixgbe_adapter
7075  * @tc: number of traffic classes currently enabled
7076  *
7077  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7078  * 802.1Q priority maps to a packet buffer that exists.
7079  */
7080 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7081 {
7082         struct ixgbe_hw *hw = &adapter->hw;
7083         u32 reg, rsave;
7084         int i;
7085
7086         /* 82598 have a static priority to TC mapping that can not
7087          * be changed so no validation is needed.
7088          */
7089         if (hw->mac.type == ixgbe_mac_82598EB)
7090                 return;
7091
7092         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7093         rsave = reg;
7094
7095         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7096                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7097
7098                 /* If up2tc is out of bounds default to zero */
7099                 if (up2tc > tc)
7100                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7101         }
7102
7103         if (reg != rsave)
7104                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7105
7106         return;
7107 }
7108
7109
7110 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7111  * classes.
7112  *
7113  * @netdev: net device to configure
7114  * @tc: number of traffic classes to enable
7115  */
7116 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7117 {
7118         struct ixgbe_adapter *adapter = netdev_priv(dev);
7119         struct ixgbe_hw *hw = &adapter->hw;
7120
7121         /* Multiple traffic classes requires multiple queues */
7122         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7123                 e_err(drv, "Enable failed, needs MSI-X\n");
7124                 return -EINVAL;
7125         }
7126
7127         /* Hardware supports up to 8 traffic classes */
7128         if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7129             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7130                 return -EINVAL;
7131
7132         /* Hardware has to reinitialize queues and interrupts to
7133          * match packet buffer alignment. Unfortunantly, the
7134          * hardware is not flexible enough to do this dynamically.
7135          */
7136         if (netif_running(dev))
7137                 ixgbe_close(dev);
7138         ixgbe_clear_interrupt_scheme(adapter);
7139
7140         if (tc) {
7141                 netdev_set_num_tc(dev, tc);
7142                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7143
7144                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7145                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7146
7147                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7148                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
7149         } else {
7150                 netdev_reset_tc(dev);
7151
7152                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7153
7154                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7155                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7156
7157                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7158                 adapter->dcb_cfg.pfc_mode_enable = false;
7159         }
7160
7161         ixgbe_init_interrupt_scheme(adapter);
7162         ixgbe_validate_rtr(adapter, tc);
7163         if (netif_running(dev))
7164                 ixgbe_open(dev);
7165
7166         return 0;
7167 }
7168
7169 void ixgbe_do_reset(struct net_device *netdev)
7170 {
7171         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7172
7173         if (netif_running(netdev))
7174                 ixgbe_reinit_locked(adapter);
7175         else
7176                 ixgbe_reset(adapter);
7177 }
7178
7179 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7180 {
7181         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7182
7183 #ifdef CONFIG_DCB
7184         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7185                 data &= ~NETIF_F_HW_VLAN_RX;
7186 #endif
7187
7188         /* return error if RXHASH is being enabled when RSS is not supported */
7189         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7190                 data &= ~NETIF_F_RXHASH;
7191
7192         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7193         if (!(data & NETIF_F_RXCSUM))
7194                 data &= ~NETIF_F_LRO;
7195
7196         /* Turn off LRO if not RSC capable or invalid ITR settings */
7197         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7198                 data &= ~NETIF_F_LRO;
7199         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7200                    (adapter->rx_itr_setting != 1 &&
7201                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7202                 data &= ~NETIF_F_LRO;
7203                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7204         }
7205
7206         return data;
7207 }
7208
7209 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7210 {
7211         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7212         bool need_reset = false;
7213
7214         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7215         if (!(data & NETIF_F_RXCSUM))
7216                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7217         else
7218                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7219
7220         /* Make sure RSC matches LRO, reset if change */
7221         if (!!(data & NETIF_F_LRO) !=
7222              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7223                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7224                 switch (adapter->hw.mac.type) {
7225                 case ixgbe_mac_X540:
7226                 case ixgbe_mac_82599EB:
7227                         need_reset = true;
7228                         break;
7229                 default:
7230                         break;
7231                 }
7232         }
7233
7234         /*
7235          * Check if Flow Director n-tuple support was enabled or disabled.  If
7236          * the state changed, we need to reset.
7237          */
7238         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7239                 /* turn off ATR, enable perfect filters and reset */
7240                 if (data & NETIF_F_NTUPLE) {
7241                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7242                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7243                         need_reset = true;
7244                 }
7245         } else if (!(data & NETIF_F_NTUPLE)) {
7246                 /* turn off Flow Director, set ATR and reset */
7247                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7248                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7249                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7250                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7251                 need_reset = true;
7252         }
7253
7254         if (need_reset)
7255                 ixgbe_do_reset(netdev);
7256
7257         return 0;
7258
7259 }
7260
7261 static const struct net_device_ops ixgbe_netdev_ops = {
7262         .ndo_open               = ixgbe_open,
7263         .ndo_stop               = ixgbe_close,
7264         .ndo_start_xmit         = ixgbe_xmit_frame,
7265         .ndo_select_queue       = ixgbe_select_queue,
7266         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7267         .ndo_validate_addr      = eth_validate_addr,
7268         .ndo_set_mac_address    = ixgbe_set_mac,
7269         .ndo_change_mtu         = ixgbe_change_mtu,
7270         .ndo_tx_timeout         = ixgbe_tx_timeout,
7271         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7272         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7273         .ndo_do_ioctl           = ixgbe_ioctl,
7274         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7275         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7276         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7277         .ndo_set_vf_spoofchk    = ixgbe_ndo_set_vf_spoofchk,
7278         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7279         .ndo_get_stats64        = ixgbe_get_stats64,
7280         .ndo_setup_tc           = ixgbe_setup_tc,
7281 #ifdef CONFIG_NET_POLL_CONTROLLER
7282         .ndo_poll_controller    = ixgbe_netpoll,
7283 #endif
7284 #ifdef IXGBE_FCOE
7285         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7286         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7287         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7288         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7289         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7290         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7291 #endif /* IXGBE_FCOE */
7292         .ndo_set_features = ixgbe_set_features,
7293         .ndo_fix_features = ixgbe_fix_features,
7294 };
7295
7296 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7297                            const struct ixgbe_info *ii)
7298 {
7299 #ifdef CONFIG_PCI_IOV
7300         struct ixgbe_hw *hw = &adapter->hw;
7301
7302         if (hw->mac.type == ixgbe_mac_82598EB)
7303                 return;
7304
7305         /* The 82599 supports up to 64 VFs per physical function
7306          * but this implementation limits allocation to 63 so that
7307          * basic networking resources are still available to the
7308          * physical function
7309          */
7310         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7311         ixgbe_enable_sriov(adapter, ii);
7312 #endif /* CONFIG_PCI_IOV */
7313 }
7314
7315 /**
7316  * ixgbe_probe - Device Initialization Routine
7317  * @pdev: PCI device information struct
7318  * @ent: entry in ixgbe_pci_tbl
7319  *
7320  * Returns 0 on success, negative on failure
7321  *
7322  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7323  * The OS initialization, configuring of the adapter private structure,
7324  * and a hardware reset occur.
7325  **/
7326 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7327                                  const struct pci_device_id *ent)
7328 {
7329         struct net_device *netdev;
7330         struct ixgbe_adapter *adapter = NULL;
7331         struct ixgbe_hw *hw;
7332         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7333         static int cards_found;
7334         int i, err, pci_using_dac;
7335         u8 part_str[IXGBE_PBANUM_LENGTH];
7336         unsigned int indices = num_possible_cpus();
7337 #ifdef IXGBE_FCOE
7338         u16 device_caps;
7339 #endif
7340         u32 eec;
7341         u16 wol_cap;
7342
7343         /* Catch broken hardware that put the wrong VF device ID in
7344          * the PCIe SR-IOV capability.
7345          */
7346         if (pdev->is_virtfn) {
7347                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7348                      pci_name(pdev), pdev->vendor, pdev->device);
7349                 return -EINVAL;
7350         }
7351
7352         err = pci_enable_device_mem(pdev);
7353         if (err)
7354                 return err;
7355
7356         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7357             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7358                 pci_using_dac = 1;
7359         } else {
7360                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7361                 if (err) {
7362                         err = dma_set_coherent_mask(&pdev->dev,
7363                                                     DMA_BIT_MASK(32));
7364                         if (err) {
7365                                 dev_err(&pdev->dev,
7366                                         "No usable DMA configuration, aborting\n");
7367                                 goto err_dma;
7368                         }
7369                 }
7370                 pci_using_dac = 0;
7371         }
7372
7373         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7374                                            IORESOURCE_MEM), ixgbe_driver_name);
7375         if (err) {
7376                 dev_err(&pdev->dev,
7377                         "pci_request_selected_regions failed 0x%x\n", err);
7378                 goto err_pci_reg;
7379         }
7380
7381         pci_enable_pcie_error_reporting(pdev);
7382
7383         pci_set_master(pdev);
7384         pci_save_state(pdev);
7385
7386 #ifdef CONFIG_IXGBE_DCB
7387         indices *= MAX_TRAFFIC_CLASS;
7388 #endif
7389
7390         if (ii->mac == ixgbe_mac_82598EB)
7391                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7392         else
7393                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7394
7395 #ifdef IXGBE_FCOE
7396         indices += min_t(unsigned int, num_possible_cpus(),
7397                          IXGBE_MAX_FCOE_INDICES);
7398 #endif
7399         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7400         if (!netdev) {
7401                 err = -ENOMEM;
7402                 goto err_alloc_etherdev;
7403         }
7404
7405         SET_NETDEV_DEV(netdev, &pdev->dev);
7406
7407         adapter = netdev_priv(netdev);
7408         pci_set_drvdata(pdev, adapter);
7409
7410         adapter->netdev = netdev;
7411         adapter->pdev = pdev;
7412         hw = &adapter->hw;
7413         hw->back = adapter;
7414         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7415
7416         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7417                               pci_resource_len(pdev, 0));
7418         if (!hw->hw_addr) {
7419                 err = -EIO;
7420                 goto err_ioremap;
7421         }
7422
7423         for (i = 1; i <= 5; i++) {
7424                 if (pci_resource_len(pdev, i) == 0)
7425                         continue;
7426         }
7427
7428         netdev->netdev_ops = &ixgbe_netdev_ops;
7429         ixgbe_set_ethtool_ops(netdev);
7430         netdev->watchdog_timeo = 5 * HZ;
7431         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7432
7433         adapter->bd_number = cards_found;
7434
7435         /* Setup hw api */
7436         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7437         hw->mac.type  = ii->mac;
7438
7439         /* EEPROM */
7440         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7441         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7442         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7443         if (!(eec & (1 << 8)))
7444                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7445
7446         /* PHY */
7447         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7448         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7449         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7450         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7451         hw->phy.mdio.mmds = 0;
7452         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7453         hw->phy.mdio.dev = netdev;
7454         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7455         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7456
7457         ii->get_invariants(hw);
7458
7459         /* setup the private structure */
7460         err = ixgbe_sw_init(adapter);
7461         if (err)
7462                 goto err_sw_init;
7463
7464         /* Make it possible the adapter to be woken up via WOL */
7465         switch (adapter->hw.mac.type) {
7466         case ixgbe_mac_82599EB:
7467         case ixgbe_mac_X540:
7468                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7469                 break;
7470         default:
7471                 break;
7472         }
7473
7474         /*
7475          * If there is a fan on this device and it has failed log the
7476          * failure.
7477          */
7478         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7479                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7480                 if (esdp & IXGBE_ESDP_SDP1)
7481                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7482         }
7483
7484         /* reset_hw fills in the perm_addr as well */
7485         hw->phy.reset_if_overtemp = true;
7486         err = hw->mac.ops.reset_hw(hw);
7487         hw->phy.reset_if_overtemp = false;
7488         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7489             hw->mac.type == ixgbe_mac_82598EB) {
7490                 err = 0;
7491         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7492                 e_dev_err("failed to load because an unsupported SFP+ "
7493                           "module type was detected.\n");
7494                 e_dev_err("Reload the driver after installing a supported "
7495                           "module.\n");
7496                 goto err_sw_init;
7497         } else if (err) {
7498                 e_dev_err("HW Init failed: %d\n", err);
7499                 goto err_sw_init;
7500         }
7501
7502         ixgbe_probe_vf(adapter, ii);
7503
7504         netdev->features = NETIF_F_SG |
7505                            NETIF_F_IP_CSUM |
7506                            NETIF_F_IPV6_CSUM |
7507                            NETIF_F_HW_VLAN_TX |
7508                            NETIF_F_HW_VLAN_RX |
7509                            NETIF_F_HW_VLAN_FILTER |
7510                            NETIF_F_TSO |
7511                            NETIF_F_TSO6 |
7512                            NETIF_F_RXHASH |
7513                            NETIF_F_RXCSUM;
7514
7515         netdev->hw_features = netdev->features;
7516
7517         switch (adapter->hw.mac.type) {
7518         case ixgbe_mac_82599EB:
7519         case ixgbe_mac_X540:
7520                 netdev->features |= NETIF_F_SCTP_CSUM;
7521                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7522                                        NETIF_F_NTUPLE;
7523                 break;
7524         default:
7525                 break;
7526         }
7527
7528         netdev->vlan_features |= NETIF_F_TSO;
7529         netdev->vlan_features |= NETIF_F_TSO6;
7530         netdev->vlan_features |= NETIF_F_IP_CSUM;
7531         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7532         netdev->vlan_features |= NETIF_F_SG;
7533
7534         netdev->priv_flags |= IFF_UNICAST_FLT;
7535
7536         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7537                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7538                                     IXGBE_FLAG_DCB_ENABLED);
7539
7540 #ifdef CONFIG_IXGBE_DCB
7541         netdev->dcbnl_ops = &dcbnl_ops;
7542 #endif
7543
7544 #ifdef IXGBE_FCOE
7545         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7546                 if (hw->mac.ops.get_device_caps) {
7547                         hw->mac.ops.get_device_caps(hw, &device_caps);
7548                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7549                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7550                 }
7551         }
7552         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7553                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7554                 netdev->vlan_features |= NETIF_F_FSO;
7555                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7556         }
7557 #endif /* IXGBE_FCOE */
7558         if (pci_using_dac) {
7559                 netdev->features |= NETIF_F_HIGHDMA;
7560                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7561         }
7562
7563         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7564                 netdev->hw_features |= NETIF_F_LRO;
7565         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7566                 netdev->features |= NETIF_F_LRO;
7567
7568         /* make sure the EEPROM is good */
7569         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7570                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7571                 err = -EIO;
7572                 goto err_eeprom;
7573         }
7574
7575         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7576         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7577
7578         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7579                 e_dev_err("invalid MAC address\n");
7580                 err = -EIO;
7581                 goto err_eeprom;
7582         }
7583
7584         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7585                     (unsigned long) adapter);
7586
7587         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7588         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7589
7590         err = ixgbe_init_interrupt_scheme(adapter);
7591         if (err)
7592                 goto err_sw_init;
7593
7594         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7595                 netdev->hw_features &= ~NETIF_F_RXHASH;
7596                 netdev->features &= ~NETIF_F_RXHASH;
7597         }
7598
7599         /* WOL not supported for all but the following */
7600         adapter->wol = 0;
7601         switch (pdev->device) {
7602         case IXGBE_DEV_ID_82599_SFP:
7603                 /* Only this subdevice supports WOL */
7604                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7605                         adapter->wol = IXGBE_WUFC_MAG;
7606                 break;
7607         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7608                 /* All except this subdevice support WOL */
7609                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7610                         adapter->wol = IXGBE_WUFC_MAG;
7611                 break;
7612         case IXGBE_DEV_ID_82599_KX4:
7613                 adapter->wol = IXGBE_WUFC_MAG;
7614                 break;
7615         case IXGBE_DEV_ID_X540T:
7616         case IXGBE_DEV_ID_X540T1:
7617                 /* Check eeprom to see if it is enabled */
7618                 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7619                 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7620
7621                 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7622                     ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7623                      (hw->bus.func == 0)))
7624                         adapter->wol = IXGBE_WUFC_MAG;
7625                 break;
7626         }
7627         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7628
7629         /* save off EEPROM version number */
7630         hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7631         hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7632
7633         /* pick up the PCI bus settings for reporting later */
7634         hw->mac.ops.get_bus_info(hw);
7635
7636         /* print bus type/speed/width info */
7637         e_dev_info("(PCI Express:%s:%s) %pM\n",
7638                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7639                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7640                     "Unknown"),
7641                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7642                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7643                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7644                     "Unknown"),
7645                    netdev->dev_addr);
7646
7647         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7648         if (err)
7649                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7650         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7651                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7652                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7653                            part_str);
7654         else
7655                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7656                            hw->mac.type, hw->phy.type, part_str);
7657
7658         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7659                 e_dev_warn("PCI-Express bandwidth available for this card is "
7660                            "not sufficient for optimal performance.\n");
7661                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7662                            "is required.\n");
7663         }
7664
7665         /* reset the hardware with the new settings */
7666         err = hw->mac.ops.start_hw(hw);
7667
7668         if (err == IXGBE_ERR_EEPROM_VERSION) {
7669                 /* We are running on a pre-production device, log a warning */
7670                 e_dev_warn("This device is a pre-production adapter/LOM. "
7671                            "Please be aware there may be issues associated "
7672                            "with your hardware.  If you are experiencing "
7673                            "problems please contact your Intel or hardware "
7674                            "representative who provided you with this "
7675                            "hardware.\n");
7676         }
7677         strcpy(netdev->name, "eth%d");
7678         err = register_netdev(netdev);
7679         if (err)
7680                 goto err_register;
7681
7682         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7683         if (hw->mac.ops.disable_tx_laser &&
7684             ((hw->phy.multispeed_fiber) ||
7685              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7686               (hw->mac.type == ixgbe_mac_82599EB))))
7687                 hw->mac.ops.disable_tx_laser(hw);
7688
7689         /* carrier off reporting is important to ethtool even BEFORE open */
7690         netif_carrier_off(netdev);
7691
7692 #ifdef CONFIG_IXGBE_DCA
7693         if (dca_add_requester(&pdev->dev) == 0) {
7694                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7695                 ixgbe_setup_dca(adapter);
7696         }
7697 #endif
7698         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7699                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7700                 for (i = 0; i < adapter->num_vfs; i++)
7701                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7702         }
7703
7704         /* firmware requires driver version to be 0xFFFFFFFF
7705          * since os does not support feature
7706          */
7707         if (hw->mac.ops.set_fw_drv_ver)
7708                 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7709                                            0xFF);
7710
7711         /* add san mac addr to netdev */
7712         ixgbe_add_sanmac_netdev(netdev);
7713
7714         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7715         cards_found++;
7716         return 0;
7717
7718 err_register:
7719         ixgbe_release_hw_control(adapter);
7720         ixgbe_clear_interrupt_scheme(adapter);
7721 err_sw_init:
7722 err_eeprom:
7723         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7724                 ixgbe_disable_sriov(adapter);
7725         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7726         iounmap(hw->hw_addr);
7727 err_ioremap:
7728         free_netdev(netdev);
7729 err_alloc_etherdev:
7730         pci_release_selected_regions(pdev,
7731                                      pci_select_bars(pdev, IORESOURCE_MEM));
7732 err_pci_reg:
7733 err_dma:
7734         pci_disable_device(pdev);
7735         return err;
7736 }
7737
7738 /**
7739  * ixgbe_remove - Device Removal Routine
7740  * @pdev: PCI device information struct
7741  *
7742  * ixgbe_remove is called by the PCI subsystem to alert the driver
7743  * that it should release a PCI device.  The could be caused by a
7744  * Hot-Plug event, or because the driver is going to be removed from
7745  * memory.
7746  **/
7747 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7748 {
7749         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7750         struct net_device *netdev = adapter->netdev;
7751
7752         set_bit(__IXGBE_DOWN, &adapter->state);
7753         cancel_work_sync(&adapter->service_task);
7754
7755 #ifdef CONFIG_IXGBE_DCA
7756         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7757                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7758                 dca_remove_requester(&pdev->dev);
7759                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7760         }
7761
7762 #endif
7763 #ifdef IXGBE_FCOE
7764         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7765                 ixgbe_cleanup_fcoe(adapter);
7766
7767 #endif /* IXGBE_FCOE */
7768
7769         /* remove the added san mac */
7770         ixgbe_del_sanmac_netdev(netdev);
7771
7772         if (netdev->reg_state == NETREG_REGISTERED)
7773                 unregister_netdev(netdev);
7774
7775         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7776                 if (!(ixgbe_check_vf_assignment(adapter)))
7777                         ixgbe_disable_sriov(adapter);
7778                 else
7779                         e_dev_warn("Unloading driver while VFs are assigned "
7780                                    "- VFs will not be deallocated\n");
7781         }
7782
7783         ixgbe_clear_interrupt_scheme(adapter);
7784
7785         ixgbe_release_hw_control(adapter);
7786
7787         iounmap(adapter->hw.hw_addr);
7788         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7789                                      IORESOURCE_MEM));
7790
7791         e_dev_info("complete\n");
7792
7793         free_netdev(netdev);
7794
7795         pci_disable_pcie_error_reporting(pdev);
7796
7797         pci_disable_device(pdev);
7798 }
7799
7800 /**
7801  * ixgbe_io_error_detected - called when PCI error is detected
7802  * @pdev: Pointer to PCI device
7803  * @state: The current pci connection state
7804  *
7805  * This function is called after a PCI bus error affecting
7806  * this device has been detected.
7807  */
7808 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7809                                                 pci_channel_state_t state)
7810 {
7811         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7812         struct net_device *netdev = adapter->netdev;
7813
7814 #ifdef CONFIG_PCI_IOV
7815         struct pci_dev *bdev, *vfdev;
7816         u32 dw0, dw1, dw2, dw3;
7817         int vf, pos;
7818         u16 req_id, pf_func;
7819
7820         if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7821             adapter->num_vfs == 0)
7822                 goto skip_bad_vf_detection;
7823
7824         bdev = pdev->bus->self;
7825         while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7826                 bdev = bdev->bus->self;
7827
7828         if (!bdev)
7829                 goto skip_bad_vf_detection;
7830
7831         pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7832         if (!pos)
7833                 goto skip_bad_vf_detection;
7834
7835         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7836         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7837         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7838         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7839
7840         req_id = dw1 >> 16;
7841         /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7842         if (!(req_id & 0x0080))
7843                 goto skip_bad_vf_detection;
7844
7845         pf_func = req_id & 0x01;
7846         if ((pf_func & 1) == (pdev->devfn & 1)) {
7847                 unsigned int device_id;
7848
7849                 vf = (req_id & 0x7F) >> 1;
7850                 e_dev_err("VF %d has caused a PCIe error\n", vf);
7851                 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7852                                 "%8.8x\tdw3: %8.8x\n",
7853                 dw0, dw1, dw2, dw3);
7854                 switch (adapter->hw.mac.type) {
7855                 case ixgbe_mac_82599EB:
7856                         device_id = IXGBE_82599_VF_DEVICE_ID;
7857                         break;
7858                 case ixgbe_mac_X540:
7859                         device_id = IXGBE_X540_VF_DEVICE_ID;
7860                         break;
7861                 default:
7862                         device_id = 0;
7863                         break;
7864                 }
7865
7866                 /* Find the pci device of the offending VF */
7867                 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7868                 while (vfdev) {
7869                         if (vfdev->devfn == (req_id & 0xFF))
7870                                 break;
7871                         vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7872                                                device_id, vfdev);
7873                 }
7874                 /*
7875                  * There's a slim chance the VF could have been hot plugged,
7876                  * so if it is no longer present we don't need to issue the
7877                  * VFLR.  Just clean up the AER in that case.
7878                  */
7879                 if (vfdev) {
7880                         e_dev_err("Issuing VFLR to VF %d\n", vf);
7881                         pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7882                 }
7883
7884                 pci_cleanup_aer_uncorrect_error_status(pdev);
7885         }
7886
7887         /*
7888          * Even though the error may have occurred on the other port
7889          * we still need to increment the vf error reference count for
7890          * both ports because the I/O resume function will be called
7891          * for both of them.
7892          */
7893         adapter->vferr_refcount++;
7894
7895         return PCI_ERS_RESULT_RECOVERED;
7896
7897 skip_bad_vf_detection:
7898 #endif /* CONFIG_PCI_IOV */
7899         netif_device_detach(netdev);
7900
7901         if (state == pci_channel_io_perm_failure)
7902                 return PCI_ERS_RESULT_DISCONNECT;
7903
7904         if (netif_running(netdev))
7905                 ixgbe_down(adapter);
7906         pci_disable_device(pdev);
7907
7908         /* Request a slot reset. */
7909         return PCI_ERS_RESULT_NEED_RESET;
7910 }
7911
7912 /**
7913  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7914  * @pdev: Pointer to PCI device
7915  *
7916  * Restart the card from scratch, as if from a cold-boot.
7917  */
7918 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7919 {
7920         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7921         pci_ers_result_t result;
7922         int err;
7923
7924         if (pci_enable_device_mem(pdev)) {
7925                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7926                 result = PCI_ERS_RESULT_DISCONNECT;
7927         } else {
7928                 pci_set_master(pdev);
7929                 pci_restore_state(pdev);
7930                 pci_save_state(pdev);
7931
7932                 pci_wake_from_d3(pdev, false);
7933
7934                 ixgbe_reset(adapter);
7935                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7936                 result = PCI_ERS_RESULT_RECOVERED;
7937         }
7938
7939         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7940         if (err) {
7941                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7942                           "failed 0x%0x\n", err);
7943                 /* non-fatal, continue */
7944         }
7945
7946         return result;
7947 }
7948
7949 /**
7950  * ixgbe_io_resume - called when traffic can start flowing again.
7951  * @pdev: Pointer to PCI device
7952  *
7953  * This callback is called when the error recovery driver tells us that
7954  * its OK to resume normal operation.
7955  */
7956 static void ixgbe_io_resume(struct pci_dev *pdev)
7957 {
7958         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7959         struct net_device *netdev = adapter->netdev;
7960
7961 #ifdef CONFIG_PCI_IOV
7962         if (adapter->vferr_refcount) {
7963                 e_info(drv, "Resuming after VF err\n");
7964                 adapter->vferr_refcount--;
7965                 return;
7966         }
7967
7968 #endif
7969         if (netif_running(netdev))
7970                 ixgbe_up(adapter);
7971
7972         netif_device_attach(netdev);
7973 }
7974
7975 static struct pci_error_handlers ixgbe_err_handler = {
7976         .error_detected = ixgbe_io_error_detected,
7977         .slot_reset = ixgbe_io_slot_reset,
7978         .resume = ixgbe_io_resume,
7979 };
7980
7981 static struct pci_driver ixgbe_driver = {
7982         .name     = ixgbe_driver_name,
7983         .id_table = ixgbe_pci_tbl,
7984         .probe    = ixgbe_probe,
7985         .remove   = __devexit_p(ixgbe_remove),
7986 #ifdef CONFIG_PM
7987         .suspend  = ixgbe_suspend,
7988         .resume   = ixgbe_resume,
7989 #endif
7990         .shutdown = ixgbe_shutdown,
7991         .err_handler = &ixgbe_err_handler
7992 };
7993
7994 /**
7995  * ixgbe_init_module - Driver Registration Routine
7996  *
7997  * ixgbe_init_module is the first routine called when the driver is
7998  * loaded. All it does is register with the PCI subsystem.
7999  **/
8000 static int __init ixgbe_init_module(void)
8001 {
8002         int ret;
8003         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8004         pr_info("%s\n", ixgbe_copyright);
8005
8006         ret = pci_register_driver(&ixgbe_driver);
8007         if (ret)
8008                 return ret;
8009
8010 #ifdef CONFIG_IXGBE_DCA
8011         dca_register_notify(&dca_notifier);
8012 #endif
8013
8014         return 0;
8015 }
8016
8017 module_init(ixgbe_init_module);
8018
8019 /**
8020  * ixgbe_exit_module - Driver Exit Cleanup Routine
8021  *
8022  * ixgbe_exit_module is called just before the driver is removed
8023  * from memory.
8024  **/
8025 static void __exit ixgbe_exit_module(void)
8026 {
8027 #ifdef CONFIG_IXGBE_DCA
8028         dca_unregister_notify(&dca_notifier);
8029 #endif
8030         pci_unregister_driver(&ixgbe_driver);
8031         rcu_barrier(); /* Wait for completion of call_rcu()'s */
8032 }
8033
8034 #ifdef CONFIG_IXGBE_DCA
8035 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8036                             void *p)
8037 {
8038         int ret_val;
8039
8040         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8041                                          __ixgbe_notify_dca);
8042
8043         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8044 }
8045
8046 #endif /* CONFIG_IXGBE_DCA */
8047
8048 module_exit(ixgbe_exit_module);
8049
8050 /* ixgbe_main.c */