drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* EMI Registers */
 144 #define I82579_EMI_ADDR         0x10
 145 #define I82579_EMI_DATA         0x11
 146 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 147
 148 /* Strapping Option Register - RO */
 149 #define E1000_STRAP                     0x0000C
 150 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 152
 153 /* OEM Bits Phy Register */
 154 #define HV_OEM_BITS            PHY_REG(768, 25)
 155 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 156 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 158
 159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 160 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 161
 162 /* KMRN Mode Control */
 163 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 164 #define HV_KMRN_MDIO_SLOW      0x0400
 165
 166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 167 /* Offset 04h HSFSTS */
 168 union ich8_hws_flash_status {
 169         struct ich8_hsfsts {
 170                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 171                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 172                 u16 dael       :1; /* bit 2 Direct Access error Log */
 173                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 174                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 175                 u16 reserved1  :2; /* bit 13:6 Reserved */
 176                 u16 reserved2  :6; /* bit 13:6 Reserved */
 177                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 178                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 179         } hsf_status;
 180         u16 regval;
 181 };
 182
 183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 184 /* Offset 06h FLCTL */
 185 union ich8_hws_flash_ctrl {
 186         struct ich8_hsflctl {
 187                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 188                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 189                 u16 reserved   :5;   /* 7:3 Reserved  */
 190                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 191                 u16 flockdn    :6;   /* 15:10 Reserved */
 192         } hsf_ctrl;
 193         u16 regval;
 194 };
 195
 196 /* ICH Flash Region Access Permissions */
 197 union ich8_hws_flash_regacc {
 198         struct ich8_flracc {
 199                 u32 grra      :8; /* 0:7 GbE region Read Access */
 200                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 201                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 202                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 203         } hsf_flregacc;
 204         u16 regval;
 205 };
 206
 207 /* ICH Flash Protected Region */
 208 union ich8_flash_protected_range {
 209         struct ich8_pr {
 210                 u32 base:13;     /* 0:12 Protected Range Base */
 211                 u32 reserved1:2; /* 13:14 Reserved */
 212                 u32 rpe:1;       /* 15 Read Protection Enable */
 213                 u32 limit:13;    /* 16:28 Protected Range Limit */
 214                 u32 reserved2:2; /* 29:30 Reserved */
 215                 u32 wpe:1;       /* 31 Write Protection Enable */
 216         } range;
 217         u32 regval;
 218 };
 219
 220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 225                                                 u32 offset, u8 byte);
 226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 227                                          u8 *data);
 228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 229                                          u16 *data);
 230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 231                                          u8 size, u16 *data);
 232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 246 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 252
 253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readw(hw->flash_address + reg);
 256 }
 257
 258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 259 {
 260         return readl(hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 264 {
 265         writew(val, hw->flash_address + reg);
 266 }
 267
 268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 269 {
 270         writel(val, hw->flash_address + reg);
 271 }
 272
 273 #define er16flash(reg)          __er16flash(hw, (reg))
 274 #define er32flash(reg)          __er32flash(hw, (reg))
 275 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 276 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 277
 278 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 279 {
 280         u32 ctrl;
 281
 282         ctrl = er32(CTRL);
 283         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 284         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 285         ew32(CTRL, ctrl);
 286         e1e_flush();
 287         udelay(10);
 288         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 289         ew32(CTRL, ctrl);
 290 }
 291
 292 /**
 293  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  Initialize family-specific PHY parameters and function pointers.
 297  **/
 298 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 299 {
 300         struct e1000_phy_info *phy = &hw->phy;
 301         u32 fwsm;
 302         s32 ret_val = 0;
 303
 304         phy->addr                     = 1;
 305         phy->reset_delay_us           = 100;
 306
 307         phy->ops.set_page             = e1000_set_page_igp;
 308         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 309         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 310         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 311         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 312         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 313         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 314         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 315         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 316         phy->ops.power_up             = e1000_power_up_phy_copper;
 317         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 318         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 319
 320         /*
 321          * The MAC-PHY interconnect may still be in SMBus mode
 322          * after Sx->S0.  If the manageability engine (ME) is
 323          * disabled, then toggle the LANPHYPC Value bit to force
 324          * the interconnect to PCIe mode.
 325          */
 326         fwsm = er32(FWSM);
 327         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 328                 e1000_toggle_lanphypc_value_ich8lan(hw);
 329                 msleep(50);
 330
 331                 /*
 332                  * Gate automatic PHY configuration by hardware on
 333                  * non-managed 82579
 334                  */
 335                 if (hw->mac.type == e1000_pch2lan)
 336                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 337         }
 338
 339         /*
 340          * Reset the PHY before any access to it.  Doing so, ensures that
 341          * the PHY is in a known good state before we read/write PHY registers.
 342          * The generic reset is sufficient here, because we haven't determined
 343          * the PHY type yet.
 344          */
 345         ret_val = e1000e_phy_hw_reset_generic(hw);
 346         if (ret_val)
 347                 goto out;
 348
 349         /* Ungate automatic PHY configuration on non-managed 82579 */
 350         if ((hw->mac.type == e1000_pch2lan) &&
 351             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 352                 usleep_range(10000, 20000);
 353                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 354         }
 355
 356         phy->id = e1000_phy_unknown;
 357         switch (hw->mac.type) {
 358         default:
 359                 ret_val = e1000e_get_phy_id(hw);
 360                 if (ret_val)
 361                         goto out;
 362                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 363                         break;
 364                 /* fall-through */
 365         case e1000_pch2lan:
 366                 /*
 367                  * In case the PHY needs to be in mdio slow mode,
 368                  * set slow mode and try to get the PHY id again.
 369                  */
 370                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 371                 if (ret_val)
 372                         goto out;
 373                 ret_val = e1000e_get_phy_id(hw);
 374                 if (ret_val)
 375                         goto out;
 376                 break;
 377         }
 378         phy->type = e1000e_get_phy_type_from_id(phy->id);
 379
 380         switch (phy->type) {
 381         case e1000_phy_82577:
 382         case e1000_phy_82579:
 383                 phy->ops.check_polarity = e1000_check_polarity_82577;
 384                 phy->ops.force_speed_duplex =
 385                     e1000_phy_force_speed_duplex_82577;
 386                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 387                 phy->ops.get_info = e1000_get_phy_info_82577;
 388                 phy->ops.commit = e1000e_phy_sw_reset;
 389                 break;
 390         case e1000_phy_82578:
 391                 phy->ops.check_polarity = e1000_check_polarity_m88;
 392                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 393                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 394                 phy->ops.get_info = e1000e_get_phy_info_m88;
 395                 break;
 396         default:
 397                 ret_val = -E1000_ERR_PHY;
 398                 break;
 399         }
 400
 401 out:
 402         return ret_val;
 403 }
 404
 405 /**
 406  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 407  *  @hw: pointer to the HW structure
 408  *
 409  *  Initialize family-specific PHY parameters and function pointers.
 410  **/
 411 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 412 {
 413         struct e1000_phy_info *phy = &hw->phy;
 414         s32 ret_val;
 415         u16 i = 0;
 416
 417         phy->addr                       = 1;
 418         phy->reset_delay_us             = 100;
 419
 420         phy->ops.power_up               = e1000_power_up_phy_copper;
 421         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 422
 423         /*
 424          * We may need to do this twice - once for IGP and if that fails,
 425          * we'll set BM func pointers and try again
 426          */
 427         ret_val = e1000e_determine_phy_address(hw);
 428         if (ret_val) {
 429                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 430                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 431                 ret_val = e1000e_determine_phy_address(hw);
 432                 if (ret_val) {
 433                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 434                         return ret_val;
 435                 }
 436         }
 437
 438         phy->id = 0;
 439         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 440                (i++ < 100)) {
 441                 usleep_range(1000, 2000);
 442                 ret_val = e1000e_get_phy_id(hw);
 443                 if (ret_val)
 444                         return ret_val;
 445         }
 446
 447         /* Verify phy id */
 448         switch (phy->id) {
 449         case IGP03E1000_E_PHY_ID:
 450                 phy->type = e1000_phy_igp_3;
 451                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 452                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 453                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 454                 phy->ops.get_info = e1000e_get_phy_info_igp;
 455                 phy->ops.check_polarity = e1000_check_polarity_igp;
 456                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 457                 break;
 458         case IFE_E_PHY_ID:
 459         case IFE_PLUS_E_PHY_ID:
 460         case IFE_C_E_PHY_ID:
 461                 phy->type = e1000_phy_ife;
 462                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 463                 phy->ops.get_info = e1000_get_phy_info_ife;
 464                 phy->ops.check_polarity = e1000_check_polarity_ife;
 465                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 466                 break;
 467         case BME1000_E_PHY_ID:
 468                 phy->type = e1000_phy_bm;
 469                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 470                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 471                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 472                 phy->ops.commit = e1000e_phy_sw_reset;
 473                 phy->ops.get_info = e1000e_get_phy_info_m88;
 474                 phy->ops.check_polarity = e1000_check_polarity_m88;
 475                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 476                 break;
 477         default:
 478                 return -E1000_ERR_PHY;
 479                 break;
 480         }
 481
 482         return 0;
 483 }
 484
 485 /**
 486  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 487  *  @hw: pointer to the HW structure
 488  *
 489  *  Initialize family-specific NVM parameters and function
 490  *  pointers.
 491  **/
 492 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 493 {
 494         struct e1000_nvm_info *nvm = &hw->nvm;
 495         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 496         u32 gfpreg, sector_base_addr, sector_end_addr;
 497         u16 i;
 498
 499         /* Can't read flash registers if the register set isn't mapped. */
 500         if (!hw->flash_address) {
 501                 e_dbg("ERROR: Flash registers not mapped\n");
 502                 return -E1000_ERR_CONFIG;
 503         }
 504
 505         nvm->type = e1000_nvm_flash_sw;
 506
 507         gfpreg = er32flash(ICH_FLASH_GFPREG);
 508
 509         /*
 510          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 511          * Add 1 to sector_end_addr since this sector is included in
 512          * the overall size.
 513          */
 514         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 515         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 516
 517         /* flash_base_addr is byte-aligned */
 518         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 519
 520         /*
 521          * find total size of the NVM, then cut in half since the total
 522          * size represents two separate NVM banks.
 523          */
 524         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 525                                 << FLASH_SECTOR_ADDR_SHIFT;
 526         nvm->flash_bank_size /= 2;
 527         /* Adjust to word count */
 528         nvm->flash_bank_size /= sizeof(u16);
 529
 530         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 531
 532         /* Clear shadow ram */
 533         for (i = 0; i < nvm->word_size; i++) {
 534                 dev_spec->shadow_ram[i].modified = false;
 535                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 536         }
 537
 538         return 0;
 539 }
 540
 541 /**
 542  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 543  *  @hw: pointer to the HW structure
 544  *
 545  *  Initialize family-specific MAC parameters and function
 546  *  pointers.
 547  **/
 548 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 549 {
 550         struct e1000_hw *hw = &adapter->hw;
 551         struct e1000_mac_info *mac = &hw->mac;
 552
 553         /* Set media type function pointer */
 554         hw->phy.media_type = e1000_media_type_copper;
 555
 556         /* Set mta register count */
 557         mac->mta_reg_count = 32;
 558         /* Set rar entry count */
 559         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 560         if (mac->type == e1000_ich8lan)
 561                 mac->rar_entry_count--;
 562         /* FWSM register */
 563         mac->has_fwsm = true;
 564         /* ARC subsystem not supported */
 565         mac->arc_subsystem_valid = false;
 566         /* Adaptive IFS supported */
 567         mac->adaptive_ifs = true;
 568
 569         /* LED operations */
 570         switch (mac->type) {
 571         case e1000_ich8lan:
 572         case e1000_ich9lan:
 573         case e1000_ich10lan:
 574                 /* check management mode */
 575                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 576                 /* ID LED init */
 577                 mac->ops.id_led_init = e1000e_id_led_init;
 578                 /* blink LED */
 579                 mac->ops.blink_led = e1000e_blink_led_generic;
 580                 /* setup LED */
 581                 mac->ops.setup_led = e1000e_setup_led_generic;
 582                 /* cleanup LED */
 583                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 584                 /* turn on/off LED */
 585                 mac->ops.led_on = e1000_led_on_ich8lan;
 586                 mac->ops.led_off = e1000_led_off_ich8lan;
 587                 break;
 588         case e1000_pchlan:
 589         case e1000_pch2lan:
 590                 /* check management mode */
 591                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 592                 /* ID LED init */
 593                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 594                 /* setup LED */
 595                 mac->ops.setup_led = e1000_setup_led_pchlan;
 596                 /* cleanup LED */
 597                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 598                 /* turn on/off LED */
 599                 mac->ops.led_on = e1000_led_on_pchlan;
 600                 mac->ops.led_off = e1000_led_off_pchlan;
 601                 break;
 602         default:
 603                 break;
 604         }
 605
 606         /* Enable PCS Lock-loss workaround for ICH8 */
 607         if (mac->type == e1000_ich8lan)
 608                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 609
 610         /* Gate automatic PHY configuration by hardware on managed 82579 */
 611         if ((mac->type == e1000_pch2lan) &&
 612             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 613                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 614
 615         return 0;
 616 }
 617
 618 /**
 619  *  e1000_set_eee_pchlan - Enable/disable EEE support
 620  *  @hw: pointer to the HW structure
 621  *
 622  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 623  *  the LPI Control register will remain set only if/when link is up.
 624  **/
 625 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 626 {
 627         s32 ret_val = 0;
 628         u16 phy_reg;
 629
 630         if (hw->phy.type != e1000_phy_82579)
 631                 goto out;
 632
 633         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 634         if (ret_val)
 635                 goto out;
 636
 637         if (hw->dev_spec.ich8lan.eee_disable)
 638                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 639         else
 640                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 641
 642         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 643 out:
 644         return ret_val;
 645 }
 646
 647 /**
 648  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 649  *  @hw: pointer to the HW structure
 650  *
 651  *  Checks to see of the link status of the hardware has changed.  If a
 652  *  change in link status has been detected, then we read the PHY registers
 653  *  to get the current speed/duplex if link exists.
 654  **/
 655 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 656 {
 657         struct e1000_mac_info *mac = &hw->mac;
 658         s32 ret_val;
 659         bool link;
 660
 661         /*
 662          * We only want to go out to the PHY registers to see if Auto-Neg
 663          * has completed and/or if our link status has changed.  The
 664          * get_link_status flag is set upon receiving a Link Status
 665          * Change or Rx Sequence Error interrupt.
 666          */
 667         if (!mac->get_link_status) {
 668                 ret_val = 0;
 669                 goto out;
 670         }
 671
 672         /*
 673          * First we want to see if the MII Status Register reports
 674          * link.  If so, then we want to get the current speed/duplex
 675          * of the PHY.
 676          */
 677         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 678         if (ret_val)
 679                 goto out;
 680
 681         if (hw->mac.type == e1000_pchlan) {
 682                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 683                 if (ret_val)
 684                         goto out;
 685         }
 686
 687         if (!link)
 688                 goto out; /* No link detected */
 689
 690         mac->get_link_status = false;
 691
 692         if (hw->phy.type == e1000_phy_82578) {
 693                 ret_val = e1000_link_stall_workaround_hv(hw);
 694                 if (ret_val)
 695                         goto out;
 696         }
 697
 698         if (hw->mac.type == e1000_pch2lan) {
 699                 ret_val = e1000_k1_workaround_lv(hw);
 700                 if (ret_val)
 701                         goto out;
 702         }
 703
 704         /*
 705          * Check if there was DownShift, must be checked
 706          * immediately after link-up
 707          */
 708         e1000e_check_downshift(hw);
 709
 710         /* Enable/Disable EEE after link up */
 711         ret_val = e1000_set_eee_pchlan(hw);
 712         if (ret_val)
 713                 goto out;
 714
 715         /*
 716          * If we are forcing speed/duplex, then we simply return since
 717          * we have already determined whether we have link or not.
 718          */
 719         if (!mac->autoneg) {
 720                 ret_val = -E1000_ERR_CONFIG;
 721                 goto out;
 722         }
 723
 724         /*
 725          * Auto-Neg is enabled.  Auto Speed Detection takes care
 726          * of MAC speed/duplex configuration.  So we only need to
 727          * configure Collision Distance in the MAC.
 728          */
 729         e1000e_config_collision_dist(hw);
 730
 731         /*
 732          * Configure Flow Control now that Auto-Neg has completed.
 733          * First, we need to restore the desired flow control
 734          * settings because we may have had to re-autoneg with a
 735          * different link partner.
 736          */
 737         ret_val = e1000e_config_fc_after_link_up(hw);
 738         if (ret_val)
 739                 e_dbg("Error configuring flow control\n");
 740
 741 out:
 742         return ret_val;
 743 }
 744
 745 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 746 {
 747         struct e1000_hw *hw = &adapter->hw;
 748         s32 rc;
 749
 750         rc = e1000_init_mac_params_ich8lan(adapter);
 751         if (rc)
 752                 return rc;
 753
 754         rc = e1000_init_nvm_params_ich8lan(hw);
 755         if (rc)
 756                 return rc;
 757
 758         switch (hw->mac.type) {
 759         case e1000_ich8lan:
 760         case e1000_ich9lan:
 761         case e1000_ich10lan:
 762                 rc = e1000_init_phy_params_ich8lan(hw);
 763                 break;
 764         case e1000_pchlan:
 765         case e1000_pch2lan:
 766                 rc = e1000_init_phy_params_pchlan(hw);
 767                 break;
 768         default:
 769                 break;
 770         }
 771         if (rc)
 772                 return rc;
 773
 774         /*
 775          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 776          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 777          */
 778         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 779             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 780              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 781                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 782                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 783
 784                 hw->mac.ops.blink_led = NULL;
 785         }
 786
 787         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 788             (adapter->hw.phy.type == e1000_phy_igp_3))
 789                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 790
 791         /* Disable EEE by default until IEEE802.3az spec is finalized */
 792         if (adapter->flags2 & FLAG2_HAS_EEE)
 793                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 794
 795         return 0;
 796 }
 797
 798 static DEFINE_MUTEX(nvm_mutex);
 799
 800 /**
 801  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 802  *  @hw: pointer to the HW structure
 803  *
 804  *  Acquires the mutex for performing NVM operations.
 805  **/
 806 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 807 {
 808         mutex_lock(&nvm_mutex);
 809
 810         return 0;
 811 }
 812
 813 /**
 814  *  e1000_release_nvm_ich8lan - Release NVM mutex
 815  *  @hw: pointer to the HW structure
 816  *
 817  *  Releases the mutex used while performing NVM operations.
 818  **/
 819 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 820 {
 821         mutex_unlock(&nvm_mutex);
 822 }
 823
 824 static DEFINE_MUTEX(swflag_mutex);
 825
 826 /**
 827  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 828  *  @hw: pointer to the HW structure
 829  *
 830  *  Acquires the software control flag for performing PHY and select
 831  *  MAC CSR accesses.
 832  **/
 833 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 834 {
 835         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 836         s32 ret_val = 0;
 837
 838         mutex_lock(&swflag_mutex);
 839
 840         while (timeout) {
 841                 extcnf_ctrl = er32(EXTCNF_CTRL);
 842                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 843                         break;
 844
 845                 mdelay(1);
 846                 timeout--;
 847         }
 848
 849         if (!timeout) {
 850                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 851                 ret_val = -E1000_ERR_CONFIG;
 852                 goto out;
 853         }
 854
 855         timeout = SW_FLAG_TIMEOUT;
 856
 857         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 858         ew32(EXTCNF_CTRL, extcnf_ctrl);
 859
 860         while (timeout) {
 861                 extcnf_ctrl = er32(EXTCNF_CTRL);
 862                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 863                         break;
 864
 865                 mdelay(1);
 866                 timeout--;
 867         }
 868
 869         if (!timeout) {
 870                 e_dbg("Failed to acquire the semaphore.\n");
 871                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 872                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 873                 ret_val = -E1000_ERR_CONFIG;
 874                 goto out;
 875         }
 876
 877 out:
 878         if (ret_val)
 879                 mutex_unlock(&swflag_mutex);
 880
 881         return ret_val;
 882 }
 883
 884 /**
 885  *  e1000_release_swflag_ich8lan - Release software control flag
 886  *  @hw: pointer to the HW structure
 887  *
 888  *  Releases the software control flag for performing PHY and select
 889  *  MAC CSR accesses.
 890  **/
 891 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 892 {
 893         u32 extcnf_ctrl;
 894
 895         extcnf_ctrl = er32(EXTCNF_CTRL);
 896
 897         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 898                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 899                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 900         } else {
 901                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 902         }
 903
 904         mutex_unlock(&swflag_mutex);
 905 }
 906
 907 /**
 908  *  e1000_check_mng_mode_ich8lan - Checks management mode
 909  *  @hw: pointer to the HW structure
 910  *
 911  *  This checks if the adapter has any manageability enabled.
 912  *  This is a function pointer entry point only called by read/write
 913  *  routines for the PHY and NVM parts.
 914  **/
 915 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 916 {
 917         u32 fwsm;
 918
 919         fwsm = er32(FWSM);
 920         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 921                ((fwsm & E1000_FWSM_MODE_MASK) ==
 922                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 923 }
 924
 925 /**
 926  *  e1000_check_mng_mode_pchlan - Checks management mode
 927  *  @hw: pointer to the HW structure
 928  *
 929  *  This checks if the adapter has iAMT enabled.
 930  *  This is a function pointer entry point only called by read/write
 931  *  routines for the PHY and NVM parts.
 932  **/
 933 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 934 {
 935         u32 fwsm;
 936
 937         fwsm = er32(FWSM);
 938         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 939                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 940 }
 941
 942 /**
 943  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 944  *  @hw: pointer to the HW structure
 945  *
 946  *  Checks if firmware is blocking the reset of the PHY.
 947  *  This is a function pointer entry point only called by
 948  *  reset routines.
 949  **/
 950 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 951 {
 952         u32 fwsm;
 953
 954         fwsm = er32(FWSM);
 955
 956         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 957 }
 958
 959 /**
 960  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 961  *  @hw: pointer to the HW structure
 962  *
 963  *  Assumes semaphore already acquired.
 964  *
 965  **/
 966 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 967 {
 968         u16 phy_data;
 969         u32 strap = er32(STRAP);
 970         s32 ret_val = 0;
 971
 972         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 973
 974         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 975         if (ret_val)
 976                 goto out;
 977
 978         phy_data &= ~HV_SMB_ADDR_MASK;
 979         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 980         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 981         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 982
 983 out:
 984         return ret_val;
 985 }
 986
 987 /**
 988  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 989  *  @hw:   pointer to the HW structure
 990  *
 991  *  SW should configure the LCD from the NVM extended configuration region
 992  *  as a workaround for certain parts.
 993  **/
 994 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 995 {
 996         struct e1000_phy_info *phy = &hw->phy;
 997         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 998         s32 ret_val = 0;
 999         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1000
1001         /*
1002          * Initialize the PHY from the NVM on ICH platforms.  This
1003          * is needed due to an issue where the NVM configuration is
1004          * not properly autoloaded after power transitions.
1005          * Therefore, after each PHY reset, we will load the
1006          * configuration data out of the NVM manually.
1007          */
1008         switch (hw->mac.type) {
1009         case e1000_ich8lan:
1010                 if (phy->type != e1000_phy_igp_3)
1011                         return ret_val;
1012
1013                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1014                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1015                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1016                         break;
1017                 }
1018                 /* Fall-thru */
1019         case e1000_pchlan:
1020         case e1000_pch2lan:
1021                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1022                 break;
1023         default:
1024                 return ret_val;
1025         }
1026
1027         ret_val = hw->phy.ops.acquire(hw);
1028         if (ret_val)
1029                 return ret_val;
1030
1031         data = er32(FEXTNVM);
1032         if (!(data & sw_cfg_mask))
1033                 goto out;
1034
1035         /*
1036          * Make sure HW does not configure LCD from PHY
1037          * extended configuration before SW configuration
1038          */
1039         data = er32(EXTCNF_CTRL);
1040         if (!(hw->mac.type == e1000_pch2lan)) {
1041                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1042                         goto out;
1043         }
1044
1045         cnf_size = er32(EXTCNF_SIZE);
1046         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1047         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1048         if (!cnf_size)
1049                 goto out;
1050
1051         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1052         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1053
1054         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1055             (hw->mac.type == e1000_pchlan)) ||
1056              (hw->mac.type == e1000_pch2lan)) {
1057                 /*
1058                  * HW configures the SMBus address and LEDs when the
1059                  * OEM and LCD Write Enable bits are set in the NVM.
1060                  * When both NVM bits are cleared, SW will configure
1061                  * them instead.
1062                  */
1063                 ret_val = e1000_write_smbus_addr(hw);
1064                 if (ret_val)
1065                         goto out;
1066
1067                 data = er32(LEDCTL);
1068                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1069                                                         (u16)data);
1070                 if (ret_val)
1071                         goto out;
1072         }
1073
1074         /* Configure LCD from extended configuration region. */
1075
1076         /* cnf_base_addr is in DWORD */
1077         word_addr = (u16)(cnf_base_addr << 1);
1078
1079         for (i = 0; i < cnf_size; i++) {
1080                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1081                                          &reg_data);
1082                 if (ret_val)
1083                         goto out;
1084
1085                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1086                                          1, &reg_addr);
1087                 if (ret_val)
1088                         goto out;
1089
1090                 /* Save off the PHY page for future writes. */
1091                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1092                         phy_page = reg_data;
1093                         continue;
1094                 }
1095
1096                 reg_addr &= PHY_REG_MASK;
1097                 reg_addr |= phy_page;
1098
1099                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1100                                                     reg_data);
1101                 if (ret_val)
1102                         goto out;
1103         }
1104
1105 out:
1106         hw->phy.ops.release(hw);
1107         return ret_val;
1108 }
1109
1110 /**
1111  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1112  *  @hw:   pointer to the HW structure
1113  *  @link: link up bool flag
1114  *
1115  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1116  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1117  *  If link is down, the function will restore the default K1 setting located
1118  *  in the NVM.
1119  **/
1120 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1121 {
1122         s32 ret_val = 0;
1123         u16 status_reg = 0;
1124         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1125
1126         if (hw->mac.type != e1000_pchlan)
1127                 goto out;
1128
1129         /* Wrap the whole flow with the sw flag */
1130         ret_val = hw->phy.ops.acquire(hw);
1131         if (ret_val)
1132                 goto out;
1133
1134         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1135         if (link) {
1136                 if (hw->phy.type == e1000_phy_82578) {
1137                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1138                                                                   &status_reg);
1139                         if (ret_val)
1140                                 goto release;
1141
1142                         status_reg &= BM_CS_STATUS_LINK_UP |
1143                                       BM_CS_STATUS_RESOLVED |
1144                                       BM_CS_STATUS_SPEED_MASK;
1145
1146                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1147                                            BM_CS_STATUS_RESOLVED |
1148                                            BM_CS_STATUS_SPEED_1000))
1149                                 k1_enable = false;
1150                 }
1151
1152                 if (hw->phy.type == e1000_phy_82577) {
1153                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1154                                                                   &status_reg);
1155                         if (ret_val)
1156                                 goto release;
1157
1158                         status_reg &= HV_M_STATUS_LINK_UP |
1159                                       HV_M_STATUS_AUTONEG_COMPLETE |
1160                                       HV_M_STATUS_SPEED_MASK;
1161
1162                         if (status_reg == (HV_M_STATUS_LINK_UP |
1163                                            HV_M_STATUS_AUTONEG_COMPLETE |
1164                                            HV_M_STATUS_SPEED_1000))
1165                                 k1_enable = false;
1166                 }
1167
1168                 /* Link stall fix for link up */
1169                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1170                                                            0x0100);
1171                 if (ret_val)
1172                         goto release;
1173
1174         } else {
1175                 /* Link stall fix for link down */
1176                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1177                                                            0x4100);
1178                 if (ret_val)
1179                         goto release;
1180         }
1181
1182         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1183
1184 release:
1185         hw->phy.ops.release(hw);
1186 out:
1187         return ret_val;
1188 }
1189
1190 /**
1191  *  e1000_configure_k1_ich8lan - Configure K1 power state
1192  *  @hw: pointer to the HW structure
1193  *  @enable: K1 state to configure
1194  *
1195  *  Configure the K1 power state based on the provided parameter.
1196  *  Assumes semaphore already acquired.
1197  *
1198  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1199  **/
1200 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1201 {
1202         s32 ret_val = 0;
1203         u32 ctrl_reg = 0;
1204         u32 ctrl_ext = 0;
1205         u32 reg = 0;
1206         u16 kmrn_reg = 0;
1207
1208         ret_val = e1000e_read_kmrn_reg_locked(hw,
1209                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1210                                              &kmrn_reg);
1211         if (ret_val)
1212                 goto out;
1213
1214         if (k1_enable)
1215                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1216         else
1217                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1218
1219         ret_val = e1000e_write_kmrn_reg_locked(hw,
1220                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1221                                               kmrn_reg);
1222         if (ret_val)
1223                 goto out;
1224
1225         udelay(20);
1226         ctrl_ext = er32(CTRL_EXT);
1227         ctrl_reg = er32(CTRL);
1228
1229         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1230         reg |= E1000_CTRL_FRCSPD;
1231         ew32(CTRL, reg);
1232
1233         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1234         e1e_flush();
1235         udelay(20);
1236         ew32(CTRL, ctrl_reg);
1237         ew32(CTRL_EXT, ctrl_ext);
1238         e1e_flush();
1239         udelay(20);
1240
1241 out:
1242         return ret_val;
1243 }
1244
1245 /**
1246  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1247  *  @hw:       pointer to the HW structure
1248  *  @d0_state: boolean if entering d0 or d3 device state
1249  *
1250  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1251  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1252  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1253  **/
1254 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1255 {
1256         s32 ret_val = 0;
1257         u32 mac_reg;
1258         u16 oem_reg;
1259
1260         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1261                 return ret_val;
1262
1263         ret_val = hw->phy.ops.acquire(hw);
1264         if (ret_val)
1265                 return ret_val;
1266
1267         if (!(hw->mac.type == e1000_pch2lan)) {
1268                 mac_reg = er32(EXTCNF_CTRL);
1269                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1270                         goto out;
1271         }
1272
1273         mac_reg = er32(FEXTNVM);
1274         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1275                 goto out;
1276
1277         mac_reg = er32(PHY_CTRL);
1278
1279         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1280         if (ret_val)
1281                 goto out;
1282
1283         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1284
1285         if (d0_state) {
1286                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1287                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1288
1289                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1290                         oem_reg |= HV_OEM_BITS_LPLU;
1291         } else {
1292                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1293                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1294
1295                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1296                         oem_reg |= HV_OEM_BITS_LPLU;
1297         }
1298         /* Restart auto-neg to activate the bits */
1299         if (!e1000_check_reset_block(hw))
1300                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1301         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1302
1303 out:
1304         hw->phy.ops.release(hw);
1305
1306         return ret_val;
1307 }
1308
1309
1310 /**
1311  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1312  *  @hw:   pointer to the HW structure
1313  **/
1314 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1315 {
1316         s32 ret_val;
1317         u16 data;
1318
1319         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1320         if (ret_val)
1321                 return ret_val;
1322
1323         data |= HV_KMRN_MDIO_SLOW;
1324
1325         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1326
1327         return ret_val;
1328 }
1329
1330 /**
1331  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1332  *  done after every PHY reset.
1333  **/
1334 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1335 {
1336         s32 ret_val = 0;
1337         u16 phy_data;
1338
1339         if (hw->mac.type != e1000_pchlan)
1340                 return ret_val;
1341
1342         /* Set MDIO slow mode before any other MDIO access */
1343         if (hw->phy.type == e1000_phy_82577) {
1344                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1345                 if (ret_val)
1346                         goto out;
1347         }
1348
1349         if (((hw->phy.type == e1000_phy_82577) &&
1350              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1351             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1352                 /* Disable generation of early preamble */
1353                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1354                 if (ret_val)
1355                         return ret_val;
1356
1357                 /* Preamble tuning for SSC */
1358                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1359                 if (ret_val)
1360                         return ret_val;
1361         }
1362
1363         if (hw->phy.type == e1000_phy_82578) {
1364                 /*
1365                  * Return registers to default by doing a soft reset then
1366                  * writing 0x3140 to the control register.
1367                  */
1368                 if (hw->phy.revision < 2) {
1369                         e1000e_phy_sw_reset(hw);
1370                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1371                 }
1372         }
1373
1374         /* Select page 0 */
1375         ret_val = hw->phy.ops.acquire(hw);
1376         if (ret_val)
1377                 return ret_val;
1378
1379         hw->phy.addr = 1;
1380         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1381         hw->phy.ops.release(hw);
1382         if (ret_val)
1383                 goto out;
1384
1385         /*
1386          * Configure the K1 Si workaround during phy reset assuming there is
1387          * link so that it disables K1 if link is in 1Gbps.
1388          */
1389         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1390         if (ret_val)
1391                 goto out;
1392
1393         /* Workaround for link disconnects on a busy hub in half duplex */
1394         ret_val = hw->phy.ops.acquire(hw);
1395         if (ret_val)
1396                 goto out;
1397         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1398         if (ret_val)
1399                 goto release;
1400         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1401                                                phy_data & 0x00FF);
1402 release:
1403         hw->phy.ops.release(hw);
1404 out:
1405         return ret_val;
1406 }
1407
1408 /**
1409  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1410  *  @hw:   pointer to the HW structure
1411  **/
1412 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1413 {
1414         u32 mac_reg;
1415         u16 i, phy_reg = 0;
1416         s32 ret_val;
1417
1418         ret_val = hw->phy.ops.acquire(hw);
1419         if (ret_val)
1420                 return;
1421         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1422         if (ret_val)
1423                 goto release;
1424
1425         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1426         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1427                 mac_reg = er32(RAL(i));
1428                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1429                                            (u16)(mac_reg & 0xFFFF));
1430                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1431                                            (u16)((mac_reg >> 16) & 0xFFFF));
1432
1433                 mac_reg = er32(RAH(i));
1434                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1435                                            (u16)(mac_reg & 0xFFFF));
1436                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1437                                            (u16)((mac_reg & E1000_RAH_AV)
1438                                                  >> 16));
1439         }
1440
1441         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1442
1443 release:
1444         hw->phy.ops.release(hw);
1445 }
1446
1447 /**
1448  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1449  *  with 82579 PHY
1450  *  @hw: pointer to the HW structure
1451  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1452  **/
1453 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1454 {
1455         s32 ret_val = 0;
1456         u16 phy_reg, data;
1457         u32 mac_reg;
1458         u16 i;
1459
1460         if (hw->mac.type != e1000_pch2lan)
1461                 goto out;
1462
1463         /* disable Rx path while enabling/disabling workaround */
1464         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1465         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1466         if (ret_val)
1467                 goto out;
1468
1469         if (enable) {
1470                 /*
1471                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1472                  * SHRAL/H) and initial CRC values to the MAC
1473                  */
1474                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1475                         u8 mac_addr[ETH_ALEN] = {0};
1476                         u32 addr_high, addr_low;
1477
1478                         addr_high = er32(RAH(i));
1479                         if (!(addr_high & E1000_RAH_AV))
1480                                 continue;
1481                         addr_low = er32(RAL(i));
1482                         mac_addr[0] = (addr_low & 0xFF);
1483                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1484                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1485                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1486                         mac_addr[4] = (addr_high & 0xFF);
1487                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1488
1489                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1490                 }
1491
1492                 /* Write Rx addresses to the PHY */
1493                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1494
1495                 /* Enable jumbo frame workaround in the MAC */
1496                 mac_reg = er32(FFLT_DBG);
1497                 mac_reg &= ~(1 << 14);
1498                 mac_reg |= (7 << 15);
1499                 ew32(FFLT_DBG, mac_reg);
1500
1501                 mac_reg = er32(RCTL);
1502                 mac_reg |= E1000_RCTL_SECRC;
1503                 ew32(RCTL, mac_reg);
1504
1505                 ret_val = e1000e_read_kmrn_reg(hw,
1506                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1507                                                 &data);
1508                 if (ret_val)
1509                         goto out;
1510                 ret_val = e1000e_write_kmrn_reg(hw,
1511                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1512                                                 data | (1 << 0));
1513                 if (ret_val)
1514                         goto out;
1515                 ret_val = e1000e_read_kmrn_reg(hw,
1516                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1517                                                 &data);
1518                 if (ret_val)
1519                         goto out;
1520                 data &= ~(0xF << 8);
1521                 data |= (0xB << 8);
1522                 ret_val = e1000e_write_kmrn_reg(hw,
1523                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1524                                                 data);
1525                 if (ret_val)
1526                         goto out;
1527
1528                 /* Enable jumbo frame workaround in the PHY */
1529                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1530                 data &= ~(0x7F << 5);
1531                 data |= (0x37 << 5);
1532                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1533                 if (ret_val)
1534                         goto out;
1535                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1536                 data &= ~(1 << 13);
1537                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1538                 if (ret_val)
1539                         goto out;
1540                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1541                 data &= ~(0x3FF << 2);
1542                 data |= (0x1A << 2);
1543                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1544                 if (ret_val)
1545                         goto out;
1546                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1547                 if (ret_val)
1548                         goto out;
1549                 e1e_rphy(hw, HV_PM_CTRL, &data);
1550                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1551                 if (ret_val)
1552                         goto out;
1553         } else {
1554                 /* Write MAC register values back to h/w defaults */
1555                 mac_reg = er32(FFLT_DBG);
1556                 mac_reg &= ~(0xF << 14);
1557                 ew32(FFLT_DBG, mac_reg);
1558
1559                 mac_reg = er32(RCTL);
1560                 mac_reg &= ~E1000_RCTL_SECRC;
1561                 ew32(RCTL, mac_reg);
1562
1563                 ret_val = e1000e_read_kmrn_reg(hw,
1564                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1565                                                 &data);
1566                 if (ret_val)
1567                         goto out;
1568                 ret_val = e1000e_write_kmrn_reg(hw,
1569                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1570                                                 data & ~(1 << 0));
1571                 if (ret_val)
1572                         goto out;
1573                 ret_val = e1000e_read_kmrn_reg(hw,
1574                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1575                                                 &data);
1576                 if (ret_val)
1577                         goto out;
1578                 data &= ~(0xF << 8);
1579                 data |= (0xB << 8);
1580                 ret_val = e1000e_write_kmrn_reg(hw,
1581                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1582                                                 data);
1583                 if (ret_val)
1584                         goto out;
1585
1586                 /* Write PHY register values back to h/w defaults */
1587                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1588                 data &= ~(0x7F << 5);
1589                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1590                 if (ret_val)
1591                         goto out;
1592                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1593                 data |= (1 << 13);
1594                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1595                 if (ret_val)
1596                         goto out;
1597                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1598                 data &= ~(0x3FF << 2);
1599                 data |= (0x8 << 2);
1600                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1601                 if (ret_val)
1602                         goto out;
1603                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1604                 if (ret_val)
1605                         goto out;
1606                 e1e_rphy(hw, HV_PM_CTRL, &data);
1607                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1608                 if (ret_val)
1609                         goto out;
1610         }
1611
1612         /* re-enable Rx path after enabling/disabling workaround */
1613         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1614
1615 out:
1616         return ret_val;
1617 }
1618
1619 /**
1620  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1621  *  done after every PHY reset.
1622  **/
1623 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1624 {
1625         s32 ret_val = 0;
1626
1627         if (hw->mac.type != e1000_pch2lan)
1628                 goto out;
1629
1630         /* Set MDIO slow mode before any other MDIO access */
1631         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1632
1633 out:
1634         return ret_val;
1635 }
1636
1637 /**
1638  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1639  *  @hw:   pointer to the HW structure
1640  *
1641  *  Workaround to set the K1 beacon duration for 82579 parts
1642  **/
1643 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1644 {
1645         s32 ret_val = 0;
1646         u16 status_reg = 0;
1647         u32 mac_reg;
1648
1649         if (hw->mac.type != e1000_pch2lan)
1650                 goto out;
1651
1652         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1653         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1654         if (ret_val)
1655                 goto out;
1656
1657         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1658             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1659                 mac_reg = er32(FEXTNVM4);
1660                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1661
1662                 if (status_reg & HV_M_STATUS_SPEED_1000)
1663                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1664                 else
1665                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1666
1667                 ew32(FEXTNVM4, mac_reg);
1668         }
1669
1670 out:
1671         return ret_val;
1672 }
1673
1674 /**
1675  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1676  *  @hw:   pointer to the HW structure
1677  *  @gate: boolean set to true to gate, false to ungate
1678  *
1679  *  Gate/ungate the automatic PHY configuration via hardware; perform
1680  *  the configuration via software instead.
1681  **/
1682 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1683 {
1684         u32 extcnf_ctrl;
1685
1686         if (hw->mac.type != e1000_pch2lan)
1687                 return;
1688
1689         extcnf_ctrl = er32(EXTCNF_CTRL);
1690
1691         if (gate)
1692                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1693         else
1694                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1695
1696         ew32(EXTCNF_CTRL, extcnf_ctrl);
1697         return;
1698 }
1699
1700 /**
1701  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1702  *  @hw: pointer to the HW structure
1703  *
1704  *  Check the appropriate indication the MAC has finished configuring the
1705  *  PHY after a software reset.
1706  **/
1707 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1708 {
1709         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1710
1711         /* Wait for basic configuration completes before proceeding */
1712         do {
1713                 data = er32(STATUS);
1714                 data &= E1000_STATUS_LAN_INIT_DONE;
1715                 udelay(100);
1716         } while ((!data) && --loop);
1717
1718         /*
1719          * If basic configuration is incomplete before the above loop
1720          * count reaches 0, loading the configuration from NVM will
1721          * leave the PHY in a bad state possibly resulting in no link.
1722          */
1723         if (loop == 0)
1724                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1725
1726         /* Clear the Init Done bit for the next init event */
1727         data = er32(STATUS);
1728         data &= ~E1000_STATUS_LAN_INIT_DONE;
1729         ew32(STATUS, data);
1730 }
1731
1732 /**
1733  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1734  *  @hw: pointer to the HW structure
1735  **/
1736 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1737 {
1738         s32 ret_val = 0;
1739         u16 reg;
1740
1741         if (e1000_check_reset_block(hw))
1742                 goto out;
1743
1744         /* Allow time for h/w to get to quiescent state after reset */
1745         usleep_range(10000, 20000);
1746
1747         /* Perform any necessary post-reset workarounds */
1748         switch (hw->mac.type) {
1749         case e1000_pchlan:
1750                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1751                 if (ret_val)
1752                         goto out;
1753                 break;
1754         case e1000_pch2lan:
1755                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1756                 if (ret_val)
1757                         goto out;
1758                 break;
1759         default:
1760                 break;
1761         }
1762
1763         /* Clear the host wakeup bit after lcd reset */
1764         if (hw->mac.type >= e1000_pchlan) {
1765                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1766                 reg &= ~BM_WUC_HOST_WU_BIT;
1767                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1768         }
1769
1770         /* Configure the LCD with the extended configuration region in NVM */
1771         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1772         if (ret_val)
1773                 goto out;
1774
1775         /* Configure the LCD with the OEM bits in NVM */
1776         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1777
1778         if (hw->mac.type == e1000_pch2lan) {
1779                 /* Ungate automatic PHY configuration on non-managed 82579 */
1780                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1781                         usleep_range(10000, 20000);
1782                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1783                 }
1784
1785                 /* Set EEE LPI Update Timer to 200usec */
1786                 ret_val = hw->phy.ops.acquire(hw);
1787                 if (ret_val)
1788                         goto out;
1789                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1790                                                        I82579_LPI_UPDATE_TIMER);
1791                 if (ret_val)
1792                         goto release;
1793                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1794                                                        0x1387);
1795 release:
1796                 hw->phy.ops.release(hw);
1797         }
1798
1799 out:
1800         return ret_val;
1801 }
1802
1803 /**
1804  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1805  *  @hw: pointer to the HW structure
1806  *
1807  *  Resets the PHY
1808  *  This is a function pointer entry point called by drivers
1809  *  or other shared routines.
1810  **/
1811 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1812 {
1813         s32 ret_val = 0;
1814
1815         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1816         if ((hw->mac.type == e1000_pch2lan) &&
1817             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1818                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1819
1820         ret_val = e1000e_phy_hw_reset_generic(hw);
1821         if (ret_val)
1822                 goto out;
1823
1824         ret_val = e1000_post_phy_reset_ich8lan(hw);
1825
1826 out:
1827         return ret_val;
1828 }
1829
1830 /**
1831  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1832  *  @hw: pointer to the HW structure
1833  *  @active: true to enable LPLU, false to disable
1834  *
1835  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1836  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1837  *  the phy speed. This function will manually set the LPLU bit and restart
1838  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1839  *  since it configures the same bit.
1840  **/
1841 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1842 {
1843         s32 ret_val = 0;
1844         u16 oem_reg;
1845
1846         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1847         if (ret_val)
1848                 goto out;
1849
1850         if (active)
1851                 oem_reg |= HV_OEM_BITS_LPLU;
1852         else
1853                 oem_reg &= ~HV_OEM_BITS_LPLU;
1854
1855         oem_reg |= HV_OEM_BITS_RESTART_AN;
1856         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1857
1858 out:
1859         return ret_val;
1860 }
1861
1862 /**
1863  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1864  *  @hw: pointer to the HW structure
1865  *  @active: true to enable LPLU, false to disable
1866  *
1867  *  Sets the LPLU D0 state according to the active flag.  When
1868  *  activating LPLU this function also disables smart speed
1869  *  and vice versa.  LPLU will not be activated unless the
1870  *  device autonegotiation advertisement meets standards of
1871  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1872  *  This is a function pointer entry point only called by
1873  *  PHY setup routines.
1874  **/
1875 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1876 {
1877         struct e1000_phy_info *phy = &hw->phy;
1878         u32 phy_ctrl;
1879         s32 ret_val = 0;
1880         u16 data;
1881
1882         if (phy->type == e1000_phy_ife)
1883                 return ret_val;
1884
1885         phy_ctrl = er32(PHY_CTRL);
1886
1887         if (active) {
1888                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1889                 ew32(PHY_CTRL, phy_ctrl);
1890
1891                 if (phy->type != e1000_phy_igp_3)
1892                         return 0;
1893
1894                 /*
1895                  * Call gig speed drop workaround on LPLU before accessing
1896                  * any PHY registers
1897                  */
1898                 if (hw->mac.type == e1000_ich8lan)
1899                         e1000e_gig_downshift_workaround_ich8lan(hw);
1900
1901                 /* When LPLU is enabled, we should disable SmartSpeed */
1902                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1903                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1904                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1905                 if (ret_val)
1906                         return ret_val;
1907         } else {
1908                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1909                 ew32(PHY_CTRL, phy_ctrl);
1910
1911                 if (phy->type != e1000_phy_igp_3)
1912                         return 0;
1913
1914                 /*
1915                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1916                  * during Dx states where the power conservation is most
1917                  * important.  During driver activity we should enable
1918                  * SmartSpeed, so performance is maintained.
1919                  */
1920                 if (phy->smart_speed == e1000_smart_speed_on) {
1921                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1922                                            &data);
1923                         if (ret_val)
1924                                 return ret_val;
1925
1926                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1927                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1928                                            data);
1929                         if (ret_val)
1930                                 return ret_val;
1931                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1932                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1933                                            &data);
1934                         if (ret_val)
1935                                 return ret_val;
1936
1937                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1938                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1939                                            data);
1940                         if (ret_val)
1941                                 return ret_val;
1942                 }
1943         }
1944
1945         return 0;
1946 }
1947
1948 /**
1949  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1950  *  @hw: pointer to the HW structure
1951  *  @active: true to enable LPLU, false to disable
1952  *
1953  *  Sets the LPLU D3 state according to the active flag.  When
1954  *  activating LPLU this function also disables smart speed
1955  *  and vice versa.  LPLU will not be activated unless the
1956  *  device autonegotiation advertisement meets standards of
1957  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1958  *  This is a function pointer entry point only called by
1959  *  PHY setup routines.
1960  **/
1961 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1962 {
1963         struct e1000_phy_info *phy = &hw->phy;
1964         u32 phy_ctrl;
1965         s32 ret_val;
1966         u16 data;
1967
1968         phy_ctrl = er32(PHY_CTRL);
1969
1970         if (!active) {
1971                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1972                 ew32(PHY_CTRL, phy_ctrl);
1973
1974                 if (phy->type != e1000_phy_igp_3)
1975                         return 0;
1976
1977                 /*
1978                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1979                  * during Dx states where the power conservation is most
1980                  * important.  During driver activity we should enable
1981                  * SmartSpeed, so performance is maintained.
1982                  */
1983                 if (phy->smart_speed == e1000_smart_speed_on) {
1984                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1985                                            &data);
1986                         if (ret_val)
1987                                 return ret_val;
1988
1989                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1990                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1991                                            data);
1992                         if (ret_val)
1993                                 return ret_val;
1994                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1995                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1996                                            &data);
1997                         if (ret_val)
1998                                 return ret_val;
1999
2000                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2001                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2002                                            data);
2003                         if (ret_val)
2004                                 return ret_val;
2005                 }
2006         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2007                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2008                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2009                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2010                 ew32(PHY_CTRL, phy_ctrl);
2011
2012                 if (phy->type != e1000_phy_igp_3)
2013                         return 0;
2014
2015                 /*
2016                  * Call gig speed drop workaround on LPLU before accessing
2017                  * any PHY registers
2018                  */
2019                 if (hw->mac.type == e1000_ich8lan)
2020                         e1000e_gig_downshift_workaround_ich8lan(hw);
2021
2022                 /* When LPLU is enabled, we should disable SmartSpeed */
2023                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2024                 if (ret_val)
2025                         return ret_val;
2026
2027                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2028                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2029         }
2030
2031         return 0;
2032 }
2033
2034 /**
2035  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2036  *  @hw: pointer to the HW structure
2037  *  @bank:  pointer to the variable that returns the active bank
2038  *
2039  *  Reads signature byte from the NVM using the flash access registers.
2040  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2041  **/
2042 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2043 {
2044         u32 eecd;
2045         struct e1000_nvm_info *nvm = &hw->nvm;
2046         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2047         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2048         u8 sig_byte = 0;
2049         s32 ret_val = 0;
2050
2051         switch (hw->mac.type) {
2052         case e1000_ich8lan:
2053         case e1000_ich9lan:
2054                 eecd = er32(EECD);
2055                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2056                     E1000_EECD_SEC1VAL_VALID_MASK) {
2057                         if (eecd & E1000_EECD_SEC1VAL)
2058                                 *bank = 1;
2059                         else
2060                                 *bank = 0;
2061
2062                         return 0;
2063                 }
2064                 e_dbg("Unable to determine valid NVM bank via EEC - "
2065                        "reading flash signature\n");
2066                 /* fall-thru */
2067         default:
2068                 /* set bank to 0 in case flash read fails */
2069                 *bank = 0;
2070
2071                 /* Check bank 0 */
2072                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2073                                                         &sig_byte);
2074                 if (ret_val)
2075                         return ret_val;
2076                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2077                     E1000_ICH_NVM_SIG_VALUE) {
2078                         *bank = 0;
2079                         return 0;
2080                 }
2081
2082                 /* Check bank 1 */
2083                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2084                                                         bank1_offset,
2085                                                         &sig_byte);
2086                 if (ret_val)
2087                         return ret_val;
2088                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2089                     E1000_ICH_NVM_SIG_VALUE) {
2090                         *bank = 1;
2091                         return 0;
2092                 }
2093
2094                 e_dbg("ERROR: No valid NVM bank present\n");
2095                 return -E1000_ERR_NVM;
2096         }
2097
2098         return 0;
2099 }
2100
2101 /**
2102  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2103  *  @hw: pointer to the HW structure
2104  *  @offset: The offset (in bytes) of the word(s) to read.
2105  *  @words: Size of data to read in words
2106  *  @data: Pointer to the word(s) to read at offset.
2107  *
2108  *  Reads a word(s) from the NVM using the flash access registers.
2109  **/
2110 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2111                                   u16 *data)
2112 {
2113         struct e1000_nvm_info *nvm = &hw->nvm;
2114         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2115         u32 act_offset;
2116         s32 ret_val = 0;
2117         u32 bank = 0;
2118         u16 i, word;
2119
2120         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2121             (words == 0)) {
2122                 e_dbg("nvm parameter(s) out of bounds\n");
2123                 ret_val = -E1000_ERR_NVM;
2124                 goto out;
2125         }
2126
2127         nvm->ops.acquire(hw);
2128
2129         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2130         if (ret_val) {
2131                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2132                 bank = 0;
2133         }
2134
2135         act_offset = (bank) ? nvm->flash_bank_size : 0;
2136         act_offset += offset;
2137
2138         ret_val = 0;
2139         for (i = 0; i < words; i++) {
2140                 if (dev_spec->shadow_ram[offset+i].modified) {
2141                         data[i] = dev_spec->shadow_ram[offset+i].value;
2142                 } else {
2143                         ret_val = e1000_read_flash_word_ich8lan(hw,
2144                                                                 act_offset + i,
2145                                                                 &word);
2146                         if (ret_val)
2147                                 break;
2148                         data[i] = word;
2149                 }
2150         }
2151
2152         nvm->ops.release(hw);
2153
2154 out:
2155         if (ret_val)
2156                 e_dbg("NVM read error: %d\n", ret_val);
2157
2158         return ret_val;
2159 }
2160
2161 /**
2162  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2163  *  @hw: pointer to the HW structure
2164  *
2165  *  This function does initial flash setup so that a new read/write/erase cycle
2166  *  can be started.
2167  **/
2168 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2169 {
2170         union ich8_hws_flash_status hsfsts;
2171         s32 ret_val = -E1000_ERR_NVM;
2172
2173         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2174
2175         /* Check if the flash descriptor is valid */
2176         if (hsfsts.hsf_status.fldesvalid == 0) {
2177                 e_dbg("Flash descriptor invalid.  "
2178                          "SW Sequencing must be used.\n");
2179                 return -E1000_ERR_NVM;
2180         }
2181
2182         /* Clear FCERR and DAEL in hw status by writing 1 */
2183         hsfsts.hsf_status.flcerr = 1;
2184         hsfsts.hsf_status.dael = 1;
2185
2186         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2187
2188         /*
2189          * Either we should have a hardware SPI cycle in progress
2190          * bit to check against, in order to start a new cycle or
2191          * FDONE bit should be changed in the hardware so that it
2192          * is 1 after hardware reset, which can then be used as an
2193          * indication whether a cycle is in progress or has been
2194          * completed.
2195          */
2196
2197         if (hsfsts.hsf_status.flcinprog == 0) {
2198                 /*
2199                  * There is no cycle running at present,
2200                  * so we can start a cycle.
2201                  * Begin by setting Flash Cycle Done.
2202                  */
2203                 hsfsts.hsf_status.flcdone = 1;
2204                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2205                 ret_val = 0;
2206         } else {
2207                 s32 i = 0;
2208
2209                 /*
2210                  * Otherwise poll for sometime so the current
2211                  * cycle has a chance to end before giving up.
2212                  */
2213                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2214                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2215                         if (hsfsts.hsf_status.flcinprog == 0) {
2216                                 ret_val = 0;
2217                                 break;
2218                         }
2219                         udelay(1);
2220                 }
2221                 if (ret_val == 0) {
2222                         /*
2223                          * Successful in waiting for previous cycle to timeout,
2224                          * now set the Flash Cycle Done.
2225                          */
2226                         hsfsts.hsf_status.flcdone = 1;
2227                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2228                 } else {
2229                         e_dbg("Flash controller busy, cannot get access\n");
2230                 }
2231         }
2232
2233         return ret_val;
2234 }
2235
2236 /**
2237  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2238  *  @hw: pointer to the HW structure
2239  *  @timeout: maximum time to wait for completion
2240  *
2241  *  This function starts a flash cycle and waits for its completion.
2242  **/
2243 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2244 {
2245         union ich8_hws_flash_ctrl hsflctl;
2246         union ich8_hws_flash_status hsfsts;
2247         s32 ret_val = -E1000_ERR_NVM;
2248         u32 i = 0;
2249
2250         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2251         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2252         hsflctl.hsf_ctrl.flcgo = 1;
2253         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2254
2255         /* wait till FDONE bit is set to 1 */
2256         do {
2257                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2258                 if (hsfsts.hsf_status.flcdone == 1)
2259                         break;
2260                 udelay(1);
2261         } while (i++ < timeout);
2262
2263         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2264                 return 0;
2265
2266         return ret_val;
2267 }
2268
2269 /**
2270  *  e1000_read_flash_word_ich8lan - Read word from flash
2271  *  @hw: pointer to the HW structure
2272  *  @offset: offset to data location
2273  *  @data: pointer to the location for storing the data
2274  *
2275  *  Reads the flash word at offset into data.  Offset is converted
2276  *  to bytes before read.
2277  **/
2278 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2279                                          u16 *data)
2280 {
2281         /* Must convert offset into bytes. */
2282         offset <<= 1;
2283
2284         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2285 }
2286
2287 /**
2288  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2289  *  @hw: pointer to the HW structure
2290  *  @offset: The offset of the byte to read.
2291  *  @data: Pointer to a byte to store the value read.
2292  *
2293  *  Reads a single byte from the NVM using the flash access registers.
2294  **/
2295 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2296                                          u8 *data)
2297 {
2298         s32 ret_val;
2299         u16 word = 0;
2300
2301         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2302         if (ret_val)
2303                 return ret_val;
2304
2305         *data = (u8)word;
2306
2307         return 0;
2308 }
2309
2310 /**
2311  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2312  *  @hw: pointer to the HW structure
2313  *  @offset: The offset (in bytes) of the byte or word to read.
2314  *  @size: Size of data to read, 1=byte 2=word
2315  *  @data: Pointer to the word to store the value read.
2316  *
2317  *  Reads a byte or word from the NVM using the flash access registers.
2318  **/
2319 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2320                                          u8 size, u16 *data)
2321 {
2322         union ich8_hws_flash_status hsfsts;
2323         union ich8_hws_flash_ctrl hsflctl;
2324         u32 flash_linear_addr;
2325         u32 flash_data = 0;
2326         s32 ret_val = -E1000_ERR_NVM;
2327         u8 count = 0;
2328
2329         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2330                 return -E1000_ERR_NVM;
2331
2332         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2333                             hw->nvm.flash_base_addr;
2334
2335         do {
2336                 udelay(1);
2337                 /* Steps */
2338                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2339                 if (ret_val != 0)
2340                         break;
2341
2342                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2343                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2344                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2345                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2346                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2347
2348                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2349
2350                 ret_val = e1000_flash_cycle_ich8lan(hw,
2351                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2352
2353                 /*
2354                  * Check if FCERR is set to 1, if set to 1, clear it
2355                  * and try the whole sequence a few more times, else
2356                  * read in (shift in) the Flash Data0, the order is
2357                  * least significant byte first msb to lsb
2358                  */
2359                 if (ret_val == 0) {
2360                         flash_data = er32flash(ICH_FLASH_FDATA0);
2361                         if (size == 1)
2362                                 *data = (u8)(flash_data & 0x000000FF);
2363                         else if (size == 2)
2364                                 *data = (u16)(flash_data & 0x0000FFFF);
2365                         break;
2366                 } else {
2367                         /*
2368                          * If we've gotten here, then things are probably
2369                          * completely hosed, but if the error condition is
2370                          * detected, it won't hurt to give it another try...
2371                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2372                          */
2373                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2374                         if (hsfsts.hsf_status.flcerr == 1) {
2375                                 /* Repeat for some time before giving up. */
2376                                 continue;
2377                         } else if (hsfsts.hsf_status.flcdone == 0) {
2378                                 e_dbg("Timeout error - flash cycle "
2379                                          "did not complete.\n");
2380                                 break;
2381                         }
2382                 }
2383         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2384
2385         return ret_val;
2386 }
2387
2388 /**
2389  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2390  *  @hw: pointer to the HW structure
2391  *  @offset: The offset (in bytes) of the word(s) to write.
2392  *  @words: Size of data to write in words
2393  *  @data: Pointer to the word(s) to write at offset.
2394  *
2395  *  Writes a byte or word to the NVM using the flash access registers.
2396  **/
2397 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2398                                    u16 *data)
2399 {
2400         struct e1000_nvm_info *nvm = &hw->nvm;
2401         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2402         u16 i;
2403
2404         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2405             (words == 0)) {
2406                 e_dbg("nvm parameter(s) out of bounds\n");
2407                 return -E1000_ERR_NVM;
2408         }
2409
2410         nvm->ops.acquire(hw);
2411
2412         for (i = 0; i < words; i++) {
2413                 dev_spec->shadow_ram[offset+i].modified = true;
2414                 dev_spec->shadow_ram[offset+i].value = data[i];
2415         }
2416
2417         nvm->ops.release(hw);
2418
2419         return 0;
2420 }
2421
2422 /**
2423  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2424  *  @hw: pointer to the HW structure
2425  *
2426  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2427  *  which writes the checksum to the shadow ram.  The changes in the shadow
2428  *  ram are then committed to the EEPROM by processing each bank at a time
2429  *  checking for the modified bit and writing only the pending changes.
2430  *  After a successful commit, the shadow ram is cleared and is ready for
2431  *  future writes.
2432  **/
2433 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2434 {
2435         struct e1000_nvm_info *nvm = &hw->nvm;
2436         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2437         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2438         s32 ret_val;
2439         u16 data;
2440
2441         ret_val = e1000e_update_nvm_checksum_generic(hw);
2442         if (ret_val)
2443                 goto out;
2444
2445         if (nvm->type != e1000_nvm_flash_sw)
2446                 goto out;
2447
2448         nvm->ops.acquire(hw);
2449
2450         /*
2451          * We're writing to the opposite bank so if we're on bank 1,
2452          * write to bank 0 etc.  We also need to erase the segment that
2453          * is going to be written
2454          */
2455         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2456         if (ret_val) {
2457                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2458                 bank = 0;
2459         }
2460
2461         if (bank == 0) {
2462                 new_bank_offset = nvm->flash_bank_size;
2463                 old_bank_offset = 0;
2464                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2465                 if (ret_val)
2466                         goto release;
2467         } else {
2468                 old_bank_offset = nvm->flash_bank_size;
2469                 new_bank_offset = 0;
2470                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2471                 if (ret_val)
2472                         goto release;
2473         }
2474
2475         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2476                 /*
2477                  * Determine whether to write the value stored
2478                  * in the other NVM bank or a modified value stored
2479                  * in the shadow RAM
2480                  */
2481                 if (dev_spec->shadow_ram[i].modified) {
2482                         data = dev_spec->shadow_ram[i].value;
2483                 } else {
2484                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2485                                                                 old_bank_offset,
2486                                                                 &data);
2487                         if (ret_val)
2488                                 break;
2489                 }
2490
2491                 /*
2492                  * If the word is 0x13, then make sure the signature bits
2493                  * (15:14) are 11b until the commit has completed.
2494                  * This will allow us to write 10b which indicates the
2495                  * signature is valid.  We want to do this after the write
2496                  * has completed so that we don't mark the segment valid
2497                  * while the write is still in progress
2498                  */
2499                 if (i == E1000_ICH_NVM_SIG_WORD)
2500                         data |= E1000_ICH_NVM_SIG_MASK;
2501
2502                 /* Convert offset to bytes. */
2503                 act_offset = (i + new_bank_offset) << 1;
2504
2505                 udelay(100);
2506                 /* Write the bytes to the new bank. */
2507                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2508                                                                act_offset,
2509                                                                (u8)data);
2510                 if (ret_val)
2511                         break;
2512
2513                 udelay(100);
2514                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2515                                                           act_offset + 1,
2516                                                           (u8)(data >> 8));
2517                 if (ret_val)
2518                         break;
2519         }
2520
2521         /*
2522          * Don't bother writing the segment valid bits if sector
2523          * programming failed.
2524          */
2525         if (ret_val) {
2526                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2527                 e_dbg("Flash commit failed.\n");
2528                 goto release;
2529         }
2530
2531         /*
2532          * Finally validate the new segment by setting bit 15:14
2533          * to 10b in word 0x13 , this can be done without an
2534          * erase as well since these bits are 11 to start with
2535          * and we need to change bit 14 to 0b
2536          */
2537         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2538         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2539         if (ret_val)
2540                 goto release;
2541
2542         data &= 0xBFFF;
2543         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2544                                                        act_offset * 2 + 1,
2545                                                        (u8)(data >> 8));
2546         if (ret_val)
2547                 goto release;
2548
2549         /*
2550          * And invalidate the previously valid segment by setting
2551          * its signature word (0x13) high_byte to 0b. This can be
2552          * done without an erase because flash erase sets all bits
2553          * to 1's. We can write 1's to 0's without an erase
2554          */
2555         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2556         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2557         if (ret_val)
2558                 goto release;
2559
2560         /* Great!  Everything worked, we can now clear the cached entries. */
2561         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2562                 dev_spec->shadow_ram[i].modified = false;
2563                 dev_spec->shadow_ram[i].value = 0xFFFF;
2564         }
2565
2566 release:
2567         nvm->ops.release(hw);
2568
2569         /*
2570          * Reload the EEPROM, or else modifications will not appear
2571          * until after the next adapter reset.
2572          */
2573         if (!ret_val) {
2574                 e1000e_reload_nvm(hw);
2575                 usleep_range(10000, 20000);
2576         }
2577
2578 out:
2579         if (ret_val)
2580                 e_dbg("NVM update error: %d\n", ret_val);
2581
2582         return ret_val;
2583 }
2584
2585 /**
2586  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2587  *  @hw: pointer to the HW structure
2588  *
2589  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2590  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2591  *  calculated, in which case we need to calculate the checksum and set bit 6.
2592  **/
2593 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2594 {
2595         s32 ret_val;
2596         u16 data;
2597
2598         /*
2599          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2600          * needs to be fixed.  This bit is an indication that the NVM
2601          * was prepared by OEM software and did not calculate the
2602          * checksum...a likely scenario.
2603          */
2604         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2605         if (ret_val)
2606                 return ret_val;
2607
2608         if ((data & 0x40) == 0) {
2609                 data |= 0x40;
2610                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2611                 if (ret_val)
2612                         return ret_val;
2613                 ret_val = e1000e_update_nvm_checksum(hw);
2614                 if (ret_val)
2615                         return ret_val;
2616         }
2617
2618         return e1000e_validate_nvm_checksum_generic(hw);
2619 }
2620
2621 /**
2622  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2623  *  @hw: pointer to the HW structure
2624  *
2625  *  To prevent malicious write/erase of the NVM, set it to be read-only
2626  *  so that the hardware ignores all write/erase cycles of the NVM via
2627  *  the flash control registers.  The shadow-ram copy of the NVM will
2628  *  still be updated, however any updates to this copy will not stick
2629  *  across driver reloads.
2630  **/
2631 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2632 {
2633         struct e1000_nvm_info *nvm = &hw->nvm;
2634         union ich8_flash_protected_range pr0;
2635         union ich8_hws_flash_status hsfsts;
2636         u32 gfpreg;
2637
2638         nvm->ops.acquire(hw);
2639
2640         gfpreg = er32flash(ICH_FLASH_GFPREG);
2641
2642         /* Write-protect GbE Sector of NVM */
2643         pr0.regval = er32flash(ICH_FLASH_PR0);
2644         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2645         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2646         pr0.range.wpe = true;
2647         ew32flash(ICH_FLASH_PR0, pr0.regval);
2648
2649         /*
2650          * Lock down a subset of GbE Flash Control Registers, e.g.
2651          * PR0 to prevent the write-protection from being lifted.
2652          * Once FLOCKDN is set, the registers protected by it cannot
2653          * be written until FLOCKDN is cleared by a hardware reset.
2654          */
2655         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2656         hsfsts.hsf_status.flockdn = true;
2657         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2658
2659         nvm->ops.release(hw);
2660 }
2661
2662 /**
2663  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2664  *  @hw: pointer to the HW structure
2665  *  @offset: The offset (in bytes) of the byte/word to read.
2666  *  @size: Size of data to read, 1=byte 2=word
2667  *  @data: The byte(s) to write to the NVM.
2668  *
2669  *  Writes one/two bytes to the NVM using the flash access registers.
2670  **/
2671 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2672                                           u8 size, u16 data)
2673 {
2674         union ich8_hws_flash_status hsfsts;
2675         union ich8_hws_flash_ctrl hsflctl;
2676         u32 flash_linear_addr;
2677         u32 flash_data = 0;
2678         s32 ret_val;
2679         u8 count = 0;
2680
2681         if (size < 1 || size > 2 || data > size * 0xff ||
2682             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2683                 return -E1000_ERR_NVM;
2684
2685         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2686                             hw->nvm.flash_base_addr;
2687
2688         do {
2689                 udelay(1);
2690                 /* Steps */
2691                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2692                 if (ret_val)
2693                         break;
2694
2695                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2696                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2697                 hsflctl.hsf_ctrl.fldbcount = size -1;
2698                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2699                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2700
2701                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2702
2703                 if (size == 1)
2704                         flash_data = (u32)data & 0x00FF;
2705                 else
2706                         flash_data = (u32)data;
2707
2708                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2709
2710                 /*
2711                  * check if FCERR is set to 1 , if set to 1, clear it
2712                  * and try the whole sequence a few more times else done
2713                  */
2714                 ret_val = e1000_flash_cycle_ich8lan(hw,
2715                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2716                 if (!ret_val)
2717                         break;
2718
2719                 /*
2720                  * If we're here, then things are most likely
2721                  * completely hosed, but if the error condition
2722                  * is detected, it won't hurt to give it another
2723                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2724                  */
2725                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2726                 if (hsfsts.hsf_status.flcerr == 1)
2727                         /* Repeat for some time before giving up. */
2728                         continue;
2729                 if (hsfsts.hsf_status.flcdone == 0) {
2730                         e_dbg("Timeout error - flash cycle "
2731                                  "did not complete.");
2732                         break;
2733                 }
2734         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2735
2736         return ret_val;
2737 }
2738
2739 /**
2740  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2741  *  @hw: pointer to the HW structure
2742  *  @offset: The index of the byte to read.
2743  *  @data: The byte to write to the NVM.
2744  *
2745  *  Writes a single byte to the NVM using the flash access registers.
2746  **/
2747 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2748                                           u8 data)
2749 {
2750         u16 word = (u16)data;
2751
2752         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2753 }
2754
2755 /**
2756  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2757  *  @hw: pointer to the HW structure
2758  *  @offset: The offset of the byte to write.
2759  *  @byte: The byte to write to the NVM.
2760  *
2761  *  Writes a single byte to the NVM using the flash access registers.
2762  *  Goes through a retry algorithm before giving up.
2763  **/
2764 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2765                                                 u32 offset, u8 byte)
2766 {
2767         s32 ret_val;
2768         u16 program_retries;
2769
2770         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2771         if (!ret_val)
2772                 return ret_val;
2773
2774         for (program_retries = 0; program_retries < 100; program_retries++) {
2775                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2776                 udelay(100);
2777                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2778                 if (!ret_val)
2779                         break;
2780         }
2781         if (program_retries == 100)
2782                 return -E1000_ERR_NVM;
2783
2784         return 0;
2785 }
2786
2787 /**
2788  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2789  *  @hw: pointer to the HW structure
2790  *  @bank: 0 for first bank, 1 for second bank, etc.
2791  *
2792  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2793  *  bank N is 4096 * N + flash_reg_addr.
2794  **/
2795 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2796 {
2797         struct e1000_nvm_info *nvm = &hw->nvm;
2798         union ich8_hws_flash_status hsfsts;
2799         union ich8_hws_flash_ctrl hsflctl;
2800         u32 flash_linear_addr;
2801         /* bank size is in 16bit words - adjust to bytes */
2802         u32 flash_bank_size = nvm->flash_bank_size * 2;
2803         s32 ret_val;
2804         s32 count = 0;
2805         s32 j, iteration, sector_size;
2806
2807         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2808
2809         /*
2810          * Determine HW Sector size: Read BERASE bits of hw flash status
2811          * register
2812          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2813          *     consecutive sectors.  The start index for the nth Hw sector
2814          *     can be calculated as = bank * 4096 + n * 256
2815          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2816          *     The start index for the nth Hw sector can be calculated
2817          *     as = bank * 4096
2818          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2819          *     (ich9 only, otherwise error condition)
2820          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2821          */
2822         switch (hsfsts.hsf_status.berasesz) {
2823         case 0:
2824                 /* Hw sector size 256 */
2825                 sector_size = ICH_FLASH_SEG_SIZE_256;
2826                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2827                 break;
2828         case 1:
2829                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2830                 iteration = 1;
2831                 break;
2832         case 2:
2833                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2834                 iteration = 1;
2835                 break;
2836         case 3:
2837                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2838                 iteration = 1;
2839                 break;
2840         default:
2841                 return -E1000_ERR_NVM;
2842         }
2843
2844         /* Start with the base address, then add the sector offset. */
2845         flash_linear_addr = hw->nvm.flash_base_addr;
2846         flash_linear_addr += (bank) ? flash_bank_size : 0;
2847
2848         for (j = 0; j < iteration ; j++) {
2849                 do {
2850                         /* Steps */
2851                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2852                         if (ret_val)
2853                                 return ret_val;
2854
2855                         /*
2856                          * Write a value 11 (block Erase) in Flash
2857                          * Cycle field in hw flash control
2858                          */
2859                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2860                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2861                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2862
2863                         /*
2864                          * Write the last 24 bits of an index within the
2865                          * block into Flash Linear address field in Flash
2866                          * Address.
2867                          */
2868                         flash_linear_addr += (j * sector_size);
2869                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2870
2871                         ret_val = e1000_flash_cycle_ich8lan(hw,
2872                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2873                         if (ret_val == 0)
2874                                 break;
2875
2876                         /*
2877                          * Check if FCERR is set to 1.  If 1,
2878                          * clear it and try the whole sequence
2879                          * a few more times else Done
2880                          */
2881                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2882                         if (hsfsts.hsf_status.flcerr == 1)
2883                                 /* repeat for some time before giving up */
2884                                 continue;
2885                         else if (hsfsts.hsf_status.flcdone == 0)
2886                                 return ret_val;
2887                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2888         }
2889
2890         return 0;
2891 }
2892
2893 /**
2894  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2895  *  @hw: pointer to the HW structure
2896  *  @data: Pointer to the LED settings
2897  *
2898  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2899  *  settings is all 0's or F's, set the LED default to a valid LED default
2900  *  setting.
2901  **/
2902 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2903 {
2904         s32 ret_val;
2905
2906         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2907         if (ret_val) {
2908                 e_dbg("NVM Read Error\n");
2909                 return ret_val;
2910         }
2911
2912         if (*data == ID_LED_RESERVED_0000 ||
2913             *data == ID_LED_RESERVED_FFFF)
2914                 *data = ID_LED_DEFAULT_ICH8LAN;
2915
2916         return 0;
2917 }
2918
2919 /**
2920  *  e1000_id_led_init_pchlan - store LED configurations
2921  *  @hw: pointer to the HW structure
2922  *
2923  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2924  *  the PHY LED configuration register.
2925  *
2926  *  PCH also does not have an "always on" or "always off" mode which
2927  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2928  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2929  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2930  *  link based on logic in e1000_led_[on|off]_pchlan().
2931  **/
2932 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2933 {
2934         struct e1000_mac_info *mac = &hw->mac;
2935         s32 ret_val;
2936         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2937         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2938         u16 data, i, temp, shift;
2939
2940         /* Get default ID LED modes */
2941         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2942         if (ret_val)
2943                 goto out;
2944
2945         mac->ledctl_default = er32(LEDCTL);
2946         mac->ledctl_mode1 = mac->ledctl_default;
2947         mac->ledctl_mode2 = mac->ledctl_default;
2948
2949         for (i = 0; i < 4; i++) {
2950                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2951                 shift = (i * 5);
2952                 switch (temp) {
2953                 case ID_LED_ON1_DEF2:
2954                 case ID_LED_ON1_ON2:
2955                 case ID_LED_ON1_OFF2:
2956                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2957                         mac->ledctl_mode1 |= (ledctl_on << shift);
2958                         break;
2959                 case ID_LED_OFF1_DEF2:
2960                 case ID_LED_OFF1_ON2:
2961                 case ID_LED_OFF1_OFF2:
2962                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2963                         mac->ledctl_mode1 |= (ledctl_off << shift);
2964                         break;
2965                 default:
2966                         /* Do nothing */
2967                         break;
2968                 }
2969                 switch (temp) {
2970                 case ID_LED_DEF1_ON2:
2971                 case ID_LED_ON1_ON2:
2972                 case ID_LED_OFF1_ON2:
2973                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2974                         mac->ledctl_mode2 |= (ledctl_on << shift);
2975                         break;
2976                 case ID_LED_DEF1_OFF2:
2977                 case ID_LED_ON1_OFF2:
2978                 case ID_LED_OFF1_OFF2:
2979                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2980                         mac->ledctl_mode2 |= (ledctl_off << shift);
2981                         break;
2982                 default:
2983                         /* Do nothing */
2984                         break;
2985                 }
2986         }
2987
2988 out:
2989         return ret_val;
2990 }
2991
2992 /**
2993  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2994  *  @hw: pointer to the HW structure
2995  *
2996  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2997  *  register, so the the bus width is hard coded.
2998  **/
2999 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3000 {
3001         struct e1000_bus_info *bus = &hw->bus;
3002         s32 ret_val;
3003
3004         ret_val = e1000e_get_bus_info_pcie(hw);
3005
3006         /*
3007          * ICH devices are "PCI Express"-ish.  They have
3008          * a configuration space, but do not contain
3009          * PCI Express Capability registers, so bus width
3010          * must be hardcoded.
3011          */
3012         if (bus->width == e1000_bus_width_unknown)
3013                 bus->width = e1000_bus_width_pcie_x1;
3014
3015         return ret_val;
3016 }
3017
3018 /**
3019  *  e1000_reset_hw_ich8lan - Reset the hardware
3020  *  @hw: pointer to the HW structure
3021  *
3022  *  Does a full reset of the hardware which includes a reset of the PHY and
3023  *  MAC.
3024  **/
3025 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3026 {
3027         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3028         u16 reg;
3029         u32 ctrl, kab;
3030         s32 ret_val;
3031
3032         /*
3033          * Prevent the PCI-E bus from sticking if there is no TLP connection
3034          * on the last TLP read/write transaction when MAC is reset.
3035          */
3036         ret_val = e1000e_disable_pcie_master(hw);
3037         if (ret_val)
3038                 e_dbg("PCI-E Master disable polling has failed.\n");
3039
3040         e_dbg("Masking off all interrupts\n");
3041         ew32(IMC, 0xffffffff);
3042
3043         /*
3044          * Disable the Transmit and Receive units.  Then delay to allow
3045          * any pending transactions to complete before we hit the MAC
3046          * with the global reset.
3047          */
3048         ew32(RCTL, 0);
3049         ew32(TCTL, E1000_TCTL_PSP);
3050         e1e_flush();
3051
3052         usleep_range(10000, 20000);
3053
3054         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3055         if (hw->mac.type == e1000_ich8lan) {
3056                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3057                 ew32(PBA, E1000_PBA_8K);
3058                 /* Set Packet Buffer Size to 16k. */
3059                 ew32(PBS, E1000_PBS_16K);
3060         }
3061
3062         if (hw->mac.type == e1000_pchlan) {
3063                 /* Save the NVM K1 bit setting*/
3064                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3065                 if (ret_val)
3066                         return ret_val;
3067
3068                 if (reg & E1000_NVM_K1_ENABLE)
3069                         dev_spec->nvm_k1_enabled = true;
3070                 else
3071                         dev_spec->nvm_k1_enabled = false;
3072         }
3073
3074         ctrl = er32(CTRL);
3075
3076         if (!e1000_check_reset_block(hw)) {
3077                 /*
3078                  * Full-chip reset requires MAC and PHY reset at the same
3079                  * time to make sure the interface between MAC and the
3080                  * external PHY is reset.
3081                  */
3082                 ctrl |= E1000_CTRL_PHY_RST;
3083
3084                 /*
3085                  * Gate automatic PHY configuration by hardware on
3086                  * non-managed 82579
3087                  */
3088                 if ((hw->mac.type == e1000_pch2lan) &&
3089                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3090                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3091         }
3092         ret_val = e1000_acquire_swflag_ich8lan(hw);
3093         e_dbg("Issuing a global reset to ich8lan\n");
3094         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3095         /* cannot issue a flush here because it hangs the hardware */
3096         msleep(20);
3097
3098         if (!ret_val)
3099                 mutex_unlock(&swflag_mutex);
3100
3101         if (ctrl & E1000_CTRL_PHY_RST) {
3102                 ret_val = hw->phy.ops.get_cfg_done(hw);
3103                 if (ret_val)
3104                         goto out;
3105
3106                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3107                 if (ret_val)
3108                         goto out;
3109         }
3110
3111         /*
3112          * For PCH, this write will make sure that any noise
3113          * will be detected as a CRC error and be dropped rather than show up
3114          * as a bad packet to the DMA engine.
3115          */
3116         if (hw->mac.type == e1000_pchlan)
3117                 ew32(CRC_OFFSET, 0x65656565);
3118
3119         ew32(IMC, 0xffffffff);
3120         er32(ICR);
3121
3122         kab = er32(KABGTXD);
3123         kab |= E1000_KABGTXD_BGSQLBIAS;
3124         ew32(KABGTXD, kab);
3125
3126 out:
3127         return ret_val;
3128 }
3129
3130 /**
3131  *  e1000_init_hw_ich8lan - Initialize the hardware
3132  *  @hw: pointer to the HW structure
3133  *
3134  *  Prepares the hardware for transmit and receive by doing the following:
3135  *   - initialize hardware bits
3136  *   - initialize LED identification
3137  *   - setup receive address registers
3138  *   - setup flow control
3139  *   - setup transmit descriptors
3140  *   - clear statistics
3141  **/
3142 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3143 {
3144         struct e1000_mac_info *mac = &hw->mac;
3145         u32 ctrl_ext, txdctl, snoop;
3146         s32 ret_val;
3147         u16 i;
3148
3149         e1000_initialize_hw_bits_ich8lan(hw);
3150
3151         /* Initialize identification LED */
3152         ret_val = mac->ops.id_led_init(hw);
3153         if (ret_val)
3154                 e_dbg("Error initializing identification LED\n");
3155                 /* This is not fatal and we should not stop init due to this */
3156
3157         /* Setup the receive address. */
3158         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3159
3160         /* Zero out the Multicast HASH table */
3161         e_dbg("Zeroing the MTA\n");
3162         for (i = 0; i < mac->mta_reg_count; i++)
3163                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3164
3165         /*
3166          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3167          * the ME.  Disable wakeup by clearing the host wakeup bit.
3168          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3169          */
3170         if (hw->phy.type == e1000_phy_82578) {
3171                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3172                 i &= ~BM_WUC_HOST_WU_BIT;
3173                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3174                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3175                 if (ret_val)
3176                         return ret_val;
3177         }
3178
3179         /* Setup link and flow control */
3180         ret_val = e1000_setup_link_ich8lan(hw);
3181
3182         /* Set the transmit descriptor write-back policy for both queues */
3183         txdctl = er32(TXDCTL(0));
3184         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3185                  E1000_TXDCTL_FULL_TX_DESC_WB;
3186         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3187                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3188         ew32(TXDCTL(0), txdctl);
3189         txdctl = er32(TXDCTL(1));
3190         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3191                  E1000_TXDCTL_FULL_TX_DESC_WB;
3192         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3193                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3194         ew32(TXDCTL(1), txdctl);
3195
3196         /*
3197          * ICH8 has opposite polarity of no_snoop bits.
3198          * By default, we should use snoop behavior.
3199          */
3200         if (mac->type == e1000_ich8lan)
3201                 snoop = PCIE_ICH8_SNOOP_ALL;
3202         else
3203                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3204         e1000e_set_pcie_no_snoop(hw, snoop);
3205
3206         ctrl_ext = er32(CTRL_EXT);
3207         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3208         ew32(CTRL_EXT, ctrl_ext);
3209
3210         /*
3211          * Clear all of the statistics registers (clear on read).  It is
3212          * important that we do this after we have tried to establish link
3213          * because the symbol error count will increment wildly if there
3214          * is no link.
3215          */
3216         e1000_clear_hw_cntrs_ich8lan(hw);
3217
3218         return 0;
3219 }
3220 /**
3221  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3222  *  @hw: pointer to the HW structure
3223  *
3224  *  Sets/Clears required hardware bits necessary for correctly setting up the
3225  *  hardware for transmit and receive.
3226  **/
3227 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3228 {
3229         u32 reg;
3230
3231         /* Extended Device Control */
3232         reg = er32(CTRL_EXT);
3233         reg |= (1 << 22);
3234         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3235         if (hw->mac.type >= e1000_pchlan)
3236                 reg |= E1000_CTRL_EXT_PHYPDEN;
3237         ew32(CTRL_EXT, reg);
3238
3239         /* Transmit Descriptor Control 0 */
3240         reg = er32(TXDCTL(0));
3241         reg |= (1 << 22);
3242         ew32(TXDCTL(0), reg);
3243
3244         /* Transmit Descriptor Control 1 */
3245         reg = er32(TXDCTL(1));
3246         reg |= (1 << 22);
3247         ew32(TXDCTL(1), reg);
3248
3249         /* Transmit Arbitration Control 0 */
3250         reg = er32(TARC(0));
3251         if (hw->mac.type == e1000_ich8lan)
3252                 reg |= (1 << 28) | (1 << 29);
3253         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3254         ew32(TARC(0), reg);
3255
3256         /* Transmit Arbitration Control 1 */
3257         reg = er32(TARC(1));
3258         if (er32(TCTL) & E1000_TCTL_MULR)
3259                 reg &= ~(1 << 28);
3260         else
3261                 reg |= (1 << 28);
3262         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3263         ew32(TARC(1), reg);
3264
3265         /* Device Status */
3266         if (hw->mac.type == e1000_ich8lan) {
3267                 reg = er32(STATUS);
3268                 reg &= ~(1 << 31);
3269                 ew32(STATUS, reg);
3270         }
3271
3272         /*
3273          * work-around descriptor data corruption issue during nfs v2 udp
3274          * traffic, just disable the nfs filtering capability
3275          */
3276         reg = er32(RFCTL);
3277         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3278         ew32(RFCTL, reg);
3279 }
3280
3281 /**
3282  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3283  *  @hw: pointer to the HW structure
3284  *
3285  *  Determines which flow control settings to use, then configures flow
3286  *  control.  Calls the appropriate media-specific link configuration
3287  *  function.  Assuming the adapter has a valid link partner, a valid link
3288  *  should be established.  Assumes the hardware has previously been reset
3289  *  and the transmitter and receiver are not enabled.
3290  **/
3291 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3292 {
3293         s32 ret_val;
3294
3295         if (e1000_check_reset_block(hw))
3296                 return 0;
3297
3298         /*
3299          * ICH parts do not have a word in the NVM to determine
3300          * the default flow control setting, so we explicitly
3301          * set it to full.
3302          */
3303         if (hw->fc.requested_mode == e1000_fc_default) {
3304                 /* Workaround h/w hang when Tx flow control enabled */
3305                 if (hw->mac.type == e1000_pchlan)
3306                         hw->fc.requested_mode = e1000_fc_rx_pause;
3307                 else
3308                         hw->fc.requested_mode = e1000_fc_full;
3309         }
3310
3311         /*
3312          * Save off the requested flow control mode for use later.  Depending
3313          * on the link partner's capabilities, we may or may not use this mode.
3314          */
3315         hw->fc.current_mode = hw->fc.requested_mode;
3316
3317         e_dbg("After fix-ups FlowControl is now = %x\n",
3318                 hw->fc.current_mode);
3319
3320         /* Continue to configure the copper link. */
3321         ret_val = e1000_setup_copper_link_ich8lan(hw);
3322         if (ret_val)
3323                 return ret_val;
3324
3325         ew32(FCTTV, hw->fc.pause_time);
3326         if ((hw->phy.type == e1000_phy_82578) ||
3327             (hw->phy.type == e1000_phy_82579) ||
3328             (hw->phy.type == e1000_phy_82577)) {
3329                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3330
3331                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3332                                    hw->fc.pause_time);
3333                 if (ret_val)
3334                         return ret_val;
3335         }
3336
3337         return e1000e_set_fc_watermarks(hw);
3338 }
3339
3340 /**
3341  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3342  *  @hw: pointer to the HW structure
3343  *
3344  *  Configures the kumeran interface to the PHY to wait the appropriate time
3345  *  when polling the PHY, then call the generic setup_copper_link to finish
3346  *  configuring the copper link.
3347  **/
3348 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3349 {
3350         u32 ctrl;
3351         s32 ret_val;
3352         u16 reg_data;
3353
3354         ctrl = er32(CTRL);
3355         ctrl |= E1000_CTRL_SLU;
3356         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3357         ew32(CTRL, ctrl);
3358
3359         /*
3360          * Set the mac to wait the maximum time between each iteration
3361          * and increase the max iterations when polling the phy;
3362          * this fixes erroneous timeouts at 10Mbps.
3363          */
3364         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3365         if (ret_val)
3366                 return ret_val;
3367         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3368                                        &reg_data);
3369         if (ret_val)
3370                 return ret_val;
3371         reg_data |= 0x3F;
3372         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3373                                         reg_data);
3374         if (ret_val)
3375                 return ret_val;
3376
3377         switch (hw->phy.type) {
3378         case e1000_phy_igp_3:
3379                 ret_val = e1000e_copper_link_setup_igp(hw);
3380                 if (ret_val)
3381                         return ret_val;
3382                 break;
3383         case e1000_phy_bm:
3384         case e1000_phy_82578:
3385                 ret_val = e1000e_copper_link_setup_m88(hw);
3386                 if (ret_val)
3387                         return ret_val;
3388                 break;
3389         case e1000_phy_82577:
3390         case e1000_phy_82579:
3391                 ret_val = e1000_copper_link_setup_82577(hw);
3392                 if (ret_val)
3393                         return ret_val;
3394                 break;
3395         case e1000_phy_ife:
3396                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3397                 if (ret_val)
3398                         return ret_val;
3399
3400                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3401
3402                 switch (hw->phy.mdix) {
3403                 case 1:
3404                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3405                         break;
3406                 case 2:
3407                         reg_data |= IFE_PMC_FORCE_MDIX;
3408                         break;
3409                 case 0:
3410                 default:
3411                         reg_data |= IFE_PMC_AUTO_MDIX;
3412                         break;
3413                 }
3414                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3415                 if (ret_val)
3416                         return ret_val;
3417                 break;
3418         default:
3419                 break;
3420         }
3421         return e1000e_setup_copper_link(hw);
3422 }
3423
3424 /**
3425  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3426  *  @hw: pointer to the HW structure
3427  *  @speed: pointer to store current link speed
3428  *  @duplex: pointer to store the current link duplex
3429  *
3430  *  Calls the generic get_speed_and_duplex to retrieve the current link
3431  *  information and then calls the Kumeran lock loss workaround for links at
3432  *  gigabit speeds.
3433  **/
3434 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3435                                           u16 *duplex)
3436 {
3437         s32 ret_val;
3438
3439         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3440         if (ret_val)
3441                 return ret_val;
3442
3443         if ((hw->mac.type == e1000_ich8lan) &&
3444             (hw->phy.type == e1000_phy_igp_3) &&
3445             (*speed == SPEED_1000)) {
3446                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3447         }
3448
3449         return ret_val;
3450 }
3451
3452 /**
3453  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3454  *  @hw: pointer to the HW structure
3455  *
3456  *  Work-around for 82566 Kumeran PCS lock loss:
3457  *  On link status change (i.e. PCI reset, speed change) and link is up and
3458  *  speed is gigabit-
3459  *    0) if workaround is optionally disabled do nothing
3460  *    1) wait 1ms for Kumeran link to come up
3461  *    2) check Kumeran Diagnostic register PCS lock loss bit
3462  *    3) if not set the link is locked (all is good), otherwise...
3463  *    4) reset the PHY
3464  *    5) repeat up to 10 times
3465  *  Note: this is only called for IGP3 copper when speed is 1gb.
3466  **/
3467 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3468 {
3469         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3470         u32 phy_ctrl;
3471         s32 ret_val;
3472         u16 i, data;
3473         bool link;
3474
3475         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3476                 return 0;
3477
3478         /*
3479          * Make sure link is up before proceeding.  If not just return.
3480          * Attempting this while link is negotiating fouled up link
3481          * stability
3482          */
3483         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3484         if (!link)
3485                 return 0;
3486
3487         for (i = 0; i < 10; i++) {
3488                 /* read once to clear */
3489                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3490                 if (ret_val)
3491                         return ret_val;
3492                 /* and again to get new status */
3493                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3494                 if (ret_val)
3495                         return ret_val;
3496
3497                 /* check for PCS lock */
3498                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3499                         return 0;
3500
3501                 /* Issue PHY reset */
3502                 e1000_phy_hw_reset(hw);
3503                 mdelay(5);
3504         }
3505         /* Disable GigE link negotiation */
3506         phy_ctrl = er32(PHY_CTRL);
3507         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3508                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3509         ew32(PHY_CTRL, phy_ctrl);
3510
3511         /*
3512          * Call gig speed drop workaround on Gig disable before accessing
3513          * any PHY registers
3514          */
3515         e1000e_gig_downshift_workaround_ich8lan(hw);
3516
3517         /* unable to acquire PCS lock */
3518         return -E1000_ERR_PHY;
3519 }
3520
3521 /**
3522  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3523  *  @hw: pointer to the HW structure
3524  *  @state: boolean value used to set the current Kumeran workaround state
3525  *
3526  *  If ICH8, set the current Kumeran workaround state (enabled - true
3527  *  /disabled - false).
3528  **/
3529 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3530                                                  bool state)
3531 {
3532         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3533
3534         if (hw->mac.type != e1000_ich8lan) {
3535                 e_dbg("Workaround applies to ICH8 only.\n");
3536                 return;
3537         }
3538
3539         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3540 }
3541
3542 /**
3543  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3544  *  @hw: pointer to the HW structure
3545  *
3546  *  Workaround for 82566 power-down on D3 entry:
3547  *    1) disable gigabit link
3548  *    2) write VR power-down enable
3549  *    3) read it back
3550  *  Continue if successful, else issue LCD reset and repeat
3551  **/
3552 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3553 {
3554         u32 reg;
3555         u16 data;
3556         u8  retry = 0;
3557
3558         if (hw->phy.type != e1000_phy_igp_3)
3559                 return;
3560
3561         /* Try the workaround twice (if needed) */
3562         do {
3563                 /* Disable link */
3564                 reg = er32(PHY_CTRL);
3565                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3566                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3567                 ew32(PHY_CTRL, reg);
3568
3569                 /*
3570                  * Call gig speed drop workaround on Gig disable before
3571                  * accessing any PHY registers
3572                  */
3573                 if (hw->mac.type == e1000_ich8lan)
3574                         e1000e_gig_downshift_workaround_ich8lan(hw);
3575
3576                 /* Write VR power-down enable */
3577                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3578                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3579                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3580
3581                 /* Read it back and test */
3582                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3583                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3584                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3585                         break;
3586
3587                 /* Issue PHY reset and repeat at most one more time */
3588                 reg = er32(CTRL);
3589                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3590                 retry++;
3591         } while (retry);
3592 }
3593
3594 /**
3595  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3596  *  @hw: pointer to the HW structure
3597  *
3598  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3599  *  LPLU, Gig disable, MDIC PHY reset):
3600  *    1) Set Kumeran Near-end loopback
3601  *    2) Clear Kumeran Near-end loopback
3602  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3603  **/
3604 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3605 {
3606         s32 ret_val;
3607         u16 reg_data;
3608
3609         if ((hw->mac.type != e1000_ich8lan) ||
3610             (hw->phy.type != e1000_phy_igp_3))
3611                 return;
3612
3613         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3614                                       &reg_data);
3615         if (ret_val)
3616                 return;
3617         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3618         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3619                                        reg_data);
3620         if (ret_val)
3621                 return;
3622         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3623         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3624                                        reg_data);
3625 }
3626
3627 /**
3628  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3629  *  @hw: pointer to the HW structure
3630  *
3631  *  During S0 to Sx transition, it is possible the link remains at gig
3632  *  instead of negotiating to a lower speed.  Before going to Sx, set
3633  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3634  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3635  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3636  **/
3637 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3638 {
3639         u32 phy_ctrl;
3640         s32 ret_val;
3641
3642         phy_ctrl = er32(PHY_CTRL);
3643         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3644         ew32(PHY_CTRL, phy_ctrl);
3645
3646         if (hw->mac.type >= e1000_pchlan) {
3647                 e1000_oem_bits_config_ich8lan(hw, false);
3648                 ret_val = hw->phy.ops.acquire(hw);
3649                 if (ret_val)
3650                         return;
3651                 e1000_write_smbus_addr(hw);
3652                 hw->phy.ops.release(hw);
3653         }
3654 }
3655
3656 /**
3657  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3658  *  @hw: pointer to the HW structure
3659  *
3660  *  During Sx to S0 transitions on non-managed devices or managed devices
3661  *  on which PHY resets are not blocked, if the PHY registers cannot be
3662  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3663  *  the PHY.
3664  **/
3665 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3666 {
3667         u32 fwsm;
3668
3669         if (hw->mac.type != e1000_pch2lan)
3670                 return;
3671
3672         fwsm = er32(FWSM);
3673         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3674                 u16 phy_id1, phy_id2;
3675                 s32 ret_val;
3676
3677                 ret_val = hw->phy.ops.acquire(hw);
3678                 if (ret_val) {
3679                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3680                         return;
3681                 }
3682
3683                 /* Test access to the PHY registers by reading the ID regs */
3684                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3685                 if (ret_val)
3686                         goto release;
3687                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3688                 if (ret_val)
3689                         goto release;
3690
3691                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3692                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3693                         goto release;
3694
3695                 e1000_toggle_lanphypc_value_ich8lan(hw);
3696
3697                 hw->phy.ops.release(hw);
3698                 msleep(50);
3699                 e1000_phy_hw_reset(hw);
3700                 msleep(50);
3701                 return;
3702         }
3703
3704 release:
3705         hw->phy.ops.release(hw);
3706
3707         return;
3708 }
3709
3710 /**
3711  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3712  *  @hw: pointer to the HW structure
3713  *
3714  *  Return the LED back to the default configuration.
3715  **/
3716 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3717 {
3718         if (hw->phy.type == e1000_phy_ife)
3719                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3720
3721         ew32(LEDCTL, hw->mac.ledctl_default);
3722         return 0;
3723 }
3724
3725 /**
3726  *  e1000_led_on_ich8lan - Turn LEDs on
3727  *  @hw: pointer to the HW structure
3728  *
3729  *  Turn on the LEDs.
3730  **/
3731 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3732 {
3733         if (hw->phy.type == e1000_phy_ife)
3734                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3735                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3736
3737         ew32(LEDCTL, hw->mac.ledctl_mode2);
3738         return 0;
3739 }
3740
3741 /**
3742  *  e1000_led_off_ich8lan - Turn LEDs off
3743  *  @hw: pointer to the HW structure
3744  *
3745  *  Turn off the LEDs.
3746  **/
3747 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3748 {
3749         if (hw->phy.type == e1000_phy_ife)
3750                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3751                                 (IFE_PSCL_PROBE_MODE |
3752                                  IFE_PSCL_PROBE_LEDS_OFF));
3753
3754         ew32(LEDCTL, hw->mac.ledctl_mode1);
3755         return 0;
3756 }
3757
3758 /**
3759  *  e1000_setup_led_pchlan - Configures SW controllable LED
3760  *  @hw: pointer to the HW structure
3761  *
3762  *  This prepares the SW controllable LED for use.
3763  **/
3764 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3765 {
3766         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3767 }
3768
3769 /**
3770  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3771  *  @hw: pointer to the HW structure
3772  *
3773  *  Return the LED back to the default configuration.
3774  **/
3775 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3776 {
3777         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3778 }
3779
3780 /**
3781  *  e1000_led_on_pchlan - Turn LEDs on
3782  *  @hw: pointer to the HW structure
3783  *
3784  *  Turn on the LEDs.
3785  **/
3786 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3787 {
3788         u16 data = (u16)hw->mac.ledctl_mode2;
3789         u32 i, led;
3790
3791         /*
3792          * If no link, then turn LED on by setting the invert bit
3793          * for each LED that's mode is "link_up" in ledctl_mode2.
3794          */
3795         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3796                 for (i = 0; i < 3; i++) {
3797                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3798                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3799                             E1000_LEDCTL_MODE_LINK_UP)
3800                                 continue;
3801                         if (led & E1000_PHY_LED0_IVRT)
3802                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3803                         else
3804                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3805                 }
3806         }
3807
3808         return e1e_wphy(hw, HV_LED_CONFIG, data);
3809 }
3810
3811 /**
3812  *  e1000_led_off_pchlan - Turn LEDs off
3813  *  @hw: pointer to the HW structure
3814  *
3815  *  Turn off the LEDs.
3816  **/
3817 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3818 {
3819         u16 data = (u16)hw->mac.ledctl_mode1;
3820         u32 i, led;
3821
3822         /*
3823          * If no link, then turn LED off by clearing the invert bit
3824          * for each LED that's mode is "link_up" in ledctl_mode1.
3825          */
3826         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3827                 for (i = 0; i < 3; i++) {
3828                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3829                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3830                             E1000_LEDCTL_MODE_LINK_UP)
3831                                 continue;
3832                         if (led & E1000_PHY_LED0_IVRT)
3833                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3834                         else
3835                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3836                 }
3837         }
3838
3839         return e1e_wphy(hw, HV_LED_CONFIG, data);
3840 }
3841
3842 /**
3843  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3844  *  @hw: pointer to the HW structure
3845  *
3846  *  Read appropriate register for the config done bit for completion status
3847  *  and configure the PHY through s/w for EEPROM-less parts.
3848  *
3849  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3850  *  config done bit, so only an error is logged and continues.  If we were
3851  *  to return with error, EEPROM-less silicon would not be able to be reset
3852  *  or change link.
3853  **/
3854 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3855 {
3856         s32 ret_val = 0;
3857         u32 bank = 0;
3858         u32 status;
3859
3860         e1000e_get_cfg_done(hw);
3861
3862         /* Wait for indication from h/w that it has completed basic config */
3863         if (hw->mac.type >= e1000_ich10lan) {
3864                 e1000_lan_init_done_ich8lan(hw);
3865         } else {
3866                 ret_val = e1000e_get_auto_rd_done(hw);
3867                 if (ret_val) {
3868                         /*
3869                          * When auto config read does not complete, do not
3870                          * return with an error. This can happen in situations
3871                          * where there is no eeprom and prevents getting link.
3872                          */
3873                         e_dbg("Auto Read Done did not complete\n");
3874                         ret_val = 0;
3875                 }
3876         }
3877
3878         /* Clear PHY Reset Asserted bit */
3879         status = er32(STATUS);
3880         if (status & E1000_STATUS_PHYRA)
3881                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3882         else
3883                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3884
3885         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3886         if (hw->mac.type <= e1000_ich9lan) {
3887                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3888                     (hw->phy.type == e1000_phy_igp_3)) {
3889                         e1000e_phy_init_script_igp3(hw);
3890                 }
3891         } else {
3892                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3893                         /* Maybe we should do a basic PHY config */
3894                         e_dbg("EEPROM not present\n");
3895                         ret_val = -E1000_ERR_CONFIG;
3896                 }
3897         }
3898
3899         return ret_val;
3900 }
3901
3902 /**
3903  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3904  * @hw: pointer to the HW structure
3905  *
3906  * In the case of a PHY power down to save power, or to turn off link during a
3907  * driver unload, or wake on lan is not enabled, remove the link.
3908  **/
3909 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3910 {
3911         /* If the management interface is not enabled, then power down */
3912         if (!(hw->mac.ops.check_mng_mode(hw) ||
3913               hw->phy.ops.check_reset_block(hw)))
3914                 e1000_power_down_phy_copper(hw);
3915 }
3916
3917 /**
3918  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3919  *  @hw: pointer to the HW structure
3920  *
3921  *  Clears hardware counters specific to the silicon family and calls
3922  *  clear_hw_cntrs_generic to clear all general purpose counters.
3923  **/
3924 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3925 {
3926         u16 phy_data;
3927         s32 ret_val;
3928
3929         e1000e_clear_hw_cntrs_base(hw);
3930
3931         er32(ALGNERRC);
3932         er32(RXERRC);
3933         er32(TNCRS);
3934         er32(CEXTERR);
3935         er32(TSCTC);
3936         er32(TSCTFC);
3937
3938         er32(MGTPRC);
3939         er32(MGTPDC);
3940         er32(MGTPTC);
3941
3942         er32(IAC);
3943         er32(ICRXOC);
3944
3945         /* Clear PHY statistics registers */
3946         if ((hw->phy.type == e1000_phy_82578) ||
3947             (hw->phy.type == e1000_phy_82579) ||
3948             (hw->phy.type == e1000_phy_82577)) {
3949                 ret_val = hw->phy.ops.acquire(hw);
3950                 if (ret_val)
3951                         return;
3952                 ret_val = hw->phy.ops.set_page(hw,
3953                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
3954                 if (ret_val)
3955                         goto release;
3956                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
3957                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
3958                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
3959                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
3960                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
3961                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
3962                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
3963                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
3964                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
3965                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
3966                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
3967                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
3968                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
3969                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
3970 release:
3971                 hw->phy.ops.release(hw);
3972         }
3973 }
3974
3975 static struct e1000_mac_operations ich8_mac_ops = {
3976         .id_led_init            = e1000e_id_led_init,
3977         /* check_mng_mode dependent on mac type */
3978         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3979         /* cleanup_led dependent on mac type */
3980         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3981         .get_bus_info           = e1000_get_bus_info_ich8lan,
3982         .set_lan_id             = e1000_set_lan_id_single_port,
3983         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3984         /* led_on dependent on mac type */
3985         /* led_off dependent on mac type */
3986         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3987         .reset_hw               = e1000_reset_hw_ich8lan,
3988         .init_hw                = e1000_init_hw_ich8lan,
3989         .setup_link             = e1000_setup_link_ich8lan,
3990         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3991         /* id_led_init dependent on mac type */
3992 };
3993
3994 static struct e1000_phy_operations ich8_phy_ops = {
3995         .acquire                = e1000_acquire_swflag_ich8lan,
3996         .check_reset_block      = e1000_check_reset_block_ich8lan,
3997         .commit                 = NULL,
3998         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3999         .get_cable_length       = e1000e_get_cable_length_igp_2,
4000         .read_reg               = e1000e_read_phy_reg_igp,
4001         .release                = e1000_release_swflag_ich8lan,
4002         .reset                  = e1000_phy_hw_reset_ich8lan,
4003         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4004         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4005         .write_reg              = e1000e_write_phy_reg_igp,
4006 };
4007
4008 static struct e1000_nvm_operations ich8_nvm_ops = {
4009         .acquire                = e1000_acquire_nvm_ich8lan,
4010         .read                   = e1000_read_nvm_ich8lan,
4011         .release                = e1000_release_nvm_ich8lan,
4012         .update                 = e1000_update_nvm_checksum_ich8lan,
4013         .valid_led_default      = e1000_valid_led_default_ich8lan,
4014         .validate               = e1000_validate_nvm_checksum_ich8lan,
4015         .write                  = e1000_write_nvm_ich8lan,
4016 };
4017
4018 struct e1000_info e1000_ich8_info = {
4019         .mac                    = e1000_ich8lan,
4020         .flags                  = FLAG_HAS_WOL
4021                                   | FLAG_IS_ICH
4022                                   | FLAG_RX_CSUM_ENABLED
4023                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4024                                   | FLAG_HAS_AMT
4025                                   | FLAG_HAS_FLASH
4026                                   | FLAG_APME_IN_WUC,
4027         .pba                    = 8,
4028         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4029         .get_variants           = e1000_get_variants_ich8lan,
4030         .mac_ops                = &ich8_mac_ops,
4031         .phy_ops                = &ich8_phy_ops,
4032         .nvm_ops                = &ich8_nvm_ops,
4033 };
4034
4035 struct e1000_info e1000_ich9_info = {
4036         .mac                    = e1000_ich9lan,
4037         .flags                  = FLAG_HAS_JUMBO_FRAMES
4038                                   | FLAG_IS_ICH
4039                                   | FLAG_HAS_WOL
4040                                   | FLAG_RX_CSUM_ENABLED
4041                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4042                                   | FLAG_HAS_AMT
4043                                   | FLAG_HAS_ERT
4044                                   | FLAG_HAS_FLASH
4045                                   | FLAG_APME_IN_WUC,
4046         .pba                    = 10,
4047         .max_hw_frame_size      = DEFAULT_JUMBO,
4048         .get_variants           = e1000_get_variants_ich8lan,
4049         .mac_ops                = &ich8_mac_ops,
4050         .phy_ops                = &ich8_phy_ops,
4051         .nvm_ops                = &ich8_nvm_ops,
4052 };
4053
4054 struct e1000_info e1000_ich10_info = {
4055         .mac                    = e1000_ich10lan,
4056         .flags                  = FLAG_HAS_JUMBO_FRAMES
4057                                   | FLAG_IS_ICH
4058                                   | FLAG_HAS_WOL
4059                                   | FLAG_RX_CSUM_ENABLED
4060                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4061                                   | FLAG_HAS_AMT
4062                                   | FLAG_HAS_ERT
4063                                   | FLAG_HAS_FLASH
4064                                   | FLAG_APME_IN_WUC,
4065         .pba                    = 10,
4066         .max_hw_frame_size      = DEFAULT_JUMBO,
4067         .get_variants           = e1000_get_variants_ich8lan,
4068         .mac_ops                = &ich8_mac_ops,
4069         .phy_ops                = &ich8_phy_ops,
4070         .nvm_ops                = &ich8_nvm_ops,
4071 };
4072
4073 struct e1000_info e1000_pch_info = {
4074         .mac                    = e1000_pchlan,
4075         .flags                  = FLAG_IS_ICH
4076                                   | FLAG_HAS_WOL
4077                                   | FLAG_RX_CSUM_ENABLED
4078                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4079                                   | FLAG_HAS_AMT
4080                                   | FLAG_HAS_FLASH
4081                                   | FLAG_HAS_JUMBO_FRAMES
4082                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4083                                   | FLAG_APME_IN_WUC,
4084         .flags2                 = FLAG2_HAS_PHY_STATS,
4085         .pba                    = 26,
4086         .max_hw_frame_size      = 4096,
4087         .get_variants           = e1000_get_variants_ich8lan,
4088         .mac_ops                = &ich8_mac_ops,
4089         .phy_ops                = &ich8_phy_ops,
4090         .nvm_ops                = &ich8_nvm_ops,
4091 };
4092
4093 struct e1000_info e1000_pch2_info = {
4094         .mac                    = e1000_pch2lan,
4095         .flags                  = FLAG_IS_ICH
4096                                   | FLAG_HAS_WOL
4097                                   | FLAG_RX_CSUM_ENABLED
4098                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4099                                   | FLAG_HAS_AMT
4100                                   | FLAG_HAS_FLASH
4101                                   | FLAG_HAS_JUMBO_FRAMES
4102                                   | FLAG_APME_IN_WUC,
4103         .flags2                 = FLAG2_HAS_PHY_STATS
4104                                   | FLAG2_HAS_EEE,
4105         .pba                    = 26,
4106         .max_hw_frame_size      = DEFAULT_JUMBO,
4107         .get_variants           = e1000_get_variants_ich8lan,
4108         .mac_ops                = &ich8_mac_ops,
4109         .phy_ops                = &ich8_phy_ops,
4110         .nvm_ops                = &ich8_nvm_ops,
4111 };