drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148
 149 /* Strapping Option Register - RO */
 150 #define E1000_STRAP                     0x0000C
 151 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 152 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 153
 154 /* OEM Bits Phy Register */
 155 #define HV_OEM_BITS            PHY_REG(768, 25)
 156 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 157 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 158 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 159
 160 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 161 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 162
 163 /* KMRN Mode Control */
 164 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 165 #define HV_KMRN_MDIO_SLOW      0x0400
 166
 167 /* KMRN FIFO Control and Status */
 168 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 169 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 170 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 171
 172 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 173 /* Offset 04h HSFSTS */
 174 union ich8_hws_flash_status {
 175         struct ich8_hsfsts {
 176                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 177                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 178                 u16 dael       :1; /* bit 2 Direct Access error Log */
 179                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 180                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 181                 u16 reserved1  :2; /* bit 13:6 Reserved */
 182                 u16 reserved2  :6; /* bit 13:6 Reserved */
 183                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 184                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 185         } hsf_status;
 186         u16 regval;
 187 };
 188
 189 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 190 /* Offset 06h FLCTL */
 191 union ich8_hws_flash_ctrl {
 192         struct ich8_hsflctl {
 193                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 194                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 195                 u16 reserved   :5;   /* 7:3 Reserved  */
 196                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 197                 u16 flockdn    :6;   /* 15:10 Reserved */
 198         } hsf_ctrl;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Region Access Permissions */
 203 union ich8_hws_flash_regacc {
 204         struct ich8_flracc {
 205                 u32 grra      :8; /* 0:7 GbE region Read Access */
 206                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 207                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 208                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 209         } hsf_flregacc;
 210         u16 regval;
 211 };
 212
 213 /* ICH Flash Protected Region */
 214 union ich8_flash_protected_range {
 215         struct ich8_pr {
 216                 u32 base:13;     /* 0:12 Protected Range Base */
 217                 u32 reserved1:2; /* 13:14 Reserved */
 218                 u32 rpe:1;       /* 15 Read Protection Enable */
 219                 u32 limit:13;    /* 16:28 Protected Range Limit */
 220                 u32 reserved2:2; /* 29:30 Reserved */
 221                 u32 wpe:1;       /* 31 Write Protection Enable */
 222         } range;
 223         u32 regval;
 224 };
 225
 226 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 227 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 228 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 230 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 231                                                 u32 offset, u8 byte);
 232 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 233                                          u8 *data);
 234 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u16 *data);
 236 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u8 size, u16 *data);
 238 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 239 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 240 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 246 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 250 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 251 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 252 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 253 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 254 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 255 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 256 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 257 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 258
 259 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 260 {
 261         return readw(hw->flash_address + reg);
 262 }
 263
 264 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 265 {
 266         return readl(hw->flash_address + reg);
 267 }
 268
 269 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 270 {
 271         writew(val, hw->flash_address + reg);
 272 }
 273
 274 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 275 {
 276         writel(val, hw->flash_address + reg);
 277 }
 278
 279 #define er16flash(reg)          __er16flash(hw, (reg))
 280 #define er32flash(reg)          __er32flash(hw, (reg))
 281 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 282 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 283
 284 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 285 {
 286         u32 ctrl;
 287
 288         ctrl = er32(CTRL);
 289         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 290         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 291         ew32(CTRL, ctrl);
 292         e1e_flush();
 293         udelay(10);
 294         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295         ew32(CTRL, ctrl);
 296 }
 297
 298 /**
 299  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Initialize family-specific PHY parameters and function pointers.
 303  **/
 304 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 305 {
 306         struct e1000_phy_info *phy = &hw->phy;
 307         u32 fwsm;
 308         s32 ret_val = 0;
 309
 310         phy->addr                     = 1;
 311         phy->reset_delay_us           = 100;
 312
 313         phy->ops.set_page             = e1000_set_page_igp;
 314         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 315         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 316         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 317         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 318         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 320         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 321         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 322         phy->ops.power_up             = e1000_power_up_phy_copper;
 323         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 324         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 325
 326         /*
 327          * The MAC-PHY interconnect may still be in SMBus mode
 328          * after Sx->S0.  If the manageability engine (ME) is
 329          * disabled, then toggle the LANPHYPC Value bit to force
 330          * the interconnect to PCIe mode.
 331          */
 332         fwsm = er32(FWSM);
 333         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 334                 e1000_toggle_lanphypc_value_ich8lan(hw);
 335                 msleep(50);
 336
 337                 /*
 338                  * Gate automatic PHY configuration by hardware on
 339                  * non-managed 82579
 340                  */
 341                 if (hw->mac.type == e1000_pch2lan)
 342                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 343         }
 344
 345         /*
 346          * Reset the PHY before any access to it.  Doing so, ensures that
 347          * the PHY is in a known good state before we read/write PHY registers.
 348          * The generic reset is sufficient here, because we haven't determined
 349          * the PHY type yet.
 350          */
 351         ret_val = e1000e_phy_hw_reset_generic(hw);
 352         if (ret_val)
 353                 goto out;
 354
 355         /* Ungate automatic PHY configuration on non-managed 82579 */
 356         if ((hw->mac.type == e1000_pch2lan) &&
 357             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 358                 usleep_range(10000, 20000);
 359                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 360         }
 361
 362         phy->id = e1000_phy_unknown;
 363         switch (hw->mac.type) {
 364         default:
 365                 ret_val = e1000e_get_phy_id(hw);
 366                 if (ret_val)
 367                         goto out;
 368                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 369                         break;
 370                 /* fall-through */
 371         case e1000_pch2lan:
 372                 /*
 373                  * In case the PHY needs to be in mdio slow mode,
 374                  * set slow mode and try to get the PHY id again.
 375                  */
 376                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 377                 if (ret_val)
 378                         goto out;
 379                 ret_val = e1000e_get_phy_id(hw);
 380                 if (ret_val)
 381                         goto out;
 382                 break;
 383         }
 384         phy->type = e1000e_get_phy_type_from_id(phy->id);
 385
 386         switch (phy->type) {
 387         case e1000_phy_82577:
 388         case e1000_phy_82579:
 389                 phy->ops.check_polarity = e1000_check_polarity_82577;
 390                 phy->ops.force_speed_duplex =
 391                     e1000_phy_force_speed_duplex_82577;
 392                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 393                 phy->ops.get_info = e1000_get_phy_info_82577;
 394                 phy->ops.commit = e1000e_phy_sw_reset;
 395                 break;
 396         case e1000_phy_82578:
 397                 phy->ops.check_polarity = e1000_check_polarity_m88;
 398                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 399                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 400                 phy->ops.get_info = e1000e_get_phy_info_m88;
 401                 break;
 402         default:
 403                 ret_val = -E1000_ERR_PHY;
 404                 break;
 405         }
 406
 407 out:
 408         return ret_val;
 409 }
 410
 411 /**
 412  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific PHY parameters and function pointers.
 416  **/
 417 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 418 {
 419         struct e1000_phy_info *phy = &hw->phy;
 420         s32 ret_val;
 421         u16 i = 0;
 422
 423         phy->addr                       = 1;
 424         phy->reset_delay_us             = 100;
 425
 426         phy->ops.power_up               = e1000_power_up_phy_copper;
 427         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 428
 429         /*
 430          * We may need to do this twice - once for IGP and if that fails,
 431          * we'll set BM func pointers and try again
 432          */
 433         ret_val = e1000e_determine_phy_address(hw);
 434         if (ret_val) {
 435                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 436                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 437                 ret_val = e1000e_determine_phy_address(hw);
 438                 if (ret_val) {
 439                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 440                         return ret_val;
 441                 }
 442         }
 443
 444         phy->id = 0;
 445         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 446                (i++ < 100)) {
 447                 usleep_range(1000, 2000);
 448                 ret_val = e1000e_get_phy_id(hw);
 449                 if (ret_val)
 450                         return ret_val;
 451         }
 452
 453         /* Verify phy id */
 454         switch (phy->id) {
 455         case IGP03E1000_E_PHY_ID:
 456                 phy->type = e1000_phy_igp_3;
 457                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 459                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 460                 phy->ops.get_info = e1000e_get_phy_info_igp;
 461                 phy->ops.check_polarity = e1000_check_polarity_igp;
 462                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 463                 break;
 464         case IFE_E_PHY_ID:
 465         case IFE_PLUS_E_PHY_ID:
 466         case IFE_C_E_PHY_ID:
 467                 phy->type = e1000_phy_ife;
 468                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 469                 phy->ops.get_info = e1000_get_phy_info_ife;
 470                 phy->ops.check_polarity = e1000_check_polarity_ife;
 471                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 472                 break;
 473         case BME1000_E_PHY_ID:
 474                 phy->type = e1000_phy_bm;
 475                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 476                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 477                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 478                 phy->ops.commit = e1000e_phy_sw_reset;
 479                 phy->ops.get_info = e1000e_get_phy_info_m88;
 480                 phy->ops.check_polarity = e1000_check_polarity_m88;
 481                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 482                 break;
 483         default:
 484                 return -E1000_ERR_PHY;
 485                 break;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Initialize family-specific NVM parameters and function
 496  *  pointers.
 497  **/
 498 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 502         u32 gfpreg, sector_base_addr, sector_end_addr;
 503         u16 i;
 504
 505         /* Can't read flash registers if the register set isn't mapped. */
 506         if (!hw->flash_address) {
 507                 e_dbg("ERROR: Flash registers not mapped\n");
 508                 return -E1000_ERR_CONFIG;
 509         }
 510
 511         nvm->type = e1000_nvm_flash_sw;
 512
 513         gfpreg = er32flash(ICH_FLASH_GFPREG);
 514
 515         /*
 516          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 517          * Add 1 to sector_end_addr since this sector is included in
 518          * the overall size.
 519          */
 520         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 521         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 522
 523         /* flash_base_addr is byte-aligned */
 524         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 525
 526         /*
 527          * find total size of the NVM, then cut in half since the total
 528          * size represents two separate NVM banks.
 529          */
 530         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 531                                 << FLASH_SECTOR_ADDR_SHIFT;
 532         nvm->flash_bank_size /= 2;
 533         /* Adjust to word count */
 534         nvm->flash_bank_size /= sizeof(u16);
 535
 536         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 537
 538         /* Clear shadow ram */
 539         for (i = 0; i < nvm->word_size; i++) {
 540                 dev_spec->shadow_ram[i].modified = false;
 541                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 542         }
 543
 544         return 0;
 545 }
 546
 547 /**
 548  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 549  *  @hw: pointer to the HW structure
 550  *
 551  *  Initialize family-specific MAC parameters and function
 552  *  pointers.
 553  **/
 554 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 555 {
 556         struct e1000_hw *hw = &adapter->hw;
 557         struct e1000_mac_info *mac = &hw->mac;
 558
 559         /* Set media type function pointer */
 560         hw->phy.media_type = e1000_media_type_copper;
 561
 562         /* Set mta register count */
 563         mac->mta_reg_count = 32;
 564         /* Set rar entry count */
 565         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 566         if (mac->type == e1000_ich8lan)
 567                 mac->rar_entry_count--;
 568         /* FWSM register */
 569         mac->has_fwsm = true;
 570         /* ARC subsystem not supported */
 571         mac->arc_subsystem_valid = false;
 572         /* Adaptive IFS supported */
 573         mac->adaptive_ifs = true;
 574
 575         /* LED operations */
 576         switch (mac->type) {
 577         case e1000_ich8lan:
 578         case e1000_ich9lan:
 579         case e1000_ich10lan:
 580                 /* check management mode */
 581                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 582                 /* ID LED init */
 583                 mac->ops.id_led_init = e1000e_id_led_init;
 584                 /* blink LED */
 585                 mac->ops.blink_led = e1000e_blink_led_generic;
 586                 /* setup LED */
 587                 mac->ops.setup_led = e1000e_setup_led_generic;
 588                 /* cleanup LED */
 589                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 590                 /* turn on/off LED */
 591                 mac->ops.led_on = e1000_led_on_ich8lan;
 592                 mac->ops.led_off = e1000_led_off_ich8lan;
 593                 break;
 594         case e1000_pchlan:
 595         case e1000_pch2lan:
 596                 /* check management mode */
 597                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 598                 /* ID LED init */
 599                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 600                 /* setup LED */
 601                 mac->ops.setup_led = e1000_setup_led_pchlan;
 602                 /* cleanup LED */
 603                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 604                 /* turn on/off LED */
 605                 mac->ops.led_on = e1000_led_on_pchlan;
 606                 mac->ops.led_off = e1000_led_off_pchlan;
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         /* Enable PCS Lock-loss workaround for ICH8 */
 613         if (mac->type == e1000_ich8lan)
 614                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 615
 616         /* Gate automatic PHY configuration by hardware on managed 82579 */
 617         if ((mac->type == e1000_pch2lan) &&
 618             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 619                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 620
 621         return 0;
 622 }
 623
 624 /**
 625  *  e1000_set_eee_pchlan - Enable/disable EEE support
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 629  *  the LPI Control register will remain set only if/when link is up.
 630  **/
 631 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 632 {
 633         s32 ret_val = 0;
 634         u16 phy_reg;
 635
 636         if (hw->phy.type != e1000_phy_82579)
 637                 goto out;
 638
 639         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 640         if (ret_val)
 641                 goto out;
 642
 643         if (hw->dev_spec.ich8lan.eee_disable)
 644                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 645         else
 646                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 647
 648         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 655  *  @hw: pointer to the HW structure
 656  *
 657  *  Checks to see of the link status of the hardware has changed.  If a
 658  *  change in link status has been detected, then we read the PHY registers
 659  *  to get the current speed/duplex if link exists.
 660  **/
 661 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 662 {
 663         struct e1000_mac_info *mac = &hw->mac;
 664         s32 ret_val;
 665         bool link;
 666         u16 phy_reg;
 667
 668         /*
 669          * We only want to go out to the PHY registers to see if Auto-Neg
 670          * has completed and/or if our link status has changed.  The
 671          * get_link_status flag is set upon receiving a Link Status
 672          * Change or Rx Sequence Error interrupt.
 673          */
 674         if (!mac->get_link_status) {
 675                 ret_val = 0;
 676                 goto out;
 677         }
 678
 679         /*
 680          * First we want to see if the MII Status Register reports
 681          * link.  If so, then we want to get the current speed/duplex
 682          * of the PHY.
 683          */
 684         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 685         if (ret_val)
 686                 goto out;
 687
 688         if (hw->mac.type == e1000_pchlan) {
 689                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 690                 if (ret_val)
 691                         goto out;
 692         }
 693
 694         if (!link)
 695                 goto out; /* No link detected */
 696
 697         mac->get_link_status = false;
 698
 699         switch (hw->mac.type) {
 700         case e1000_pch2lan:
 701                 ret_val = e1000_k1_workaround_lv(hw);
 702                 if (ret_val)
 703                         goto out;
 704                 /* fall-thru */
 705         case e1000_pchlan:
 706                 if (hw->phy.type == e1000_phy_82578) {
 707                         ret_val = e1000_link_stall_workaround_hv(hw);
 708                         if (ret_val)
 709                                 goto out;
 710                 }
 711
 712                 /*
 713                  * Workaround for PCHx parts in half-duplex:
 714                  * Set the number of preambles removed from the packet
 715                  * when it is passed from the PHY to the MAC to prevent
 716                  * the MAC from misinterpreting the packet type.
 717                  */
 718                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 719                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 720
 721                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 722                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 723
 724                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 725                 break;
 726         default:
 727                 break;
 728         }
 729
 730         /*
 731          * Check if there was DownShift, must be checked
 732          * immediately after link-up
 733          */
 734         e1000e_check_downshift(hw);
 735
 736         /* Enable/Disable EEE after link up */
 737         ret_val = e1000_set_eee_pchlan(hw);
 738         if (ret_val)
 739                 goto out;
 740
 741         /*
 742          * If we are forcing speed/duplex, then we simply return since
 743          * we have already determined whether we have link or not.
 744          */
 745         if (!mac->autoneg) {
 746                 ret_val = -E1000_ERR_CONFIG;
 747                 goto out;
 748         }
 749
 750         /*
 751          * Auto-Neg is enabled.  Auto Speed Detection takes care
 752          * of MAC speed/duplex configuration.  So we only need to
 753          * configure Collision Distance in the MAC.
 754          */
 755         e1000e_config_collision_dist(hw);
 756
 757         /*
 758          * Configure Flow Control now that Auto-Neg has completed.
 759          * First, we need to restore the desired flow control
 760          * settings because we may have had to re-autoneg with a
 761          * different link partner.
 762          */
 763         ret_val = e1000e_config_fc_after_link_up(hw);
 764         if (ret_val)
 765                 e_dbg("Error configuring flow control\n");
 766
 767 out:
 768         return ret_val;
 769 }
 770
 771 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 772 {
 773         struct e1000_hw *hw = &adapter->hw;
 774         s32 rc;
 775
 776         rc = e1000_init_mac_params_ich8lan(adapter);
 777         if (rc)
 778                 return rc;
 779
 780         rc = e1000_init_nvm_params_ich8lan(hw);
 781         if (rc)
 782                 return rc;
 783
 784         switch (hw->mac.type) {
 785         case e1000_ich8lan:
 786         case e1000_ich9lan:
 787         case e1000_ich10lan:
 788                 rc = e1000_init_phy_params_ich8lan(hw);
 789                 break;
 790         case e1000_pchlan:
 791         case e1000_pch2lan:
 792                 rc = e1000_init_phy_params_pchlan(hw);
 793                 break;
 794         default:
 795                 break;
 796         }
 797         if (rc)
 798                 return rc;
 799
 800         /*
 801          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 802          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 803          */
 804         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 805             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 806              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 807                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 808                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 809
 810                 hw->mac.ops.blink_led = NULL;
 811         }
 812
 813         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 814             (adapter->hw.phy.type != e1000_phy_ife))
 815                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 816
 817         /* Enable workaround for 82579 w/ ME enabled */
 818         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 819             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 820                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 821
 822         /* Disable EEE by default until IEEE802.3az spec is finalized */
 823         if (adapter->flags2 & FLAG2_HAS_EEE)
 824                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 825
 826         return 0;
 827 }
 828
 829 static DEFINE_MUTEX(nvm_mutex);
 830
 831 /**
 832  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 833  *  @hw: pointer to the HW structure
 834  *
 835  *  Acquires the mutex for performing NVM operations.
 836  **/
 837 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 838 {
 839         mutex_lock(&nvm_mutex);
 840
 841         return 0;
 842 }
 843
 844 /**
 845  *  e1000_release_nvm_ich8lan - Release NVM mutex
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  Releases the mutex used while performing NVM operations.
 849  **/
 850 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 851 {
 852         mutex_unlock(&nvm_mutex);
 853 }
 854
 855 /**
 856  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 857  *  @hw: pointer to the HW structure
 858  *
 859  *  Acquires the software control flag for performing PHY and select
 860  *  MAC CSR accesses.
 861  **/
 862 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 863 {
 864         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 865         s32 ret_val = 0;
 866
 867         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 868                              &hw->adapter->state)) {
 869                 WARN(1, "e1000e: %s: contention for Phy access\n",
 870                      hw->adapter->netdev->name);
 871                 return -E1000_ERR_PHY;
 872         }
 873
 874         while (timeout) {
 875                 extcnf_ctrl = er32(EXTCNF_CTRL);
 876                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 877                         break;
 878
 879                 mdelay(1);
 880                 timeout--;
 881         }
 882
 883         if (!timeout) {
 884                 e_dbg("SW has already locked the resource.\n");
 885                 ret_val = -E1000_ERR_CONFIG;
 886                 goto out;
 887         }
 888
 889         timeout = SW_FLAG_TIMEOUT;
 890
 891         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 892         ew32(EXTCNF_CTRL, extcnf_ctrl);
 893
 894         while (timeout) {
 895                 extcnf_ctrl = er32(EXTCNF_CTRL);
 896                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 897                         break;
 898
 899                 mdelay(1);
 900                 timeout--;
 901         }
 902
 903         if (!timeout) {
 904                 e_dbg("Failed to acquire the semaphore, FW or HW has it: "
 905                       "FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 906                       er32(FWSM), extcnf_ctrl);
 907                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 908                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 909                 ret_val = -E1000_ERR_CONFIG;
 910                 goto out;
 911         }
 912
 913 out:
 914         if (ret_val)
 915                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 916
 917         return ret_val;
 918 }
 919
 920 /**
 921  *  e1000_release_swflag_ich8lan - Release software control flag
 922  *  @hw: pointer to the HW structure
 923  *
 924  *  Releases the software control flag for performing PHY and select
 925  *  MAC CSR accesses.
 926  **/
 927 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 928 {
 929         u32 extcnf_ctrl;
 930
 931         extcnf_ctrl = er32(EXTCNF_CTRL);
 932
 933         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 934                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 935                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 936         } else {
 937                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 938         }
 939
 940         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 941 }
 942
 943 /**
 944  *  e1000_check_mng_mode_ich8lan - Checks management mode
 945  *  @hw: pointer to the HW structure
 946  *
 947  *  This checks if the adapter has any manageability enabled.
 948  *  This is a function pointer entry point only called by read/write
 949  *  routines for the PHY and NVM parts.
 950  **/
 951 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 952 {
 953         u32 fwsm;
 954
 955         fwsm = er32(FWSM);
 956         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 957                ((fwsm & E1000_FWSM_MODE_MASK) ==
 958                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 959 }
 960
 961 /**
 962  *  e1000_check_mng_mode_pchlan - Checks management mode
 963  *  @hw: pointer to the HW structure
 964  *
 965  *  This checks if the adapter has iAMT enabled.
 966  *  This is a function pointer entry point only called by read/write
 967  *  routines for the PHY and NVM parts.
 968  **/
 969 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 970 {
 971         u32 fwsm;
 972
 973         fwsm = er32(FWSM);
 974         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 975                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 976 }
 977
 978 /**
 979  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 980  *  @hw: pointer to the HW structure
 981  *
 982  *  Checks if firmware is blocking the reset of the PHY.
 983  *  This is a function pointer entry point only called by
 984  *  reset routines.
 985  **/
 986 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 987 {
 988         u32 fwsm;
 989
 990         fwsm = er32(FWSM);
 991
 992         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 993 }
 994
 995 /**
 996  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 997  *  @hw: pointer to the HW structure
 998  *
 999  *  Assumes semaphore already acquired.
1000  *
1001  **/
1002 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1003 {
1004         u16 phy_data;
1005         u32 strap = er32(STRAP);
1006         s32 ret_val = 0;
1007
1008         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1009
1010         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1011         if (ret_val)
1012                 goto out;
1013
1014         phy_data &= ~HV_SMB_ADDR_MASK;
1015         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1016         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1017         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1018
1019 out:
1020         return ret_val;
1021 }
1022
1023 /**
1024  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1025  *  @hw:   pointer to the HW structure
1026  *
1027  *  SW should configure the LCD from the NVM extended configuration region
1028  *  as a workaround for certain parts.
1029  **/
1030 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1031 {
1032         struct e1000_phy_info *phy = &hw->phy;
1033         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1034         s32 ret_val = 0;
1035         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1036
1037         /*
1038          * Initialize the PHY from the NVM on ICH platforms.  This
1039          * is needed due to an issue where the NVM configuration is
1040          * not properly autoloaded after power transitions.
1041          * Therefore, after each PHY reset, we will load the
1042          * configuration data out of the NVM manually.
1043          */
1044         switch (hw->mac.type) {
1045         case e1000_ich8lan:
1046                 if (phy->type != e1000_phy_igp_3)
1047                         return ret_val;
1048
1049                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1050                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1051                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1052                         break;
1053                 }
1054                 /* Fall-thru */
1055         case e1000_pchlan:
1056         case e1000_pch2lan:
1057                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1058                 break;
1059         default:
1060                 return ret_val;
1061         }
1062
1063         ret_val = hw->phy.ops.acquire(hw);
1064         if (ret_val)
1065                 return ret_val;
1066
1067         data = er32(FEXTNVM);
1068         if (!(data & sw_cfg_mask))
1069                 goto out;
1070
1071         /*
1072          * Make sure HW does not configure LCD from PHY
1073          * extended configuration before SW configuration
1074          */
1075         data = er32(EXTCNF_CTRL);
1076         if (!(hw->mac.type == e1000_pch2lan)) {
1077                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1078                         goto out;
1079         }
1080
1081         cnf_size = er32(EXTCNF_SIZE);
1082         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1083         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1084         if (!cnf_size)
1085                 goto out;
1086
1087         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1088         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1089
1090         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1091             (hw->mac.type == e1000_pchlan)) ||
1092              (hw->mac.type == e1000_pch2lan)) {
1093                 /*
1094                  * HW configures the SMBus address and LEDs when the
1095                  * OEM and LCD Write Enable bits are set in the NVM.
1096                  * When both NVM bits are cleared, SW will configure
1097                  * them instead.
1098                  */
1099                 ret_val = e1000_write_smbus_addr(hw);
1100                 if (ret_val)
1101                         goto out;
1102
1103                 data = er32(LEDCTL);
1104                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1105                                                         (u16)data);
1106                 if (ret_val)
1107                         goto out;
1108         }
1109
1110         /* Configure LCD from extended configuration region. */
1111
1112         /* cnf_base_addr is in DWORD */
1113         word_addr = (u16)(cnf_base_addr << 1);
1114
1115         for (i = 0; i < cnf_size; i++) {
1116                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1117                                          &reg_data);
1118                 if (ret_val)
1119                         goto out;
1120
1121                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1122                                          1, &reg_addr);
1123                 if (ret_val)
1124                         goto out;
1125
1126                 /* Save off the PHY page for future writes. */
1127                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1128                         phy_page = reg_data;
1129                         continue;
1130                 }
1131
1132                 reg_addr &= PHY_REG_MASK;
1133                 reg_addr |= phy_page;
1134
1135                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1136                                                     reg_data);
1137                 if (ret_val)
1138                         goto out;
1139         }
1140
1141 out:
1142         hw->phy.ops.release(hw);
1143         return ret_val;
1144 }
1145
1146 /**
1147  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1148  *  @hw:   pointer to the HW structure
1149  *  @link: link up bool flag
1150  *
1151  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1152  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1153  *  If link is down, the function will restore the default K1 setting located
1154  *  in the NVM.
1155  **/
1156 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1157 {
1158         s32 ret_val = 0;
1159         u16 status_reg = 0;
1160         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1161
1162         if (hw->mac.type != e1000_pchlan)
1163                 goto out;
1164
1165         /* Wrap the whole flow with the sw flag */
1166         ret_val = hw->phy.ops.acquire(hw);
1167         if (ret_val)
1168                 goto out;
1169
1170         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1171         if (link) {
1172                 if (hw->phy.type == e1000_phy_82578) {
1173                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1174                                                                   &status_reg);
1175                         if (ret_val)
1176                                 goto release;
1177
1178                         status_reg &= BM_CS_STATUS_LINK_UP |
1179                                       BM_CS_STATUS_RESOLVED |
1180                                       BM_CS_STATUS_SPEED_MASK;
1181
1182                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1183                                            BM_CS_STATUS_RESOLVED |
1184                                            BM_CS_STATUS_SPEED_1000))
1185                                 k1_enable = false;
1186                 }
1187
1188                 if (hw->phy.type == e1000_phy_82577) {
1189                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1190                                                                   &status_reg);
1191                         if (ret_val)
1192                                 goto release;
1193
1194                         status_reg &= HV_M_STATUS_LINK_UP |
1195                                       HV_M_STATUS_AUTONEG_COMPLETE |
1196                                       HV_M_STATUS_SPEED_MASK;
1197
1198                         if (status_reg == (HV_M_STATUS_LINK_UP |
1199                                            HV_M_STATUS_AUTONEG_COMPLETE |
1200                                            HV_M_STATUS_SPEED_1000))
1201                                 k1_enable = false;
1202                 }
1203
1204                 /* Link stall fix for link up */
1205                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1206                                                            0x0100);
1207                 if (ret_val)
1208                         goto release;
1209
1210         } else {
1211                 /* Link stall fix for link down */
1212                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1213                                                            0x4100);
1214                 if (ret_val)
1215                         goto release;
1216         }
1217
1218         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1219
1220 release:
1221         hw->phy.ops.release(hw);
1222 out:
1223         return ret_val;
1224 }
1225
1226 /**
1227  *  e1000_configure_k1_ich8lan - Configure K1 power state
1228  *  @hw: pointer to the HW structure
1229  *  @enable: K1 state to configure
1230  *
1231  *  Configure the K1 power state based on the provided parameter.
1232  *  Assumes semaphore already acquired.
1233  *
1234  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1235  **/
1236 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1237 {
1238         s32 ret_val = 0;
1239         u32 ctrl_reg = 0;
1240         u32 ctrl_ext = 0;
1241         u32 reg = 0;
1242         u16 kmrn_reg = 0;
1243
1244         ret_val = e1000e_read_kmrn_reg_locked(hw,
1245                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1246                                              &kmrn_reg);
1247         if (ret_val)
1248                 goto out;
1249
1250         if (k1_enable)
1251                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1252         else
1253                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1254
1255         ret_val = e1000e_write_kmrn_reg_locked(hw,
1256                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1257                                               kmrn_reg);
1258         if (ret_val)
1259                 goto out;
1260
1261         udelay(20);
1262         ctrl_ext = er32(CTRL_EXT);
1263         ctrl_reg = er32(CTRL);
1264
1265         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1266         reg |= E1000_CTRL_FRCSPD;
1267         ew32(CTRL, reg);
1268
1269         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1270         e1e_flush();
1271         udelay(20);
1272         ew32(CTRL, ctrl_reg);
1273         ew32(CTRL_EXT, ctrl_ext);
1274         e1e_flush();
1275         udelay(20);
1276
1277 out:
1278         return ret_val;
1279 }
1280
1281 /**
1282  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1283  *  @hw:       pointer to the HW structure
1284  *  @d0_state: boolean if entering d0 or d3 device state
1285  *
1286  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1287  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1288  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1289  **/
1290 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1291 {
1292         s32 ret_val = 0;
1293         u32 mac_reg;
1294         u16 oem_reg;
1295
1296         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1297                 return ret_val;
1298
1299         ret_val = hw->phy.ops.acquire(hw);
1300         if (ret_val)
1301                 return ret_val;
1302
1303         if (!(hw->mac.type == e1000_pch2lan)) {
1304                 mac_reg = er32(EXTCNF_CTRL);
1305                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1306                         goto out;
1307         }
1308
1309         mac_reg = er32(FEXTNVM);
1310         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1311                 goto out;
1312
1313         mac_reg = er32(PHY_CTRL);
1314
1315         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1316         if (ret_val)
1317                 goto out;
1318
1319         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1320
1321         if (d0_state) {
1322                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1323                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1324
1325                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1326                         oem_reg |= HV_OEM_BITS_LPLU;
1327
1328                 /* Set Restart auto-neg to activate the bits */
1329                 if (!e1000_check_reset_block(hw))
1330                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1331         } else {
1332                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1333                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1334                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1335
1336                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1337                                E1000_PHY_CTRL_NOND0A_LPLU))
1338                         oem_reg |= HV_OEM_BITS_LPLU;
1339         }
1340
1341         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1342
1343 out:
1344         hw->phy.ops.release(hw);
1345
1346         return ret_val;
1347 }
1348
1349
1350 /**
1351  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1352  *  @hw:   pointer to the HW structure
1353  **/
1354 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1355 {
1356         s32 ret_val;
1357         u16 data;
1358
1359         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1360         if (ret_val)
1361                 return ret_val;
1362
1363         data |= HV_KMRN_MDIO_SLOW;
1364
1365         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1366
1367         return ret_val;
1368 }
1369
1370 /**
1371  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1372  *  done after every PHY reset.
1373  **/
1374 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1375 {
1376         s32 ret_val = 0;
1377         u16 phy_data;
1378
1379         if (hw->mac.type != e1000_pchlan)
1380                 return ret_val;
1381
1382         /* Set MDIO slow mode before any other MDIO access */
1383         if (hw->phy.type == e1000_phy_82577) {
1384                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1385                 if (ret_val)
1386                         goto out;
1387         }
1388
1389         if (((hw->phy.type == e1000_phy_82577) &&
1390              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1391             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1392                 /* Disable generation of early preamble */
1393                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1394                 if (ret_val)
1395                         return ret_val;
1396
1397                 /* Preamble tuning for SSC */
1398                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1399                 if (ret_val)
1400                         return ret_val;
1401         }
1402
1403         if (hw->phy.type == e1000_phy_82578) {
1404                 /*
1405                  * Return registers to default by doing a soft reset then
1406                  * writing 0x3140 to the control register.
1407                  */
1408                 if (hw->phy.revision < 2) {
1409                         e1000e_phy_sw_reset(hw);
1410                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1411                 }
1412         }
1413
1414         /* Select page 0 */
1415         ret_val = hw->phy.ops.acquire(hw);
1416         if (ret_val)
1417                 return ret_val;
1418
1419         hw->phy.addr = 1;
1420         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1421         hw->phy.ops.release(hw);
1422         if (ret_val)
1423                 goto out;
1424
1425         /*
1426          * Configure the K1 Si workaround during phy reset assuming there is
1427          * link so that it disables K1 if link is in 1Gbps.
1428          */
1429         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1430         if (ret_val)
1431                 goto out;
1432
1433         /* Workaround for link disconnects on a busy hub in half duplex */
1434         ret_val = hw->phy.ops.acquire(hw);
1435         if (ret_val)
1436                 goto out;
1437         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1438         if (ret_val)
1439                 goto release;
1440         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1441                                                phy_data & 0x00FF);
1442 release:
1443         hw->phy.ops.release(hw);
1444 out:
1445         return ret_val;
1446 }
1447
1448 /**
1449  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1450  *  @hw:   pointer to the HW structure
1451  **/
1452 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1453 {
1454         u32 mac_reg;
1455         u16 i, phy_reg = 0;
1456         s32 ret_val;
1457
1458         ret_val = hw->phy.ops.acquire(hw);
1459         if (ret_val)
1460                 return;
1461         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1462         if (ret_val)
1463                 goto release;
1464
1465         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1466         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1467                 mac_reg = er32(RAL(i));
1468                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1469                                            (u16)(mac_reg & 0xFFFF));
1470                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1471                                            (u16)((mac_reg >> 16) & 0xFFFF));
1472
1473                 mac_reg = er32(RAH(i));
1474                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1475                                            (u16)(mac_reg & 0xFFFF));
1476                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1477                                            (u16)((mac_reg & E1000_RAH_AV)
1478                                                  >> 16));
1479         }
1480
1481         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1482
1483 release:
1484         hw->phy.ops.release(hw);
1485 }
1486
1487 /**
1488  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1489  *  with 82579 PHY
1490  *  @hw: pointer to the HW structure
1491  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1492  **/
1493 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1494 {
1495         s32 ret_val = 0;
1496         u16 phy_reg, data;
1497         u32 mac_reg;
1498         u16 i;
1499
1500         if (hw->mac.type != e1000_pch2lan)
1501                 goto out;
1502
1503         /* disable Rx path while enabling/disabling workaround */
1504         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1505         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1506         if (ret_val)
1507                 goto out;
1508
1509         if (enable) {
1510                 /*
1511                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1512                  * SHRAL/H) and initial CRC values to the MAC
1513                  */
1514                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1515                         u8 mac_addr[ETH_ALEN] = {0};
1516                         u32 addr_high, addr_low;
1517
1518                         addr_high = er32(RAH(i));
1519                         if (!(addr_high & E1000_RAH_AV))
1520                                 continue;
1521                         addr_low = er32(RAL(i));
1522                         mac_addr[0] = (addr_low & 0xFF);
1523                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1524                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1525                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1526                         mac_addr[4] = (addr_high & 0xFF);
1527                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1528
1529                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1530                 }
1531
1532                 /* Write Rx addresses to the PHY */
1533                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1534
1535                 /* Enable jumbo frame workaround in the MAC */
1536                 mac_reg = er32(FFLT_DBG);
1537                 mac_reg &= ~(1 << 14);
1538                 mac_reg |= (7 << 15);
1539                 ew32(FFLT_DBG, mac_reg);
1540
1541                 mac_reg = er32(RCTL);
1542                 mac_reg |= E1000_RCTL_SECRC;
1543                 ew32(RCTL, mac_reg);
1544
1545                 ret_val = e1000e_read_kmrn_reg(hw,
1546                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1547                                                 &data);
1548                 if (ret_val)
1549                         goto out;
1550                 ret_val = e1000e_write_kmrn_reg(hw,
1551                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1552                                                 data | (1 << 0));
1553                 if (ret_val)
1554                         goto out;
1555                 ret_val = e1000e_read_kmrn_reg(hw,
1556                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1557                                                 &data);
1558                 if (ret_val)
1559                         goto out;
1560                 data &= ~(0xF << 8);
1561                 data |= (0xB << 8);
1562                 ret_val = e1000e_write_kmrn_reg(hw,
1563                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1564                                                 data);
1565                 if (ret_val)
1566                         goto out;
1567
1568                 /* Enable jumbo frame workaround in the PHY */
1569                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1570                 data &= ~(0x7F << 5);
1571                 data |= (0x37 << 5);
1572                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1573                 if (ret_val)
1574                         goto out;
1575                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1576                 data &= ~(1 << 13);
1577                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1578                 if (ret_val)
1579                         goto out;
1580                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1581                 data &= ~(0x3FF << 2);
1582                 data |= (0x1A << 2);
1583                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1584                 if (ret_val)
1585                         goto out;
1586                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1587                 if (ret_val)
1588                         goto out;
1589                 e1e_rphy(hw, HV_PM_CTRL, &data);
1590                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1591                 if (ret_val)
1592                         goto out;
1593         } else {
1594                 /* Write MAC register values back to h/w defaults */
1595                 mac_reg = er32(FFLT_DBG);
1596                 mac_reg &= ~(0xF << 14);
1597                 ew32(FFLT_DBG, mac_reg);
1598
1599                 mac_reg = er32(RCTL);
1600                 mac_reg &= ~E1000_RCTL_SECRC;
1601                 ew32(RCTL, mac_reg);
1602
1603                 ret_val = e1000e_read_kmrn_reg(hw,
1604                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1605                                                 &data);
1606                 if (ret_val)
1607                         goto out;
1608                 ret_val = e1000e_write_kmrn_reg(hw,
1609                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1610                                                 data & ~(1 << 0));
1611                 if (ret_val)
1612                         goto out;
1613                 ret_val = e1000e_read_kmrn_reg(hw,
1614                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1615                                                 &data);
1616                 if (ret_val)
1617                         goto out;
1618                 data &= ~(0xF << 8);
1619                 data |= (0xB << 8);
1620                 ret_val = e1000e_write_kmrn_reg(hw,
1621                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1622                                                 data);
1623                 if (ret_val)
1624                         goto out;
1625
1626                 /* Write PHY register values back to h/w defaults */
1627                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1628                 data &= ~(0x7F << 5);
1629                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1630                 if (ret_val)
1631                         goto out;
1632                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1633                 data |= (1 << 13);
1634                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1635                 if (ret_val)
1636                         goto out;
1637                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1638                 data &= ~(0x3FF << 2);
1639                 data |= (0x8 << 2);
1640                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1641                 if (ret_val)
1642                         goto out;
1643                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1644                 if (ret_val)
1645                         goto out;
1646                 e1e_rphy(hw, HV_PM_CTRL, &data);
1647                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1648                 if (ret_val)
1649                         goto out;
1650         }
1651
1652         /* re-enable Rx path after enabling/disabling workaround */
1653         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1654
1655 out:
1656         return ret_val;
1657 }
1658
1659 /**
1660  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1661  *  done after every PHY reset.
1662  **/
1663 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1664 {
1665         s32 ret_val = 0;
1666
1667         if (hw->mac.type != e1000_pch2lan)
1668                 goto out;
1669
1670         /* Set MDIO slow mode before any other MDIO access */
1671         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1672
1673 out:
1674         return ret_val;
1675 }
1676
1677 /**
1678  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1679  *  @hw:   pointer to the HW structure
1680  *
1681  *  Workaround to set the K1 beacon duration for 82579 parts
1682  **/
1683 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1684 {
1685         s32 ret_val = 0;
1686         u16 status_reg = 0;
1687         u32 mac_reg;
1688         u16 phy_reg;
1689
1690         if (hw->mac.type != e1000_pch2lan)
1691                 goto out;
1692
1693         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1694         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1695         if (ret_val)
1696                 goto out;
1697
1698         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1699             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1700                 mac_reg = er32(FEXTNVM4);
1701                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1702
1703                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1704                 if (ret_val)
1705                         goto out;
1706
1707                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1708                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1709                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1710                 } else {
1711                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1712                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1713                 }
1714                 ew32(FEXTNVM4, mac_reg);
1715                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1716         }
1717
1718 out:
1719         return ret_val;
1720 }
1721
1722 /**
1723  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1724  *  @hw:   pointer to the HW structure
1725  *  @gate: boolean set to true to gate, false to ungate
1726  *
1727  *  Gate/ungate the automatic PHY configuration via hardware; perform
1728  *  the configuration via software instead.
1729  **/
1730 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1731 {
1732         u32 extcnf_ctrl;
1733
1734         if (hw->mac.type != e1000_pch2lan)
1735                 return;
1736
1737         extcnf_ctrl = er32(EXTCNF_CTRL);
1738
1739         if (gate)
1740                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1741         else
1742                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1743
1744         ew32(EXTCNF_CTRL, extcnf_ctrl);
1745         return;
1746 }
1747
1748 /**
1749  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1750  *  @hw: pointer to the HW structure
1751  *
1752  *  Check the appropriate indication the MAC has finished configuring the
1753  *  PHY after a software reset.
1754  **/
1755 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1756 {
1757         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1758
1759         /* Wait for basic configuration completes before proceeding */
1760         do {
1761                 data = er32(STATUS);
1762                 data &= E1000_STATUS_LAN_INIT_DONE;
1763                 udelay(100);
1764         } while ((!data) && --loop);
1765
1766         /*
1767          * If basic configuration is incomplete before the above loop
1768          * count reaches 0, loading the configuration from NVM will
1769          * leave the PHY in a bad state possibly resulting in no link.
1770          */
1771         if (loop == 0)
1772                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1773
1774         /* Clear the Init Done bit for the next init event */
1775         data = er32(STATUS);
1776         data &= ~E1000_STATUS_LAN_INIT_DONE;
1777         ew32(STATUS, data);
1778 }
1779
1780 /**
1781  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1782  *  @hw: pointer to the HW structure
1783  **/
1784 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1785 {
1786         s32 ret_val = 0;
1787         u16 reg;
1788
1789         if (e1000_check_reset_block(hw))
1790                 goto out;
1791
1792         /* Allow time for h/w to get to quiescent state after reset */
1793         usleep_range(10000, 20000);
1794
1795         /* Perform any necessary post-reset workarounds */
1796         switch (hw->mac.type) {
1797         case e1000_pchlan:
1798                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1799                 if (ret_val)
1800                         goto out;
1801                 break;
1802         case e1000_pch2lan:
1803                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1804                 if (ret_val)
1805                         goto out;
1806                 break;
1807         default:
1808                 break;
1809         }
1810
1811         /* Clear the host wakeup bit after lcd reset */
1812         if (hw->mac.type >= e1000_pchlan) {
1813                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1814                 reg &= ~BM_WUC_HOST_WU_BIT;
1815                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1816         }
1817
1818         /* Configure the LCD with the extended configuration region in NVM */
1819         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1820         if (ret_val)
1821                 goto out;
1822
1823         /* Configure the LCD with the OEM bits in NVM */
1824         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1825
1826         if (hw->mac.type == e1000_pch2lan) {
1827                 /* Ungate automatic PHY configuration on non-managed 82579 */
1828                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1829                         usleep_range(10000, 20000);
1830                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1831                 }
1832
1833                 /* Set EEE LPI Update Timer to 200usec */
1834                 ret_val = hw->phy.ops.acquire(hw);
1835                 if (ret_val)
1836                         goto out;
1837                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1838                                                        I82579_LPI_UPDATE_TIMER);
1839                 if (ret_val)
1840                         goto release;
1841                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1842                                                        0x1387);
1843 release:
1844                 hw->phy.ops.release(hw);
1845         }
1846
1847 out:
1848         return ret_val;
1849 }
1850
1851 /**
1852  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1853  *  @hw: pointer to the HW structure
1854  *
1855  *  Resets the PHY
1856  *  This is a function pointer entry point called by drivers
1857  *  or other shared routines.
1858  **/
1859 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1860 {
1861         s32 ret_val = 0;
1862
1863         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1864         if ((hw->mac.type == e1000_pch2lan) &&
1865             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1866                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1867
1868         ret_val = e1000e_phy_hw_reset_generic(hw);
1869         if (ret_val)
1870                 goto out;
1871
1872         ret_val = e1000_post_phy_reset_ich8lan(hw);
1873
1874 out:
1875         return ret_val;
1876 }
1877
1878 /**
1879  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1880  *  @hw: pointer to the HW structure
1881  *  @active: true to enable LPLU, false to disable
1882  *
1883  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1884  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1885  *  the phy speed. This function will manually set the LPLU bit and restart
1886  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1887  *  since it configures the same bit.
1888  **/
1889 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1890 {
1891         s32 ret_val = 0;
1892         u16 oem_reg;
1893
1894         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1895         if (ret_val)
1896                 goto out;
1897
1898         if (active)
1899                 oem_reg |= HV_OEM_BITS_LPLU;
1900         else
1901                 oem_reg &= ~HV_OEM_BITS_LPLU;
1902
1903         oem_reg |= HV_OEM_BITS_RESTART_AN;
1904         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1905
1906 out:
1907         return ret_val;
1908 }
1909
1910 /**
1911  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1912  *  @hw: pointer to the HW structure
1913  *  @active: true to enable LPLU, false to disable
1914  *
1915  *  Sets the LPLU D0 state according to the active flag.  When
1916  *  activating LPLU this function also disables smart speed
1917  *  and vice versa.  LPLU will not be activated unless the
1918  *  device autonegotiation advertisement meets standards of
1919  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1920  *  This is a function pointer entry point only called by
1921  *  PHY setup routines.
1922  **/
1923 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1924 {
1925         struct e1000_phy_info *phy = &hw->phy;
1926         u32 phy_ctrl;
1927         s32 ret_val = 0;
1928         u16 data;
1929
1930         if (phy->type == e1000_phy_ife)
1931                 return ret_val;
1932
1933         phy_ctrl = er32(PHY_CTRL);
1934
1935         if (active) {
1936                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1937                 ew32(PHY_CTRL, phy_ctrl);
1938
1939                 if (phy->type != e1000_phy_igp_3)
1940                         return 0;
1941
1942                 /*
1943                  * Call gig speed drop workaround on LPLU before accessing
1944                  * any PHY registers
1945                  */
1946                 if (hw->mac.type == e1000_ich8lan)
1947                         e1000e_gig_downshift_workaround_ich8lan(hw);
1948
1949                 /* When LPLU is enabled, we should disable SmartSpeed */
1950                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1951                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1952                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1953                 if (ret_val)
1954                         return ret_val;
1955         } else {
1956                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1957                 ew32(PHY_CTRL, phy_ctrl);
1958
1959                 if (phy->type != e1000_phy_igp_3)
1960                         return 0;
1961
1962                 /*
1963                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1964                  * during Dx states where the power conservation is most
1965                  * important.  During driver activity we should enable
1966                  * SmartSpeed, so performance is maintained.
1967                  */
1968                 if (phy->smart_speed == e1000_smart_speed_on) {
1969                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1970                                            &data);
1971                         if (ret_val)
1972                                 return ret_val;
1973
1974                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1975                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1976                                            data);
1977                         if (ret_val)
1978                                 return ret_val;
1979                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1980                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1981                                            &data);
1982                         if (ret_val)
1983                                 return ret_val;
1984
1985                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1986                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1987                                            data);
1988                         if (ret_val)
1989                                 return ret_val;
1990                 }
1991         }
1992
1993         return 0;
1994 }
1995
1996 /**
1997  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1998  *  @hw: pointer to the HW structure
1999  *  @active: true to enable LPLU, false to disable
2000  *
2001  *  Sets the LPLU D3 state according to the active flag.  When
2002  *  activating LPLU this function also disables smart speed
2003  *  and vice versa.  LPLU will not be activated unless the
2004  *  device autonegotiation advertisement meets standards of
2005  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2006  *  This is a function pointer entry point only called by
2007  *  PHY setup routines.
2008  **/
2009 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2010 {
2011         struct e1000_phy_info *phy = &hw->phy;
2012         u32 phy_ctrl;
2013         s32 ret_val;
2014         u16 data;
2015
2016         phy_ctrl = er32(PHY_CTRL);
2017
2018         if (!active) {
2019                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2020                 ew32(PHY_CTRL, phy_ctrl);
2021
2022                 if (phy->type != e1000_phy_igp_3)
2023                         return 0;
2024
2025                 /*
2026                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2027                  * during Dx states where the power conservation is most
2028                  * important.  During driver activity we should enable
2029                  * SmartSpeed, so performance is maintained.
2030                  */
2031                 if (phy->smart_speed == e1000_smart_speed_on) {
2032                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2033                                            &data);
2034                         if (ret_val)
2035                                 return ret_val;
2036
2037                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2038                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2039                                            data);
2040                         if (ret_val)
2041                                 return ret_val;
2042                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2043                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2044                                            &data);
2045                         if (ret_val)
2046                                 return ret_val;
2047
2048                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2049                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2050                                            data);
2051                         if (ret_val)
2052                                 return ret_val;
2053                 }
2054         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2055                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2056                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2057                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2058                 ew32(PHY_CTRL, phy_ctrl);
2059
2060                 if (phy->type != e1000_phy_igp_3)
2061                         return 0;
2062
2063                 /*
2064                  * Call gig speed drop workaround on LPLU before accessing
2065                  * any PHY registers
2066                  */
2067                 if (hw->mac.type == e1000_ich8lan)
2068                         e1000e_gig_downshift_workaround_ich8lan(hw);
2069
2070                 /* When LPLU is enabled, we should disable SmartSpeed */
2071                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2072                 if (ret_val)
2073                         return ret_val;
2074
2075                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2076                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2077         }
2078
2079         return 0;
2080 }
2081
2082 /**
2083  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2084  *  @hw: pointer to the HW structure
2085  *  @bank:  pointer to the variable that returns the active bank
2086  *
2087  *  Reads signature byte from the NVM using the flash access registers.
2088  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2089  **/
2090 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2091 {
2092         u32 eecd;
2093         struct e1000_nvm_info *nvm = &hw->nvm;
2094         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2095         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2096         u8 sig_byte = 0;
2097         s32 ret_val = 0;
2098
2099         switch (hw->mac.type) {
2100         case e1000_ich8lan:
2101         case e1000_ich9lan:
2102                 eecd = er32(EECD);
2103                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2104                     E1000_EECD_SEC1VAL_VALID_MASK) {
2105                         if (eecd & E1000_EECD_SEC1VAL)
2106                                 *bank = 1;
2107                         else
2108                                 *bank = 0;
2109
2110                         return 0;
2111                 }
2112                 e_dbg("Unable to determine valid NVM bank via EEC - "
2113                        "reading flash signature\n");
2114                 /* fall-thru */
2115         default:
2116                 /* set bank to 0 in case flash read fails */
2117                 *bank = 0;
2118
2119                 /* Check bank 0 */
2120                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2121                                                         &sig_byte);
2122                 if (ret_val)
2123                         return ret_val;
2124                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2125                     E1000_ICH_NVM_SIG_VALUE) {
2126                         *bank = 0;
2127                         return 0;
2128                 }
2129
2130                 /* Check bank 1 */
2131                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2132                                                         bank1_offset,
2133                                                         &sig_byte);
2134                 if (ret_val)
2135                         return ret_val;
2136                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2137                     E1000_ICH_NVM_SIG_VALUE) {
2138                         *bank = 1;
2139                         return 0;
2140                 }
2141
2142                 e_dbg("ERROR: No valid NVM bank present\n");
2143                 return -E1000_ERR_NVM;
2144         }
2145
2146         return 0;
2147 }
2148
2149 /**
2150  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2151  *  @hw: pointer to the HW structure
2152  *  @offset: The offset (in bytes) of the word(s) to read.
2153  *  @words: Size of data to read in words
2154  *  @data: Pointer to the word(s) to read at offset.
2155  *
2156  *  Reads a word(s) from the NVM using the flash access registers.
2157  **/
2158 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2159                                   u16 *data)
2160 {
2161         struct e1000_nvm_info *nvm = &hw->nvm;
2162         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2163         u32 act_offset;
2164         s32 ret_val = 0;
2165         u32 bank = 0;
2166         u16 i, word;
2167
2168         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2169             (words == 0)) {
2170                 e_dbg("nvm parameter(s) out of bounds\n");
2171                 ret_val = -E1000_ERR_NVM;
2172                 goto out;
2173         }
2174
2175         nvm->ops.acquire(hw);
2176
2177         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2178         if (ret_val) {
2179                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2180                 bank = 0;
2181         }
2182
2183         act_offset = (bank) ? nvm->flash_bank_size : 0;
2184         act_offset += offset;
2185
2186         ret_val = 0;
2187         for (i = 0; i < words; i++) {
2188                 if (dev_spec->shadow_ram[offset+i].modified) {
2189                         data[i] = dev_spec->shadow_ram[offset+i].value;
2190                 } else {
2191                         ret_val = e1000_read_flash_word_ich8lan(hw,
2192                                                                 act_offset + i,
2193                                                                 &word);
2194                         if (ret_val)
2195                                 break;
2196                         data[i] = word;
2197                 }
2198         }
2199
2200         nvm->ops.release(hw);
2201
2202 out:
2203         if (ret_val)
2204                 e_dbg("NVM read error: %d\n", ret_val);
2205
2206         return ret_val;
2207 }
2208
2209 /**
2210  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2211  *  @hw: pointer to the HW structure
2212  *
2213  *  This function does initial flash setup so that a new read/write/erase cycle
2214  *  can be started.
2215  **/
2216 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2217 {
2218         union ich8_hws_flash_status hsfsts;
2219         s32 ret_val = -E1000_ERR_NVM;
2220
2221         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2222
2223         /* Check if the flash descriptor is valid */
2224         if (hsfsts.hsf_status.fldesvalid == 0) {
2225                 e_dbg("Flash descriptor invalid.  "
2226                          "SW Sequencing must be used.\n");
2227                 return -E1000_ERR_NVM;
2228         }
2229
2230         /* Clear FCERR and DAEL in hw status by writing 1 */
2231         hsfsts.hsf_status.flcerr = 1;
2232         hsfsts.hsf_status.dael = 1;
2233
2234         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2235
2236         /*
2237          * Either we should have a hardware SPI cycle in progress
2238          * bit to check against, in order to start a new cycle or
2239          * FDONE bit should be changed in the hardware so that it
2240          * is 1 after hardware reset, which can then be used as an
2241          * indication whether a cycle is in progress or has been
2242          * completed.
2243          */
2244
2245         if (hsfsts.hsf_status.flcinprog == 0) {
2246                 /*
2247                  * There is no cycle running at present,
2248                  * so we can start a cycle.
2249                  * Begin by setting Flash Cycle Done.
2250                  */
2251                 hsfsts.hsf_status.flcdone = 1;
2252                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2253                 ret_val = 0;
2254         } else {
2255                 s32 i = 0;
2256
2257                 /*
2258                  * Otherwise poll for sometime so the current
2259                  * cycle has a chance to end before giving up.
2260                  */
2261                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2262                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2263                         if (hsfsts.hsf_status.flcinprog == 0) {
2264                                 ret_val = 0;
2265                                 break;
2266                         }
2267                         udelay(1);
2268                 }
2269                 if (ret_val == 0) {
2270                         /*
2271                          * Successful in waiting for previous cycle to timeout,
2272                          * now set the Flash Cycle Done.
2273                          */
2274                         hsfsts.hsf_status.flcdone = 1;
2275                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2276                 } else {
2277                         e_dbg("Flash controller busy, cannot get access\n");
2278                 }
2279         }
2280
2281         return ret_val;
2282 }
2283
2284 /**
2285  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2286  *  @hw: pointer to the HW structure
2287  *  @timeout: maximum time to wait for completion
2288  *
2289  *  This function starts a flash cycle and waits for its completion.
2290  **/
2291 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2292 {
2293         union ich8_hws_flash_ctrl hsflctl;
2294         union ich8_hws_flash_status hsfsts;
2295         s32 ret_val = -E1000_ERR_NVM;
2296         u32 i = 0;
2297
2298         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2299         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2300         hsflctl.hsf_ctrl.flcgo = 1;
2301         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2302
2303         /* wait till FDONE bit is set to 1 */
2304         do {
2305                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2306                 if (hsfsts.hsf_status.flcdone == 1)
2307                         break;
2308                 udelay(1);
2309         } while (i++ < timeout);
2310
2311         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2312                 return 0;
2313
2314         return ret_val;
2315 }
2316
2317 /**
2318  *  e1000_read_flash_word_ich8lan - Read word from flash
2319  *  @hw: pointer to the HW structure
2320  *  @offset: offset to data location
2321  *  @data: pointer to the location for storing the data
2322  *
2323  *  Reads the flash word at offset into data.  Offset is converted
2324  *  to bytes before read.
2325  **/
2326 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2327                                          u16 *data)
2328 {
2329         /* Must convert offset into bytes. */
2330         offset <<= 1;
2331
2332         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2333 }
2334
2335 /**
2336  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2337  *  @hw: pointer to the HW structure
2338  *  @offset: The offset of the byte to read.
2339  *  @data: Pointer to a byte to store the value read.
2340  *
2341  *  Reads a single byte from the NVM using the flash access registers.
2342  **/
2343 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2344                                          u8 *data)
2345 {
2346         s32 ret_val;
2347         u16 word = 0;
2348
2349         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2350         if (ret_val)
2351                 return ret_val;
2352
2353         *data = (u8)word;
2354
2355         return 0;
2356 }
2357
2358 /**
2359  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2360  *  @hw: pointer to the HW structure
2361  *  @offset: The offset (in bytes) of the byte or word to read.
2362  *  @size: Size of data to read, 1=byte 2=word
2363  *  @data: Pointer to the word to store the value read.
2364  *
2365  *  Reads a byte or word from the NVM using the flash access registers.
2366  **/
2367 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2368                                          u8 size, u16 *data)
2369 {
2370         union ich8_hws_flash_status hsfsts;
2371         union ich8_hws_flash_ctrl hsflctl;
2372         u32 flash_linear_addr;
2373         u32 flash_data = 0;
2374         s32 ret_val = -E1000_ERR_NVM;
2375         u8 count = 0;
2376
2377         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2378                 return -E1000_ERR_NVM;
2379
2380         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2381                             hw->nvm.flash_base_addr;
2382
2383         do {
2384                 udelay(1);
2385                 /* Steps */
2386                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2387                 if (ret_val != 0)
2388                         break;
2389
2390                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2391                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2392                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2393                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2394                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2395
2396                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2397
2398                 ret_val = e1000_flash_cycle_ich8lan(hw,
2399                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2400
2401                 /*
2402                  * Check if FCERR is set to 1, if set to 1, clear it
2403                  * and try the whole sequence a few more times, else
2404                  * read in (shift in) the Flash Data0, the order is
2405                  * least significant byte first msb to lsb
2406                  */
2407                 if (ret_val == 0) {
2408                         flash_data = er32flash(ICH_FLASH_FDATA0);
2409                         if (size == 1)
2410                                 *data = (u8)(flash_data & 0x000000FF);
2411                         else if (size == 2)
2412                                 *data = (u16)(flash_data & 0x0000FFFF);
2413                         break;
2414                 } else {
2415                         /*
2416                          * If we've gotten here, then things are probably
2417                          * completely hosed, but if the error condition is
2418                          * detected, it won't hurt to give it another try...
2419                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2420                          */
2421                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2422                         if (hsfsts.hsf_status.flcerr == 1) {
2423                                 /* Repeat for some time before giving up. */
2424                                 continue;
2425                         } else if (hsfsts.hsf_status.flcdone == 0) {
2426                                 e_dbg("Timeout error - flash cycle "
2427                                          "did not complete.\n");
2428                                 break;
2429                         }
2430                 }
2431         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2432
2433         return ret_val;
2434 }
2435
2436 /**
2437  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2438  *  @hw: pointer to the HW structure
2439  *  @offset: The offset (in bytes) of the word(s) to write.
2440  *  @words: Size of data to write in words
2441  *  @data: Pointer to the word(s) to write at offset.
2442  *
2443  *  Writes a byte or word to the NVM using the flash access registers.
2444  **/
2445 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2446                                    u16 *data)
2447 {
2448         struct e1000_nvm_info *nvm = &hw->nvm;
2449         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2450         u16 i;
2451
2452         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2453             (words == 0)) {
2454                 e_dbg("nvm parameter(s) out of bounds\n");
2455                 return -E1000_ERR_NVM;
2456         }
2457
2458         nvm->ops.acquire(hw);
2459
2460         for (i = 0; i < words; i++) {
2461                 dev_spec->shadow_ram[offset+i].modified = true;
2462                 dev_spec->shadow_ram[offset+i].value = data[i];
2463         }
2464
2465         nvm->ops.release(hw);
2466
2467         return 0;
2468 }
2469
2470 /**
2471  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2472  *  @hw: pointer to the HW structure
2473  *
2474  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2475  *  which writes the checksum to the shadow ram.  The changes in the shadow
2476  *  ram are then committed to the EEPROM by processing each bank at a time
2477  *  checking for the modified bit and writing only the pending changes.
2478  *  After a successful commit, the shadow ram is cleared and is ready for
2479  *  future writes.
2480  **/
2481 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2482 {
2483         struct e1000_nvm_info *nvm = &hw->nvm;
2484         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2485         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2486         s32 ret_val;
2487         u16 data;
2488
2489         ret_val = e1000e_update_nvm_checksum_generic(hw);
2490         if (ret_val)
2491                 goto out;
2492
2493         if (nvm->type != e1000_nvm_flash_sw)
2494                 goto out;
2495
2496         nvm->ops.acquire(hw);
2497
2498         /*
2499          * We're writing to the opposite bank so if we're on bank 1,
2500          * write to bank 0 etc.  We also need to erase the segment that
2501          * is going to be written
2502          */
2503         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2504         if (ret_val) {
2505                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2506                 bank = 0;
2507         }
2508
2509         if (bank == 0) {
2510                 new_bank_offset = nvm->flash_bank_size;
2511                 old_bank_offset = 0;
2512                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2513                 if (ret_val)
2514                         goto release;
2515         } else {
2516                 old_bank_offset = nvm->flash_bank_size;
2517                 new_bank_offset = 0;
2518                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2519                 if (ret_val)
2520                         goto release;
2521         }
2522
2523         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2524                 /*
2525                  * Determine whether to write the value stored
2526                  * in the other NVM bank or a modified value stored
2527                  * in the shadow RAM
2528                  */
2529                 if (dev_spec->shadow_ram[i].modified) {
2530                         data = dev_spec->shadow_ram[i].value;
2531                 } else {
2532                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2533                                                                 old_bank_offset,
2534                                                                 &data);
2535                         if (ret_val)
2536                                 break;
2537                 }
2538
2539                 /*
2540                  * If the word is 0x13, then make sure the signature bits
2541                  * (15:14) are 11b until the commit has completed.
2542                  * This will allow us to write 10b which indicates the
2543                  * signature is valid.  We want to do this after the write
2544                  * has completed so that we don't mark the segment valid
2545                  * while the write is still in progress
2546                  */
2547                 if (i == E1000_ICH_NVM_SIG_WORD)
2548                         data |= E1000_ICH_NVM_SIG_MASK;
2549
2550                 /* Convert offset to bytes. */
2551                 act_offset = (i + new_bank_offset) << 1;
2552
2553                 udelay(100);
2554                 /* Write the bytes to the new bank. */
2555                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2556                                                                act_offset,
2557                                                                (u8)data);
2558                 if (ret_val)
2559                         break;
2560
2561                 udelay(100);
2562                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2563                                                           act_offset + 1,
2564                                                           (u8)(data >> 8));
2565                 if (ret_val)
2566                         break;
2567         }
2568
2569         /*
2570          * Don't bother writing the segment valid bits if sector
2571          * programming failed.
2572          */
2573         if (ret_val) {
2574                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2575                 e_dbg("Flash commit failed.\n");
2576                 goto release;
2577         }
2578
2579         /*
2580          * Finally validate the new segment by setting bit 15:14
2581          * to 10b in word 0x13 , this can be done without an
2582          * erase as well since these bits are 11 to start with
2583          * and we need to change bit 14 to 0b
2584          */
2585         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2586         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2587         if (ret_val)
2588                 goto release;
2589
2590         data &= 0xBFFF;
2591         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2592                                                        act_offset * 2 + 1,
2593                                                        (u8)(data >> 8));
2594         if (ret_val)
2595                 goto release;
2596
2597         /*
2598          * And invalidate the previously valid segment by setting
2599          * its signature word (0x13) high_byte to 0b. This can be
2600          * done without an erase because flash erase sets all bits
2601          * to 1's. We can write 1's to 0's without an erase
2602          */
2603         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2604         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2605         if (ret_val)
2606                 goto release;
2607
2608         /* Great!  Everything worked, we can now clear the cached entries. */
2609         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2610                 dev_spec->shadow_ram[i].modified = false;
2611                 dev_spec->shadow_ram[i].value = 0xFFFF;
2612         }
2613
2614 release:
2615         nvm->ops.release(hw);
2616
2617         /*
2618          * Reload the EEPROM, or else modifications will not appear
2619          * until after the next adapter reset.
2620          */
2621         if (!ret_val) {
2622                 e1000e_reload_nvm(hw);
2623                 usleep_range(10000, 20000);
2624         }
2625
2626 out:
2627         if (ret_val)
2628                 e_dbg("NVM update error: %d\n", ret_val);
2629
2630         return ret_val;
2631 }
2632
2633 /**
2634  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2635  *  @hw: pointer to the HW structure
2636  *
2637  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2638  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2639  *  calculated, in which case we need to calculate the checksum and set bit 6.
2640  **/
2641 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2642 {
2643         s32 ret_val;
2644         u16 data;
2645
2646         /*
2647          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2648          * needs to be fixed.  This bit is an indication that the NVM
2649          * was prepared by OEM software and did not calculate the
2650          * checksum...a likely scenario.
2651          */
2652         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2653         if (ret_val)
2654                 return ret_val;
2655
2656         if ((data & 0x40) == 0) {
2657                 data |= 0x40;
2658                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2659                 if (ret_val)
2660                         return ret_val;
2661                 ret_val = e1000e_update_nvm_checksum(hw);
2662                 if (ret_val)
2663                         return ret_val;
2664         }
2665
2666         return e1000e_validate_nvm_checksum_generic(hw);
2667 }
2668
2669 /**
2670  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2671  *  @hw: pointer to the HW structure
2672  *
2673  *  To prevent malicious write/erase of the NVM, set it to be read-only
2674  *  so that the hardware ignores all write/erase cycles of the NVM via
2675  *  the flash control registers.  The shadow-ram copy of the NVM will
2676  *  still be updated, however any updates to this copy will not stick
2677  *  across driver reloads.
2678  **/
2679 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2680 {
2681         struct e1000_nvm_info *nvm = &hw->nvm;
2682         union ich8_flash_protected_range pr0;
2683         union ich8_hws_flash_status hsfsts;
2684         u32 gfpreg;
2685
2686         nvm->ops.acquire(hw);
2687
2688         gfpreg = er32flash(ICH_FLASH_GFPREG);
2689
2690         /* Write-protect GbE Sector of NVM */
2691         pr0.regval = er32flash(ICH_FLASH_PR0);
2692         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2693         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2694         pr0.range.wpe = true;
2695         ew32flash(ICH_FLASH_PR0, pr0.regval);
2696
2697         /*
2698          * Lock down a subset of GbE Flash Control Registers, e.g.
2699          * PR0 to prevent the write-protection from being lifted.
2700          * Once FLOCKDN is set, the registers protected by it cannot
2701          * be written until FLOCKDN is cleared by a hardware reset.
2702          */
2703         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2704         hsfsts.hsf_status.flockdn = true;
2705         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2706
2707         nvm->ops.release(hw);
2708 }
2709
2710 /**
2711  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2712  *  @hw: pointer to the HW structure
2713  *  @offset: The offset (in bytes) of the byte/word to read.
2714  *  @size: Size of data to read, 1=byte 2=word
2715  *  @data: The byte(s) to write to the NVM.
2716  *
2717  *  Writes one/two bytes to the NVM using the flash access registers.
2718  **/
2719 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2720                                           u8 size, u16 data)
2721 {
2722         union ich8_hws_flash_status hsfsts;
2723         union ich8_hws_flash_ctrl hsflctl;
2724         u32 flash_linear_addr;
2725         u32 flash_data = 0;
2726         s32 ret_val;
2727         u8 count = 0;
2728
2729         if (size < 1 || size > 2 || data > size * 0xff ||
2730             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2731                 return -E1000_ERR_NVM;
2732
2733         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2734                             hw->nvm.flash_base_addr;
2735
2736         do {
2737                 udelay(1);
2738                 /* Steps */
2739                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2740                 if (ret_val)
2741                         break;
2742
2743                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2744                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2745                 hsflctl.hsf_ctrl.fldbcount = size -1;
2746                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2747                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2748
2749                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2750
2751                 if (size == 1)
2752                         flash_data = (u32)data & 0x00FF;
2753                 else
2754                         flash_data = (u32)data;
2755
2756                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2757
2758                 /*
2759                  * check if FCERR is set to 1 , if set to 1, clear it
2760                  * and try the whole sequence a few more times else done
2761                  */
2762                 ret_val = e1000_flash_cycle_ich8lan(hw,
2763                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2764                 if (!ret_val)
2765                         break;
2766
2767                 /*
2768                  * If we're here, then things are most likely
2769                  * completely hosed, but if the error condition
2770                  * is detected, it won't hurt to give it another
2771                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2772                  */
2773                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2774                 if (hsfsts.hsf_status.flcerr == 1)
2775                         /* Repeat for some time before giving up. */
2776                         continue;
2777                 if (hsfsts.hsf_status.flcdone == 0) {
2778                         e_dbg("Timeout error - flash cycle "
2779                                  "did not complete.");
2780                         break;
2781                 }
2782         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2783
2784         return ret_val;
2785 }
2786
2787 /**
2788  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2789  *  @hw: pointer to the HW structure
2790  *  @offset: The index of the byte to read.
2791  *  @data: The byte to write to the NVM.
2792  *
2793  *  Writes a single byte to the NVM using the flash access registers.
2794  **/
2795 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2796                                           u8 data)
2797 {
2798         u16 word = (u16)data;
2799
2800         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2801 }
2802
2803 /**
2804  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2805  *  @hw: pointer to the HW structure
2806  *  @offset: The offset of the byte to write.
2807  *  @byte: The byte to write to the NVM.
2808  *
2809  *  Writes a single byte to the NVM using the flash access registers.
2810  *  Goes through a retry algorithm before giving up.
2811  **/
2812 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2813                                                 u32 offset, u8 byte)
2814 {
2815         s32 ret_val;
2816         u16 program_retries;
2817
2818         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2819         if (!ret_val)
2820                 return ret_val;
2821
2822         for (program_retries = 0; program_retries < 100; program_retries++) {
2823                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2824                 udelay(100);
2825                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2826                 if (!ret_val)
2827                         break;
2828         }
2829         if (program_retries == 100)
2830                 return -E1000_ERR_NVM;
2831
2832         return 0;
2833 }
2834
2835 /**
2836  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2837  *  @hw: pointer to the HW structure
2838  *  @bank: 0 for first bank, 1 for second bank, etc.
2839  *
2840  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2841  *  bank N is 4096 * N + flash_reg_addr.
2842  **/
2843 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2844 {
2845         struct e1000_nvm_info *nvm = &hw->nvm;
2846         union ich8_hws_flash_status hsfsts;
2847         union ich8_hws_flash_ctrl hsflctl;
2848         u32 flash_linear_addr;
2849         /* bank size is in 16bit words - adjust to bytes */
2850         u32 flash_bank_size = nvm->flash_bank_size * 2;
2851         s32 ret_val;
2852         s32 count = 0;
2853         s32 j, iteration, sector_size;
2854
2855         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2856
2857         /*
2858          * Determine HW Sector size: Read BERASE bits of hw flash status
2859          * register
2860          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2861          *     consecutive sectors.  The start index for the nth Hw sector
2862          *     can be calculated as = bank * 4096 + n * 256
2863          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2864          *     The start index for the nth Hw sector can be calculated
2865          *     as = bank * 4096
2866          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2867          *     (ich9 only, otherwise error condition)
2868          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2869          */
2870         switch (hsfsts.hsf_status.berasesz) {
2871         case 0:
2872                 /* Hw sector size 256 */
2873                 sector_size = ICH_FLASH_SEG_SIZE_256;
2874                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2875                 break;
2876         case 1:
2877                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2878                 iteration = 1;
2879                 break;
2880         case 2:
2881                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2882                 iteration = 1;
2883                 break;
2884         case 3:
2885                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2886                 iteration = 1;
2887                 break;
2888         default:
2889                 return -E1000_ERR_NVM;
2890         }
2891
2892         /* Start with the base address, then add the sector offset. */
2893         flash_linear_addr = hw->nvm.flash_base_addr;
2894         flash_linear_addr += (bank) ? flash_bank_size : 0;
2895
2896         for (j = 0; j < iteration ; j++) {
2897                 do {
2898                         /* Steps */
2899                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2900                         if (ret_val)
2901                                 return ret_val;
2902
2903                         /*
2904                          * Write a value 11 (block Erase) in Flash
2905                          * Cycle field in hw flash control
2906                          */
2907                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2908                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2909                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2910
2911                         /*
2912                          * Write the last 24 bits of an index within the
2913                          * block into Flash Linear address field in Flash
2914                          * Address.
2915                          */
2916                         flash_linear_addr += (j * sector_size);
2917                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2918
2919                         ret_val = e1000_flash_cycle_ich8lan(hw,
2920                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2921                         if (ret_val == 0)
2922                                 break;
2923
2924                         /*
2925                          * Check if FCERR is set to 1.  If 1,
2926                          * clear it and try the whole sequence
2927                          * a few more times else Done
2928                          */
2929                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2930                         if (hsfsts.hsf_status.flcerr == 1)
2931                                 /* repeat for some time before giving up */
2932                                 continue;
2933                         else if (hsfsts.hsf_status.flcdone == 0)
2934                                 return ret_val;
2935                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2936         }
2937
2938         return 0;
2939 }
2940
2941 /**
2942  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2943  *  @hw: pointer to the HW structure
2944  *  @data: Pointer to the LED settings
2945  *
2946  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2947  *  settings is all 0's or F's, set the LED default to a valid LED default
2948  *  setting.
2949  **/
2950 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2951 {
2952         s32 ret_val;
2953
2954         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2955         if (ret_val) {
2956                 e_dbg("NVM Read Error\n");
2957                 return ret_val;
2958         }
2959
2960         if (*data == ID_LED_RESERVED_0000 ||
2961             *data == ID_LED_RESERVED_FFFF)
2962                 *data = ID_LED_DEFAULT_ICH8LAN;
2963
2964         return 0;
2965 }
2966
2967 /**
2968  *  e1000_id_led_init_pchlan - store LED configurations
2969  *  @hw: pointer to the HW structure
2970  *
2971  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2972  *  the PHY LED configuration register.
2973  *
2974  *  PCH also does not have an "always on" or "always off" mode which
2975  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2976  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2977  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2978  *  link based on logic in e1000_led_[on|off]_pchlan().
2979  **/
2980 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2981 {
2982         struct e1000_mac_info *mac = &hw->mac;
2983         s32 ret_val;
2984         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2985         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2986         u16 data, i, temp, shift;
2987
2988         /* Get default ID LED modes */
2989         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2990         if (ret_val)
2991                 goto out;
2992
2993         mac->ledctl_default = er32(LEDCTL);
2994         mac->ledctl_mode1 = mac->ledctl_default;
2995         mac->ledctl_mode2 = mac->ledctl_default;
2996
2997         for (i = 0; i < 4; i++) {
2998                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2999                 shift = (i * 5);
3000                 switch (temp) {
3001                 case ID_LED_ON1_DEF2:
3002                 case ID_LED_ON1_ON2:
3003                 case ID_LED_ON1_OFF2:
3004                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3005                         mac->ledctl_mode1 |= (ledctl_on << shift);
3006                         break;
3007                 case ID_LED_OFF1_DEF2:
3008                 case ID_LED_OFF1_ON2:
3009                 case ID_LED_OFF1_OFF2:
3010                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3011                         mac->ledctl_mode1 |= (ledctl_off << shift);
3012                         break;
3013                 default:
3014                         /* Do nothing */
3015                         break;
3016                 }
3017                 switch (temp) {
3018                 case ID_LED_DEF1_ON2:
3019                 case ID_LED_ON1_ON2:
3020                 case ID_LED_OFF1_ON2:
3021                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3022                         mac->ledctl_mode2 |= (ledctl_on << shift);
3023                         break;
3024                 case ID_LED_DEF1_OFF2:
3025                 case ID_LED_ON1_OFF2:
3026                 case ID_LED_OFF1_OFF2:
3027                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3028                         mac->ledctl_mode2 |= (ledctl_off << shift);
3029                         break;
3030                 default:
3031                         /* Do nothing */
3032                         break;
3033                 }
3034         }
3035
3036 out:
3037         return ret_val;
3038 }
3039
3040 /**
3041  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3042  *  @hw: pointer to the HW structure
3043  *
3044  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3045  *  register, so the the bus width is hard coded.
3046  **/
3047 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3048 {
3049         struct e1000_bus_info *bus = &hw->bus;
3050         s32 ret_val;
3051
3052         ret_val = e1000e_get_bus_info_pcie(hw);
3053
3054         /*
3055          * ICH devices are "PCI Express"-ish.  They have
3056          * a configuration space, but do not contain
3057          * PCI Express Capability registers, so bus width
3058          * must be hardcoded.
3059          */
3060         if (bus->width == e1000_bus_width_unknown)
3061                 bus->width = e1000_bus_width_pcie_x1;
3062
3063         return ret_val;
3064 }
3065
3066 /**
3067  *  e1000_reset_hw_ich8lan - Reset the hardware
3068  *  @hw: pointer to the HW structure
3069  *
3070  *  Does a full reset of the hardware which includes a reset of the PHY and
3071  *  MAC.
3072  **/
3073 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3074 {
3075         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3076         u16 reg;
3077         u32 ctrl, kab;
3078         s32 ret_val;
3079
3080         /*
3081          * Prevent the PCI-E bus from sticking if there is no TLP connection
3082          * on the last TLP read/write transaction when MAC is reset.
3083          */
3084         ret_val = e1000e_disable_pcie_master(hw);
3085         if (ret_val)
3086                 e_dbg("PCI-E Master disable polling has failed.\n");
3087
3088         e_dbg("Masking off all interrupts\n");
3089         ew32(IMC, 0xffffffff);
3090
3091         /*
3092          * Disable the Transmit and Receive units.  Then delay to allow
3093          * any pending transactions to complete before we hit the MAC
3094          * with the global reset.
3095          */
3096         ew32(RCTL, 0);
3097         ew32(TCTL, E1000_TCTL_PSP);
3098         e1e_flush();
3099
3100         usleep_range(10000, 20000);
3101
3102         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3103         if (hw->mac.type == e1000_ich8lan) {
3104                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3105                 ew32(PBA, E1000_PBA_8K);
3106                 /* Set Packet Buffer Size to 16k. */
3107                 ew32(PBS, E1000_PBS_16K);
3108         }
3109
3110         if (hw->mac.type == e1000_pchlan) {
3111                 /* Save the NVM K1 bit setting*/
3112                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3113                 if (ret_val)
3114                         return ret_val;
3115
3116                 if (reg & E1000_NVM_K1_ENABLE)
3117                         dev_spec->nvm_k1_enabled = true;
3118                 else
3119                         dev_spec->nvm_k1_enabled = false;
3120         }
3121
3122         ctrl = er32(CTRL);
3123
3124         if (!e1000_check_reset_block(hw)) {
3125                 /*
3126                  * Full-chip reset requires MAC and PHY reset at the same
3127                  * time to make sure the interface between MAC and the
3128                  * external PHY is reset.
3129                  */
3130                 ctrl |= E1000_CTRL_PHY_RST;
3131
3132                 /*
3133                  * Gate automatic PHY configuration by hardware on
3134                  * non-managed 82579
3135                  */
3136                 if ((hw->mac.type == e1000_pch2lan) &&
3137                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3138                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3139         }
3140         ret_val = e1000_acquire_swflag_ich8lan(hw);
3141         e_dbg("Issuing a global reset to ich8lan\n");
3142         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3143         /* cannot issue a flush here because it hangs the hardware */
3144         msleep(20);
3145
3146         if (!ret_val)
3147                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3148
3149         if (ctrl & E1000_CTRL_PHY_RST) {
3150                 ret_val = hw->phy.ops.get_cfg_done(hw);
3151                 if (ret_val)
3152                         goto out;
3153
3154                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3155                 if (ret_val)
3156                         goto out;
3157         }
3158
3159         /*
3160          * For PCH, this write will make sure that any noise
3161          * will be detected as a CRC error and be dropped rather than show up
3162          * as a bad packet to the DMA engine.
3163          */
3164         if (hw->mac.type == e1000_pchlan)
3165                 ew32(CRC_OFFSET, 0x65656565);
3166
3167         ew32(IMC, 0xffffffff);
3168         er32(ICR);
3169
3170         kab = er32(KABGTXD);
3171         kab |= E1000_KABGTXD_BGSQLBIAS;
3172         ew32(KABGTXD, kab);
3173
3174 out:
3175         return ret_val;
3176 }
3177
3178 /**
3179  *  e1000_init_hw_ich8lan - Initialize the hardware
3180  *  @hw: pointer to the HW structure
3181  *
3182  *  Prepares the hardware for transmit and receive by doing the following:
3183  *   - initialize hardware bits
3184  *   - initialize LED identification
3185  *   - setup receive address registers
3186  *   - setup flow control
3187  *   - setup transmit descriptors
3188  *   - clear statistics
3189  **/
3190 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3191 {
3192         struct e1000_mac_info *mac = &hw->mac;
3193         u32 ctrl_ext, txdctl, snoop;
3194         s32 ret_val;
3195         u16 i;
3196
3197         e1000_initialize_hw_bits_ich8lan(hw);
3198
3199         /* Initialize identification LED */
3200         ret_val = mac->ops.id_led_init(hw);
3201         if (ret_val)
3202                 e_dbg("Error initializing identification LED\n");
3203                 /* This is not fatal and we should not stop init due to this */
3204
3205         /* Setup the receive address. */
3206         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3207
3208         /* Zero out the Multicast HASH table */
3209         e_dbg("Zeroing the MTA\n");
3210         for (i = 0; i < mac->mta_reg_count; i++)
3211                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3212
3213         /*
3214          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3215          * the ME.  Disable wakeup by clearing the host wakeup bit.
3216          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3217          */
3218         if (hw->phy.type == e1000_phy_82578) {
3219                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3220                 i &= ~BM_WUC_HOST_WU_BIT;
3221                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3222                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3223                 if (ret_val)
3224                         return ret_val;
3225         }
3226
3227         /* Setup link and flow control */
3228         ret_val = e1000_setup_link_ich8lan(hw);
3229
3230         /* Set the transmit descriptor write-back policy for both queues */
3231         txdctl = er32(TXDCTL(0));
3232         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3233                  E1000_TXDCTL_FULL_TX_DESC_WB;
3234         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3235                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3236         ew32(TXDCTL(0), txdctl);
3237         txdctl = er32(TXDCTL(1));
3238         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3239                  E1000_TXDCTL_FULL_TX_DESC_WB;
3240         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3241                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3242         ew32(TXDCTL(1), txdctl);
3243
3244         /*
3245          * ICH8 has opposite polarity of no_snoop bits.
3246          * By default, we should use snoop behavior.
3247          */
3248         if (mac->type == e1000_ich8lan)
3249                 snoop = PCIE_ICH8_SNOOP_ALL;
3250         else
3251                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3252         e1000e_set_pcie_no_snoop(hw, snoop);
3253
3254         ctrl_ext = er32(CTRL_EXT);
3255         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3256         ew32(CTRL_EXT, ctrl_ext);
3257
3258         /*
3259          * Clear all of the statistics registers (clear on read).  It is
3260          * important that we do this after we have tried to establish link
3261          * because the symbol error count will increment wildly if there
3262          * is no link.
3263          */
3264         e1000_clear_hw_cntrs_ich8lan(hw);
3265
3266         return 0;
3267 }
3268 /**
3269  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3270  *  @hw: pointer to the HW structure
3271  *
3272  *  Sets/Clears required hardware bits necessary for correctly setting up the
3273  *  hardware for transmit and receive.
3274  **/
3275 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3276 {
3277         u32 reg;
3278
3279         /* Extended Device Control */
3280         reg = er32(CTRL_EXT);
3281         reg |= (1 << 22);
3282         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3283         if (hw->mac.type >= e1000_pchlan)
3284                 reg |= E1000_CTRL_EXT_PHYPDEN;
3285         ew32(CTRL_EXT, reg);
3286
3287         /* Transmit Descriptor Control 0 */
3288         reg = er32(TXDCTL(0));
3289         reg |= (1 << 22);
3290         ew32(TXDCTL(0), reg);
3291
3292         /* Transmit Descriptor Control 1 */
3293         reg = er32(TXDCTL(1));
3294         reg |= (1 << 22);
3295         ew32(TXDCTL(1), reg);
3296
3297         /* Transmit Arbitration Control 0 */
3298         reg = er32(TARC(0));
3299         if (hw->mac.type == e1000_ich8lan)
3300                 reg |= (1 << 28) | (1 << 29);
3301         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3302         ew32(TARC(0), reg);
3303
3304         /* Transmit Arbitration Control 1 */
3305         reg = er32(TARC(1));
3306         if (er32(TCTL) & E1000_TCTL_MULR)
3307                 reg &= ~(1 << 28);
3308         else
3309                 reg |= (1 << 28);
3310         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3311         ew32(TARC(1), reg);
3312
3313         /* Device Status */
3314         if (hw->mac.type == e1000_ich8lan) {
3315                 reg = er32(STATUS);
3316                 reg &= ~(1 << 31);
3317                 ew32(STATUS, reg);
3318         }
3319
3320         /*
3321          * work-around descriptor data corruption issue during nfs v2 udp
3322          * traffic, just disable the nfs filtering capability
3323          */
3324         reg = er32(RFCTL);
3325         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3326         ew32(RFCTL, reg);
3327 }
3328
3329 /**
3330  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3331  *  @hw: pointer to the HW structure
3332  *
3333  *  Determines which flow control settings to use, then configures flow
3334  *  control.  Calls the appropriate media-specific link configuration
3335  *  function.  Assuming the adapter has a valid link partner, a valid link
3336  *  should be established.  Assumes the hardware has previously been reset
3337  *  and the transmitter and receiver are not enabled.
3338  **/
3339 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3340 {
3341         s32 ret_val;
3342
3343         if (e1000_check_reset_block(hw))
3344                 return 0;
3345
3346         /*
3347          * ICH parts do not have a word in the NVM to determine
3348          * the default flow control setting, so we explicitly
3349          * set it to full.
3350          */
3351         if (hw->fc.requested_mode == e1000_fc_default) {
3352                 /* Workaround h/w hang when Tx flow control enabled */
3353                 if (hw->mac.type == e1000_pchlan)
3354                         hw->fc.requested_mode = e1000_fc_rx_pause;
3355                 else
3356                         hw->fc.requested_mode = e1000_fc_full;
3357         }
3358
3359         /*
3360          * Save off the requested flow control mode for use later.  Depending
3361          * on the link partner's capabilities, we may or may not use this mode.
3362          */
3363         hw->fc.current_mode = hw->fc.requested_mode;
3364
3365         e_dbg("After fix-ups FlowControl is now = %x\n",
3366                 hw->fc.current_mode);
3367
3368         /* Continue to configure the copper link. */
3369         ret_val = e1000_setup_copper_link_ich8lan(hw);
3370         if (ret_val)
3371                 return ret_val;
3372
3373         ew32(FCTTV, hw->fc.pause_time);
3374         if ((hw->phy.type == e1000_phy_82578) ||
3375             (hw->phy.type == e1000_phy_82579) ||
3376             (hw->phy.type == e1000_phy_82577)) {
3377                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3378
3379                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3380                                    hw->fc.pause_time);
3381                 if (ret_val)
3382                         return ret_val;
3383         }
3384
3385         return e1000e_set_fc_watermarks(hw);
3386 }
3387
3388 /**
3389  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3390  *  @hw: pointer to the HW structure
3391  *
3392  *  Configures the kumeran interface to the PHY to wait the appropriate time
3393  *  when polling the PHY, then call the generic setup_copper_link to finish
3394  *  configuring the copper link.
3395  **/
3396 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3397 {
3398         u32 ctrl;
3399         s32 ret_val;
3400         u16 reg_data;
3401
3402         ctrl = er32(CTRL);
3403         ctrl |= E1000_CTRL_SLU;
3404         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3405         ew32(CTRL, ctrl);
3406
3407         /*
3408          * Set the mac to wait the maximum time between each iteration
3409          * and increase the max iterations when polling the phy;
3410          * this fixes erroneous timeouts at 10Mbps.
3411          */
3412         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3413         if (ret_val)
3414                 return ret_val;
3415         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3416                                        &reg_data);
3417         if (ret_val)
3418                 return ret_val;
3419         reg_data |= 0x3F;
3420         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3421                                         reg_data);
3422         if (ret_val)
3423                 return ret_val;
3424
3425         switch (hw->phy.type) {
3426         case e1000_phy_igp_3:
3427                 ret_val = e1000e_copper_link_setup_igp(hw);
3428                 if (ret_val)
3429                         return ret_val;
3430                 break;
3431         case e1000_phy_bm:
3432         case e1000_phy_82578:
3433                 ret_val = e1000e_copper_link_setup_m88(hw);
3434                 if (ret_val)
3435                         return ret_val;
3436                 break;
3437         case e1000_phy_82577:
3438         case e1000_phy_82579:
3439                 ret_val = e1000_copper_link_setup_82577(hw);
3440                 if (ret_val)
3441                         return ret_val;
3442                 break;
3443         case e1000_phy_ife:
3444                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3445                 if (ret_val)
3446                         return ret_val;
3447
3448                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3449
3450                 switch (hw->phy.mdix) {
3451                 case 1:
3452                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3453                         break;
3454                 case 2:
3455                         reg_data |= IFE_PMC_FORCE_MDIX;
3456                         break;
3457                 case 0:
3458                 default:
3459                         reg_data |= IFE_PMC_AUTO_MDIX;
3460                         break;
3461                 }
3462                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3463                 if (ret_val)
3464                         return ret_val;
3465                 break;
3466         default:
3467                 break;
3468         }
3469         return e1000e_setup_copper_link(hw);
3470 }
3471
3472 /**
3473  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3474  *  @hw: pointer to the HW structure
3475  *  @speed: pointer to store current link speed
3476  *  @duplex: pointer to store the current link duplex
3477  *
3478  *  Calls the generic get_speed_and_duplex to retrieve the current link
3479  *  information and then calls the Kumeran lock loss workaround for links at
3480  *  gigabit speeds.
3481  **/
3482 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3483                                           u16 *duplex)
3484 {
3485         s32 ret_val;
3486
3487         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3488         if (ret_val)
3489                 return ret_val;
3490
3491         if ((hw->mac.type == e1000_ich8lan) &&
3492             (hw->phy.type == e1000_phy_igp_3) &&
3493             (*speed == SPEED_1000)) {
3494                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3495         }
3496
3497         return ret_val;
3498 }
3499
3500 /**
3501  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3502  *  @hw: pointer to the HW structure
3503  *
3504  *  Work-around for 82566 Kumeran PCS lock loss:
3505  *  On link status change (i.e. PCI reset, speed change) and link is up and
3506  *  speed is gigabit-
3507  *    0) if workaround is optionally disabled do nothing
3508  *    1) wait 1ms for Kumeran link to come up
3509  *    2) check Kumeran Diagnostic register PCS lock loss bit
3510  *    3) if not set the link is locked (all is good), otherwise...
3511  *    4) reset the PHY
3512  *    5) repeat up to 10 times
3513  *  Note: this is only called for IGP3 copper when speed is 1gb.
3514  **/
3515 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3516 {
3517         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3518         u32 phy_ctrl;
3519         s32 ret_val;
3520         u16 i, data;
3521         bool link;
3522
3523         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3524                 return 0;
3525
3526         /*
3527          * Make sure link is up before proceeding.  If not just return.
3528          * Attempting this while link is negotiating fouled up link
3529          * stability
3530          */
3531         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3532         if (!link)
3533                 return 0;
3534
3535         for (i = 0; i < 10; i++) {
3536                 /* read once to clear */
3537                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3538                 if (ret_val)
3539                         return ret_val;
3540                 /* and again to get new status */
3541                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3542                 if (ret_val)
3543                         return ret_val;
3544
3545                 /* check for PCS lock */
3546                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3547                         return 0;
3548
3549                 /* Issue PHY reset */
3550                 e1000_phy_hw_reset(hw);
3551                 mdelay(5);
3552         }
3553         /* Disable GigE link negotiation */
3554         phy_ctrl = er32(PHY_CTRL);
3555         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3556                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3557         ew32(PHY_CTRL, phy_ctrl);
3558
3559         /*
3560          * Call gig speed drop workaround on Gig disable before accessing
3561          * any PHY registers
3562          */
3563         e1000e_gig_downshift_workaround_ich8lan(hw);
3564
3565         /* unable to acquire PCS lock */
3566         return -E1000_ERR_PHY;
3567 }
3568
3569 /**
3570  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3571  *  @hw: pointer to the HW structure
3572  *  @state: boolean value used to set the current Kumeran workaround state
3573  *
3574  *  If ICH8, set the current Kumeran workaround state (enabled - true
3575  *  /disabled - false).
3576  **/
3577 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3578                                                  bool state)
3579 {
3580         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3581
3582         if (hw->mac.type != e1000_ich8lan) {
3583                 e_dbg("Workaround applies to ICH8 only.\n");
3584                 return;
3585         }
3586
3587         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3588 }
3589
3590 /**
3591  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3592  *  @hw: pointer to the HW structure
3593  *
3594  *  Workaround for 82566 power-down on D3 entry:
3595  *    1) disable gigabit link
3596  *    2) write VR power-down enable
3597  *    3) read it back
3598  *  Continue if successful, else issue LCD reset and repeat
3599  **/
3600 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3601 {
3602         u32 reg;
3603         u16 data;
3604         u8  retry = 0;
3605
3606         if (hw->phy.type != e1000_phy_igp_3)
3607                 return;
3608
3609         /* Try the workaround twice (if needed) */
3610         do {
3611                 /* Disable link */
3612                 reg = er32(PHY_CTRL);
3613                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3614                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3615                 ew32(PHY_CTRL, reg);
3616
3617                 /*
3618                  * Call gig speed drop workaround on Gig disable before
3619                  * accessing any PHY registers
3620                  */
3621                 if (hw->mac.type == e1000_ich8lan)
3622                         e1000e_gig_downshift_workaround_ich8lan(hw);
3623
3624                 /* Write VR power-down enable */
3625                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3626                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3627                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3628
3629                 /* Read it back and test */
3630                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3631                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3632                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3633                         break;
3634
3635                 /* Issue PHY reset and repeat at most one more time */
3636                 reg = er32(CTRL);
3637                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3638                 retry++;
3639         } while (retry);
3640 }
3641
3642 /**
3643  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3644  *  @hw: pointer to the HW structure
3645  *
3646  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3647  *  LPLU, Gig disable, MDIC PHY reset):
3648  *    1) Set Kumeran Near-end loopback
3649  *    2) Clear Kumeran Near-end loopback
3650  *  Should only be called for ICH8[m] devices with any 1G Phy.
3651  **/
3652 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3653 {
3654         s32 ret_val;
3655         u16 reg_data;
3656
3657         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3658                 return;
3659
3660         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3661                                       &reg_data);
3662         if (ret_val)
3663                 return;
3664         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3665         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3666                                        reg_data);
3667         if (ret_val)
3668                 return;
3669         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3670         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3671                                        reg_data);
3672 }
3673
3674 /**
3675  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3676  *  @hw: pointer to the HW structure
3677  *
3678  *  During S0 to Sx transition, it is possible the link remains at gig
3679  *  instead of negotiating to a lower speed.  Before going to Sx, set
3680  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3681  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3682  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3683  **/
3684 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3685 {
3686         u32 phy_ctrl;
3687         s32 ret_val;
3688
3689         phy_ctrl = er32(PHY_CTRL);
3690         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3691         ew32(PHY_CTRL, phy_ctrl);
3692
3693         if (hw->mac.type == e1000_ich8lan)
3694                 e1000e_gig_downshift_workaround_ich8lan(hw);
3695
3696         if (hw->mac.type >= e1000_pchlan) {
3697                 e1000_oem_bits_config_ich8lan(hw, false);
3698                 e1000_phy_hw_reset_ich8lan(hw);
3699                 ret_val = hw->phy.ops.acquire(hw);
3700                 if (ret_val)
3701                         return;
3702                 e1000_write_smbus_addr(hw);
3703                 hw->phy.ops.release(hw);
3704         }
3705 }
3706
3707 /**
3708  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3709  *  @hw: pointer to the HW structure
3710  *
3711  *  During Sx to S0 transitions on non-managed devices or managed devices
3712  *  on which PHY resets are not blocked, if the PHY registers cannot be
3713  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3714  *  the PHY.
3715  **/
3716 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3717 {
3718         u32 fwsm;
3719
3720         if (hw->mac.type != e1000_pch2lan)
3721                 return;
3722
3723         fwsm = er32(FWSM);
3724         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3725                 u16 phy_id1, phy_id2;
3726                 s32 ret_val;
3727
3728                 ret_val = hw->phy.ops.acquire(hw);
3729                 if (ret_val) {
3730                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3731                         return;
3732                 }
3733
3734                 /* Test access to the PHY registers by reading the ID regs */
3735                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3736                 if (ret_val)
3737                         goto release;
3738                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3739                 if (ret_val)
3740                         goto release;
3741
3742                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3743                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3744                         goto release;
3745
3746                 e1000_toggle_lanphypc_value_ich8lan(hw);
3747
3748                 hw->phy.ops.release(hw);
3749                 msleep(50);
3750                 e1000_phy_hw_reset(hw);
3751                 msleep(50);
3752                 return;
3753         }
3754
3755 release:
3756         hw->phy.ops.release(hw);
3757
3758         return;
3759 }
3760
3761 /**
3762  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3763  *  @hw: pointer to the HW structure
3764  *
3765  *  Return the LED back to the default configuration.
3766  **/
3767 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3768 {
3769         if (hw->phy.type == e1000_phy_ife)
3770                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3771
3772         ew32(LEDCTL, hw->mac.ledctl_default);
3773         return 0;
3774 }
3775
3776 /**
3777  *  e1000_led_on_ich8lan - Turn LEDs on
3778  *  @hw: pointer to the HW structure
3779  *
3780  *  Turn on the LEDs.
3781  **/
3782 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3783 {
3784         if (hw->phy.type == e1000_phy_ife)
3785                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3786                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3787
3788         ew32(LEDCTL, hw->mac.ledctl_mode2);
3789         return 0;
3790 }
3791
3792 /**
3793  *  e1000_led_off_ich8lan - Turn LEDs off
3794  *  @hw: pointer to the HW structure
3795  *
3796  *  Turn off the LEDs.
3797  **/
3798 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3799 {
3800         if (hw->phy.type == e1000_phy_ife)
3801                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3802                                 (IFE_PSCL_PROBE_MODE |
3803                                  IFE_PSCL_PROBE_LEDS_OFF));
3804
3805         ew32(LEDCTL, hw->mac.ledctl_mode1);
3806         return 0;
3807 }
3808
3809 /**
3810  *  e1000_setup_led_pchlan - Configures SW controllable LED
3811  *  @hw: pointer to the HW structure
3812  *
3813  *  This prepares the SW controllable LED for use.
3814  **/
3815 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3816 {
3817         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3818 }
3819
3820 /**
3821  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3822  *  @hw: pointer to the HW structure
3823  *
3824  *  Return the LED back to the default configuration.
3825  **/
3826 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3827 {
3828         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3829 }
3830
3831 /**
3832  *  e1000_led_on_pchlan - Turn LEDs on
3833  *  @hw: pointer to the HW structure
3834  *
3835  *  Turn on the LEDs.
3836  **/
3837 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3838 {
3839         u16 data = (u16)hw->mac.ledctl_mode2;
3840         u32 i, led;
3841
3842         /*
3843          * If no link, then turn LED on by setting the invert bit
3844          * for each LED that's mode is "link_up" in ledctl_mode2.
3845          */
3846         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3847                 for (i = 0; i < 3; i++) {
3848                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3849                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3850                             E1000_LEDCTL_MODE_LINK_UP)
3851                                 continue;
3852                         if (led & E1000_PHY_LED0_IVRT)
3853                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3854                         else
3855                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3856                 }
3857         }
3858
3859         return e1e_wphy(hw, HV_LED_CONFIG, data);
3860 }
3861
3862 /**
3863  *  e1000_led_off_pchlan - Turn LEDs off
3864  *  @hw: pointer to the HW structure
3865  *
3866  *  Turn off the LEDs.
3867  **/
3868 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3869 {
3870         u16 data = (u16)hw->mac.ledctl_mode1;
3871         u32 i, led;
3872
3873         /*
3874          * If no link, then turn LED off by clearing the invert bit
3875          * for each LED that's mode is "link_up" in ledctl_mode1.
3876          */
3877         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3878                 for (i = 0; i < 3; i++) {
3879                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3880                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3881                             E1000_LEDCTL_MODE_LINK_UP)
3882                                 continue;
3883                         if (led & E1000_PHY_LED0_IVRT)
3884                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3885                         else
3886                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3887                 }
3888         }
3889
3890         return e1e_wphy(hw, HV_LED_CONFIG, data);
3891 }
3892
3893 /**
3894  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3895  *  @hw: pointer to the HW structure
3896  *
3897  *  Read appropriate register for the config done bit for completion status
3898  *  and configure the PHY through s/w for EEPROM-less parts.
3899  *
3900  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3901  *  config done bit, so only an error is logged and continues.  If we were
3902  *  to return with error, EEPROM-less silicon would not be able to be reset
3903  *  or change link.
3904  **/
3905 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3906 {
3907         s32 ret_val = 0;
3908         u32 bank = 0;
3909         u32 status;
3910
3911         e1000e_get_cfg_done(hw);
3912
3913         /* Wait for indication from h/w that it has completed basic config */
3914         if (hw->mac.type >= e1000_ich10lan) {
3915                 e1000_lan_init_done_ich8lan(hw);
3916         } else {
3917                 ret_val = e1000e_get_auto_rd_done(hw);
3918                 if (ret_val) {
3919                         /*
3920                          * When auto config read does not complete, do not
3921                          * return with an error. This can happen in situations
3922                          * where there is no eeprom and prevents getting link.
3923                          */
3924                         e_dbg("Auto Read Done did not complete\n");
3925                         ret_val = 0;
3926                 }
3927         }
3928
3929         /* Clear PHY Reset Asserted bit */
3930         status = er32(STATUS);
3931         if (status & E1000_STATUS_PHYRA)
3932                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3933         else
3934                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3935
3936         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3937         if (hw->mac.type <= e1000_ich9lan) {
3938                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3939                     (hw->phy.type == e1000_phy_igp_3)) {
3940                         e1000e_phy_init_script_igp3(hw);
3941                 }
3942         } else {
3943                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3944                         /* Maybe we should do a basic PHY config */
3945                         e_dbg("EEPROM not present\n");
3946                         ret_val = -E1000_ERR_CONFIG;
3947                 }
3948         }
3949
3950         return ret_val;
3951 }
3952
3953 /**
3954  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3955  * @hw: pointer to the HW structure
3956  *
3957  * In the case of a PHY power down to save power, or to turn off link during a
3958  * driver unload, or wake on lan is not enabled, remove the link.
3959  **/
3960 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3961 {
3962         /* If the management interface is not enabled, then power down */
3963         if (!(hw->mac.ops.check_mng_mode(hw) ||
3964               hw->phy.ops.check_reset_block(hw)))
3965                 e1000_power_down_phy_copper(hw);
3966 }
3967
3968 /**
3969  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3970  *  @hw: pointer to the HW structure
3971  *
3972  *  Clears hardware counters specific to the silicon family and calls
3973  *  clear_hw_cntrs_generic to clear all general purpose counters.
3974  **/
3975 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3976 {
3977         u16 phy_data;
3978         s32 ret_val;
3979
3980         e1000e_clear_hw_cntrs_base(hw);
3981
3982         er32(ALGNERRC);
3983         er32(RXERRC);
3984         er32(TNCRS);
3985         er32(CEXTERR);
3986         er32(TSCTC);
3987         er32(TSCTFC);
3988
3989         er32(MGTPRC);
3990         er32(MGTPDC);
3991         er32(MGTPTC);
3992
3993         er32(IAC);
3994         er32(ICRXOC);
3995
3996         /* Clear PHY statistics registers */
3997         if ((hw->phy.type == e1000_phy_82578) ||
3998             (hw->phy.type == e1000_phy_82579) ||
3999             (hw->phy.type == e1000_phy_82577)) {
4000                 ret_val = hw->phy.ops.acquire(hw);
4001                 if (ret_val)
4002                         return;
4003                 ret_val = hw->phy.ops.set_page(hw,
4004                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4005                 if (ret_val)
4006                         goto release;
4007                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4008                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4009                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4010                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4011                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4012                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4013                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4014                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4015                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4016                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4017                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4018                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4019                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4020                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4021 release:
4022                 hw->phy.ops.release(hw);
4023         }
4024 }
4025
4026 static const struct e1000_mac_operations ich8_mac_ops = {
4027         .id_led_init            = e1000e_id_led_init,
4028         /* check_mng_mode dependent on mac type */
4029         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4030         /* cleanup_led dependent on mac type */
4031         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4032         .get_bus_info           = e1000_get_bus_info_ich8lan,
4033         .set_lan_id             = e1000_set_lan_id_single_port,
4034         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4035         /* led_on dependent on mac type */
4036         /* led_off dependent on mac type */
4037         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4038         .reset_hw               = e1000_reset_hw_ich8lan,
4039         .init_hw                = e1000_init_hw_ich8lan,
4040         .setup_link             = e1000_setup_link_ich8lan,
4041         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4042         /* id_led_init dependent on mac type */
4043 };
4044
4045 static const struct e1000_phy_operations ich8_phy_ops = {
4046         .acquire                = e1000_acquire_swflag_ich8lan,
4047         .check_reset_block      = e1000_check_reset_block_ich8lan,
4048         .commit                 = NULL,
4049         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4050         .get_cable_length       = e1000e_get_cable_length_igp_2,
4051         .read_reg               = e1000e_read_phy_reg_igp,
4052         .release                = e1000_release_swflag_ich8lan,
4053         .reset                  = e1000_phy_hw_reset_ich8lan,
4054         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4055         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4056         .write_reg              = e1000e_write_phy_reg_igp,
4057 };
4058
4059 static const struct e1000_nvm_operations ich8_nvm_ops = {
4060         .acquire                = e1000_acquire_nvm_ich8lan,
4061         .read                   = e1000_read_nvm_ich8lan,
4062         .release                = e1000_release_nvm_ich8lan,
4063         .update                 = e1000_update_nvm_checksum_ich8lan,
4064         .valid_led_default      = e1000_valid_led_default_ich8lan,
4065         .validate               = e1000_validate_nvm_checksum_ich8lan,
4066         .write                  = e1000_write_nvm_ich8lan,
4067 };
4068
4069 const struct e1000_info e1000_ich8_info = {
4070         .mac                    = e1000_ich8lan,
4071         .flags                  = FLAG_HAS_WOL
4072                                   | FLAG_IS_ICH
4073                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4074                                   | FLAG_HAS_AMT
4075                                   | FLAG_HAS_FLASH
4076                                   | FLAG_APME_IN_WUC,
4077         .pba                    = 8,
4078         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4079         .get_variants           = e1000_get_variants_ich8lan,
4080         .mac_ops                = &ich8_mac_ops,
4081         .phy_ops                = &ich8_phy_ops,
4082         .nvm_ops                = &ich8_nvm_ops,
4083 };
4084
4085 const struct e1000_info e1000_ich9_info = {
4086         .mac                    = e1000_ich9lan,
4087         .flags                  = FLAG_HAS_JUMBO_FRAMES
4088                                   | FLAG_IS_ICH
4089                                   | FLAG_HAS_WOL
4090                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4091                                   | FLAG_HAS_AMT
4092                                   | FLAG_HAS_ERT
4093                                   | FLAG_HAS_FLASH
4094                                   | FLAG_APME_IN_WUC,
4095         .pba                    = 10,
4096         .max_hw_frame_size      = DEFAULT_JUMBO,
4097         .get_variants           = e1000_get_variants_ich8lan,
4098         .mac_ops                = &ich8_mac_ops,
4099         .phy_ops                = &ich8_phy_ops,
4100         .nvm_ops                = &ich8_nvm_ops,
4101 };
4102
4103 const struct e1000_info e1000_ich10_info = {
4104         .mac                    = e1000_ich10lan,
4105         .flags                  = FLAG_HAS_JUMBO_FRAMES
4106                                   | FLAG_IS_ICH
4107                                   | FLAG_HAS_WOL
4108                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4109                                   | FLAG_HAS_AMT
4110                                   | FLAG_HAS_ERT
4111                                   | FLAG_HAS_FLASH
4112                                   | FLAG_APME_IN_WUC,
4113         .pba                    = 10,
4114         .max_hw_frame_size      = DEFAULT_JUMBO,
4115         .get_variants           = e1000_get_variants_ich8lan,
4116         .mac_ops                = &ich8_mac_ops,
4117         .phy_ops                = &ich8_phy_ops,
4118         .nvm_ops                = &ich8_nvm_ops,
4119 };
4120
4121 const struct e1000_info e1000_pch_info = {
4122         .mac                    = e1000_pchlan,
4123         .flags                  = FLAG_IS_ICH
4124                                   | FLAG_HAS_WOL
4125                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4126                                   | FLAG_HAS_AMT
4127                                   | FLAG_HAS_FLASH
4128                                   | FLAG_HAS_JUMBO_FRAMES
4129                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4130                                   | FLAG_APME_IN_WUC,
4131         .flags2                 = FLAG2_HAS_PHY_STATS,
4132         .pba                    = 26,
4133         .max_hw_frame_size      = 4096,
4134         .get_variants           = e1000_get_variants_ich8lan,
4135         .mac_ops                = &ich8_mac_ops,
4136         .phy_ops                = &ich8_phy_ops,
4137         .nvm_ops                = &ich8_nvm_ops,
4138 };
4139
4140 const struct e1000_info e1000_pch2_info = {
4141         .mac                    = e1000_pch2lan,
4142         .flags                  = FLAG_IS_ICH
4143                                   | FLAG_HAS_WOL
4144                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4145                                   | FLAG_HAS_AMT
4146                                   | FLAG_HAS_FLASH
4147                                   | FLAG_HAS_JUMBO_FRAMES
4148                                   | FLAG_APME_IN_WUC,
4149         .flags2                 = FLAG2_HAS_PHY_STATS
4150                                   | FLAG2_HAS_EEE,
4151         .pba                    = 26,
4152         .max_hw_frame_size      = DEFAULT_JUMBO,
4153         .get_variants           = e1000_get_variants_ich8lan,
4154         .mac_ops                = &ich8_mac_ops,
4155         .phy_ops                = &ich8_phy_ops,
4156         .nvm_ops                = &ich8_nvm_ops,
4157 };