drivers/net/ethernet/freescale/ucc_geth.c

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *         Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Gigabit Ethernet Driver
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/slab.h>
  19 #include <linux/stddef.h>
  20 #include <linux/module.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/mm.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/mii.h>
  29 #include <linux/phy.h>
  30 #include <linux/workqueue.h>
  31 #include <linux/of_mdio.h>
  32 #include <linux/of_net.h>
  33 #include <linux/of_platform.h>
  34
  35 #include <asm/uaccess.h>
  36 #include <asm/irq.h>
  37 #include <asm/io.h>
  38 #include <asm/immap_qe.h>
  39 #include <asm/qe.h>
  40 #include <asm/ucc.h>
  41 #include <asm/ucc_fast.h>
  42 #include <asm/machdep.h>
  43
  44 #include "ucc_geth.h"
  45 #include "fsl_pq_mdio.h"
  46
  47 #undef DEBUG
  48
  49 #define ugeth_printk(level, format, arg...)  \
  50         printk(level format "\n", ## arg)
  51
  52 #define ugeth_dbg(format, arg...)            \
  53         ugeth_printk(KERN_DEBUG , format , ## arg)
  54 #define ugeth_err(format, arg...)            \
  55         ugeth_printk(KERN_ERR , format , ## arg)
  56 #define ugeth_info(format, arg...)           \
  57         ugeth_printk(KERN_INFO , format , ## arg)
  58 #define ugeth_warn(format, arg...)           \
  59         ugeth_printk(KERN_WARNING , format , ## arg)
  60
  61 #ifdef UGETH_VERBOSE_DEBUG
  62 #define ugeth_vdbg ugeth_dbg
  63 #else
  64 #define ugeth_vdbg(fmt, args...) do { } while (0)
  65 #endif                          /* UGETH_VERBOSE_DEBUG */
  66 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
  67
  68
  69 static DEFINE_SPINLOCK(ugeth_lock);
  70
  71 static struct {
  72         u32 msg_enable;
  73 } debug = { -1 };
  74
  75 module_param_named(debug, debug.msg_enable, int, 0);
  76 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
  77
  78 static struct ucc_geth_info ugeth_primary_info = {
  79         .uf_info = {
  80                     .bd_mem_part = MEM_PART_SYSTEM,
  81                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  82                     .max_rx_buf_length = 1536,
  83                     /* adjusted at startup if max-speed 1000 */
  84                     .urfs = UCC_GETH_URFS_INIT,
  85                     .urfet = UCC_GETH_URFET_INIT,
  86                     .urfset = UCC_GETH_URFSET_INIT,
  87                     .utfs = UCC_GETH_UTFS_INIT,
  88                     .utfet = UCC_GETH_UTFET_INIT,
  89                     .utftt = UCC_GETH_UTFTT_INIT,
  90                     .ufpt = 256,
  91                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  92                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  93                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  94                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  95                     .tcrc = UCC_FAST_16_BIT_CRC,
  96                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  97                     },
  98         .numQueuesTx = 1,
  99         .numQueuesRx = 1,
 100         .extendedFilteringChainPointer = ((uint32_t) NULL),
 101         .typeorlen = 3072 /*1536 */ ,
 102         .nonBackToBackIfgPart1 = 0x40,
 103         .nonBackToBackIfgPart2 = 0x60,
 104         .miminumInterFrameGapEnforcement = 0x50,
 105         .backToBackInterFrameGap = 0x60,
 106         .mblinterval = 128,
 107         .nortsrbytetime = 5,
 108         .fracsiz = 1,
 109         .strictpriorityq = 0xff,
 110         .altBebTruncation = 0xa,
 111         .excessDefer = 1,
 112         .maxRetransmission = 0xf,
 113         .collisionWindow = 0x37,
 114         .receiveFlowControl = 1,
 115         .transmitFlowControl = 1,
 116         .maxGroupAddrInHash = 4,
 117         .maxIndAddrInHash = 4,
 118         .prel = 7,
 119         .maxFrameLength = 1518,
 120         .minFrameLength = 64,
 121         .maxD1Length = 1520,
 122         .maxD2Length = 1520,
 123         .vlantype = 0x8100,
 124         .ecamptr = ((uint32_t) NULL),
 125         .eventRegMask = UCCE_OTHER,
 126         .pausePeriod = 0xf000,
 127         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 128         .bdRingLenTx = {
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN,
 132                         TX_BD_RING_LEN,
 133                         TX_BD_RING_LEN,
 134                         TX_BD_RING_LEN,
 135                         TX_BD_RING_LEN,
 136                         TX_BD_RING_LEN},
 137
 138         .bdRingLenRx = {
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN,
 142                         RX_BD_RING_LEN,
 143                         RX_BD_RING_LEN,
 144                         RX_BD_RING_LEN,
 145                         RX_BD_RING_LEN,
 146                         RX_BD_RING_LEN},
 147
 148         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 149         .largestexternallookupkeysize =
 150             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 151         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
 152                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
 153                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
 154         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 155         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 156         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 157         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 158         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 159         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
 160         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
 161         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 162         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 163 };
 164
 165 static struct ucc_geth_info ugeth_info[8];
 166
 167 #ifdef DEBUG
 168 static void mem_disp(u8 *addr, int size)
 169 {
 170         u8 *i;
 171         int size16Aling = (size >> 4) << 4;
 172         int size4Aling = (size >> 2) << 2;
 173         int notAlign = 0;
 174         if (size % 16)
 175                 notAlign = 1;
 176
 177         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 178                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 179                        (u32) i,
 180                        *((u32 *) (i)),
 181                        *((u32 *) (i + 4)),
 182                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 183         if (notAlign == 1)
 184                 printk("0x%08x: ", (u32) i);
 185         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 186                 printk("%08x ", *((u32 *) (i)));
 187         for (; (u32) i < (u32) addr + size; i++)
 188                 printk("%02x", *((u8 *) (i)));
 189         if (notAlign == 1)
 190                 printk("\r\n");
 191 }
 192 #endif /* DEBUG */
 193
 194 static struct list_head *dequeue(struct list_head *lh)
 195 {
 196         unsigned long flags;
 197
 198         spin_lock_irqsave(&ugeth_lock, flags);
 199         if (!list_empty(lh)) {
 200                 struct list_head *node = lh->next;
 201                 list_del(node);
 202                 spin_unlock_irqrestore(&ugeth_lock, flags);
 203                 return node;
 204         } else {
 205                 spin_unlock_irqrestore(&ugeth_lock, flags);
 206                 return NULL;
 207         }
 208 }
 209
 210 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
 211                 u8 __iomem *bd)
 212 {
 213         struct sk_buff *skb = NULL;
 214
 215         skb = __skb_dequeue(&ugeth->rx_recycle);
 216         if (!skb)
 217                 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
 218                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 219         if (skb == NULL)
 220                 return NULL;
 221
 222         /* We need the data buffer to be aligned properly.  We will reserve
 223          * as many bytes as needed to align the data properly
 224          */
 225         skb_reserve(skb,
 226                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 227                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 228                                               1)));
 229
 230         skb->dev = ugeth->ndev;
 231
 232         out_be32(&((struct qe_bd __iomem *)bd)->buf,
 233                       dma_map_single(ugeth->dev,
 234                                      skb->data,
 235                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 236                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 237                                      DMA_FROM_DEVICE));
 238
 239         out_be32((u32 __iomem *)bd,
 240                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
 241
 242         return skb;
 243 }
 244
 245 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 246 {
 247         u8 __iomem *bd;
 248         u32 bd_status;
 249         struct sk_buff *skb;
 250         int i;
 251
 252         bd = ugeth->p_rx_bd_ring[rxQ];
 253         i = 0;
 254
 255         do {
 256                 bd_status = in_be32((u32 __iomem *)bd);
 257                 skb = get_new_skb(ugeth, bd);
 258
 259                 if (!skb)       /* If can not allocate data buffer,
 260                                 abort. Cleanup will be elsewhere */
 261                         return -ENOMEM;
 262
 263                 ugeth->rx_skbuff[rxQ][i] = skb;
 264
 265                 /* advance the BD pointer */
 266                 bd += sizeof(struct qe_bd);
 267                 i++;
 268         } while (!(bd_status & R_W));
 269
 270         return 0;
 271 }
 272
 273 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 274                                   u32 *p_start,
 275                                   u8 num_entries,
 276                                   u32 thread_size,
 277                                   u32 thread_alignment,
 278                                   unsigned int risc,
 279                                   int skip_page_for_first_entry)
 280 {
 281         u32 init_enet_offset;
 282         u8 i;
 283         int snum;
 284
 285         for (i = 0; i < num_entries; i++) {
 286                 if ((snum = qe_get_snum()) < 0) {
 287                         if (netif_msg_ifup(ugeth))
 288                                 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
 289                         return snum;
 290                 }
 291                 if ((i == 0) && skip_page_for_first_entry)
 292                 /* First entry of Rx does not have page */
 293                         init_enet_offset = 0;
 294                 else {
 295                         init_enet_offset =
 296                             qe_muram_alloc(thread_size, thread_alignment);
 297                         if (IS_ERR_VALUE(init_enet_offset)) {
 298                                 if (netif_msg_ifup(ugeth))
 299                                         ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
 300                                 qe_put_snum((u8) snum);
 301                                 return -ENOMEM;
 302                         }
 303                 }
 304                 *(p_start++) =
 305                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 306                     | risc;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 313                                     u32 *p_start,
 314                                     u8 num_entries,
 315                                     unsigned int risc,
 316                                     int skip_page_for_first_entry)
 317 {
 318         u32 init_enet_offset;
 319         u8 i;
 320         int snum;
 321
 322         for (i = 0; i < num_entries; i++) {
 323                 u32 val = *p_start;
 324
 325                 /* Check that this entry was actually valid --
 326                 needed in case failed in allocations */
 327                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 328                         snum =
 329                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 330                             ENET_INIT_PARAM_SNUM_SHIFT;
 331                         qe_put_snum((u8) snum);
 332                         if (!((i == 0) && skip_page_for_first_entry)) {
 333                         /* First entry of Rx does not have page */
 334                                 init_enet_offset =
 335                                     (val & ENET_INIT_PARAM_PTR_MASK);
 336                                 qe_muram_free(init_enet_offset);
 337                         }
 338                         *p_start++ = 0;
 339                 }
 340         }
 341
 342         return 0;
 343 }
 344
 345 #ifdef DEBUG
 346 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 347                                   u32 __iomem *p_start,
 348                                   u8 num_entries,
 349                                   u32 thread_size,
 350                                   unsigned int risc,
 351                                   int skip_page_for_first_entry)
 352 {
 353         u32 init_enet_offset;
 354         u8 i;
 355         int snum;
 356
 357         for (i = 0; i < num_entries; i++) {
 358                 u32 val = in_be32(p_start);
 359
 360                 /* Check that this entry was actually valid --
 361                 needed in case failed in allocations */
 362                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 363                         snum =
 364                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 365                             ENET_INIT_PARAM_SNUM_SHIFT;
 366                         qe_put_snum((u8) snum);
 367                         if (!((i == 0) && skip_page_for_first_entry)) {
 368                         /* First entry of Rx does not have page */
 369                                 init_enet_offset =
 370                                     (in_be32(p_start) &
 371                                      ENET_INIT_PARAM_PTR_MASK);
 372                                 ugeth_info("Init enet entry %d:", i);
 373                                 ugeth_info("Base address: 0x%08x",
 374                                            (u32)
 375                                            qe_muram_addr(init_enet_offset));
 376                                 mem_disp(qe_muram_addr(init_enet_offset),
 377                                          thread_size);
 378                         }
 379                         p_start++;
 380                 }
 381         }
 382
 383         return 0;
 384 }
 385 #endif
 386
 387 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 388 {
 389         kfree(enet_addr_cont);
 390 }
 391
 392 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
 393 {
 394         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 395         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 396         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 397 }
 398
 399 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 400 {
 401         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 402
 403         if (!(paddr_num < NUM_OF_PADDRS)) {
 404                 ugeth_warn("%s: Illagel paddr_num.", __func__);
 405                 return -EINVAL;
 406         }
 407
 408         p_82xx_addr_filt =
 409             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 410             addressfiltering;
 411
 412         /* Writing address ff.ff.ff.ff.ff.ff disables address
 413         recognition for this register */
 414         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 415         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 416         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 417
 418         return 0;
 419 }
 420
 421 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 422                                 u8 *p_enet_addr)
 423 {
 424         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 425         u32 cecr_subblock;
 426
 427         p_82xx_addr_filt =
 428             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 429             addressfiltering;
 430
 431         cecr_subblock =
 432             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 433
 434         /* Ethernet frames are defined in Little Endian mode,
 435         therefore to insert */
 436         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 437
 438         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 439
 440         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 441                      QE_CR_PROTOCOL_ETHERNET, 0);
 442 }
 443
 444 static inline int compare_addr(u8 **addr1, u8 **addr2)
 445 {
 446         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
 447 }
 448
 449 #ifdef DEBUG
 450 static void get_statistics(struct ucc_geth_private *ugeth,
 451                            struct ucc_geth_tx_firmware_statistics *
 452                            tx_firmware_statistics,
 453                            struct ucc_geth_rx_firmware_statistics *
 454                            rx_firmware_statistics,
 455                            struct ucc_geth_hardware_statistics *hardware_statistics)
 456 {
 457         struct ucc_fast __iomem *uf_regs;
 458         struct ucc_geth __iomem *ug_regs;
 459         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 460         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 461
 462         ug_regs = ugeth->ug_regs;
 463         uf_regs = (struct ucc_fast __iomem *) ug_regs;
 464         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 465         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 466
 467         /* Tx firmware only if user handed pointer and driver actually
 468         gathers Tx firmware statistics */
 469         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 470                 tx_firmware_statistics->sicoltx =
 471                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 472                 tx_firmware_statistics->mulcoltx =
 473                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 474                 tx_firmware_statistics->latecoltxfr =
 475                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 476                 tx_firmware_statistics->frabortduecol =
 477                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 478                 tx_firmware_statistics->frlostinmactxer =
 479                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 480                 tx_firmware_statistics->carriersenseertx =
 481                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 482                 tx_firmware_statistics->frtxok =
 483                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 484                 tx_firmware_statistics->txfrexcessivedefer =
 485                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 486                 tx_firmware_statistics->txpkts256 =
 487                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 488                 tx_firmware_statistics->txpkts512 =
 489                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 490                 tx_firmware_statistics->txpkts1024 =
 491                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 492                 tx_firmware_statistics->txpktsjumbo =
 493                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 494         }
 495
 496         /* Rx firmware only if user handed pointer and driver actually
 497          * gathers Rx firmware statistics */
 498         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 499                 int i;
 500                 rx_firmware_statistics->frrxfcser =
 501                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 502                 rx_firmware_statistics->fraligner =
 503                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 504                 rx_firmware_statistics->inrangelenrxer =
 505                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 506                 rx_firmware_statistics->outrangelenrxer =
 507                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 508                 rx_firmware_statistics->frtoolong =
 509                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 510                 rx_firmware_statistics->runt =
 511                     in_be32(&p_rx_fw_statistics_pram->runt);
 512                 rx_firmware_statistics->verylongevent =
 513                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 514                 rx_firmware_statistics->symbolerror =
 515                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 516                 rx_firmware_statistics->dropbsy =
 517                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 518                 for (i = 0; i < 0x8; i++)
 519                         rx_firmware_statistics->res0[i] =
 520                             p_rx_fw_statistics_pram->res0[i];
 521                 rx_firmware_statistics->mismatchdrop =
 522                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 523                 rx_firmware_statistics->underpkts =
 524                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 525                 rx_firmware_statistics->pkts256 =
 526                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 527                 rx_firmware_statistics->pkts512 =
 528                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 529                 rx_firmware_statistics->pkts1024 =
 530                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 531                 rx_firmware_statistics->pktsjumbo =
 532                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 533                 rx_firmware_statistics->frlossinmacer =
 534                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 535                 rx_firmware_statistics->pausefr =
 536                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 537                 for (i = 0; i < 0x4; i++)
 538                         rx_firmware_statistics->res1[i] =
 539                             p_rx_fw_statistics_pram->res1[i];
 540                 rx_firmware_statistics->removevlan =
 541                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 542                 rx_firmware_statistics->replacevlan =
 543                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 544                 rx_firmware_statistics->insertvlan =
 545                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 546         }
 547
 548         /* Hardware only if user handed pointer and driver actually
 549         gathers hardware statistics */
 550         if (hardware_statistics &&
 551             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
 552                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 553                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 554                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 555                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 556                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 557                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 558                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 559                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 560                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 561                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 562                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 563                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 564                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 565                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 566                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 567         }
 568 }
 569
 570 static void dump_bds(struct ucc_geth_private *ugeth)
 571 {
 572         int i;
 573         int length;
 574
 575         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 576                 if (ugeth->p_tx_bd_ring[i]) {
 577                         length =
 578                             (ugeth->ug_info->bdRingLenTx[i] *
 579                              sizeof(struct qe_bd));
 580                         ugeth_info("TX BDs[%d]", i);
 581                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 582                 }
 583         }
 584         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 585                 if (ugeth->p_rx_bd_ring[i]) {
 586                         length =
 587                             (ugeth->ug_info->bdRingLenRx[i] *
 588                              sizeof(struct qe_bd));
 589                         ugeth_info("RX BDs[%d]", i);
 590                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 591                 }
 592         }
 593 }
 594
 595 static void dump_regs(struct ucc_geth_private *ugeth)
 596 {
 597         int i;
 598
 599         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1);
 600         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
 601
 602         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
 603                    (u32) & ugeth->ug_regs->maccfg1,
 604                    in_be32(&ugeth->ug_regs->maccfg1));
 605         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
 606                    (u32) & ugeth->ug_regs->maccfg2,
 607                    in_be32(&ugeth->ug_regs->maccfg2));
 608         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
 609                    (u32) & ugeth->ug_regs->ipgifg,
 610                    in_be32(&ugeth->ug_regs->ipgifg));
 611         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
 612                    (u32) & ugeth->ug_regs->hafdup,
 613                    in_be32(&ugeth->ug_regs->hafdup));
 614         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
 615                    (u32) & ugeth->ug_regs->ifctl,
 616                    in_be32(&ugeth->ug_regs->ifctl));
 617         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
 618                    (u32) & ugeth->ug_regs->ifstat,
 619                    in_be32(&ugeth->ug_regs->ifstat));
 620         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
 621                    (u32) & ugeth->ug_regs->macstnaddr1,
 622                    in_be32(&ugeth->ug_regs->macstnaddr1));
 623         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
 624                    (u32) & ugeth->ug_regs->macstnaddr2,
 625                    in_be32(&ugeth->ug_regs->macstnaddr2));
 626         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
 627                    (u32) & ugeth->ug_regs->uempr,
 628                    in_be32(&ugeth->ug_regs->uempr));
 629         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
 630                    (u32) & ugeth->ug_regs->utbipar,
 631                    in_be32(&ugeth->ug_regs->utbipar));
 632         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
 633                    (u32) & ugeth->ug_regs->uescr,
 634                    in_be16(&ugeth->ug_regs->uescr));
 635         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
 636                    (u32) & ugeth->ug_regs->tx64,
 637                    in_be32(&ugeth->ug_regs->tx64));
 638         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
 639                    (u32) & ugeth->ug_regs->tx127,
 640                    in_be32(&ugeth->ug_regs->tx127));
 641         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
 642                    (u32) & ugeth->ug_regs->tx255,
 643                    in_be32(&ugeth->ug_regs->tx255));
 644         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
 645                    (u32) & ugeth->ug_regs->rx64,
 646                    in_be32(&ugeth->ug_regs->rx64));
 647         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
 648                    (u32) & ugeth->ug_regs->rx127,
 649                    in_be32(&ugeth->ug_regs->rx127));
 650         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
 651                    (u32) & ugeth->ug_regs->rx255,
 652                    in_be32(&ugeth->ug_regs->rx255));
 653         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
 654                    (u32) & ugeth->ug_regs->txok,
 655                    in_be32(&ugeth->ug_regs->txok));
 656         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
 657                    (u32) & ugeth->ug_regs->txcf,
 658                    in_be16(&ugeth->ug_regs->txcf));
 659         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
 660                    (u32) & ugeth->ug_regs->tmca,
 661                    in_be32(&ugeth->ug_regs->tmca));
 662         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
 663                    (u32) & ugeth->ug_regs->tbca,
 664                    in_be32(&ugeth->ug_regs->tbca));
 665         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
 666                    (u32) & ugeth->ug_regs->rxfok,
 667                    in_be32(&ugeth->ug_regs->rxfok));
 668         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
 669                    (u32) & ugeth->ug_regs->rxbok,
 670                    in_be32(&ugeth->ug_regs->rxbok));
 671         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
 672                    (u32) & ugeth->ug_regs->rbyt,
 673                    in_be32(&ugeth->ug_regs->rbyt));
 674         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
 675                    (u32) & ugeth->ug_regs->rmca,
 676                    in_be32(&ugeth->ug_regs->rmca));
 677         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
 678                    (u32) & ugeth->ug_regs->rbca,
 679                    in_be32(&ugeth->ug_regs->rbca));
 680         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
 681                    (u32) & ugeth->ug_regs->scar,
 682                    in_be32(&ugeth->ug_regs->scar));
 683         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
 684                    (u32) & ugeth->ug_regs->scam,
 685                    in_be32(&ugeth->ug_regs->scam));
 686
 687         if (ugeth->p_thread_data_tx) {
 688                 int numThreadsTxNumerical;
 689                 switch (ugeth->ug_info->numThreadsTx) {
 690                 case UCC_GETH_NUM_OF_THREADS_1:
 691                         numThreadsTxNumerical = 1;
 692                         break;
 693                 case UCC_GETH_NUM_OF_THREADS_2:
 694                         numThreadsTxNumerical = 2;
 695                         break;
 696                 case UCC_GETH_NUM_OF_THREADS_4:
 697                         numThreadsTxNumerical = 4;
 698                         break;
 699                 case UCC_GETH_NUM_OF_THREADS_6:
 700                         numThreadsTxNumerical = 6;
 701                         break;
 702                 case UCC_GETH_NUM_OF_THREADS_8:
 703                         numThreadsTxNumerical = 8;
 704                         break;
 705                 default:
 706                         numThreadsTxNumerical = 0;
 707                         break;
 708                 }
 709
 710                 ugeth_info("Thread data TXs:");
 711                 ugeth_info("Base address: 0x%08x",
 712                            (u32) ugeth->p_thread_data_tx);
 713                 for (i = 0; i < numThreadsTxNumerical; i++) {
 714                         ugeth_info("Thread data TX[%d]:", i);
 715                         ugeth_info("Base address: 0x%08x",
 716                                    (u32) & ugeth->p_thread_data_tx[i]);
 717                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 718                                  sizeof(struct ucc_geth_thread_data_tx));
 719                 }
 720         }
 721         if (ugeth->p_thread_data_rx) {
 722                 int numThreadsRxNumerical;
 723                 switch (ugeth->ug_info->numThreadsRx) {
 724                 case UCC_GETH_NUM_OF_THREADS_1:
 725                         numThreadsRxNumerical = 1;
 726                         break;
 727                 case UCC_GETH_NUM_OF_THREADS_2:
 728                         numThreadsRxNumerical = 2;
 729                         break;
 730                 case UCC_GETH_NUM_OF_THREADS_4:
 731                         numThreadsRxNumerical = 4;
 732                         break;
 733                 case UCC_GETH_NUM_OF_THREADS_6:
 734                         numThreadsRxNumerical = 6;
 735                         break;
 736                 case UCC_GETH_NUM_OF_THREADS_8:
 737                         numThreadsRxNumerical = 8;
 738                         break;
 739                 default:
 740                         numThreadsRxNumerical = 0;
 741                         break;
 742                 }
 743
 744                 ugeth_info("Thread data RX:");
 745                 ugeth_info("Base address: 0x%08x",
 746                            (u32) ugeth->p_thread_data_rx);
 747                 for (i = 0; i < numThreadsRxNumerical; i++) {
 748                         ugeth_info("Thread data RX[%d]:", i);
 749                         ugeth_info("Base address: 0x%08x",
 750                                    (u32) & ugeth->p_thread_data_rx[i]);
 751                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 752                                  sizeof(struct ucc_geth_thread_data_rx));
 753                 }
 754         }
 755         if (ugeth->p_exf_glbl_param) {
 756                 ugeth_info("EXF global param:");
 757                 ugeth_info("Base address: 0x%08x",
 758                            (u32) ugeth->p_exf_glbl_param);
 759                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 760                          sizeof(*ugeth->p_exf_glbl_param));
 761         }
 762         if (ugeth->p_tx_glbl_pram) {
 763                 ugeth_info("TX global param:");
 764                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
 765                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
 766                            (u32) & ugeth->p_tx_glbl_pram->temoder,
 767                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
 768                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
 769                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
 770                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 771                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
 772                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
 773                            in_be32(&ugeth->p_tx_glbl_pram->
 774                                    schedulerbasepointer));
 775                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
 776                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
 777                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 778                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
 779                            (u32) & ugeth->p_tx_glbl_pram->tstate,
 780                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
 781                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
 782                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
 783                            ugeth->p_tx_glbl_pram->iphoffset[0]);
 784                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
 785                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
 786                            ugeth->p_tx_glbl_pram->iphoffset[1]);
 787                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
 788                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
 789                            ugeth->p_tx_glbl_pram->iphoffset[2]);
 790                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
 791                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
 792                            ugeth->p_tx_glbl_pram->iphoffset[3]);
 793                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
 794                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
 795                            ugeth->p_tx_glbl_pram->iphoffset[4]);
 796                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
 797                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
 798                            ugeth->p_tx_glbl_pram->iphoffset[5]);
 799                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
 800                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
 801                            ugeth->p_tx_glbl_pram->iphoffset[6]);
 802                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
 803                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
 804                            ugeth->p_tx_glbl_pram->iphoffset[7]);
 805                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
 806                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
 807                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 808                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
 809                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
 810                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 811                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
 812                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
 813                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 814                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
 815                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
 816                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 817                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
 818                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
 819                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 820                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
 821                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
 822                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 823                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
 824                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
 825                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 826                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
 827                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
 828                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 829                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
 830                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
 831                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 832         }
 833         if (ugeth->p_rx_glbl_pram) {
 834                 ugeth_info("RX global param:");
 835                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
 836                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
 837                            (u32) & ugeth->p_rx_glbl_pram->remoder,
 838                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
 839                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
 840                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
 841                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
 842                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
 843                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
 844                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
 845                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
 846                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
 847                            ugeth->p_rx_glbl_pram->rxgstpack);
 848                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
 849                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
 850                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
 851                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
 852                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
 853                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
 854                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
 855                            (u32) & ugeth->p_rx_glbl_pram->rstate,
 856                            ugeth->p_rx_glbl_pram->rstate);
 857                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
 858                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
 859                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
 860                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
 861                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
 862                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
 863                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
 864                            (u32) & ugeth->p_rx_glbl_pram->mflr,
 865                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
 866                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
 867                            (u32) & ugeth->p_rx_glbl_pram->minflr,
 868                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
 869                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
 870                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
 871                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
 872                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
 873                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
 874                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
 875                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
 876                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
 877                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
 878                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
 879                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
 880                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
 881                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
 882                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
 883                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
 884                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
 885                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
 886                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
 887                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
 888                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
 889                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
 890                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
 891                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
 892                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
 893                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
 894                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
 895                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
 896                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
 897                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
 898                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
 899                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
 900                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
 901                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
 902                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
 903                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
 904                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
 905                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
 906                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
 907                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
 908                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
 909                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
 910                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
 911                 for (i = 0; i < 64; i++)
 912                         ugeth_info
 913                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
 914                              i,
 915                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
 916                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
 917                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
 918                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
 919                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
 920         }
 921         if (ugeth->p_send_q_mem_reg) {
 922                 ugeth_info("Send Q memory registers:");
 923                 ugeth_info("Base address: 0x%08x",
 924                            (u32) ugeth->p_send_q_mem_reg);
 925                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 926                         ugeth_info("SQQD[%d]:", i);
 927                         ugeth_info("Base address: 0x%08x",
 928                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
 929                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
 930                                  sizeof(struct ucc_geth_send_queue_qd));
 931                 }
 932         }
 933         if (ugeth->p_scheduler) {
 934                 ugeth_info("Scheduler:");
 935                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
 936                 mem_disp((u8 *) ugeth->p_scheduler,
 937                          sizeof(*ugeth->p_scheduler));
 938         }
 939         if (ugeth->p_tx_fw_statistics_pram) {
 940                 ugeth_info("TX FW statistics pram:");
 941                 ugeth_info("Base address: 0x%08x",
 942                            (u32) ugeth->p_tx_fw_statistics_pram);
 943                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
 944                          sizeof(*ugeth->p_tx_fw_statistics_pram));
 945         }
 946         if (ugeth->p_rx_fw_statistics_pram) {
 947                 ugeth_info("RX FW statistics pram:");
 948                 ugeth_info("Base address: 0x%08x",
 949                            (u32) ugeth->p_rx_fw_statistics_pram);
 950                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
 951                          sizeof(*ugeth->p_rx_fw_statistics_pram));
 952         }
 953         if (ugeth->p_rx_irq_coalescing_tbl) {
 954                 ugeth_info("RX IRQ coalescing tables:");
 955                 ugeth_info("Base address: 0x%08x",
 956                            (u32) ugeth->p_rx_irq_coalescing_tbl);
 957                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 958                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
 959                         ugeth_info("Base address: 0x%08x",
 960                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
 961                                    coalescingentry[i]);
 962                         ugeth_info
 963                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
 964                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
 965                              coalescingentry[i].interruptcoalescingmaxvalue,
 966                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 967                                      coalescingentry[i].
 968                                      interruptcoalescingmaxvalue));
 969                         ugeth_info
 970                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
 971                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
 972                              coalescingentry[i].interruptcoalescingcounter,
 973                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 974                                      coalescingentry[i].
 975                                      interruptcoalescingcounter));
 976                 }
 977         }
 978         if (ugeth->p_rx_bd_qs_tbl) {
 979                 ugeth_info("RX BD QS tables:");
 980                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
 981                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 982                         ugeth_info("RX BD QS table[%d]:", i);
 983                         ugeth_info("Base address: 0x%08x",
 984                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
 985                         ugeth_info
 986                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
 987                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
 988                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
 989                         ugeth_info
 990                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
 991                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
 992                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
 993                         ugeth_info
 994                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
 995                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
 996                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
 997                                      externalbdbaseptr));
 998                         ugeth_info
 999                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1000                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1001                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1002                         ugeth_info("ucode RX Prefetched BDs:");
1003                         ugeth_info("Base address: 0x%08x",
1004                                    (u32)
1005                                    qe_muram_addr(in_be32
1006                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1007                                                   bdbaseptr)));
1008                         mem_disp((u8 *)
1009                                  qe_muram_addr(in_be32
1010                                                (&ugeth->p_rx_bd_qs_tbl[i].
1011                                                 bdbaseptr)),
1012                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1013                 }
1014         }
1015         if (ugeth->p_init_enet_param_shadow) {
1016                 int size;
1017                 ugeth_info("Init enet param shadow:");
1018                 ugeth_info("Base address: 0x%08x",
1019                            (u32) ugeth->p_init_enet_param_shadow);
1020                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1021                          sizeof(*ugeth->p_init_enet_param_shadow));
1022
1023                 size = sizeof(struct ucc_geth_thread_rx_pram);
1024                 if (ugeth->ug_info->rxExtendedFiltering) {
1025                         size +=
1026                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1027                         if (ugeth->ug_info->largestexternallookupkeysize ==
1028                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1029                                 size +=
1030                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1031                         if (ugeth->ug_info->largestexternallookupkeysize ==
1032                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1033                                 size +=
1034                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1035                 }
1036
1037                 dump_init_enet_entries(ugeth,
1038                                        &(ugeth->p_init_enet_param_shadow->
1039                                          txthread[0]),
1040                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1041                                        sizeof(struct ucc_geth_thread_tx_pram),
1042                                        ugeth->ug_info->riscTx, 0);
1043                 dump_init_enet_entries(ugeth,
1044                                        &(ugeth->p_init_enet_param_shadow->
1045                                          rxthread[0]),
1046                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1047                                        ugeth->ug_info->riscRx, 1);
1048         }
1049 }
1050 #endif /* DEBUG */
1051
1052 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1053                                   u32 __iomem *maccfg1_register,
1054                                   u32 __iomem *maccfg2_register)
1055 {
1056         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1057         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1058         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1059 }
1060
1061 static int init_half_duplex_params(int alt_beb,
1062                                    int back_pressure_no_backoff,
1063                                    int no_backoff,
1064                                    int excess_defer,
1065                                    u8 alt_beb_truncation,
1066                                    u8 max_retransmissions,
1067                                    u8 collision_window,
1068                                    u32 __iomem *hafdup_register)
1069 {
1070         u32 value = 0;
1071
1072         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1073             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1074             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1075                 return -EINVAL;
1076
1077         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1078
1079         if (alt_beb)
1080                 value |= HALFDUP_ALT_BEB;
1081         if (back_pressure_no_backoff)
1082                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1083         if (no_backoff)
1084                 value |= HALFDUP_NO_BACKOFF;
1085         if (excess_defer)
1086                 value |= HALFDUP_EXCESSIVE_DEFER;
1087
1088         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1089
1090         value |= collision_window;
1091
1092         out_be32(hafdup_register, value);
1093         return 0;
1094 }
1095
1096 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1097                                        u8 non_btb_ipg,
1098                                        u8 min_ifg,
1099                                        u8 btb_ipg,
1100                                        u32 __iomem *ipgifg_register)
1101 {
1102         u32 value = 0;
1103
1104         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1105         IPG part 2 */
1106         if (non_btb_cs_ipg > non_btb_ipg)
1107                 return -EINVAL;
1108
1109         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1110             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1111             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1112             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1113                 return -EINVAL;
1114
1115         value |=
1116             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1117              IPGIFG_NBTB_CS_IPG_MASK);
1118         value |=
1119             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1120              IPGIFG_NBTB_IPG_MASK);
1121         value |=
1122             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1123              IPGIFG_MIN_IFG_MASK);
1124         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1125
1126         out_be32(ipgifg_register, value);
1127         return 0;
1128 }
1129
1130 int init_flow_control_params(u32 automatic_flow_control_mode,
1131                                     int rx_flow_control_enable,
1132                                     int tx_flow_control_enable,
1133                                     u16 pause_period,
1134                                     u16 extension_field,
1135                                     u32 __iomem *upsmr_register,
1136                                     u32 __iomem *uempr_register,
1137                                     u32 __iomem *maccfg1_register)
1138 {
1139         u32 value = 0;
1140
1141         /* Set UEMPR register */
1142         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1143         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1144         out_be32(uempr_register, value);
1145
1146         /* Set UPSMR register */
1147         setbits32(upsmr_register, automatic_flow_control_mode);
1148
1149         value = in_be32(maccfg1_register);
1150         if (rx_flow_control_enable)
1151                 value |= MACCFG1_FLOW_RX;
1152         if (tx_flow_control_enable)
1153                 value |= MACCFG1_FLOW_TX;
1154         out_be32(maccfg1_register, value);
1155
1156         return 0;
1157 }
1158
1159 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1160                                              int auto_zero_hardware_statistics,
1161                                              u32 __iomem *upsmr_register,
1162                                              u16 __iomem *uescr_register)
1163 {
1164         u16 uescr_value = 0;
1165
1166         /* Enable hardware statistics gathering if requested */
1167         if (enable_hardware_statistics)
1168                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1169
1170         /* Clear hardware statistics counters */
1171         uescr_value = in_be16(uescr_register);
1172         uescr_value |= UESCR_CLRCNT;
1173         /* Automatically zero hardware statistics counters on read,
1174         if requested */
1175         if (auto_zero_hardware_statistics)
1176                 uescr_value |= UESCR_AUTOZ;
1177         out_be16(uescr_register, uescr_value);
1178
1179         return 0;
1180 }
1181
1182 static int init_firmware_statistics_gathering_mode(int
1183                 enable_tx_firmware_statistics,
1184                 int enable_rx_firmware_statistics,
1185                 u32 __iomem *tx_rmon_base_ptr,
1186                 u32 tx_firmware_statistics_structure_address,
1187                 u32 __iomem *rx_rmon_base_ptr,
1188                 u32 rx_firmware_statistics_structure_address,
1189                 u16 __iomem *temoder_register,
1190                 u32 __iomem *remoder_register)
1191 {
1192         /* Note: this function does not check if */
1193         /* the parameters it receives are NULL   */
1194
1195         if (enable_tx_firmware_statistics) {
1196                 out_be32(tx_rmon_base_ptr,
1197                          tx_firmware_statistics_structure_address);
1198                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1199         }
1200
1201         if (enable_rx_firmware_statistics) {
1202                 out_be32(rx_rmon_base_ptr,
1203                          rx_firmware_statistics_structure_address);
1204                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1205         }
1206
1207         return 0;
1208 }
1209
1210 static int init_mac_station_addr_regs(u8 address_byte_0,
1211                                       u8 address_byte_1,
1212                                       u8 address_byte_2,
1213                                       u8 address_byte_3,
1214                                       u8 address_byte_4,
1215                                       u8 address_byte_5,
1216                                       u32 __iomem *macstnaddr1_register,
1217                                       u32 __iomem *macstnaddr2_register)
1218 {
1219         u32 value = 0;
1220
1221         /* Example: for a station address of 0x12345678ABCD, */
1222         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1223
1224         /* MACSTNADDR1 Register: */
1225
1226         /* 0                      7   8                      15  */
1227         /* station address byte 5     station address byte 4     */
1228         /* 16                     23  24                     31  */
1229         /* station address byte 3     station address byte 2     */
1230         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1231         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1232         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1233         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1234
1235         out_be32(macstnaddr1_register, value);
1236
1237         /* MACSTNADDR2 Register: */
1238
1239         /* 0                      7   8                      15  */
1240         /* station address byte 1     station address byte 0     */
1241         /* 16                     23  24                     31  */
1242         /*         reserved                   reserved           */
1243         value = 0;
1244         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1245         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1246
1247         out_be32(macstnaddr2_register, value);
1248
1249         return 0;
1250 }
1251
1252 static int init_check_frame_length_mode(int length_check,
1253                                         u32 __iomem *maccfg2_register)
1254 {
1255         u32 value = 0;
1256
1257         value = in_be32(maccfg2_register);
1258
1259         if (length_check)
1260                 value |= MACCFG2_LC;
1261         else
1262                 value &= ~MACCFG2_LC;
1263
1264         out_be32(maccfg2_register, value);
1265         return 0;
1266 }
1267
1268 static int init_preamble_length(u8 preamble_length,
1269                                 u32 __iomem *maccfg2_register)
1270 {
1271         if ((preamble_length < 3) || (preamble_length > 7))
1272                 return -EINVAL;
1273
1274         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1275                         preamble_length << MACCFG2_PREL_SHIFT);
1276
1277         return 0;
1278 }
1279
1280 static int init_rx_parameters(int reject_broadcast,
1281                               int receive_short_frames,
1282                               int promiscuous, u32 __iomem *upsmr_register)
1283 {
1284         u32 value = 0;
1285
1286         value = in_be32(upsmr_register);
1287
1288         if (reject_broadcast)
1289                 value |= UCC_GETH_UPSMR_BRO;
1290         else
1291                 value &= ~UCC_GETH_UPSMR_BRO;
1292
1293         if (receive_short_frames)
1294                 value |= UCC_GETH_UPSMR_RSH;
1295         else
1296                 value &= ~UCC_GETH_UPSMR_RSH;
1297
1298         if (promiscuous)
1299                 value |= UCC_GETH_UPSMR_PRO;
1300         else
1301                 value &= ~UCC_GETH_UPSMR_PRO;
1302
1303         out_be32(upsmr_register, value);
1304
1305         return 0;
1306 }
1307
1308 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1309                                 u16 __iomem *mrblr_register)
1310 {
1311         /* max_rx_buf_len value must be a multiple of 128 */
1312         if ((max_rx_buf_len == 0) ||
1313             (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1314                 return -EINVAL;
1315
1316         out_be16(mrblr_register, max_rx_buf_len);
1317         return 0;
1318 }
1319
1320 static int init_min_frame_len(u16 min_frame_length,
1321                               u16 __iomem *minflr_register,
1322                               u16 __iomem *mrblr_register)
1323 {
1324         u16 mrblr_value = 0;
1325
1326         mrblr_value = in_be16(mrblr_register);
1327         if (min_frame_length >= (mrblr_value - 4))
1328                 return -EINVAL;
1329
1330         out_be16(minflr_register, min_frame_length);
1331         return 0;
1332 }
1333
1334 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1335 {
1336         struct ucc_geth_info *ug_info;
1337         struct ucc_geth __iomem *ug_regs;
1338         struct ucc_fast __iomem *uf_regs;
1339         int ret_val;
1340         u32 upsmr, maccfg2;
1341         u16 value;
1342
1343         ugeth_vdbg("%s: IN", __func__);
1344
1345         ug_info = ugeth->ug_info;
1346         ug_regs = ugeth->ug_regs;
1347         uf_regs = ugeth->uccf->uf_regs;
1348
1349         /*                    Set MACCFG2                    */
1350         maccfg2 = in_be32(&ug_regs->maccfg2);
1351         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1352         if ((ugeth->max_speed == SPEED_10) ||
1353             (ugeth->max_speed == SPEED_100))
1354                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1355         else if (ugeth->max_speed == SPEED_1000)
1356                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1357         maccfg2 |= ug_info->padAndCrc;
1358         out_be32(&ug_regs->maccfg2, maccfg2);
1359
1360         /*                    Set UPSMR                      */
1361         upsmr = in_be32(&uf_regs->upsmr);
1362         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1363                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1364         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1365             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1366             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1367             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1368             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1369             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1370                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1371                         upsmr |= UCC_GETH_UPSMR_RPM;
1372                 switch (ugeth->max_speed) {
1373                 case SPEED_10:
1374                         upsmr |= UCC_GETH_UPSMR_R10M;
1375                         /* FALLTHROUGH */
1376                 case SPEED_100:
1377                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1378                                 upsmr |= UCC_GETH_UPSMR_RMM;
1379                 }
1380         }
1381         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1382             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1383                 upsmr |= UCC_GETH_UPSMR_TBIM;
1384         }
1385         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1386                 upsmr |= UCC_GETH_UPSMR_SGMM;
1387
1388         out_be32(&uf_regs->upsmr, upsmr);
1389
1390         /* Disable autonegotiation in tbi mode, because by default it
1391         comes up in autonegotiation mode. */
1392         /* Note that this depends on proper setting in utbipar register. */
1393         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1394             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1395                 struct ucc_geth_info *ug_info = ugeth->ug_info;
1396                 struct phy_device *tbiphy;
1397
1398                 if (!ug_info->tbi_node)
1399                         ugeth_warn("TBI mode requires that the device "
1400                                 "tree specify a tbi-handle\n");
1401
1402                 tbiphy = of_phy_find_device(ug_info->tbi_node);
1403                 if (!tbiphy)
1404                         ugeth_warn("Could not get TBI device\n");
1405
1406                 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1407                 value &= ~0x1000;       /* Turn off autonegotiation */
1408                 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1409         }
1410
1411         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1412
1413         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1414         if (ret_val != 0) {
1415                 if (netif_msg_probe(ugeth))
1416                         ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1417                              __func__);
1418                 return ret_val;
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1425 {
1426         struct ucc_fast_private *uccf;
1427         u32 cecr_subblock;
1428         u32 temp;
1429         int i = 10;
1430
1431         uccf = ugeth->uccf;
1432
1433         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1434         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1435         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1436
1437         /* Issue host command */
1438         cecr_subblock =
1439             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1440         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1441                      QE_CR_PROTOCOL_ETHERNET, 0);
1442
1443         /* Wait for command to complete */
1444         do {
1445                 msleep(10);
1446                 temp = in_be32(uccf->p_ucce);
1447         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1448
1449         uccf->stopped_tx = 1;
1450
1451         return 0;
1452 }
1453
1454 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1455 {
1456         struct ucc_fast_private *uccf;
1457         u32 cecr_subblock;
1458         u8 temp;
1459         int i = 10;
1460
1461         uccf = ugeth->uccf;
1462
1463         /* Clear acknowledge bit */
1464         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1465         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1466         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1467
1468         /* Keep issuing command and checking acknowledge bit until
1469         it is asserted, according to spec */
1470         do {
1471                 /* Issue host command */
1472                 cecr_subblock =
1473                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1474                                                 ucc_num);
1475                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1476                              QE_CR_PROTOCOL_ETHERNET, 0);
1477                 msleep(10);
1478                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1479         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1480
1481         uccf->stopped_rx = 1;
1482
1483         return 0;
1484 }
1485
1486 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1487 {
1488         struct ucc_fast_private *uccf;
1489         u32 cecr_subblock;
1490
1491         uccf = ugeth->uccf;
1492
1493         cecr_subblock =
1494             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1495         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1496         uccf->stopped_tx = 0;
1497
1498         return 0;
1499 }
1500
1501 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1502 {
1503         struct ucc_fast_private *uccf;
1504         u32 cecr_subblock;
1505
1506         uccf = ugeth->uccf;
1507
1508         cecr_subblock =
1509             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1510         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1511                      0);
1512         uccf->stopped_rx = 0;
1513
1514         return 0;
1515 }
1516
1517 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1518 {
1519         struct ucc_fast_private *uccf;
1520         int enabled_tx, enabled_rx;
1521
1522         uccf = ugeth->uccf;
1523
1524         /* check if the UCC number is in range. */
1525         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1526                 if (netif_msg_probe(ugeth))
1527                         ugeth_err("%s: ucc_num out of range.", __func__);
1528                 return -EINVAL;
1529         }
1530
1531         enabled_tx = uccf->enabled_tx;
1532         enabled_rx = uccf->enabled_rx;
1533
1534         /* Get Tx and Rx going again, in case this channel was actively
1535         disabled. */
1536         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1537                 ugeth_restart_tx(ugeth);
1538         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1539                 ugeth_restart_rx(ugeth);
1540
1541         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1542
1543         return 0;
1544
1545 }
1546
1547 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1548 {
1549         struct ucc_fast_private *uccf;
1550
1551         uccf = ugeth->uccf;
1552
1553         /* check if the UCC number is in range. */
1554         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1555                 if (netif_msg_probe(ugeth))
1556                         ugeth_err("%s: ucc_num out of range.", __func__);
1557                 return -EINVAL;
1558         }
1559
1560         /* Stop any transmissions */
1561         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1562                 ugeth_graceful_stop_tx(ugeth);
1563
1564         /* Stop any receptions */
1565         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1566                 ugeth_graceful_stop_rx(ugeth);
1567
1568         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1569
1570         return 0;
1571 }
1572
1573 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1574 {
1575         /* Prevent any further xmits, plus detach the device. */
1576         netif_device_detach(ugeth->ndev);
1577
1578         /* Wait for any current xmits to finish. */
1579         netif_tx_disable(ugeth->ndev);
1580
1581         /* Disable the interrupt to avoid NAPI rescheduling. */
1582         disable_irq(ugeth->ug_info->uf_info.irq);
1583
1584         /* Stop NAPI, and possibly wait for its completion. */
1585         napi_disable(&ugeth->napi);
1586 }
1587
1588 static void ugeth_activate(struct ucc_geth_private *ugeth)
1589 {
1590         napi_enable(&ugeth->napi);
1591         enable_irq(ugeth->ug_info->uf_info.irq);
1592         netif_device_attach(ugeth->ndev);
1593 }
1594
1595 /* Called every time the controller might need to be made
1596  * aware of new link state.  The PHY code conveys this
1597  * information through variables in the ugeth structure, and this
1598  * function converts those variables into the appropriate
1599  * register values, and can bring down the device if needed.
1600  */
1601
1602 static void adjust_link(struct net_device *dev)
1603 {
1604         struct ucc_geth_private *ugeth = netdev_priv(dev);
1605         struct ucc_geth __iomem *ug_regs;
1606         struct ucc_fast __iomem *uf_regs;
1607         struct phy_device *phydev = ugeth->phydev;
1608         int new_state = 0;
1609
1610         ug_regs = ugeth->ug_regs;
1611         uf_regs = ugeth->uccf->uf_regs;
1612
1613         if (phydev->link) {
1614                 u32 tempval = in_be32(&ug_regs->maccfg2);
1615                 u32 upsmr = in_be32(&uf_regs->upsmr);
1616                 /* Now we make sure that we can be in full duplex mode.
1617                  * If not, we operate in half-duplex mode. */
1618                 if (phydev->duplex != ugeth->oldduplex) {
1619                         new_state = 1;
1620                         if (!(phydev->duplex))
1621                                 tempval &= ~(MACCFG2_FDX);
1622                         else
1623                                 tempval |= MACCFG2_FDX;
1624                         ugeth->oldduplex = phydev->duplex;
1625                 }
1626
1627                 if (phydev->speed != ugeth->oldspeed) {
1628                         new_state = 1;
1629                         switch (phydev->speed) {
1630                         case SPEED_1000:
1631                                 tempval = ((tempval &
1632                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1633                                             MACCFG2_INTERFACE_MODE_BYTE);
1634                                 break;
1635                         case SPEED_100:
1636                         case SPEED_10:
1637                                 tempval = ((tempval &
1638                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1639                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1640                                 /* if reduced mode, re-set UPSMR.R10M */
1641                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1642                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1643                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1644                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1645                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1646                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1647                                         if (phydev->speed == SPEED_10)
1648                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1649                                         else
1650                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1651                                 }
1652                                 break;
1653                         default:
1654                                 if (netif_msg_link(ugeth))
1655                                         ugeth_warn(
1656                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1657                                                 dev->name, phydev->speed);
1658                                 break;
1659                         }
1660                         ugeth->oldspeed = phydev->speed;
1661                 }
1662
1663                 if (!ugeth->oldlink) {
1664                         new_state = 1;
1665                         ugeth->oldlink = 1;
1666                 }
1667
1668                 if (new_state) {
1669                         /*
1670                          * To change the MAC configuration we need to disable
1671                          * the controller. To do so, we have to either grab
1672                          * ugeth->lock, which is a bad idea since 'graceful
1673                          * stop' commands might take quite a while, or we can
1674                          * quiesce driver's activity.
1675                          */
1676                         ugeth_quiesce(ugeth);
1677                         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1678
1679                         out_be32(&ug_regs->maccfg2, tempval);
1680                         out_be32(&uf_regs->upsmr, upsmr);
1681
1682                         ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1683                         ugeth_activate(ugeth);
1684                 }
1685         } else if (ugeth->oldlink) {
1686                         new_state = 1;
1687                         ugeth->oldlink = 0;
1688                         ugeth->oldspeed = 0;
1689                         ugeth->oldduplex = -1;
1690         }
1691
1692         if (new_state && netif_msg_link(ugeth))
1693                 phy_print_status(phydev);
1694 }
1695
1696 /* Initialize TBI PHY interface for communicating with the
1697  * SERDES lynx PHY on the chip.  We communicate with this PHY
1698  * through the MDIO bus on each controller, treating it as a
1699  * "normal" PHY at the address found in the UTBIPA register.  We assume
1700  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1701  * it to a value that doesn't conflict with other PHYs on the bus, or the
1702  * value doesn't matter, as there are no other PHYs on the bus.
1703  */
1704 static void uec_configure_serdes(struct net_device *dev)
1705 {
1706         struct ucc_geth_private *ugeth = netdev_priv(dev);
1707         struct ucc_geth_info *ug_info = ugeth->ug_info;
1708         struct phy_device *tbiphy;
1709
1710         if (!ug_info->tbi_node) {
1711                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1712                         "tree specify a tbi-handle\n");
1713                 return;
1714         }
1715
1716         tbiphy = of_phy_find_device(ug_info->tbi_node);
1717         if (!tbiphy) {
1718                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1719                 return;
1720         }
1721
1722         /*
1723          * If the link is already up, we must already be ok, and don't need to
1724          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1725          * everything for us?  Resetting it takes the link down and requires
1726          * several seconds for it to come back.
1727          */
1728         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1729                 return;
1730
1731         /* Single clk mode, mii mode off(for serdes communication) */
1732         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1733
1734         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1735
1736         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1737 }
1738
1739 /* Configure the PHY for dev.
1740  * returns 0 if success.  -1 if failure
1741  */
1742 static int init_phy(struct net_device *dev)
1743 {
1744         struct ucc_geth_private *priv = netdev_priv(dev);
1745         struct ucc_geth_info *ug_info = priv->ug_info;
1746         struct phy_device *phydev;
1747
1748         priv->oldlink = 0;
1749         priv->oldspeed = 0;
1750         priv->oldduplex = -1;
1751
1752         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1753                                 priv->phy_interface);
1754         if (!phydev)
1755                 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1756                                                    priv->phy_interface);
1757         if (!phydev) {
1758                 dev_err(&dev->dev, "Could not attach to PHY\n");
1759                 return -ENODEV;
1760         }
1761
1762         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1763                 uec_configure_serdes(dev);
1764
1765         phydev->supported &= (SUPPORTED_MII |
1766                               SUPPORTED_Autoneg |
1767                               ADVERTISED_10baseT_Half |
1768                               ADVERTISED_10baseT_Full |
1769                               ADVERTISED_100baseT_Half |
1770                               ADVERTISED_100baseT_Full);
1771
1772         if (priv->max_speed == SPEED_1000)
1773                 phydev->supported |= ADVERTISED_1000baseT_Full;
1774
1775         phydev->advertising = phydev->supported;
1776
1777         priv->phydev = phydev;
1778
1779         return 0;
1780 }
1781
1782 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1783 {
1784 #ifdef DEBUG
1785         ucc_fast_dump_regs(ugeth->uccf);
1786         dump_regs(ugeth);
1787         dump_bds(ugeth);
1788 #endif
1789 }
1790
1791 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1792                                                        ugeth,
1793                                                        enum enet_addr_type
1794                                                        enet_addr_type)
1795 {
1796         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1797         struct ucc_fast_private *uccf;
1798         enum comm_dir comm_dir;
1799         struct list_head *p_lh;
1800         u16 i, num;
1801         u32 __iomem *addr_h;
1802         u32 __iomem *addr_l;
1803         u8 *p_counter;
1804
1805         uccf = ugeth->uccf;
1806
1807         p_82xx_addr_filt =
1808             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1809             ugeth->p_rx_glbl_pram->addressfiltering;
1810
1811         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1812                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1813                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1814                 p_lh = &ugeth->group_hash_q;
1815                 p_counter = &(ugeth->numGroupAddrInHash);
1816         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1817                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1818                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1819                 p_lh = &ugeth->ind_hash_q;
1820                 p_counter = &(ugeth->numIndAddrInHash);
1821         } else
1822                 return -EINVAL;
1823
1824         comm_dir = 0;
1825         if (uccf->enabled_tx)
1826                 comm_dir |= COMM_DIR_TX;
1827         if (uccf->enabled_rx)
1828                 comm_dir |= COMM_DIR_RX;
1829         if (comm_dir)
1830                 ugeth_disable(ugeth, comm_dir);
1831
1832         /* Clear the hash table. */
1833         out_be32(addr_h, 0x00000000);
1834         out_be32(addr_l, 0x00000000);
1835
1836         if (!p_lh)
1837                 return 0;
1838
1839         num = *p_counter;
1840
1841         /* Delete all remaining CQ elements */
1842         for (i = 0; i < num; i++)
1843                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1844
1845         *p_counter = 0;
1846
1847         if (comm_dir)
1848                 ugeth_enable(ugeth, comm_dir);
1849
1850         return 0;
1851 }
1852
1853 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1854                                                     u8 paddr_num)
1855 {
1856         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1857         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1858 }
1859
1860 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1861 {
1862         u16 i, j;
1863         u8 __iomem *bd;
1864
1865         if (!ugeth)
1866                 return;
1867
1868         if (ugeth->uccf) {
1869                 ucc_fast_free(ugeth->uccf);
1870                 ugeth->uccf = NULL;
1871         }
1872
1873         if (ugeth->p_thread_data_tx) {
1874                 qe_muram_free(ugeth->thread_dat_tx_offset);
1875                 ugeth->p_thread_data_tx = NULL;
1876         }
1877         if (ugeth->p_thread_data_rx) {
1878                 qe_muram_free(ugeth->thread_dat_rx_offset);
1879                 ugeth->p_thread_data_rx = NULL;
1880         }
1881         if (ugeth->p_exf_glbl_param) {
1882                 qe_muram_free(ugeth->exf_glbl_param_offset);
1883                 ugeth->p_exf_glbl_param = NULL;
1884         }
1885         if (ugeth->p_rx_glbl_pram) {
1886                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1887                 ugeth->p_rx_glbl_pram = NULL;
1888         }
1889         if (ugeth->p_tx_glbl_pram) {
1890                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1891                 ugeth->p_tx_glbl_pram = NULL;
1892         }
1893         if (ugeth->p_send_q_mem_reg) {
1894                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1895                 ugeth->p_send_q_mem_reg = NULL;
1896         }
1897         if (ugeth->p_scheduler) {
1898                 qe_muram_free(ugeth->scheduler_offset);
1899                 ugeth->p_scheduler = NULL;
1900         }
1901         if (ugeth->p_tx_fw_statistics_pram) {
1902                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1903                 ugeth->p_tx_fw_statistics_pram = NULL;
1904         }
1905         if (ugeth->p_rx_fw_statistics_pram) {
1906                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1907                 ugeth->p_rx_fw_statistics_pram = NULL;
1908         }
1909         if (ugeth->p_rx_irq_coalescing_tbl) {
1910                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1911                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1912         }
1913         if (ugeth->p_rx_bd_qs_tbl) {
1914                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1915                 ugeth->p_rx_bd_qs_tbl = NULL;
1916         }
1917         if (ugeth->p_init_enet_param_shadow) {
1918                 return_init_enet_entries(ugeth,
1919                                          &(ugeth->p_init_enet_param_shadow->
1920                                            rxthread[0]),
1921                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1922                                          ugeth->ug_info->riscRx, 1);
1923                 return_init_enet_entries(ugeth,
1924                                          &(ugeth->p_init_enet_param_shadow->
1925                                            txthread[0]),
1926                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1927                                          ugeth->ug_info->riscTx, 0);
1928                 kfree(ugeth->p_init_enet_param_shadow);
1929                 ugeth->p_init_enet_param_shadow = NULL;
1930         }
1931         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1932                 bd = ugeth->p_tx_bd_ring[i];
1933                 if (!bd)
1934                         continue;
1935                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1936                         if (ugeth->tx_skbuff[i][j]) {
1937                                 dma_unmap_single(ugeth->dev,
1938                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1939                                                  (in_be32((u32 __iomem *)bd) &
1940                                                   BD_LENGTH_MASK),
1941                                                  DMA_TO_DEVICE);
1942                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1943                                 ugeth->tx_skbuff[i][j] = NULL;
1944                         }
1945                 }
1946
1947                 kfree(ugeth->tx_skbuff[i]);
1948
1949                 if (ugeth->p_tx_bd_ring[i]) {
1950                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1951                             MEM_PART_SYSTEM)
1952                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1953                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1954                                  MEM_PART_MURAM)
1955                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1956                         ugeth->p_tx_bd_ring[i] = NULL;
1957                 }
1958         }
1959         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1960                 if (ugeth->p_rx_bd_ring[i]) {
1961                         /* Return existing data buffers in ring */
1962                         bd = ugeth->p_rx_bd_ring[i];
1963                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1964                                 if (ugeth->rx_skbuff[i][j]) {
1965                                         dma_unmap_single(ugeth->dev,
1966                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1967                                                 ugeth->ug_info->
1968                                                 uf_info.max_rx_buf_length +
1969                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1970                                                 DMA_FROM_DEVICE);
1971                                         dev_kfree_skb_any(
1972                                                 ugeth->rx_skbuff[i][j]);
1973                                         ugeth->rx_skbuff[i][j] = NULL;
1974                                 }
1975                                 bd += sizeof(struct qe_bd);
1976                         }
1977
1978                         kfree(ugeth->rx_skbuff[i]);
1979
1980                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1981                             MEM_PART_SYSTEM)
1982                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1983                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1984                                  MEM_PART_MURAM)
1985                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1986                         ugeth->p_rx_bd_ring[i] = NULL;
1987                 }
1988         }
1989         while (!list_empty(&ugeth->group_hash_q))
1990                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1991                                         (dequeue(&ugeth->group_hash_q)));
1992         while (!list_empty(&ugeth->ind_hash_q))
1993                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1994                                         (dequeue(&ugeth->ind_hash_q)));
1995         if (ugeth->ug_regs) {
1996                 iounmap(ugeth->ug_regs);
1997                 ugeth->ug_regs = NULL;
1998         }
1999
2000         skb_queue_purge(&ugeth->rx_recycle);
2001 }
2002
2003 static void ucc_geth_set_multi(struct net_device *dev)
2004 {
2005         struct ucc_geth_private *ugeth;
2006         struct netdev_hw_addr *ha;
2007         struct ucc_fast __iomem *uf_regs;
2008         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2009
2010         ugeth = netdev_priv(dev);
2011
2012         uf_regs = ugeth->uccf->uf_regs;
2013
2014         if (dev->flags & IFF_PROMISC) {
2015                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2016         } else {
2017                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2018
2019                 p_82xx_addr_filt =
2020                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2021                     p_rx_glbl_pram->addressfiltering;
2022
2023                 if (dev->flags & IFF_ALLMULTI) {
2024                         /* Catch all multicast addresses, so set the
2025                          * filter to all 1's.
2026                          */
2027                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2028                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2029                 } else {
2030                         /* Clear filter and add the addresses in the list.
2031                          */
2032                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2033                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2034
2035                         netdev_for_each_mc_addr(ha, dev) {
2036                                 /* Ask CPM to run CRC and set bit in
2037                                  * filter mask.
2038                                  */
2039                                 hw_add_addr_in_hash(ugeth, ha->addr);
2040                         }
2041                 }
2042         }
2043 }
2044
2045 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2046 {
2047         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2048         struct phy_device *phydev = ugeth->phydev;
2049
2050         ugeth_vdbg("%s: IN", __func__);
2051
2052         /*
2053          * Tell the kernel the link is down.
2054          * Must be done before disabling the controller
2055          * or deadlock may happen.
2056          */
2057         phy_stop(phydev);
2058
2059         /* Disable the controller */
2060         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2061
2062         /* Mask all interrupts */
2063         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2064
2065         /* Clear all interrupts */
2066         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2067
2068         /* Disable Rx and Tx */
2069         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2070
2071         ucc_geth_memclean(ugeth);
2072 }
2073
2074 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2075 {
2076         struct ucc_geth_info *ug_info;
2077         struct ucc_fast_info *uf_info;
2078         int i;
2079
2080         ug_info = ugeth->ug_info;
2081         uf_info = &ug_info->uf_info;
2082
2083         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2084               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2085                 if (netif_msg_probe(ugeth))
2086                         ugeth_err("%s: Bad memory partition value.",
2087                                         __func__);
2088                 return -EINVAL;
2089         }
2090
2091         /* Rx BD lengths */
2092         for (i = 0; i < ug_info->numQueuesRx; i++) {
2093                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2094                     (ug_info->bdRingLenRx[i] %
2095                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2096                         if (netif_msg_probe(ugeth))
2097                                 ugeth_err
2098                                     ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2099                                         __func__);
2100                         return -EINVAL;
2101                 }
2102         }
2103
2104         /* Tx BD lengths */
2105         for (i = 0; i < ug_info->numQueuesTx; i++) {
2106                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2107                         if (netif_msg_probe(ugeth))
2108                                 ugeth_err
2109                                     ("%s: Tx BD ring length must be no smaller than 2.",
2110                                      __func__);
2111                         return -EINVAL;
2112                 }
2113         }
2114
2115         /* mrblr */
2116         if ((uf_info->max_rx_buf_length == 0) ||
2117             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2118                 if (netif_msg_probe(ugeth))
2119                         ugeth_err
2120                             ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2121                              __func__);
2122                 return -EINVAL;
2123         }
2124
2125         /* num Tx queues */
2126         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2127                 if (netif_msg_probe(ugeth))
2128                         ugeth_err("%s: number of tx queues too large.", __func__);
2129                 return -EINVAL;
2130         }
2131
2132         /* num Rx queues */
2133         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2134                 if (netif_msg_probe(ugeth))
2135                         ugeth_err("%s: number of rx queues too large.", __func__);
2136                 return -EINVAL;
2137         }
2138
2139         /* l2qt */
2140         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2141                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2142                         if (netif_msg_probe(ugeth))
2143                                 ugeth_err
2144                                     ("%s: VLAN priority table entry must not be"
2145                                         " larger than number of Rx queues.",
2146                                      __func__);
2147                         return -EINVAL;
2148                 }
2149         }
2150
2151         /* l3qt */
2152         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2153                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2154                         if (netif_msg_probe(ugeth))
2155                                 ugeth_err
2156                                     ("%s: IP priority table entry must not be"
2157                                         " larger than number of Rx queues.",
2158                                      __func__);
2159                         return -EINVAL;
2160                 }
2161         }
2162
2163         if (ug_info->cam && !ug_info->ecamptr) {
2164                 if (netif_msg_probe(ugeth))
2165                         ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2166                                   __func__);
2167                 return -EINVAL;
2168         }
2169
2170         if ((ug_info->numStationAddresses !=
2171              UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2172             ug_info->rxExtendedFiltering) {
2173                 if (netif_msg_probe(ugeth))
2174                         ugeth_err("%s: Number of station addresses greater than 1 "
2175                                   "not allowed in extended parsing mode.",
2176                                   __func__);
2177                 return -EINVAL;
2178         }
2179
2180         /* Generate uccm_mask for receive */
2181         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2182         for (i = 0; i < ug_info->numQueuesRx; i++)
2183                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2184
2185         for (i = 0; i < ug_info->numQueuesTx; i++)
2186                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2187         /* Initialize the general fast UCC block. */
2188         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2189                 if (netif_msg_probe(ugeth))
2190                         ugeth_err("%s: Failed to init uccf.", __func__);
2191                 return -ENOMEM;
2192         }
2193
2194         /* read the number of risc engines, update the riscTx and riscRx
2195          * if there are 4 riscs in QE
2196          */
2197         if (qe_get_num_of_risc() == 4) {
2198                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2199                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2200         }
2201
2202         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2203         if (!ugeth->ug_regs) {
2204                 if (netif_msg_probe(ugeth))
2205                         ugeth_err("%s: Failed to ioremap regs.", __func__);
2206                 return -ENOMEM;
2207         }
2208
2209         skb_queue_head_init(&ugeth->rx_recycle);
2210
2211         return 0;
2212 }
2213
2214 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2215 {
2216         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2217         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2218         struct ucc_fast_private *uccf;
2219         struct ucc_geth_info *ug_info;
2220         struct ucc_fast_info *uf_info;
2221         struct ucc_fast __iomem *uf_regs;
2222         struct ucc_geth __iomem *ug_regs;
2223         int ret_val = -EINVAL;
2224         u32 remoder = UCC_GETH_REMODER_INIT;
2225         u32 init_enet_pram_offset, cecr_subblock, command;
2226         u32 ifstat, i, j, size, l2qt, l3qt, length;
2227         u16 temoder = UCC_GETH_TEMODER_INIT;
2228         u16 test;
2229         u8 function_code = 0;
2230         u8 __iomem *bd;
2231         u8 __iomem *endOfRing;
2232         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2233
2234         ugeth_vdbg("%s: IN", __func__);
2235         uccf = ugeth->uccf;
2236         ug_info = ugeth->ug_info;
2237         uf_info = &ug_info->uf_info;
2238         uf_regs = uccf->uf_regs;
2239         ug_regs = ugeth->ug_regs;
2240
2241         switch (ug_info->numThreadsRx) {
2242         case UCC_GETH_NUM_OF_THREADS_1:
2243                 numThreadsRxNumerical = 1;
2244                 break;
2245         case UCC_GETH_NUM_OF_THREADS_2:
2246                 numThreadsRxNumerical = 2;
2247                 break;
2248         case UCC_GETH_NUM_OF_THREADS_4:
2249                 numThreadsRxNumerical = 4;
2250                 break;
2251         case UCC_GETH_NUM_OF_THREADS_6:
2252                 numThreadsRxNumerical = 6;
2253                 break;
2254         case UCC_GETH_NUM_OF_THREADS_8:
2255                 numThreadsRxNumerical = 8;
2256                 break;
2257         default:
2258                 if (netif_msg_ifup(ugeth))
2259                         ugeth_err("%s: Bad number of Rx threads value.",
2260                                         __func__);
2261                 return -EINVAL;
2262                 break;
2263         }
2264
2265         switch (ug_info->numThreadsTx) {
2266         case UCC_GETH_NUM_OF_THREADS_1:
2267                 numThreadsTxNumerical = 1;
2268                 break;
2269         case UCC_GETH_NUM_OF_THREADS_2:
2270                 numThreadsTxNumerical = 2;
2271                 break;
2272         case UCC_GETH_NUM_OF_THREADS_4:
2273                 numThreadsTxNumerical = 4;
2274                 break;
2275         case UCC_GETH_NUM_OF_THREADS_6:
2276                 numThreadsTxNumerical = 6;
2277                 break;
2278         case UCC_GETH_NUM_OF_THREADS_8:
2279                 numThreadsTxNumerical = 8;
2280                 break;
2281         default:
2282                 if (netif_msg_ifup(ugeth))
2283                         ugeth_err("%s: Bad number of Tx threads value.",
2284                                         __func__);
2285                 return -EINVAL;
2286                 break;
2287         }
2288
2289         /* Calculate rx_extended_features */
2290         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2291             ug_info->ipAddressAlignment ||
2292             (ug_info->numStationAddresses !=
2293              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2294
2295         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2296                 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2297                 (ug_info->vlanOperationNonTagged !=
2298                  UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2299
2300         init_default_reg_vals(&uf_regs->upsmr,
2301                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2302
2303         /*                    Set UPSMR                      */
2304         /* For more details see the hardware spec.           */
2305         init_rx_parameters(ug_info->bro,
2306                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2307
2308         /* We're going to ignore other registers for now, */
2309         /* except as needed to get up and running         */
2310
2311         /*                    Set MACCFG1                    */
2312         /* For more details see the hardware spec.           */
2313         init_flow_control_params(ug_info->aufc,
2314                                  ug_info->receiveFlowControl,
2315                                  ug_info->transmitFlowControl,
2316                                  ug_info->pausePeriod,
2317                                  ug_info->extensionField,
2318                                  &uf_regs->upsmr,
2319                                  &ug_regs->uempr, &ug_regs->maccfg1);
2320
2321         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2322
2323         /*                    Set IPGIFG                     */
2324         /* For more details see the hardware spec.           */
2325         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2326                                               ug_info->nonBackToBackIfgPart2,
2327                                               ug_info->
2328                                               miminumInterFrameGapEnforcement,
2329                                               ug_info->backToBackInterFrameGap,
2330                                               &ug_regs->ipgifg);
2331         if (ret_val != 0) {
2332                 if (netif_msg_ifup(ugeth))
2333                         ugeth_err("%s: IPGIFG initialization parameter too large.",
2334                                   __func__);
2335                 return ret_val;
2336         }
2337
2338         /*                    Set HAFDUP                     */
2339         /* For more details see the hardware spec.           */
2340         ret_val = init_half_duplex_params(ug_info->altBeb,
2341                                           ug_info->backPressureNoBackoff,
2342                                           ug_info->noBackoff,
2343                                           ug_info->excessDefer,
2344                                           ug_info->altBebTruncation,
2345                                           ug_info->maxRetransmission,
2346                                           ug_info->collisionWindow,
2347                                           &ug_regs->hafdup);
2348         if (ret_val != 0) {
2349                 if (netif_msg_ifup(ugeth))
2350                         ugeth_err("%s: Half Duplex initialization parameter too large.",
2351                           __func__);
2352                 return ret_val;
2353         }
2354
2355         /*                    Set IFSTAT                     */
2356         /* For more details see the hardware spec.           */
2357         /* Read only - resets upon read                      */
2358         ifstat = in_be32(&ug_regs->ifstat);
2359
2360         /*                    Clear UEMPR                    */
2361         /* For more details see the hardware spec.           */
2362         out_be32(&ug_regs->uempr, 0);
2363
2364         /*                    Set UESCR                      */
2365         /* For more details see the hardware spec.           */
2366         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2367                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2368                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2369
2370         /* Allocate Tx bds */
2371         for (j = 0; j < ug_info->numQueuesTx; j++) {
2372                 /* Allocate in multiple of
2373                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2374                    according to spec */
2375                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2376                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2377                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2378                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2379                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2380                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2381                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2382                         u32 align = 4;
2383                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2384                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2385                         ugeth->tx_bd_ring_offset[j] =
2386                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2387
2388                         if (ugeth->tx_bd_ring_offset[j] != 0)
2389                                 ugeth->p_tx_bd_ring[j] =
2390                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2391                                         align) & ~(align - 1));
2392                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2393                         ugeth->tx_bd_ring_offset[j] =
2394                             qe_muram_alloc(length,
2395                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2396                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2397                                 ugeth->p_tx_bd_ring[j] =
2398                                     (u8 __iomem *) qe_muram_addr(ugeth->
2399                                                          tx_bd_ring_offset[j]);
2400                 }
2401                 if (!ugeth->p_tx_bd_ring[j]) {
2402                         if (netif_msg_ifup(ugeth))
2403                                 ugeth_err
2404                                     ("%s: Can not allocate memory for Tx bd rings.",
2405                                      __func__);
2406                         return -ENOMEM;
2407                 }
2408                 /* Zero unused end of bd ring, according to spec */
2409                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2410                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2411                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2412         }
2413
2414         /* Allocate Rx bds */
2415         for (j = 0; j < ug_info->numQueuesRx; j++) {
2416                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2417                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2418                         u32 align = 4;
2419                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2420                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2421                         ugeth->rx_bd_ring_offset[j] =
2422                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2423                         if (ugeth->rx_bd_ring_offset[j] != 0)
2424                                 ugeth->p_rx_bd_ring[j] =
2425                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2426                                         align) & ~(align - 1));
2427                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2428                         ugeth->rx_bd_ring_offset[j] =
2429                             qe_muram_alloc(length,
2430                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2431                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2432                                 ugeth->p_rx_bd_ring[j] =
2433                                     (u8 __iomem *) qe_muram_addr(ugeth->
2434                                                          rx_bd_ring_offset[j]);
2435                 }
2436                 if (!ugeth->p_rx_bd_ring[j]) {
2437                         if (netif_msg_ifup(ugeth))
2438                                 ugeth_err
2439                                     ("%s: Can not allocate memory for Rx bd rings.",
2440                                      __func__);
2441                         return -ENOMEM;
2442                 }
2443         }
2444
2445         /* Init Tx bds */
2446         for (j = 0; j < ug_info->numQueuesTx; j++) {
2447                 /* Setup the skbuff rings */
2448                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2449                                               ugeth->ug_info->bdRingLenTx[j],
2450                                               GFP_KERNEL);
2451
2452                 if (ugeth->tx_skbuff[j] == NULL) {
2453                         if (netif_msg_ifup(ugeth))
2454                                 ugeth_err("%s: Could not allocate tx_skbuff",
2455                                           __func__);
2456                         return -ENOMEM;
2457                 }
2458
2459                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2460                         ugeth->tx_skbuff[j][i] = NULL;
2461
2462                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2463                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2464                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2465                         /* clear bd buffer */
2466                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2467                         /* set bd status and length */
2468                         out_be32((u32 __iomem *)bd, 0);
2469                         bd += sizeof(struct qe_bd);
2470                 }
2471                 bd -= sizeof(struct qe_bd);
2472                 /* set bd status and length */
2473                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2474         }
2475
2476         /* Init Rx bds */
2477         for (j = 0; j < ug_info->numQueuesRx; j++) {
2478                 /* Setup the skbuff rings */
2479                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2480                                               ugeth->ug_info->bdRingLenRx[j],
2481                                               GFP_KERNEL);
2482
2483                 if (ugeth->rx_skbuff[j] == NULL) {
2484                         if (netif_msg_ifup(ugeth))
2485                                 ugeth_err("%s: Could not allocate rx_skbuff",
2486                                           __func__);
2487                         return -ENOMEM;
2488                 }
2489
2490                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2491                         ugeth->rx_skbuff[j][i] = NULL;
2492
2493                 ugeth->skb_currx[j] = 0;
2494                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2495                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2496                         /* set bd status and length */
2497                         out_be32((u32 __iomem *)bd, R_I);
2498                         /* clear bd buffer */
2499                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2500                         bd += sizeof(struct qe_bd);
2501                 }
2502                 bd -= sizeof(struct qe_bd);
2503                 /* set bd status and length */
2504                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2505         }
2506
2507         /*
2508          * Global PRAM
2509          */
2510         /* Tx global PRAM */
2511         /* Allocate global tx parameter RAM page */
2512         ugeth->tx_glbl_pram_offset =
2513             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2514                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2515         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2516                 if (netif_msg_ifup(ugeth))
2517                         ugeth_err
2518                             ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2519                              __func__);
2520                 return -ENOMEM;
2521         }
2522         ugeth->p_tx_glbl_pram =
2523             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2524                                                         tx_glbl_pram_offset);
2525         /* Zero out p_tx_glbl_pram */
2526         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2527
2528         /* Fill global PRAM */
2529
2530         /* TQPTR */
2531         /* Size varies with number of Tx threads */
2532         ugeth->thread_dat_tx_offset =
2533             qe_muram_alloc(numThreadsTxNumerical *
2534                            sizeof(struct ucc_geth_thread_data_tx) +
2535                            32 * (numThreadsTxNumerical == 1),
2536                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2537         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2538                 if (netif_msg_ifup(ugeth))
2539                         ugeth_err
2540                             ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2541                              __func__);
2542                 return -ENOMEM;
2543         }
2544
2545         ugeth->p_thread_data_tx =
2546             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2547                                                         thread_dat_tx_offset);
2548         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2549
2550         /* vtagtable */
2551         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2552                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2553                          ug_info->vtagtable[i]);
2554
2555         /* iphoffset */
2556         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2557                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2558                                 ug_info->iphoffset[i]);
2559
2560         /* SQPTR */
2561         /* Size varies with number of Tx queues */
2562         ugeth->send_q_mem_reg_offset =
2563             qe_muram_alloc(ug_info->numQueuesTx *
2564                            sizeof(struct ucc_geth_send_queue_qd),
2565                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2566         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2567                 if (netif_msg_ifup(ugeth))
2568                         ugeth_err
2569                             ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2570                              __func__);
2571                 return -ENOMEM;
2572         }
2573
2574         ugeth->p_send_q_mem_reg =
2575             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2576                         send_q_mem_reg_offset);
2577         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2578
2579         /* Setup the table */
2580         /* Assume BD rings are already established */
2581         for (i = 0; i < ug_info->numQueuesTx; i++) {
2582                 endOfRing =
2583                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2584                                               1) * sizeof(struct qe_bd);
2585                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2586                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2587                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2588                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2589                                  last_bd_completed_address,
2590                                  (u32) virt_to_phys(endOfRing));
2591                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2592                            MEM_PART_MURAM) {
2593                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2594                                  (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2595                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2596                                  last_bd_completed_address,
2597                                  (u32)qe_muram_dma(endOfRing));
2598                 }
2599         }
2600
2601         /* schedulerbasepointer */
2602
2603         if (ug_info->numQueuesTx > 1) {
2604         /* scheduler exists only if more than 1 tx queue */
2605                 ugeth->scheduler_offset =
2606                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2607                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2608                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2609                         if (netif_msg_ifup(ugeth))
2610                                 ugeth_err
2611                                  ("%s: Can not allocate DPRAM memory for p_scheduler.",
2612                                      __func__);
2613                         return -ENOMEM;
2614                 }
2615
2616                 ugeth->p_scheduler =
2617                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2618                                                            scheduler_offset);
2619                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2620                          ugeth->scheduler_offset);
2621                 /* Zero out p_scheduler */
2622                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2623
2624                 /* Set values in scheduler */
2625                 out_be32(&ugeth->p_scheduler->mblinterval,
2626                          ug_info->mblinterval);
2627                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2628                          ug_info->nortsrbytetime);
2629                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2630                 out_8(&ugeth->p_scheduler->strictpriorityq,
2631                                 ug_info->strictpriorityq);
2632                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2633                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2634                 for (i = 0; i < NUM_TX_QUEUES; i++)
2635                         out_8(&ugeth->p_scheduler->weightfactor[i],
2636                             ug_info->weightfactor[i]);
2637
2638                 /* Set pointers to cpucount registers in scheduler */
2639                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2640                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2641                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2642                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2643                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2644                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2645                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2646                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2647         }
2648
2649         /* schedulerbasepointer */
2650         /* TxRMON_PTR (statistics) */
2651         if (ug_info->
2652             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2653                 ugeth->tx_fw_statistics_pram_offset =
2654                     qe_muram_alloc(sizeof
2655                                    (struct ucc_geth_tx_firmware_statistics_pram),
2656                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2657                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2658                         if (netif_msg_ifup(ugeth))
2659                                 ugeth_err
2660                                     ("%s: Can not allocate DPRAM memory for"
2661                                         " p_tx_fw_statistics_pram.",
2662                                         __func__);
2663                         return -ENOMEM;
2664                 }
2665                 ugeth->p_tx_fw_statistics_pram =
2666                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2667                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2668                 /* Zero out p_tx_fw_statistics_pram */
2669                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2670                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2671         }
2672
2673         /* temoder */
2674         /* Already has speed set */
2675
2676         if (ug_info->numQueuesTx > 1)
2677                 temoder |= TEMODER_SCHEDULER_ENABLE;
2678         if (ug_info->ipCheckSumGenerate)
2679                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2680         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2681         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2682
2683         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2684
2685         /* Function code register value to be used later */
2686         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2687         /* Required for QE */
2688
2689         /* function code register */
2690         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2691
2692         /* Rx global PRAM */
2693         /* Allocate global rx parameter RAM page */
2694         ugeth->rx_glbl_pram_offset =
2695             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2696                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2697         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2698                 if (netif_msg_ifup(ugeth))
2699                         ugeth_err
2700                             ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2701                              __func__);
2702                 return -ENOMEM;
2703         }
2704         ugeth->p_rx_glbl_pram =
2705             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2706                                                         rx_glbl_pram_offset);
2707         /* Zero out p_rx_glbl_pram */
2708         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2709
2710         /* Fill global PRAM */
2711
2712         /* RQPTR */
2713         /* Size varies with number of Rx threads */
2714         ugeth->thread_dat_rx_offset =
2715             qe_muram_alloc(numThreadsRxNumerical *
2716                            sizeof(struct ucc_geth_thread_data_rx),
2717                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2718         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2719                 if (netif_msg_ifup(ugeth))
2720                         ugeth_err
2721                             ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2722                              __func__);
2723                 return -ENOMEM;
2724         }
2725
2726         ugeth->p_thread_data_rx =
2727             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2728                                                         thread_dat_rx_offset);
2729         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2730
2731         /* typeorlen */
2732         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2733
2734         /* rxrmonbaseptr (statistics) */
2735         if (ug_info->
2736             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2737                 ugeth->rx_fw_statistics_pram_offset =
2738                     qe_muram_alloc(sizeof
2739                                    (struct ucc_geth_rx_firmware_statistics_pram),
2740                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2741                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2742                         if (netif_msg_ifup(ugeth))
2743                                 ugeth_err
2744                                         ("%s: Can not allocate DPRAM memory for"
2745                                         " p_rx_fw_statistics_pram.", __func__);
2746                         return -ENOMEM;
2747                 }
2748                 ugeth->p_rx_fw_statistics_pram =
2749                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2750                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2751                 /* Zero out p_rx_fw_statistics_pram */
2752                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2753                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2754         }
2755
2756         /* intCoalescingPtr */
2757
2758         /* Size varies with number of Rx queues */
2759         ugeth->rx_irq_coalescing_tbl_offset =
2760             qe_muram_alloc(ug_info->numQueuesRx *
2761                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2762                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2763         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2764                 if (netif_msg_ifup(ugeth))
2765                         ugeth_err
2766                             ("%s: Can not allocate DPRAM memory for"
2767                                 " p_rx_irq_coalescing_tbl.", __func__);
2768                 return -ENOMEM;
2769         }
2770
2771         ugeth->p_rx_irq_coalescing_tbl =
2772             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2773             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2774         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2775                  ugeth->rx_irq_coalescing_tbl_offset);
2776
2777         /* Fill interrupt coalescing table */
2778         for (i = 0; i < ug_info->numQueuesRx; i++) {
2779                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2780                          interruptcoalescingmaxvalue,
2781                          ug_info->interruptcoalescingmaxvalue[i]);
2782                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2783                          interruptcoalescingcounter,
2784                          ug_info->interruptcoalescingmaxvalue[i]);
2785         }
2786
2787         /* MRBLR */
2788         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2789                              &ugeth->p_rx_glbl_pram->mrblr);
2790         /* MFLR */
2791         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2792         /* MINFLR */
2793         init_min_frame_len(ug_info->minFrameLength,
2794                            &ugeth->p_rx_glbl_pram->minflr,
2795                            &ugeth->p_rx_glbl_pram->mrblr);
2796         /* MAXD1 */
2797         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2798         /* MAXD2 */
2799         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2800
2801         /* l2qt */
2802         l2qt = 0;
2803         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2804                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2805         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2806
2807         /* l3qt */
2808         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2809                 l3qt = 0;
2810                 for (i = 0; i < 8; i++)
2811                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2812                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2813         }
2814
2815         /* vlantype */
2816         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2817
2818         /* vlantci */
2819         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2820
2821         /* ecamptr */
2822         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2823
2824         /* RBDQPTR */
2825         /* Size varies with number of Rx queues */
2826         ugeth->rx_bd_qs_tbl_offset =
2827             qe_muram_alloc(ug_info->numQueuesRx *
2828                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2829                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2830                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2831         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2832                 if (netif_msg_ifup(ugeth))
2833                         ugeth_err
2834                             ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2835                              __func__);
2836                 return -ENOMEM;
2837         }
2838
2839         ugeth->p_rx_bd_qs_tbl =
2840             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2841                                     rx_bd_qs_tbl_offset);
2842         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2843         /* Zero out p_rx_bd_qs_tbl */
2844         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2845                0,
2846                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2847                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2848
2849         /* Setup the table */
2850         /* Assume BD rings are already established */
2851         for (i = 0; i < ug_info->numQueuesRx; i++) {
2852                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2853                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2854                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2855                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2856                            MEM_PART_MURAM) {
2857                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2858                                  (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2859                 }
2860                 /* rest of fields handled by QE */
2861         }
2862
2863         /* remoder */
2864         /* Already has speed set */
2865
2866         if (ugeth->rx_extended_features)
2867                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2868         if (ug_info->rxExtendedFiltering)
2869                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2870         if (ug_info->dynamicMaxFrameLength)
2871                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2872         if (ug_info->dynamicMinFrameLength)
2873                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2874         remoder |=
2875             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2876         remoder |=
2877             ug_info->
2878             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2879         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2880         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2881         if (ug_info->ipCheckSumCheck)
2882                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2883         if (ug_info->ipAddressAlignment)
2884                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2885         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2886
2887         /* Note that this function must be called */
2888         /* ONLY AFTER p_tx_fw_statistics_pram */
2889         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2890         init_firmware_statistics_gathering_mode((ug_info->
2891                 statisticsMode &
2892                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2893                 (ug_info->statisticsMode &
2894                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2895                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2896                 ugeth->tx_fw_statistics_pram_offset,
2897                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2898                 ugeth->rx_fw_statistics_pram_offset,
2899                 &ugeth->p_tx_glbl_pram->temoder,
2900                 &ugeth->p_rx_glbl_pram->remoder);
2901
2902         /* function code register */
2903         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2904
2905         /* initialize extended filtering */
2906         if (ug_info->rxExtendedFiltering) {
2907                 if (!ug_info->extendedFilteringChainPointer) {
2908                         if (netif_msg_ifup(ugeth))
2909                                 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2910                                           __func__);
2911                         return -EINVAL;
2912                 }
2913
2914                 /* Allocate memory for extended filtering Mode Global
2915                 Parameters */
2916                 ugeth->exf_glbl_param_offset =
2917                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2918                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2919                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2920                         if (netif_msg_ifup(ugeth))
2921                                 ugeth_err
2922                                         ("%s: Can not allocate DPRAM memory for"
2923                                         " p_exf_glbl_param.", __func__);
2924                         return -ENOMEM;
2925                 }
2926
2927                 ugeth->p_exf_glbl_param =
2928                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2929                                  exf_glbl_param_offset);
2930                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2931                          ugeth->exf_glbl_param_offset);
2932                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2933                          (u32) ug_info->extendedFilteringChainPointer);
2934
2935         } else {                /* initialize 82xx style address filtering */
2936
2937                 /* Init individual address recognition registers to disabled */
2938
2939                 for (j = 0; j < NUM_OF_PADDRS; j++)
2940                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2941
2942                 p_82xx_addr_filt =
2943                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2944                     p_rx_glbl_pram->addressfiltering;
2945
2946                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2947                         ENET_ADDR_TYPE_GROUP);
2948                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2949                         ENET_ADDR_TYPE_INDIVIDUAL);
2950         }
2951
2952         /*
2953          * Initialize UCC at QE level
2954          */
2955
2956         command = QE_INIT_TX_RX;
2957
2958         /* Allocate shadow InitEnet command parameter structure.
2959          * This is needed because after the InitEnet command is executed,
2960          * the structure in DPRAM is released, because DPRAM is a premium
2961          * resource.
2962          * This shadow structure keeps a copy of what was done so that the
2963          * allocated resources can be released when the channel is freed.
2964          */
2965         if (!(ugeth->p_init_enet_param_shadow =
2966               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2967                 if (netif_msg_ifup(ugeth))
2968                         ugeth_err
2969                             ("%s: Can not allocate memory for"
2970                                 " p_UccInitEnetParamShadows.", __func__);
2971                 return -ENOMEM;
2972         }
2973         /* Zero out *p_init_enet_param_shadow */
2974         memset((char *)ugeth->p_init_enet_param_shadow,
2975                0, sizeof(struct ucc_geth_init_pram));
2976
2977         /* Fill shadow InitEnet command parameter structure */
2978
2979         ugeth->p_init_enet_param_shadow->resinit1 =
2980             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2981         ugeth->p_init_enet_param_shadow->resinit2 =
2982             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2983         ugeth->p_init_enet_param_shadow->resinit3 =
2984             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2985         ugeth->p_init_enet_param_shadow->resinit4 =
2986             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2987         ugeth->p_init_enet_param_shadow->resinit5 =
2988             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2989         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2990             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2991         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2992             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2993
2994         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2995             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2996         if ((ug_info->largestexternallookupkeysize !=
2997              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2998             (ug_info->largestexternallookupkeysize !=
2999              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
3000             (ug_info->largestexternallookupkeysize !=
3001              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3002                 if (netif_msg_ifup(ugeth))
3003                         ugeth_err("%s: Invalid largest External Lookup Key Size.",
3004                                   __func__);
3005                 return -EINVAL;
3006         }
3007         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3008             ug_info->largestexternallookupkeysize;
3009         size = sizeof(struct ucc_geth_thread_rx_pram);
3010         if (ug_info->rxExtendedFiltering) {
3011                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3012                 if (ug_info->largestexternallookupkeysize ==
3013                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3014                         size +=
3015                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3016                 if (ug_info->largestexternallookupkeysize ==
3017                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3018                         size +=
3019                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3020         }
3021
3022         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3023                 p_init_enet_param_shadow->rxthread[0]),
3024                 (u8) (numThreadsRxNumerical + 1)
3025                 /* Rx needs one extra for terminator */
3026                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3027                 ug_info->riscRx, 1)) != 0) {
3028                 if (netif_msg_ifup(ugeth))
3029                                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3030                                         __func__);
3031                 return ret_val;
3032         }
3033
3034         ugeth->p_init_enet_param_shadow->txglobal =
3035             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3036         if ((ret_val =
3037              fill_init_enet_entries(ugeth,
3038                                     &(ugeth->p_init_enet_param_shadow->
3039                                       txthread[0]), numThreadsTxNumerical,
3040                                     sizeof(struct ucc_geth_thread_tx_pram),
3041                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3042                                     ug_info->riscTx, 0)) != 0) {
3043                 if (netif_msg_ifup(ugeth))
3044                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3045                                   __func__);
3046                 return ret_val;
3047         }
3048
3049         /* Load Rx bds with buffers */
3050         for (i = 0; i < ug_info->numQueuesRx; i++) {
3051                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3052                         if (netif_msg_ifup(ugeth))
3053                                 ugeth_err("%s: Can not fill Rx bds with buffers.",
3054                                           __func__);
3055                         return ret_val;
3056                 }
3057         }
3058
3059         /* Allocate InitEnet command parameter structure */
3060         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3061         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3062                 if (netif_msg_ifup(ugeth))
3063                         ugeth_err
3064                             ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3065                              __func__);
3066                 return -ENOMEM;
3067         }
3068         p_init_enet_pram =
3069             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3070
3071         /* Copy shadow InitEnet command parameter structure into PRAM */
3072         out_8(&p_init_enet_pram->resinit1,
3073                         ugeth->p_init_enet_param_shadow->resinit1);
3074         out_8(&p_init_enet_pram->resinit2,
3075                         ugeth->p_init_enet_param_shadow->resinit2);
3076         out_8(&p_init_enet_pram->resinit3,
3077                         ugeth->p_init_enet_param_shadow->resinit3);
3078         out_8(&p_init_enet_pram->resinit4,
3079                         ugeth->p_init_enet_param_shadow->resinit4);
3080         out_be16(&p_init_enet_pram->resinit5,
3081                  ugeth->p_init_enet_param_shadow->resinit5);
3082         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3083             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3084         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3085                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3086         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3087                 out_be32(&p_init_enet_pram->rxthread[i],
3088                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3089         out_be32(&p_init_enet_pram->txglobal,
3090                  ugeth->p_init_enet_param_shadow->txglobal);
3091         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3092                 out_be32(&p_init_enet_pram->txthread[i],
3093                          ugeth->p_init_enet_param_shadow->txthread[i]);
3094
3095         /* Issue QE command */
3096         cecr_subblock =
3097             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3098         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3099                      init_enet_pram_offset);
3100
3101         /* Free InitEnet command parameter */
3102         qe_muram_free(init_enet_pram_offset);
3103
3104         return 0;
3105 }
3106
3107 /* This is called by the kernel when a frame is ready for transmission. */
3108 /* It is pointed to by the dev->hard_start_xmit function pointer */
3109 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3110 {
3111         struct ucc_geth_private *ugeth = netdev_priv(dev);
3112 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3113         struct ucc_fast_private *uccf;
3114 #endif
3115         u8 __iomem *bd;                 /* BD pointer */
3116         u32 bd_status;
3117         u8 txQ = 0;
3118         unsigned long flags;
3119
3120         ugeth_vdbg("%s: IN", __func__);
3121
3122         spin_lock_irqsave(&ugeth->lock, flags);
3123
3124         dev->stats.tx_bytes += skb->len;
3125
3126         /* Start from the next BD that should be filled */
3127         bd = ugeth->txBd[txQ];
3128         bd_status = in_be32((u32 __iomem *)bd);
3129         /* Save the skb pointer so we can free it later */
3130         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3131
3132         /* Update the current skb pointer (wrapping if this was the last) */
3133         ugeth->skb_curtx[txQ] =
3134             (ugeth->skb_curtx[txQ] +
3135              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3136
3137         /* set up the buffer descriptor */
3138         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3139                       dma_map_single(ugeth->dev, skb->data,
3140                               skb->len, DMA_TO_DEVICE));
3141
3142         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3143
3144         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3145
3146         /* set bd status and length */
3147         out_be32((u32 __iomem *)bd, bd_status);
3148
3149         /* Move to next BD in the ring */
3150         if (!(bd_status & T_W))
3151                 bd += sizeof(struct qe_bd);
3152         else
3153                 bd = ugeth->p_tx_bd_ring[txQ];
3154
3155         /* If the next BD still needs to be cleaned up, then the bds
3156            are full.  We need to tell the kernel to stop sending us stuff. */
3157         if (bd == ugeth->confBd[txQ]) {
3158                 if (!netif_queue_stopped(dev))
3159                         netif_stop_queue(dev);
3160         }
3161
3162         ugeth->txBd[txQ] = bd;
3163
3164         skb_tx_timestamp(skb);
3165
3166         if (ugeth->p_scheduler) {
3167                 ugeth->cpucount[txQ]++;
3168                 /* Indicate to QE that there are more Tx bds ready for
3169                 transmission */
3170                 /* This is done by writing a running counter of the bd
3171                 count to the scheduler PRAM. */
3172                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3173         }
3174
3175 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3176         uccf = ugeth->uccf;
3177         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3178 #endif
3179         spin_unlock_irqrestore(&ugeth->lock, flags);
3180
3181         return NETDEV_TX_OK;
3182 }
3183
3184 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3185 {
3186         struct sk_buff *skb;
3187         u8 __iomem *bd;
3188         u16 length, howmany = 0;
3189         u32 bd_status;
3190         u8 *bdBuffer;
3191         struct net_device *dev;
3192
3193         ugeth_vdbg("%s: IN", __func__);
3194
3195         dev = ugeth->ndev;
3196
3197         /* collect received buffers */
3198         bd = ugeth->rxBd[rxQ];
3199
3200         bd_status = in_be32((u32 __iomem *)bd);
3201
3202         /* while there are received buffers and BD is full (~R_E) */
3203         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3204                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3205                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3206                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3207
3208                 /* determine whether buffer is first, last, first and last
3209                 (single buffer frame) or middle (not first and not last) */
3210                 if (!skb ||
3211                     (!(bd_status & (R_F | R_L))) ||
3212                     (bd_status & R_ERRORS_FATAL)) {
3213                         if (netif_msg_rx_err(ugeth))
3214                                 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3215                                            __func__, __LINE__, (u32) skb);
3216                         if (skb) {
3217                                 skb->data = skb->head + NET_SKB_PAD;
3218                                 skb->len = 0;
3219                                 skb_reset_tail_pointer(skb);
3220                                 __skb_queue_head(&ugeth->rx_recycle, skb);
3221                         }
3222
3223                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3224                         dev->stats.rx_dropped++;
3225                 } else {
3226                         dev->stats.rx_packets++;
3227                         howmany++;
3228
3229                         /* Prep the skb for the packet */
3230                         skb_put(skb, length);
3231
3232                         /* Tell the skb what kind of packet this is */
3233                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3234
3235                         dev->stats.rx_bytes += length;
3236                         /* Send the packet up the stack */
3237                         netif_receive_skb(skb);
3238                 }
3239
3240                 skb = get_new_skb(ugeth, bd);
3241                 if (!skb) {
3242                         if (netif_msg_rx_err(ugeth))
3243                                 ugeth_warn("%s: No Rx Data Buffer", __func__);
3244                         dev->stats.rx_dropped++;
3245                         break;
3246                 }
3247
3248                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3249
3250                 /* update to point at the next skb */
3251                 ugeth->skb_currx[rxQ] =
3252                     (ugeth->skb_currx[rxQ] +
3253                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3254
3255                 if (bd_status & R_W)
3256                         bd = ugeth->p_rx_bd_ring[rxQ];
3257                 else
3258                         bd += sizeof(struct qe_bd);
3259
3260                 bd_status = in_be32((u32 __iomem *)bd);
3261         }
3262
3263         ugeth->rxBd[rxQ] = bd;
3264         return howmany;
3265 }
3266
3267 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3268 {
3269         /* Start from the next BD that should be filled */
3270         struct ucc_geth_private *ugeth = netdev_priv(dev);
3271         u8 __iomem *bd;         /* BD pointer */
3272         u32 bd_status;
3273
3274         bd = ugeth->confBd[txQ];
3275         bd_status = in_be32((u32 __iomem *)bd);
3276
3277         /* Normal processing. */
3278         while ((bd_status & T_R) == 0) {
3279                 struct sk_buff *skb;
3280
3281                 /* BD contains already transmitted buffer.   */
3282                 /* Handle the transmitted buffer and release */
3283                 /* the BD to be used with the current frame  */
3284
3285                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3286                 if (!skb)
3287                         break;
3288
3289                 dev->stats.tx_packets++;
3290
3291                 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3292                              skb_recycle_check(skb,
3293                                     ugeth->ug_info->uf_info.max_rx_buf_length +
3294                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3295                         __skb_queue_head(&ugeth->rx_recycle, skb);
3296                 else
3297                         dev_kfree_skb(skb);
3298
3299                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3300                 ugeth->skb_dirtytx[txQ] =
3301                     (ugeth->skb_dirtytx[txQ] +
3302                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3303
3304                 /* We freed a buffer, so now we can restart transmission */
3305                 if (netif_queue_stopped(dev))
3306                         netif_wake_queue(dev);
3307
3308                 /* Advance the confirmation BD pointer */
3309                 if (!(bd_status & T_W))
3310                         bd += sizeof(struct qe_bd);
3311                 else
3312                         bd = ugeth->p_tx_bd_ring[txQ];
3313                 bd_status = in_be32((u32 __iomem *)bd);
3314         }
3315         ugeth->confBd[txQ] = bd;
3316         return 0;
3317 }
3318
3319 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3320 {
3321         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3322         struct ucc_geth_info *ug_info;
3323         int howmany, i;
3324
3325         ug_info = ugeth->ug_info;
3326
3327         /* Tx event processing */
3328         spin_lock(&ugeth->lock);
3329         for (i = 0; i < ug_info->numQueuesTx; i++)
3330                 ucc_geth_tx(ugeth->ndev, i);
3331         spin_unlock(&ugeth->lock);
3332
3333         howmany = 0;
3334         for (i = 0; i < ug_info->numQueuesRx; i++)
3335                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3336
3337         if (howmany < budget) {
3338                 napi_complete(napi);
3339                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3340         }
3341
3342         return howmany;
3343 }
3344
3345 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3346 {
3347         struct net_device *dev = info;
3348         struct ucc_geth_private *ugeth = netdev_priv(dev);
3349         struct ucc_fast_private *uccf;
3350         struct ucc_geth_info *ug_info;
3351         register u32 ucce;
3352         register u32 uccm;
3353
3354         ugeth_vdbg("%s: IN", __func__);
3355
3356         uccf = ugeth->uccf;
3357         ug_info = ugeth->ug_info;
3358
3359         /* read and clear events */
3360         ucce = (u32) in_be32(uccf->p_ucce);
3361         uccm = (u32) in_be32(uccf->p_uccm);
3362         ucce &= uccm;
3363         out_be32(uccf->p_ucce, ucce);
3364
3365         /* check for receive events that require processing */
3366         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3367                 if (napi_schedule_prep(&ugeth->napi)) {
3368                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3369                         out_be32(uccf->p_uccm, uccm);
3370                         __napi_schedule(&ugeth->napi);
3371                 }
3372         }
3373
3374         /* Errors and other events */
3375         if (ucce & UCCE_OTHER) {
3376                 if (ucce & UCC_GETH_UCCE_BSY)
3377                         dev->stats.rx_errors++;
3378                 if (ucce & UCC_GETH_UCCE_TXE)
3379                         dev->stats.tx_errors++;
3380         }
3381
3382         return IRQ_HANDLED;
3383 }
3384
3385 #ifdef CONFIG_NET_POLL_CONTROLLER
3386 /*
3387  * Polling 'interrupt' - used by things like netconsole to send skbs
3388  * without having to re-enable interrupts. It's not called while
3389  * the interrupt routine is executing.
3390  */
3391 static void ucc_netpoll(struct net_device *dev)
3392 {
3393         struct ucc_geth_private *ugeth = netdev_priv(dev);
3394         int irq = ugeth->ug_info->uf_info.irq;
3395
3396         disable_irq(irq);
3397         ucc_geth_irq_handler(irq, dev);
3398         enable_irq(irq);
3399 }
3400 #endif /* CONFIG_NET_POLL_CONTROLLER */
3401
3402 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3403 {
3404         struct ucc_geth_private *ugeth = netdev_priv(dev);
3405         struct sockaddr *addr = p;
3406
3407         if (!is_valid_ether_addr(addr->sa_data))
3408                 return -EADDRNOTAVAIL;
3409
3410         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3411
3412         /*
3413          * If device is not running, we will set mac addr register
3414          * when opening the device.
3415          */
3416         if (!netif_running(dev))
3417                 return 0;
3418
3419         spin_lock_irq(&ugeth->lock);
3420         init_mac_station_addr_regs(dev->dev_addr[0],
3421                                    dev->dev_addr[1],
3422                                    dev->dev_addr[2],
3423                                    dev->dev_addr[3],
3424                                    dev->dev_addr[4],
3425                                    dev->dev_addr[5],
3426                                    &ugeth->ug_regs->macstnaddr1,
3427                                    &ugeth->ug_regs->macstnaddr2);
3428         spin_unlock_irq(&ugeth->lock);
3429
3430         return 0;
3431 }
3432
3433 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3434 {
3435         struct net_device *dev = ugeth->ndev;
3436         int err;
3437
3438         err = ucc_struct_init(ugeth);
3439         if (err) {
3440                 if (netif_msg_ifup(ugeth))
3441                         ugeth_err("%s: Cannot configure internal struct, "
3442                                   "aborting.", dev->name);
3443                 goto err;
3444         }
3445
3446         err = ucc_geth_startup(ugeth);
3447         if (err) {
3448                 if (netif_msg_ifup(ugeth))
3449                         ugeth_err("%s: Cannot configure net device, aborting.",
3450                                   dev->name);
3451                 goto err;
3452         }
3453
3454         err = adjust_enet_interface(ugeth);
3455         if (err) {
3456                 if (netif_msg_ifup(ugeth))
3457                         ugeth_err("%s: Cannot configure net device, aborting.",
3458                                   dev->name);
3459                 goto err;
3460         }
3461
3462         /*       Set MACSTNADDR1, MACSTNADDR2                */
3463         /* For more details see the hardware spec.           */
3464         init_mac_station_addr_regs(dev->dev_addr[0],
3465                                    dev->dev_addr[1],
3466                                    dev->dev_addr[2],
3467                                    dev->dev_addr[3],
3468                                    dev->dev_addr[4],
3469                                    dev->dev_addr[5],
3470                                    &ugeth->ug_regs->macstnaddr1,
3471                                    &ugeth->ug_regs->macstnaddr2);
3472
3473         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3474         if (err) {
3475                 if (netif_msg_ifup(ugeth))
3476                         ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3477                 goto err;
3478         }
3479
3480         return 0;
3481 err:
3482         ucc_geth_stop(ugeth);
3483         return err;
3484 }
3485
3486 /* Called when something needs to use the ethernet device */
3487 /* Returns 0 for success. */
3488 static int ucc_geth_open(struct net_device *dev)
3489 {
3490         struct ucc_geth_private *ugeth = netdev_priv(dev);
3491         int err;
3492
3493         ugeth_vdbg("%s: IN", __func__);
3494
3495         /* Test station address */
3496         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3497                 if (netif_msg_ifup(ugeth))
3498                         ugeth_err("%s: Multicast address used for station "
3499                                   "address - is this what you wanted?",
3500                                   __func__);
3501                 return -EINVAL;
3502         }
3503
3504         err = init_phy(dev);
3505         if (err) {
3506                 if (netif_msg_ifup(ugeth))
3507                         ugeth_err("%s: Cannot initialize PHY, aborting.",
3508                                   dev->name);
3509                 return err;
3510         }
3511
3512         err = ucc_geth_init_mac(ugeth);
3513         if (err) {
3514                 if (netif_msg_ifup(ugeth))
3515                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3516                                   dev->name);
3517                 goto err;
3518         }
3519
3520         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3521                           0, "UCC Geth", dev);
3522         if (err) {
3523                 if (netif_msg_ifup(ugeth))
3524                         ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3525                                   dev->name);
3526                 goto err;
3527         }
3528
3529         phy_start(ugeth->phydev);
3530         napi_enable(&ugeth->napi);
3531         netif_start_queue(dev);
3532
3533         device_set_wakeup_capable(&dev->dev,
3534                         qe_alive_during_sleep() || ugeth->phydev->irq);
3535         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3536
3537         return err;
3538
3539 err:
3540         ucc_geth_stop(ugeth);
3541         return err;
3542 }
3543
3544 /* Stops the kernel queue, and halts the controller */
3545 static int ucc_geth_close(struct net_device *dev)
3546 {
3547         struct ucc_geth_private *ugeth = netdev_priv(dev);
3548
3549         ugeth_vdbg("%s: IN", __func__);
3550
3551         napi_disable(&ugeth->napi);
3552
3553         cancel_work_sync(&ugeth->timeout_work);
3554         ucc_geth_stop(ugeth);
3555         phy_disconnect(ugeth->phydev);
3556         ugeth->phydev = NULL;
3557
3558         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3559
3560         netif_stop_queue(dev);
3561
3562         return 0;
3563 }
3564
3565 /* Reopen device. This will reset the MAC and PHY. */
3566 static void ucc_geth_timeout_work(struct work_struct *work)
3567 {
3568         struct ucc_geth_private *ugeth;
3569         struct net_device *dev;
3570
3571         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3572         dev = ugeth->ndev;
3573
3574         ugeth_vdbg("%s: IN", __func__);
3575
3576         dev->stats.tx_errors++;
3577
3578         ugeth_dump_regs(ugeth);
3579
3580         if (dev->flags & IFF_UP) {
3581                 /*
3582                  * Must reset MAC *and* PHY. This is done by reopening
3583                  * the device.
3584                  */
3585                 netif_tx_stop_all_queues(dev);
3586                 ucc_geth_stop(ugeth);
3587                 ucc_geth_init_mac(ugeth);
3588                 /* Must start PHY here */
3589                 phy_start(ugeth->phydev);
3590                 netif_tx_start_all_queues(dev);
3591         }
3592
3593         netif_tx_schedule_all(dev);
3594 }
3595
3596 /*
3597  * ucc_geth_timeout gets called when a packet has not been
3598  * transmitted after a set amount of time.
3599  */
3600 static void ucc_geth_timeout(struct net_device *dev)
3601 {
3602         struct ucc_geth_private *ugeth = netdev_priv(dev);
3603
3604         schedule_work(&ugeth->timeout_work);
3605 }
3606
3607
3608 #ifdef CONFIG_PM
3609
3610 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3611 {
3612         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3613         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3614
3615         if (!netif_running(ndev))
3616                 return 0;
3617
3618         netif_device_detach(ndev);
3619         napi_disable(&ugeth->napi);
3620
3621         /*
3622          * Disable the controller, otherwise we'll wakeup on any network
3623          * activity.
3624          */
3625         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3626
3627         if (ugeth->wol_en & WAKE_MAGIC) {
3628                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3629                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3630                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3631         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3632                 phy_stop(ugeth->phydev);
3633         }
3634
3635         return 0;
3636 }
3637
3638 static int ucc_geth_resume(struct platform_device *ofdev)
3639 {
3640         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3641         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3642         int err;
3643
3644         if (!netif_running(ndev))
3645                 return 0;
3646
3647         if (qe_alive_during_sleep()) {
3648                 if (ugeth->wol_en & WAKE_MAGIC) {
3649                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3650                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3651                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3652                 }
3653                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3654         } else {
3655                 /*
3656                  * Full reinitialization is required if QE shuts down
3657                  * during sleep.
3658                  */
3659                 ucc_geth_memclean(ugeth);
3660
3661                 err = ucc_geth_init_mac(ugeth);
3662                 if (err) {
3663                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3664                                   ndev->name);
3665                         return err;
3666                 }
3667         }
3668
3669         ugeth->oldlink = 0;
3670         ugeth->oldspeed = 0;
3671         ugeth->oldduplex = -1;
3672
3673         phy_stop(ugeth->phydev);
3674         phy_start(ugeth->phydev);
3675
3676         napi_enable(&ugeth->napi);
3677         netif_device_attach(ndev);
3678
3679         return 0;
3680 }
3681
3682 #else
3683 #define ucc_geth_suspend NULL
3684 #define ucc_geth_resume NULL
3685 #endif
3686
3687 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3688 {
3689         if (strcasecmp(phy_connection_type, "mii") == 0)
3690                 return PHY_INTERFACE_MODE_MII;
3691         if (strcasecmp(phy_connection_type, "gmii") == 0)
3692                 return PHY_INTERFACE_MODE_GMII;
3693         if (strcasecmp(phy_connection_type, "tbi") == 0)
3694                 return PHY_INTERFACE_MODE_TBI;
3695         if (strcasecmp(phy_connection_type, "rmii") == 0)
3696                 return PHY_INTERFACE_MODE_RMII;
3697         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3698                 return PHY_INTERFACE_MODE_RGMII;
3699         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3700                 return PHY_INTERFACE_MODE_RGMII_ID;
3701         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3702                 return PHY_INTERFACE_MODE_RGMII_TXID;
3703         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3704                 return PHY_INTERFACE_MODE_RGMII_RXID;
3705         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3706                 return PHY_INTERFACE_MODE_RTBI;
3707         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3708                 return PHY_INTERFACE_MODE_SGMII;
3709
3710         return PHY_INTERFACE_MODE_MII;
3711 }
3712
3713 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3714 {
3715         struct ucc_geth_private *ugeth = netdev_priv(dev);
3716
3717         if (!netif_running(dev))
3718                 return -EINVAL;
3719
3720         if (!ugeth->phydev)
3721                 return -ENODEV;
3722
3723         return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3724 }
3725
3726 static const struct net_device_ops ucc_geth_netdev_ops = {
3727         .ndo_open               = ucc_geth_open,
3728         .ndo_stop               = ucc_geth_close,
3729         .ndo_start_xmit         = ucc_geth_start_xmit,
3730         .ndo_validate_addr      = eth_validate_addr,
3731         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3732         .ndo_change_mtu         = eth_change_mtu,
3733         .ndo_set_rx_mode        = ucc_geth_set_multi,
3734         .ndo_tx_timeout         = ucc_geth_timeout,
3735         .ndo_do_ioctl           = ucc_geth_ioctl,
3736 #ifdef CONFIG_NET_POLL_CONTROLLER
3737         .ndo_poll_controller    = ucc_netpoll,
3738 #endif
3739 };
3740
3741 static int ucc_geth_probe(struct platform_device* ofdev)
3742 {
3743         struct device *device = &ofdev->dev;
3744         struct device_node *np = ofdev->dev.of_node;
3745         struct net_device *dev = NULL;
3746         struct ucc_geth_private *ugeth = NULL;
3747         struct ucc_geth_info *ug_info;
3748         struct resource res;
3749         int err, ucc_num, max_speed = 0;
3750         const unsigned int *prop;
3751         const char *sprop;
3752         const void *mac_addr;
3753         phy_interface_t phy_interface;
3754         static const int enet_to_speed[] = {
3755                 SPEED_10, SPEED_10, SPEED_10,
3756                 SPEED_100, SPEED_100, SPEED_100,
3757                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3758         };
3759         static const phy_interface_t enet_to_phy_interface[] = {
3760                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3761                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3762                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3763                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3764                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3765                 PHY_INTERFACE_MODE_SGMII,
3766         };
3767
3768         ugeth_vdbg("%s: IN", __func__);
3769
3770         prop = of_get_property(np, "cell-index", NULL);
3771         if (!prop) {
3772                 prop = of_get_property(np, "device-id", NULL);
3773                 if (!prop)
3774                         return -ENODEV;
3775         }
3776
3777         ucc_num = *prop - 1;
3778         if ((ucc_num < 0) || (ucc_num > 7))
3779                 return -ENODEV;
3780
3781         ug_info = &ugeth_info[ucc_num];
3782         if (ug_info == NULL) {
3783                 if (netif_msg_probe(&debug))
3784                         ugeth_err("%s: [%d] Missing additional data!",
3785                                         __func__, ucc_num);
3786                 return -ENODEV;
3787         }
3788
3789         ug_info->uf_info.ucc_num = ucc_num;
3790
3791         sprop = of_get_property(np, "rx-clock-name", NULL);
3792         if (sprop) {
3793                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3794                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3795                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3796                         printk(KERN_ERR
3797                                 "ucc_geth: invalid rx-clock-name property\n");
3798                         return -EINVAL;
3799                 }
3800         } else {
3801                 prop = of_get_property(np, "rx-clock", NULL);
3802                 if (!prop) {
3803                         /* If both rx-clock-name and rx-clock are missing,
3804                            we want to tell people to use rx-clock-name. */
3805                         printk(KERN_ERR
3806                                 "ucc_geth: missing rx-clock-name property\n");
3807                         return -EINVAL;
3808                 }
3809                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3810                         printk(KERN_ERR
3811                                 "ucc_geth: invalid rx-clock propperty\n");
3812                         return -EINVAL;
3813                 }
3814                 ug_info->uf_info.rx_clock = *prop;
3815         }
3816
3817         sprop = of_get_property(np, "tx-clock-name", NULL);
3818         if (sprop) {
3819                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3820                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3821                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3822                         printk(KERN_ERR
3823                                 "ucc_geth: invalid tx-clock-name property\n");
3824                         return -EINVAL;
3825                 }
3826         } else {
3827                 prop = of_get_property(np, "tx-clock", NULL);
3828                 if (!prop) {
3829                         printk(KERN_ERR
3830                                 "ucc_geth: missing tx-clock-name property\n");
3831                         return -EINVAL;
3832                 }
3833                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3834                         printk(KERN_ERR
3835                                 "ucc_geth: invalid tx-clock property\n");
3836                         return -EINVAL;
3837                 }
3838                 ug_info->uf_info.tx_clock = *prop;
3839         }
3840
3841         err = of_address_to_resource(np, 0, &res);
3842         if (err)
3843                 return -EINVAL;
3844
3845         ug_info->uf_info.regs = res.start;
3846         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3847
3848         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3849
3850         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3851         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3852
3853         /* get the phy interface type, or default to MII */
3854         prop = of_get_property(np, "phy-connection-type", NULL);
3855         if (!prop) {
3856                 /* handle interface property present in old trees */
3857                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3858                 if (prop != NULL) {
3859                         phy_interface = enet_to_phy_interface[*prop];
3860                         max_speed = enet_to_speed[*prop];
3861                 } else
3862                         phy_interface = PHY_INTERFACE_MODE_MII;
3863         } else {
3864                 phy_interface = to_phy_interface((const char *)prop);
3865         }
3866
3867         /* get speed, or derive from PHY interface */
3868         if (max_speed == 0)
3869                 switch (phy_interface) {
3870                 case PHY_INTERFACE_MODE_GMII:
3871                 case PHY_INTERFACE_MODE_RGMII:
3872                 case PHY_INTERFACE_MODE_RGMII_ID:
3873                 case PHY_INTERFACE_MODE_RGMII_RXID:
3874                 case PHY_INTERFACE_MODE_RGMII_TXID:
3875                 case PHY_INTERFACE_MODE_TBI:
3876                 case PHY_INTERFACE_MODE_RTBI:
3877                 case PHY_INTERFACE_MODE_SGMII:
3878                         max_speed = SPEED_1000;
3879                         break;
3880                 default:
3881                         max_speed = SPEED_100;
3882                         break;
3883                 }
3884
3885         if (max_speed == SPEED_1000) {
3886                 /* configure muram FIFOs for gigabit operation */
3887                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3888                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3889                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3890                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3891                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3892                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3893                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3894
3895                 /* If QE's snum number is 46 which means we need to support
3896                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3897                  * more Threads to Rx.
3898                  */
3899                 if (qe_get_num_of_snums() == 46)
3900                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3901                 else
3902                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3903         }
3904
3905         if (netif_msg_probe(&debug))
3906                 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d)\n",
3907                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3908                         ug_info->uf_info.irq);
3909
3910         /* Create an ethernet device instance */
3911         dev = alloc_etherdev(sizeof(*ugeth));
3912
3913         if (dev == NULL)
3914                 return -ENOMEM;
3915
3916         ugeth = netdev_priv(dev);
3917         spin_lock_init(&ugeth->lock);
3918
3919         /* Create CQs for hash tables */
3920         INIT_LIST_HEAD(&ugeth->group_hash_q);
3921         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3922
3923         dev_set_drvdata(device, dev);
3924
3925         /* Set the dev->base_addr to the gfar reg region */
3926         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3927
3928         SET_NETDEV_DEV(dev, device);
3929
3930         /* Fill in the dev structure */
3931         uec_set_ethtool_ops(dev);
3932         dev->netdev_ops = &ucc_geth_netdev_ops;
3933         dev->watchdog_timeo = TX_TIMEOUT;
3934         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3935         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3936         dev->mtu = 1500;
3937
3938         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3939         ugeth->phy_interface = phy_interface;
3940         ugeth->max_speed = max_speed;
3941
3942         err = register_netdev(dev);
3943         if (err) {
3944                 if (netif_msg_probe(ugeth))
3945                         ugeth_err("%s: Cannot register net device, aborting.",
3946                                   dev->name);
3947                 free_netdev(dev);
3948                 return err;
3949         }
3950
3951         mac_addr = of_get_mac_address(np);
3952         if (mac_addr)
3953                 memcpy(dev->dev_addr, mac_addr, 6);
3954
3955         ugeth->ug_info = ug_info;
3956         ugeth->dev = device;
3957         ugeth->ndev = dev;
3958         ugeth->node = np;
3959
3960         return 0;
3961 }
3962
3963 static int ucc_geth_remove(struct platform_device* ofdev)
3964 {
3965         struct device *device = &ofdev->dev;
3966         struct net_device *dev = dev_get_drvdata(device);
3967         struct ucc_geth_private *ugeth = netdev_priv(dev);
3968
3969         unregister_netdev(dev);
3970         free_netdev(dev);
3971         ucc_geth_memclean(ugeth);
3972         dev_set_drvdata(device, NULL);
3973
3974         return 0;
3975 }
3976
3977 static struct of_device_id ucc_geth_match[] = {
3978         {
3979                 .type = "network",
3980                 .compatible = "ucc_geth",
3981         },
3982         {},
3983 };
3984
3985 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3986
3987 static struct platform_driver ucc_geth_driver = {
3988         .driver = {
3989                 .name = DRV_NAME,
3990                 .owner = THIS_MODULE,
3991                 .of_match_table = ucc_geth_match,
3992         },
3993         .probe          = ucc_geth_probe,
3994         .remove         = ucc_geth_remove,
3995         .suspend        = ucc_geth_suspend,
3996         .resume         = ucc_geth_resume,
3997 };
3998
3999 static int __init ucc_geth_init(void)
4000 {
4001         int i, ret;
4002
4003         if (netif_msg_drv(&debug))
4004                 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
4005         for (i = 0; i < 8; i++)
4006                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4007                        sizeof(ugeth_primary_info));
4008
4009         ret = platform_driver_register(&ucc_geth_driver);
4010
4011         return ret;
4012 }
4013
4014 static void __exit ucc_geth_exit(void)
4015 {
4016         platform_driver_unregister(&ucc_geth_driver);
4017 }
4018
4019 module_init(ucc_geth_init);
4020 module_exit(ucc_geth_exit);
4021
4022 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4023 MODULE_DESCRIPTION(DRV_DESC);
4024 MODULE_VERSION(DRV_VERSION);
4025 MODULE_LICENSE("GPL");