drivers/net/ethernet/dec/tulip/media.c

   1 /*
   2         drivers/net/tulip/media.c
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please submit bugs to http://bugzilla.kernel.org/ .
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/mii.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pci.h>
  18 #include "tulip.h"
  19
  20
  21 /* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
  22    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
  23    "overclocking" issues or future 66Mhz PCI. */
  24 #define mdio_delay() ioread32(mdio_addr)
  25
  26 /* Read and write the MII registers using software-generated serial
  27    MDIO protocol.  It is just different enough from the EEPROM protocol
  28    to not share code.  The maxium data clock rate is 2.5 Mhz. */
  29 #define MDIO_SHIFT_CLK          0x10000
  30 #define MDIO_DATA_WRITE0        0x00000
  31 #define MDIO_DATA_WRITE1        0x20000
  32 #define MDIO_ENB                0x00000 /* Ignore the 0x02000 databook setting. */
  33 #define MDIO_ENB_IN             0x40000
  34 #define MDIO_DATA_READ          0x80000
  35
  36 static const unsigned char comet_miireg2offset[32] = {
  37         0xB4, 0xB8, 0xBC, 0xC0,  0xC4, 0xC8, 0xCC, 0,  0,0,0,0,  0,0,0,0,
  38         0,0xD0,0,0,  0,0,0,0,  0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
  39
  40
  41 /* MII transceiver control section.
  42    Read and write the MII registers using software-generated serial
  43    MDIO protocol.
  44    See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
  45    or DP83840A data sheet for more details.
  46    */
  47
  48 int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
  49 {
  50         struct tulip_private *tp = netdev_priv(dev);
  51         int i;
  52         int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
  53         int retval = 0;
  54         void __iomem *ioaddr = tp->base_addr;
  55         void __iomem *mdio_addr = ioaddr + CSR9;
  56         unsigned long flags;
  57
  58         if (location & ~0x1f)
  59                 return 0xffff;
  60
  61         if (tp->chip_id == COMET  &&  phy_id == 30) {
  62                 if (comet_miireg2offset[location])
  63                         return ioread32(ioaddr + comet_miireg2offset[location]);
  64                 return 0xffff;
  65         }
  66
  67         spin_lock_irqsave(&tp->mii_lock, flags);
  68         if (tp->chip_id == LC82C168) {
  69                 iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
  70                 ioread32(ioaddr + 0xA0);
  71                 ioread32(ioaddr + 0xA0);
  72                 for (i = 1000; i >= 0; --i) {
  73                         barrier();
  74                         if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
  75                                 break;
  76                 }
  77                 spin_unlock_irqrestore(&tp->mii_lock, flags);
  78                 return retval & 0xffff;
  79         }
  80
  81         /* Establish sync by sending at least 32 logic ones. */
  82         for (i = 32; i >= 0; i--) {
  83                 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
  84                 mdio_delay();
  85                 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
  86                 mdio_delay();
  87         }
  88         /* Shift the read command bits out. */
  89         for (i = 15; i >= 0; i--) {
  90                 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
  91
  92                 iowrite32(MDIO_ENB | dataval, mdio_addr);
  93                 mdio_delay();
  94                 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
  95                 mdio_delay();
  96         }
  97         /* Read the two transition, 16 data, and wire-idle bits. */
  98         for (i = 19; i > 0; i--) {
  99                 iowrite32(MDIO_ENB_IN, mdio_addr);
 100                 mdio_delay();
 101                 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
 102                 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
 103                 mdio_delay();
 104         }
 105
 106         spin_unlock_irqrestore(&tp->mii_lock, flags);
 107         return (retval>>1) & 0xffff;
 108 }
 109
 110 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
 111 {
 112         struct tulip_private *tp = netdev_priv(dev);
 113         int i;
 114         int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
 115         void __iomem *ioaddr = tp->base_addr;
 116         void __iomem *mdio_addr = ioaddr + CSR9;
 117         unsigned long flags;
 118
 119         if (location & ~0x1f)
 120                 return;
 121
 122         if (tp->chip_id == COMET && phy_id == 30) {
 123                 if (comet_miireg2offset[location])
 124                         iowrite32(val, ioaddr + comet_miireg2offset[location]);
 125                 return;
 126         }
 127
 128         spin_lock_irqsave(&tp->mii_lock, flags);
 129         if (tp->chip_id == LC82C168) {
 130                 iowrite32(cmd, ioaddr + 0xA0);
 131                 for (i = 1000; i >= 0; --i) {
 132                         barrier();
 133                         if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
 134                                 break;
 135                 }
 136                 spin_unlock_irqrestore(&tp->mii_lock, flags);
 137                 return;
 138         }
 139
 140         /* Establish sync by sending 32 logic ones. */
 141         for (i = 32; i >= 0; i--) {
 142                 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
 143                 mdio_delay();
 144                 iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
 145                 mdio_delay();
 146         }
 147         /* Shift the command bits out. */
 148         for (i = 31; i >= 0; i--) {
 149                 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
 150                 iowrite32(MDIO_ENB | dataval, mdio_addr);
 151                 mdio_delay();
 152                 iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
 153                 mdio_delay();
 154         }
 155         /* Clear out extra bits. */
 156         for (i = 2; i > 0; i--) {
 157                 iowrite32(MDIO_ENB_IN, mdio_addr);
 158                 mdio_delay();
 159                 iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
 160                 mdio_delay();
 161         }
 162
 163         spin_unlock_irqrestore(&tp->mii_lock, flags);
 164 }
 165
 166
 167 /* Set up the transceiver control registers for the selected media type. */
 168 void tulip_select_media(struct net_device *dev, int startup)
 169 {
 170         struct tulip_private *tp = netdev_priv(dev);
 171         void __iomem *ioaddr = tp->base_addr;
 172         struct mediatable *mtable = tp->mtable;
 173         u32 new_csr6;
 174         int i;
 175
 176         if (mtable) {
 177                 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
 178                 unsigned char *p = mleaf->leafdata;
 179                 switch (mleaf->type) {
 180                 case 0:                                 /* 21140 non-MII xcvr. */
 181                         if (tulip_debug > 1)
 182                                 netdev_dbg(dev, "Using a 21140 non-MII transceiver with control setting %02x\n",
 183                                            p[1]);
 184                         dev->if_port = p[0];
 185                         if (startup)
 186                                 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
 187                         iowrite32(p[1], ioaddr + CSR12);
 188                         new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
 189                         break;
 190                 case 2: case 4: {
 191                         u16 setup[5];
 192                         u32 csr13val, csr14val, csr15dir, csr15val;
 193                         for (i = 0; i < 5; i++)
 194                                 setup[i] = get_u16(&p[i*2 + 1]);
 195
 196                         dev->if_port = p[0] & MEDIA_MASK;
 197                         if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
 198                                 tp->full_duplex = 1;
 199
 200                         if (startup && mtable->has_reset) {
 201                                 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
 202                                 unsigned char *rst = rleaf->leafdata;
 203                                 if (tulip_debug > 1)
 204                                         netdev_dbg(dev, "Resetting the transceiver\n");
 205                                 for (i = 0; i < rst[0]; i++)
 206                                         iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
 207                         }
 208                         if (tulip_debug > 1)
 209                                 netdev_dbg(dev, "21143 non-MII %s transceiver control %04x/%04x\n",
 210                                            medianame[dev->if_port],
 211                                            setup[0], setup[1]);
 212                         if (p[0] & 0x40) {      /* SIA (CSR13-15) setup values are provided. */
 213                                 csr13val = setup[0];
 214                                 csr14val = setup[1];
 215                                 csr15dir = (setup[3]<<16) | setup[2];
 216                                 csr15val = (setup[4]<<16) | setup[2];
 217                                 iowrite32(0, ioaddr + CSR13);
 218                                 iowrite32(csr14val, ioaddr + CSR14);
 219                                 iowrite32(csr15dir, ioaddr + CSR15);    /* Direction */
 220                                 iowrite32(csr15val, ioaddr + CSR15);    /* Data */
 221                                 iowrite32(csr13val, ioaddr + CSR13);
 222                         } else {
 223                                 csr13val = 1;
 224                                 csr14val = 0;
 225                                 csr15dir = (setup[0]<<16) | 0x0008;
 226                                 csr15val = (setup[1]<<16) | 0x0008;
 227                                 if (dev->if_port <= 4)
 228                                         csr14val = t21142_csr14[dev->if_port];
 229                                 if (startup) {
 230                                         iowrite32(0, ioaddr + CSR13);
 231                                         iowrite32(csr14val, ioaddr + CSR14);
 232                                 }
 233                                 iowrite32(csr15dir, ioaddr + CSR15);    /* Direction */
 234                                 iowrite32(csr15val, ioaddr + CSR15);    /* Data */
 235                                 if (startup) iowrite32(csr13val, ioaddr + CSR13);
 236                         }
 237                         if (tulip_debug > 1)
 238                                 netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
 239                                            csr15dir, csr15val);
 240                         if (mleaf->type == 4)
 241                                 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
 242                         else
 243                                 new_csr6 = 0x82420000;
 244                         break;
 245                 }
 246                 case 1: case 3: {
 247                         int phy_num = p[0];
 248                         int init_length = p[1];
 249                         u16 *misc_info, tmp_info;
 250
 251                         dev->if_port = 11;
 252                         new_csr6 = 0x020E0000;
 253                         if (mleaf->type == 3) { /* 21142 */
 254                                 u16 *init_sequence = (u16*)(p+2);
 255                                 u16 *reset_sequence = &((u16*)(p+3))[init_length];
 256                                 int reset_length = p[2 + init_length*2];
 257                                 misc_info = reset_sequence + reset_length;
 258                                 if (startup) {
 259                                         int timeout = 10;       /* max 1 ms */
 260                                         for (i = 0; i < reset_length; i++)
 261                                                 iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
 262
 263                                         /* flush posted writes */
 264                                         ioread32(ioaddr + CSR15);
 265
 266                                         /* Sect 3.10.3 in DP83840A.pdf (p39) */
 267                                         udelay(500);
 268
 269                                         /* Section 4.2 in DP83840A.pdf (p43) */
 270                                         /* and IEEE 802.3 "22.2.4.1.1 Reset" */
 271                                         while (timeout-- &&
 272                                                 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
 273                                                 udelay(100);
 274                                 }
 275                                 for (i = 0; i < init_length; i++)
 276                                         iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
 277
 278                                 ioread32(ioaddr + CSR15);       /* flush posted writes */
 279                         } else {
 280                                 u8 *init_sequence = p + 2;
 281                                 u8 *reset_sequence = p + 3 + init_length;
 282                                 int reset_length = p[2 + init_length];
 283                                 misc_info = (u16*)(reset_sequence + reset_length);
 284                                 if (startup) {
 285                                         int timeout = 10;       /* max 1 ms */
 286                                         iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
 287                                         for (i = 0; i < reset_length; i++)
 288                                                 iowrite32(reset_sequence[i], ioaddr + CSR12);
 289
 290                                         /* flush posted writes */
 291                                         ioread32(ioaddr + CSR12);
 292
 293                                         /* Sect 3.10.3 in DP83840A.pdf (p39) */
 294                                         udelay(500);
 295
 296                                         /* Section 4.2 in DP83840A.pdf (p43) */
 297                                         /* and IEEE 802.3 "22.2.4.1.1 Reset" */
 298                                         while (timeout-- &&
 299                                                 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
 300                                                 udelay(100);
 301                                 }
 302                                 for (i = 0; i < init_length; i++)
 303                                         iowrite32(init_sequence[i], ioaddr + CSR12);
 304
 305                                 ioread32(ioaddr + CSR12);       /* flush posted writes */
 306                         }
 307
 308                         tmp_info = get_u16(&misc_info[1]);
 309                         if (tmp_info)
 310                                 tp->advertising[phy_num] = tmp_info | 1;
 311                         if (tmp_info && startup < 2) {
 312                                 if (tp->mii_advertise == 0)
 313                                         tp->mii_advertise = tp->advertising[phy_num];
 314                                 if (tulip_debug > 1)
 315                                         netdev_dbg(dev, " Advertising %04x on MII %d\n",
 316                                                    tp->mii_advertise,
 317                                                    tp->phys[phy_num]);
 318                                 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
 319                         }
 320                         break;
 321                 }
 322                 case 5: case 6: {
 323                         u16 setup[5];
 324
 325                         new_csr6 = 0; /* FIXME */
 326
 327                         for (i = 0; i < 5; i++)
 328                                 setup[i] = get_u16(&p[i*2 + 1]);
 329
 330                         if (startup && mtable->has_reset) {
 331                                 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
 332                                 unsigned char *rst = rleaf->leafdata;
 333                                 if (tulip_debug > 1)
 334                                         netdev_dbg(dev, "Resetting the transceiver\n");
 335                                 for (i = 0; i < rst[0]; i++)
 336                                         iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
 337                         }
 338
 339                         break;
 340                 }
 341                 default:
 342                         netdev_dbg(dev, " Invalid media table selection %d\n",
 343                                    mleaf->type);
 344                         new_csr6 = 0x020E0000;
 345                 }
 346                 if (tulip_debug > 1)
 347                         netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
 348                                    medianame[dev->if_port],
 349                                    ioread32(ioaddr + CSR12) & 0xff);
 350         } else if (tp->chip_id == LC82C168) {
 351                 if (startup && ! tp->medialock)
 352                         dev->if_port = tp->mii_cnt ? 11 : 0;
 353                 if (tulip_debug > 1)
 354                         netdev_dbg(dev, "PNIC PHY status is %3.3x, media %s\n",
 355                                    ioread32(ioaddr + 0xB8),
 356                                    medianame[dev->if_port]);
 357                 if (tp->mii_cnt) {
 358                         new_csr6 = 0x810C0000;
 359                         iowrite32(0x0001, ioaddr + CSR15);
 360                         iowrite32(0x0201B07A, ioaddr + 0xB8);
 361                 } else if (startup) {
 362                         /* Start with 10mbps to do autonegotiation. */
 363                         iowrite32(0x32, ioaddr + CSR12);
 364                         new_csr6 = 0x00420000;
 365                         iowrite32(0x0001B078, ioaddr + 0xB8);
 366                         iowrite32(0x0201B078, ioaddr + 0xB8);
 367                 } else if (dev->if_port == 3  ||  dev->if_port == 5) {
 368                         iowrite32(0x33, ioaddr + CSR12);
 369                         new_csr6 = 0x01860000;
 370                         /* Trigger autonegotiation. */
 371                         iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
 372                 } else {
 373                         iowrite32(0x32, ioaddr + CSR12);
 374                         new_csr6 = 0x00420000;
 375                         iowrite32(0x1F078, ioaddr + 0xB8);
 376                 }
 377         } else {                                        /* Unknown chip type with no media table. */
 378                 if (tp->default_port == 0)
 379                         dev->if_port = tp->mii_cnt ? 11 : 3;
 380                 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
 381                         new_csr6 = 0x020E0000;
 382                 } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
 383                         new_csr6 = 0x02860000;
 384                 } else
 385                         new_csr6 = 0x03860000;
 386                 if (tulip_debug > 1)
 387                         netdev_dbg(dev, "No media description table, assuming %s transceiver, CSR12 %02x\n",
 388                                    medianame[dev->if_port],
 389                                    ioread32(ioaddr + CSR12));
 390         }
 391
 392         tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
 393
 394         mdelay(1);
 395 }
 396
 397 /*
 398   Check the MII negotiated duplex and change the CSR6 setting if
 399   required.
 400   Return 0 if everything is OK.
 401   Return < 0 if the transceiver is missing or has no link beat.
 402   */
 403 int tulip_check_duplex(struct net_device *dev)
 404 {
 405         struct tulip_private *tp = netdev_priv(dev);
 406         unsigned int bmsr, lpa, negotiated, new_csr6;
 407
 408         bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
 409         lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
 410         if (tulip_debug > 1)
 411                 dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n",
 412                          bmsr, lpa);
 413         if (bmsr == 0xffff)
 414                 return -2;
 415         if ((bmsr & BMSR_LSTATUS) == 0) {
 416                 int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
 417                 if ((new_bmsr & BMSR_LSTATUS) == 0) {
 418                         if (tulip_debug  > 1)
 419                                 dev_info(&dev->dev,
 420                                          "No link beat on the MII interface, status %04x\n",
 421                                          new_bmsr);
 422                         return -1;
 423                 }
 424         }
 425         negotiated = lpa & tp->advertising[0];
 426         tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
 427
 428         new_csr6 = tp->csr6;
 429
 430         if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
 431         else                      new_csr6 |= TxThreshold;
 432         if (tp->full_duplex) new_csr6 |= FullDuplex;
 433         else                 new_csr6 &= ~FullDuplex;
 434
 435         if (new_csr6 != tp->csr6) {
 436                 tp->csr6 = new_csr6;
 437                 tulip_restart_rxtx(tp);
 438
 439                 if (tulip_debug > 0)
 440                         dev_info(&dev->dev,
 441                                  "Setting %s-duplex based on MII#%d link partner capability of %04x\n",
 442                                  tp->full_duplex ? "full" : "half",
 443                                  tp->phys[0], lpa);
 444                 return 1;
 445         }
 446
 447         return 0;
 448 }
 449
 450 void __devinit tulip_find_mii (struct net_device *dev, int board_idx)
 451 {
 452         struct tulip_private *tp = netdev_priv(dev);
 453         int phyn, phy_idx = 0;
 454         int mii_reg0;
 455         int mii_advert;
 456         unsigned int to_advert, new_bmcr, ane_switch;
 457
 458         /* Find the connected MII xcvrs.
 459            Doing this in open() would allow detecting external xcvrs later,
 460            but takes much time. */
 461         for (phyn = 1; phyn <= 32 && phy_idx < sizeof (tp->phys); phyn++) {
 462                 int phy = phyn & 0x1f;
 463                 int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
 464                 if ((mii_status & 0x8301) == 0x8001 ||
 465                     ((mii_status & BMSR_100BASE4) == 0 &&
 466                      (mii_status & 0x7800) != 0)) {
 467                         /* preserve Becker logic, gain indentation level */
 468                 } else {
 469                         continue;
 470                 }
 471
 472                 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
 473                 mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
 474                 ane_switch = 0;
 475
 476                 /* if not advertising at all, gen an
 477                  * advertising value from the capability
 478                  * bits in BMSR
 479                  */
 480                 if ((mii_advert & ADVERTISE_ALL) == 0) {
 481                         unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
 482                         mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
 483                 }
 484
 485                 if (tp->mii_advertise) {
 486                         tp->advertising[phy_idx] =
 487                         to_advert = tp->mii_advertise;
 488                 } else if (tp->advertising[phy_idx]) {
 489                         to_advert = tp->advertising[phy_idx];
 490                 } else {
 491                         tp->advertising[phy_idx] =
 492                         tp->mii_advertise =
 493                         to_advert = mii_advert;
 494                 }
 495
 496                 tp->phys[phy_idx++] = phy;
 497
 498                 pr_info("tulip%d:  MII transceiver #%d config %04x status %04x advertising %04x\n",
 499                         board_idx, phy, mii_reg0, mii_status, mii_advert);
 500
 501                 /* Fixup for DLink with miswired PHY. */
 502                 if (mii_advert != to_advert) {
 503                         pr_debug("tulip%d:  Advertising %04x on PHY %d, previously advertising %04x\n",
 504                                  board_idx, to_advert, phy, mii_advert);
 505                         tulip_mdio_write (dev, phy, 4, to_advert);
 506                 }
 507
 508                 /* Enable autonegotiation: some boards default to off. */
 509                 if (tp->default_port == 0) {
 510                         new_bmcr = mii_reg0 | BMCR_ANENABLE;
 511                         if (new_bmcr != mii_reg0) {
 512                                 new_bmcr |= BMCR_ANRESTART;
 513                                 ane_switch = 1;
 514                         }
 515                 }
 516                 /* ...or disable nway, if forcing media */
 517                 else {
 518                         new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
 519                         if (new_bmcr != mii_reg0)
 520                                 ane_switch = 1;
 521                 }
 522
 523                 /* clear out bits we never want at this point */
 524                 new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
 525                               BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
 526                               BMCR_RESET);
 527
 528                 if (tp->full_duplex)
 529                         new_bmcr |= BMCR_FULLDPLX;
 530                 if (tulip_media_cap[tp->default_port] & MediaIs100)
 531                         new_bmcr |= BMCR_SPEED100;
 532
 533                 if (new_bmcr != mii_reg0) {
 534                         /* some phys need the ANE switch to
 535                          * happen before forced media settings
 536                          * will "take."  However, we write the
 537                          * same value twice in order not to
 538                          * confuse the sane phys.
 539                          */
 540                         if (ane_switch) {
 541                                 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
 542                                 udelay (10);
 543                         }
 544                         tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
 545                 }
 546         }
 547         tp->mii_cnt = phy_idx;
 548         if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
 549                 pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",
 550                         board_idx);
 551                 tp->phys[0] = 1;
 552         }
 553 }