1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
41 /****************************************************************************
42 * Shared HW configuration *
43 ****************************************************************************/
44 #define PIN_CFG_NA 0x00000000
45 #define PIN_CFG_GPIO0_P0 0x00000001
46 #define PIN_CFG_GPIO1_P0 0x00000002
47 #define PIN_CFG_GPIO2_P0 0x00000003
48 #define PIN_CFG_GPIO3_P0 0x00000004
49 #define PIN_CFG_GPIO0_P1 0x00000005
50 #define PIN_CFG_GPIO1_P1 0x00000006
51 #define PIN_CFG_GPIO2_P1 0x00000007
52 #define PIN_CFG_GPIO3_P1 0x00000008
53 #define PIN_CFG_EPIO0 0x00000009
54 #define PIN_CFG_EPIO1 0x0000000a
55 #define PIN_CFG_EPIO2 0x0000000b
56 #define PIN_CFG_EPIO3 0x0000000c
57 #define PIN_CFG_EPIO4 0x0000000d
58 #define PIN_CFG_EPIO5 0x0000000e
59 #define PIN_CFG_EPIO6 0x0000000f
60 #define PIN_CFG_EPIO7 0x00000010
61 #define PIN_CFG_EPIO8 0x00000011
62 #define PIN_CFG_EPIO9 0x00000012
63 #define PIN_CFG_EPIO10 0x00000013
64 #define PIN_CFG_EPIO11 0x00000014
65 #define PIN_CFG_EPIO12 0x00000015
66 #define PIN_CFG_EPIO13 0x00000016
67 #define PIN_CFG_EPIO14 0x00000017
68 #define PIN_CFG_EPIO15 0x00000018
69 #define PIN_CFG_EPIO16 0x00000019
70 #define PIN_CFG_EPIO17 0x0000001a
71 #define PIN_CFG_EPIO18 0x0000001b
72 #define PIN_CFG_EPIO19 0x0000001c
73 #define PIN_CFG_EPIO20 0x0000001d
74 #define PIN_CFG_EPIO21 0x0000001e
75 #define PIN_CFG_EPIO22 0x0000001f
76 #define PIN_CFG_EPIO23 0x00000020
77 #define PIN_CFG_EPIO24 0x00000021
78 #define PIN_CFG_EPIO25 0x00000022
79 #define PIN_CFG_EPIO26 0x00000023
80 #define PIN_CFG_EPIO27 0x00000024
81 #define PIN_CFG_EPIO28 0x00000025
82 #define PIN_CFG_EPIO29 0x00000026
83 #define PIN_CFG_EPIO30 0x00000027
84 #define PIN_CFG_EPIO31 0x00000028
87 #define EPIO_CFG_NA 0x00000000
88 #define EPIO_CFG_EPIO0 0x00000001
89 #define EPIO_CFG_EPIO1 0x00000002
90 #define EPIO_CFG_EPIO2 0x00000003
91 #define EPIO_CFG_EPIO3 0x00000004
92 #define EPIO_CFG_EPIO4 0x00000005
93 #define EPIO_CFG_EPIO5 0x00000006
94 #define EPIO_CFG_EPIO6 0x00000007
95 #define EPIO_CFG_EPIO7 0x00000008
96 #define EPIO_CFG_EPIO8 0x00000009
97 #define EPIO_CFG_EPIO9 0x0000000a
98 #define EPIO_CFG_EPIO10 0x0000000b
99 #define EPIO_CFG_EPIO11 0x0000000c
100 #define EPIO_CFG_EPIO12 0x0000000d
101 #define EPIO_CFG_EPIO13 0x0000000e
102 #define EPIO_CFG_EPIO14 0x0000000f
103 #define EPIO_CFG_EPIO15 0x00000010
104 #define EPIO_CFG_EPIO16 0x00000011
105 #define EPIO_CFG_EPIO17 0x00000012
106 #define EPIO_CFG_EPIO18 0x00000013
107 #define EPIO_CFG_EPIO19 0x00000014
108 #define EPIO_CFG_EPIO20 0x00000015
109 #define EPIO_CFG_EPIO21 0x00000016
110 #define EPIO_CFG_EPIO22 0x00000017
111 #define EPIO_CFG_EPIO23 0x00000018
112 #define EPIO_CFG_EPIO24 0x00000019
113 #define EPIO_CFG_EPIO25 0x0000001a
114 #define EPIO_CFG_EPIO26 0x0000001b
115 #define EPIO_CFG_EPIO27 0x0000001c
116 #define EPIO_CFG_EPIO28 0x0000001d
117 #define EPIO_CFG_EPIO29 0x0000001e
118 #define EPIO_CFG_EPIO30 0x0000001f
119 #define EPIO_CFG_EPIO31 0x00000020
122 struct shared_hw_cfg { /* NVRAM Offset */
123 /* Up to 16 bytes of NULL-terminated string */
124 u8 part_num[16]; /* 0x104 */
126 u32 config; /* 0x114 */
127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
142 /* Whatever MFW found in NVM
143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
160 #define SHARED_HW_CFG_LED_MAC1 0x00000000
161 #define SHARED_HW_CFG_LED_PHY1 0x00010000
162 #define SHARED_HW_CFG_LED_PHY2 0x00020000
163 #define SHARED_HW_CFG_LED_PHY3 0x00030000
164 #define SHARED_HW_CFG_LED_MAC2 0x00040000
165 #define SHARED_HW_CFG_LED_PHY4 0x00050000
166 #define SHARED_HW_CFG_LED_PHY5 0x00060000
167 #define SHARED_HW_CFG_LED_PHY6 0x00070000
168 #define SHARED_HW_CFG_LED_MAC3 0x00080000
169 #define SHARED_HW_CFG_LED_PHY7 0x00090000
170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
190 #define SHARED_HW_CFG_ATC_MASK 0x80000000
191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
194 u32 config2; /* 0x118 */
195 /* one time auto detect grace period (in sec) */
196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
202 /* The default value for the core clock is 250MHz and it is
203 achieved by setting the clock change to 4 */
204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
217 /* Output low when PERST is asserted */
218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
229 /* The fan failure mechanism is usually related to the PHY type
230 since the power consumption of the board is determined by the PHY.
231 Currently, fan is required for most designs with SFX7101, BCM8727
232 and BCM8481. If a fan is not required for a board which uses one
233 of those PHYs, this field should be set to "Disabled". If a fan is
234 required for a different PHY type, this option should be set to
235 "Enabled". The fan failure indication is expected on SPIO5 */
236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
242 /* ASPM Power Management support */
243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
251 tl_control_0 (register 0x2800) */
252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
264 /* Set the MDC/MDIO access for the first external phy */
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
273 /* Set the MDC/MDIO access for the second external phy */
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
283 u32 power_dissipated; /* 0x11c */
284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
294 u32 ump_nc_si_config; /* 0x120 */
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
310 u32 board; /* 0x124 */
311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
315 /* Use the PIN_CFG_XXX defines on top */
316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
325 u32 wc_lane_config; /* 0x128 */
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
337 /* TX lane Polarity swap */
338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
342 /* TX lane Polarity swap */
343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
348 /* Selects the port layout of the board */
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
360 /****************************************************************************
361 * Port HW configuration *
362 ****************************************************************************/
363 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
373 u32 power_dissipated;
374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
412 /* Default values: 2P-64, 4P-32 */
413 u32 pf_config; /* 0x158 */
414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
417 /* Default values: 17 */
418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
424 u32 vf_config; /* 0x15C */
425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
431 u32 mf_pci_id; /* 0x160 */
432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
435 /* Controls the TX laser of the SFP+ module */
436 u32 sfp_ctrl; /* 0x164 */
437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
438 #define PORT_HW_CFG_TX_LASER_SHIFT 0
439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
445 /* Controls the fault module LED of the SFP+ */
446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
454 /* The output pin TX_DIS that controls the TX laser of the SFP+
455 module. Use the PIN_CFG_XXX defines on top */
456 u32 e3_sfp_ctrl; /* 0x168 */
457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
464 /* The input pin MOD_ABS that indicates whether SFP+ module is
465 present or not. Use the PIN_CFG_XXX defines on top */
466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
470 module. Use the PIN_CFG_XXX defines on top */
471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
475 * The input pin which signals module transmit fault. Use the
476 * PIN_CFG_XXX defines on top
478 u32 e3_cmn_pin_cfg; /* 0x16C */
479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
494 /* The output pin values BSC_SEL which selects the I2C for this port
496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
501 * The input pin I_FAULT which indicate over-current has occurred.
502 * Use the PIN_CFG_XXX defines on top
504 u32 e3_cmn_pin_cfg1; /* 0x170 */
505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
507 u32 reserved0[7]; /* 0x174 */
509 u32 aeu_int_mask; /* 0x190 */
511 u32 media_type; /* 0x194 */
512 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
515 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
518 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
521 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
522 (not direct mode), those values will not take effect on the 4 XGXS
523 lanes. For some external PHYs (such as 8706 and 8726) the values
524 will be used to configure the external PHY in those cases, not
525 all 4 values are needed. */
526 u16 xgxs_config_rx[4]; /* 0x198 */
527 u16 xgxs_config_tx[4]; /* 0x1A0 */
529 /* For storing FCOE mac on shared memory */
530 u32 fcoe_fip_mac_upper;
531 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
532 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
533 u32 fcoe_fip_mac_lower;
535 u32 fcoe_wwn_port_name_upper;
536 u32 fcoe_wwn_port_name_lower;
538 u32 fcoe_wwn_node_name_upper;
539 u32 fcoe_wwn_node_name_lower;
541 u32 Reserved1[49]; /* 0x1C0 */
543 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
545 u32 xgbt_phy_cfg; /* 0x284 */
546 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
549 u32 default_cfg; /* 0x288 */
550 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
551 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
552 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
553 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
554 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
555 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
557 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
558 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
559 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
560 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
561 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
562 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
564 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
565 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
566 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
567 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
568 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
569 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
571 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
572 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
573 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
574 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
575 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
576 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
578 /* When KR link is required to be set to force which is not
579 KR-compliant, this parameter determine what is the trigger for it.
580 When GPIO is selected, low input will force the speed. Currently
581 default speed is 1G. In the future, it may be widen to select the
582 forced speed in with another parameter. Note when force-1G is
583 enabled, it override option 56: Link Speed option. */
584 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
596 /* Enable to determine with which GPIO to reset the external phy */
597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
609 /* Enable BAM on KR */
610 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
615 /* Enable Common Mode Sense */
616 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
617 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
618 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
619 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
621 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY, 84833 only */
622 #define PORT_HW_CFG_RJ45_PR_SWP_MASK 0x00400000
623 #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT 22
624 #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED 0x00000000
625 #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED 0x00400000
627 /* Determine the Serdes electrical interface */
628 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
629 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
630 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
631 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
632 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
633 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
634 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
635 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
638 u32 speed_capability_mask2; /* 0x28C */
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
662 /* In the case where two media types (e.g. copper and fiber) are
663 present and electrically active at the same time, PHY Selection
664 will determine which of the two PHYs will be designated as the
665 Active PHY and used for a connection to the network. */
666 u32 multi_phy_config; /* 0x290 */
667 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
668 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
669 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
672 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
673 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
675 /* When enabled, all second phy nvram parameters will be swapped
676 with the first phy parameters */
677 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
678 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
679 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
680 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
683 /* Address of the second external phy */
684 u32 external_phy_config2; /* 0x294 */
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
688 /* The second XGXS external PHY type */
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
712 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
713 8706, 8726 and 8727) not all 4 values are needed. */
714 u16 xgxs_config2_rx[4]; /* 0x296 */
715 u16 xgxs_config2_tx[4]; /* 0x2A0 */
718 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
719 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
721 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
723 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
725 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
727 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
729 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
731 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
733 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
735 /* Indicate whether to swap the external phy polarity */
736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
738 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
741 u32 external_phy_config;
742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
743 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
778 u32 speed_capability_mask;
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
803 /* A place to hold the original MAC address as a backup */
804 u32 backup_mac_upper; /* 0x2B4 */
805 u32 backup_mac_lower; /* 0x2B8 */
810 /****************************************************************************
811 * Shared Feature configuration *
812 ****************************************************************************/
813 struct shared_feat_cfg { /* NVRAM Offset */
815 u32 config; /* 0x450 */
816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
818 /* Use NVRAM values instead of HW default values */
819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
833 /* Override the OTP back to single function mode. When using GPIO,
834 high means only SF, 0 is according to CLP configuration */
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
842 /* The interval in seconds between sending LLDP packets. Set to zero
843 to disable the feature */
844 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
847 /* The assigned device type ID for LLDP usage */
848 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
854 /****************************************************************************
855 * Port Feature configuration *
856 ****************************************************************************/
857 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
860 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
861 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
862 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
863 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
864 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
865 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
866 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
867 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
868 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
869 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
870 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
871 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
872 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
873 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
874 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
875 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
876 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
877 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
878 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
879 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
880 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
881 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
882 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
883 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
884 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
885 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
886 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
887 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
888 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
889 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
890 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
891 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
892 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
893 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
894 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
895 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
897 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
898 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
899 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
901 #define PORT_FEAT_CFG_AUTOGREEN_MASK 0x00000200
902 #define PORT_FEAT_CFG_AUTOGREEN_SHIFT 9
903 #define PORT_FEAT_CFG_AUTOGREEN_DISABLED 0x00000000
904 #define PORT_FEAT_CFG_AUTOGREEN_ENABLED 0x00000200
906 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
907 #define PORT_FEATURE_EN_SIZE_SHIFT 24
908 #define PORT_FEATURE_WOL_ENABLED 0x01000000
909 #define PORT_FEATURE_MBA_ENABLED 0x02000000
910 #define PORT_FEATURE_MFW_ENABLED 0x04000000
912 /* Advertise expansion ROM even if MBA is disabled */
913 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
914 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
915 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
917 /* Check the optic vendor via i2c against a list of approved modules
918 in a separate nvram image */
919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
920 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
923 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
925 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
926 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
929 /* Default is used when driver sets to "auto" mode */
930 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
931 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
932 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
933 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
934 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
935 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
936 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
937 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
938 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
945 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
946 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
947 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
948 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
950 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
951 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
953 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
954 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
955 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
956 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
957 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
958 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
977 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
978 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
981 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
982 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
983 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
984 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
986 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
987 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
988 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
989 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
990 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
991 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
992 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
993 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
994 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
995 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
997 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
998 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
999 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1002 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1003 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1004 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1007 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1008 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1009 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1010 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1011 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1014 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1015 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1037 u32 link_config; /* Used as HW defaults for the driver */
1038 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1039 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1040 /* (forced) low speed switch (< 10G) */
1041 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1042 /* (forced) high speed switch (>= 10G) */
1043 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1044 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1045 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1047 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1048 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1049 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1050 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1051 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1052 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1053 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1054 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1055 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1056 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1057 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1059 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1060 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1061 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1062 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1063 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1064 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1065 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1067 /* The default for MCP link configuration,
1068 uses the same defines as link_config */
1069 u32 mfw_wol_link_cfg;
1071 /* The default for the driver of the second external phy,
1072 uses the same defines as link_config */
1073 u32 link_config2; /* 0x47C */
1075 /* The default for MCP of the second external phy,
1076 uses the same defines as link_config */
1077 u32 mfw_wol_link_cfg2; /* 0x480 */
1079 u32 Reserved2[17]; /* 0x484 */
1084 /****************************************************************************
1085 * Device Information *
1086 ****************************************************************************/
1087 struct shm_dev_info { /* size */
1089 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1091 struct shared_hw_cfg shared_hw_config; /* 40 */
1093 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1095 struct shared_feat_cfg shared_feature_config; /* 4 */
1097 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1102 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1103 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1114 #define E1_FUNC_MAX 2
1115 #define E1H_FUNC_MAX 8
1116 #define E2_FUNC_MAX 4 /* per path */
1125 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1126 /* This value (in milliseconds) determines the frequency of the driver
1127 * issuing the PULSE message code. The firmware monitors this periodic
1128 * pulse to determine when to switch to an OS-absent mode. */
1129 #define DRV_PULSE_PERIOD_MS 250
1131 /* This value (in milliseconds) determines how long the driver should
1132 * wait for an acknowledgement from the firmware before timing out. Once
1133 * the firmware has timed out, the driver will assume there is no firmware
1134 * running and there won't be any firmware-driver synchronization during a
1136 #define FW_ACK_TIME_OUT_MS 5000
1138 #define FW_ACK_POLL_TIME_MS 1
1140 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1142 /* LED Blink rate that will achieve ~15.9Hz */
1143 #define LED_BLINK_RATE_VAL 480
1145 /****************************************************************************
1146 * Driver <-> FW Mailbox *
1147 ****************************************************************************/
1148 struct drv_port_mb {
1151 /* Driver should update this field on any link change event */
1153 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1154 #define LINK_STATUS_LINK_UP 0x00000001
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1161 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1162 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1163 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1164 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1165 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1166 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1167 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1168 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1169 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1170 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1171 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1173 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1174 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1176 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1177 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1178 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1180 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1181 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1182 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1183 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1184 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1185 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1186 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1188 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1189 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1191 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1192 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1194 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1195 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1196 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1197 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1198 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1200 #define LINK_STATUS_SERDES_LINK 0x00100000
1202 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1203 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1204 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1205 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1207 #define LINK_STATUS_PFC_ENABLED 0x20000000
1209 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1215 /* MCP firmware does not use this field */
1216 u32 ext_phy_fw_version;
1221 struct drv_func_mb {
1224 #define DRV_MSG_CODE_MASK 0xffff0000
1225 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1226 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1227 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1228 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1229 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1230 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1231 #define DRV_MSG_CODE_DCC_OK 0x30000000
1232 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1233 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1234 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1235 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1236 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1237 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1238 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1239 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1241 * The optic module verification command requires bootcode
1242 * v5.0.6 or later, te specific optic module verification command
1243 * requires bootcode v5.2.12 or later
1245 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1246 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1247 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1248 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1249 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1251 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1252 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1254 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1256 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1257 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1258 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1260 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1262 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1263 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1264 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1265 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1267 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1270 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1271 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1274 #define FW_MSG_CODE_MASK 0xffff0000
1275 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1276 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1277 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1278 /* Load common chip is supported from bc 6.0.0 */
1279 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1280 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1282 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1283 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1284 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1285 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1286 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1287 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1288 #define FW_MSG_CODE_DCC_DONE 0x30100000
1289 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1290 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1291 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1292 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1293 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1294 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1295 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1296 #define FW_MSG_CODE_NO_KEY 0x80f00000
1297 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1298 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1299 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1300 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1301 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1302 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1303 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1304 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1305 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1306 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1308 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1309 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1311 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1313 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1314 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1315 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1316 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1318 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1323 #define DRV_PULSE_SEQ_MASK 0x00007fff
1324 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1326 * The system time is in the format of
1327 * (year-2001)*12*32 + month*32 + day.
1329 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1331 * Indicate to the firmware not to go into the
1332 * OS-absent when it is not getting driver pulse.
1333 * This is used for debugging as well for PXE(MBA).
1337 #define MCP_PULSE_SEQ_MASK 0x00007fff
1338 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1339 /* Indicates to the driver not to assert due to lack
1340 * of MCP response */
1341 #define MCP_EVENT_MASK 0xffff0000
1342 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1344 u32 iscsi_boot_signature;
1345 u32 iscsi_boot_block_offset;
1348 #define DRV_STATUS_PMF 0x00000001
1349 #define DRV_STATUS_VF_DISABLED 0x00000002
1350 #define DRV_STATUS_SET_MF_BW 0x00000004
1351 #define DRV_STATUS_LINK_EVENT 0x00000008
1353 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1354 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1355 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1356 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1357 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1358 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1359 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1361 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1362 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1365 #define VIRT_MAC_SIGN_MASK 0xffff0000
1366 #define VIRT_MAC_SIGNATURE 0x564d0000
1372 /****************************************************************************
1373 * Management firmware state *
1374 ****************************************************************************/
1375 /* Allocate 440 bytes for management firmware */
1376 #define MGMTFW_STATE_WORD_SIZE 110
1378 struct mgmtfw_state {
1379 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1383 /****************************************************************************
1384 * Multi-Function configuration *
1385 ****************************************************************************/
1386 struct shared_mf_cfg {
1389 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1391 #define SHARED_MF_CLP_EXIT 0x00000001
1393 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1397 struct port_mf_cfg {
1399 u32 dynamic_cfg; /* device control channel */
1400 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1401 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1402 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1408 struct func_mf_cfg {
1412 /* function 0 of each port cannot be hidden */
1413 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1415 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1416 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1417 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1418 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1419 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1420 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1421 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1423 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1424 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1427 /* 0 - low priority, 3 - high priority */
1428 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1429 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1430 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1433 /* value range - 0..100, increments in 100Mbps */
1434 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1435 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1436 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1437 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1438 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1439 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1441 u32 mac_upper; /* MAC */
1442 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1443 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1444 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1446 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1448 u32 e1hov_tag; /* VNI */
1449 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1450 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1451 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1456 /* This structure is not applicable and should not be accessed on 57711 */
1457 struct func_ext_cfg {
1459 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1460 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1461 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1462 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1463 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1464 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1466 u32 iscsi_mac_addr_upper;
1467 u32 iscsi_mac_addr_lower;
1469 u32 fcoe_mac_addr_upper;
1470 u32 fcoe_mac_addr_lower;
1472 u32 fcoe_wwn_port_name_upper;
1473 u32 fcoe_wwn_port_name_lower;
1475 u32 fcoe_wwn_node_name_upper;
1476 u32 fcoe_wwn_node_name_lower;
1479 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1480 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1481 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1482 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1483 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1484 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1489 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1490 struct port_mf_cfg port_mf_config[PORT_MAX]; /* 0x10 * 2 = 0x20 */
1491 /* for all chips, there are 8 mf functions */
1492 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1494 * Extended configuration per function - this array does not exist and
1495 * should not be accessed on 57711
1497 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1500 /****************************************************************************
1501 * Shared Memory Region *
1502 ****************************************************************************/
1503 struct shmem_region { /* SharedMem Offset (size) */
1505 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1506 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1507 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1509 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1510 #define SHR_MEM_VALIDITY_MB 0x00200000
1511 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1512 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1513 /* One licensing bit should be set */
1514 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1515 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1516 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1517 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1519 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1520 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1521 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1522 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1523 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1524 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1526 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1528 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1530 /* FW information (for internal FW use) */
1531 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1532 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1534 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1537 /* This is a variable length array */
1538 /* the number of function depends on the chip type */
1539 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1541 /* the number of function depends on the chip type */
1542 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1545 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1547 /****************************************************************************
1548 * Shared Memory 2 Region *
1549 ****************************************************************************/
1550 /* The fw_flr_ack is actually built in the following way: */
1552 /* 64 bit: VF ack */
1553 /* 8 bit: ios_dis_ack */
1554 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1555 /* u32. The fw must have the VF right after the PF since this is how it */
1556 /* access arrays(it expects always the VF to reside after the PF, and that */
1557 /* makes the calculation much easier for it. ) */
1558 /* In order to answer both limitations, and keep the struct small, the code */
1559 /* will abuse the structure defined here to achieve the actual partition */
1561 /****************************************************************************/
1571 struct fw_flr_ack ack;
1574 /**** SUPPORT FOR SHMEM ARRRAYS ***
1575 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1576 * define arrays with storage types smaller then unsigned dwords.
1577 * The macros below add generic support for SHMEM arrays with numeric elements
1578 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1579 * array with individual bit-filed elements accessed using shifts and masks.
1583 /* eb is the bitwidth of a single element */
1584 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1585 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1587 /* the bit-position macro allows the used to flip the order of the arrays
1588 * elements on a per byte or word boundary.
1590 * example: an array with 8 entries each 4 bit wide. This array will fit into
1591 * a single dword. The diagrmas below show the array order of the nibbles.
1593 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1596 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1599 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1602 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1605 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1608 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1611 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1612 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1613 (((i)%((fb)/(eb))) * (eb)))
1615 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1616 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1617 SHMEM_ARRAY_MASK(eb))
1619 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1621 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1622 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1623 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1624 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1628 /****START OF DCBX STRUCTURES DECLARATIONS****/
1629 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1630 #define DCBX_PRI_PG_BITWIDTH 4
1631 #define DCBX_PRI_PG_FBITS 8
1632 #define DCBX_PRI_PG_GET(a, i) \
1633 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1634 #define DCBX_PRI_PG_SET(a, i, val) \
1635 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1636 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1637 #define DCBX_BW_PG_BITWIDTH 8
1638 #define DCBX_PG_BW_GET(a, i) \
1639 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1640 #define DCBX_PG_BW_SET(a, i, val) \
1641 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1642 #define DCBX_STRICT_PRI_PG 15
1643 #define DCBX_MAX_APP_PROTOCOL 16
1644 #define FCOE_APP_IDX 0
1645 #define ISCSI_APP_IDX 1
1646 #define PREDEFINED_APP_IDX_MAX 2
1649 /* Big/Little endian have the same representation. */
1650 struct dcbx_ets_feature {
1652 * For Admin MIB - is this feature supported by the
1653 * driver | For Local MIB - should this feature be enabled.
1660 /* Driver structure in LE */
1661 struct dcbx_pfc_feature {
1664 #define DCBX_PFC_PRI_0 0x01
1665 #define DCBX_PFC_PRI_1 0x02
1666 #define DCBX_PFC_PRI_2 0x04
1667 #define DCBX_PFC_PRI_3 0x08
1668 #define DCBX_PFC_PRI_4 0x10
1669 #define DCBX_PFC_PRI_5 0x20
1670 #define DCBX_PFC_PRI_6 0x40
1671 #define DCBX_PFC_PRI_7 0x80
1675 #elif defined(__LITTLE_ENDIAN)
1680 #define DCBX_PFC_PRI_0 0x01
1681 #define DCBX_PFC_PRI_1 0x02
1682 #define DCBX_PFC_PRI_2 0x04
1683 #define DCBX_PFC_PRI_3 0x08
1684 #define DCBX_PFC_PRI_4 0x10
1685 #define DCBX_PFC_PRI_5 0x20
1686 #define DCBX_PFC_PRI_6 0x40
1687 #define DCBX_PFC_PRI_7 0x80
1691 struct dcbx_app_priority_entry {
1696 #define DCBX_APP_ENTRY_VALID 0x01
1697 #define DCBX_APP_ENTRY_SF_MASK 0x30
1698 #define DCBX_APP_ENTRY_SF_SHIFT 4
1699 #define DCBX_APP_SF_ETH_TYPE 0x10
1700 #define DCBX_APP_SF_PORT 0x20
1701 #elif defined(__LITTLE_ENDIAN)
1703 #define DCBX_APP_ENTRY_VALID 0x01
1704 #define DCBX_APP_ENTRY_SF_MASK 0x30
1705 #define DCBX_APP_ENTRY_SF_SHIFT 4
1706 #define DCBX_APP_SF_ETH_TYPE 0x10
1707 #define DCBX_APP_SF_PORT 0x20
1714 /* FW structure in BE */
1715 struct dcbx_app_priority_feature {
1721 #elif defined(__LITTLE_ENDIAN)
1727 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1730 /* FW structure in BE */
1731 struct dcbx_features {
1733 struct dcbx_ets_feature ets;
1735 struct dcbx_pfc_feature pfc;
1737 struct dcbx_app_priority_feature app;
1740 /* LLDP protocol parameters */
1741 /* FW structure in BE */
1742 struct lldp_params {
1744 u8 msg_fast_tx_interval;
1748 #define LLDP_TX_ONLY 0x01
1749 #define LLDP_RX_ONLY 0x02
1750 #define LLDP_TX_RX 0x03
1751 #define LLDP_DISABLED 0x04
1756 #elif defined(__LITTLE_ENDIAN)
1758 #define LLDP_TX_ONLY 0x01
1759 #define LLDP_RX_ONLY 0x02
1760 #define LLDP_TX_RX 0x03
1761 #define LLDP_DISABLED 0x04
1764 u8 msg_fast_tx_interval;
1770 #define REM_CHASSIS_ID_STAT_LEN 4
1771 #define REM_PORT_ID_STAT_LEN 4
1772 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1773 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1774 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1775 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1778 struct lldp_dcbx_stat {
1779 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1780 #define LOCAL_PORT_ID_STAT_LEN 2
1781 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1782 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1783 /* Holds local Port ID 8B payload of constant subtype 3. */
1784 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1785 /* Number of DCBX frames transmitted. */
1786 u32 num_tx_dcbx_pkts;
1787 /* Number of DCBX frames received. */
1788 u32 num_rx_dcbx_pkts;
1791 /* ADMIN MIB - DCBX local machine default configuration. */
1792 struct lldp_admin_mib {
1794 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1795 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1796 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1797 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1798 #define DCBX_ETS_RECO_VALID 0x00000010
1799 #define DCBX_ETS_WILLING 0x00000020
1800 #define DCBX_PFC_WILLING 0x00000040
1801 #define DCBX_APP_WILLING 0x00000080
1802 #define DCBX_VERSION_CEE 0x00000100
1803 #define DCBX_VERSION_IEEE 0x00000200
1804 #define DCBX_DCBX_ENABLED 0x00000400
1805 #define DCBX_CEE_VERSION_MASK 0x0000f000
1806 #define DCBX_CEE_VERSION_SHIFT 12
1807 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1808 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1809 struct dcbx_features features;
1812 /* REMOTE MIB - remote machine DCBX configuration. */
1813 struct lldp_remote_mib {
1816 #define DCBX_ETS_TLV_RX 0x00000001
1817 #define DCBX_PFC_TLV_RX 0x00000002
1818 #define DCBX_APP_TLV_RX 0x00000004
1819 #define DCBX_ETS_RX_ERROR 0x00000010
1820 #define DCBX_PFC_RX_ERROR 0x00000020
1821 #define DCBX_APP_RX_ERROR 0x00000040
1822 #define DCBX_ETS_REM_WILLING 0x00000100
1823 #define DCBX_PFC_REM_WILLING 0x00000200
1824 #define DCBX_APP_REM_WILLING 0x00000400
1825 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1826 #define DCBX_REMOTE_MIB_VALID 0x00002000
1827 struct dcbx_features features;
1831 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1832 struct lldp_local_mib {
1834 /* Indicates if there is mismatch with negotiation results. */
1836 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1837 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1838 #define DCBX_LOCAL_APP_ERROR 0x00000004
1839 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1840 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1841 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1842 struct dcbx_features features;
1845 /***END OF DCBX STRUCTURES DECLARATIONS***/
1847 struct ncsi_oem_fcoe_features {
1849 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1850 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1852 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1853 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1856 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1857 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1859 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1860 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1863 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1864 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1866 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1867 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1870 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1871 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1874 struct ncsi_oem_data {
1875 u32 driver_version[4];
1876 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1879 struct shmem2_region {
1881 u32 size; /* 0x0000 */
1883 u32 dcc_support; /* 0x0004 */
1884 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1885 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1886 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1887 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1888 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1889 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1891 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
1893 * For backwards compatibility, if the mf_cfg_addr does not exist
1894 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1895 * end of struct shmem_region
1897 u32 mf_cfg_addr; /* 0x0010 */
1898 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1900 struct fw_flr_mb flr_mb; /* 0x0014 */
1901 u32 dcbx_lldp_params_offset; /* 0x0028 */
1902 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1903 u32 dcbx_neg_res_offset; /* 0x002c */
1904 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1905 u32 dcbx_remote_mib_offset; /* 0x0030 */
1906 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1908 * The other shmemX_base_addr holds the other path's shmem address
1909 * required for example in case of common phy init, or for path1 to know
1910 * the address of mcp debug trace which is located in offset from shmem
1913 u32 other_shmem_base_addr; /* 0x0034 */
1914 u32 other_shmem2_base_addr; /* 0x0038 */
1916 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
1917 * which were disabled/flred
1919 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
1922 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
1925 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
1927 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
1928 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1931 * edebug_driver_if field is used to transfer messages between edebug
1932 * app to the driver through shmem2.
1935 * bits 0-2 - function number / instance of driver to perform request
1936 * bits 3-5 - op code / is_ack?
1939 u32 edebug_driver_if[2]; /* 0x0068 */
1940 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
1941 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
1942 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
1944 u32 nvm_retain_bitmap_addr; /* 0x0070 */
1946 u32 reserved1; /* 0x0074 */
1948 u32 reserved2[E2_FUNC_MAX];
1950 u32 reserved3[E2_FUNC_MAX];/* 0x0088 */
1951 u32 reserved4[E2_FUNC_MAX];/* 0x0098 */
1953 u32 swim_base_addr; /* 0x0108 */
1959 /* generic flags controlled by the driver */
1961 #define DRV_FLAGS_DCB_CONFIGURED 0x1
1963 /* pointer to extended dev_info shared data copied from nvm image */
1964 u32 extended_dev_info_shared_addr;
1965 u32 ncsi_oem_data_addr;
1969 u32 ocsd_req_update_interval;
1974 u32 rx_stat_ifhcinoctets;
1975 u32 rx_stat_ifhcinbadoctets;
1976 u32 rx_stat_etherstatsfragments;
1977 u32 rx_stat_ifhcinucastpkts;
1978 u32 rx_stat_ifhcinmulticastpkts;
1979 u32 rx_stat_ifhcinbroadcastpkts;
1980 u32 rx_stat_dot3statsfcserrors;
1981 u32 rx_stat_dot3statsalignmenterrors;
1982 u32 rx_stat_dot3statscarriersenseerrors;
1983 u32 rx_stat_xonpauseframesreceived;
1984 u32 rx_stat_xoffpauseframesreceived;
1985 u32 rx_stat_maccontrolframesreceived;
1986 u32 rx_stat_xoffstateentered;
1987 u32 rx_stat_dot3statsframestoolong;
1988 u32 rx_stat_etherstatsjabbers;
1989 u32 rx_stat_etherstatsundersizepkts;
1990 u32 rx_stat_etherstatspkts64octets;
1991 u32 rx_stat_etherstatspkts65octetsto127octets;
1992 u32 rx_stat_etherstatspkts128octetsto255octets;
1993 u32 rx_stat_etherstatspkts256octetsto511octets;
1994 u32 rx_stat_etherstatspkts512octetsto1023octets;
1995 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1996 u32 rx_stat_etherstatspktsover1522octets;
1998 u32 rx_stat_falsecarriererrors;
2000 u32 tx_stat_ifhcoutoctets;
2001 u32 tx_stat_ifhcoutbadoctets;
2002 u32 tx_stat_etherstatscollisions;
2003 u32 tx_stat_outxonsent;
2004 u32 tx_stat_outxoffsent;
2005 u32 tx_stat_flowcontroldone;
2006 u32 tx_stat_dot3statssinglecollisionframes;
2007 u32 tx_stat_dot3statsmultiplecollisionframes;
2008 u32 tx_stat_dot3statsdeferredtransmissions;
2009 u32 tx_stat_dot3statsexcessivecollisions;
2010 u32 tx_stat_dot3statslatecollisions;
2011 u32 tx_stat_ifhcoutucastpkts;
2012 u32 tx_stat_ifhcoutmulticastpkts;
2013 u32 tx_stat_ifhcoutbroadcastpkts;
2014 u32 tx_stat_etherstatspkts64octets;
2015 u32 tx_stat_etherstatspkts65octetsto127octets;
2016 u32 tx_stat_etherstatspkts128octetsto255octets;
2017 u32 tx_stat_etherstatspkts256octetsto511octets;
2018 u32 tx_stat_etherstatspkts512octetsto1023octets;
2019 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2020 u32 tx_stat_etherstatspktsover1522octets;
2021 u32 tx_stat_dot3statsinternalmactransmiterrors;
2025 struct bmac1_stats {
2026 u32 tx_stat_gtpkt_lo;
2027 u32 tx_stat_gtpkt_hi;
2028 u32 tx_stat_gtxpf_lo;
2029 u32 tx_stat_gtxpf_hi;
2030 u32 tx_stat_gtfcs_lo;
2031 u32 tx_stat_gtfcs_hi;
2032 u32 tx_stat_gtmca_lo;
2033 u32 tx_stat_gtmca_hi;
2034 u32 tx_stat_gtbca_lo;
2035 u32 tx_stat_gtbca_hi;
2036 u32 tx_stat_gtfrg_lo;
2037 u32 tx_stat_gtfrg_hi;
2038 u32 tx_stat_gtovr_lo;
2039 u32 tx_stat_gtovr_hi;
2040 u32 tx_stat_gt64_lo;
2041 u32 tx_stat_gt64_hi;
2042 u32 tx_stat_gt127_lo;
2043 u32 tx_stat_gt127_hi;
2044 u32 tx_stat_gt255_lo;
2045 u32 tx_stat_gt255_hi;
2046 u32 tx_stat_gt511_lo;
2047 u32 tx_stat_gt511_hi;
2048 u32 tx_stat_gt1023_lo;
2049 u32 tx_stat_gt1023_hi;
2050 u32 tx_stat_gt1518_lo;
2051 u32 tx_stat_gt1518_hi;
2052 u32 tx_stat_gt2047_lo;
2053 u32 tx_stat_gt2047_hi;
2054 u32 tx_stat_gt4095_lo;
2055 u32 tx_stat_gt4095_hi;
2056 u32 tx_stat_gt9216_lo;
2057 u32 tx_stat_gt9216_hi;
2058 u32 tx_stat_gt16383_lo;
2059 u32 tx_stat_gt16383_hi;
2060 u32 tx_stat_gtmax_lo;
2061 u32 tx_stat_gtmax_hi;
2062 u32 tx_stat_gtufl_lo;
2063 u32 tx_stat_gtufl_hi;
2064 u32 tx_stat_gterr_lo;
2065 u32 tx_stat_gterr_hi;
2066 u32 tx_stat_gtbyt_lo;
2067 u32 tx_stat_gtbyt_hi;
2069 u32 rx_stat_gr64_lo;
2070 u32 rx_stat_gr64_hi;
2071 u32 rx_stat_gr127_lo;
2072 u32 rx_stat_gr127_hi;
2073 u32 rx_stat_gr255_lo;
2074 u32 rx_stat_gr255_hi;
2075 u32 rx_stat_gr511_lo;
2076 u32 rx_stat_gr511_hi;
2077 u32 rx_stat_gr1023_lo;
2078 u32 rx_stat_gr1023_hi;
2079 u32 rx_stat_gr1518_lo;
2080 u32 rx_stat_gr1518_hi;
2081 u32 rx_stat_gr2047_lo;
2082 u32 rx_stat_gr2047_hi;
2083 u32 rx_stat_gr4095_lo;
2084 u32 rx_stat_gr4095_hi;
2085 u32 rx_stat_gr9216_lo;
2086 u32 rx_stat_gr9216_hi;
2087 u32 rx_stat_gr16383_lo;
2088 u32 rx_stat_gr16383_hi;
2089 u32 rx_stat_grmax_lo;
2090 u32 rx_stat_grmax_hi;
2091 u32 rx_stat_grpkt_lo;
2092 u32 rx_stat_grpkt_hi;
2093 u32 rx_stat_grfcs_lo;
2094 u32 rx_stat_grfcs_hi;
2095 u32 rx_stat_grmca_lo;
2096 u32 rx_stat_grmca_hi;
2097 u32 rx_stat_grbca_lo;
2098 u32 rx_stat_grbca_hi;
2099 u32 rx_stat_grxcf_lo;
2100 u32 rx_stat_grxcf_hi;
2101 u32 rx_stat_grxpf_lo;
2102 u32 rx_stat_grxpf_hi;
2103 u32 rx_stat_grxuo_lo;
2104 u32 rx_stat_grxuo_hi;
2105 u32 rx_stat_grjbr_lo;
2106 u32 rx_stat_grjbr_hi;
2107 u32 rx_stat_grovr_lo;
2108 u32 rx_stat_grovr_hi;
2109 u32 rx_stat_grflr_lo;
2110 u32 rx_stat_grflr_hi;
2111 u32 rx_stat_grmeg_lo;
2112 u32 rx_stat_grmeg_hi;
2113 u32 rx_stat_grmeb_lo;
2114 u32 rx_stat_grmeb_hi;
2115 u32 rx_stat_grbyt_lo;
2116 u32 rx_stat_grbyt_hi;
2117 u32 rx_stat_grund_lo;
2118 u32 rx_stat_grund_hi;
2119 u32 rx_stat_grfrg_lo;
2120 u32 rx_stat_grfrg_hi;
2121 u32 rx_stat_grerb_lo;
2122 u32 rx_stat_grerb_hi;
2123 u32 rx_stat_grfre_lo;
2124 u32 rx_stat_grfre_hi;
2125 u32 rx_stat_gripj_lo;
2126 u32 rx_stat_gripj_hi;
2129 struct bmac2_stats {
2130 u32 tx_stat_gtpk_lo; /* gtpok */
2131 u32 tx_stat_gtpk_hi; /* gtpok */
2132 u32 tx_stat_gtxpf_lo; /* gtpf */
2133 u32 tx_stat_gtxpf_hi; /* gtpf */
2134 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2135 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2136 u32 tx_stat_gtfcs_lo;
2137 u32 tx_stat_gtfcs_hi;
2138 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2139 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2140 u32 tx_stat_gtmca_lo;
2141 u32 tx_stat_gtmca_hi;
2142 u32 tx_stat_gtbca_lo;
2143 u32 tx_stat_gtbca_hi;
2144 u32 tx_stat_gtovr_lo;
2145 u32 tx_stat_gtovr_hi;
2146 u32 tx_stat_gtfrg_lo;
2147 u32 tx_stat_gtfrg_hi;
2148 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2149 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2150 u32 tx_stat_gt64_lo;
2151 u32 tx_stat_gt64_hi;
2152 u32 tx_stat_gt127_lo;
2153 u32 tx_stat_gt127_hi;
2154 u32 tx_stat_gt255_lo;
2155 u32 tx_stat_gt255_hi;
2156 u32 tx_stat_gt511_lo;
2157 u32 tx_stat_gt511_hi;
2158 u32 tx_stat_gt1023_lo;
2159 u32 tx_stat_gt1023_hi;
2160 u32 tx_stat_gt1518_lo;
2161 u32 tx_stat_gt1518_hi;
2162 u32 tx_stat_gt2047_lo;
2163 u32 tx_stat_gt2047_hi;
2164 u32 tx_stat_gt4095_lo;
2165 u32 tx_stat_gt4095_hi;
2166 u32 tx_stat_gt9216_lo;
2167 u32 tx_stat_gt9216_hi;
2168 u32 tx_stat_gt16383_lo;
2169 u32 tx_stat_gt16383_hi;
2170 u32 tx_stat_gtmax_lo;
2171 u32 tx_stat_gtmax_hi;
2172 u32 tx_stat_gtufl_lo;
2173 u32 tx_stat_gtufl_hi;
2174 u32 tx_stat_gterr_lo;
2175 u32 tx_stat_gterr_hi;
2176 u32 tx_stat_gtbyt_lo;
2177 u32 tx_stat_gtbyt_hi;
2179 u32 rx_stat_gr64_lo;
2180 u32 rx_stat_gr64_hi;
2181 u32 rx_stat_gr127_lo;
2182 u32 rx_stat_gr127_hi;
2183 u32 rx_stat_gr255_lo;
2184 u32 rx_stat_gr255_hi;
2185 u32 rx_stat_gr511_lo;
2186 u32 rx_stat_gr511_hi;
2187 u32 rx_stat_gr1023_lo;
2188 u32 rx_stat_gr1023_hi;
2189 u32 rx_stat_gr1518_lo;
2190 u32 rx_stat_gr1518_hi;
2191 u32 rx_stat_gr2047_lo;
2192 u32 rx_stat_gr2047_hi;
2193 u32 rx_stat_gr4095_lo;
2194 u32 rx_stat_gr4095_hi;
2195 u32 rx_stat_gr9216_lo;
2196 u32 rx_stat_gr9216_hi;
2197 u32 rx_stat_gr16383_lo;
2198 u32 rx_stat_gr16383_hi;
2199 u32 rx_stat_grmax_lo;
2200 u32 rx_stat_grmax_hi;
2201 u32 rx_stat_grpkt_lo;
2202 u32 rx_stat_grpkt_hi;
2203 u32 rx_stat_grfcs_lo;
2204 u32 rx_stat_grfcs_hi;
2205 u32 rx_stat_gruca_lo;
2206 u32 rx_stat_gruca_hi;
2207 u32 rx_stat_grmca_lo;
2208 u32 rx_stat_grmca_hi;
2209 u32 rx_stat_grbca_lo;
2210 u32 rx_stat_grbca_hi;
2211 u32 rx_stat_grxpf_lo; /* grpf */
2212 u32 rx_stat_grxpf_hi; /* grpf */
2213 u32 rx_stat_grpp_lo;
2214 u32 rx_stat_grpp_hi;
2215 u32 rx_stat_grxuo_lo; /* gruo */
2216 u32 rx_stat_grxuo_hi; /* gruo */
2217 u32 rx_stat_grjbr_lo;
2218 u32 rx_stat_grjbr_hi;
2219 u32 rx_stat_grovr_lo;
2220 u32 rx_stat_grovr_hi;
2221 u32 rx_stat_grxcf_lo; /* grcf */
2222 u32 rx_stat_grxcf_hi; /* grcf */
2223 u32 rx_stat_grflr_lo;
2224 u32 rx_stat_grflr_hi;
2225 u32 rx_stat_grpok_lo;
2226 u32 rx_stat_grpok_hi;
2227 u32 rx_stat_grmeg_lo;
2228 u32 rx_stat_grmeg_hi;
2229 u32 rx_stat_grmeb_lo;
2230 u32 rx_stat_grmeb_hi;
2231 u32 rx_stat_grbyt_lo;
2232 u32 rx_stat_grbyt_hi;
2233 u32 rx_stat_grund_lo;
2234 u32 rx_stat_grund_hi;
2235 u32 rx_stat_grfrg_lo;
2236 u32 rx_stat_grfrg_hi;
2237 u32 rx_stat_grerb_lo; /* grerrbyt */
2238 u32 rx_stat_grerb_hi; /* grerrbyt */
2239 u32 rx_stat_grfre_lo; /* grfrerr */
2240 u32 rx_stat_grfre_hi; /* grfrerr */
2241 u32 rx_stat_gripj_lo;
2242 u32 rx_stat_gripj_hi;
2245 struct mstat_stats {
2247 /* OTE MSTAT on E3 has a bug where this register's contents are
2248 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2292 u32 tx_collisions_lo;
2293 u32 tx_collisions_hi;
2294 u32 tx_singlecollision_lo;
2295 u32 tx_singlecollision_hi;
2296 u32 tx_multiplecollisions_lo;
2297 u32 tx_multiplecollisions_hi;
2300 u32 tx_excessivecollisions_lo;
2301 u32 tx_excessivecollisions_hi;
2302 u32 tx_latecollisions_lo;
2303 u32 tx_latecollisions_hi;
2362 u32 rx_alignmenterrors_lo;
2363 u32 rx_alignmenterrors_hi;
2364 u32 rx_falsecarrier_lo;
2365 u32 rx_falsecarrier_hi;
2366 u32 rx_llfcmsgcnt_lo;
2367 u32 rx_llfcmsgcnt_hi;
2372 struct emac_stats emac_stats;
2373 struct bmac1_stats bmac1_stats;
2374 struct bmac2_stats bmac2_stats;
2375 struct mstat_stats mstat_stats;
2381 u32 rx_stat_ifhcinbadoctets_hi;
2382 u32 rx_stat_ifhcinbadoctets_lo;
2384 /* out_bad_octets */
2385 u32 tx_stat_ifhcoutbadoctets_hi;
2386 u32 tx_stat_ifhcoutbadoctets_lo;
2388 /* crc_receive_errors */
2389 u32 rx_stat_dot3statsfcserrors_hi;
2390 u32 rx_stat_dot3statsfcserrors_lo;
2391 /* alignment_errors */
2392 u32 rx_stat_dot3statsalignmenterrors_hi;
2393 u32 rx_stat_dot3statsalignmenterrors_lo;
2394 /* carrier_sense_errors */
2395 u32 rx_stat_dot3statscarriersenseerrors_hi;
2396 u32 rx_stat_dot3statscarriersenseerrors_lo;
2397 /* false_carrier_detections */
2398 u32 rx_stat_falsecarriererrors_hi;
2399 u32 rx_stat_falsecarriererrors_lo;
2401 /* runt_packets_received */
2402 u32 rx_stat_etherstatsundersizepkts_hi;
2403 u32 rx_stat_etherstatsundersizepkts_lo;
2404 /* jabber_packets_received */
2405 u32 rx_stat_dot3statsframestoolong_hi;
2406 u32 rx_stat_dot3statsframestoolong_lo;
2408 /* error_runt_packets_received */
2409 u32 rx_stat_etherstatsfragments_hi;
2410 u32 rx_stat_etherstatsfragments_lo;
2411 /* error_jabber_packets_received */
2412 u32 rx_stat_etherstatsjabbers_hi;
2413 u32 rx_stat_etherstatsjabbers_lo;
2415 /* control_frames_received */
2416 u32 rx_stat_maccontrolframesreceived_hi;
2417 u32 rx_stat_maccontrolframesreceived_lo;
2418 u32 rx_stat_mac_xpf_hi;
2419 u32 rx_stat_mac_xpf_lo;
2420 u32 rx_stat_mac_xcf_hi;
2421 u32 rx_stat_mac_xcf_lo;
2423 /* xoff_state_entered */
2424 u32 rx_stat_xoffstateentered_hi;
2425 u32 rx_stat_xoffstateentered_lo;
2426 /* pause_xon_frames_received */
2427 u32 rx_stat_xonpauseframesreceived_hi;
2428 u32 rx_stat_xonpauseframesreceived_lo;
2429 /* pause_xoff_frames_received */
2430 u32 rx_stat_xoffpauseframesreceived_hi;
2431 u32 rx_stat_xoffpauseframesreceived_lo;
2432 /* pause_xon_frames_transmitted */
2433 u32 tx_stat_outxonsent_hi;
2434 u32 tx_stat_outxonsent_lo;
2435 /* pause_xoff_frames_transmitted */
2436 u32 tx_stat_outxoffsent_hi;
2437 u32 tx_stat_outxoffsent_lo;
2438 /* flow_control_done */
2439 u32 tx_stat_flowcontroldone_hi;
2440 u32 tx_stat_flowcontroldone_lo;
2442 /* ether_stats_collisions */
2443 u32 tx_stat_etherstatscollisions_hi;
2444 u32 tx_stat_etherstatscollisions_lo;
2445 /* single_collision_transmit_frames */
2446 u32 tx_stat_dot3statssinglecollisionframes_hi;
2447 u32 tx_stat_dot3statssinglecollisionframes_lo;
2448 /* multiple_collision_transmit_frames */
2449 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2450 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2451 /* deferred_transmissions */
2452 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2453 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2454 /* excessive_collision_frames */
2455 u32 tx_stat_dot3statsexcessivecollisions_hi;
2456 u32 tx_stat_dot3statsexcessivecollisions_lo;
2457 /* late_collision_frames */
2458 u32 tx_stat_dot3statslatecollisions_hi;
2459 u32 tx_stat_dot3statslatecollisions_lo;
2461 /* frames_transmitted_64_bytes */
2462 u32 tx_stat_etherstatspkts64octets_hi;
2463 u32 tx_stat_etherstatspkts64octets_lo;
2464 /* frames_transmitted_65_127_bytes */
2465 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2466 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2467 /* frames_transmitted_128_255_bytes */
2468 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2469 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2470 /* frames_transmitted_256_511_bytes */
2471 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2472 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2473 /* frames_transmitted_512_1023_bytes */
2474 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2475 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2476 /* frames_transmitted_1024_1522_bytes */
2477 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2478 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2479 /* frames_transmitted_1523_9022_bytes */
2480 u32 tx_stat_etherstatspktsover1522octets_hi;
2481 u32 tx_stat_etherstatspktsover1522octets_lo;
2482 u32 tx_stat_mac_2047_hi;
2483 u32 tx_stat_mac_2047_lo;
2484 u32 tx_stat_mac_4095_hi;
2485 u32 tx_stat_mac_4095_lo;
2486 u32 tx_stat_mac_9216_hi;
2487 u32 tx_stat_mac_9216_lo;
2488 u32 tx_stat_mac_16383_hi;
2489 u32 tx_stat_mac_16383_lo;
2491 /* internal_mac_transmit_errors */
2492 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2493 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2495 /* if_out_discards */
2496 u32 tx_stat_mac_ufl_hi;
2497 u32 tx_stat_mac_ufl_lo;
2501 #define MAC_STX_IDX_MAX 2
2503 struct host_port_stats {
2504 u32 host_port_stats_start;
2506 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2511 u32 host_port_stats_end;
2515 struct host_func_stats {
2516 u32 host_func_stats_start;
2518 u32 total_bytes_received_hi;
2519 u32 total_bytes_received_lo;
2521 u32 total_bytes_transmitted_hi;
2522 u32 total_bytes_transmitted_lo;
2524 u32 total_unicast_packets_received_hi;
2525 u32 total_unicast_packets_received_lo;
2527 u32 total_multicast_packets_received_hi;
2528 u32 total_multicast_packets_received_lo;
2530 u32 total_broadcast_packets_received_hi;
2531 u32 total_broadcast_packets_received_lo;
2533 u32 total_unicast_packets_transmitted_hi;
2534 u32 total_unicast_packets_transmitted_lo;
2536 u32 total_multicast_packets_transmitted_hi;
2537 u32 total_multicast_packets_transmitted_lo;
2539 u32 total_broadcast_packets_transmitted_hi;
2540 u32 total_broadcast_packets_transmitted_lo;
2542 u32 valid_bytes_received_hi;
2543 u32 valid_bytes_received_lo;
2545 u32 host_func_stats_end;
2548 /* VIC definitions */
2549 #define VICSTATST_UIF_INDEX 2
2551 #define BCM_5710_FW_MAJOR_VERSION 7
2552 #define BCM_5710_FW_MINOR_VERSION 0
2553 #define BCM_5710_FW_REVISION_VERSION 29
2554 #define BCM_5710_FW_ENGINEERING_VERSION 0
2555 #define BCM_5710_FW_COMPILE_FLAGS 1
2561 struct atten_sp_status_block {
2563 __le32 attn_bits_ack;
2566 __le16 attn_bits_index;
2572 * The eth aggregative context of Cstorm
2574 struct cstorm_eth_ag_context {
2575 u32 __reserved0[10];
2580 * dmae command structure
2582 struct dmae_command {
2584 #define DMAE_COMMAND_SRC (0x1<<0)
2585 #define DMAE_COMMAND_SRC_SHIFT 0
2586 #define DMAE_COMMAND_DST (0x3<<1)
2587 #define DMAE_COMMAND_DST_SHIFT 1
2588 #define DMAE_COMMAND_C_DST (0x1<<3)
2589 #define DMAE_COMMAND_C_DST_SHIFT 3
2590 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2591 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2592 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2593 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2594 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2595 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2596 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2597 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2598 #define DMAE_COMMAND_PORT (0x1<<11)
2599 #define DMAE_COMMAND_PORT_SHIFT 11
2600 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2601 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2602 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2603 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2604 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2605 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2606 #define DMAE_COMMAND_E1HVN (0x3<<15)
2607 #define DMAE_COMMAND_E1HVN_SHIFT 15
2608 #define DMAE_COMMAND_DST_VN (0x3<<17)
2609 #define DMAE_COMMAND_DST_VN_SHIFT 17
2610 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2611 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2612 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2613 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2614 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2615 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2620 #if defined(__BIG_ENDIAN)
2622 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2623 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2624 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2625 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2626 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2627 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2628 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2629 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2630 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2631 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2632 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2633 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2635 #elif defined(__LITTLE_ENDIAN)
2638 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2639 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2640 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2641 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2642 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2643 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2644 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2645 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2646 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2647 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2648 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2649 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2656 #if defined(__BIG_ENDIAN)
2659 #elif defined(__LITTLE_ENDIAN)
2663 #if defined(__BIG_ENDIAN)
2666 #elif defined(__LITTLE_ENDIAN)
2670 #if defined(__BIG_ENDIAN)
2673 #elif defined(__LITTLE_ENDIAN)
2681 * common data for all protocols
2683 struct doorbell_hdr {
2685 #define DOORBELL_HDR_RX (0x1<<0)
2686 #define DOORBELL_HDR_RX_SHIFT 0
2687 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2688 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2689 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2690 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2691 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2692 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2698 struct eth_tx_doorbell {
2699 #if defined(__BIG_ENDIAN)
2702 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2703 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2704 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2705 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2706 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2707 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2708 struct doorbell_hdr hdr;
2709 #elif defined(__LITTLE_ENDIAN)
2710 struct doorbell_hdr hdr;
2712 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2713 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2714 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2715 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2716 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2717 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2724 * 3 lines. status block
2726 struct hc_status_block_e1x {
2727 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2728 __le16 running_index[HC_SB_MAX_SM];
2735 struct host_hc_status_block_e1x {
2736 struct hc_status_block_e1x sb;
2741 * 3 lines. status block
2743 struct hc_status_block_e2 {
2744 __le16 index_values[HC_SB_MAX_INDICES_E2];
2745 __le16 running_index[HC_SB_MAX_SM];
2746 __le32 reserved[11];
2752 struct host_hc_status_block_e2 {
2753 struct hc_status_block_e2 sb;
2758 * 5 lines. slow-path status block
2760 struct hc_sp_status_block {
2761 __le16 index_values[HC_SP_SB_MAX_INDICES];
2762 __le16 running_index;
2770 struct host_sp_status_block {
2771 struct atten_sp_status_block atten_status_block;
2772 struct hc_sp_status_block sp_sb;
2777 * IGU driver acknowledgment register
2779 struct igu_ack_register {
2780 #if defined(__BIG_ENDIAN)
2781 u16 sb_id_and_flags;
2782 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2783 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2784 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2785 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2786 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2787 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2788 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2789 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2790 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2791 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2792 u16 status_block_index;
2793 #elif defined(__LITTLE_ENDIAN)
2794 u16 status_block_index;
2795 u16 sb_id_and_flags;
2796 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2797 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2798 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2799 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2800 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2801 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2802 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2803 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2804 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2805 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2811 * IGU driver acknowledgement register
2813 struct igu_backward_compatible {
2814 u32 sb_id_and_flags;
2815 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2816 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2817 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2818 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2819 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2820 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2821 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2822 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2823 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2824 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2825 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2826 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2832 * IGU driver acknowledgement register
2834 struct igu_regular {
2835 u32 sb_id_and_flags;
2836 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2837 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2838 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2839 #define IGU_REGULAR_RESERVED0_SHIFT 20
2840 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2841 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2842 #define IGU_REGULAR_BUPDATE (0x1<<24)
2843 #define IGU_REGULAR_BUPDATE_SHIFT 24
2844 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2845 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2846 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2847 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2848 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2849 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2850 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2851 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2852 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2853 #define IGU_REGULAR_BCLEANUP_SHIFT 31
2858 * IGU driver acknowledgement register
2860 union igu_consprod_reg {
2861 struct igu_regular regular;
2862 struct igu_backward_compatible backward_compatible;
2867 * Igu control commands
2870 IGU_CTRL_CMD_TYPE_RD,
2871 IGU_CTRL_CMD_TYPE_WR,
2877 * Control register for the IGU command register
2879 struct igu_ctrl_reg {
2881 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2882 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
2883 #define IGU_CTRL_REG_FID (0x7F<<12)
2884 #define IGU_CTRL_REG_FID_SHIFT 12
2885 #define IGU_CTRL_REG_RESERVED (0x1<<19)
2886 #define IGU_CTRL_REG_RESERVED_SHIFT 19
2887 #define IGU_CTRL_REG_TYPE (0x1<<20)
2888 #define IGU_CTRL_REG_TYPE_SHIFT 20
2889 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2890 #define IGU_CTRL_REG_UNUSED_SHIFT 21
2895 * Igu interrupt command
2909 enum igu_seg_access {
2910 IGU_SEG_ACCESS_NORM,
2912 IGU_SEG_ACCESS_ATTN,
2918 * Parser parsing flags field
2920 struct parsing_flags {
2922 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2923 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2924 #define PARSING_FLAGS_VLAN (0x1<<1)
2925 #define PARSING_FLAGS_VLAN_SHIFT 1
2926 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2927 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2928 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2929 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2930 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2931 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2932 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2933 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2934 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2935 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2936 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2937 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2938 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2939 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2940 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2941 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2942 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2943 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2944 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2945 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2946 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
2947 #define PARSING_FLAGS_RESERVED0_SHIFT 14
2952 * Parsing flags for TCP ACK type
2954 enum prs_flags_ack_type {
2955 PRS_FLAG_PUREACK_PIGGY,
2956 PRS_FLAG_PUREACK_PURE,
2957 MAX_PRS_FLAGS_ACK_TYPE
2962 * Parsing flags for Ethernet address type
2964 enum prs_flags_eth_addr_type {
2965 PRS_FLAG_ETHTYPE_NON_UNICAST,
2966 PRS_FLAG_ETHTYPE_UNICAST,
2967 MAX_PRS_FLAGS_ETH_ADDR_TYPE
2972 * Parsing flags for over-ethernet protocol
2974 enum prs_flags_over_eth {
2975 PRS_FLAG_OVERETH_UNKNOWN,
2976 PRS_FLAG_OVERETH_IPV4,
2977 PRS_FLAG_OVERETH_IPV6,
2978 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
2979 MAX_PRS_FLAGS_OVER_ETH
2984 * Parsing flags for over-IP protocol
2986 enum prs_flags_over_ip {
2987 PRS_FLAG_OVERIP_UNKNOWN,
2988 PRS_FLAG_OVERIP_TCP,
2989 PRS_FLAG_OVERIP_UDP,
2990 MAX_PRS_FLAGS_OVER_IP
2995 * SDM operation gen command (generate aggregative interrupt)
2999 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3000 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3001 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3002 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3003 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3004 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3005 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3006 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3007 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3008 #define SDM_OP_GEN_RESERVED_SHIFT 17
3013 * Timers connection context
3015 struct timers_block_context {
3020 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3021 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3022 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3023 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3024 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3025 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3030 * The eth aggregative context of Tstorm
3032 struct tstorm_eth_ag_context {
3033 u32 __reserved0[14];
3038 * The eth aggregative context of Ustorm
3040 struct ustorm_eth_ag_context {
3042 #if defined(__BIG_ENDIAN)
3046 #elif defined(__LITTLE_ENDIAN)
3056 * The eth aggregative context of Xstorm
3058 struct xstorm_eth_ag_context {
3060 #if defined(__BIG_ENDIAN)
3064 #elif defined(__LITTLE_ENDIAN)
3074 * doorbell message sent to the chip
3077 #if defined(__BIG_ENDIAN)
3080 struct doorbell_hdr header;
3081 #elif defined(__LITTLE_ENDIAN)
3082 struct doorbell_hdr header;
3090 * doorbell message sent to the chip
3092 struct doorbell_set_prod {
3093 #if defined(__BIG_ENDIAN)
3096 struct doorbell_hdr header;
3097 #elif defined(__LITTLE_ENDIAN)
3098 struct doorbell_hdr header;
3112 * Classify rule opcodes in E2/E3
3114 enum classify_rule {
3115 CLASSIFY_RULE_OPCODE_MAC,
3116 CLASSIFY_RULE_OPCODE_VLAN,
3117 CLASSIFY_RULE_OPCODE_PAIR,
3123 * Classify rule types in E2/E3
3125 enum classify_rule_action_type {
3126 CLASSIFY_RULE_REMOVE,
3128 MAX_CLASSIFY_RULE_ACTION_TYPE
3133 * client init ramrod data
3135 struct client_init_general_data {
3137 u8 statistics_counter_id;
3138 u8 statistics_en_flg;
3143 u8 statistics_zero_flg;
3152 * client init rx data
3154 struct client_init_rx_data {
3156 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3157 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3158 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3159 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3160 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2)
3161 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2
3162 u8 vmqueue_mode_en_flg;
3163 u8 extra_data_over_sgl_en_flg;
3164 u8 cache_line_alignment_log_size;
3165 u8 enable_dynamic_hc;
3166 u8 max_sges_for_packet;
3168 u8 drop_ip_cs_err_flg;
3169 u8 drop_tcp_cs_err_flg;
3171 u8 drop_udp_cs_err_flg;
3172 u8 inner_vlan_removal_enable_flg;
3173 u8 outer_vlan_removal_enable_flg;
3175 u8 rx_sb_index_number;
3178 u8 silent_vlan_removal_flg;
3179 __le16 max_bytes_on_bd;
3180 __le16 sge_buff_size;
3181 u8 approx_mcast_engine_id;
3183 struct regpair bd_page_base;
3184 struct regpair sge_page_base;
3185 struct regpair cqe_page_base;
3188 __le16 max_agg_size;
3190 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3191 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3192 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3193 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3194 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3195 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3196 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3197 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3198 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3199 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3200 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3201 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3202 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3203 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3204 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3205 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3206 __le16 cqe_pause_thr_low;
3207 __le16 cqe_pause_thr_high;
3208 __le16 bd_pause_thr_low;
3209 __le16 bd_pause_thr_high;
3210 __le16 sge_pause_thr_low;
3211 __le16 sge_pause_thr_high;
3213 __le16 silent_vlan_value;
3214 __le16 silent_vlan_mask;
3215 __le32 reserved6[2];
3219 * client init tx data
3221 struct client_init_tx_data {
3222 u8 enforce_security_flg;
3223 u8 tx_status_block_id;
3224 u8 tx_sb_index_number;
3225 u8 tss_leading_client_id;
3226 u8 tx_switching_flg;
3227 u8 anti_spoofing_flg;
3228 __le16 default_vlan;
3229 struct regpair tx_bd_page_base;
3231 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3232 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3233 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3234 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3235 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3236 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3237 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3238 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3239 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3240 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3241 u8 default_vlan_flg;
3247 * client init ramrod data
3249 struct client_init_ramrod_data {
3250 struct client_init_general_data general;
3251 struct client_init_rx_data rx;
3252 struct client_init_tx_data tx;
3257 * client update ramrod data
3259 struct client_update_ramrod_data {
3262 u8 inner_vlan_removal_enable_flg;
3263 u8 inner_vlan_removal_change_flg;
3264 u8 outer_vlan_removal_enable_flg;
3265 u8 outer_vlan_removal_change_flg;
3266 u8 anti_spoofing_enable_flg;
3267 u8 anti_spoofing_change_flg;
3269 u8 activate_change_flg;
3270 __le16 default_vlan;
3271 u8 default_vlan_enable_flg;
3272 u8 default_vlan_change_flg;
3273 __le16 silent_vlan_value;
3274 __le16 silent_vlan_mask;
3275 u8 silent_vlan_removal_flg;
3276 u8 silent_vlan_change_flg;
3282 * The eth storm context of Cstorm
3284 struct cstorm_eth_st_context {
3289 struct double_regpair {
3298 * Ethernet address typesm used in ethernet tx BDs
3300 enum eth_addr_type {
3312 struct eth_classify_cmd_header {
3313 u8 cmd_general_data;
3314 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3315 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3316 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3317 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3318 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3319 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3320 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3321 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3322 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3323 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3331 * header for eth classification config ramrod
3333 struct eth_classify_header {
3342 * Command for adding/removing a MAC classification rule
3344 struct eth_classify_mac_cmd {
3345 struct eth_classify_cmd_header header;
3355 * Command for adding/removing a MAC-VLAN pair classification rule
3357 struct eth_classify_pair_cmd {
3358 struct eth_classify_cmd_header header;
3368 * Command for adding/removing a VLAN classification rule
3370 struct eth_classify_vlan_cmd {
3371 struct eth_classify_cmd_header header;
3379 * union for eth classification rule
3381 union eth_classify_rule_cmd {
3382 struct eth_classify_mac_cmd mac;
3383 struct eth_classify_vlan_cmd vlan;
3384 struct eth_classify_pair_cmd pair;
3388 * parameters for eth classification configuration ramrod
3390 struct eth_classify_rules_ramrod_data {
3391 struct eth_classify_header header;
3392 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3397 * The data contain client ID need to the ramrod
3399 struct eth_common_ramrod_data {
3406 * The eth storm context of Ustorm
3408 struct ustorm_eth_st_context {
3413 * The eth storm context of Tstorm
3415 struct tstorm_eth_st_context {
3416 u32 __reserved0[28];
3420 * The eth storm context of Xstorm
3422 struct xstorm_eth_st_context {
3427 * Ethernet connection context
3429 struct eth_context {
3430 struct ustorm_eth_st_context ustorm_st_context;
3431 struct tstorm_eth_st_context tstorm_st_context;
3432 struct xstorm_eth_ag_context xstorm_ag_context;
3433 struct tstorm_eth_ag_context tstorm_ag_context;
3434 struct cstorm_eth_ag_context cstorm_ag_context;
3435 struct ustorm_eth_ag_context ustorm_ag_context;
3436 struct timers_block_context timers_context;
3437 struct xstorm_eth_st_context xstorm_st_context;
3438 struct cstorm_eth_st_context cstorm_st_context;
3443 * union for sgl and raw data.
3445 union eth_sgl_or_raw_data {
3451 * eth FP end aggregation CQE parameters struct
3453 struct eth_end_agg_rx_cqe {
3454 u8 type_error_flags;
3455 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3456 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3457 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3458 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3459 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3460 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3464 __le32 timestamp_delta;
3465 __le16 num_of_coalesced_segs;
3470 union eth_sgl_or_raw_data sgl_or_raw_data;
3471 __le32 reserved5[8];
3476 * regular eth FP CQE parameters struct
3478 struct eth_fast_path_rx_cqe {
3479 u8 type_error_flags;
3480 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3481 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3482 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3483 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3484 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3485 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3486 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3487 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3488 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3489 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3490 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3491 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3493 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3494 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3495 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3496 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3497 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3498 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3499 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3500 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3501 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3502 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3503 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3504 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3506 u8 placement_offset;
3507 __le32 rss_hash_result;
3511 struct parsing_flags pars_flags;
3512 union eth_sgl_or_raw_data sgl_or_raw_data;
3513 __le32 reserved1[8];
3518 * Command for setting classification flags for a client
3520 struct eth_filter_rules_cmd {
3521 u8 cmd_general_data;
3522 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3523 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3524 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3525 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3526 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3527 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3532 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3533 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3534 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3535 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3536 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3537 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3538 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3539 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3540 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3541 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3542 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3543 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3544 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3545 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3546 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3547 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3549 struct regpair reserved4;
3554 * parameters for eth classification filters ramrod
3556 struct eth_filter_rules_ramrod_data {
3557 struct eth_classify_header header;
3558 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3563 * parameters for eth classification configuration ramrod
3565 struct eth_general_rules_ramrod_data {
3566 struct eth_classify_header header;
3567 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3572 * The data for Halt ramrod
3574 struct eth_halt_ramrod_data {
3581 * Command for setting multicast classification for a client
3583 struct eth_multicast_rules_cmd {
3584 u8 cmd_general_data;
3585 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3586 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3587 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3588 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3589 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3590 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3591 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3592 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3597 struct regpair reserved3;
3602 * parameters for multicast classification ramrod
3604 struct eth_multicast_rules_ramrod_data {
3605 struct eth_classify_header header;
3606 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3611 * Place holder for ramrods protocol specific data
3613 struct ramrod_data {
3619 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3621 union eth_ramrod_data {
3622 struct ramrod_data general;
3627 * RSS toeplitz hash type, as reported in CQE
3629 enum eth_rss_hash_type {
3636 E1HOV_PRI_HASH_TYPE,
3638 MAX_ETH_RSS_HASH_TYPE
3646 ETH_RSS_MODE_DISABLED,
3647 ETH_RSS_MODE_REGULAR,
3648 ETH_RSS_MODE_VLAN_PRI,
3649 ETH_RSS_MODE_E1HOV_PRI,
3650 ETH_RSS_MODE_IP_DSCP,
3656 * parameters for RSS update ramrod (E2)
3658 struct eth_rss_update_ramrod_data {
3661 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3662 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3663 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3664 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3665 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3666 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3667 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3668 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3669 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3670 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3671 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3672 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3673 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3674 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3675 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3676 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3680 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3681 __le32 rss_key[T_ETH_RSS_KEY];
3688 * The eth Rx Buffer Descriptor
3697 * Eth Rx Cqe structure- general structure for ramrods
3699 struct common_ramrod_eth_rx_cqe {
3701 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3702 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3703 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3704 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3705 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3706 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3709 __le32 conn_and_cmd_data;
3710 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3711 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3712 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3713 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3714 struct ramrod_data protocol_data;
3716 __le32 reserved2[11];
3720 * Rx Last CQE in page (in ETH)
3722 struct eth_rx_cqe_next_page {
3725 __le32 reserved[14];
3729 * union for all eth rx cqe types (fix their sizes)
3732 struct eth_fast_path_rx_cqe fast_path_cqe;
3733 struct common_ramrod_eth_rx_cqe ramrod_cqe;
3734 struct eth_rx_cqe_next_page next_page_cqe;
3735 struct eth_end_agg_rx_cqe end_agg_cqe;
3740 * Values for RX ETH CQE type field
3742 enum eth_rx_cqe_type {
3743 RX_ETH_CQE_TYPE_ETH_FASTPATH,
3744 RX_ETH_CQE_TYPE_ETH_RAMROD,
3745 RX_ETH_CQE_TYPE_ETH_START_AGG,
3746 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
3752 * Type of SGL/Raw field in ETH RX fast path CQE
3754 enum eth_rx_fp_sel {
3762 * The eth Rx SGE Descriptor
3771 * common data for all protocols
3774 __le32 conn_and_cmd_data;
3775 #define SPE_HDR_CID (0xFFFFFF<<0)
3776 #define SPE_HDR_CID_SHIFT 0
3777 #define SPE_HDR_CMD_ID (0xFF<<24)
3778 #define SPE_HDR_CMD_ID_SHIFT 24
3780 #define SPE_HDR_CONN_TYPE (0xFF<<0)
3781 #define SPE_HDR_CONN_TYPE_SHIFT 0
3782 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
3783 #define SPE_HDR_FUNCTION_ID_SHIFT 8
3788 * specific data for ethernet slow path element
3790 union eth_specific_data {
3791 u8 protocol_data[8];
3792 struct regpair client_update_ramrod_data;
3793 struct regpair client_init_ramrod_init_data;
3794 struct eth_halt_ramrod_data halt_ramrod_data;
3795 struct regpair update_data_addr;
3796 struct eth_common_ramrod_data common_ramrod_data;
3797 struct regpair classify_cfg_addr;
3798 struct regpair filter_cfg_addr;
3799 struct regpair mcast_cfg_addr;
3803 * Ethernet slow path element
3807 union eth_specific_data data;
3812 * Ethernet command ID for slow path elements
3814 enum eth_spqe_cmd_id {
3815 RAMROD_CMD_ID_ETH_UNUSED,
3816 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
3817 RAMROD_CMD_ID_ETH_HALT,
3818 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
3819 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
3820 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
3821 RAMROD_CMD_ID_ETH_EMPTY,
3822 RAMROD_CMD_ID_ETH_TERMINATE,
3823 RAMROD_CMD_ID_ETH_TPA_UPDATE,
3824 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
3825 RAMROD_CMD_ID_ETH_FILTER_RULES,
3826 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3827 RAMROD_CMD_ID_ETH_RSS_UPDATE,
3828 RAMROD_CMD_ID_ETH_SET_MAC,
3834 * eth tpa update command
3836 enum eth_tpa_update_command {
3837 TPA_UPDATE_NONE_COMMAND,
3838 TPA_UPDATE_ENABLE_COMMAND,
3839 TPA_UPDATE_DISABLE_COMMAND,
3840 MAX_ETH_TPA_UPDATE_COMMAND
3845 * Tx regular BD structure
3850 __le16 total_pkt_bytes;
3857 * structure for easy accessibility to assembler
3859 struct eth_tx_bd_flags {
3861 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
3862 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
3863 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
3864 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
3865 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
3866 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
3867 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
3868 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
3869 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
3870 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
3871 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
3872 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
3873 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
3874 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
3878 * The eth Tx Buffer Descriptor
3880 struct eth_tx_start_bd {
3885 __le16 vlan_or_ethertype;
3886 struct eth_tx_bd_flags bd_flags;
3888 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
3889 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
3890 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
3891 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
3892 #define ETH_TX_START_BD_RESREVED (0x1<<5)
3893 #define ETH_TX_START_BD_RESREVED_SHIFT 5
3894 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
3895 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
3899 * Tx parsing BD structure for ETH E1/E1h
3901 struct eth_tx_parse_bd_e1x {
3903 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
3904 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
3905 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
3906 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
3907 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
3908 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
3909 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
3910 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
3911 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
3912 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
3914 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
3915 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
3916 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
3917 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
3918 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
3919 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
3920 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
3921 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
3922 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
3923 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
3924 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
3925 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
3926 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
3927 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
3928 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
3929 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
3932 __le16 total_hlen_w;
3933 __le16 tcp_pseudo_csum;
3936 __le32 tcp_send_seq;
3940 * Tx parsing BD structure for ETH E2
3942 struct eth_tx_parse_bd_e2 {
3943 __le16 dst_mac_addr_lo;
3944 __le16 dst_mac_addr_mid;
3945 __le16 dst_mac_addr_hi;
3946 __le16 src_mac_addr_lo;
3947 __le16 src_mac_addr_mid;
3948 __le16 src_mac_addr_hi;
3949 __le32 parsing_data;
3950 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
3951 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
3952 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
3953 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
3954 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
3955 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
3956 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
3957 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
3961 * The last BD in the BD memory will hold a pointer to the next BD memory
3963 struct eth_tx_next_bd {
3970 * union for 4 Bd types
3972 union eth_tx_bd_types {
3973 struct eth_tx_start_bd start_bd;
3974 struct eth_tx_bd reg_bd;
3975 struct eth_tx_parse_bd_e1x parse_bd_e1x;
3976 struct eth_tx_parse_bd_e2 parse_bd_e2;
3977 struct eth_tx_next_bd next_bd;
3981 * array of 13 bds as appears in the eth xstorm context
3983 struct eth_tx_bds_array {
3984 union eth_tx_bd_types bds[13];
3989 * VLAN mode on TX BDs
3991 enum eth_tx_vlan_type {
3995 X_ETH_FW_ADDED_VLAN,
3996 MAX_ETH_TX_VLAN_TYPE
4001 * Ethernet VLAN filtering mode in E1x
4003 enum eth_vlan_filter_mode {
4004 ETH_VLAN_FILTER_ANY_VLAN,
4005 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4006 ETH_VLAN_FILTER_CLASSIFY,
4007 MAX_ETH_VLAN_FILTER_MODE
4012 * MAC filtering configuration command header
4014 struct mac_configuration_hdr {
4022 * MAC address in list for ramrod
4024 struct mac_configuration_entry {
4025 __le16 lsb_mac_addr;
4026 __le16 middle_mac_addr;
4027 __le16 msb_mac_addr;
4031 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4032 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4033 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4034 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4035 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4036 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4037 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4038 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4039 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4040 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4041 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4042 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4044 __le32 clients_bit_vector;
4048 * MAC filtering configuration command
4050 struct mac_configuration_cmd {
4051 struct mac_configuration_hdr hdr;
4052 struct mac_configuration_entry config_table[64];
4057 * Set-MAC command type (in E1x)
4059 enum set_mac_action_type {
4060 T_ETH_MAC_COMMAND_INVALIDATE,
4061 T_ETH_MAC_COMMAND_SET,
4062 MAX_SET_MAC_ACTION_TYPE
4067 * tpa update ramrod data
4069 struct tpa_update_ramrod_data {
4074 u8 max_sges_for_packet;
4075 u8 complete_on_both_clients;
4077 __le16 sge_buff_size;
4078 __le16 max_agg_size;
4079 __le32 sge_page_base_lo;
4080 __le32 sge_page_base_hi;
4081 __le16 sge_pause_thr_low;
4082 __le16 sge_pause_thr_high;
4087 * approximate-match multicast filtering for E1H per function in Tstorm
4089 struct tstorm_eth_approximate_match_multicast_filtering {
4090 u32 mcast_add_hash_bit_array[8];
4095 * Common configuration parameters per function in Tstorm
4097 struct tstorm_eth_function_common_config {
4098 __le16 config_flags;
4099 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4100 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4101 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4102 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4103 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4104 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4105 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4106 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4107 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4108 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4109 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4110 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4111 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4112 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4120 * MAC filtering configuration parameters per port in Tstorm
4122 struct tstorm_eth_mac_filter_config {
4123 __le32 ucast_drop_all;
4124 __le32 ucast_accept_all;
4125 __le32 mcast_drop_all;
4126 __le32 mcast_accept_all;
4127 __le32 bcast_accept_all;
4128 __le32 vlan_filter[2];
4129 __le32 unmatched_unicast;
4134 * tx only queue init ramrod data
4136 struct tx_queue_init_ramrod_data {
4137 struct client_init_general_data general;
4138 struct client_init_tx_data tx;
4143 * Three RX producers for ETH
4145 struct ustorm_eth_rx_producers {
4146 #if defined(__BIG_ENDIAN)
4149 #elif defined(__LITTLE_ENDIAN)
4153 #if defined(__BIG_ENDIAN)
4156 #elif defined(__LITTLE_ENDIAN)
4164 * cfc delete event data
4166 struct cfc_del_event_data {
4174 * per-port SAFC demo variables
4176 struct cmng_flags_per_port {
4178 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4179 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4180 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4181 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4182 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4183 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4184 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4185 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4186 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4187 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4193 * per-port rate shaping variables
4195 struct rate_shaping_vars_per_port {
4196 u32 rs_periodic_timeout;
4201 * per-port fairness variables
4203 struct fairness_vars_per_port {
4206 u32 fairness_timeout;
4211 * per-port SAFC variables
4213 struct safc_struct_per_port {
4214 #if defined(__BIG_ENDIAN)
4217 u8 safc_timeout_usec;
4218 #elif defined(__LITTLE_ENDIAN)
4219 u8 safc_timeout_usec;
4223 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4224 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4228 * Per-port congestion management variables
4230 struct cmng_struct_per_port {
4231 struct rate_shaping_vars_per_port rs_vars;
4232 struct fairness_vars_per_port fair_vars;
4233 struct safc_struct_per_port safc_vars;
4234 struct cmng_flags_per_port flags;
4239 * Protocol-common command ID for slow path elements
4241 enum common_spqe_cmd_id {
4242 RAMROD_CMD_ID_COMMON_UNUSED,
4243 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4244 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4245 RAMROD_CMD_ID_COMMON_CFC_DEL,
4246 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4247 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4248 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4249 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4250 RAMROD_CMD_ID_COMMON_RESERVED1,
4251 RAMROD_CMD_ID_COMMON_RESERVED2,
4252 MAX_COMMON_SPQE_CMD_ID
4257 * Per-protocol connection types
4259 enum connection_type {
4260 ETH_CONNECTION_TYPE,
4261 TOE_CONNECTION_TYPE,
4262 RDMA_CONNECTION_TYPE,
4263 ISCSI_CONNECTION_TYPE,
4264 FCOE_CONNECTION_TYPE,
4265 RESERVED_CONNECTION_TYPE_0,
4266 RESERVED_CONNECTION_TYPE_1,
4267 RESERVED_CONNECTION_TYPE_2,
4268 NONE_CONNECTION_TYPE,
4285 * Dynamic HC counters set by the driver
4287 struct hc_dynamic_drv_counter {
4288 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4292 * zone A per-queue data
4294 struct cstorm_queue_zone_data {
4295 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4296 struct regpair reserved[2];
4301 * Vf-PF channel data in cstorm ram (non-triggered zone)
4303 struct vf_pf_channel_zone_data {
4309 * zone for VF non-triggered data
4311 struct non_trigger_vf_zone {
4312 struct vf_pf_channel_zone_data vf_pf_channel;
4316 * Vf-PF channel trigger zone in cstorm ram
4318 struct vf_pf_channel_zone_trigger {
4323 * zone that triggers the in-bound interrupt
4325 struct trigger_vf_zone {
4326 #if defined(__BIG_ENDIAN)
4329 struct vf_pf_channel_zone_trigger vf_pf_channel;
4330 #elif defined(__LITTLE_ENDIAN)
4331 struct vf_pf_channel_zone_trigger vf_pf_channel;
4339 * zone B per-VF data
4341 struct cstorm_vf_zone_data {
4342 struct non_trigger_vf_zone non_trigger;
4343 struct trigger_vf_zone trigger;
4348 * Dynamic host coalescing init parameters, per state machine
4350 struct dynamic_hc_sm_config {
4352 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4353 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4354 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4355 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4356 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4360 * Dynamic host coalescing init parameters
4362 struct dynamic_hc_config {
4363 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4367 struct e2_integ_data {
4368 #if defined(__BIG_ENDIAN)
4370 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4371 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4372 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4373 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4374 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4375 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4376 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4377 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4378 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4379 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4380 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4381 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4385 #elif defined(__LITTLE_ENDIAN)
4390 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4391 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4392 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4393 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4394 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4395 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4396 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4397 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4398 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4399 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4400 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4401 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4403 #if defined(__BIG_ENDIAN)
4407 #elif defined(__LITTLE_ENDIAN)
4416 * set mac event data
4418 struct eth_event_data {
4428 struct vf_pf_event_data {
4439 struct vf_flr_event_data {
4448 * malicious VF event data
4450 struct malicious_vf_event_data {
4459 * union for all event ring message types
4462 struct vf_pf_event_data vf_pf_event;
4463 struct eth_event_data eth_event;
4464 struct cfc_del_event_data cfc_del_event;
4465 struct vf_flr_event_data vf_flr_event;
4466 struct malicious_vf_event_data malicious_vf_event;
4471 * per PF event ring data
4473 struct event_ring_data {
4474 struct regpair base_addr;
4475 #if defined(__BIG_ENDIAN)
4479 #elif defined(__LITTLE_ENDIAN)
4489 * event ring message element (each element is 128 bits)
4491 struct event_ring_msg {
4495 union event_data data;
4499 * event ring next page element (128 bits)
4501 struct event_ring_next {
4502 struct regpair addr;
4507 * union for event ring element types (each element is 128 bits)
4509 union event_ring_elem {
4510 struct event_ring_msg message;
4511 struct event_ring_next next_page;
4516 * Common event ring opcodes
4518 enum event_ring_opcode {
4519 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4520 EVENT_RING_OPCODE_FUNCTION_START,
4521 EVENT_RING_OPCODE_FUNCTION_STOP,
4522 EVENT_RING_OPCODE_CFC_DEL,
4523 EVENT_RING_OPCODE_CFC_DEL_WB,
4524 EVENT_RING_OPCODE_STAT_QUERY,
4525 EVENT_RING_OPCODE_STOP_TRAFFIC,
4526 EVENT_RING_OPCODE_START_TRAFFIC,
4527 EVENT_RING_OPCODE_VF_FLR,
4528 EVENT_RING_OPCODE_MALICIOUS_VF,
4529 EVENT_RING_OPCODE_FORWARD_SETUP,
4530 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4531 EVENT_RING_OPCODE_RESERVED1,
4532 EVENT_RING_OPCODE_RESERVED2,
4533 EVENT_RING_OPCODE_SET_MAC,
4534 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4535 EVENT_RING_OPCODE_FILTERS_RULES,
4536 EVENT_RING_OPCODE_MULTICAST_RULES,
4537 MAX_EVENT_RING_OPCODE
4542 * Modes for fairness algorithm
4544 enum fairness_mode {
4545 FAIRNESS_COS_WRR_MODE,
4546 FAIRNESS_COS_ETS_MODE,
4552 * per-vnic fairness variables
4554 struct fairness_vars_per_vn {
4555 u32 cos_credit_delta[MAX_COS_NUMBER];
4556 u32 vn_credit_delta;
4564 struct priority_cos {
4571 * The data for flow control configuration
4573 struct flow_control_configuration {
4574 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4577 u8 dont_add_pri_0_en;
4586 struct function_start_data {
4587 __le16 function_mode;
4591 u8 network_cos_mode;
4596 * FW version stored in the Xstorm RAM
4599 #if defined(__BIG_ENDIAN)
4604 #elif defined(__LITTLE_ENDIAN)
4611 #define FW_VERSION_OPTIMIZED (0x1<<0)
4612 #define FW_VERSION_OPTIMIZED_SHIFT 0
4613 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
4614 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
4615 #define FW_VERSION_CHIP_VERSION (0x3<<2)
4616 #define FW_VERSION_CHIP_VERSION_SHIFT 2
4617 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
4618 #define __FW_VERSION_RESERVED_SHIFT 4
4623 * Dynamic Host-Coalescing - Driver(host) counters
4625 struct hc_dynamic_sb_drv_counters {
4626 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
4631 * 2 bytes. configuration/state parameters for a single protocol index
4633 struct hc_index_data {
4634 #if defined(__BIG_ENDIAN)
4636 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4637 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4638 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4639 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4640 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4641 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4642 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4643 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4645 #elif defined(__LITTLE_ENDIAN)
4648 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4649 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4650 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4651 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4652 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4653 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4654 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4655 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4663 struct hc_status_block_sm {
4664 #if defined(__BIG_ENDIAN)
4669 #elif defined(__LITTLE_ENDIAN)
4679 * hold PCI identification variables- used in various places in firmware
4682 #if defined(__BIG_ENDIAN)
4687 #elif defined(__LITTLE_ENDIAN)
4696 * The fast-path status block meta-data, common to all chips
4699 struct regpair host_sb_addr;
4700 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
4701 struct pci_entity p_func;
4702 #if defined(__BIG_ENDIAN)
4707 #elif defined(__LITTLE_ENDIAN)
4713 struct regpair rsrv1[2];
4718 * Segment types for host coaslescing
4728 * The fast-path status block meta-data
4730 struct hc_sp_status_block_data {
4731 struct regpair host_sb_addr;
4732 #if defined(__BIG_ENDIAN)
4737 #elif defined(__LITTLE_ENDIAN)
4743 struct pci_entity p_func;
4748 * The fast-path status block meta-data
4750 struct hc_status_block_data_e1x {
4751 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
4752 struct hc_sb_data common;
4757 * The fast-path status block meta-data
4759 struct hc_status_block_data_e2 {
4760 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
4761 struct hc_sb_data common;
4766 * IGU block operartion modes (in Everest2)
4786 * Multi-function modes
4792 MULTI_FUNCTION_RESERVED,
4797 * Protocol-common statistics collected by the Tstorm (per pf)
4799 struct tstorm_per_pf_stats {
4800 struct regpair rcv_error_bytes;
4806 struct per_pf_stats {
4807 struct tstorm_per_pf_stats tstorm_pf_statistics;
4812 * Protocol-common statistics collected by the Tstorm (per port)
4814 struct tstorm_per_port_stats {
4816 __le32 mac_filter_discard;
4817 __le32 brb_truncate_discard;
4818 __le32 mf_tag_discard;
4826 struct per_port_stats {
4827 struct tstorm_per_port_stats tstorm_port_statistics;
4832 * Protocol-common statistics collected by the Tstorm (per client)
4834 struct tstorm_per_queue_stats {
4835 struct regpair rcv_ucast_bytes;
4836 __le32 rcv_ucast_pkts;
4837 __le32 checksum_discard;
4838 struct regpair rcv_bcast_bytes;
4839 __le32 rcv_bcast_pkts;
4840 __le32 pkts_too_big_discard;
4841 struct regpair rcv_mcast_bytes;
4842 __le32 rcv_mcast_pkts;
4843 __le32 ttl0_discard;
4844 __le16 no_buff_discard;
4850 * Protocol-common statistics collected by the Ustorm (per client)
4852 struct ustorm_per_queue_stats {
4853 struct regpair ucast_no_buff_bytes;
4854 struct regpair mcast_no_buff_bytes;
4855 struct regpair bcast_no_buff_bytes;
4856 __le32 ucast_no_buff_pkts;
4857 __le32 mcast_no_buff_pkts;
4858 __le32 bcast_no_buff_pkts;
4859 __le32 coalesced_pkts;
4860 struct regpair coalesced_bytes;
4861 __le32 coalesced_events;
4862 __le32 coalesced_aborts;
4866 * Protocol-common statistics collected by the Xstorm (per client)
4868 struct xstorm_per_queue_stats {
4869 struct regpair ucast_bytes_sent;
4870 struct regpair mcast_bytes_sent;
4871 struct regpair bcast_bytes_sent;
4872 __le32 ucast_pkts_sent;
4873 __le32 mcast_pkts_sent;
4874 __le32 bcast_pkts_sent;
4875 __le32 error_drop_pkts;
4881 struct per_queue_stats {
4882 struct tstorm_per_queue_stats tstorm_queue_statistics;
4883 struct ustorm_per_queue_stats ustorm_queue_statistics;
4884 struct xstorm_per_queue_stats xstorm_queue_statistics;
4889 * FW version stored in first line of pram
4891 struct pram_fw_version {
4897 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
4898 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
4899 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
4900 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
4901 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
4902 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
4903 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
4904 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
4905 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
4906 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
4911 * Ethernet slow path element
4913 union protocol_common_specific_data {
4914 u8 protocol_data[8];
4915 struct regpair phy_address;
4916 struct regpair mac_config_addr;
4920 * The send queue element
4922 struct protocol_common_spe {
4924 union protocol_common_specific_data data;
4929 * a single rate shaping counter. can be used as protocol or vnic counter
4931 struct rate_shaping_counter {
4933 #if defined(__BIG_ENDIAN)
4936 #elif defined(__LITTLE_ENDIAN)
4944 * per-vnic rate shaping variables
4946 struct rate_shaping_vars_per_vn {
4947 struct rate_shaping_counter vn_counter;
4952 * The send queue element
4954 struct slow_path_element {
4956 struct regpair protocol_data;
4961 * Protocol-common statistics counter
4963 struct stats_counter {
4964 __le16 xstats_counter;
4967 __le16 tstats_counter;
4970 __le16 ustats_counter;
4973 __le16 cstats_counter;
4982 struct stats_query_entry {
4987 struct regpair address;
4993 struct stats_query_cmd_group {
4994 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
4999 * statistic command header
5001 struct stats_query_header {
5004 __le16 drv_stats_counter;
5006 struct regpair stats_counters_addrs;
5011 * Types of statistcis query entry
5013 enum stats_query_type {
5019 MAX_STATS_QUERY_TYPE
5024 * Indicate of the function status block state
5026 enum status_block_state {
5030 MAX_STATUS_BLOCK_STATE
5035 * Storm IDs (including attentions for IGU related enums)
5048 * Taffic types used in ETS and flow control algorithms
5051 LLFC_TRAFFIC_TYPE_NW,
5052 LLFC_TRAFFIC_TYPE_FCOE,
5053 LLFC_TRAFFIC_TYPE_ISCSI,
5059 * zone A per-queue data
5061 struct tstorm_queue_zone_data {
5062 struct regpair reserved[4];
5067 * zone B per-VF data
5069 struct tstorm_vf_zone_data {
5070 struct regpair reserved;
5075 * zone A per-queue data
5077 struct ustorm_queue_zone_data {
5078 struct ustorm_eth_rx_producers eth_rx_producers;
5079 struct regpair reserved[3];
5084 * zone B per-VF data
5086 struct ustorm_vf_zone_data {
5087 struct regpair reserved;
5092 * data per VF-PF channel
5094 struct vf_pf_channel_data {
5095 #if defined(__BIG_ENDIAN)
5099 #elif defined(__LITTLE_ENDIAN)
5109 * State of VF-PF channel
5111 enum vf_pf_channel_state {
5112 VF_PF_CHANNEL_STATE_READY,
5113 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5114 MAX_VF_PF_CHANNEL_STATE
5119 * zone A per-queue data
5121 struct xstorm_queue_zone_data {
5122 struct regpair reserved[4];
5127 * zone B per-VF data
5129 struct xstorm_vf_zone_data {
5130 struct regpair reserved;
5133 #endif /* BNX2X_HSI_H */
git.openpandora.org / pandora-kernel.git / blob