drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567LM-2 Gigabit Network Connection
  44  * 82567LF-2 Gigabit Network Connection
  45  * 82567V-2 Gigabit Network Connection
  46  * 82567LF-3 Gigabit Network Connection
  47  * 82567LM-3 Gigabit Network Connection
  48  * 82567LM-4 Gigabit Network Connection
  49  */
  50
  51 #include <linux/netdevice.h>
  52 #include <linux/ethtool.h>
  53 #include <linux/delay.h>
  54 #include <linux/pci.h>
  55
  56 #include "e1000.h"
  57
  58 #define ICH_FLASH_GFPREG                0x0000
  59 #define ICH_FLASH_HSFSTS                0x0004
  60 #define ICH_FLASH_HSFCTL                0x0006
  61 #define ICH_FLASH_FADDR                 0x0008
  62 #define ICH_FLASH_FDATA0                0x0010
  63 #define ICH_FLASH_PR0                   0x0074
  64
  65 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  66 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  67 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  68 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  69 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  70
  71 #define ICH_CYCLE_READ                  0
  72 #define ICH_CYCLE_WRITE                 2
  73 #define ICH_CYCLE_ERASE                 3
  74
  75 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  76 #define FLASH_SECTOR_ADDR_SHIFT         12
  77
  78 #define ICH_FLASH_SEG_SIZE_256          256
  79 #define ICH_FLASH_SEG_SIZE_4K           4096
  80 #define ICH_FLASH_SEG_SIZE_8K           8192
  81 #define ICH_FLASH_SEG_SIZE_64K          65536
  82
  83
  84 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  85
  86 #define E1000_ICH_MNG_IAMT_MODE         0x2
  87
  88 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  89                                  (ID_LED_DEF1_OFF2 <<  8) | \
  90                                  (ID_LED_DEF1_ON2  <<  4) | \
  91                                  (ID_LED_DEF1_DEF2))
  92
  93 #define E1000_ICH_NVM_SIG_WORD          0x13
  94 #define E1000_ICH_NVM_SIG_MASK          0xC000
  95
  96 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  97
  98 #define E1000_FEXTNVM_SW_CONFIG         1
  99 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 100
 101 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 102
 103 #define E1000_ICH_RAR_ENTRIES           7
 104
 105 #define PHY_PAGE_SHIFT 5
 106 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 107                            ((reg) & MAX_PHY_REG_ADDRESS))
 108 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 109 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 110
 111 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 112 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 113 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 114
 115 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 116 /* Offset 04h HSFSTS */
 117 union ich8_hws_flash_status {
 118         struct ich8_hsfsts {
 119                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 120                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 121                 u16 dael       :1; /* bit 2 Direct Access error Log */
 122                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 123                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 124                 u16 reserved1  :2; /* bit 13:6 Reserved */
 125                 u16 reserved2  :6; /* bit 13:6 Reserved */
 126                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 127                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 128         } hsf_status;
 129         u16 regval;
 130 };
 131
 132 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 133 /* Offset 06h FLCTL */
 134 union ich8_hws_flash_ctrl {
 135         struct ich8_hsflctl {
 136                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 137                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 138                 u16 reserved   :5;   /* 7:3 Reserved  */
 139                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 140                 u16 flockdn    :6;   /* 15:10 Reserved */
 141         } hsf_ctrl;
 142         u16 regval;
 143 };
 144
 145 /* ICH Flash Region Access Permissions */
 146 union ich8_hws_flash_regacc {
 147         struct ich8_flracc {
 148                 u32 grra      :8; /* 0:7 GbE region Read Access */
 149                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 150                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 151                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 152         } hsf_flregacc;
 153         u16 regval;
 154 };
 155
 156 /* ICH Flash Protected Region */
 157 union ich8_flash_protected_range {
 158         struct ich8_pr {
 159                 u32 base:13;     /* 0:12 Protected Range Base */
 160                 u32 reserved1:2; /* 13:14 Reserved */
 161                 u32 rpe:1;       /* 15 Read Protection Enable */
 162                 u32 limit:13;    /* 16:28 Protected Range Limit */
 163                 u32 reserved2:2; /* 29:30 Reserved */
 164                 u32 wpe:1;       /* 31 Write Protection Enable */
 165         } range;
 166         u32 regval;
 167 };
 168
 169 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 170 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 171 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 172 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 173 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 174 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 175                                                 u32 offset, u8 byte);
 176 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 177                                          u8 *data);
 178 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 179                                          u16 *data);
 180 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 181                                          u8 size, u16 *data);
 182 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 183 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 184 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 185
 186 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 187 {
 188         return readw(hw->flash_address + reg);
 189 }
 190
 191 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 192 {
 193         return readl(hw->flash_address + reg);
 194 }
 195
 196 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 197 {
 198         writew(val, hw->flash_address + reg);
 199 }
 200
 201 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 202 {
 203         writel(val, hw->flash_address + reg);
 204 }
 205
 206 #define er16flash(reg)          __er16flash(hw, (reg))
 207 #define er32flash(reg)          __er32flash(hw, (reg))
 208 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 209 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 210
 211 /**
 212  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 213  *  @hw: pointer to the HW structure
 214  *
 215  *  Initialize family-specific PHY parameters and function pointers.
 216  **/
 217 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 218 {
 219         struct e1000_phy_info *phy = &hw->phy;
 220         s32 ret_val;
 221         u16 i = 0;
 222
 223         phy->addr                       = 1;
 224         phy->reset_delay_us             = 100;
 225
 226         /*
 227          * We may need to do this twice - once for IGP and if that fails,
 228          * we'll set BM func pointers and try again
 229          */
 230         ret_val = e1000e_determine_phy_address(hw);
 231         if (ret_val) {
 232                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 233                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 234                 ret_val = e1000e_determine_phy_address(hw);
 235                 if (ret_val)
 236                         return ret_val;
 237         }
 238
 239         phy->id = 0;
 240         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 241                (i++ < 100)) {
 242                 msleep(1);
 243                 ret_val = e1000e_get_phy_id(hw);
 244                 if (ret_val)
 245                         return ret_val;
 246         }
 247
 248         /* Verify phy id */
 249         switch (phy->id) {
 250         case IGP03E1000_E_PHY_ID:
 251                 phy->type = e1000_phy_igp_3;
 252                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 253                 break;
 254         case IFE_E_PHY_ID:
 255         case IFE_PLUS_E_PHY_ID:
 256         case IFE_C_E_PHY_ID:
 257                 phy->type = e1000_phy_ife;
 258                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 259                 break;
 260         case BME1000_E_PHY_ID:
 261                 phy->type = e1000_phy_bm;
 262                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 263                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 264                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 265                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 266                 break;
 267         default:
 268                 return -E1000_ERR_PHY;
 269                 break;
 270         }
 271
 272         return 0;
 273 }
 274
 275 /**
 276  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 277  *  @hw: pointer to the HW structure
 278  *
 279  *  Initialize family-specific NVM parameters and function
 280  *  pointers.
 281  **/
 282 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 283 {
 284         struct e1000_nvm_info *nvm = &hw->nvm;
 285         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 286         u32 gfpreg;
 287         u32 sector_base_addr;
 288         u32 sector_end_addr;
 289         u16 i;
 290
 291         /* Can't read flash registers if the register set isn't mapped. */
 292         if (!hw->flash_address) {
 293                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 294                 return -E1000_ERR_CONFIG;
 295         }
 296
 297         nvm->type = e1000_nvm_flash_sw;
 298
 299         gfpreg = er32flash(ICH_FLASH_GFPREG);
 300
 301         /*
 302          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 303          * Add 1 to sector_end_addr since this sector is included in
 304          * the overall size.
 305          */
 306         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 307         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 308
 309         /* flash_base_addr is byte-aligned */
 310         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 311
 312         /*
 313          * find total size of the NVM, then cut in half since the total
 314          * size represents two separate NVM banks.
 315          */
 316         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 317                                 << FLASH_SECTOR_ADDR_SHIFT;
 318         nvm->flash_bank_size /= 2;
 319         /* Adjust to word count */
 320         nvm->flash_bank_size /= sizeof(u16);
 321
 322         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 323
 324         /* Clear shadow ram */
 325         for (i = 0; i < nvm->word_size; i++) {
 326                 dev_spec->shadow_ram[i].modified = 0;
 327                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 328         }
 329
 330         return 0;
 331 }
 332
 333 /**
 334  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 335  *  @hw: pointer to the HW structure
 336  *
 337  *  Initialize family-specific MAC parameters and function
 338  *  pointers.
 339  **/
 340 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 341 {
 342         struct e1000_hw *hw = &adapter->hw;
 343         struct e1000_mac_info *mac = &hw->mac;
 344
 345         /* Set media type function pointer */
 346         hw->phy.media_type = e1000_media_type_copper;
 347
 348         /* Set mta register count */
 349         mac->mta_reg_count = 32;
 350         /* Set rar entry count */
 351         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 352         if (mac->type == e1000_ich8lan)
 353                 mac->rar_entry_count--;
 354         /* Set if manageability features are enabled. */
 355         mac->arc_subsystem_valid = 1;
 356
 357         /* Enable PCS Lock-loss workaround for ICH8 */
 358         if (mac->type == e1000_ich8lan)
 359                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 360
 361         return 0;
 362 }
 363
 364 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 365 {
 366         struct e1000_hw *hw = &adapter->hw;
 367         s32 rc;
 368
 369         rc = e1000_init_mac_params_ich8lan(adapter);
 370         if (rc)
 371                 return rc;
 372
 373         rc = e1000_init_nvm_params_ich8lan(hw);
 374         if (rc)
 375                 return rc;
 376
 377         rc = e1000_init_phy_params_ich8lan(hw);
 378         if (rc)
 379                 return rc;
 380
 381         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 382             (adapter->hw.phy.type == e1000_phy_igp_3))
 383                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 384
 385         return 0;
 386 }
 387
 388 static DEFINE_MUTEX(nvm_mutex);
 389 static pid_t nvm_owner = -1;
 390
 391 /**
 392  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 393  *  @hw: pointer to the HW structure
 394  *
 395  *  Acquires the software control flag for performing NVM and PHY
 396  *  operations.  This is a function pointer entry point only called by
 397  *  read/write routines for the PHY and NVM parts.
 398  **/
 399 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 400 {
 401         u32 extcnf_ctrl;
 402         u32 timeout = PHY_CFG_TIMEOUT;
 403
 404         might_sleep();
 405
 406         if (!mutex_trylock(&nvm_mutex)) {
 407                 WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n",
 408                      nvm_owner);
 409                 mutex_lock(&nvm_mutex);
 410         }
 411         nvm_owner = current->pid;
 412
 413         while (timeout) {
 414                 extcnf_ctrl = er32(EXTCNF_CTRL);
 415                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 416                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 417
 418                 extcnf_ctrl = er32(EXTCNF_CTRL);
 419                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 420                         break;
 421                 mdelay(1);
 422                 timeout--;
 423         }
 424
 425         if (!timeout) {
 426                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 427                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 428                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 429                 nvm_owner = -1;
 430                 mutex_unlock(&nvm_mutex);
 431                 return -E1000_ERR_CONFIG;
 432         }
 433
 434         return 0;
 435 }
 436
 437 /**
 438  *  e1000_release_swflag_ich8lan - Release software control flag
 439  *  @hw: pointer to the HW structure
 440  *
 441  *  Releases the software control flag for performing NVM and PHY operations.
 442  *  This is a function pointer entry point only called by read/write
 443  *  routines for the PHY and NVM parts.
 444  **/
 445 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 446 {
 447         u32 extcnf_ctrl;
 448
 449         extcnf_ctrl = er32(EXTCNF_CTRL);
 450         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 451         ew32(EXTCNF_CTRL, extcnf_ctrl);
 452
 453         nvm_owner = -1;
 454         mutex_unlock(&nvm_mutex);
 455 }
 456
 457 /**
 458  *  e1000_check_mng_mode_ich8lan - Checks management mode
 459  *  @hw: pointer to the HW structure
 460  *
 461  *  This checks if the adapter has manageability enabled.
 462  *  This is a function pointer entry point only called by read/write
 463  *  routines for the PHY and NVM parts.
 464  **/
 465 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 466 {
 467         u32 fwsm = er32(FWSM);
 468
 469         return (fwsm & E1000_FWSM_MODE_MASK) ==
 470                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 471 }
 472
 473 /**
 474  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 475  *  @hw: pointer to the HW structure
 476  *
 477  *  Checks if firmware is blocking the reset of the PHY.
 478  *  This is a function pointer entry point only called by
 479  *  reset routines.
 480  **/
 481 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 482 {
 483         u32 fwsm;
 484
 485         fwsm = er32(FWSM);
 486
 487         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 488 }
 489
 490 /**
 491  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 492  *  @hw: pointer to the HW structure
 493  *
 494  *  Forces the speed and duplex settings of the PHY.
 495  *  This is a function pointer entry point only called by
 496  *  PHY setup routines.
 497  **/
 498 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_phy_info *phy = &hw->phy;
 501         s32 ret_val;
 502         u16 data;
 503         bool link;
 504
 505         if (phy->type != e1000_phy_ife) {
 506                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 507                 return ret_val;
 508         }
 509
 510         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 511         if (ret_val)
 512                 return ret_val;
 513
 514         e1000e_phy_force_speed_duplex_setup(hw, &data);
 515
 516         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 517         if (ret_val)
 518                 return ret_val;
 519
 520         /* Disable MDI-X support for 10/100 */
 521         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 522         if (ret_val)
 523                 return ret_val;
 524
 525         data &= ~IFE_PMC_AUTO_MDIX;
 526         data &= ~IFE_PMC_FORCE_MDIX;
 527
 528         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 529         if (ret_val)
 530                 return ret_val;
 531
 532         hw_dbg(hw, "IFE PMC: %X\n", data);
 533
 534         udelay(1);
 535
 536         if (phy->autoneg_wait_to_complete) {
 537                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 538
 539                 ret_val = e1000e_phy_has_link_generic(hw,
 540                                                      PHY_FORCE_LIMIT,
 541                                                      100000,
 542                                                      &link);
 543                 if (ret_val)
 544                         return ret_val;
 545
 546                 if (!link)
 547                         hw_dbg(hw, "Link taking longer than expected.\n");
 548
 549                 /* Try once more */
 550                 ret_val = e1000e_phy_has_link_generic(hw,
 551                                                      PHY_FORCE_LIMIT,
 552                                                      100000,
 553                                                      &link);
 554                 if (ret_val)
 555                         return ret_val;
 556         }
 557
 558         return 0;
 559 }
 560
 561 /**
 562  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  Resets the PHY
 566  *  This is a function pointer entry point called by drivers
 567  *  or other shared routines.
 568  **/
 569 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 570 {
 571         struct e1000_phy_info *phy = &hw->phy;
 572         u32 i;
 573         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 574         s32 ret_val;
 575         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 576         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 577
 578         ret_val = e1000e_phy_hw_reset_generic(hw);
 579         if (ret_val)
 580                 return ret_val;
 581
 582         /*
 583          * Initialize the PHY from the NVM on ICH platforms.  This
 584          * is needed due to an issue where the NVM configuration is
 585          * not properly autoloaded after power transitions.
 586          * Therefore, after each PHY reset, we will load the
 587          * configuration data out of the NVM manually.
 588          */
 589         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 590                 struct e1000_adapter *adapter = hw->adapter;
 591
 592                 /* Check if SW needs configure the PHY */
 593                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 594                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 595                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 596                 else
 597                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 598
 599                 data = er32(FEXTNVM);
 600                 if (!(data & sw_cfg_mask))
 601                         return 0;
 602
 603                 /* Wait for basic configuration completes before proceeding*/
 604                 do {
 605                         data = er32(STATUS);
 606                         data &= E1000_STATUS_LAN_INIT_DONE;
 607                         udelay(100);
 608                 } while ((!data) && --loop);
 609
 610                 /*
 611                  * If basic configuration is incomplete before the above loop
 612                  * count reaches 0, loading the configuration from NVM will
 613                  * leave the PHY in a bad state possibly resulting in no link.
 614                  */
 615                 if (loop == 0) {
 616                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 617                 }
 618
 619                 /* Clear the Init Done bit for the next init event */
 620                 data = er32(STATUS);
 621                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 622                 ew32(STATUS, data);
 623
 624                 /*
 625                  * Make sure HW does not configure LCD from PHY
 626                  * extended configuration before SW configuration
 627                  */
 628                 data = er32(EXTCNF_CTRL);
 629                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 630                         return 0;
 631
 632                 cnf_size = er32(EXTCNF_SIZE);
 633                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 634                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 635                 if (!cnf_size)
 636                         return 0;
 637
 638                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 639                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 640
 641                 /* Configure LCD from extended configuration region. */
 642
 643                 /* cnf_base_addr is in DWORD */
 644                 word_addr = (u16)(cnf_base_addr << 1);
 645
 646                 for (i = 0; i < cnf_size; i++) {
 647                         ret_val = e1000_read_nvm(hw,
 648                                                 (word_addr + i * 2),
 649                                                 1,
 650                                                 &reg_data);
 651                         if (ret_val)
 652                                 return ret_val;
 653
 654                         ret_val = e1000_read_nvm(hw,
 655                                                 (word_addr + i * 2 + 1),
 656                                                 1,
 657                                                 &reg_addr);
 658                         if (ret_val)
 659                                 return ret_val;
 660
 661                         /* Save off the PHY page for future writes. */
 662                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 663                                 phy_page = reg_data;
 664                                 continue;
 665                         }
 666
 667                         reg_addr |= phy_page;
 668
 669                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 670                         if (ret_val)
 671                                 return ret_val;
 672                 }
 673         }
 674
 675         return 0;
 676 }
 677
 678 /**
 679  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 680  *  @hw: pointer to the HW structure
 681  *
 682  *  Populates "phy" structure with various feature states.
 683  *  This function is only called by other family-specific
 684  *  routines.
 685  **/
 686 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 687 {
 688         struct e1000_phy_info *phy = &hw->phy;
 689         s32 ret_val;
 690         u16 data;
 691         bool link;
 692
 693         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 694         if (ret_val)
 695                 return ret_val;
 696
 697         if (!link) {
 698                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 699                 return -E1000_ERR_CONFIG;
 700         }
 701
 702         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 703         if (ret_val)
 704                 return ret_val;
 705         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 706
 707         if (phy->polarity_correction) {
 708                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 709                 if (ret_val)
 710                         return ret_val;
 711         } else {
 712                 /* Polarity is forced */
 713                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 714                                       ? e1000_rev_polarity_reversed
 715                                       : e1000_rev_polarity_normal;
 716         }
 717
 718         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 719         if (ret_val)
 720                 return ret_val;
 721
 722         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 723
 724         /* The following parameters are undefined for 10/100 operation. */
 725         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 726         phy->local_rx = e1000_1000t_rx_status_undefined;
 727         phy->remote_rx = e1000_1000t_rx_status_undefined;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 734  *  @hw: pointer to the HW structure
 735  *
 736  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 737  *  This is a function pointer entry point called by drivers
 738  *  or other shared routines.
 739  **/
 740 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 741 {
 742         switch (hw->phy.type) {
 743         case e1000_phy_ife:
 744                 return e1000_get_phy_info_ife_ich8lan(hw);
 745                 break;
 746         case e1000_phy_igp_3:
 747         case e1000_phy_bm:
 748                 return e1000e_get_phy_info_igp(hw);
 749                 break;
 750         default:
 751                 break;
 752         }
 753
 754         return -E1000_ERR_PHY_TYPE;
 755 }
 756
 757 /**
 758  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 759  *  @hw: pointer to the HW structure
 760  *
 761  *  Polarity is determined on the polarity reversal feature being enabled.
 762  *  This function is only called by other family-specific
 763  *  routines.
 764  **/
 765 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 766 {
 767         struct e1000_phy_info *phy = &hw->phy;
 768         s32 ret_val;
 769         u16 phy_data, offset, mask;
 770
 771         /*
 772          * Polarity is determined based on the reversal feature being enabled.
 773          */
 774         if (phy->polarity_correction) {
 775                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 776                 mask    = IFE_PESC_POLARITY_REVERSED;
 777         } else {
 778                 offset  = IFE_PHY_SPECIAL_CONTROL;
 779                 mask    = IFE_PSC_FORCE_POLARITY;
 780         }
 781
 782         ret_val = e1e_rphy(hw, offset, &phy_data);
 783
 784         if (!ret_val)
 785                 phy->cable_polarity = (phy_data & mask)
 786                                       ? e1000_rev_polarity_reversed
 787                                       : e1000_rev_polarity_normal;
 788
 789         return ret_val;
 790 }
 791
 792 /**
 793  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 794  *  @hw: pointer to the HW structure
 795  *  @active: TRUE to enable LPLU, FALSE to disable
 796  *
 797  *  Sets the LPLU D0 state according to the active flag.  When
 798  *  activating LPLU this function also disables smart speed
 799  *  and vice versa.  LPLU will not be activated unless the
 800  *  device autonegotiation advertisement meets standards of
 801  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 802  *  This is a function pointer entry point only called by
 803  *  PHY setup routines.
 804  **/
 805 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 806 {
 807         struct e1000_phy_info *phy = &hw->phy;
 808         u32 phy_ctrl;
 809         s32 ret_val = 0;
 810         u16 data;
 811
 812         if (phy->type == e1000_phy_ife)
 813                 return ret_val;
 814
 815         phy_ctrl = er32(PHY_CTRL);
 816
 817         if (active) {
 818                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 819                 ew32(PHY_CTRL, phy_ctrl);
 820
 821                 /*
 822                  * Call gig speed drop workaround on LPLU before accessing
 823                  * any PHY registers
 824                  */
 825                 if ((hw->mac.type == e1000_ich8lan) &&
 826                     (hw->phy.type == e1000_phy_igp_3))
 827                         e1000e_gig_downshift_workaround_ich8lan(hw);
 828
 829                 /* When LPLU is enabled, we should disable SmartSpeed */
 830                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 831                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 832                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 833                 if (ret_val)
 834                         return ret_val;
 835         } else {
 836                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 837                 ew32(PHY_CTRL, phy_ctrl);
 838
 839                 /*
 840                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 841                  * during Dx states where the power conservation is most
 842                  * important.  During driver activity we should enable
 843                  * SmartSpeed, so performance is maintained.
 844                  */
 845                 if (phy->smart_speed == e1000_smart_speed_on) {
 846                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 847                                            &data);
 848                         if (ret_val)
 849                                 return ret_val;
 850
 851                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 852                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 853                                            data);
 854                         if (ret_val)
 855                                 return ret_val;
 856                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 857                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 858                                            &data);
 859                         if (ret_val)
 860                                 return ret_val;
 861
 862                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 863                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 864                                            data);
 865                         if (ret_val)
 866                                 return ret_val;
 867                 }
 868         }
 869
 870         return 0;
 871 }
 872
 873 /**
 874  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 875  *  @hw: pointer to the HW structure
 876  *  @active: TRUE to enable LPLU, FALSE to disable
 877  *
 878  *  Sets the LPLU D3 state according to the active flag.  When
 879  *  activating LPLU this function also disables smart speed
 880  *  and vice versa.  LPLU will not be activated unless the
 881  *  device autonegotiation advertisement meets standards of
 882  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 883  *  This is a function pointer entry point only called by
 884  *  PHY setup routines.
 885  **/
 886 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 887 {
 888         struct e1000_phy_info *phy = &hw->phy;
 889         u32 phy_ctrl;
 890         s32 ret_val;
 891         u16 data;
 892
 893         phy_ctrl = er32(PHY_CTRL);
 894
 895         if (!active) {
 896                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 897                 ew32(PHY_CTRL, phy_ctrl);
 898                 /*
 899                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 900                  * during Dx states where the power conservation is most
 901                  * important.  During driver activity we should enable
 902                  * SmartSpeed, so performance is maintained.
 903                  */
 904                 if (phy->smart_speed == e1000_smart_speed_on) {
 905                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 906                                            &data);
 907                         if (ret_val)
 908                                 return ret_val;
 909
 910                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 911                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 912                                            data);
 913                         if (ret_val)
 914                                 return ret_val;
 915                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 916                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 917                                            &data);
 918                         if (ret_val)
 919                                 return ret_val;
 920
 921                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 922                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 923                                            data);
 924                         if (ret_val)
 925                                 return ret_val;
 926                 }
 927         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 928                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 929                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 930                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 931                 ew32(PHY_CTRL, phy_ctrl);
 932
 933                 /*
 934                  * Call gig speed drop workaround on LPLU before accessing
 935                  * any PHY registers
 936                  */
 937                 if ((hw->mac.type == e1000_ich8lan) &&
 938                     (hw->phy.type == e1000_phy_igp_3))
 939                         e1000e_gig_downshift_workaround_ich8lan(hw);
 940
 941                 /* When LPLU is enabled, we should disable SmartSpeed */
 942                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 943                 if (ret_val)
 944                         return ret_val;
 945
 946                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 947                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 948         }
 949
 950         return 0;
 951 }
 952
 953 /**
 954  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 955  *  @hw: pointer to the HW structure
 956  *  @bank:  pointer to the variable that returns the active bank
 957  *
 958  *  Reads signature byte from the NVM using the flash access registers.
 959  **/
 960 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 961 {
 962         struct e1000_nvm_info *nvm = &hw->nvm;
 963         /* flash bank size is in words */
 964         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
 965         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
 966         u8 bank_high_byte = 0;
 967
 968         if (hw->mac.type != e1000_ich10lan) {
 969                 if (er32(EECD) & E1000_EECD_SEC1VAL)
 970                         *bank = 1;
 971                 else
 972                         *bank = 0;
 973         } else {
 974                 /*
 975                  * Make sure the signature for bank 0 is valid,
 976                  * if not check for bank1
 977                  */
 978                 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
 979                 if ((bank_high_byte & 0xC0) == 0x80) {
 980                         *bank = 0;
 981                 } else {
 982                         /*
 983                          * find if segment 1 is valid by verifying
 984                          * bit 15:14 = 10b in word 0x13
 985                          */
 986                         e1000_read_flash_byte_ich8lan(hw,
 987                                                       act_offset + bank1_offset,
 988                                                       &bank_high_byte);
 989
 990                         /* bank1 has a valid signature equivalent to SEC1V */
 991                         if ((bank_high_byte & 0xC0) == 0x80) {
 992                                 *bank = 1;
 993                         } else {
 994                                 hw_dbg(hw, "ERROR: EEPROM not present\n");
 995                                 return -E1000_ERR_NVM;
 996                         }
 997                 }
 998         }
 999
1000         return 0;
1001 }
1002
1003 /**
1004  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1005  *  @hw: pointer to the HW structure
1006  *  @offset: The offset (in bytes) of the word(s) to read.
1007  *  @words: Size of data to read in words
1008  *  @data: Pointer to the word(s) to read at offset.
1009  *
1010  *  Reads a word(s) from the NVM using the flash access registers.
1011  **/
1012 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1013                                   u16 *data)
1014 {
1015         struct e1000_nvm_info *nvm = &hw->nvm;
1016         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1017         u32 act_offset;
1018         s32 ret_val;
1019         u32 bank = 0;
1020         u16 i, word;
1021
1022         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1023             (words == 0)) {
1024                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1025                 return -E1000_ERR_NVM;
1026         }
1027
1028         ret_val = e1000_acquire_swflag_ich8lan(hw);
1029         if (ret_val)
1030                 return ret_val;
1031
1032         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1033         if (ret_val)
1034                 return ret_val;
1035
1036         act_offset = (bank) ? nvm->flash_bank_size : 0;
1037         act_offset += offset;
1038
1039         for (i = 0; i < words; i++) {
1040                 if ((dev_spec->shadow_ram) &&
1041                     (dev_spec->shadow_ram[offset+i].modified)) {
1042                         data[i] = dev_spec->shadow_ram[offset+i].value;
1043                 } else {
1044                         ret_val = e1000_read_flash_word_ich8lan(hw,
1045                                                                 act_offset + i,
1046                                                                 &word);
1047                         if (ret_val)
1048                                 break;
1049                         data[i] = word;
1050                 }
1051         }
1052
1053         e1000_release_swflag_ich8lan(hw);
1054
1055         return ret_val;
1056 }
1057
1058 /**
1059  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1060  *  @hw: pointer to the HW structure
1061  *
1062  *  This function does initial flash setup so that a new read/write/erase cycle
1063  *  can be started.
1064  **/
1065 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1066 {
1067         union ich8_hws_flash_status hsfsts;
1068         s32 ret_val = -E1000_ERR_NVM;
1069         s32 i = 0;
1070
1071         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1072
1073         /* Check if the flash descriptor is valid */
1074         if (hsfsts.hsf_status.fldesvalid == 0) {
1075                 hw_dbg(hw, "Flash descriptor invalid.  "
1076                          "SW Sequencing must be used.");
1077                 return -E1000_ERR_NVM;
1078         }
1079
1080         /* Clear FCERR and DAEL in hw status by writing 1 */
1081         hsfsts.hsf_status.flcerr = 1;
1082         hsfsts.hsf_status.dael = 1;
1083
1084         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1085
1086         /*
1087          * Either we should have a hardware SPI cycle in progress
1088          * bit to check against, in order to start a new cycle or
1089          * FDONE bit should be changed in the hardware so that it
1090          * is 1 after hardware reset, which can then be used as an
1091          * indication whether a cycle is in progress or has been
1092          * completed.
1093          */
1094
1095         if (hsfsts.hsf_status.flcinprog == 0) {
1096                 /*
1097                  * There is no cycle running at present,
1098                  * so we can start a cycle
1099                  * Begin by setting Flash Cycle Done.
1100                  */
1101                 hsfsts.hsf_status.flcdone = 1;
1102                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1103                 ret_val = 0;
1104         } else {
1105                 /*
1106                  * otherwise poll for sometime so the current
1107                  * cycle has a chance to end before giving up.
1108                  */
1109                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1110                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1111                         if (hsfsts.hsf_status.flcinprog == 0) {
1112                                 ret_val = 0;
1113                                 break;
1114                         }
1115                         udelay(1);
1116                 }
1117                 if (ret_val == 0) {
1118                         /*
1119                          * Successful in waiting for previous cycle to timeout,
1120                          * now set the Flash Cycle Done.
1121                          */
1122                         hsfsts.hsf_status.flcdone = 1;
1123                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1124                 } else {
1125                         hw_dbg(hw, "Flash controller busy, cannot get access");
1126                 }
1127         }
1128
1129         return ret_val;
1130 }
1131
1132 /**
1133  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1134  *  @hw: pointer to the HW structure
1135  *  @timeout: maximum time to wait for completion
1136  *
1137  *  This function starts a flash cycle and waits for its completion.
1138  **/
1139 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1140 {
1141         union ich8_hws_flash_ctrl hsflctl;
1142         union ich8_hws_flash_status hsfsts;
1143         s32 ret_val = -E1000_ERR_NVM;
1144         u32 i = 0;
1145
1146         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1147         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1148         hsflctl.hsf_ctrl.flcgo = 1;
1149         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1150
1151         /* wait till FDONE bit is set to 1 */
1152         do {
1153                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1154                 if (hsfsts.hsf_status.flcdone == 1)
1155                         break;
1156                 udelay(1);
1157         } while (i++ < timeout);
1158
1159         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1160                 return 0;
1161
1162         return ret_val;
1163 }
1164
1165 /**
1166  *  e1000_read_flash_word_ich8lan - Read word from flash
1167  *  @hw: pointer to the HW structure
1168  *  @offset: offset to data location
1169  *  @data: pointer to the location for storing the data
1170  *
1171  *  Reads the flash word at offset into data.  Offset is converted
1172  *  to bytes before read.
1173  **/
1174 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1175                                          u16 *data)
1176 {
1177         /* Must convert offset into bytes. */
1178         offset <<= 1;
1179
1180         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1181 }
1182
1183 /**
1184  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1185  *  @hw: pointer to the HW structure
1186  *  @offset: The offset of the byte to read.
1187  *  @data: Pointer to a byte to store the value read.
1188  *
1189  *  Reads a single byte from the NVM using the flash access registers.
1190  **/
1191 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1192                                          u8 *data)
1193 {
1194         s32 ret_val;
1195         u16 word = 0;
1196
1197         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1198         if (ret_val)
1199                 return ret_val;
1200
1201         *data = (u8)word;
1202
1203         return 0;
1204 }
1205
1206 /**
1207  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1208  *  @hw: pointer to the HW structure
1209  *  @offset: The offset (in bytes) of the byte or word to read.
1210  *  @size: Size of data to read, 1=byte 2=word
1211  *  @data: Pointer to the word to store the value read.
1212  *
1213  *  Reads a byte or word from the NVM using the flash access registers.
1214  **/
1215 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1216                                          u8 size, u16 *data)
1217 {
1218         union ich8_hws_flash_status hsfsts;
1219         union ich8_hws_flash_ctrl hsflctl;
1220         u32 flash_linear_addr;
1221         u32 flash_data = 0;
1222         s32 ret_val = -E1000_ERR_NVM;
1223         u8 count = 0;
1224
1225         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1226                 return -E1000_ERR_NVM;
1227
1228         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1229                             hw->nvm.flash_base_addr;
1230
1231         do {
1232                 udelay(1);
1233                 /* Steps */
1234                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1235                 if (ret_val != 0)
1236                         break;
1237
1238                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1239                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1240                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1241                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1242                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1243
1244                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1245
1246                 ret_val = e1000_flash_cycle_ich8lan(hw,
1247                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1248
1249                 /*
1250                  * Check if FCERR is set to 1, if set to 1, clear it
1251                  * and try the whole sequence a few more times, else
1252                  * read in (shift in) the Flash Data0, the order is
1253                  * least significant byte first msb to lsb
1254                  */
1255                 if (ret_val == 0) {
1256                         flash_data = er32flash(ICH_FLASH_FDATA0);
1257                         if (size == 1) {
1258                                 *data = (u8)(flash_data & 0x000000FF);
1259                         } else if (size == 2) {
1260                                 *data = (u16)(flash_data & 0x0000FFFF);
1261                         }
1262                         break;
1263                 } else {
1264                         /*
1265                          * If we've gotten here, then things are probably
1266                          * completely hosed, but if the error condition is
1267                          * detected, it won't hurt to give it another try...
1268                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1269                          */
1270                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1271                         if (hsfsts.hsf_status.flcerr == 1) {
1272                                 /* Repeat for some time before giving up. */
1273                                 continue;
1274                         } else if (hsfsts.hsf_status.flcdone == 0) {
1275                                 hw_dbg(hw, "Timeout error - flash cycle "
1276                                          "did not complete.");
1277                                 break;
1278                         }
1279                 }
1280         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1281
1282         return ret_val;
1283 }
1284
1285 /**
1286  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1287  *  @hw: pointer to the HW structure
1288  *  @offset: The offset (in bytes) of the word(s) to write.
1289  *  @words: Size of data to write in words
1290  *  @data: Pointer to the word(s) to write at offset.
1291  *
1292  *  Writes a byte or word to the NVM using the flash access registers.
1293  **/
1294 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1295                                    u16 *data)
1296 {
1297         struct e1000_nvm_info *nvm = &hw->nvm;
1298         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1299         s32 ret_val;
1300         u16 i;
1301
1302         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1303             (words == 0)) {
1304                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1305                 return -E1000_ERR_NVM;
1306         }
1307
1308         ret_val = e1000_acquire_swflag_ich8lan(hw);
1309         if (ret_val)
1310                 return ret_val;
1311
1312         for (i = 0; i < words; i++) {
1313                 dev_spec->shadow_ram[offset+i].modified = 1;
1314                 dev_spec->shadow_ram[offset+i].value = data[i];
1315         }
1316
1317         e1000_release_swflag_ich8lan(hw);
1318
1319         return 0;
1320 }
1321
1322 /**
1323  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1324  *  @hw: pointer to the HW structure
1325  *
1326  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1327  *  which writes the checksum to the shadow ram.  The changes in the shadow
1328  *  ram are then committed to the EEPROM by processing each bank at a time
1329  *  checking for the modified bit and writing only the pending changes.
1330  *  After a successful commit, the shadow ram is cleared and is ready for
1331  *  future writes.
1332  **/
1333 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1334 {
1335         struct e1000_nvm_info *nvm = &hw->nvm;
1336         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1337         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1338         s32 ret_val;
1339         u16 data;
1340
1341         ret_val = e1000e_update_nvm_checksum_generic(hw);
1342         if (ret_val)
1343                 return ret_val;
1344
1345         if (nvm->type != e1000_nvm_flash_sw)
1346                 return ret_val;
1347
1348         ret_val = e1000_acquire_swflag_ich8lan(hw);
1349         if (ret_val)
1350                 return ret_val;
1351
1352         /*
1353          * We're writing to the opposite bank so if we're on bank 1,
1354          * write to bank 0 etc.  We also need to erase the segment that
1355          * is going to be written
1356          */
1357         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1358         if (ret_val)
1359                 return ret_val;
1360
1361         if (bank == 0) {
1362                 new_bank_offset = nvm->flash_bank_size;
1363                 old_bank_offset = 0;
1364                 e1000_erase_flash_bank_ich8lan(hw, 1);
1365         } else {
1366                 old_bank_offset = nvm->flash_bank_size;
1367                 new_bank_offset = 0;
1368                 e1000_erase_flash_bank_ich8lan(hw, 0);
1369         }
1370
1371         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1372                 /*
1373                  * Determine whether to write the value stored
1374                  * in the other NVM bank or a modified value stored
1375                  * in the shadow RAM
1376                  */
1377                 if (dev_spec->shadow_ram[i].modified) {
1378                         data = dev_spec->shadow_ram[i].value;
1379                 } else {
1380                         e1000_read_flash_word_ich8lan(hw,
1381                                                       i + old_bank_offset,
1382                                                       &data);
1383                 }
1384
1385                 /*
1386                  * If the word is 0x13, then make sure the signature bits
1387                  * (15:14) are 11b until the commit has completed.
1388                  * This will allow us to write 10b which indicates the
1389                  * signature is valid.  We want to do this after the write
1390                  * has completed so that we don't mark the segment valid
1391                  * while the write is still in progress
1392                  */
1393                 if (i == E1000_ICH_NVM_SIG_WORD)
1394                         data |= E1000_ICH_NVM_SIG_MASK;
1395
1396                 /* Convert offset to bytes. */
1397                 act_offset = (i + new_bank_offset) << 1;
1398
1399                 udelay(100);
1400                 /* Write the bytes to the new bank. */
1401                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1402                                                                act_offset,
1403                                                                (u8)data);
1404                 if (ret_val)
1405                         break;
1406
1407                 udelay(100);
1408                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1409                                                           act_offset + 1,
1410                                                           (u8)(data >> 8));
1411                 if (ret_val)
1412                         break;
1413         }
1414
1415         /*
1416          * Don't bother writing the segment valid bits if sector
1417          * programming failed.
1418          */
1419         if (ret_val) {
1420                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1421                 hw_dbg(hw, "Flash commit failed.\n");
1422                 e1000_release_swflag_ich8lan(hw);
1423                 return ret_val;
1424         }
1425
1426         /*
1427          * Finally validate the new segment by setting bit 15:14
1428          * to 10b in word 0x13 , this can be done without an
1429          * erase as well since these bits are 11 to start with
1430          * and we need to change bit 14 to 0b
1431          */
1432         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1433         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1434         data &= 0xBFFF;
1435         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1436                                                        act_offset * 2 + 1,
1437                                                        (u8)(data >> 8));
1438         if (ret_val) {
1439                 e1000_release_swflag_ich8lan(hw);
1440                 return ret_val;
1441         }
1442
1443         /*
1444          * And invalidate the previously valid segment by setting
1445          * its signature word (0x13) high_byte to 0b. This can be
1446          * done without an erase because flash erase sets all bits
1447          * to 1's. We can write 1's to 0's without an erase
1448          */
1449         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1450         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1451         if (ret_val) {
1452                 e1000_release_swflag_ich8lan(hw);
1453                 return ret_val;
1454         }
1455
1456         /* Great!  Everything worked, we can now clear the cached entries. */
1457         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1458                 dev_spec->shadow_ram[i].modified = 0;
1459                 dev_spec->shadow_ram[i].value = 0xFFFF;
1460         }
1461
1462         e1000_release_swflag_ich8lan(hw);
1463
1464         /*
1465          * Reload the EEPROM, or else modifications will not appear
1466          * until after the next adapter reset.
1467          */
1468         e1000e_reload_nvm(hw);
1469         msleep(10);
1470
1471         return ret_val;
1472 }
1473
1474 /**
1475  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1476  *  @hw: pointer to the HW structure
1477  *
1478  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1479  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1480  *  calculated, in which case we need to calculate the checksum and set bit 6.
1481  **/
1482 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1483 {
1484         s32 ret_val;
1485         u16 data;
1486
1487         /*
1488          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1489          * needs to be fixed.  This bit is an indication that the NVM
1490          * was prepared by OEM software and did not calculate the
1491          * checksum...a likely scenario.
1492          */
1493         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1494         if (ret_val)
1495                 return ret_val;
1496
1497         if ((data & 0x40) == 0) {
1498                 data |= 0x40;
1499                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1500                 if (ret_val)
1501                         return ret_val;
1502                 ret_val = e1000e_update_nvm_checksum(hw);
1503                 if (ret_val)
1504                         return ret_val;
1505         }
1506
1507         return e1000e_validate_nvm_checksum_generic(hw);
1508 }
1509
1510 /**
1511  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1512  *  @hw: pointer to the HW structure
1513  *
1514  *  To prevent malicious write/erase of the NVM, set it to be read-only
1515  *  so that the hardware ignores all write/erase cycles of the NVM via
1516  *  the flash control registers.  The shadow-ram copy of the NVM will
1517  *  still be updated, however any updates to this copy will not stick
1518  *  across driver reloads.
1519  **/
1520 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1521 {
1522         union ich8_flash_protected_range pr0;
1523         union ich8_hws_flash_status hsfsts;
1524         u32 gfpreg;
1525         s32 ret_val;
1526
1527         ret_val = e1000_acquire_swflag_ich8lan(hw);
1528         if (ret_val)
1529                 return;
1530
1531         gfpreg = er32flash(ICH_FLASH_GFPREG);
1532
1533         /* Write-protect GbE Sector of NVM */
1534         pr0.regval = er32flash(ICH_FLASH_PR0);
1535         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1536         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1537         pr0.range.wpe = true;
1538         ew32flash(ICH_FLASH_PR0, pr0.regval);
1539
1540         /*
1541          * Lock down a subset of GbE Flash Control Registers, e.g.
1542          * PR0 to prevent the write-protection from being lifted.
1543          * Once FLOCKDN is set, the registers protected by it cannot
1544          * be written until FLOCKDN is cleared by a hardware reset.
1545          */
1546         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1547         hsfsts.hsf_status.flockdn = true;
1548         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1549
1550         e1000_release_swflag_ich8lan(hw);
1551 }
1552
1553 /**
1554  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1555  *  @hw: pointer to the HW structure
1556  *  @offset: The offset (in bytes) of the byte/word to read.
1557  *  @size: Size of data to read, 1=byte 2=word
1558  *  @data: The byte(s) to write to the NVM.
1559  *
1560  *  Writes one/two bytes to the NVM using the flash access registers.
1561  **/
1562 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1563                                           u8 size, u16 data)
1564 {
1565         union ich8_hws_flash_status hsfsts;
1566         union ich8_hws_flash_ctrl hsflctl;
1567         u32 flash_linear_addr;
1568         u32 flash_data = 0;
1569         s32 ret_val;
1570         u8 count = 0;
1571
1572         if (size < 1 || size > 2 || data > size * 0xff ||
1573             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1574                 return -E1000_ERR_NVM;
1575
1576         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1577                             hw->nvm.flash_base_addr;
1578
1579         do {
1580                 udelay(1);
1581                 /* Steps */
1582                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1583                 if (ret_val)
1584                         break;
1585
1586                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1587                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1588                 hsflctl.hsf_ctrl.fldbcount = size -1;
1589                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1590                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1591
1592                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1593
1594                 if (size == 1)
1595                         flash_data = (u32)data & 0x00FF;
1596                 else
1597                         flash_data = (u32)data;
1598
1599                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1600
1601                 /*
1602                  * check if FCERR is set to 1 , if set to 1, clear it
1603                  * and try the whole sequence a few more times else done
1604                  */
1605                 ret_val = e1000_flash_cycle_ich8lan(hw,
1606                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1607                 if (!ret_val)
1608                         break;
1609
1610                 /*
1611                  * If we're here, then things are most likely
1612                  * completely hosed, but if the error condition
1613                  * is detected, it won't hurt to give it another
1614                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1615                  */
1616                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1617                 if (hsfsts.hsf_status.flcerr == 1)
1618                         /* Repeat for some time before giving up. */
1619                         continue;
1620                 if (hsfsts.hsf_status.flcdone == 0) {
1621                         hw_dbg(hw, "Timeout error - flash cycle "
1622                                  "did not complete.");
1623                         break;
1624                 }
1625         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1626
1627         return ret_val;
1628 }
1629
1630 /**
1631  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1632  *  @hw: pointer to the HW structure
1633  *  @offset: The index of the byte to read.
1634  *  @data: The byte to write to the NVM.
1635  *
1636  *  Writes a single byte to the NVM using the flash access registers.
1637  **/
1638 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1639                                           u8 data)
1640 {
1641         u16 word = (u16)data;
1642
1643         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1644 }
1645
1646 /**
1647  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1648  *  @hw: pointer to the HW structure
1649  *  @offset: The offset of the byte to write.
1650  *  @byte: The byte to write to the NVM.
1651  *
1652  *  Writes a single byte to the NVM using the flash access registers.
1653  *  Goes through a retry algorithm before giving up.
1654  **/
1655 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1656                                                 u32 offset, u8 byte)
1657 {
1658         s32 ret_val;
1659         u16 program_retries;
1660
1661         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1662         if (!ret_val)
1663                 return ret_val;
1664
1665         for (program_retries = 0; program_retries < 100; program_retries++) {
1666                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1667                 udelay(100);
1668                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1669                 if (!ret_val)
1670                         break;
1671         }
1672         if (program_retries == 100)
1673                 return -E1000_ERR_NVM;
1674
1675         return 0;
1676 }
1677
1678 /**
1679  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1680  *  @hw: pointer to the HW structure
1681  *  @bank: 0 for first bank, 1 for second bank, etc.
1682  *
1683  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1684  *  bank N is 4096 * N + flash_reg_addr.
1685  **/
1686 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1687 {
1688         struct e1000_nvm_info *nvm = &hw->nvm;
1689         union ich8_hws_flash_status hsfsts;
1690         union ich8_hws_flash_ctrl hsflctl;
1691         u32 flash_linear_addr;
1692         /* bank size is in 16bit words - adjust to bytes */
1693         u32 flash_bank_size = nvm->flash_bank_size * 2;
1694         s32 ret_val;
1695         s32 count = 0;
1696         s32 iteration;
1697         s32 sector_size;
1698         s32 j;
1699
1700         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1701
1702         /*
1703          * Determine HW Sector size: Read BERASE bits of hw flash status
1704          * register
1705          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1706          *     consecutive sectors.  The start index for the nth Hw sector
1707          *     can be calculated as = bank * 4096 + n * 256
1708          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1709          *     The start index for the nth Hw sector can be calculated
1710          *     as = bank * 4096
1711          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1712          *     (ich9 only, otherwise error condition)
1713          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1714          */
1715         switch (hsfsts.hsf_status.berasesz) {
1716         case 0:
1717                 /* Hw sector size 256 */
1718                 sector_size = ICH_FLASH_SEG_SIZE_256;
1719                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1720                 break;
1721         case 1:
1722                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1723                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1724                 break;
1725         case 2:
1726                 if (hw->mac.type == e1000_ich9lan) {
1727                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1728                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1729                 } else {
1730                         return -E1000_ERR_NVM;
1731                 }
1732                 break;
1733         case 3:
1734                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1735                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1736                 break;
1737         default:
1738                 return -E1000_ERR_NVM;
1739         }
1740
1741         /* Start with the base address, then add the sector offset. */
1742         flash_linear_addr = hw->nvm.flash_base_addr;
1743         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1744
1745         for (j = 0; j < iteration ; j++) {
1746                 do {
1747                         /* Steps */
1748                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1749                         if (ret_val)
1750                                 return ret_val;
1751
1752                         /*
1753                          * Write a value 11 (block Erase) in Flash
1754                          * Cycle field in hw flash control
1755                          */
1756                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1757                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1758                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1759
1760                         /*
1761                          * Write the last 24 bits of an index within the
1762                          * block into Flash Linear address field in Flash
1763                          * Address.
1764                          */
1765                         flash_linear_addr += (j * sector_size);
1766                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1767
1768                         ret_val = e1000_flash_cycle_ich8lan(hw,
1769                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1770                         if (ret_val == 0)
1771                                 break;
1772
1773                         /*
1774                          * Check if FCERR is set to 1.  If 1,
1775                          * clear it and try the whole sequence
1776                          * a few more times else Done
1777                          */
1778                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1779                         if (hsfsts.hsf_status.flcerr == 1)
1780                                 /* repeat for some time before giving up */
1781                                 continue;
1782                         else if (hsfsts.hsf_status.flcdone == 0)
1783                                 return ret_val;
1784                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1785         }
1786
1787         return 0;
1788 }
1789
1790 /**
1791  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1792  *  @hw: pointer to the HW structure
1793  *  @data: Pointer to the LED settings
1794  *
1795  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1796  *  settings is all 0's or F's, set the LED default to a valid LED default
1797  *  setting.
1798  **/
1799 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1800 {
1801         s32 ret_val;
1802
1803         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1804         if (ret_val) {
1805                 hw_dbg(hw, "NVM Read Error\n");
1806                 return ret_val;
1807         }
1808
1809         if (*data == ID_LED_RESERVED_0000 ||
1810             *data == ID_LED_RESERVED_FFFF)
1811                 *data = ID_LED_DEFAULT_ICH8LAN;
1812
1813         return 0;
1814 }
1815
1816 /**
1817  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1818  *  @hw: pointer to the HW structure
1819  *
1820  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1821  *  register, so the the bus width is hard coded.
1822  **/
1823 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1824 {
1825         struct e1000_bus_info *bus = &hw->bus;
1826         s32 ret_val;
1827
1828         ret_val = e1000e_get_bus_info_pcie(hw);
1829
1830         /*
1831          * ICH devices are "PCI Express"-ish.  They have
1832          * a configuration space, but do not contain
1833          * PCI Express Capability registers, so bus width
1834          * must be hardcoded.
1835          */
1836         if (bus->width == e1000_bus_width_unknown)
1837                 bus->width = e1000_bus_width_pcie_x1;
1838
1839         return ret_val;
1840 }
1841
1842 /**
1843  *  e1000_reset_hw_ich8lan - Reset the hardware
1844  *  @hw: pointer to the HW structure
1845  *
1846  *  Does a full reset of the hardware which includes a reset of the PHY and
1847  *  MAC.
1848  **/
1849 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1850 {
1851         u32 ctrl, icr, kab;
1852         s32 ret_val;
1853
1854         /*
1855          * Prevent the PCI-E bus from sticking if there is no TLP connection
1856          * on the last TLP read/write transaction when MAC is reset.
1857          */
1858         ret_val = e1000e_disable_pcie_master(hw);
1859         if (ret_val) {
1860                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1861         }
1862
1863         hw_dbg(hw, "Masking off all interrupts\n");
1864         ew32(IMC, 0xffffffff);
1865
1866         /*
1867          * Disable the Transmit and Receive units.  Then delay to allow
1868          * any pending transactions to complete before we hit the MAC
1869          * with the global reset.
1870          */
1871         ew32(RCTL, 0);
1872         ew32(TCTL, E1000_TCTL_PSP);
1873         e1e_flush();
1874
1875         msleep(10);
1876
1877         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1878         if (hw->mac.type == e1000_ich8lan) {
1879                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1880                 ew32(PBA, E1000_PBA_8K);
1881                 /* Set Packet Buffer Size to 16k. */
1882                 ew32(PBS, E1000_PBS_16K);
1883         }
1884
1885         ctrl = er32(CTRL);
1886
1887         if (!e1000_check_reset_block(hw)) {
1888                 /*
1889                  * PHY HW reset requires MAC CORE reset at the same
1890                  * time to make sure the interface between MAC and the
1891                  * external PHY is reset.
1892                  */
1893                 ctrl |= E1000_CTRL_PHY_RST;
1894         }
1895         ret_val = e1000_acquire_swflag_ich8lan(hw);
1896         hw_dbg(hw, "Issuing a global reset to ich8lan");
1897         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1898         msleep(20);
1899
1900         /* release the swflag because it is not reset by hardware reset */
1901         e1000_release_swflag_ich8lan(hw);
1902
1903         ret_val = e1000e_get_auto_rd_done(hw);
1904         if (ret_val) {
1905                 /*
1906                  * When auto config read does not complete, do not
1907                  * return with an error. This can happen in situations
1908                  * where there is no eeprom and prevents getting link.
1909                  */
1910                 hw_dbg(hw, "Auto Read Done did not complete\n");
1911         }
1912
1913         ew32(IMC, 0xffffffff);
1914         icr = er32(ICR);
1915
1916         kab = er32(KABGTXD);
1917         kab |= E1000_KABGTXD_BGSQLBIAS;
1918         ew32(KABGTXD, kab);
1919
1920         return ret_val;
1921 }
1922
1923 /**
1924  *  e1000_init_hw_ich8lan - Initialize the hardware
1925  *  @hw: pointer to the HW structure
1926  *
1927  *  Prepares the hardware for transmit and receive by doing the following:
1928  *   - initialize hardware bits
1929  *   - initialize LED identification
1930  *   - setup receive address registers
1931  *   - setup flow control
1932  *   - setup transmit descriptors
1933  *   - clear statistics
1934  **/
1935 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1936 {
1937         struct e1000_mac_info *mac = &hw->mac;
1938         u32 ctrl_ext, txdctl, snoop;
1939         s32 ret_val;
1940         u16 i;
1941
1942         e1000_initialize_hw_bits_ich8lan(hw);
1943
1944         /* Initialize identification LED */
1945         ret_val = e1000e_id_led_init(hw);
1946         if (ret_val) {
1947                 hw_dbg(hw, "Error initializing identification LED\n");
1948                 return ret_val;
1949         }
1950
1951         /* Setup the receive address. */
1952         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1953
1954         /* Zero out the Multicast HASH table */
1955         hw_dbg(hw, "Zeroing the MTA\n");
1956         for (i = 0; i < mac->mta_reg_count; i++)
1957                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1958
1959         /* Setup link and flow control */
1960         ret_val = e1000_setup_link_ich8lan(hw);
1961
1962         /* Set the transmit descriptor write-back policy for both queues */
1963         txdctl = er32(TXDCTL(0));
1964         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1965                  E1000_TXDCTL_FULL_TX_DESC_WB;
1966         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1967                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1968         ew32(TXDCTL(0), txdctl);
1969         txdctl = er32(TXDCTL(1));
1970         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1971                  E1000_TXDCTL_FULL_TX_DESC_WB;
1972         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1973                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1974         ew32(TXDCTL(1), txdctl);
1975
1976         /*
1977          * ICH8 has opposite polarity of no_snoop bits.
1978          * By default, we should use snoop behavior.
1979          */
1980         if (mac->type == e1000_ich8lan)
1981                 snoop = PCIE_ICH8_SNOOP_ALL;
1982         else
1983                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1984         e1000e_set_pcie_no_snoop(hw, snoop);
1985
1986         ctrl_ext = er32(CTRL_EXT);
1987         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1988         ew32(CTRL_EXT, ctrl_ext);
1989
1990         /*
1991          * Clear all of the statistics registers (clear on read).  It is
1992          * important that we do this after we have tried to establish link
1993          * because the symbol error count will increment wildly if there
1994          * is no link.
1995          */
1996         e1000_clear_hw_cntrs_ich8lan(hw);
1997
1998         return 0;
1999 }
2000 /**
2001  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2002  *  @hw: pointer to the HW structure
2003  *
2004  *  Sets/Clears required hardware bits necessary for correctly setting up the
2005  *  hardware for transmit and receive.
2006  **/
2007 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2008 {
2009         u32 reg;
2010
2011         /* Extended Device Control */
2012         reg = er32(CTRL_EXT);
2013         reg |= (1 << 22);
2014         ew32(CTRL_EXT, reg);
2015
2016         /* Transmit Descriptor Control 0 */
2017         reg = er32(TXDCTL(0));
2018         reg |= (1 << 22);
2019         ew32(TXDCTL(0), reg);
2020
2021         /* Transmit Descriptor Control 1 */
2022         reg = er32(TXDCTL(1));
2023         reg |= (1 << 22);
2024         ew32(TXDCTL(1), reg);
2025
2026         /* Transmit Arbitration Control 0 */
2027         reg = er32(TARC(0));
2028         if (hw->mac.type == e1000_ich8lan)
2029                 reg |= (1 << 28) | (1 << 29);
2030         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2031         ew32(TARC(0), reg);
2032
2033         /* Transmit Arbitration Control 1 */
2034         reg = er32(TARC(1));
2035         if (er32(TCTL) & E1000_TCTL_MULR)
2036                 reg &= ~(1 << 28);
2037         else
2038                 reg |= (1 << 28);
2039         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2040         ew32(TARC(1), reg);
2041
2042         /* Device Status */
2043         if (hw->mac.type == e1000_ich8lan) {
2044                 reg = er32(STATUS);
2045                 reg &= ~(1 << 31);
2046                 ew32(STATUS, reg);
2047         }
2048 }
2049
2050 /**
2051  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2052  *  @hw: pointer to the HW structure
2053  *
2054  *  Determines which flow control settings to use, then configures flow
2055  *  control.  Calls the appropriate media-specific link configuration
2056  *  function.  Assuming the adapter has a valid link partner, a valid link
2057  *  should be established.  Assumes the hardware has previously been reset
2058  *  and the transmitter and receiver are not enabled.
2059  **/
2060 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2061 {
2062         s32 ret_val;
2063
2064         if (e1000_check_reset_block(hw))
2065                 return 0;
2066
2067         /*
2068          * ICH parts do not have a word in the NVM to determine
2069          * the default flow control setting, so we explicitly
2070          * set it to full.
2071          */
2072         if (hw->fc.type == e1000_fc_default)
2073                 hw->fc.type = e1000_fc_full;
2074
2075         hw->fc.original_type = hw->fc.type;
2076
2077         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
2078
2079         /* Continue to configure the copper link. */
2080         ret_val = e1000_setup_copper_link_ich8lan(hw);
2081         if (ret_val)
2082                 return ret_val;
2083
2084         ew32(FCTTV, hw->fc.pause_time);
2085
2086         return e1000e_set_fc_watermarks(hw);
2087 }
2088
2089 /**
2090  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2091  *  @hw: pointer to the HW structure
2092  *
2093  *  Configures the kumeran interface to the PHY to wait the appropriate time
2094  *  when polling the PHY, then call the generic setup_copper_link to finish
2095  *  configuring the copper link.
2096  **/
2097 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2098 {
2099         u32 ctrl;
2100         s32 ret_val;
2101         u16 reg_data;
2102
2103         ctrl = er32(CTRL);
2104         ctrl |= E1000_CTRL_SLU;
2105         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2106         ew32(CTRL, ctrl);
2107
2108         /*
2109          * Set the mac to wait the maximum time between each iteration
2110          * and increase the max iterations when polling the phy;
2111          * this fixes erroneous timeouts at 10Mbps.
2112          */
2113         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2114         if (ret_val)
2115                 return ret_val;
2116         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2117         if (ret_val)
2118                 return ret_val;
2119         reg_data |= 0x3F;
2120         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2121         if (ret_val)
2122                 return ret_val;
2123
2124         if (hw->phy.type == e1000_phy_igp_3) {
2125                 ret_val = e1000e_copper_link_setup_igp(hw);
2126                 if (ret_val)
2127                         return ret_val;
2128         } else if (hw->phy.type == e1000_phy_bm) {
2129                 ret_val = e1000e_copper_link_setup_m88(hw);
2130                 if (ret_val)
2131                         return ret_val;
2132         }
2133
2134         if (hw->phy.type == e1000_phy_ife) {
2135                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2136                 if (ret_val)
2137                         return ret_val;
2138
2139                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2140
2141                 switch (hw->phy.mdix) {
2142                 case 1:
2143                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2144                         break;
2145                 case 2:
2146                         reg_data |= IFE_PMC_FORCE_MDIX;
2147                         break;
2148                 case 0:
2149                 default:
2150                         reg_data |= IFE_PMC_AUTO_MDIX;
2151                         break;
2152                 }
2153                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2154                 if (ret_val)
2155                         return ret_val;
2156         }
2157         return e1000e_setup_copper_link(hw);
2158 }
2159
2160 /**
2161  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2162  *  @hw: pointer to the HW structure
2163  *  @speed: pointer to store current link speed
2164  *  @duplex: pointer to store the current link duplex
2165  *
2166  *  Calls the generic get_speed_and_duplex to retrieve the current link
2167  *  information and then calls the Kumeran lock loss workaround for links at
2168  *  gigabit speeds.
2169  **/
2170 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2171                                           u16 *duplex)
2172 {
2173         s32 ret_val;
2174
2175         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2176         if (ret_val)
2177                 return ret_val;
2178
2179         if ((hw->mac.type == e1000_ich8lan) &&
2180             (hw->phy.type == e1000_phy_igp_3) &&
2181             (*speed == SPEED_1000)) {
2182                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2183         }
2184
2185         return ret_val;
2186 }
2187
2188 /**
2189  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2190  *  @hw: pointer to the HW structure
2191  *
2192  *  Work-around for 82566 Kumeran PCS lock loss:
2193  *  On link status change (i.e. PCI reset, speed change) and link is up and
2194  *  speed is gigabit-
2195  *    0) if workaround is optionally disabled do nothing
2196  *    1) wait 1ms for Kumeran link to come up
2197  *    2) check Kumeran Diagnostic register PCS lock loss bit
2198  *    3) if not set the link is locked (all is good), otherwise...
2199  *    4) reset the PHY
2200  *    5) repeat up to 10 times
2201  *  Note: this is only called for IGP3 copper when speed is 1gb.
2202  **/
2203 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2204 {
2205         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2206         u32 phy_ctrl;
2207         s32 ret_val;
2208         u16 i, data;
2209         bool link;
2210
2211         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2212                 return 0;
2213
2214         /*
2215          * Make sure link is up before proceeding.  If not just return.
2216          * Attempting this while link is negotiating fouled up link
2217          * stability
2218          */
2219         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2220         if (!link)
2221                 return 0;
2222
2223         for (i = 0; i < 10; i++) {
2224                 /* read once to clear */
2225                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2226                 if (ret_val)
2227                         return ret_val;
2228                 /* and again to get new status */
2229                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2230                 if (ret_val)
2231                         return ret_val;
2232
2233                 /* check for PCS lock */
2234                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2235                         return 0;
2236
2237                 /* Issue PHY reset */
2238                 e1000_phy_hw_reset(hw);
2239                 mdelay(5);
2240         }
2241         /* Disable GigE link negotiation */
2242         phy_ctrl = er32(PHY_CTRL);
2243         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2244                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2245         ew32(PHY_CTRL, phy_ctrl);
2246
2247         /*
2248          * Call gig speed drop workaround on Gig disable before accessing
2249          * any PHY registers
2250          */
2251         e1000e_gig_downshift_workaround_ich8lan(hw);
2252
2253         /* unable to acquire PCS lock */
2254         return -E1000_ERR_PHY;
2255 }
2256
2257 /**
2258  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2259  *  @hw: pointer to the HW structure
2260  *  @state: boolean value used to set the current Kumeran workaround state
2261  *
2262  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2263  *  /disabled - FALSE).
2264  **/
2265 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2266                                                  bool state)
2267 {
2268         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2269
2270         if (hw->mac.type != e1000_ich8lan) {
2271                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2272                 return;
2273         }
2274
2275         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2276 }
2277
2278 /**
2279  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2280  *  @hw: pointer to the HW structure
2281  *
2282  *  Workaround for 82566 power-down on D3 entry:
2283  *    1) disable gigabit link
2284  *    2) write VR power-down enable
2285  *    3) read it back
2286  *  Continue if successful, else issue LCD reset and repeat
2287  **/
2288 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2289 {
2290         u32 reg;
2291         u16 data;
2292         u8  retry = 0;
2293
2294         if (hw->phy.type != e1000_phy_igp_3)
2295                 return;
2296
2297         /* Try the workaround twice (if needed) */
2298         do {
2299                 /* Disable link */
2300                 reg = er32(PHY_CTRL);
2301                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2302                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2303                 ew32(PHY_CTRL, reg);
2304
2305                 /*
2306                  * Call gig speed drop workaround on Gig disable before
2307                  * accessing any PHY registers
2308                  */
2309                 if (hw->mac.type == e1000_ich8lan)
2310                         e1000e_gig_downshift_workaround_ich8lan(hw);
2311
2312                 /* Write VR power-down enable */
2313                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2314                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2315                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2316
2317                 /* Read it back and test */
2318                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2319                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2320                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2321                         break;
2322
2323                 /* Issue PHY reset and repeat at most one more time */
2324                 reg = er32(CTRL);
2325                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2326                 retry++;
2327         } while (retry);
2328 }
2329
2330 /**
2331  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2332  *  @hw: pointer to the HW structure
2333  *
2334  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2335  *  LPLU, Gig disable, MDIC PHY reset):
2336  *    1) Set Kumeran Near-end loopback
2337  *    2) Clear Kumeran Near-end loopback
2338  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2339  **/
2340 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2341 {
2342         s32 ret_val;
2343         u16 reg_data;
2344
2345         if ((hw->mac.type != e1000_ich8lan) ||
2346             (hw->phy.type != e1000_phy_igp_3))
2347                 return;
2348
2349         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2350                                       &reg_data);
2351         if (ret_val)
2352                 return;
2353         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2354         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2355                                        reg_data);
2356         if (ret_val)
2357                 return;
2358         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2359         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2360                                        reg_data);
2361 }
2362
2363 /**
2364  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2365  *  @hw: pointer to the HW structure
2366  *
2367  *  During S0 to Sx transition, it is possible the link remains at gig
2368  *  instead of negotiating to a lower speed.  Before going to Sx, set
2369  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2370  *  to a lower speed.
2371  *
2372  *  Should only be called for ICH9 and ICH10 devices.
2373  **/
2374 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2375 {
2376         u32 phy_ctrl;
2377
2378         if ((hw->mac.type == e1000_ich10lan) ||
2379             (hw->mac.type == e1000_ich9lan)) {
2380                 phy_ctrl = er32(PHY_CTRL);
2381                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2382                             E1000_PHY_CTRL_GBE_DISABLE;
2383                 ew32(PHY_CTRL, phy_ctrl);
2384         }
2385
2386         return;
2387 }
2388
2389 /**
2390  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2391  *  @hw: pointer to the HW structure
2392  *
2393  *  Return the LED back to the default configuration.
2394  **/
2395 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2396 {
2397         if (hw->phy.type == e1000_phy_ife)
2398                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2399
2400         ew32(LEDCTL, hw->mac.ledctl_default);
2401         return 0;
2402 }
2403
2404 /**
2405  *  e1000_led_on_ich8lan - Turn LEDs on
2406  *  @hw: pointer to the HW structure
2407  *
2408  *  Turn on the LEDs.
2409  **/
2410 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2411 {
2412         if (hw->phy.type == e1000_phy_ife)
2413                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2414                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2415
2416         ew32(LEDCTL, hw->mac.ledctl_mode2);
2417         return 0;
2418 }
2419
2420 /**
2421  *  e1000_led_off_ich8lan - Turn LEDs off
2422  *  @hw: pointer to the HW structure
2423  *
2424  *  Turn off the LEDs.
2425  **/
2426 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2427 {
2428         if (hw->phy.type == e1000_phy_ife)
2429                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2430                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2431
2432         ew32(LEDCTL, hw->mac.ledctl_mode1);
2433         return 0;
2434 }
2435
2436 /**
2437  *  e1000_get_cfg_done_ich8lan - Read config done bit
2438  *  @hw: pointer to the HW structure
2439  *
2440  *  Read the management control register for the config done bit for
2441  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2442  *  to read the config done bit, so an error is *ONLY* logged and returns
2443  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2444  *  would not be able to be reset or change link.
2445  **/
2446 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2447 {
2448         u32 bank = 0;
2449
2450         e1000e_get_cfg_done(hw);
2451
2452         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2453         if (hw->mac.type != e1000_ich10lan) {
2454                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2455                     (hw->phy.type == e1000_phy_igp_3)) {
2456                         e1000e_phy_init_script_igp3(hw);
2457                 }
2458         } else {
2459                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2460                         /* Maybe we should do a basic PHY config */
2461                         hw_dbg(hw, "EEPROM not present\n");
2462                         return -E1000_ERR_CONFIG;
2463                 }
2464         }
2465
2466         return 0;
2467 }
2468
2469 /**
2470  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2471  *  @hw: pointer to the HW structure
2472  *
2473  *  Clears hardware counters specific to the silicon family and calls
2474  *  clear_hw_cntrs_generic to clear all general purpose counters.
2475  **/
2476 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2477 {
2478         u32 temp;
2479
2480         e1000e_clear_hw_cntrs_base(hw);
2481
2482         temp = er32(ALGNERRC);
2483         temp = er32(RXERRC);
2484         temp = er32(TNCRS);
2485         temp = er32(CEXTERR);
2486         temp = er32(TSCTC);
2487         temp = er32(TSCTFC);
2488
2489         temp = er32(MGTPRC);
2490         temp = er32(MGTPDC);
2491         temp = er32(MGTPTC);
2492
2493         temp = er32(IAC);
2494         temp = er32(ICRXOC);
2495
2496 }
2497
2498 static struct e1000_mac_operations ich8_mac_ops = {
2499         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2500         .check_for_link         = e1000e_check_for_copper_link,
2501         .cleanup_led            = e1000_cleanup_led_ich8lan,
2502         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2503         .get_bus_info           = e1000_get_bus_info_ich8lan,
2504         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2505         .led_on                 = e1000_led_on_ich8lan,
2506         .led_off                = e1000_led_off_ich8lan,
2507         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2508         .reset_hw               = e1000_reset_hw_ich8lan,
2509         .init_hw                = e1000_init_hw_ich8lan,
2510         .setup_link             = e1000_setup_link_ich8lan,
2511         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2512 };
2513
2514 static struct e1000_phy_operations ich8_phy_ops = {
2515         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2516         .check_reset_block      = e1000_check_reset_block_ich8lan,
2517         .commit_phy             = NULL,
2518         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2519         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2520         .get_cable_length       = e1000e_get_cable_length_igp_2,
2521         .get_phy_info           = e1000_get_phy_info_ich8lan,
2522         .read_phy_reg           = e1000e_read_phy_reg_igp,
2523         .release_phy            = e1000_release_swflag_ich8lan,
2524         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2525         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2526         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2527         .write_phy_reg          = e1000e_write_phy_reg_igp,
2528 };
2529
2530 static struct e1000_nvm_operations ich8_nvm_ops = {
2531         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2532         .read_nvm               = e1000_read_nvm_ich8lan,
2533         .release_nvm            = e1000_release_swflag_ich8lan,
2534         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2535         .valid_led_default      = e1000_valid_led_default_ich8lan,
2536         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2537         .write_nvm              = e1000_write_nvm_ich8lan,
2538 };
2539
2540 struct e1000_info e1000_ich8_info = {
2541         .mac                    = e1000_ich8lan,
2542         .flags                  = FLAG_HAS_WOL
2543                                   | FLAG_IS_ICH
2544                                   | FLAG_RX_CSUM_ENABLED
2545                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2546                                   | FLAG_HAS_AMT
2547                                   | FLAG_HAS_FLASH
2548                                   | FLAG_APME_IN_WUC,
2549         .pba                    = 8,
2550         .get_variants           = e1000_get_variants_ich8lan,
2551         .mac_ops                = &ich8_mac_ops,
2552         .phy_ops                = &ich8_phy_ops,
2553         .nvm_ops                = &ich8_nvm_ops,
2554 };
2555
2556 struct e1000_info e1000_ich9_info = {
2557         .mac                    = e1000_ich9lan,
2558         .flags                  = FLAG_HAS_JUMBO_FRAMES
2559                                   | FLAG_IS_ICH
2560                                   | FLAG_HAS_WOL
2561                                   | FLAG_RX_CSUM_ENABLED
2562                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2563                                   | FLAG_HAS_AMT
2564                                   | FLAG_HAS_ERT
2565                                   | FLAG_HAS_FLASH
2566                                   | FLAG_APME_IN_WUC,
2567         .pba                    = 10,
2568         .get_variants           = e1000_get_variants_ich8lan,
2569         .mac_ops                = &ich8_mac_ops,
2570         .phy_ops                = &ich8_phy_ops,
2571         .nvm_ops                = &ich8_nvm_ops,
2572 };
2573
2574 struct e1000_info e1000_ich10_info = {
2575         .mac                    = e1000_ich10lan,
2576         .flags                  = FLAG_HAS_JUMBO_FRAMES
2577                                   | FLAG_IS_ICH
2578                                   | FLAG_HAS_WOL
2579                                   | FLAG_RX_CSUM_ENABLED
2580                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2581                                   | FLAG_HAS_AMT
2582                                   | FLAG_HAS_ERT
2583                                   | FLAG_HAS_FLASH
2584                                   | FLAG_APME_IN_WUC,
2585         .pba                    = 10,
2586         .get_variants           = e1000_get_variants_ich8lan,
2587         .mac_ops                = &ich8_mac_ops,
2588         .phy_ops                = &ich8_phy_ops,
2589         .nvm_ops                = &ich8_nvm_ops,
2590 };