drivers/net/cpmac.c

   1 /*
   2  * Copyright (C) 2006, 2007 Eugene Konev
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/moduleparam.h>
  22
  23 #include <linux/sched.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/errno.h>
  27 #include <linux/types.h>
  28 #include <linux/delay.h>
  29
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/phy_fixed.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/dma-mapping.h>
  39 #include <asm/gpio.h>
  40 #include <asm/atomic.h>
  41
  42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  44 MODULE_LICENSE("GPL");
  45 MODULE_ALIAS("platform:cpmac");
  46
  47 static int debug_level = 8;
  48 static int dumb_switch;
  49
  50 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  51 module_param(debug_level, int, 0444);
  52 module_param(dumb_switch, int, 0444);
  53
  54 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  55 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  56
  57 #define CPMAC_VERSION "0.5.0"
  58 /* frame size + 802.1q tag */
  59 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
  60 #define CPMAC_QUEUES    8
  61
  62 /* Ethernet registers */
  63 #define CPMAC_TX_CONTROL                0x0004
  64 #define CPMAC_TX_TEARDOWN               0x0008
  65 #define CPMAC_RX_CONTROL                0x0014
  66 #define CPMAC_RX_TEARDOWN               0x0018
  67 #define CPMAC_MBP                       0x0100
  68 # define MBP_RXPASSCRC                  0x40000000
  69 # define MBP_RXQOS                      0x20000000
  70 # define MBP_RXNOCHAIN                  0x10000000
  71 # define MBP_RXCMF                      0x01000000
  72 # define MBP_RXSHORT                    0x00800000
  73 # define MBP_RXCEF                      0x00400000
  74 # define MBP_RXPROMISC                  0x00200000
  75 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
  76 # define MBP_RXBCAST                    0x00002000
  77 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
  78 # define MBP_RXMCAST                    0x00000020
  79 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
  80 #define CPMAC_UNICAST_ENABLE            0x0104
  81 #define CPMAC_UNICAST_CLEAR             0x0108
  82 #define CPMAC_MAX_LENGTH                0x010c
  83 #define CPMAC_BUFFER_OFFSET             0x0110
  84 #define CPMAC_MAC_CONTROL               0x0160
  85 # define MAC_TXPTYPE                    0x00000200
  86 # define MAC_TXPACE                     0x00000040
  87 # define MAC_MII                        0x00000020
  88 # define MAC_TXFLOW                     0x00000010
  89 # define MAC_RXFLOW                     0x00000008
  90 # define MAC_MTEST                      0x00000004
  91 # define MAC_LOOPBACK                   0x00000002
  92 # define MAC_FDX                        0x00000001
  93 #define CPMAC_MAC_STATUS                0x0164
  94 # define MAC_STATUS_QOS                 0x00000004
  95 # define MAC_STATUS_RXFLOW              0x00000002
  96 # define MAC_STATUS_TXFLOW              0x00000001
  97 #define CPMAC_TX_INT_ENABLE             0x0178
  98 #define CPMAC_TX_INT_CLEAR              0x017c
  99 #define CPMAC_MAC_INT_VECTOR            0x0180
 100 # define MAC_INT_STATUS                 0x00080000
 101 # define MAC_INT_HOST                   0x00040000
 102 # define MAC_INT_RX                     0x00020000
 103 # define MAC_INT_TX                     0x00010000
 104 #define CPMAC_MAC_EOI_VECTOR            0x0184
 105 #define CPMAC_RX_INT_ENABLE             0x0198
 106 #define CPMAC_RX_INT_CLEAR              0x019c
 107 #define CPMAC_MAC_INT_ENABLE            0x01a8
 108 #define CPMAC_MAC_INT_CLEAR             0x01ac
 109 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
 110 #define CPMAC_MAC_ADDR_MID              0x01d0
 111 #define CPMAC_MAC_ADDR_HI               0x01d4
 112 #define CPMAC_MAC_HASH_LO               0x01d8
 113 #define CPMAC_MAC_HASH_HI               0x01dc
 114 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
 115 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
 116 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
 117 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
 118 #define CPMAC_REG_END                   0x0680
 119 /*
 120  * Rx/Tx statistics
 121  * TODO: use some of them to fill stats in cpmac_stats()
 122  */
 123 #define CPMAC_STATS_RX_GOOD             0x0200
 124 #define CPMAC_STATS_RX_BCAST            0x0204
 125 #define CPMAC_STATS_RX_MCAST            0x0208
 126 #define CPMAC_STATS_RX_PAUSE            0x020c
 127 #define CPMAC_STATS_RX_CRC              0x0210
 128 #define CPMAC_STATS_RX_ALIGN            0x0214
 129 #define CPMAC_STATS_RX_OVER             0x0218
 130 #define CPMAC_STATS_RX_JABBER           0x021c
 131 #define CPMAC_STATS_RX_UNDER            0x0220
 132 #define CPMAC_STATS_RX_FRAG             0x0224
 133 #define CPMAC_STATS_RX_FILTER           0x0228
 134 #define CPMAC_STATS_RX_QOSFILTER        0x022c
 135 #define CPMAC_STATS_RX_OCTETS           0x0230
 136
 137 #define CPMAC_STATS_TX_GOOD             0x0234
 138 #define CPMAC_STATS_TX_BCAST            0x0238
 139 #define CPMAC_STATS_TX_MCAST            0x023c
 140 #define CPMAC_STATS_TX_PAUSE            0x0240
 141 #define CPMAC_STATS_TX_DEFER            0x0244
 142 #define CPMAC_STATS_TX_COLLISION        0x0248
 143 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
 144 #define CPMAC_STATS_TX_MULTICOLL        0x0250
 145 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
 146 #define CPMAC_STATS_TX_LATECOLL         0x0258
 147 #define CPMAC_STATS_TX_UNDERRUN         0x025c
 148 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
 149 #define CPMAC_STATS_TX_OCTETS           0x0264
 150
 151 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
 152 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
 153                                                 (reg)))
 154
 155 /* MDIO bus */
 156 #define CPMAC_MDIO_VERSION              0x0000
 157 #define CPMAC_MDIO_CONTROL              0x0004
 158 # define MDIOC_IDLE                     0x80000000
 159 # define MDIOC_ENABLE                   0x40000000
 160 # define MDIOC_PREAMBLE                 0x00100000
 161 # define MDIOC_FAULT                    0x00080000
 162 # define MDIOC_FAULTDETECT              0x00040000
 163 # define MDIOC_INTTEST                  0x00020000
 164 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
 165 #define CPMAC_MDIO_ALIVE                0x0008
 166 #define CPMAC_MDIO_LINK                 0x000c
 167 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
 168 # define MDIO_BUSY                      0x80000000
 169 # define MDIO_WRITE                     0x40000000
 170 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
 171 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
 172 # define MDIO_DATA(data)                ((data) & 0xffff)
 173 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
 174 # define PHYSEL_LINKSEL                 0x00000040
 175 # define PHYSEL_LINKINT                 0x00000020
 176
 177 struct cpmac_desc {
 178         u32 hw_next;
 179         u32 hw_data;
 180         u16 buflen;
 181         u16 bufflags;
 182         u16 datalen;
 183         u16 dataflags;
 184 #define CPMAC_SOP                       0x8000
 185 #define CPMAC_EOP                       0x4000
 186 #define CPMAC_OWN                       0x2000
 187 #define CPMAC_EOQ                       0x1000
 188         struct sk_buff *skb;
 189         struct cpmac_desc *next;
 190         struct cpmac_desc *prev;
 191         dma_addr_t mapping;
 192         dma_addr_t data_mapping;
 193 };
 194
 195 struct cpmac_priv {
 196         spinlock_t lock;
 197         spinlock_t rx_lock;
 198         struct cpmac_desc *rx_head;
 199         int ring_size;
 200         struct cpmac_desc *desc_ring;
 201         dma_addr_t dma_ring;
 202         void __iomem *regs;
 203         struct mii_bus *mii_bus;
 204         struct phy_device *phy;
 205         char phy_name[BUS_ID_SIZE];
 206         int oldlink, oldspeed, oldduplex;
 207         u32 msg_enable;
 208         struct net_device *dev;
 209         struct work_struct reset_work;
 210         struct platform_device *pdev;
 211         struct napi_struct napi;
 212         atomic_t reset_pending;
 213 };
 214
 215 static irqreturn_t cpmac_irq(int, void *);
 216 static void cpmac_hw_start(struct net_device *dev);
 217 static void cpmac_hw_stop(struct net_device *dev);
 218 static int cpmac_stop(struct net_device *dev);
 219 static int cpmac_open(struct net_device *dev);
 220
 221 static void cpmac_dump_regs(struct net_device *dev)
 222 {
 223         int i;
 224         struct cpmac_priv *priv = netdev_priv(dev);
 225         for (i = 0; i < CPMAC_REG_END; i += 4) {
 226                 if (i % 16 == 0) {
 227                         if (i)
 228                                 printk("\n");
 229                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
 230                                priv->regs + i);
 231                 }
 232                 printk(" %08x", cpmac_read(priv->regs, i));
 233         }
 234         printk("\n");
 235 }
 236
 237 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
 238 {
 239         int i;
 240         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
 241         for (i = 0; i < sizeof(*desc) / 4; i++)
 242                 printk(" %08x", ((u32 *)desc)[i]);
 243         printk("\n");
 244 }
 245
 246 static void cpmac_dump_all_desc(struct net_device *dev)
 247 {
 248         struct cpmac_priv *priv = netdev_priv(dev);
 249         struct cpmac_desc *dump = priv->rx_head;
 250         do {
 251                 cpmac_dump_desc(dev, dump);
 252                 dump = dump->next;
 253         } while (dump != priv->rx_head);
 254 }
 255
 256 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
 257 {
 258         int i;
 259         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
 260         for (i = 0; i < skb->len; i++) {
 261                 if (i % 16 == 0) {
 262                         if (i)
 263                                 printk("\n");
 264                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
 265                                skb->data + i);
 266                 }
 267                 printk(" %02x", ((u8 *)skb->data)[i]);
 268         }
 269         printk("\n");
 270 }
 271
 272 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 273 {
 274         u32 val;
 275
 276         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 277                 cpu_relax();
 278         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
 279                     MDIO_PHY(phy_id));
 280         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
 281                 cpu_relax();
 282         return MDIO_DATA(val);
 283 }
 284
 285 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 286                             int reg, u16 val)
 287 {
 288         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 289                 cpu_relax();
 290         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
 291                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
 292         return 0;
 293 }
 294
 295 static int cpmac_mdio_reset(struct mii_bus *bus)
 296 {
 297         ar7_device_reset(AR7_RESET_BIT_MDIO);
 298         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
 299                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
 300         return 0;
 301 }
 302
 303 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
 304
 305 static struct mii_bus cpmac_mii = {
 306         .name = "cpmac-mii",
 307         .read = cpmac_mdio_read,
 308         .write = cpmac_mdio_write,
 309         .reset = cpmac_mdio_reset,
 310         .irq = mii_irqs,
 311 };
 312
 313 static int cpmac_config(struct net_device *dev, struct ifmap *map)
 314 {
 315         if (dev->flags & IFF_UP)
 316                 return -EBUSY;
 317
 318         /* Don't allow changing the I/O address */
 319         if (map->base_addr != dev->base_addr)
 320                 return -EOPNOTSUPP;
 321
 322         /* ignore other fields */
 323         return 0;
 324 }
 325
 326 static void cpmac_set_multicast_list(struct net_device *dev)
 327 {
 328         struct dev_mc_list *iter;
 329         int i;
 330         u8 tmp;
 331         u32 mbp, bit, hash[2] = { 0, };
 332         struct cpmac_priv *priv = netdev_priv(dev);
 333
 334         mbp = cpmac_read(priv->regs, CPMAC_MBP);
 335         if (dev->flags & IFF_PROMISC) {
 336                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
 337                             MBP_RXPROMISC);
 338         } else {
 339                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
 340                 if (dev->flags & IFF_ALLMULTI) {
 341                         /* enable all multicast mode */
 342                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
 343                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
 344                 } else {
 345                         /*
 346                          * cpmac uses some strange mac address hashing
 347                          * (not crc32)
 348                          */
 349                         for (i = 0, iter = dev->mc_list; i < dev->mc_count;
 350                              i++, iter = iter->next) {
 351                                 bit = 0;
 352                                 tmp = iter->dmi_addr[0];
 353                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 354                                 tmp = iter->dmi_addr[1];
 355                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 356                                 tmp = iter->dmi_addr[2];
 357                                 bit  ^= (tmp >> 6) ^ tmp;
 358                                 tmp = iter->dmi_addr[3];
 359                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 360                                 tmp = iter->dmi_addr[4];
 361                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 362                                 tmp = iter->dmi_addr[5];
 363                                 bit  ^= (tmp >> 6) ^ tmp;
 364                                 bit &= 0x3f;
 365                                 hash[bit / 32] |= 1 << (bit % 32);
 366                         }
 367
 368                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
 369                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
 370                 }
 371         }
 372 }
 373
 374 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
 375                                     struct cpmac_desc *desc)
 376 {
 377         struct sk_buff *skb, *result = NULL;
 378
 379         if (unlikely(netif_msg_hw(priv)))
 380                 cpmac_dump_desc(priv->dev, desc);
 381         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
 382         if (unlikely(!desc->datalen)) {
 383                 if (netif_msg_rx_err(priv) && net_ratelimit())
 384                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
 385                                priv->dev->name);
 386                 return NULL;
 387         }
 388
 389         skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
 390         if (likely(skb)) {
 391                 skb_reserve(skb, 2);
 392                 skb_put(desc->skb, desc->datalen);
 393                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
 394                 desc->skb->ip_summed = CHECKSUM_NONE;
 395                 priv->dev->stats.rx_packets++;
 396                 priv->dev->stats.rx_bytes += desc->datalen;
 397                 result = desc->skb;
 398                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
 399                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
 400                 desc->skb = skb;
 401                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
 402                                                     CPMAC_SKB_SIZE,
 403                                                     DMA_FROM_DEVICE);
 404                 desc->hw_data = (u32)desc->data_mapping;
 405                 if (unlikely(netif_msg_pktdata(priv))) {
 406                         printk(KERN_DEBUG "%s: received packet:\n",
 407                                priv->dev->name);
 408                         cpmac_dump_skb(priv->dev, result);
 409                 }
 410         } else {
 411                 if (netif_msg_rx_err(priv) && net_ratelimit())
 412                         printk(KERN_WARNING
 413                                "%s: low on skbs, dropping packet\n",
 414                                priv->dev->name);
 415                 priv->dev->stats.rx_dropped++;
 416         }
 417
 418         desc->buflen = CPMAC_SKB_SIZE;
 419         desc->dataflags = CPMAC_OWN;
 420
 421         return result;
 422 }
 423
 424 static int cpmac_poll(struct napi_struct *napi, int budget)
 425 {
 426         struct sk_buff *skb;
 427         struct cpmac_desc *desc, *restart;
 428         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
 429         int received = 0, processed = 0;
 430
 431         spin_lock(&priv->rx_lock);
 432         if (unlikely(!priv->rx_head)) {
 433                 if (netif_msg_rx_err(priv) && net_ratelimit())
 434                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
 435                                priv->dev->name);
 436                 spin_unlock(&priv->rx_lock);
 437                 netif_rx_complete(priv->dev, napi);
 438                 return 0;
 439         }
 440
 441         desc = priv->rx_head;
 442         restart = NULL;
 443         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
 444                 processed++;
 445
 446                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
 447                         /* The last update to eoq->hw_next didn't happen
 448                         * soon enough, and the receiver stopped here.
 449                         *Remember this descriptor so we can restart
 450                         * the receiver after freeing some space.
 451                         */
 452                         if (unlikely(restart)) {
 453                                 if (netif_msg_rx_err(priv))
 454                                         printk(KERN_ERR "%s: poll found a"
 455                                                 " duplicate EOQ: %p and %p\n",
 456                                                 priv->dev->name, restart, desc);
 457                                 goto fatal_error;
 458                         }
 459
 460                         restart = desc->next;
 461                 }
 462
 463                 skb = cpmac_rx_one(priv, desc);
 464                 if (likely(skb)) {
 465                         netif_receive_skb(skb);
 466                         received++;
 467                 }
 468                 desc = desc->next;
 469         }
 470
 471         if (desc != priv->rx_head) {
 472                 /* We freed some buffers, but not the whole ring,
 473                  * add what we did free to the rx list */
 474                 desc->prev->hw_next = (u32)0;
 475                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
 476         }
 477
 478         /* Optimization: If we did not actually process an EOQ (perhaps because
 479          * of quota limits), check to see if the tail of the queue has EOQ set.
 480         * We should immediately restart in that case so that the receiver can
 481         * restart and run in parallel with more packet processing.
 482         * This lets us handle slightly larger bursts before running
 483         * out of ring space (assuming dev->weight < ring_size) */
 484
 485         if (!restart &&
 486              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
 487                     == CPMAC_EOQ &&
 488              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
 489                 /* reset EOQ so the poll loop (above) doesn't try to
 490                 * restart this when it eventually gets to this descriptor.
 491                 */
 492                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
 493                 restart = priv->rx_head;
 494         }
 495
 496         if (restart) {
 497                 priv->dev->stats.rx_errors++;
 498                 priv->dev->stats.rx_fifo_errors++;
 499                 if (netif_msg_rx_err(priv) && net_ratelimit())
 500                         printk(KERN_WARNING "%s: rx dma ring overrun\n",
 501                                priv->dev->name);
 502
 503                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
 504                         if (netif_msg_drv(priv))
 505                                 printk(KERN_ERR "%s: cpmac_poll is trying to "
 506                                         "restart rx from a descriptor that's "
 507                                         "not free: %p\n",
 508                                         priv->dev->name, restart);
 509                                 goto fatal_error;
 510                 }
 511
 512                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
 513         }
 514
 515         priv->rx_head = desc;
 516         spin_unlock(&priv->rx_lock);
 517         if (unlikely(netif_msg_rx_status(priv)))
 518                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
 519                        priv->dev->name, received);
 520         if (processed == 0) {
 521                 /* we ran out of packets to read,
 522                  * revert to interrupt-driven mode */
 523                 netif_rx_complete(priv->dev, napi);
 524                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 525                 return 0;
 526         }
 527
 528         return 1;
 529
 530 fatal_error:
 531         /* Something went horribly wrong.
 532          * Reset hardware to try to recover rather than wedging. */
 533
 534         if (netif_msg_drv(priv)) {
 535                 printk(KERN_ERR "%s: cpmac_poll is confused. "
 536                                 "Resetting hardware\n", priv->dev->name);
 537                 cpmac_dump_all_desc(priv->dev);
 538                 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
 539                         priv->dev->name,
 540                         cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
 541                         cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
 542         }
 543
 544         spin_unlock(&priv->rx_lock);
 545         netif_rx_complete(priv->dev, napi);
 546         netif_tx_stop_all_queues(priv->dev);
 547         napi_disable(&priv->napi);
 548
 549         atomic_inc(&priv->reset_pending);
 550         cpmac_hw_stop(priv->dev);
 551         if (!schedule_work(&priv->reset_work))
 552                 atomic_dec(&priv->reset_pending);
 553         return 0;
 554
 555 }
 556
 557 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 558 {
 559         int queue, len;
 560         struct cpmac_desc *desc;
 561         struct cpmac_priv *priv = netdev_priv(dev);
 562
 563         if (unlikely(atomic_read(&priv->reset_pending)))
 564                 return NETDEV_TX_BUSY;
 565
 566         if (unlikely(skb_padto(skb, ETH_ZLEN)))
 567                 return NETDEV_TX_OK;
 568
 569         len = max(skb->len, ETH_ZLEN);
 570         queue = skb_get_queue_mapping(skb);
 571         netif_stop_subqueue(dev, queue);
 572
 573         desc = &priv->desc_ring[queue];
 574         if (unlikely(desc->dataflags & CPMAC_OWN)) {
 575                 if (netif_msg_tx_err(priv) && net_ratelimit())
 576                         printk(KERN_WARNING "%s: tx dma ring full\n",
 577                                dev->name);
 578                 return NETDEV_TX_BUSY;
 579         }
 580
 581         spin_lock(&priv->lock);
 582         dev->trans_start = jiffies;
 583         spin_unlock(&priv->lock);
 584         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
 585         desc->skb = skb;
 586         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
 587                                             DMA_TO_DEVICE);
 588         desc->hw_data = (u32)desc->data_mapping;
 589         desc->datalen = len;
 590         desc->buflen = len;
 591         if (unlikely(netif_msg_tx_queued(priv)))
 592                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
 593                        skb->len);
 594         if (unlikely(netif_msg_hw(priv)))
 595                 cpmac_dump_desc(dev, desc);
 596         if (unlikely(netif_msg_pktdata(priv)))
 597                 cpmac_dump_skb(dev, skb);
 598         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
 599
 600         return NETDEV_TX_OK;
 601 }
 602
 603 static void cpmac_end_xmit(struct net_device *dev, int queue)
 604 {
 605         struct cpmac_desc *desc;
 606         struct cpmac_priv *priv = netdev_priv(dev);
 607
 608         desc = &priv->desc_ring[queue];
 609         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
 610         if (likely(desc->skb)) {
 611                 spin_lock(&priv->lock);
 612                 dev->stats.tx_packets++;
 613                 dev->stats.tx_bytes += desc->skb->len;
 614                 spin_unlock(&priv->lock);
 615                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
 616                                  DMA_TO_DEVICE);
 617
 618                 if (unlikely(netif_msg_tx_done(priv)))
 619                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
 620                                desc->skb, desc->skb->len);
 621
 622                 dev_kfree_skb_irq(desc->skb);
 623                 desc->skb = NULL;
 624                 if (netif_subqueue_stopped(dev, queue))
 625                         netif_wake_subqueue(dev, queue);
 626         } else {
 627                 if (netif_msg_tx_err(priv) && net_ratelimit())
 628                         printk(KERN_WARNING
 629                                "%s: end_xmit: spurious interrupt\n", dev->name);
 630                 if (netif_subqueue_stopped(dev, queue))
 631                         netif_wake_subqueue(dev, queue);
 632         }
 633 }
 634
 635 static void cpmac_hw_stop(struct net_device *dev)
 636 {
 637         int i;
 638         struct cpmac_priv *priv = netdev_priv(dev);
 639         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 640
 641         ar7_device_reset(pdata->reset_bit);
 642         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 643                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
 644         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 645                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
 646         for (i = 0; i < 8; i++) {
 647                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 648                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 649         }
 650         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 651         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 652         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 653         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 654         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 655                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
 656 }
 657
 658 static void cpmac_hw_start(struct net_device *dev)
 659 {
 660         int i;
 661         struct cpmac_priv *priv = netdev_priv(dev);
 662         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 663
 664         ar7_device_reset(pdata->reset_bit);
 665         for (i = 0; i < 8; i++) {
 666                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 667                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 668         }
 669         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
 670
 671         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
 672                     MBP_RXMCAST);
 673         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
 674         for (i = 0; i < 8; i++)
 675                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 676         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 677         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 678                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 679                     (dev->dev_addr[3] << 24));
 680         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 681         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 682         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 683         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 684         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 685         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
 686         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 687         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
 688         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 689
 690         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 691                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
 692         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 693                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
 694         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 695                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
 696                     MAC_FDX);
 697 }
 698
 699 static void cpmac_clear_rx(struct net_device *dev)
 700 {
 701         struct cpmac_priv *priv = netdev_priv(dev);
 702         struct cpmac_desc *desc;
 703         int i;
 704         if (unlikely(!priv->rx_head))
 705                 return;
 706         desc = priv->rx_head;
 707         for (i = 0; i < priv->ring_size; i++) {
 708                 if ((desc->dataflags & CPMAC_OWN) == 0) {
 709                         if (netif_msg_rx_err(priv) && net_ratelimit())
 710                                 printk(KERN_WARNING "%s: packet dropped\n",
 711                                        dev->name);
 712                         if (unlikely(netif_msg_hw(priv)))
 713                                 cpmac_dump_desc(dev, desc);
 714                         desc->dataflags = CPMAC_OWN;
 715                         dev->stats.rx_dropped++;
 716                 }
 717                 desc->hw_next = desc->next->mapping;
 718                 desc = desc->next;
 719         }
 720         priv->rx_head->prev->hw_next = 0;
 721 }
 722
 723 static void cpmac_clear_tx(struct net_device *dev)
 724 {
 725         struct cpmac_priv *priv = netdev_priv(dev);
 726         int i;
 727         if (unlikely(!priv->desc_ring))
 728                 return;
 729         for (i = 0; i < CPMAC_QUEUES; i++) {
 730                 priv->desc_ring[i].dataflags = 0;
 731                 if (priv->desc_ring[i].skb) {
 732                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 733                         priv->desc_ring[i].skb = NULL;
 734                 }
 735         }
 736 }
 737
 738 static void cpmac_hw_error(struct work_struct *work)
 739 {
 740         int i;
 741         struct cpmac_priv *priv =
 742                 container_of(work, struct cpmac_priv, reset_work);
 743
 744         spin_lock(&priv->rx_lock);
 745         cpmac_clear_rx(priv->dev);
 746         spin_unlock(&priv->rx_lock);
 747         cpmac_clear_tx(priv->dev);
 748         cpmac_hw_start(priv->dev);
 749         barrier();
 750         atomic_dec(&priv->reset_pending);
 751
 752         netif_tx_wake_all_queues(priv->dev);
 753         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 754 }
 755
 756 static void cpmac_check_status(struct net_device *dev)
 757 {
 758         struct cpmac_priv *priv = netdev_priv(dev);
 759
 760         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
 761         int rx_channel = (macstatus >> 8) & 7;
 762         int rx_code = (macstatus >> 12) & 15;
 763         int tx_channel = (macstatus >> 16) & 7;
 764         int tx_code = (macstatus >> 20) & 15;
 765
 766         if (rx_code || tx_code) {
 767                 if (netif_msg_drv(priv) && net_ratelimit()) {
 768                         /* Can't find any documentation on what these
 769                          *error codes actually are. So just log them and hope..
 770                          */
 771                         if (rx_code)
 772                                 printk(KERN_WARNING "%s: host error %d on rx "
 773                                      "channel %d (macstatus %08x), resetting\n",
 774                                      dev->name, rx_code, rx_channel, macstatus);
 775                         if (tx_code)
 776                                 printk(KERN_WARNING "%s: host error %d on tx "
 777                                      "channel %d (macstatus %08x), resetting\n",
 778                                      dev->name, tx_code, tx_channel, macstatus);
 779                 }
 780
 781                 netif_tx_stop_all_queues(dev);
 782                 cpmac_hw_stop(dev);
 783                 if (schedule_work(&priv->reset_work))
 784                         atomic_inc(&priv->reset_pending);
 785                 if (unlikely(netif_msg_hw(priv)))
 786                         cpmac_dump_regs(dev);
 787         }
 788         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 789 }
 790
 791 static irqreturn_t cpmac_irq(int irq, void *dev_id)
 792 {
 793         struct net_device *dev = dev_id;
 794         struct cpmac_priv *priv;
 795         int queue;
 796         u32 status;
 797
 798         priv = netdev_priv(dev);
 799
 800         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
 801
 802         if (unlikely(netif_msg_intr(priv)))
 803                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
 804                        status);
 805
 806         if (status & MAC_INT_TX)
 807                 cpmac_end_xmit(dev, (status & 7));
 808
 809         if (status & MAC_INT_RX) {
 810                 queue = (status >> 8) & 7;
 811                 if (netif_rx_schedule_prep(dev, &priv->napi)) {
 812                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
 813                         __netif_rx_schedule(dev, &priv->napi);
 814                 }
 815         }
 816
 817         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
 818
 819         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
 820                 cpmac_check_status(dev);
 821
 822         return IRQ_HANDLED;
 823 }
 824
 825 static void cpmac_tx_timeout(struct net_device *dev)
 826 {
 827         int i;
 828         struct cpmac_priv *priv = netdev_priv(dev);
 829
 830         spin_lock(&priv->lock);
 831         dev->stats.tx_errors++;
 832         spin_unlock(&priv->lock);
 833         if (netif_msg_tx_err(priv) && net_ratelimit())
 834                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
 835
 836         atomic_inc(&priv->reset_pending);
 837         barrier();
 838         cpmac_clear_tx(dev);
 839         barrier();
 840         atomic_dec(&priv->reset_pending);
 841
 842         netif_tx_wake_all_queues(priv->dev);
 843 }
 844
 845 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 846 {
 847         struct cpmac_priv *priv = netdev_priv(dev);
 848         if (!(netif_running(dev)))
 849                 return -EINVAL;
 850         if (!priv->phy)
 851                 return -EINVAL;
 852         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
 853             (cmd == SIOCSMIIREG))
 854                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
 855
 856         return -EOPNOTSUPP;
 857 }
 858
 859 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 860 {
 861         struct cpmac_priv *priv = netdev_priv(dev);
 862
 863         if (priv->phy)
 864                 return phy_ethtool_gset(priv->phy, cmd);
 865
 866         return -EINVAL;
 867 }
 868
 869 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 870 {
 871         struct cpmac_priv *priv = netdev_priv(dev);
 872
 873         if (!capable(CAP_NET_ADMIN))
 874                 return -EPERM;
 875
 876         if (priv->phy)
 877                 return phy_ethtool_sset(priv->phy, cmd);
 878
 879         return -EINVAL;
 880 }
 881
 882 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 883 {
 884         struct cpmac_priv *priv = netdev_priv(dev);
 885
 886         ring->rx_max_pending = 1024;
 887         ring->rx_mini_max_pending = 1;
 888         ring->rx_jumbo_max_pending = 1;
 889         ring->tx_max_pending = 1;
 890
 891         ring->rx_pending = priv->ring_size;
 892         ring->rx_mini_pending = 1;
 893         ring->rx_jumbo_pending = 1;
 894         ring->tx_pending = 1;
 895 }
 896
 897 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 898 {
 899         struct cpmac_priv *priv = netdev_priv(dev);
 900
 901         if (netif_running(dev))
 902                 return -EBUSY;
 903         priv->ring_size = ring->rx_pending;
 904         return 0;
 905 }
 906
 907 static void cpmac_get_drvinfo(struct net_device *dev,
 908                               struct ethtool_drvinfo *info)
 909 {
 910         strcpy(info->driver, "cpmac");
 911         strcpy(info->version, CPMAC_VERSION);
 912         info->fw_version[0] = '\0';
 913         sprintf(info->bus_info, "%s", "cpmac");
 914         info->regdump_len = 0;
 915 }
 916
 917 static const struct ethtool_ops cpmac_ethtool_ops = {
 918         .get_settings = cpmac_get_settings,
 919         .set_settings = cpmac_set_settings,
 920         .get_drvinfo = cpmac_get_drvinfo,
 921         .get_link = ethtool_op_get_link,
 922         .get_ringparam = cpmac_get_ringparam,
 923         .set_ringparam = cpmac_set_ringparam,
 924 };
 925
 926 static void cpmac_adjust_link(struct net_device *dev)
 927 {
 928         struct cpmac_priv *priv = netdev_priv(dev);
 929         int new_state = 0;
 930
 931         spin_lock(&priv->lock);
 932         if (priv->phy->link) {
 933                 netif_tx_start_all_queues(dev);
 934                 if (priv->phy->duplex != priv->oldduplex) {
 935                         new_state = 1;
 936                         priv->oldduplex = priv->phy->duplex;
 937                 }
 938
 939                 if (priv->phy->speed != priv->oldspeed) {
 940                         new_state = 1;
 941                         priv->oldspeed = priv->phy->speed;
 942                 }
 943
 944                 if (!priv->oldlink) {
 945                         new_state = 1;
 946                         priv->oldlink = 1;
 947                 }
 948         } else if (priv->oldlink) {
 949                 new_state = 1;
 950                 priv->oldlink = 0;
 951                 priv->oldspeed = 0;
 952                 priv->oldduplex = -1;
 953         }
 954
 955         if (new_state && netif_msg_link(priv) && net_ratelimit())
 956                 phy_print_status(priv->phy);
 957
 958         spin_unlock(&priv->lock);
 959 }
 960
 961 static int cpmac_open(struct net_device *dev)
 962 {
 963         int i, size, res;
 964         struct cpmac_priv *priv = netdev_priv(dev);
 965         struct resource *mem;
 966         struct cpmac_desc *desc;
 967         struct sk_buff *skb;
 968
 969         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 970         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
 971                 if (netif_msg_drv(priv))
 972                         printk(KERN_ERR "%s: failed to request registers\n",
 973                                dev->name);
 974                 res = -ENXIO;
 975                 goto fail_reserve;
 976         }
 977
 978         priv->regs = ioremap(mem->start, mem->end - mem->start);
 979         if (!priv->regs) {
 980                 if (netif_msg_drv(priv))
 981                         printk(KERN_ERR "%s: failed to remap registers\n",
 982                                dev->name);
 983                 res = -ENXIO;
 984                 goto fail_remap;
 985         }
 986
 987         size = priv->ring_size + CPMAC_QUEUES;
 988         priv->desc_ring = dma_alloc_coherent(&dev->dev,
 989                                              sizeof(struct cpmac_desc) * size,
 990                                              &priv->dma_ring,
 991                                              GFP_KERNEL);
 992         if (!priv->desc_ring) {
 993                 res = -ENOMEM;
 994                 goto fail_alloc;
 995         }
 996
 997         for (i = 0; i < size; i++)
 998                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
 999
1000         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1001         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
1002                 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
1003                 if (unlikely(!skb)) {
1004                         res = -ENOMEM;
1005                         goto fail_desc;
1006                 }
1007                 skb_reserve(skb, 2);
1008                 desc->skb = skb;
1009                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1010                                                     CPMAC_SKB_SIZE,
1011                                                     DMA_FROM_DEVICE);
1012                 desc->hw_data = (u32)desc->data_mapping;
1013                 desc->buflen = CPMAC_SKB_SIZE;
1014                 desc->dataflags = CPMAC_OWN;
1015                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1016                 desc->next->prev = desc;
1017                 desc->hw_next = (u32)desc->next->mapping;
1018         }
1019
1020         priv->rx_head->prev->hw_next = (u32)0;
1021
1022         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1023                                dev->name, dev))) {
1024                 if (netif_msg_drv(priv))
1025                         printk(KERN_ERR "%s: failed to obtain irq\n",
1026                                dev->name);
1027                 goto fail_irq;
1028         }
1029
1030         atomic_set(&priv->reset_pending, 0);
1031         INIT_WORK(&priv->reset_work, cpmac_hw_error);
1032         cpmac_hw_start(dev);
1033
1034         napi_enable(&priv->napi);
1035         priv->phy->state = PHY_CHANGELINK;
1036         phy_start(priv->phy);
1037
1038         return 0;
1039
1040 fail_irq:
1041 fail_desc:
1042         for (i = 0; i < priv->ring_size; i++) {
1043                 if (priv->rx_head[i].skb) {
1044                         dma_unmap_single(&dev->dev,
1045                                          priv->rx_head[i].data_mapping,
1046                                          CPMAC_SKB_SIZE,
1047                                          DMA_FROM_DEVICE);
1048                         kfree_skb(priv->rx_head[i].skb);
1049                 }
1050         }
1051 fail_alloc:
1052         kfree(priv->desc_ring);
1053         iounmap(priv->regs);
1054
1055 fail_remap:
1056         release_mem_region(mem->start, mem->end - mem->start);
1057
1058 fail_reserve:
1059         return res;
1060 }
1061
1062 static int cpmac_stop(struct net_device *dev)
1063 {
1064         int i;
1065         struct cpmac_priv *priv = netdev_priv(dev);
1066         struct resource *mem;
1067
1068         netif_tx_stop_all_queues(dev);
1069
1070         cancel_work_sync(&priv->reset_work);
1071         napi_disable(&priv->napi);
1072         phy_stop(priv->phy);
1073
1074         cpmac_hw_stop(dev);
1075
1076         for (i = 0; i < 8; i++)
1077                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1078         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1079         cpmac_write(priv->regs, CPMAC_MBP, 0);
1080
1081         free_irq(dev->irq, dev);
1082         iounmap(priv->regs);
1083         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1084         release_mem_region(mem->start, mem->end - mem->start);
1085         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1086         for (i = 0; i < priv->ring_size; i++) {
1087                 if (priv->rx_head[i].skb) {
1088                         dma_unmap_single(&dev->dev,
1089                                          priv->rx_head[i].data_mapping,
1090                                          CPMAC_SKB_SIZE,
1091                                          DMA_FROM_DEVICE);
1092                         kfree_skb(priv->rx_head[i].skb);
1093                 }
1094         }
1095
1096         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1097                           (CPMAC_QUEUES + priv->ring_size),
1098                           priv->desc_ring, priv->dma_ring);
1099         return 0;
1100 }
1101
1102 static int external_switch;
1103
1104 static int __devinit cpmac_probe(struct platform_device *pdev)
1105 {
1106         int rc, phy_id, i;
1107         char *mdio_bus_id = "0";
1108         struct resource *mem;
1109         struct cpmac_priv *priv;
1110         struct net_device *dev;
1111         struct plat_cpmac_data *pdata;
1112         DECLARE_MAC_BUF(mac);
1113
1114         pdata = pdev->dev.platform_data;
1115
1116         for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1117                 if (!(pdata->phy_mask & (1 << phy_id)))
1118                         continue;
1119                 if (!cpmac_mii.phy_map[phy_id])
1120                         continue;
1121                 break;
1122         }
1123
1124         if (phy_id == PHY_MAX_ADDR) {
1125                 if (external_switch || dumb_switch) {
1126                         mdio_bus_id = 0; /* fixed phys bus */
1127                         phy_id = pdev->id;
1128                 } else {
1129                         dev_err(&pdev->dev, "no PHY present\n");
1130                         return -ENODEV;
1131                 }
1132         }
1133
1134         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1135
1136         if (!dev) {
1137                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1138                 return -ENOMEM;
1139         }
1140
1141         platform_set_drvdata(pdev, dev);
1142         priv = netdev_priv(dev);
1143
1144         priv->pdev = pdev;
1145         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1146         if (!mem) {
1147                 rc = -ENODEV;
1148                 goto fail;
1149         }
1150
1151         dev->irq = platform_get_irq_byname(pdev, "irq");
1152
1153         dev->open               = cpmac_open;
1154         dev->stop               = cpmac_stop;
1155         dev->set_config         = cpmac_config;
1156         dev->hard_start_xmit    = cpmac_start_xmit;
1157         dev->do_ioctl           = cpmac_ioctl;
1158         dev->set_multicast_list = cpmac_set_multicast_list;
1159         dev->tx_timeout         = cpmac_tx_timeout;
1160         dev->ethtool_ops        = &cpmac_ethtool_ops;
1161
1162         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1163
1164         spin_lock_init(&priv->lock);
1165         spin_lock_init(&priv->rx_lock);
1166         priv->dev = dev;
1167         priv->ring_size = 64;
1168         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1169         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1170
1171         priv->phy = phy_connect(dev, cpmac_mii.phy_map[phy_id]->dev.bus_id,
1172                                 &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1173         if (IS_ERR(priv->phy)) {
1174                 if (netif_msg_drv(priv))
1175                         printk(KERN_ERR "%s: Could not attach to PHY\n",
1176                                dev->name);
1177                 return PTR_ERR(priv->phy);
1178         }
1179
1180         if ((rc = register_netdev(dev))) {
1181                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1182                        dev->name);
1183                 goto fail;
1184         }
1185
1186         if (netif_msg_probe(priv)) {
1187                 printk(KERN_INFO
1188                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1189                        "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1190                        priv->phy_name, print_mac(mac, dev->dev_addr));
1191         }
1192         return 0;
1193
1194 fail:
1195         free_netdev(dev);
1196         return rc;
1197 }
1198
1199 static int __devexit cpmac_remove(struct platform_device *pdev)
1200 {
1201         struct net_device *dev = platform_get_drvdata(pdev);
1202         unregister_netdev(dev);
1203         free_netdev(dev);
1204         return 0;
1205 }
1206
1207 static struct platform_driver cpmac_driver = {
1208         .driver.name = "cpmac",
1209         .driver.owner = THIS_MODULE,
1210         .probe = cpmac_probe,
1211         .remove = __devexit_p(cpmac_remove),
1212 };
1213
1214 int __devinit cpmac_init(void)
1215 {
1216         u32 mask;
1217         int i, res;
1218
1219         cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1220
1221         if (!cpmac_mii.priv) {
1222                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1223                 return -ENXIO;
1224         }
1225
1226 #warning FIXME: unhardcode gpio&reset bits
1227         ar7_gpio_disable(26);
1228         ar7_gpio_disable(27);
1229         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1230         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1231         ar7_device_reset(AR7_RESET_BIT_EPHY);
1232
1233         cpmac_mii.reset(&cpmac_mii);
1234
1235         for (i = 0; i < 300000; i++)
1236                 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1237                         break;
1238                 else
1239                         cpu_relax();
1240
1241         mask &= 0x7fffffff;
1242         if (mask & (mask - 1)) {
1243                 external_switch = 1;
1244                 mask = 0;
1245         }
1246
1247         cpmac_mii.phy_mask = ~(mask | 0x80000000);
1248         snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
1249
1250         res = mdiobus_register(&cpmac_mii);
1251         if (res)
1252                 goto fail_mii;
1253
1254         res = platform_driver_register(&cpmac_driver);
1255         if (res)
1256                 goto fail_cpmac;
1257
1258         return 0;
1259
1260 fail_cpmac:
1261         mdiobus_unregister(&cpmac_mii);
1262
1263 fail_mii:
1264         iounmap(cpmac_mii.priv);
1265
1266         return res;
1267 }
1268
1269 void __devexit cpmac_exit(void)
1270 {
1271         platform_driver_unregister(&cpmac_driver);
1272         mdiobus_unregister(&cpmac_mii);
1273         iounmap(cpmac_mii.priv);
1274 }
1275
1276 module_init(cpmac_init);
1277 module_exit(cpmac_exit);