drivers/net/chelsio/tp.c

   1 /* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
   2 #include "common.h"
   3 #include "regs.h"
   4 #include "tp.h"
   5 #ifdef CONFIG_CHELSIO_T1_1G
   6 #include "fpga_defs.h"
   7 #endif
   8
   9 struct petp {
  10         adapter_t *adapter;
  11 };
  12
  13 /* Pause deadlock avoidance parameters */
  14 #define DROP_MSEC 16
  15 #define DROP_PKTS_CNT  1
  16
  17 static void tp_init(adapter_t * ap, const struct tp_params *p,
  18                     unsigned int tp_clk)
  19 {
  20         if (t1_is_asic(ap)) {
  21                 u32 val;
  22
  23                 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
  24                     F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
  25                 if (!p->pm_size)
  26                         val |= F_OFFLOAD_DISABLE;
  27                 else
  28                         val |= F_TP_IN_ESPI_CHECK_IP_CSUM |
  29                             F_TP_IN_ESPI_CHECK_TCP_CSUM;
  30                 writel(val, ap->regs + A_TP_IN_CONFIG);
  31                 writel(F_TP_OUT_CSPI_CPL |
  32                        F_TP_OUT_ESPI_ETHERNET |
  33                        F_TP_OUT_ESPI_GENERATE_IP_CSUM |
  34                        F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
  35                        ap->regs + A_TP_OUT_CONFIG);
  36                 writel(V_IP_TTL(64) |
  37                        F_PATH_MTU /* IP DF bit */  |
  38                        V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
  39                        V_SYN_COOKIE_PARAMETER(29),
  40                        ap->regs + A_TP_GLOBAL_CONFIG);
  41                 /*
  42                  * Enable pause frame deadlock prevention.
  43                  */
  44                 if (is_T2(ap) && ap->params.nports > 1) {
  45                         u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
  46
  47                         writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
  48                                V_DROP_TICKS_CNT(drop_ticks) |
  49                                V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
  50                                ap->regs + A_TP_TX_DROP_CONFIG);
  51                 }
  52
  53         }
  54 }
  55
  56 void t1_tp_destroy(struct petp *tp)
  57 {
  58         kfree(tp);
  59 }
  60
  61 struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p)
  62 {
  63         struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
  64         if (!tp)
  65                 return NULL;
  66
  67         tp->adapter = adapter;
  68
  69         return tp;
  70 }
  71
  72 void t1_tp_intr_enable(struct petp *tp)
  73 {
  74         u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
  75
  76 #ifdef CONFIG_CHELSIO_T1_1G
  77         if (!t1_is_asic(tp->adapter)) {
  78                 /* FPGA */
  79                 writel(0xffffffff,
  80                        tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
  81                 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
  82                        tp->adapter->regs + A_PL_ENABLE);
  83         } else
  84 #endif
  85         {
  86                 /* We don't use any TP interrupts */
  87                 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
  88                 writel(tp_intr | F_PL_INTR_TP,
  89                        tp->adapter->regs + A_PL_ENABLE);
  90         }
  91 }
  92
  93 void t1_tp_intr_disable(struct petp *tp)
  94 {
  95         u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
  96
  97 #ifdef CONFIG_CHELSIO_T1_1G
  98         if (!t1_is_asic(tp->adapter)) {
  99                 /* FPGA */
 100                 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
 101                 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
 102                        tp->adapter->regs + A_PL_ENABLE);
 103         } else
 104 #endif
 105         {
 106                 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
 107                 writel(tp_intr & ~F_PL_INTR_TP,
 108                        tp->adapter->regs + A_PL_ENABLE);
 109         }
 110 }
 111
 112 void t1_tp_intr_clear(struct petp *tp)
 113 {
 114 #ifdef CONFIG_CHELSIO_T1_1G
 115         if (!t1_is_asic(tp->adapter)) {
 116                 writel(0xffffffff,
 117                        tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
 118                 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
 119                 return;
 120         }
 121 #endif
 122         writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
 123         writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
 124 }
 125
 126 int t1_tp_intr_handler(struct petp *tp)
 127 {
 128         u32 cause;
 129
 130 #ifdef CONFIG_CHELSIO_T1_1G
 131         /* FPGA doesn't support TP interrupts. */
 132         if (!t1_is_asic(tp->adapter))
 133                 return 1;
 134 #endif
 135
 136         cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
 137         writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
 138         return 0;
 139 }
 140
 141 static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
 142 {
 143         u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
 144
 145         if (enable)
 146                 val |= csum_bit;
 147         else
 148                 val &= ~csum_bit;
 149         writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
 150 }
 151
 152 void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
 153 {
 154         set_csum_offload(tp, F_IP_CSUM, enable);
 155 }
 156
 157 void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable)
 158 {
 159         set_csum_offload(tp, F_UDP_CSUM, enable);
 160 }
 161
 162 void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
 163 {
 164         set_csum_offload(tp, F_TCP_CSUM, enable);
 165 }
 166
 167 /*
 168  * Initialize TP state.  tp_params contains initial settings for some TP
 169  * parameters, particularly the one-time PM and CM settings.
 170  */
 171 int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
 172 {
 173         adapter_t *adapter = tp->adapter;
 174
 175         tp_init(adapter, p, tp_clk);
 176         writel(F_TP_RESET, adapter->regs +  A_TP_RESET);
 177         return 0;
 178 }