2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
14 * Your platform definition file should specify something like:
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
20 * at91_add_device_can(&ek_can_data);
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
41 #include <mach/board.h>
43 #define AT91_NAPI_WEIGHT 12
49 #define AT91_MB_RX_NUM 12
50 #define AT91_MB_TX_SHIFT 2
52 #define AT91_MB_RX_FIRST 0
53 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
55 #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
56 #define AT91_MB_RX_SPLIT 8
57 #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
58 #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
59 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
61 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
62 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
63 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
65 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
66 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
67 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
68 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
70 /* Common registers */
85 /* Mailbox registers (0 <= i <= 15) */
86 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
87 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
88 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
89 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
90 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
91 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
92 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
93 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
96 #define AT91_MR_CANEN BIT(0)
97 #define AT91_MR_LPM BIT(1)
98 #define AT91_MR_ABM BIT(2)
99 #define AT91_MR_OVL BIT(3)
100 #define AT91_MR_TEOF BIT(4)
101 #define AT91_MR_TTM BIT(5)
102 #define AT91_MR_TIMFRZ BIT(6)
103 #define AT91_MR_DRPT BIT(7)
105 #define AT91_SR_RBSY BIT(29)
107 #define AT91_MMR_PRIO_SHIFT (16)
109 #define AT91_MID_MIDE BIT(29)
111 #define AT91_MSR_MRTR BIT(20)
112 #define AT91_MSR_MABT BIT(22)
113 #define AT91_MSR_MRDY BIT(23)
114 #define AT91_MSR_MMI BIT(24)
116 #define AT91_MCR_MRTR BIT(20)
117 #define AT91_MCR_MTCR BIT(23)
121 AT91_MB_MODE_DISABLED = 0,
123 AT91_MB_MODE_RX_OVRWR = 2,
125 AT91_MB_MODE_CONSUMER = 4,
126 AT91_MB_MODE_PRODUCER = 5,
129 /* Interrupt mask bits */
130 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
131 - (1 << AT91_MB_RX_FIRST))
132 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
133 - (1 << AT91_MB_TX_FIRST))
134 #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
136 #define AT91_IRQ_ERRA (1 << 16)
137 #define AT91_IRQ_WARN (1 << 17)
138 #define AT91_IRQ_ERRP (1 << 18)
139 #define AT91_IRQ_BOFF (1 << 19)
140 #define AT91_IRQ_SLEEP (1 << 20)
141 #define AT91_IRQ_WAKEUP (1 << 21)
142 #define AT91_IRQ_TOVF (1 << 22)
143 #define AT91_IRQ_TSTP (1 << 23)
144 #define AT91_IRQ_CERR (1 << 24)
145 #define AT91_IRQ_SERR (1 << 25)
146 #define AT91_IRQ_AERR (1 << 26)
147 #define AT91_IRQ_FERR (1 << 27)
148 #define AT91_IRQ_BERR (1 << 28)
150 #define AT91_IRQ_ERR_ALL (0x1fff0000)
151 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
153 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
154 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
156 #define AT91_IRQ_ALL (0x1fffffff)
159 struct can_priv can; /* must be the first member! */
160 struct net_device *dev;
161 struct napi_struct napi;
163 void __iomem *reg_base;
166 unsigned int tx_next;
167 unsigned int tx_echo;
168 unsigned int rx_next;
171 struct at91_can_data *pdata;
174 static struct can_bittiming_const at91_bittiming_const = {
175 .name = KBUILD_MODNAME,
186 static inline int get_tx_next_mb(const struct at91_priv *priv)
188 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
191 static inline int get_tx_next_prio(const struct at91_priv *priv)
193 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
196 static inline int get_tx_echo_mb(const struct at91_priv *priv)
198 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
201 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
203 return __raw_readl(priv->reg_base + reg);
206 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
209 __raw_writel(value, priv->reg_base + reg);
212 static inline void set_mb_mode_prio(const struct at91_priv *priv,
213 unsigned int mb, enum at91_mb_mode mode, int prio)
215 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
218 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
219 enum at91_mb_mode mode)
221 set_mb_mode_prio(priv, mb, mode, 0);
225 * Swtich transceiver on or off
227 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
229 if (priv->pdata && priv->pdata->transceiver_switch)
230 priv->pdata->transceiver_switch(on);
233 static void at91_setup_mailboxes(struct net_device *dev)
235 struct at91_priv *priv = netdev_priv(dev);
239 * The first 12 mailboxes are used as a reception FIFO. The
240 * last mailbox is configured with overwrite option. The
241 * overwrite flag indicates a FIFO overflow.
243 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
244 set_mb_mode(priv, i, AT91_MB_MODE_RX);
245 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
247 /* reset acceptance mask and id register */
248 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) {
249 at91_write(priv, AT91_MAM(i), 0x0 );
250 at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
253 /* The last 4 mailboxes are used for transmitting. */
254 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
255 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
257 /* Reset tx and rx helper pointers */
258 priv->tx_next = priv->tx_echo = 0;
259 priv->rx_next = AT91_MB_RX_FIRST;
262 static int at91_set_bittiming(struct net_device *dev)
264 const struct at91_priv *priv = netdev_priv(dev);
265 const struct can_bittiming *bt = &priv->can.bittiming;
268 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
269 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
270 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
271 ((bt->phase_seg2 - 1) << 0);
273 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
275 at91_write(priv, AT91_BR, reg_br);
280 static int at91_get_berr_counter(const struct net_device *dev,
281 struct can_berr_counter *bec)
283 const struct at91_priv *priv = netdev_priv(dev);
284 u32 reg_ecr = at91_read(priv, AT91_ECR);
286 bec->rxerr = reg_ecr & 0xff;
287 bec->txerr = reg_ecr >> 16;
292 static void at91_chip_start(struct net_device *dev)
294 struct at91_priv *priv = netdev_priv(dev);
297 /* disable interrupts */
298 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
301 reg_mr = at91_read(priv, AT91_MR);
302 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
304 at91_set_bittiming(dev);
305 at91_setup_mailboxes(dev);
306 at91_transceiver_switch(priv, 1);
309 at91_write(priv, AT91_MR, AT91_MR_CANEN);
311 priv->can.state = CAN_STATE_ERROR_ACTIVE;
313 /* Enable interrupts */
314 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
315 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
316 at91_write(priv, AT91_IER, reg_ier);
319 static void at91_chip_stop(struct net_device *dev, enum can_state state)
321 struct at91_priv *priv = netdev_priv(dev);
324 /* disable interrupts */
325 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
327 reg_mr = at91_read(priv, AT91_MR);
328 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
330 at91_transceiver_switch(priv, 0);
331 priv->can.state = state;
335 * theory of operation:
337 * According to the datasheet priority 0 is the highest priority, 15
338 * is the lowest. If two mailboxes have the same priority level the
339 * message of the mailbox with the lowest number is sent first.
341 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
342 * the next mailbox with prio 0, and so on, until all mailboxes are
343 * used. Then we start from the beginning with mailbox
344 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
345 * prio 1. When we reach the last mailbox with prio 15, we have to
346 * stop sending, waiting for all messages to be delivered, then start
347 * again with mailbox AT91_MB_TX_FIRST prio 0.
349 * We use the priv->tx_next as counter for the next transmission
350 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
351 * encode the mailbox number, the upper 4 bits the mailbox priority:
353 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
354 * (mb - AT91_MB_TX_FIRST);
357 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
359 struct at91_priv *priv = netdev_priv(dev);
360 struct net_device_stats *stats = &dev->stats;
361 struct can_frame *cf = (struct can_frame *)skb->data;
362 unsigned int mb, prio;
363 u32 reg_mid, reg_mcr;
365 if (can_dropped_invalid_skb(dev, skb))
368 mb = get_tx_next_mb(priv);
369 prio = get_tx_next_prio(priv);
371 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
372 netif_stop_queue(dev);
374 netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
375 return NETDEV_TX_BUSY;
378 if (cf->can_id & CAN_EFF_FLAG)
379 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
381 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
383 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
384 (cf->can_dlc << 16) | AT91_MCR_MTCR;
386 /* disable MB while writing ID (see datasheet) */
387 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
388 at91_write(priv, AT91_MID(mb), reg_mid);
389 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
391 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
392 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
394 /* This triggers transmission */
395 at91_write(priv, AT91_MCR(mb), reg_mcr);
397 stats->tx_bytes += cf->can_dlc;
399 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
400 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
403 * we have to stop the queue and deliver all messages in case
404 * of a prio+mb counter wrap around. This is the case if
405 * tx_next buffer prio and mailbox equals 0.
407 * also stop the queue if next buffer is still in use
411 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
413 (priv->tx_next & AT91_NEXT_MASK) == 0)
414 netif_stop_queue(dev);
416 /* Enable interrupt for this mailbox */
417 at91_write(priv, AT91_IER, 1 << mb);
423 * at91_activate_rx_low - activate lower rx mailboxes
426 * Reenables the lower mailboxes for reception of new CAN messages
428 static inline void at91_activate_rx_low(const struct at91_priv *priv)
430 u32 mask = AT91_MB_RX_LOW_MASK;
431 at91_write(priv, AT91_TCR, mask);
435 * at91_activate_rx_mb - reactive single rx mailbox
437 * @mb: mailbox to reactivate
439 * Reenables given mailbox for reception of new CAN messages
441 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
445 at91_write(priv, AT91_TCR, mask);
449 * at91_rx_overflow_err - send error frame due to rx overflow
452 static void at91_rx_overflow_err(struct net_device *dev)
454 struct net_device_stats *stats = &dev->stats;
456 struct can_frame *cf;
458 netdev_dbg(dev, "RX buffer overflow\n");
459 stats->rx_over_errors++;
462 skb = alloc_can_err_skb(dev, &cf);
466 cf->can_id |= CAN_ERR_CRTL;
467 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
468 netif_receive_skb(skb);
471 stats->rx_bytes += cf->can_dlc;
475 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
477 * @mb: mailbox number to read from
478 * @cf: can frame where to store message
480 * Reads a CAN message from the given mailbox and stores data into
481 * given can frame. "mb" and "cf" must be valid.
483 static void at91_read_mb(struct net_device *dev, unsigned int mb,
484 struct can_frame *cf)
486 const struct at91_priv *priv = netdev_priv(dev);
487 u32 reg_msr, reg_mid;
489 reg_mid = at91_read(priv, AT91_MID(mb));
490 if (reg_mid & AT91_MID_MIDE)
491 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
493 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
495 reg_msr = at91_read(priv, AT91_MSR(mb));
496 if (reg_msr & AT91_MSR_MRTR)
497 cf->can_id |= CAN_RTR_FLAG;
498 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
500 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
501 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
503 /* allow RX of extended frames */
504 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
506 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
507 at91_rx_overflow_err(dev);
511 * at91_read_msg - read CAN message from mailbox
513 * @mb: mail box to read from
515 * Reads a CAN message from given mailbox, and put into linux network
516 * RX queue, does all housekeeping chores (stats, ...)
518 static void at91_read_msg(struct net_device *dev, unsigned int mb)
520 struct net_device_stats *stats = &dev->stats;
521 struct can_frame *cf;
524 skb = alloc_can_skb(dev, &cf);
525 if (unlikely(!skb)) {
530 at91_read_mb(dev, mb, cf);
531 netif_receive_skb(skb);
534 stats->rx_bytes += cf->can_dlc;
538 * at91_poll_rx - read multiple CAN messages from mailboxes
540 * @quota: max number of pkgs we're allowed to receive
542 * Theory of Operation:
544 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
545 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
547 * Like it or not, but the chip always saves a received CAN message
548 * into the first free mailbox it finds (starting with the
549 * lowest). This makes it very difficult to read the messages in the
550 * right order from the chip. This is how we work around that problem:
552 * The first message goes into mb nr. 0 and issues an interrupt. All
553 * rx ints are disabled in the interrupt handler and a napi poll is
554 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
555 * receive another message).
558 * ______^______ __^__
560 * +-+-+-+-+-+-+-+-++-+-+-+-+
561 * |x|x|x|x|x|x|x|x|| | | | |
562 * +-+-+-+-+-+-+-+-++-+-+-+-+
563 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
564 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
566 * The variable priv->rx_next points to the next mailbox to read a
567 * message from. As long we're in the lower mailboxes we just read the
568 * mailbox but not reenable it.
570 * With completion of the last of the lower mailboxes, we reenable the
571 * whole first group, but continue to look for filled mailboxes in the
572 * upper mailboxes. Imagine the second group like overflow mailboxes,
573 * which takes CAN messages if the lower goup is full. While in the
574 * upper group we reenable the mailbox right after reading it. Giving
575 * the chip more room to store messages.
577 * After finishing we look again in the lower group if we've still
581 static int at91_poll_rx(struct net_device *dev, int quota)
583 struct at91_priv *priv = netdev_priv(dev);
584 u32 reg_sr = at91_read(priv, AT91_SR);
585 const unsigned long *addr = (unsigned long *)®_sr;
589 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
590 reg_sr & AT91_MB_RX_LOW_MASK)
592 "order of incoming frames cannot be guaranteed\n");
595 for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next);
596 mb < AT91_MB_RX_LAST + 1 && quota > 0;
597 reg_sr = at91_read(priv, AT91_SR),
598 mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) {
599 at91_read_msg(dev, mb);
601 /* reactivate mailboxes */
602 if (mb == AT91_MB_RX_LOW_LAST)
603 /* all lower mailboxed, if just finished it */
604 at91_activate_rx_low(priv);
605 else if (mb > AT91_MB_RX_LOW_LAST)
606 /* only the mailbox we read */
607 at91_activate_rx_mb(priv, mb);
613 /* upper group completed, look again in lower */
614 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
615 quota > 0 && mb > AT91_MB_RX_LAST) {
616 priv->rx_next = AT91_MB_RX_FIRST;
623 static void at91_poll_err_frame(struct net_device *dev,
624 struct can_frame *cf, u32 reg_sr)
626 struct at91_priv *priv = netdev_priv(dev);
629 if (reg_sr & AT91_IRQ_CERR) {
630 netdev_dbg(dev, "CERR irq\n");
631 dev->stats.rx_errors++;
632 priv->can.can_stats.bus_error++;
633 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
637 if (reg_sr & AT91_IRQ_SERR) {
638 netdev_dbg(dev, "SERR irq\n");
639 dev->stats.rx_errors++;
640 priv->can.can_stats.bus_error++;
641 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
642 cf->data[2] |= CAN_ERR_PROT_STUFF;
645 /* Acknowledgement Error */
646 if (reg_sr & AT91_IRQ_AERR) {
647 netdev_dbg(dev, "AERR irq\n");
648 dev->stats.tx_errors++;
649 cf->can_id |= CAN_ERR_ACK;
653 if (reg_sr & AT91_IRQ_FERR) {
654 netdev_dbg(dev, "FERR irq\n");
655 dev->stats.rx_errors++;
656 priv->can.can_stats.bus_error++;
657 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
658 cf->data[2] |= CAN_ERR_PROT_FORM;
662 if (reg_sr & AT91_IRQ_BERR) {
663 netdev_dbg(dev, "BERR irq\n");
664 dev->stats.tx_errors++;
665 priv->can.can_stats.bus_error++;
666 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
667 cf->data[2] |= CAN_ERR_PROT_BIT;
671 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
674 struct can_frame *cf;
679 skb = alloc_can_err_skb(dev, &cf);
683 at91_poll_err_frame(dev, cf, reg_sr);
684 netif_receive_skb(skb);
686 dev->stats.rx_packets++;
687 dev->stats.rx_bytes += cf->can_dlc;
692 static int at91_poll(struct napi_struct *napi, int quota)
694 struct net_device *dev = napi->dev;
695 const struct at91_priv *priv = netdev_priv(dev);
696 u32 reg_sr = at91_read(priv, AT91_SR);
699 if (reg_sr & AT91_IRQ_MB_RX)
700 work_done += at91_poll_rx(dev, quota - work_done);
703 * The error bits are clear on read,
704 * so use saved value from irq handler.
706 reg_sr |= priv->reg_sr;
707 if (reg_sr & AT91_IRQ_ERR_FRAME)
708 work_done += at91_poll_err(dev, quota - work_done, reg_sr);
710 if (work_done < quota) {
711 /* enable IRQs for frame errors and all mailboxes >= rx_next */
712 u32 reg_ier = AT91_IRQ_ERR_FRAME;
713 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
716 at91_write(priv, AT91_IER, reg_ier);
723 * theory of operation:
725 * priv->tx_echo holds the number of the oldest can_frame put for
726 * transmission into the hardware, but not yet ACKed by the CAN tx
729 * We iterate from priv->tx_echo to priv->tx_next and check if the
730 * packet has been transmitted, echo it back to the CAN framework. If
731 * we discover a not yet transmitted package, stop looking for more.
734 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
736 struct at91_priv *priv = netdev_priv(dev);
740 /* masking of reg_sr not needed, already done by at91_irq */
742 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
743 mb = get_tx_echo_mb(priv);
745 /* no event in mailbox? */
746 if (!(reg_sr & (1 << mb)))
749 /* Disable irq for this TX mailbox */
750 at91_write(priv, AT91_IDR, 1 << mb);
753 * only echo if mailbox signals us a transfer
754 * complete (MSR_MRDY). Otherwise it's a tansfer
755 * abort. "can_bus_off()" takes care about the skbs
756 * parked in the echo queue.
758 reg_msr = at91_read(priv, AT91_MSR(mb));
759 if (likely(reg_msr & AT91_MSR_MRDY &&
760 ~reg_msr & AT91_MSR_MABT)) {
761 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
762 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
763 dev->stats.tx_packets++;
768 * restart queue if we don't have a wrap around but restart if
769 * we get a TX int for the last can frame directly before a
772 if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
773 (priv->tx_echo & AT91_NEXT_MASK) == 0)
774 netif_wake_queue(dev);
777 static void at91_irq_err_state(struct net_device *dev,
778 struct can_frame *cf, enum can_state new_state)
780 struct at91_priv *priv = netdev_priv(dev);
781 u32 reg_idr = 0, reg_ier = 0;
782 struct can_berr_counter bec;
784 at91_get_berr_counter(dev, &bec);
786 switch (priv->can.state) {
787 case CAN_STATE_ERROR_ACTIVE:
790 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
791 * => : there was a warning int
793 if (new_state >= CAN_STATE_ERROR_WARNING &&
794 new_state <= CAN_STATE_BUS_OFF) {
795 netdev_dbg(dev, "Error Warning IRQ\n");
796 priv->can.can_stats.error_warning++;
798 cf->can_id |= CAN_ERR_CRTL;
799 cf->data[1] = (bec.txerr > bec.rxerr) ?
800 CAN_ERR_CRTL_TX_WARNING :
801 CAN_ERR_CRTL_RX_WARNING;
803 case CAN_STATE_ERROR_WARNING: /* fallthrough */
805 * from: ERROR_ACTIVE, ERROR_WARNING
806 * to : ERROR_PASSIVE, BUS_OFF
807 * => : error passive int
809 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
810 new_state <= CAN_STATE_BUS_OFF) {
811 netdev_dbg(dev, "Error Passive IRQ\n");
812 priv->can.can_stats.error_passive++;
814 cf->can_id |= CAN_ERR_CRTL;
815 cf->data[1] = (bec.txerr > bec.rxerr) ?
816 CAN_ERR_CRTL_TX_PASSIVE :
817 CAN_ERR_CRTL_RX_PASSIVE;
820 case CAN_STATE_BUS_OFF:
823 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
825 if (new_state <= CAN_STATE_ERROR_PASSIVE) {
826 cf->can_id |= CAN_ERR_RESTARTED;
828 netdev_dbg(dev, "restarted\n");
829 priv->can.can_stats.restarts++;
831 netif_carrier_on(dev);
832 netif_wake_queue(dev);
840 /* process state changes depending on the new state */
842 case CAN_STATE_ERROR_ACTIVE:
844 * actually we want to enable AT91_IRQ_WARN here, but
845 * it screws up the system under certain
846 * circumstances. so just enable AT91_IRQ_ERRP, thus
849 netdev_dbg(dev, "Error Active\n");
850 cf->can_id |= CAN_ERR_PROT;
851 cf->data[2] = CAN_ERR_PROT_ACTIVE;
852 case CAN_STATE_ERROR_WARNING: /* fallthrough */
853 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
854 reg_ier = AT91_IRQ_ERRP;
856 case CAN_STATE_ERROR_PASSIVE:
857 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
858 reg_ier = AT91_IRQ_BOFF;
860 case CAN_STATE_BUS_OFF:
861 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
862 AT91_IRQ_WARN | AT91_IRQ_BOFF;
865 cf->can_id |= CAN_ERR_BUSOFF;
867 netdev_dbg(dev, "bus-off\n");
868 netif_carrier_off(dev);
869 priv->can.can_stats.bus_off++;
871 /* turn off chip, if restart is disabled */
872 if (!priv->can.restart_ms) {
873 at91_chip_stop(dev, CAN_STATE_BUS_OFF);
881 at91_write(priv, AT91_IDR, reg_idr);
882 at91_write(priv, AT91_IER, reg_ier);
885 static void at91_irq_err(struct net_device *dev)
887 struct at91_priv *priv = netdev_priv(dev);
889 struct can_frame *cf;
890 enum can_state new_state;
893 reg_sr = at91_read(priv, AT91_SR);
895 /* we need to look at the unmasked reg_sr */
896 if (unlikely(reg_sr & AT91_IRQ_BOFF))
897 new_state = CAN_STATE_BUS_OFF;
898 else if (unlikely(reg_sr & AT91_IRQ_ERRP))
899 new_state = CAN_STATE_ERROR_PASSIVE;
900 else if (unlikely(reg_sr & AT91_IRQ_WARN))
901 new_state = CAN_STATE_ERROR_WARNING;
902 else if (likely(reg_sr & AT91_IRQ_ERRA))
903 new_state = CAN_STATE_ERROR_ACTIVE;
905 netdev_err(dev, "BUG! hardware in undefined state\n");
909 /* state hasn't changed */
910 if (likely(new_state == priv->can.state))
913 skb = alloc_can_err_skb(dev, &cf);
917 at91_irq_err_state(dev, cf, new_state);
920 dev->stats.rx_packets++;
921 dev->stats.rx_bytes += cf->can_dlc;
923 priv->can.state = new_state;
929 static irqreturn_t at91_irq(int irq, void *dev_id)
931 struct net_device *dev = dev_id;
932 struct at91_priv *priv = netdev_priv(dev);
933 irqreturn_t handled = IRQ_NONE;
936 reg_sr = at91_read(priv, AT91_SR);
937 reg_imr = at91_read(priv, AT91_IMR);
939 /* Ignore masked interrupts */
944 handled = IRQ_HANDLED;
946 /* Receive or error interrupt? -> napi */
947 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
949 * The error bits are clear on read,
950 * save for later use.
952 priv->reg_sr = reg_sr;
953 at91_write(priv, AT91_IDR,
954 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
955 napi_schedule(&priv->napi);
958 /* Transmission complete interrupt */
959 if (reg_sr & AT91_IRQ_MB_TX)
960 at91_irq_tx(dev, reg_sr);
968 static int at91_open(struct net_device *dev)
970 struct at91_priv *priv = netdev_priv(dev);
973 clk_enable(priv->clk);
975 /* check or determine and set bittime */
976 err = open_candev(dev);
980 /* register interrupt handler */
981 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
987 /* start chip and queuing */
988 at91_chip_start(dev);
989 napi_enable(&priv->napi);
990 netif_start_queue(dev);
997 clk_disable(priv->clk);
1003 * stop CAN bus activity
1005 static int at91_close(struct net_device *dev)
1007 struct at91_priv *priv = netdev_priv(dev);
1009 netif_stop_queue(dev);
1010 napi_disable(&priv->napi);
1011 at91_chip_stop(dev, CAN_STATE_STOPPED);
1013 free_irq(dev->irq, dev);
1014 clk_disable(priv->clk);
1021 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1024 case CAN_MODE_START:
1025 at91_chip_start(dev);
1026 netif_wake_queue(dev);
1036 static const struct net_device_ops at91_netdev_ops = {
1037 .ndo_open = at91_open,
1038 .ndo_stop = at91_close,
1039 .ndo_start_xmit = at91_start_xmit,
1042 static int __devinit at91_can_probe(struct platform_device *pdev)
1044 struct net_device *dev;
1045 struct at91_priv *priv;
1046 struct resource *res;
1051 clk = clk_get(&pdev->dev, "can_clk");
1053 dev_err(&pdev->dev, "no clock defined\n");
1058 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1059 irq = platform_get_irq(pdev, 0);
1060 if (!res || irq <= 0) {
1065 if (!request_mem_region(res->start,
1072 addr = ioremap_nocache(res->start, resource_size(res));
1078 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
1084 dev->netdev_ops = &at91_netdev_ops;
1086 dev->flags |= IFF_ECHO;
1088 priv = netdev_priv(dev);
1089 priv->can.clock.freq = clk_get_rate(clk);
1090 priv->can.bittiming_const = &at91_bittiming_const;
1091 priv->can.do_set_mode = at91_set_mode;
1092 priv->can.do_get_berr_counter = at91_get_berr_counter;
1093 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
1094 priv->reg_base = addr;
1097 priv->pdata = pdev->dev.platform_data;
1099 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
1101 dev_set_drvdata(&pdev->dev, dev);
1102 SET_NETDEV_DEV(dev, &pdev->dev);
1104 err = register_candev(dev);
1106 dev_err(&pdev->dev, "registering netdev failed\n");
1110 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1111 priv->reg_base, dev->irq);
1120 release_mem_region(res->start, resource_size(res));
1127 static int __devexit at91_can_remove(struct platform_device *pdev)
1129 struct net_device *dev = platform_get_drvdata(pdev);
1130 struct at91_priv *priv = netdev_priv(dev);
1131 struct resource *res;
1133 unregister_netdev(dev);
1135 platform_set_drvdata(pdev, NULL);
1137 iounmap(priv->reg_base);
1139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1140 release_mem_region(res->start, resource_size(res));
1149 static struct platform_driver at91_can_driver = {
1150 .probe = at91_can_probe,
1151 .remove = __devexit_p(at91_can_remove),
1153 .name = KBUILD_MODNAME,
1154 .owner = THIS_MODULE,
1158 static int __init at91_can_module_init(void)
1160 return platform_driver_register(&at91_can_driver);
1163 static void __exit at91_can_module_exit(void)
1165 platform_driver_unregister(&at91_can_driver);
1168 module_init(at91_can_module_init);
1169 module_exit(at91_can_module_exit);
1171 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1172 MODULE_LICENSE("GPL v2");
1173 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");